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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20 struct ao_i2c_stm_info {
  21         uint8_t tx_dma_index;
  22         uint8_t rx_dma_index;
  23         struct stm_i2c  *stm_i2c;
  24 };
  25
  26 #define I2C_TIMEOUT     100
  27
  28 #define I2C_IDLE        0
  29 #define I2C_RUNNING     1
  30 #define I2C_ERROR       2
  31
  32 static uint8_t  ao_i2c_state[STM_NUM_I2C];
  33 static uint16_t ao_i2c_addr[STM_NUM_I2C];
  34 uint8_t         ao_i2c_mutex[STM_NUM_I2C];
  35
  36 #if AO_PCLK1 == 2000000
  37 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_2_MHZ
  38 #endif
  39 #if AO_PCLK1 == 4000000
  40 #  define AO_STM_I2C_CR2_FREQ   STM_I2C_CR2_FREQ_4_MHZ
  41 #endif
  42 #if AO_PCLK1 == 8000000
  43 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_8_MHZ
  44 #endif
  45 #if AO_PCLK1 == 16000000
  46 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_16_MHZ
  47 #endif
  48 #if AO_PCLK1 == 32000000
  49 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_32_MHZ
  50 #endif
  51
  52 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) |      \
  53                         (0 << STM_I2C_CR1_ALERT) |      \
  54                         (0 << STM_I2C_CR1_PEC) |        \
  55                         (0 << STM_I2C_CR1_POS) |        \
  56                         (0 << STM_I2C_CR1_ACK) |        \
  57                         (0 << STM_I2C_CR1_STOP) |       \
  58                         (0 << STM_I2C_CR1_START) |      \
  59                         (0 << STM_I2C_CR1_NOSTRETCH) |  \
  60                         (0 << STM_I2C_CR1_ENGC) |       \
  61                         (0 << STM_I2C_CR1_ENPEC) |      \
  62                         (0 << STM_I2C_CR1_ENARP) |      \
  63                         (0 << STM_I2C_CR1_SMBTYPE) |    \
  64                         (0 << STM_I2C_CR1_SMBUS) |      \
  65                         (1 << STM_I2C_CR1_PE))
  66
  67 #define AO_STM_I2C_CR2  ((0 << STM_I2C_CR2_LAST) |                      \
  68                          (0 << STM_I2C_CR2_DMAEN) |                     \
  69                          (0 << STM_I2C_CR2_ITBUFEN) |                   \
  70                          (0 << STM_I2C_CR2_ITEVTEN) |                   \
  71                          (0 << STM_I2C_CR2_ITERREN) |                   \
  72                          (AO_STM_I2C_CR2_FREQ << STM_I2C_CR2_FREQ))
  73
  74 static const struct ao_i2c_stm_info     ao_i2c_stm_info[STM_NUM_I2C] = {
  75         {
  76                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
  77                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
  78                 .stm_i2c = &stm_i2c1
  79         },
  80         {
  81                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
  82                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
  83                 .stm_i2c = &stm_i2c2
  84         },
  85 };
  86
  87 static uint8_t  *ao_i2c_recv_data[STM_NUM_I2C];
  88 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
  89 static uint16_t ev_count;
  90
  91 static void
  92 ao_i2c_ev_isr(uint8_t index)
  93 {
  94         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
  95         uint32_t        sr1;
  96
  97         ++ev_count;
  98         sr1 = stm_i2c->sr1;
  99         if (sr1 & (1 << STM_I2C_SR1_SB))
 100                 stm_i2c->dr = ao_i2c_addr[index];
 101         if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
 102                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
 103                 ao_i2c_state[index] = I2C_RUNNING;
 104                 ao_wakeup(&ao_i2c_state[index]);
 105         }
 106         if (sr1 & (1 << STM_I2C_SR1_BTF)) {
 107                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
 108                 ao_wakeup(&ao_i2c_state[index]);
 109         }
 110         if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
 111                 if (ao_i2c_recv_len[index]) {
 112                         *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
 113                         if (!--ao_i2c_recv_len[index])
 114                                 ao_wakeup(&ao_i2c_recv_len[index]);
 115                 }
 116         }
 117 }
 118
 119 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
 120 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
 121
 122 static void
 123 ao_i2c_er_isr(uint8_t index)
 124 {
 125         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 126         uint32_t        sr1;
 127
 128         sr1 = stm_i2c->sr1;
 129         if (sr1 & (1 << STM_I2C_SR1_AF)) {
 130                 ao_i2c_state[index] = I2C_ERROR;
 131                 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
 132                 ao_wakeup(&ao_i2c_state[index]);
 133         }
 134 }
 135
 136 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
 137 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
 138
 139 void
 140 ao_i2c_get(uint8_t index)
 141 {
 142         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 143         ao_mutex_get(&ao_i2c_mutex[index]);
 144
 145         stm_i2c->sr1 = 0;
 146         stm_i2c->sr2 = 0;
 147 }
 148
 149 void
 150 ao_i2c_put(uint8_t index)
 151 {
 152         ao_mutex_put(&ao_i2c_mutex[index]);
 153 }
 154
 155 uint8_t
 156 ao_i2c_start(uint8_t index, uint16_t addr)
 157 {
 158         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 159         uint32_t        sr1, sr2;
 160         int             t;
 161
 162         ao_i2c_state[index] = I2C_IDLE;
 163         ao_i2c_addr[index] = addr;
 164         stm_i2c->cr2 = AO_STM_I2C_CR2;
 165         stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START);
 166         for (t = 0; t < I2C_TIMEOUT; t++) {
 167                 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_START)))
 168                         break;
 169         }
 170         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
 171         ao_alarm(AO_MS_TO_TICKS(250));
 172         cli();
 173         while (ao_i2c_state[index] == I2C_IDLE)
 174                 if (ao_sleep(&ao_i2c_state[index]))
 175                         break;
 176         sei();
 177         ao_clear_alarm();
 178         return ao_i2c_state[index] == I2C_RUNNING;
 179 }
 180
 181 static void
 182 ao_i2c_wait_stop(uint8_t index)
 183 {
 184         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 185         int     t;
 186
 187         for (t = 0; t < I2C_TIMEOUT; t++) {
 188                 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_STOP)))
 189                         break;
 190                 ao_yield();
 191         }
 192         ao_i2c_state[index] = I2C_IDLE;
 193 }
 194
 195 uint8_t
 196 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
 197 {
 198         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 199         uint8_t         *b = block;
 200         uint32_t        sr1;
 201         uint8_t         tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
 202
 203         /* Clear any pending ADDR bit */
 204         (void) stm_i2c->sr2;
 205         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN);
 206         ao_dma_set_transfer(tx_dma_index,
 207                             &stm_i2c->dr,
 208                             block,
 209                             len,
 210                             (0 << STM_DMA_CCR_MEM2MEM) |
 211                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 212                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 213                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 214                             (1 << STM_DMA_CCR_MINC) |
 215                             (0 << STM_DMA_CCR_PINC) |
 216                             (0 << STM_DMA_CCR_CIRC) |
 217                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 218
 219         ao_dma_start(tx_dma_index);
 220         ao_alarm(1 + len);
 221         cli();
 222         while (!ao_dma_done[tx_dma_index])
 223                 if (ao_sleep(&ao_dma_done[tx_dma_index]))
 224                         break;
 225         ao_clear_alarm();
 226         ao_dma_done_transfer(tx_dma_index);
 227         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
 228         while ((stm_i2c->sr1 & (1 << STM_I2C_SR1_BTF)) == 0)
 229                 if (ao_sleep(&ao_i2c_state[index]))
 230                         break;
 231         stm_i2c->cr2 = AO_STM_I2C_CR2;
 232         sei();
 233         if (stop) {
 234                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 235                 ao_i2c_wait_stop(index);
 236         }
 237         return TRUE;
 238 }
 239
 240 void
 241 ao_i2c_recv_dma_isr(int index)
 242 {
 243         int             i;
 244         struct stm_i2c  *stm_i2c = NULL;
 245
 246         for (i = 0; i < STM_NUM_I2C; i++)
 247                 if (index == ao_i2c_stm_info[i].rx_dma_index) {
 248                         stm_i2c = ao_i2c_stm_info[i].stm_i2c;
 249                         break;
 250                 }
 251         if (!stm_i2c)
 252                 return;
 253         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
 254         ao_dma_done[index] = 1;
 255         ao_wakeup(&ao_dma_done[index]);
 256 }
 257
 258 uint8_t
 259 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
 260 {
 261         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 262         uint8_t         *b = block;
 263         int             t;
 264         uint8_t         ret = TRUE;
 265
 266         if (len == 0)
 267                 return TRUE;
 268         if (len == 1) {
 269                 ao_i2c_recv_data[index] = block;
 270                 ao_i2c_recv_len[index] = 1;
 271                 stm_i2c->cr1 = AO_STM_I2C_CR1;
 272
 273                 /* Clear any pending ADDR bit */
 274                 stm_i2c->sr2;
 275
 276                 /* Enable interrupts to transfer the byte */
 277                 stm_i2c->cr2 = (AO_STM_I2C_CR2 |
 278                                 (1 << STM_I2C_CR2_ITEVTEN) |
 279                                 (1 << STM_I2C_CR2_ITERREN) |
 280                                 (1 << STM_I2C_CR2_ITBUFEN));
 281                 if (stop)
 282                         stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 283
 284                 ao_alarm(1);
 285                 cli();
 286                 while (ao_i2c_recv_len[index])
 287                         if (ao_sleep(&ao_i2c_recv_len[index]))
 288                                 break;
 289                 sei();
 290                 ret = ao_i2c_recv_len[index] == 0;
 291                 ao_clear_alarm();
 292         } else {
 293                 uint8_t         rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
 294                 ao_dma_set_transfer(rx_dma_index,
 295                                     &stm_i2c->dr,
 296                                     block,
 297                                     len,
 298                                     (0 << STM_DMA_CCR_MEM2MEM) |
 299                                     (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 300                                     (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 301                                     (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 302                                     (1 << STM_DMA_CCR_MINC) |
 303                                     (0 << STM_DMA_CCR_PINC) |
 304                                     (0 << STM_DMA_CCR_CIRC) |
 305                                     (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 306                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK);
 307                 stm_i2c->cr2 = AO_STM_I2C_CR2 |
 308                         (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST);
 309                 /* Clear any pending ADDR bit */
 310                 (void) stm_i2c->sr2;
 311
 312                 ao_dma_start(rx_dma_index);
 313                 ao_alarm(len);
 314                 cli();
 315                 while (!ao_dma_done[rx_dma_index])
 316                         if (ao_sleep(&ao_dma_done[rx_dma_index]))
 317                                 break;
 318                 sei();
 319                 ao_clear_alarm();
 320                 ret = ao_dma_done[rx_dma_index];
 321                 ao_dma_done_transfer(rx_dma_index);
 322                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 323         }
 324         if (stop)
 325                 ao_i2c_wait_stop(index);
 326         return ret;
 327 }
 328
 329 void
 330 ao_i2c_channel_init(uint8_t index)
 331 {
 332         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 333         int i;
 334
 335         /* Turn I2C off while configuring */
 336         stm_i2c->cr1 = (1 << STM_I2C_CR1_SWRST);
 337         for (i = 0; i < 100; i++)
 338                 asm("nop");
 339         stm_i2c->cr1 = 0;
 340         stm_i2c->cr2 = AO_STM_I2C_CR2;
 341
 342         (void) stm_i2c->sr1;
 343         (void) stm_i2c->sr2;
 344         (void) stm_i2c->dr;
 345
 346         stm_i2c->sr1 = 0;
 347         stm_i2c->sr2 = 0;
 348
 349         stm_i2c->ccr = ((1 << STM_I2C_CCR_FS) |
 350                         (0 << STM_I2C_CCR_DUTY) |
 351                         (20 << STM_I2C_CCR_CCR));
 352
 353
 354         stm_i2c->cr1 = AO_STM_I2C_CR1;
 355 }
 356
 357 void
 358 ao_i2c_init(void)
 359 {
 360         /* All of the I2C configurations are on port B */
 361         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 362 #if HAS_I2C_1
 363 # if I2C_1_PB6_PB7
 364         stm_afr_set(&stm_gpiob, 6, STM_AFR_AF4);
 365         stm_afr_set(&stm_gpiob, 7, STM_AFR_AF4);
 366 # else
 367 #  if I2C_1_PB8_PB9
 368         stm_afr_set(&stm_gpiob, 8, STM_AFR_AF4);
 369         stm_afr_set(&stm_gpiob, 9, STM_AFR_AF4);
 370 #  else
 371 #   error "No I2C_1 port configuration specified"
 372 #  endif
 373 # endif
 374
 375         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
 376         ao_i2c_channel_init(0);
 377
 378         stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
 379         stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, 3);
 380         stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
 381         stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, 3);
 382 #endif
 383
 384 #if HAS_I2C_2
 385 # if I2C_2_PB10_PB11
 386         stm_afr_set(&stm_gpiob, 10, STM_AFR_AF4);
 387         stm_afr_set(&stm_gpiob, 11, STM_AFR_AF4);
 388 # else
 389 #  error "No I2C_2 port configuration specified"
 390 # endif
 391         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
 392         ao_i2c_channel_init(1);
 393
 394         stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
 395         stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, 3);
 396         stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
 397         stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, 3);
 398 #endif
 399 }