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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include "ao.h"
  19
  20 #define NUM_DMA 7
  21
  22 struct ao_dma_config {
  23         uint32_t        isr;
  24 };
  25
  26 uint8_t ao_dma_done[NUM_DMA];
  27
  28 static struct ao_dma_config ao_dma_config[NUM_DMA];
  29 static uint8_t ao_dma_mutex[NUM_DMA];
  30
  31 static void
  32 ao_dma_isr(uint8_t index) {
  33         /* Get channel interrupt bits */
  34         uint32_t        isr = stm_dma.isr & (STM_DMA_ISR_MASK <<
  35                                              STM_DMA_ISR(index));
  36
  37         /* Ack them */
  38         stm_dma.ifcr = isr;
  39         isr >>= STM_DMA_ISR(index);
  40         ao_dma_config[index].isr |= isr;
  41         ao_dma_done[index] = 1;
  42         ao_wakeup(&ao_dma_done[index]);
  43 }
  44
  45 void stm_dma1_channel1_isr(void) { ao_dma_isr(STM_DMA_INDEX(1)); }
  46 void stm_dma1_channel2_isr(void) { ao_dma_isr(STM_DMA_INDEX(2)); }
  47 void stm_dma1_channel3_isr(void) { ao_dma_isr(STM_DMA_INDEX(3)); }
  48 void stm_dma1_channel4_isr(void) { ao_dma_isr(STM_DMA_INDEX(4)); }
  49 void stm_dma1_channel5_isr(void) { ao_dma_isr(STM_DMA_INDEX(5)); }
  50 void stm_dma1_channel6_isr(void) { ao_dma_isr(STM_DMA_INDEX(6)); }
  51 void stm_dma1_channel7_isr(void) { ao_dma_isr(STM_DMA_INDEX(7)); }
  52
  53 void
  54 ao_dma_set_transfer(uint8_t             index,
  55                     volatile void       *peripheral,
  56                     void                *memory,
  57                     uint16_t            count,
  58                     uint32_t            ccr)
  59 {
  60         ao_mutex_get(&ao_dma_mutex[index]);
  61         stm_dma.channel[index].ccr = ccr | (1 << STM_DMA_CCR_TCIE);
  62         stm_dma.channel[index].cndtr = count;
  63         stm_dma.channel[index].cpar = (uint32_t) peripheral;
  64         stm_dma.channel[index].cmar = (uint32_t) memory;
  65 }
  66
  67 void
  68 ao_dma_start(uint8_t index)
  69 {
  70         ao_dma_done[index] = 0;
  71         stm_dma.channel[index].ccr |= (1 << STM_DMA_CCR_EN);
  72 }
  73
  74 void
  75 ao_dma_done_transfer(uint8_t index)
  76 {
  77         stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
  78         ao_mutex_put(&ao_dma_mutex[index]);
  79 }
  80
  81 void
  82 ao_dma_abort(uint8_t index)
  83 {
  84         stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
  85 }
  86
  87 void
  88 ao_dma_init(void)
  89 {
  90         int     index;
  91
  92         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
  93
  94         for (index = 0; index < STM_NUM_DMA; index++) {
  95                 stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
  96                 stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index, 4);
  97         }
  98
  99 }