Merge remote-tracking branch 'mjb/master'
[fw/altos] / src / stm / ao_arch_funcs.h
1 /*
2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; version 2 of the License.
7  *
8  * This program is distributed in the hope that it will be useful, but
9  * WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
11  * General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License along
14  * with this program; if not, write to the Free Software Foundation, Inc.,
15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
16  */
17
18 #ifndef _AO_ARCH_FUNCS_H_
19 #define _AO_ARCH_FUNCS_H_
20
21 /* ao_spi_stm.c
22  */
23
24 #define AO_SPI_SPEED_FAST       STM_SPI_CR1_BR_PCLK_4
25 #define AO_SPI_SPEED_1MHz       STM_SPI_CR1_BR_PCLK_16
26 #define AO_SPI_SPEED_200kHz     STM_SPI_CR1_BR_PCLK_256
27
28 #define AO_SPI_CONFIG_1         0x00
29 #define AO_SPI_1_CONFIG_PA5_PA6_PA7     AO_SPI_CONFIG_1
30 #define AO_SPI_2_CONFIG_PB13_PB14_PB15  AO_SPI_CONFIG_1
31
32 #define AO_SPI_CONFIG_2         0x04
33 #define AO_SPI_1_CONFIG_PB3_PB4_PB5     AO_SPI_CONFIG_2
34 #define AO_SPI_2_CONFIG_PD1_PD3_PD4     AO_SPI_CONFIG_2
35
36 #define AO_SPI_CONFIG_3         0x08
37 #define AO_SPI_1_CONFIG_PE13_PE14_PE15  AO_SPI_CONFIG_3
38
39 #define AO_SPI_CONFIG_NONE      0x0c
40
41 #define AO_SPI_INDEX_MASK       0x01
42 #define AO_SPI_CONFIG_MASK      0x0c
43
44 #define AO_SPI_1_PA5_PA6_PA7    (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
45 #define AO_SPI_1_PB3_PB4_PB5    (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
46 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
47
48 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
49 #define AO_SPI_2_PD1_PD3_PD4    (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
50
51 #define AO_SPI_INDEX(id)        ((id) & AO_SPI_INDEX_MASK)
52 #define AO_SPI_CONFIG(id)       ((id) & AO_SPI_CONFIG_MASK)
53
54 void
55 ao_spi_get(uint8_t spi_index, uint32_t speed);
56
57 void
58 ao_spi_put(uint8_t spi_index);
59
60 void
61 ao_spi_send(void *block, uint16_t len, uint8_t spi_index);
62
63 void
64 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
65
66 void
67 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
68
69 void
70 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
71
72 extern uint16_t ao_spi_speed[STM_NUM_SPI];
73
74 void
75 ao_spi_init(void);
76
77 #define ao_spi_get_mask(reg,mask,bus, speed) do {               \
78                 ao_spi_get(bus, speed);                         \
79                 (reg)->bsrr = ((uint32_t) mask) << 16;  \
80         } while (0)
81
82 #define ao_spi_put_mask(reg,mask,bus) do {      \
83                 (reg)->bsrr = mask;             \
84                 ao_spi_put(bus);                \
85         } while (0)
86
87 #define ao_spi_get_bit(reg,bit,pin,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
88 #define ao_spi_put_bit(reg,bit,pin,bus) ao_spi_put_mask(reg,(1<<bit),bus)
89
90 #define ao_enable_port(port) do {                                       \
91                 if ((port) == &stm_gpioa)                               \
92                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
93                 else if ((port) == &stm_gpiob)                          \
94                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
95                 else if ((port) == &stm_gpioc)                          \
96                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
97                 else if ((port) == &stm_gpiod)                          \
98                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
99                 else if ((port) == &stm_gpioe)                          \
100                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
101         } while (0)
102
103
104 #define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
105
106 #define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
107
108 #define ao_enable_output(port,bit,pin,v) do {                   \
109                 ao_enable_port(port);                           \
110                 ao_gpio_set(port, bit, pin, v);                 \
111                 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
112         } while (0)
113
114 #define ao_enable_input(port,bit,mode) do {                             \
115                 ao_enable_port(port);                                   \
116                 stm_moder_set(port, bit, STM_MODER_INPUT);              \
117                 if (mode == AO_EXTI_MODE_PULL_UP)                       \
118                         stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP);    \
119                 else if (mode == AO_EXTI_MODE_PULL_DOWN)                \
120                         stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN);  \
121                 else                                                    \
122                         stm_pupdr_set(port, bit, STM_PUPDR_NONE);       \
123         } while (0)
124
125 #define ao_enable_cs(port,bit) do {                             \
126                 stm_gpio_set((port), bit, 1);                   \
127                 stm_moder_set((port), bit, STM_MODER_OUTPUT);   \
128         } while (0)
129
130 #define ao_spi_init_cs(port, mask) do {                         \
131                 ao_enable_port(port);                           \
132                 if ((mask) & 0x0001) ao_enable_cs(port, 0);     \
133                 if ((mask) & 0x0002) ao_enable_cs(port, 1);     \
134                 if ((mask) & 0x0004) ao_enable_cs(port, 2);     \
135                 if ((mask) & 0x0008) ao_enable_cs(port, 3);     \
136                 if ((mask) & 0x0010) ao_enable_cs(port, 4);     \
137                 if ((mask) & 0x0020) ao_enable_cs(port, 5);     \
138                 if ((mask) & 0x0040) ao_enable_cs(port, 6);     \
139                 if ((mask) & 0x0080) ao_enable_cs(port, 7);     \
140                 if ((mask) & 0x0100) ao_enable_cs(port, 8);     \
141                 if ((mask) & 0x0200) ao_enable_cs(port, 9);     \
142                 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
143                 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
144                 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
145                 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
146                 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
147                 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
148         } while (0)
149
150 /* ao_dma_stm.c
151  */
152
153 extern uint8_t ao_dma_done[STM_NUM_DMA];
154
155 void
156 ao_dma_set_transfer(uint8_t             index,
157                     volatile void       *peripheral,
158                     void                *memory,
159                     uint16_t            count,
160                     uint32_t            ccr);
161
162 void
163 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
164
165 void
166 ao_dma_start(uint8_t index);
167
168 void
169 ao_dma_done_transfer(uint8_t index);
170
171 void
172 ao_dma_abort(uint8_t index);
173
174 void
175 ao_dma_alloc(uint8_t index);
176
177 void
178 ao_dma_init(void);
179
180 /* ao_i2c_stm.c */
181
182 void
183 ao_i2c_get(uint8_t i2c_index);
184
185 uint8_t
186 ao_i2c_start(uint8_t i2c_index, uint16_t address);
187
188 void
189 ao_i2c_put(uint8_t i2c_index);
190
191 uint8_t
192 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
193
194 uint8_t
195 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
196
197 void
198 ao_i2c_init(void);
199
200 #endif /* _AO_ARCH_FUNCS_H_ */