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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20
  21 volatile __xdata struct ao_adc  ao_adc_ring[AO_ADC_RING];
  22 volatile __data uint8_t         ao_adc_head;
  23 static uint8_t                  ao_adc_ready;
  24
  25 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  26                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  27                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  28                                  (0 << STM_ADC_CR2_JWSTART) |           \
  29                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  30                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  31                                  (0 << STM_ADC_CR2_ALIGN) |             \
  32                                  (0 << STM_ADC_CR2_EOCS) |              \
  33                                  (1 << STM_ADC_CR2_DDS) |               \
  34                                  (1 << STM_ADC_CR2_DMA) |               \
  35                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  36                                  (0 << STM_ADC_CR2_CONT) |              \
  37                                  (1 << STM_ADC_CR2_ADON))
  38
  39 /*
  40  * Callback from DMA ISR
  41  *
  42  * Mark time in ring, shut down DMA engine
  43  */
  44 static void ao_adc_done(int index)
  45 {
  46         ao_adc_ring[ao_adc_head].tick = ao_time();
  47         ao_adc_head = ao_adc_ring_next(ao_adc_head);
  48         ao_wakeup((void *) &ao_adc_head);
  49         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  50         ao_adc_ready = 1;
  51 }
  52
  53 /*
  54  * Start the ADC sequence using the DMA engine
  55  */
  56 void
  57 ao_adc_poll(void)
  58 {
  59         if (!ao_adc_ready)
  60                 return;
  61         ao_adc_ready = 0;
  62         stm_adc.sr = 0;
  63         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  64                             &stm_adc.dr,
  65                             (void *) (&ao_adc_ring[ao_adc_head].tick + 1),
  66                             AO_NUM_ADC,
  67                             (0 << STM_DMA_CCR_MEM2MEM) |
  68                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  69                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  70                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  71                             (1 << STM_DMA_CCR_MINC) |
  72                             (0 << STM_DMA_CCR_PINC) |
  73                             (0 << STM_DMA_CCR_CIRC) |
  74                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  75         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  76         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  77
  78         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  79 }
  80
  81 /*
  82  * Fetch a copy of the most recent ADC data
  83  */
  84 void
  85 ao_adc_get(__xdata struct ao_adc *packet)
  86 {
  87         uint8_t i = ao_adc_ring_prev(ao_adc_head);
  88         memcpy(packet, (void *) &ao_adc_ring[i], sizeof (struct ao_adc));
  89 }
  90
  91 static void
  92 ao_adc_dump(void) __reentrant
  93 {
  94         struct ao_adc   packet;
  95         int16_t *d;
  96         uint8_t i;
  97
  98         ao_adc_get(&packet);
  99         printf("tick: %5u",  packet.tick);
 100         d = (int16_t *) (&packet.tick + 1);
 101         for (i = 0; i < AO_NUM_ADC; i++)
 102                 printf (" %2d: %5d", i, d[i]);
 103         printf("\n");
 104 }
 105
 106 __code struct ao_cmds ao_adc_cmds[] = {
 107         { ao_adc_dump,  "a\0Display current ADC values" },
 108         { 0, NULL },
 109 };
 110
 111 void
 112 ao_adc_init(void)
 113 {
 114 #ifdef AO_ADC_PIN0_PORT
 115         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 116 #endif
 117
 118 #ifdef AO_ADC_PIN0_PORT
 119         stm_moder_set(&AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 120 #endif
 121 #ifdef AO_ADC_PIN1_PORT
 122         stm_moder_set(&AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 123 #endif
 124 #ifdef AO_ADC_PIN2_PORT
 125         stm_moder_set(&AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 126 #endif
 127 #ifdef AO_ADC_PIN3_PORT
 128         stm_moder_set(&AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 129 #endif
 130 #ifdef AO_ADC_PIN4_PORT
 131         stm_moder_set(&AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 132 #endif
 133 #ifdef AO_ADC_PIN5_PORT
 134         stm_moder_set(&AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 135 #endif
 136 #ifdef AO_ADC_PIN6_PORT
 137         stm_moder_set(&AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 138 #endif
 139 #ifdef AO_ADC_PIN7_PORT
 140         stm_moder_set(&AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 141 #endif
 142 #ifdef AO_ADC_PIN8_PORT
 143         stm_moder_set(&AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 144 #endif
 145 #ifdef AO_ADC_PIN9_PORT
 146         stm_moder_set(&AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 147 #endif
 148
 149         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 150
 151         /* Turn off ADC during configuration */
 152         stm_adc.cr2 = 0;
 153
 154         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 155                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 156                        (0 << STM_ADC_CR1_AWDEN ) |
 157                        (0 << STM_ADC_CR1_JAWDEN ) |
 158                        (0 << STM_ADC_CR1_PDI ) |
 159                        (0 << STM_ADC_CR1_PDD ) |
 160                        (0 << STM_ADC_CR1_DISCNUM ) |
 161                        (0 << STM_ADC_CR1_JDISCEN ) |
 162                        (0 << STM_ADC_CR1_DISCEN ) |
 163                        (0 << STM_ADC_CR1_JAUTO ) |
 164                        (0 << STM_ADC_CR1_AWDSGL ) |
 165                        (1 << STM_ADC_CR1_SCAN ) |
 166                        (0 << STM_ADC_CR1_JEOCIE ) |
 167                        (0 << STM_ADC_CR1_AWDIE ) |
 168                        (0 << STM_ADC_CR1_EOCIE ) |
 169                        (0 << STM_ADC_CR1_AWDCH ));
 170
 171         /* 384 cycle sample time for everyone */
 172         stm_adc.smpr1 = 0x3ffff;
 173         stm_adc.smpr2 = 0x3fffffff;
 174         stm_adc.smpr3 = 0x3fffffff;
 175
 176         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 177         stm_adc.sqr2 = 0;
 178         stm_adc.sqr3 = 0;
 179         stm_adc.sqr4 = 0;
 180         stm_adc.sqr5 = 0;
 181 #if AO_NUM_ADC > 0
 182         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 183 #endif
 184 #if AO_NUM_ADC > 1
 185         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 186 #endif
 187 #if AO_NUM_ADC > 2
 188         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 189 #endif
 190 #if AO_NUM_ADC > 3
 191         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 192 #endif
 193 #if AO_NUM_ADC > 4
 194         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 195 #endif
 196 #if AO_NUM_ADC > 5
 197         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 198 #endif
 199 #if AO_NUM_ADC > 6
 200         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 201 #endif
 202 #if AO_NUM_ADC > 7
 203         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 204 #endif
 205 #if AO_NUM_ADC > 8
 206         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 207 #endif
 208
 209         /* Turn ADC on */
 210         stm_adc.cr2 = AO_ADC_CR2_VAL;
 211
 212         /* Wait for ADC to be ready */
 213         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 214                 ;
 215
 216 #if HAS_ADC_TEMP
 217         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 218 #else
 219         stm_adc.ccr = 0;
 220 #endif
 221         /* Clear any stale status bits */
 222         stm_adc.sr = 0;
 223         ao_adc_ready = 1;
 224
 225         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 226         ao_cmd_register(&ao_adc_cmds[0]);
 227 }