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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20 #include <ao_data.h>
  21
  22 static uint8_t                  ao_adc_ready;
  23
  24 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  25                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  26                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  27                                  (0 << STM_ADC_CR2_JWSTART) |           \
  28                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  29                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  30                                  (0 << STM_ADC_CR2_ALIGN) |             \
  31                                  (0 << STM_ADC_CR2_EOCS) |              \
  32                                  (1 << STM_ADC_CR2_DDS) |               \
  33                                  (1 << STM_ADC_CR2_DMA) |               \
  34                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  35                                  (0 << STM_ADC_CR2_CONT) |              \
  36                                  (1 << STM_ADC_CR2_ADON))
  37
  38 /*
  39  * Callback from DMA ISR
  40  *
  41  * Mark time in ring, shut down DMA engine
  42  */
  43 static void ao_adc_done(int index)
  44 {
  45         (void) index;
  46         AO_DATA_PRESENT(AO_DATA_ADC);
  47         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  48         ao_data_fill(ao_data_head);
  49         ao_adc_ready = 1;
  50 }
  51
  52 /*
  53  * Start the ADC sequence using the DMA engine
  54  */
  55 void
  56 ao_adc_poll(void)
  57 {
  58         if (!ao_adc_ready)
  59                 return;
  60         ao_adc_ready = 0;
  61         stm_adc.sr = 0;
  62         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  63                             &stm_adc.dr,
  64                             (void *) (&ao_data_ring[ao_data_head].adc),
  65                             AO_NUM_ADC,
  66                             (0 << STM_DMA_CCR_MEM2MEM) |
  67                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  68                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  69                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  70                             (1 << STM_DMA_CCR_MINC) |
  71                             (0 << STM_DMA_CCR_PINC) |
  72                             (0 << STM_DMA_CCR_CIRC) |
  73                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  74         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  75         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  76
  77         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  78 }
  79
  80 /*
  81  * Fetch a copy of the most recent ADC data
  82  */
  83 void
  84 ao_adc_get(struct ao_adc *packet)
  85 {
  86 #if HAS_FLIGHT
  87         uint8_t i = ao_data_ring_prev(ao_sample_data);
  88 #else
  89         uint8_t i = ao_data_ring_prev(ao_data_head);
  90 #endif
  91         memcpy(packet, (void *) &ao_data_ring[i].adc, sizeof (struct ao_adc));
  92 }
  93
  94 #ifdef AO_ADC_SQ1_NAME
  95 static const char *ao_adc_name[AO_NUM_ADC] = {
  96         AO_ADC_SQ1_NAME,
  97 #ifdef AO_ADC_SQ2_NAME
  98         AO_ADC_SQ2_NAME,
  99 #endif
 100 #ifdef AO_ADC_SQ3_NAME
 101         AO_ADC_SQ3_NAME,
 102 #endif
 103 #ifdef AO_ADC_SQ4_NAME
 104         AO_ADC_SQ4_NAME,
 105 #endif
 106 #ifdef AO_ADC_SQ5_NAME
 107         AO_ADC_SQ5_NAME,
 108 #endif
 109 #ifdef AO_ADC_SQ6_NAME
 110         AO_ADC_SQ6_NAME,
 111 #endif
 112 #ifdef AO_ADC_SQ7_NAME
 113         AO_ADC_SQ7_NAME,
 114 #endif
 115 #ifdef AO_ADC_SQ8_NAME
 116         AO_ADC_SQ8_NAME,
 117 #endif
 118 #ifdef AO_ADC_SQ9_NAME
 119         AO_ADC_SQ9_NAME,
 120 #endif
 121 #ifdef AO_ADC_SQ10_NAME
 122         AO_ADC_SQ10_NAME,
 123 #endif
 124 #ifdef AO_ADC_SQ11_NAME
 125         AO_ADC_SQ11_NAME,
 126 #endif
 127 #ifdef AO_ADC_SQ12_NAME
 128         AO_ADC_SQ12_NAME,
 129 #endif
 130 #ifdef AO_ADC_SQ13_NAME
 131         AO_ADC_SQ13_NAME,
 132 #endif
 133 #ifdef AO_ADC_SQ14_NAME
 134         AO_ADC_SQ14_NAME,
 135 #endif
 136 #ifdef AO_ADC_SQ15_NAME
 137         AO_ADC_SQ15_NAME,
 138 #endif
 139 #ifdef AO_ADC_SQ16_NAME
 140         AO_ADC_SQ16_NAME,
 141 #endif
 142 #ifdef AO_ADC_SQ17_NAME
 143         AO_ADC_SQ17_NAME,
 144 #endif
 145 #ifdef AO_ADC_SQ18_NAME
 146         AO_ADC_SQ18_NAME,
 147 #endif
 148 #ifdef AO_ADC_SQ19_NAME
 149         AO_ADC_SQ19_NAME,
 150 #endif
 151 #ifdef AO_ADC_SQ20_NAME
 152         AO_ADC_SQ20_NAME,
 153 #endif
 154 #ifdef AO_ADC_SQ21_NAME
 155         #error "too many ADC names"
 156 #endif
 157 };
 158 #endif
 159
 160 static void
 161 ao_adc_dump(void)
 162 {
 163         struct ao_data  packet;
 164 #ifndef AO_ADC_DUMP
 165         uint8_t i;
 166         int16_t *d;
 167 #endif
 168
 169         ao_data_get(&packet);
 170 #ifdef AO_ADC_DUMP
 171         AO_ADC_DUMP(&packet);
 172 #else
 173         printf("tick: %5u",  packet.tick);
 174         d = (int16_t *) (&packet.adc);
 175         for (i = 0; i < AO_NUM_ADC; i++) {
 176 #ifdef AO_ADC_SQ1_NAME
 177                 if (ao_adc_name[i])
 178                         printf (" %s: %5d", ao_adc_name[i], d[i]);
 179                 else
 180 #endif
 181                         printf (" %2d: %5d", i, d[i]);
 182         }
 183         printf("\n");
 184 #endif
 185 }
 186
 187 const struct ao_cmds ao_adc_cmds[] = {
 188         { ao_adc_dump,  "a\0Display current ADC values" },
 189         { 0, NULL },
 190 };
 191
 192 void
 193 ao_adc_init(void)
 194 {
 195 #ifdef AO_ADC_PIN0_PORT
 196         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 197 #endif
 198
 199 #ifdef AO_ADC_PIN0_PORT
 200         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 201 #endif
 202 #ifdef AO_ADC_PIN1_PORT
 203         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 204 #endif
 205 #ifdef AO_ADC_PIN2_PORT
 206         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 207 #endif
 208 #ifdef AO_ADC_PIN3_PORT
 209         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 210 #endif
 211 #ifdef AO_ADC_PIN4_PORT
 212         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 213 #endif
 214 #ifdef AO_ADC_PIN5_PORT
 215         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 216 #endif
 217 #ifdef AO_ADC_PIN6_PORT
 218         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 219 #endif
 220 #ifdef AO_ADC_PIN7_PORT
 221         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 222 #endif
 223 #ifdef AO_ADC_PIN8_PORT
 224         stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 225 #endif
 226 #ifdef AO_ADC_PIN9_PORT
 227         stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 228 #endif
 229 #ifdef AO_ADC_PIN10_PORT
 230         stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
 231 #endif
 232 #ifdef AO_ADC_PIN11_PORT
 233         stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
 234 #endif
 235 #ifdef AO_ADC_PIN12_PORT
 236         stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
 237 #endif
 238 #ifdef AO_ADC_PIN13_PORT
 239         stm_moder_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN, STM_MODER_ANALOG);
 240 #endif
 241 #ifdef AO_ADC_PIN14_PORT
 242         stm_moder_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN, STM_MODER_ANALOG);
 243 #endif
 244 #ifdef AO_ADC_PIN15_PORT
 245         stm_moder_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN, STM_MODER_ANALOG);
 246 #endif
 247 #ifdef AO_ADC_PIN16_PORT
 248         stm_moder_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN, STM_MODER_ANALOG);
 249 #endif
 250 #ifdef AO_ADC_PIN17_PORT
 251         stm_moder_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN, STM_MODER_ANALOG);
 252 #endif
 253 #ifdef AO_ADC_PIN18_PORT
 254         stm_moder_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN, STM_MODER_ANALOG);
 255 #endif
 256 #ifdef AO_ADC_PIN19_PORT
 257         stm_moder_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN, STM_MODER_ANALOG);
 258 #endif
 259 #ifdef AO_ADC_PIN20_PORT
 260         stm_moder_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN, STM_MODER_ANALOG);
 261 #endif
 262 #ifdef AO_ADC_PIN21_PORT
 263         stm_moder_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN, STM_MODER_ANALOG);
 264 #endif
 265 #ifdef AO_ADC_PIN22_PORT
 266         stm_moder_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN, STM_MODER_ANALOG);
 267 #endif
 268 #ifdef AO_ADC_PIN23_PORT
 269         stm_moder_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN, STM_MODER_ANALOG);
 270 #endif
 271 #ifdef AO_ADC_PIN24_PORT
 272         #error "Too many ADC ports"
 273 #endif
 274
 275         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 276
 277         /* Turn off ADC during configuration */
 278         stm_adc.cr2 = 0;
 279
 280         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 281                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 282                        (0 << STM_ADC_CR1_AWDEN ) |
 283                        (0 << STM_ADC_CR1_JAWDEN ) |
 284                        (0 << STM_ADC_CR1_PDI ) |
 285                        (0 << STM_ADC_CR1_PDD ) |
 286                        (0 << STM_ADC_CR1_DISCNUM ) |
 287                        (0 << STM_ADC_CR1_JDISCEN ) |
 288                        (0 << STM_ADC_CR1_DISCEN ) |
 289                        (0 << STM_ADC_CR1_JAUTO ) |
 290                        (0 << STM_ADC_CR1_AWDSGL ) |
 291                        (1 << STM_ADC_CR1_SCAN ) |
 292                        (0 << STM_ADC_CR1_JEOCIE ) |
 293                        (0 << STM_ADC_CR1_AWDIE ) |
 294                        (0 << STM_ADC_CR1_EOCIE ) |
 295                        (0 << STM_ADC_CR1_AWDCH ));
 296
 297         /* 384 cycle sample time for everyone */
 298         stm_adc.smpr1 = 0x3ffff;
 299         stm_adc.smpr2 = 0x3fffffff;
 300         stm_adc.smpr3 = 0x3fffffff;
 301
 302         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 303         stm_adc.sqr2 = 0;
 304         stm_adc.sqr3 = 0;
 305         stm_adc.sqr4 = 0;
 306         stm_adc.sqr5 = 0;
 307 #if AO_NUM_ADC > 0
 308         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 309 #endif
 310 #if AO_NUM_ADC > 1
 311         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 312 #endif
 313 #if AO_NUM_ADC > 2
 314         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 315 #endif
 316 #if AO_NUM_ADC > 3
 317         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 318 #endif
 319 #if AO_NUM_ADC > 4
 320         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 321 #endif
 322 #if AO_NUM_ADC > 5
 323         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 324 #endif
 325 #if AO_NUM_ADC > 6
 326         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 327 #endif
 328 #if AO_NUM_ADC > 7
 329         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 330 #endif
 331 #if AO_NUM_ADC > 8
 332         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 333 #endif
 334 #if AO_NUM_ADC > 9
 335         stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
 336 #endif
 337 #if AO_NUM_ADC > 10
 338         stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
 339 #endif
 340 #if AO_NUM_ADC > 11
 341         stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
 342 #endif
 343 #if AO_NUM_ADC > 12
 344         stm_adc.sqr3 |= (AO_ADC_SQ13 << 0);
 345 #endif
 346 #if AO_NUM_ADC > 13
 347         stm_adc.sqr3 |= (AO_ADC_SQ14 << 5);
 348 #endif
 349 #if AO_NUM_ADC > 14
 350         stm_adc.sqr3 |= (AO_ADC_SQ15 << 10);
 351 #endif
 352 #if AO_NUM_ADC > 15
 353         stm_adc.sqr3 |= (AO_ADC_SQ16 << 15);
 354 #endif
 355 #if AO_NUM_ADC > 16
 356         stm_adc.sqr3 |= (AO_ADC_SQ17 << 20);
 357 #endif
 358 #if AO_NUM_ADC > 17
 359         stm_adc.sqr3 |= (AO_ADC_SQ18 << 25);
 360 #endif
 361 #if AO_NUM_ADC > 18
 362 #error "need to finish stm_adc.sqr settings"
 363 #endif
 364
 365         /* Turn ADC on */
 366         stm_adc.cr2 = AO_ADC_CR2_VAL;
 367
 368         /* Wait for ADC to be ready */
 369         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 370                 ;
 371
 372 #ifndef HAS_ADC_TEMP
 373 #error Please define HAS_ADC_TEMP
 374 #endif
 375 #if HAS_ADC_TEMP
 376         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 377 #else
 378         stm_adc.ccr = 0;
 379 #endif
 380         /* Clear any stale status bits */
 381         stm_adc.sr = 0;
 382
 383         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 384
 385         ao_cmd_register(&ao_adc_cmds[0]);
 386
 387         ao_adc_ready = 1;
 388 }