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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20 #include <ao_data.h>
  21
  22 static uint8_t                  ao_adc_ready;
  23
  24 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  25                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  26                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  27                                  (0 << STM_ADC_CR2_JWSTART) |           \
  28                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  29                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  30                                  (0 << STM_ADC_CR2_ALIGN) |             \
  31                                  (0 << STM_ADC_CR2_EOCS) |              \
  32                                  (1 << STM_ADC_CR2_DDS) |               \
  33                                  (1 << STM_ADC_CR2_DMA) |               \
  34                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  35                                  (0 << STM_ADC_CR2_CONT) |              \
  36                                  (1 << STM_ADC_CR2_ADON))
  37
  38 /*
  39  * Callback from DMA ISR
  40  *
  41  * Mark time in ring, shut down DMA engine
  42  */
  43 static void ao_adc_done(int index)
  44 {
  45         (void) index;
  46         AO_DATA_PRESENT(AO_DATA_ADC);
  47         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  48         ao_data_fill(ao_data_head);
  49         ao_adc_ready = 1;
  50 }
  51
  52 /*
  53  * Start the ADC sequence using the DMA engine
  54  */
  55 void
  56 ao_adc_poll(void)
  57 {
  58         if (!ao_adc_ready)
  59                 return;
  60         ao_adc_ready = 0;
  61         stm_adc.sr = 0;
  62         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  63                             &stm_adc.dr,
  64                             (void *) (&ao_data_ring[ao_data_head].adc),
  65                             AO_NUM_ADC,
  66                             (0 << STM_DMA_CCR_MEM2MEM) |
  67                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  68                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  69                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  70                             (1 << STM_DMA_CCR_MINC) |
  71                             (0 << STM_DMA_CCR_PINC) |
  72                             (0 << STM_DMA_CCR_CIRC) |
  73                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  74         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  75         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  76
  77         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  78 }
  79
  80 #ifdef AO_ADC_SQ1_NAME
  81 static const char *ao_adc_name[AO_NUM_ADC] = {
  82         AO_ADC_SQ1_NAME,
  83 #ifdef AO_ADC_SQ2_NAME
  84         AO_ADC_SQ2_NAME,
  85 #endif
  86 #ifdef AO_ADC_SQ3_NAME
  87         AO_ADC_SQ3_NAME,
  88 #endif
  89 #ifdef AO_ADC_SQ4_NAME
  90         AO_ADC_SQ4_NAME,
  91 #endif
  92 #ifdef AO_ADC_SQ5_NAME
  93         AO_ADC_SQ5_NAME,
  94 #endif
  95 #ifdef AO_ADC_SQ6_NAME
  96         AO_ADC_SQ6_NAME,
  97 #endif
  98 #ifdef AO_ADC_SQ7_NAME
  99         AO_ADC_SQ7_NAME,
 100 #endif
 101 #ifdef AO_ADC_SQ8_NAME
 102         AO_ADC_SQ8_NAME,
 103 #endif
 104 #ifdef AO_ADC_SQ9_NAME
 105         AO_ADC_SQ9_NAME,
 106 #endif
 107 #ifdef AO_ADC_SQ10_NAME
 108         AO_ADC_SQ10_NAME,
 109 #endif
 110 #ifdef AO_ADC_SQ11_NAME
 111         AO_ADC_SQ11_NAME,
 112 #endif
 113 #ifdef AO_ADC_SQ12_NAME
 114         AO_ADC_SQ12_NAME,
 115 #endif
 116 #ifdef AO_ADC_SQ13_NAME
 117         AO_ADC_SQ13_NAME,
 118 #endif
 119 #ifdef AO_ADC_SQ14_NAME
 120         AO_ADC_SQ14_NAME,
 121 #endif
 122 #ifdef AO_ADC_SQ15_NAME
 123         AO_ADC_SQ15_NAME,
 124 #endif
 125 #ifdef AO_ADC_SQ16_NAME
 126         AO_ADC_SQ16_NAME,
 127 #endif
 128 #ifdef AO_ADC_SQ17_NAME
 129         AO_ADC_SQ17_NAME,
 130 #endif
 131 #ifdef AO_ADC_SQ18_NAME
 132         AO_ADC_SQ18_NAME,
 133 #endif
 134 #ifdef AO_ADC_SQ19_NAME
 135         AO_ADC_SQ19_NAME,
 136 #endif
 137 #ifdef AO_ADC_SQ20_NAME
 138         AO_ADC_SQ20_NAME,
 139 #endif
 140 #ifdef AO_ADC_SQ21_NAME
 141         #error "too many ADC names"
 142 #endif
 143 };
 144 #endif
 145
 146 static void
 147 ao_adc_dump(void)
 148 {
 149         struct ao_data  packet;
 150 #ifndef AO_ADC_DUMP
 151         uint8_t i;
 152         int16_t *d;
 153 #endif
 154
 155         ao_data_get(&packet);
 156 #ifdef AO_ADC_DUMP
 157         AO_ADC_DUMP(&packet);
 158 #else
 159         printf("tick: %5u",  packet.tick);
 160         d = (int16_t *) (&packet.adc);
 161         for (i = 0; i < AO_NUM_ADC; i++) {
 162 #ifdef AO_ADC_SQ1_NAME
 163                 if (ao_adc_name[i])
 164                         printf (" %s: %5d", ao_adc_name[i], d[i]);
 165                 else
 166 #endif
 167                         printf (" %2d: %5d", i, d[i]);
 168         }
 169         printf("\n");
 170 #endif
 171 }
 172
 173 const struct ao_cmds ao_adc_cmds[] = {
 174         { ao_adc_dump,  "a\0Display current ADC values" },
 175         { 0, NULL },
 176 };
 177
 178 void
 179 ao_adc_init(void)
 180 {
 181 #ifdef AO_ADC_PIN0_PORT
 182         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 183 #endif
 184
 185 #ifdef AO_ADC_PIN0_PORT
 186         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 187 #endif
 188 #ifdef AO_ADC_PIN1_PORT
 189         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 190 #endif
 191 #ifdef AO_ADC_PIN2_PORT
 192         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 193 #endif
 194 #ifdef AO_ADC_PIN3_PORT
 195         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 196 #endif
 197 #ifdef AO_ADC_PIN4_PORT
 198         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 199 #endif
 200 #ifdef AO_ADC_PIN5_PORT
 201         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 202 #endif
 203 #ifdef AO_ADC_PIN6_PORT
 204         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 205 #endif
 206 #ifdef AO_ADC_PIN7_PORT
 207         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 208 #endif
 209 #ifdef AO_ADC_PIN8_PORT
 210         stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 211 #endif
 212 #ifdef AO_ADC_PIN9_PORT
 213         stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 214 #endif
 215 #ifdef AO_ADC_PIN10_PORT
 216         stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
 217 #endif
 218 #ifdef AO_ADC_PIN11_PORT
 219         stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
 220 #endif
 221 #ifdef AO_ADC_PIN12_PORT
 222         stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
 223 #endif
 224 #ifdef AO_ADC_PIN13_PORT
 225         stm_moder_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN, STM_MODER_ANALOG);
 226 #endif
 227 #ifdef AO_ADC_PIN14_PORT
 228         stm_moder_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN, STM_MODER_ANALOG);
 229 #endif
 230 #ifdef AO_ADC_PIN15_PORT
 231         stm_moder_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN, STM_MODER_ANALOG);
 232 #endif
 233 #ifdef AO_ADC_PIN16_PORT
 234         stm_moder_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN, STM_MODER_ANALOG);
 235 #endif
 236 #ifdef AO_ADC_PIN17_PORT
 237         stm_moder_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN, STM_MODER_ANALOG);
 238 #endif
 239 #ifdef AO_ADC_PIN18_PORT
 240         stm_moder_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN, STM_MODER_ANALOG);
 241 #endif
 242 #ifdef AO_ADC_PIN19_PORT
 243         stm_moder_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN, STM_MODER_ANALOG);
 244 #endif
 245 #ifdef AO_ADC_PIN20_PORT
 246         stm_moder_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN, STM_MODER_ANALOG);
 247 #endif
 248 #ifdef AO_ADC_PIN21_PORT
 249         stm_moder_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN, STM_MODER_ANALOG);
 250 #endif
 251 #ifdef AO_ADC_PIN22_PORT
 252         stm_moder_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN, STM_MODER_ANALOG);
 253 #endif
 254 #ifdef AO_ADC_PIN23_PORT
 255         stm_moder_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN, STM_MODER_ANALOG);
 256 #endif
 257 #ifdef AO_ADC_PIN24_PORT
 258         #error "Too many ADC ports"
 259 #endif
 260
 261         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 262
 263         /* Turn off ADC during configuration */
 264         stm_adc.cr2 = 0;
 265
 266         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 267                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 268                        (0 << STM_ADC_CR1_AWDEN ) |
 269                        (0 << STM_ADC_CR1_JAWDEN ) |
 270                        (0 << STM_ADC_CR1_PDI ) |
 271                        (0 << STM_ADC_CR1_PDD ) |
 272                        (0 << STM_ADC_CR1_DISCNUM ) |
 273                        (0 << STM_ADC_CR1_JDISCEN ) |
 274                        (0 << STM_ADC_CR1_DISCEN ) |
 275                        (0 << STM_ADC_CR1_JAUTO ) |
 276                        (0 << STM_ADC_CR1_AWDSGL ) |
 277                        (1 << STM_ADC_CR1_SCAN ) |
 278                        (0 << STM_ADC_CR1_JEOCIE ) |
 279                        (0 << STM_ADC_CR1_AWDIE ) |
 280                        (0 << STM_ADC_CR1_EOCIE ) |
 281                        (0 << STM_ADC_CR1_AWDCH ));
 282
 283         /* 384 cycle sample time for everyone */
 284         stm_adc.smpr1 = 0x3ffff;
 285         stm_adc.smpr2 = 0x3fffffff;
 286         stm_adc.smpr3 = 0x3fffffff;
 287
 288         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 289         stm_adc.sqr2 = 0;
 290         stm_adc.sqr3 = 0;
 291         stm_adc.sqr4 = 0;
 292         stm_adc.sqr5 = 0;
 293 #if AO_NUM_ADC > 0
 294         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 295 #endif
 296 #if AO_NUM_ADC > 1
 297         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 298 #endif
 299 #if AO_NUM_ADC > 2
 300         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 301 #endif
 302 #if AO_NUM_ADC > 3
 303         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 304 #endif
 305 #if AO_NUM_ADC > 4
 306         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 307 #endif
 308 #if AO_NUM_ADC > 5
 309         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 310 #endif
 311 #if AO_NUM_ADC > 6
 312         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 313 #endif
 314 #if AO_NUM_ADC > 7
 315         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 316 #endif
 317 #if AO_NUM_ADC > 8
 318         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 319 #endif
 320 #if AO_NUM_ADC > 9
 321         stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
 322 #endif
 323 #if AO_NUM_ADC > 10
 324         stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
 325 #endif
 326 #if AO_NUM_ADC > 11
 327         stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
 328 #endif
 329 #if AO_NUM_ADC > 12
 330         stm_adc.sqr3 |= (AO_ADC_SQ13 << 0);
 331 #endif
 332 #if AO_NUM_ADC > 13
 333         stm_adc.sqr3 |= (AO_ADC_SQ14 << 5);
 334 #endif
 335 #if AO_NUM_ADC > 14
 336         stm_adc.sqr3 |= (AO_ADC_SQ15 << 10);
 337 #endif
 338 #if AO_NUM_ADC > 15
 339         stm_adc.sqr3 |= (AO_ADC_SQ16 << 15);
 340 #endif
 341 #if AO_NUM_ADC > 16
 342         stm_adc.sqr3 |= (AO_ADC_SQ17 << 20);
 343 #endif
 344 #if AO_NUM_ADC > 17
 345         stm_adc.sqr3 |= (AO_ADC_SQ18 << 25);
 346 #endif
 347 #if AO_NUM_ADC > 18
 348 #error "need to finish stm_adc.sqr settings"
 349 #endif
 350
 351         /* Turn ADC on */
 352         stm_adc.cr2 = AO_ADC_CR2_VAL;
 353
 354         /* Wait for ADC to be ready */
 355         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 356                 ;
 357
 358 #ifndef HAS_ADC_TEMP
 359 #error Please define HAS_ADC_TEMP
 360 #endif
 361 #if HAS_ADC_TEMP
 362         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 363 #else
 364         stm_adc.ccr = 0;
 365 #endif
 366         /* Clear any stale status bits */
 367         stm_adc.sr = 0;
 368
 369         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 370
 371         ao_cmd_register(&ao_adc_cmds[0]);
 372
 373         ao_adc_ready = 1;
 374 }