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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_data.h>
  20
  21 static uint8_t                  ao_adc_ready;
  22
  23 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  24                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  25                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  26                                  (0 << STM_ADC_CR2_JWSTART) |           \
  27                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  28                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  29                                  (0 << STM_ADC_CR2_ALIGN) |             \
  30                                  (0 << STM_ADC_CR2_EOCS) |              \
  31                                  (1 << STM_ADC_CR2_DDS) |               \
  32                                  (1 << STM_ADC_CR2_DMA) |               \
  33                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  34                                  (0 << STM_ADC_CR2_CONT) |              \
  35                                  (1 << STM_ADC_CR2_ADON))
  36
  37 /*
  38  * Callback from DMA ISR
  39  *
  40  * Mark time in ring, shut down DMA engine
  41  */
  42 static void ao_adc_done(int index)
  43 {
  44         AO_DATA_PRESENT(AO_DATA_ADC);
  45         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  46         if (ao_data_present == AO_DATA_ALL) {
  47 #if HAS_MS5607
  48                 ao_data_ring[ao_data_head].ms5607_raw = ao_ms5607_current;
  49 #endif
  50 #if HAS_MMA655X
  51                 ao_data_ring[ao_data_head].mma655x = ao_mma655x_current;
  52 #endif
  53 #if HAS_HMC5883
  54                 ao_data_ring[ao_data_head].hmc5883 = ao_hmc5883_current;
  55 #endif
  56 #if HAS_MPU6000
  57                 ao_data_ring[ao_data_head].mpu6000 = ao_mpu6000_current;
  58 #endif
  59                 ao_data_ring[ao_data_head].tick = ao_tick_count;
  60                 ao_data_head = ao_data_ring_next(ao_data_head);
  61                 ao_wakeup((void *) &ao_data_head);
  62         }
  63         ao_adc_ready = 1;
  64 }
  65
  66 /*
  67  * Start the ADC sequence using the DMA engine
  68  */
  69 void
  70 ao_adc_poll(void)
  71 {
  72         if (!ao_adc_ready)
  73                 return;
  74         ao_adc_ready = 0;
  75         stm_adc.sr = 0;
  76         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  77                             &stm_adc.dr,
  78                             (void *) (&ao_data_ring[ao_data_head].adc),
  79                             AO_NUM_ADC,
  80                             (0 << STM_DMA_CCR_MEM2MEM) |
  81                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  82                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  83                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  84                             (1 << STM_DMA_CCR_MINC) |
  85                             (0 << STM_DMA_CCR_PINC) |
  86                             (0 << STM_DMA_CCR_CIRC) |
  87                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  88         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  89         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  90
  91         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  92 }
  93
  94 /*
  95  * Fetch a copy of the most recent ADC data
  96  */
  97 void
  98 ao_adc_get(__xdata struct ao_adc *packet)
  99 {
 100 #if HAS_FLIGHT
 101         uint8_t i = ao_data_ring_prev(ao_sample_data);
 102 #else
 103         uint8_t i = ao_data_ring_prev(ao_data_head);
 104 #endif
 105         memcpy(packet, (void *) &ao_data_ring[i].adc, sizeof (struct ao_adc));
 106 }
 107
 108 static void
 109 ao_adc_dump(void) __reentrant
 110 {
 111         struct ao_data  packet;
 112         int16_t *d;
 113         uint8_t i;
 114
 115         ao_data_get(&packet);
 116 #ifdef AO_ADC_DUMP
 117         AO_ADC_DUMP(&packet);
 118 #else
 119         printf("tick: %5u",  packet.tick);
 120         d = (int16_t *) (&packet.adc);
 121         for (i = 0; i < AO_NUM_ADC; i++)
 122                 printf (" %2d: %5d", i, d[i]);
 123         printf("\n");
 124 #endif
 125 }
 126
 127 __code struct ao_cmds ao_adc_cmds[] = {
 128         { ao_adc_dump,  "a\0Display current ADC values" },
 129         { 0, NULL },
 130 };
 131
 132 void
 133 ao_adc_init(void)
 134 {
 135 #ifdef AO_ADC_PIN0_PORT
 136         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 137 #endif
 138
 139 #ifdef AO_ADC_PIN0_PORT
 140         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 141 #endif
 142 #ifdef AO_ADC_PIN1_PORT
 143         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 144 #endif
 145 #ifdef AO_ADC_PIN2_PORT
 146         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 147 #endif
 148 #ifdef AO_ADC_PIN3_PORT
 149         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 150 #endif
 151 #ifdef AO_ADC_PIN4_PORT
 152         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 153 #endif
 154 #ifdef AO_ADC_PIN5_PORT
 155         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 156 #endif
 157 #ifdef AO_ADC_PIN6_PORT
 158         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 159 #endif
 160 #ifdef AO_ADC_PIN7_PORT
 161         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 162 #endif
 163 #ifdef AO_ADC_PIN8_PORT
 164         stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 165 #endif
 166 #ifdef AO_ADC_PIN9_PORT
 167         stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 168 #endif
 169 #ifdef AO_ADC_PIN10_PORT
 170         stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
 171 #endif
 172 #ifdef AO_ADC_PIN11_PORT
 173         stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
 174 #endif
 175 #ifdef AO_ADC_PIN12_PORT
 176         stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
 177 #endif
 178
 179         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 180
 181         /* Turn off ADC during configuration */
 182         stm_adc.cr2 = 0;
 183
 184         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 185                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 186                        (0 << STM_ADC_CR1_AWDEN ) |
 187                        (0 << STM_ADC_CR1_JAWDEN ) |
 188                        (0 << STM_ADC_CR1_PDI ) |
 189                        (0 << STM_ADC_CR1_PDD ) |
 190                        (0 << STM_ADC_CR1_DISCNUM ) |
 191                        (0 << STM_ADC_CR1_JDISCEN ) |
 192                        (0 << STM_ADC_CR1_DISCEN ) |
 193                        (0 << STM_ADC_CR1_JAUTO ) |
 194                        (0 << STM_ADC_CR1_AWDSGL ) |
 195                        (1 << STM_ADC_CR1_SCAN ) |
 196                        (0 << STM_ADC_CR1_JEOCIE ) |
 197                        (0 << STM_ADC_CR1_AWDIE ) |
 198                        (0 << STM_ADC_CR1_EOCIE ) |
 199                        (0 << STM_ADC_CR1_AWDCH ));
 200
 201         /* 384 cycle sample time for everyone */
 202         stm_adc.smpr1 = 0x3ffff;
 203         stm_adc.smpr2 = 0x3fffffff;
 204         stm_adc.smpr3 = 0x3fffffff;
 205
 206         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 207         stm_adc.sqr2 = 0;
 208         stm_adc.sqr3 = 0;
 209         stm_adc.sqr4 = 0;
 210         stm_adc.sqr5 = 0;
 211 #if AO_NUM_ADC > 0
 212         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 213 #endif
 214 #if AO_NUM_ADC > 1
 215         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 216 #endif
 217 #if AO_NUM_ADC > 2
 218         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 219 #endif
 220 #if AO_NUM_ADC > 3
 221         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 222 #endif
 223 #if AO_NUM_ADC > 4
 224         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 225 #endif
 226 #if AO_NUM_ADC > 5
 227         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 228 #endif
 229 #if AO_NUM_ADC > 6
 230         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 231 #endif
 232 #if AO_NUM_ADC > 7
 233         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 234 #endif
 235 #if AO_NUM_ADC > 8
 236         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 237 #endif
 238 #if AO_NUM_ADC > 9
 239         stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
 240 #endif
 241 #if AO_NUM_ADC > 10
 242         stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
 243 #endif
 244 #if AO_NUM_ADC > 11
 245         stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
 246 #endif
 247 #if AO_NUM_ADC > 12
 248 #error "need to finish stm_adc.sqr settings"
 249 #endif
 250
 251         /* Turn ADC on */
 252         stm_adc.cr2 = AO_ADC_CR2_VAL;
 253
 254         /* Wait for ADC to be ready */
 255         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 256                 ;
 257
 258 #if HAS_ADC_TEMP
 259         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 260 #else
 261         stm_adc.ccr = 0;
 262 #endif
 263         /* Clear any stale status bits */
 264         stm_adc.sr = 0;
 265
 266         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 267
 268         ao_cmd_register(&ao_adc_cmds[0]);
 269
 270         ao_adc_ready = 1;
 271 }