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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_data.h>
  20
  21 static uint8_t                  ao_adc_ready;
  22
  23 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  24                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  25                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  26                                  (0 << STM_ADC_CR2_JWSTART) |           \
  27                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  28                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  29                                  (0 << STM_ADC_CR2_ALIGN) |             \
  30                                  (0 << STM_ADC_CR2_EOCS) |              \
  31                                  (1 << STM_ADC_CR2_DDS) |               \
  32                                  (1 << STM_ADC_CR2_DMA) |               \
  33                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  34                                  (0 << STM_ADC_CR2_CONT) |              \
  35                                  (1 << STM_ADC_CR2_ADON))
  36
  37 /*
  38  * Callback from DMA ISR
  39  *
  40  * Mark time in ring, shut down DMA engine
  41  */
  42 static void ao_adc_done(int index)
  43 {
  44         (void) index;
  45         AO_DATA_PRESENT(AO_DATA_ADC);
  46         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  47         if (ao_data_present == AO_DATA_ALL) {
  48 #if HAS_MS5607
  49                 ao_data_ring[ao_data_head].ms5607_raw = ao_ms5607_current;
  50 #endif
  51 #if HAS_MMA655X
  52                 ao_data_ring[ao_data_head].mma655x = ao_mma655x_current;
  53 #endif
  54 #if HAS_HMC5883
  55                 ao_data_ring[ao_data_head].hmc5883 = ao_hmc5883_current;
  56 #endif
  57 #if HAS_MPU6000
  58                 ao_data_ring[ao_data_head].mpu6000 = ao_mpu6000_current;
  59 #endif
  60                 ao_data_ring[ao_data_head].tick = ao_tick_count;
  61                 ao_data_head = ao_data_ring_next(ao_data_head);
  62                 ao_wakeup((void *) &ao_data_head);
  63         }
  64         ao_adc_ready = 1;
  65 }
  66
  67 /*
  68  * Start the ADC sequence using the DMA engine
  69  */
  70 void
  71 ao_adc_poll(void)
  72 {
  73         if (!ao_adc_ready)
  74                 return;
  75         ao_adc_ready = 0;
  76         stm_adc.sr = 0;
  77         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  78                             &stm_adc.dr,
  79                             (void *) (&ao_data_ring[ao_data_head].adc),
  80                             AO_NUM_ADC,
  81                             (0 << STM_DMA_CCR_MEM2MEM) |
  82                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  83                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  84                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  85                             (1 << STM_DMA_CCR_MINC) |
  86                             (0 << STM_DMA_CCR_PINC) |
  87                             (0 << STM_DMA_CCR_CIRC) |
  88                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  89         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  90         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  91
  92         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  93 }
  94
  95 /*
  96  * Fetch a copy of the most recent ADC data
  97  */
  98 void
  99 ao_adc_get(__xdata struct ao_adc *packet)
 100 {
 101 #if HAS_FLIGHT
 102         uint8_t i = ao_data_ring_prev(ao_sample_data);
 103 #else
 104         uint8_t i = ao_data_ring_prev(ao_data_head);
 105 #endif
 106         memcpy(packet, (void *) &ao_data_ring[i].adc, sizeof (struct ao_adc));
 107 }
 108
 109 static void
 110 ao_adc_dump(void) __reentrant
 111 {
 112         struct ao_data  packet;
 113 #ifndef AO_ADC_DUMP
 114         uint8_t i;
 115         int16_t *d;
 116 #endif
 117
 118         ao_data_get(&packet);
 119 #ifdef AO_ADC_DUMP
 120         AO_ADC_DUMP(&packet);
 121 #else
 122         printf("tick: %5u",  packet.tick);
 123         d = (int16_t *) (&packet.adc);
 124         for (i = 0; i < AO_NUM_ADC; i++)
 125                 printf (" %2d: %5d", i, d[i]);
 126         printf("\n");
 127 #endif
 128 }
 129
 130 __code struct ao_cmds ao_adc_cmds[] = {
 131         { ao_adc_dump,  "a\0Display current ADC values" },
 132         { 0, NULL },
 133 };
 134
 135 void
 136 ao_adc_init(void)
 137 {
 138 #ifdef AO_ADC_PIN0_PORT
 139         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 140 #endif
 141
 142 #ifdef AO_ADC_PIN0_PORT
 143         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 144 #endif
 145 #ifdef AO_ADC_PIN1_PORT
 146         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 147 #endif
 148 #ifdef AO_ADC_PIN2_PORT
 149         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 150 #endif
 151 #ifdef AO_ADC_PIN3_PORT
 152         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 153 #endif
 154 #ifdef AO_ADC_PIN4_PORT
 155         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 156 #endif
 157 #ifdef AO_ADC_PIN5_PORT
 158         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 159 #endif
 160 #ifdef AO_ADC_PIN6_PORT
 161         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 162 #endif
 163 #ifdef AO_ADC_PIN7_PORT
 164         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 165 #endif
 166 #ifdef AO_ADC_PIN8_PORT
 167         stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 168 #endif
 169 #ifdef AO_ADC_PIN9_PORT
 170         stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 171 #endif
 172 #ifdef AO_ADC_PIN10_PORT
 173         stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
 174 #endif
 175 #ifdef AO_ADC_PIN11_PORT
 176         stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
 177 #endif
 178 #ifdef AO_ADC_PIN12_PORT
 179         stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
 180 #endif
 181
 182         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 183
 184         /* Turn off ADC during configuration */
 185         stm_adc.cr2 = 0;
 186
 187         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 188                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 189                        (0 << STM_ADC_CR1_AWDEN ) |
 190                        (0 << STM_ADC_CR1_JAWDEN ) |
 191                        (0 << STM_ADC_CR1_PDI ) |
 192                        (0 << STM_ADC_CR1_PDD ) |
 193                        (0 << STM_ADC_CR1_DISCNUM ) |
 194                        (0 << STM_ADC_CR1_JDISCEN ) |
 195                        (0 << STM_ADC_CR1_DISCEN ) |
 196                        (0 << STM_ADC_CR1_JAUTO ) |
 197                        (0 << STM_ADC_CR1_AWDSGL ) |
 198                        (1 << STM_ADC_CR1_SCAN ) |
 199                        (0 << STM_ADC_CR1_JEOCIE ) |
 200                        (0 << STM_ADC_CR1_AWDIE ) |
 201                        (0 << STM_ADC_CR1_EOCIE ) |
 202                        (0 << STM_ADC_CR1_AWDCH ));
 203
 204         /* 384 cycle sample time for everyone */
 205         stm_adc.smpr1 = 0x3ffff;
 206         stm_adc.smpr2 = 0x3fffffff;
 207         stm_adc.smpr3 = 0x3fffffff;
 208
 209         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 210         stm_adc.sqr2 = 0;
 211         stm_adc.sqr3 = 0;
 212         stm_adc.sqr4 = 0;
 213         stm_adc.sqr5 = 0;
 214 #if AO_NUM_ADC > 0
 215         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 216 #endif
 217 #if AO_NUM_ADC > 1
 218         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 219 #endif
 220 #if AO_NUM_ADC > 2
 221         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 222 #endif
 223 #if AO_NUM_ADC > 3
 224         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 225 #endif
 226 #if AO_NUM_ADC > 4
 227         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 228 #endif
 229 #if AO_NUM_ADC > 5
 230         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 231 #endif
 232 #if AO_NUM_ADC > 6
 233         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 234 #endif
 235 #if AO_NUM_ADC > 7
 236         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 237 #endif
 238 #if AO_NUM_ADC > 8
 239         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 240 #endif
 241 #if AO_NUM_ADC > 9
 242         stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
 243 #endif
 244 #if AO_NUM_ADC > 10
 245         stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
 246 #endif
 247 #if AO_NUM_ADC > 11
 248         stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
 249 #endif
 250 #if AO_NUM_ADC > 12
 251 #error "need to finish stm_adc.sqr settings"
 252 #endif
 253
 254         /* Turn ADC on */
 255         stm_adc.cr2 = AO_ADC_CR2_VAL;
 256
 257         /* Wait for ADC to be ready */
 258         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 259                 ;
 260
 261 #if HAS_ADC_TEMP
 262         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 263 #else
 264         stm_adc.ccr = 0;
 265 #endif
 266         /* Clear any stale status bits */
 267         stm_adc.sr = 0;
 268
 269         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 270
 271         ao_cmd_register(&ao_adc_cmds[0]);
 272
 273         ao_adc_ready = 1;
 274 }