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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20 #include <ao_data.h>
  21
  22 static uint8_t                  ao_adc_ready;
  23
  24 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  25                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  26                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  27                                  (0 << STM_ADC_CR2_JWSTART) |           \
  28                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  29                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  30                                  (0 << STM_ADC_CR2_ALIGN) |             \
  31                                  (0 << STM_ADC_CR2_EOCS) |              \
  32                                  (1 << STM_ADC_CR2_DDS) |               \
  33                                  (1 << STM_ADC_CR2_DMA) |               \
  34                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  35                                  (0 << STM_ADC_CR2_CONT) |              \
  36                                  (1 << STM_ADC_CR2_ADON))
  37
  38 /*
  39  * Callback from DMA ISR
  40  *
  41  * Mark time in ring, shut down DMA engine
  42  */
  43 static void ao_adc_done(int index)
  44 {
  45         (void) index;
  46         AO_DATA_PRESENT(AO_DATA_ADC);
  47         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  48         if (ao_data_present == AO_DATA_ALL) {
  49 #if HAS_MS5607
  50                 ao_data_ring[ao_data_head].ms5607_raw = ao_ms5607_current;
  51 #endif
  52 #if HAS_MMA655X
  53                 ao_data_ring[ao_data_head].mma655x = ao_mma655x_current;
  54 #endif
  55 #if HAS_HMC5883
  56                 ao_data_ring[ao_data_head].hmc5883 = ao_hmc5883_current;
  57 #endif
  58 #if HAS_MPU6000
  59                 ao_data_ring[ao_data_head].mpu6000 = ao_mpu6000_current;
  60 #endif
  61 #if HAS_MPU9250
  62                 ao_data_ring[ao_data_head].mpu9250 = ao_mpu9250_current;
  63 #endif
  64                 ao_data_ring[ao_data_head].tick = ao_tick_count;
  65                 ao_data_head = ao_data_ring_next(ao_data_head);
  66                 ao_wakeup((void *) &ao_data_head);
  67         }
  68         ao_adc_ready = 1;
  69 }
  70
  71 /*
  72  * Start the ADC sequence using the DMA engine
  73  */
  74 void
  75 ao_adc_poll(void)
  76 {
  77         if (!ao_adc_ready)
  78                 return;
  79         ao_adc_ready = 0;
  80         stm_adc.sr = 0;
  81         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  82                             &stm_adc.dr,
  83                             (void *) (&ao_data_ring[ao_data_head].adc),
  84                             AO_NUM_ADC,
  85                             (0 << STM_DMA_CCR_MEM2MEM) |
  86                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  87                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  88                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  89                             (1 << STM_DMA_CCR_MINC) |
  90                             (0 << STM_DMA_CCR_PINC) |
  91                             (0 << STM_DMA_CCR_CIRC) |
  92                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  93         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  94         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  95
  96         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  97 }
  98
  99 /*
 100  * Fetch a copy of the most recent ADC data
 101  */
 102 void
 103 ao_adc_get(struct ao_adc *packet)
 104 {
 105 #if HAS_FLIGHT
 106         uint8_t i = ao_data_ring_prev(ao_sample_data);
 107 #else
 108         uint8_t i = ao_data_ring_prev(ao_data_head);
 109 #endif
 110         memcpy(packet, (void *) &ao_data_ring[i].adc, sizeof (struct ao_adc));
 111 }
 112
 113 #ifdef AO_ADC_SQ1_NAME
 114 static const char *ao_adc_name[AO_NUM_ADC] = {
 115         AO_ADC_SQ1_NAME,
 116 #ifdef AO_ADC_SQ2_NAME
 117         AO_ADC_SQ2_NAME,
 118 #endif
 119 #ifdef AO_ADC_SQ3_NAME
 120         AO_ADC_SQ3_NAME,
 121 #endif
 122 #ifdef AO_ADC_SQ4_NAME
 123         AO_ADC_SQ4_NAME,
 124 #endif
 125 #ifdef AO_ADC_SQ5_NAME
 126         AO_ADC_SQ5_NAME,
 127 #endif
 128 #ifdef AO_ADC_SQ6_NAME
 129         AO_ADC_SQ6_NAME,
 130 #endif
 131 #ifdef AO_ADC_SQ7_NAME
 132         AO_ADC_SQ7_NAME,
 133 #endif
 134 #ifdef AO_ADC_SQ8_NAME
 135         AO_ADC_SQ8_NAME,
 136 #endif
 137 #ifdef AO_ADC_SQ9_NAME
 138         AO_ADC_SQ9_NAME,
 139 #endif
 140 #ifdef AO_ADC_SQ10_NAME
 141         AO_ADC_SQ10_NAME,
 142 #endif
 143 #ifdef AO_ADC_SQ11_NAME
 144         AO_ADC_SQ11_NAME,
 145 #endif
 146 #ifdef AO_ADC_SQ12_NAME
 147         AO_ADC_SQ12_NAME,
 148 #endif
 149 #ifdef AO_ADC_SQ13_NAME
 150         AO_ADC_SQ13_NAME,
 151 #endif
 152 #ifdef AO_ADC_SQ14_NAME
 153         AO_ADC_SQ14_NAME,
 154 #endif
 155 #ifdef AO_ADC_SQ15_NAME
 156         AO_ADC_SQ15_NAME,
 157 #endif
 158 #ifdef AO_ADC_SQ16_NAME
 159         AO_ADC_SQ16_NAME,
 160 #endif
 161 #ifdef AO_ADC_SQ17_NAME
 162         AO_ADC_SQ17_NAME,
 163 #endif
 164 #ifdef AO_ADC_SQ18_NAME
 165         AO_ADC_SQ18_NAME,
 166 #endif
 167 #ifdef AO_ADC_SQ19_NAME
 168         AO_ADC_SQ19_NAME,
 169 #endif
 170 #ifdef AO_ADC_SQ20_NAME
 171         AO_ADC_SQ20_NAME,
 172 #endif
 173 #ifdef AO_ADC_SQ21_NAME
 174         #error "too many ADC names"
 175 #endif
 176 };
 177 #endif
 178
 179 static void
 180 ao_adc_dump(void)
 181 {
 182         struct ao_data  packet;
 183 #ifndef AO_ADC_DUMP
 184         uint8_t i;
 185         int16_t *d;
 186 #endif
 187
 188         ao_data_get(&packet);
 189 #ifdef AO_ADC_DUMP
 190         AO_ADC_DUMP(&packet);
 191 #else
 192         printf("tick: %5u",  packet.tick);
 193         d = (int16_t *) (&packet.adc);
 194         for (i = 0; i < AO_NUM_ADC; i++) {
 195 #ifdef AO_ADC_SQ1_NAME
 196                 if (ao_adc_name[i])
 197                         printf (" %s: %5d", ao_adc_name[i], d[i]);
 198                 else
 199 #endif
 200                         printf (" %2d: %5d", i, d[i]);
 201         }
 202         printf("\n");
 203 #endif
 204 }
 205
 206 const struct ao_cmds ao_adc_cmds[] = {
 207         { ao_adc_dump,  "a\0Display current ADC values" },
 208         { 0, NULL },
 209 };
 210
 211 void
 212 ao_adc_init(void)
 213 {
 214 #ifdef AO_ADC_PIN0_PORT
 215         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 216 #endif
 217
 218 #ifdef AO_ADC_PIN0_PORT
 219         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 220 #endif
 221 #ifdef AO_ADC_PIN1_PORT
 222         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 223 #endif
 224 #ifdef AO_ADC_PIN2_PORT
 225         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 226 #endif
 227 #ifdef AO_ADC_PIN3_PORT
 228         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 229 #endif
 230 #ifdef AO_ADC_PIN4_PORT
 231         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 232 #endif
 233 #ifdef AO_ADC_PIN5_PORT
 234         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 235 #endif
 236 #ifdef AO_ADC_PIN6_PORT
 237         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 238 #endif
 239 #ifdef AO_ADC_PIN7_PORT
 240         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 241 #endif
 242 #ifdef AO_ADC_PIN8_PORT
 243         stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 244 #endif
 245 #ifdef AO_ADC_PIN9_PORT
 246         stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 247 #endif
 248 #ifdef AO_ADC_PIN10_PORT
 249         stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
 250 #endif
 251 #ifdef AO_ADC_PIN11_PORT
 252         stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
 253 #endif
 254 #ifdef AO_ADC_PIN12_PORT
 255         stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
 256 #endif
 257 #ifdef AO_ADC_PIN13_PORT
 258         stm_moder_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN, STM_MODER_ANALOG);
 259 #endif
 260 #ifdef AO_ADC_PIN14_PORT
 261         stm_moder_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN, STM_MODER_ANALOG);
 262 #endif
 263 #ifdef AO_ADC_PIN15_PORT
 264         stm_moder_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN, STM_MODER_ANALOG);
 265 #endif
 266 #ifdef AO_ADC_PIN16_PORT
 267         stm_moder_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN, STM_MODER_ANALOG);
 268 #endif
 269 #ifdef AO_ADC_PIN17_PORT
 270         stm_moder_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN, STM_MODER_ANALOG);
 271 #endif
 272 #ifdef AO_ADC_PIN18_PORT
 273         stm_moder_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN, STM_MODER_ANALOG);
 274 #endif
 275 #ifdef AO_ADC_PIN19_PORT
 276         stm_moder_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN, STM_MODER_ANALOG);
 277 #endif
 278 #ifdef AO_ADC_PIN20_PORT
 279         stm_moder_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN, STM_MODER_ANALOG);
 280 #endif
 281 #ifdef AO_ADC_PIN21_PORT
 282         stm_moder_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN, STM_MODER_ANALOG);
 283 #endif
 284 #ifdef AO_ADC_PIN22_PORT
 285         stm_moder_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN, STM_MODER_ANALOG);
 286 #endif
 287 #ifdef AO_ADC_PIN23_PORT
 288         stm_moder_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN, STM_MODER_ANALOG);
 289 #endif
 290 #ifdef AO_ADC_PIN24_PORT
 291         #error "Too many ADC ports"
 292 #endif
 293
 294         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 295
 296         /* Turn off ADC during configuration */
 297         stm_adc.cr2 = 0;
 298
 299         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 300                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 301                        (0 << STM_ADC_CR1_AWDEN ) |
 302                        (0 << STM_ADC_CR1_JAWDEN ) |
 303                        (0 << STM_ADC_CR1_PDI ) |
 304                        (0 << STM_ADC_CR1_PDD ) |
 305                        (0 << STM_ADC_CR1_DISCNUM ) |
 306                        (0 << STM_ADC_CR1_JDISCEN ) |
 307                        (0 << STM_ADC_CR1_DISCEN ) |
 308                        (0 << STM_ADC_CR1_JAUTO ) |
 309                        (0 << STM_ADC_CR1_AWDSGL ) |
 310                        (1 << STM_ADC_CR1_SCAN ) |
 311                        (0 << STM_ADC_CR1_JEOCIE ) |
 312                        (0 << STM_ADC_CR1_AWDIE ) |
 313                        (0 << STM_ADC_CR1_EOCIE ) |
 314                        (0 << STM_ADC_CR1_AWDCH ));
 315
 316         /* 384 cycle sample time for everyone */
 317         stm_adc.smpr1 = 0x3ffff;
 318         stm_adc.smpr2 = 0x3fffffff;
 319         stm_adc.smpr3 = 0x3fffffff;
 320
 321         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 322         stm_adc.sqr2 = 0;
 323         stm_adc.sqr3 = 0;
 324         stm_adc.sqr4 = 0;
 325         stm_adc.sqr5 = 0;
 326 #if AO_NUM_ADC > 0
 327         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 328 #endif
 329 #if AO_NUM_ADC > 1
 330         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 331 #endif
 332 #if AO_NUM_ADC > 2
 333         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 334 #endif
 335 #if AO_NUM_ADC > 3
 336         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 337 #endif
 338 #if AO_NUM_ADC > 4
 339         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 340 #endif
 341 #if AO_NUM_ADC > 5
 342         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 343 #endif
 344 #if AO_NUM_ADC > 6
 345         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 346 #endif
 347 #if AO_NUM_ADC > 7
 348         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 349 #endif
 350 #if AO_NUM_ADC > 8
 351         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 352 #endif
 353 #if AO_NUM_ADC > 9
 354         stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
 355 #endif
 356 #if AO_NUM_ADC > 10
 357         stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
 358 #endif
 359 #if AO_NUM_ADC > 11
 360         stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
 361 #endif
 362 #if AO_NUM_ADC > 12
 363         stm_adc.sqr3 |= (AO_ADC_SQ13 << 0);
 364 #endif
 365 #if AO_NUM_ADC > 13
 366         stm_adc.sqr3 |= (AO_ADC_SQ14 << 5);
 367 #endif
 368 #if AO_NUM_ADC > 14
 369         stm_adc.sqr3 |= (AO_ADC_SQ15 << 10);
 370 #endif
 371 #if AO_NUM_ADC > 15
 372         stm_adc.sqr3 |= (AO_ADC_SQ16 << 15);
 373 #endif
 374 #if AO_NUM_ADC > 16
 375         stm_adc.sqr3 |= (AO_ADC_SQ17 << 20);
 376 #endif
 377 #if AO_NUM_ADC > 17
 378         stm_adc.sqr3 |= (AO_ADC_SQ18 << 25);
 379 #endif
 380 #if AO_NUM_ADC > 18
 381 #error "need to finish stm_adc.sqr settings"
 382 #endif
 383
 384         /* Turn ADC on */
 385         stm_adc.cr2 = AO_ADC_CR2_VAL;
 386
 387         /* Wait for ADC to be ready */
 388         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 389                 ;
 390
 391 #ifndef HAS_ADC_TEMP
 392 #error Please define HAS_ADC_TEMP
 393 #endif
 394 #if HAS_ADC_TEMP
 395         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 396 #else
 397         stm_adc.ccr = 0;
 398 #endif
 399         /* Clear any stale status bits */
 400         stm_adc.sr = 0;
 401
 402         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 403
 404         ao_cmd_register(&ao_adc_cmds[0]);
 405
 406         ao_adc_ready = 1;
 407 }