2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #define HAS_TASK_QUEUE 1
23 /* 8MHz High speed external crystal */
24 #define AO_HSE 8000000
26 /* PLLVCO = 96MHz (so that USB will work) */
28 #define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
30 /* SYSCLK = 32MHz (no need to go faster than CPU) */
32 #define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
34 /* HCLK = 32MHz (CPU clock) */
35 #define AO_AHB_PRESCALER 1
36 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
38 /* Run APB1 at 16MHz (HCLK/2) */
39 #define AO_APB1_PRESCALER 2
40 #define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2
42 /* Run APB2 at 16MHz (HCLK/2) */
43 #define AO_APB2_PRESCALER 2
44 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2
46 #define HAS_SERIAL_1 1
47 #define USE_SERIAL_1_STDIN 0
48 #define SERIAL_1_PB6_PB7 0
49 #define SERIAL_1_PA9_PA10 1
51 #define HAS_SERIAL_2 0
52 #define USE_SERIAL_2_STDIN 0
53 #define SERIAL_2_PA2_PA3 0
54 #define SERIAL_2_PD5_PD6 0
56 #define HAS_SERIAL_3 0
57 #define USE_SERIAL_3_STDIN 0
58 #define SERIAL_3_PB10_PB11 0
59 #define SERIAL_3_PC10_PC11 1
60 #define SERIAL_3_PD8_PD9 0
63 #define USE_INTERNAL_FLASH 0
67 #define HAS_TELEMETRY 0
70 #define SPI_1_PA5_PA6_PA7 0
71 #define SPI_1_PB3_PB4_PB5 0
72 #define SPI_1_PE13_PE14_PE15 1 /* */
75 #define SPI_2_PB13_PB14_PB15 1 /* */
76 #define SPI_2_PD1_PD3_PD4 0
78 #define SPI_2_PORT (&stm_gpiob)
79 #define SPI_2_SCK_PIN 13
80 #define SPI_2_MISO_PIN 14
81 #define SPI_2_MOSI_PIN 15
84 #define I2C_1_PB6_PB7 1
85 #define I2C_1_PB8_PB9 0
88 #define I2C_2_PB10_PB11 1
90 #define PACKET_HAS_SLAVE 0
91 #define PACKET_HAS_MASTER 0
93 #define LOW_LEVEL_DEBUG 0
95 #define LED_PORT_0_ENABLE STM_RCC_AHBENR_GPIOCEN
96 #define LED_PORT_0 (&stm_gpioc)
97 #define LED_PORT_0_MASK (0xff)
98 #define LED_PORT_0_SHIFT 0
100 #define LED_PIN_GREEN 7
101 #define LED_PIN_RED_2 8
102 #define LED_PIN_GREEN_2 9
103 #define AO_LED_RED (1 << LED_PIN_RED)
104 #define AO_LED_GREEN (1 << LED_PIN_GREEN)
105 #define AO_LED_RED_2 (1 << LED_PIN_RED_2)
106 #define AO_LED_GREEN_2 (1 << LED_PIN_GREEN_2)
108 #define LEDS_AVAILABLE (AO_LED_RED | AO_LED_GREEN | AO_LED_RED_2 | AO_LED_GREEN_2)
118 #define AO_DATA_RING 32
119 #define AO_ADC_NUM_SENSE 6
122 int16_t tx_pa_current; /* ADC_IN0 */
123 int16_t tx_pa_temp; /* ADC_IN1 */
124 int16_t tx_xo_temp; /* ADC_IN2 */
125 int16_t rx_xo_temp; /* ADC_IN3 */
126 int16_t ihu_current; /* ADC_IN8 */
127 int16_t rx_cd; /* ADC_IN9 */
128 int16_t ant_sense_1; /* ADC_IN10 */
129 int16_t ant_sense_2; /* ADC_IN11 */
132 #define AO_ADC_TX_PA_CURRENT 0
133 #define AO_ADC_TX_PA_CURRENT_PORT (&stm_gpioa)
134 #define AO_ADC_TX_PA_CURRENT_PIN 0
136 #define AO_ADC_TX_PA_TEMP 1
137 #define AO_ADC_TX_PA_TEMP_PORT (&stm_gpioa)
138 #define AO_ADC_TX_PA_TEMP_PIN 1
140 #define AO_ADC_TX_XO_TEMP 2
141 #define AO_ADC_TX_XO_TEMP_PORT (&stm_gpioa)
142 #define AO_ADC_TX_XO_TEMP_PIN 2
144 #define AO_ADC_RX_XO_TEMP 3
145 #define AO_ADC_RX_XO_TEMP_PORT (&stm_gpioa)
146 #define AO_ADC_RX_XO_TEMP_PIN 3
148 #define AO_ADC_IHU_CURRENT 8
149 #define AO_ADC_IHU_CURRENT_PORT (&stm_gpiob)
150 #define AO_ADC_IHU_CURRENT_PIN 0
152 #define AO_ADC_RX_CD 9
153 #define AO_ADC_RX_CD_PORT (&stm_gpiob)
154 #define AO_ADC_RX_CD_PIN 1
156 #define AO_ADC_ANT_SENSE_1 10
157 #define AO_ADC_ANT_SENSE_1_PORT (&stm_gpioc)
158 #define AO_ADC_ANT_SENSE_1_PIN 0
160 #define AO_ADC_ANT_SENSE_2 11
161 #define AO_ADC_ANT_SENSE_2_PORT (&stm_gpioc)
162 #define AO_ADC_ANT_SENSE_2_PIN 1
164 #define AO_ADC_TEMP 16
166 #define AO_ADC_RCC_AHBENR ((1 << STM_RCC_AHBENR_GPIOAEN) | \
167 (1 << STM_RCC_AHBENR_GPIOBEN) | \
168 (1 << STM_RCC_AHBENR_GPIOCEN))
170 #define AO_NUM_ADC_PIN (9)
172 #define AO_ADC_PIN0_PORT AO_ADC_TX_PA_CURRENT_PORT
173 #define AO_ADC_PIN0_PIN AO_ADC_TX_PA_CURRENT_PIN
174 #define AO_ADC_PIN1_PORT AO_ADC_TX_PA_TEMP_PORT
175 #define AO_ADC_PIN1_PIN AO_ADC_TX_PA_TEMP_PIN
176 #define AO_ADC_PIN2_PORT AO_ADC_TX_XO_TEMP_PORT
177 #define AO_ADC_PIN2_PIN AO_ADC_TX_XO_TEMP_PIN
178 #define AO_ADC_PIN3_PORT AO_ADC_RX_XO_TEMP_PORT
179 #define AO_ADC_PIN3_PIN AO_ADC_RX_XO_TEMP_PIN
180 #define AO_ADC_PIN4_PORT AO_ADC_IHU_CURRENT_PORT
181 #define AO_ADC_PIN4_PIN AO_ADC_IHU_CURRENT_PIN
182 #define AO_ADC_PIN5_PORT AO_ADC_IHU_CURRENT_PORT
183 #define AO_ADC_PIN5_PIN AO_ADC_IHU_CURRENT_PIN
184 #define AO_ADC_PIN6_PORT AO_ADC_RX_CD_PORT
185 #define AO_ADC_PIN6_PIN AO_ADC_RX_CD_PIN
186 #define AO_ADC_PIN7_PORT AO_ADC_ANT_SENSE_1_PORT
187 #define AO_ADC_PIN7_PIN AO_ADC_ANT_SENSE_1_PIN
188 #define AO_ADC_PIN8_PORT AO_ADC_ANT_SENSE_2_PORT
189 #define AO_ADC_PIN8_PIN AO_ADC_ANT_SENSE_2_PIN
191 #define AO_NUM_ADC (AO_NUM_ADC_PIN + 1) /* Add internal temp sensor */
193 #define AO_ADC_SQ1 AO_ADC_TX_PA_CURRENT
194 #define AO_ADC_SQ2 AO_ADC_TX_PA_TEMP
195 #define AO_ADC_SQ3 AO_ADC_TX_XO_TEMP
196 #define AO_ADC_SQ4 AO_ADC_RX_XO_TEMP
197 #define AO_ADC_SQ5 AO_ADC_IHU_CURRENT
198 #define AO_ADC_SQ6 AO_ADC_IHU_CURRENT
199 #define AO_ADC_SQ7 AO_ADC_RX_CD
200 #define AO_ADC_SQ8 AO_ADC_ANT_SENSE_1
201 #define AO_ADC_SQ9 AO_ADC_ANT_SENSE_2
202 #define AO_ADC_SQ10 AO_ADC_TEMP
204 #endif /* _AO_PINS_H_ */