1 /***************************************************************
2 * SmartRF Studio(tm) Export
4 * Radio register settings specifed with address, value
8 ***************************************************************/
11 * Values affecting receive sensitivity:
14 * PQT - sets how good the preamble needs to look before
15 * we start looking for a sync word
16 * SYNC_THR - sets how good the sync needs to be before we
17 * start decoding a packet
20 /* Values depending on data rate
26 #ifndef AO_CC1200_AGC_GAIN_ADJUST
27 #define AO_CC1200_AGC_GAIN_ADJUST -81
30 CC1200_IOCFG2, 0x06, /* GPIO2 IO Pin Configuration */
31 CC1200_SYNC3, 0xD3, /* Sync Word Configuration [23:16] */
32 CC1200_SYNC2, 0x91, /* Sync Word Configuration [23:16] */
33 CC1200_SYNC1, 0xD3, /* Sync Word Configuration [15:8] */
34 CC1200_SYNC0, 0x91, /* Sync Word Configuration [7:0] */
35 CC1200_SYNC_CFG1, /* Sync Word Detection Configuration Reg. 1 */
36 ((CC1200_SYNC_CFG1_SYNC_MODE_16_BITS << CC1200_SYNC_CFG1_SYNC_MODE) |
37 (11 << CC1200_SYNC_CFG1_SYNC_THR)),
38 CC1200_SYNC_CFG0, /* Sync Word Detection Configuration Reg. 0 */
39 ((1 << CC1200_SYNC_CFG0_AUTO_CLEAR) |
40 (0 << CC1200_SYNC_CFG0_RX_CONFIG_LIMITATION) |
41 (1 << CC1200_SYNC_CFG0_PQT_GATING_EN) |
42 (0 << CC1200_SYNC_CFG0_EXT_SYNC_DETECT) |
43 (CC1200_SYNC_CFG0_SYNC_STRICT_SYNC_CHECK_DISABLED << CC1200_SYNC_CFG0_SYNC_STRICT_SYNC_CHECK)),
44 CC1200_DEVIATION_M, 0x50, /* Frequency Deviation Configuration */
45 CC1200_DCFILT_CFG, 0x5d, /* Digital DC Removal Configuration */
46 CC1200_PREAMBLE_CFG0, /* Preamble Detection Configuration Reg. 0 */
47 ((1 << CC1200_PREAMBLE_CFG0_PQT_EN) |
48 (CC1200_PREAMBLE_CFG0_PQT_VALID_TIMEOUT_11 << CC1200_PREAMBLE_CFG0_PQT_VALID_TIMEOUT) |
49 (15 << CC1200_PREAMBLE_CFG0_PQT)),
50 CC1200_IQIC, 0xcb, /* Digital Image Channel Compensation Configuration */
51 CC1200_CHAN_BW, 0x11, /* Channel Filter Configuration */
52 CC1200_MDMCFG1, 0x40, /* General Modem Parameter Configuration Reg. 1 */
53 CC1200_MDMCFG0, 0x05, /* General Modem Parameter Configuration Reg. 0 */
54 CC1200_SYMBOL_RATE2, 0x93, /* Symbol Rate Configuration Exponent and Mantissa [1.. */
55 CC1200_AGC_REF, 0x27, /* AGC Reference Level Configuration */
56 CC1200_AGC_CS_THR, 0xec, /* Carrier Sense Threshold Configuration */
57 CC1200_AGC_GAIN_ADJUST, /* RSSI adjustment */
58 AO_CC1200_AGC_GAIN_ADJUST,
59 CC1200_AGC_CFG1, 0x51, /* Automatic Gain Control Configuration Reg. 1 */
60 CC1200_AGC_CFG0, 0x87, /* Automatic Gain Control Configuration Reg. 0 */
61 CC1200_FIFO_CFG, 0x40, /* FIFO Configuration */
62 CC1200_SETTLING_CFG, /* Frequency Synthesizer Calibration and Settling Configuration */
63 ((CC1200_SETTLING_CFG_FS_AUTOCAL_EVERY_4TH_TIME << CC1200_SETTLING_CFG_FS_AUTOCAL) |
64 (CC1200_SETTLING_CFG_LOCK_TIME_75_30 << CC1200_SETTLING_CFG_LOCK_TIME) |
65 (CC1200_SETTLING_CFG_FSREG_TIME_60 << CC1200_SETTLING_CFG_FSREG_TIME)),
66 CC1200_FS_CFG, /* Frequency Synthesizer Configuration */
67 ((1 << CC1200_FS_CFG_LOCK_EN) |
68 (CC1200_FS_CFG_FSD_BANDSELECT_410_480 << CC1200_FS_CFG_FSD_BANDSELECT)),
69 CC1200_PKT_CFG2, /* Packet Configuration Reg. 2 */
70 ((0 << CC1200_PKT_CFG2_FG_MODE_EN) |
71 (CC1200_PKT_CFG2_CCA_MODE_ALWAYS_CLEAR << CC1200_PKT_CFG2_CCA_MODE) |
72 (CC1200_PKT_CFG2_PKT_FORMAT_NORMAL << CC1200_PKT_CFG2_PKT_FORMAT)),
73 CC1200_PKT_CFG1, /* Packet Configuration Reg. 1 */
74 ((1 << CC1200_PKT_CFG1_FEC_EN) |
75 (1 << CC1200_PKT_CFG1_WHITE_DATA) |
76 (0 << CC1200_PKT_CFG1_PN9_SWAP_EN) |
77 (CC1200_PKT_CFG1_ADDR_CHECK_CFG_NONE << CC1200_PKT_CFG1_ADDR_CHECK_CFG) |
78 (CC1200_PKT_CFG1_CRC_CFG_CRC16_INIT_ONES << CC1200_PKT_CFG1_CRC_CFG) |
79 (1 << CC1200_PKT_CFG1_APPEND_STATUS)),
80 CC1200_PKT_CFG0, /* Packet Configuration Reg. 0 */
81 ((CC1200_PKT_CFG0_LENGTH_CONFIG_FIXED << CC1200_PKT_CFG0_LENGTH_CONFIG) |
82 (0 << CC1200_PKT_CFG0_PKG_BIT_LEN) |
83 (0 << CC1200_PKT_CFG0_UART_MODE_EN) |
84 (0 << CC1200_PKT_CFG0_UART_SWAP_EN)),
85 CC1200_RFEND_CFG1, /* RFEND Configuration Reg. 1 */
86 ((CC1200_RFEND_CFG1_RXOFF_MODE_IDLE << CC1200_RFEND_CFG1_RXOFF_MODE) |
87 (CC1200_RFEND_CFG1_RX_TIME_INFINITE << CC1200_RFEND_CFG1_RX_TIME) |
88 (0 << CC1200_RFEND_CFG1_RX_TIME_QUAL)),
89 CC1200_RFEND_CFG0, /* RFEND Configuration Reg. 0 */
90 ((0 << CC1200_RFEND_CFG0_CAL_END_WAKE_UP_EN) |
91 (CC1200_RFEND_CFG0_TXOFF_MODE_IDLE << CC1200_RFEND_CFG0_TXOFF_MODE) |
92 (1 << CC1200_RFEND_CFG0_TERM_ON_BAD_PACKET_EN) |
93 (0 << CC1200_RFEND_CFG0_ANT_DIV_RX_TERM_CFG)),
94 CC1200_PA_CFG1, 0x3f, /* Power Amplifier Configuration Reg. 1 */
95 CC1200_PA_CFG0, 0x53, /* Power Amplifier Configuration Reg. 0 */
96 CC1200_PKT_LEN, 0xff, /* Packet Length Configuration */
97 CC1200_IF_MIX_CFG, 0x1c, /* IF Mix Configuration */
98 CC1200_FREQOFF_CFG, 0x22, /* Frequency Offset Correction Configuration */
99 CC1200_MDMCFG2, /* General Modem Parameter Configuration Reg. 2 */
100 ((CC1200_MDMCFG2_ASK_SHAPE_8 << CC1200_MDMCFG2_ASK_SHAPE) |
101 (CC1200_MDMCFG2_SYMBOL_MAP_CFG_MODE_0 << CC1200_MDMCFG2_SYMBOL_MAP_CFG) |
102 (CC1200_MDMCFG2_UPSAMPLER_P_8 << CC1200_MDMCFG2_UPSAMPLER_P) |
103 (0 << CC1200_MDMCFG2_CFM_DATA_EN)),
104 CC1200_FREQ2, 0x6c, /* Frequency Configuration [23:16] */
105 CC1200_FREQ1, 0xa3, /* Frequency Configuration [15:8] */
106 CC1200_FREQ0, 0x33, /* Frequency Configuration [7:0] */
107 CC1200_IF_ADC1, 0xee, /* Analog to Digital Converter Configuration Reg. 1 */
108 CC1200_IF_ADC0, 0x10, /* Analog to Digital Converter Configuration Reg. 0 */
109 CC1200_FS_DIG1, 0x07, /* Frequency Synthesizer Digital Reg. 1 */
110 CC1200_FS_DIG0, 0xaf, /* Frequency Synthesizer Digital Reg. 0 */
111 CC1200_FS_CAL1, 0x40, /* Frequency Synthesizer Calibration Reg. 1 */
112 CC1200_FS_CAL0, 0x0e, /* Frequency Synthesizer Calibration Reg. 0 */
113 CC1200_FS_DIVTWO, 0x03, /* Frequency Synthesizer Divide by 2 */
114 CC1200_FS_DSM0, 0x33, /* FS Digital Synthesizer Module Configuration Reg. 0 */
115 CC1200_FS_DVC0, 0x17, /* Frequency Synthesizer Divider Chain Configuration .. */
116 CC1200_FS_PFD, 0x00, /* Frequency Synthesizer Phase Frequency Detector Con.. */
117 CC1200_FS_PRE, 0x6e, /* Frequency Synthesizer Prescaler Configuration */
118 CC1200_FS_REG_DIV_CML, 0x1c, /* Frequency Synthesizer Divider Regulator Configurat.. */
119 CC1200_FS_SPARE, 0xac, /* Frequency Synthesizer Spare */
120 CC1200_FS_VCO0, 0xb5, /* FS Voltage Controlled Oscillator Configuration Reg.. */
121 CC1200_XOSC5, 0x0e, /* Crystal Oscillator Configuration Reg. 5 */
122 CC1200_XOSC1, 0x03, /* Crystal Oscillator Configuration Reg. 1 */
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