2 * Copyright © 2009 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #include "at45db161d.h"
22 * Using SPI on USART 0, with P1_1 as the chip select
26 #define FLASH_CS_INDEX 1
28 __xdata uint8_t ao_flash_dma_in_done;
29 __xdata uint8_t ao_flash_dma_out_done;
30 __xdata uint8_t ao_flash_mutex;
32 uint8_t ao_flash_dma_out_id;
33 uint8_t ao_flash_dma_in_id;
35 static __xdata uint8_t ao_flash_const = 0xff;
37 #define ao_flash_delay() do { \
43 void ao_flash_cs_low(void)
50 void ao_flash_cs_high(void)
57 /* Send bytes over SPI.
59 * This sets up two DMA engines, one writing the data and another reading
60 * bytes coming back. We use the bytes coming back to tell when the transfer
61 * is complete, as the transmit register is double buffered and hence signals
62 * completion one byte before the transfer is actually complete
65 ao_flash_send(void __xdata *block, uint16_t len)
67 ao_dma_set_transfer(ao_flash_dma_in_id,
72 DMA_CFG0_TMODE_SINGLE |
73 DMA_CFG0_TRIGGER_URX0,
76 DMA_CFG1_PRIORITY_NORMAL);
78 ao_dma_set_transfer(ao_flash_dma_out_id,
83 DMA_CFG0_TMODE_SINGLE |
84 DMA_CFG0_TRIGGER_UTX0,
87 DMA_CFG1_PRIORITY_NORMAL);
89 ao_dma_start(ao_flash_dma_in_id);
90 ao_dma_start(ao_flash_dma_out_id);
91 ao_dma_trigger(ao_flash_dma_out_id);
92 __critical while (!ao_flash_dma_in_done)
93 ao_sleep(&ao_flash_dma_in_done);
96 /* Receive bytes over SPI.
98 * This sets up tow DMA engines, one reading the data and another
99 * writing constant values to the SPI transmitter as that is what
100 * clocks the data coming in.
103 ao_flash_recv(void __xdata *block, uint16_t len)
105 ao_dma_set_transfer(ao_flash_dma_in_id,
109 DMA_CFG0_WORDSIZE_8 |
110 DMA_CFG0_TMODE_SINGLE |
111 DMA_CFG0_TRIGGER_URX0,
114 DMA_CFG1_PRIORITY_NORMAL);
116 ao_dma_set_transfer(ao_flash_dma_out_id,
120 DMA_CFG0_WORDSIZE_8 |
121 DMA_CFG0_TMODE_SINGLE |
122 DMA_CFG0_TRIGGER_UTX0,
125 DMA_CFG1_PRIORITY_NORMAL);
127 ao_dma_start(ao_flash_dma_in_id);
128 ao_dma_start(ao_flash_dma_out_id);
129 ao_dma_trigger(ao_flash_dma_out_id);
130 __critical while (!ao_flash_dma_in_done)
131 ao_sleep(&ao_flash_dma_in_done);
134 struct ao_flash_instruction {
137 } __xdata ao_flash_instruction;
140 ao_flash_set_pagesize_512(void)
143 ao_flash_instruction.instruction = FLASH_SET_CONFIG;
144 ao_flash_instruction.address[0] = FLASH_SET_512_BYTE_0;
145 ao_flash_instruction.address[1] = FLASH_SET_512_BYTE_1;
146 ao_flash_instruction.address[2] = FLASH_SET_512_BYTE_2;
147 ao_flash_send(&ao_flash_instruction, 4);
153 ao_flash_read_status(void)
156 ao_flash_instruction.instruction = FLASH_READ_STATUS;
157 ao_flash_send(&ao_flash_instruction, 1);
158 ao_flash_recv(&ao_flash_instruction, 1);
160 return ao_flash_instruction.instruction;
163 #define FLASH_BLOCK_NONE 0xffff
165 static __xdata uint8_t ao_flash_data[FLASH_BLOCK_SIZE_MAX];
166 static __pdata uint16_t ao_flash_block = FLASH_BLOCK_NONE;
167 static __pdata uint8_t ao_flash_block_dirty;
168 static __pdata uint8_t ao_flash_write_pending;
169 static __pdata uint8_t ao_flash_setup_done;
170 static __data uint32_t ao_flash_device_size;
171 static __data uint8_t ao_flash_block_shift;
178 if (ao_flash_setup_done)
181 ao_mutex_get(&ao_flash_mutex);
182 if (ao_flash_setup_done) {
183 ao_mutex_put(&ao_flash_mutex);
186 ao_flash_setup_done = 1;
188 /* On first use, check to see if the flash chip has
189 * been programmed to use 512 byte pages. If not, do so.
190 * And then, because the flash part must be power cycled
191 * for that change to take effect, panic.
193 status = ao_flash_read_status();
195 if (!(status & FLASH_STATUS_PAGESIZE_512)) {
196 ao_flash_set_pagesize_512();
197 ao_panic(AO_PANIC_FLASH);
200 switch (status & 0x3c) {
204 ao_flash_block_shift = 9;
205 ao_flash_device_size = ((uint32_t) 4 * (uint32_t) 1024 * (uint32_t) 1024);
210 ao_flash_block_shift = 9;
211 ao_flash_device_size = ((uint32_t) 2 * (uint32_t) 1024 * (uint32_t) 1024);
216 ao_flash_block_shift = 8;
217 ao_flash_device_size = ((uint32_t) 1024 * (uint32_t) 1024);
222 ao_flash_block_shift = 8;
223 ao_flash_device_size = ((uint32_t) 512 * (uint32_t) 1024);
228 ao_flash_block_shift = 8;
229 ao_flash_device_size = ((uint32_t) 256 * (uint32_t) 1024);
234 ao_flash_block_shift = 8;
235 ao_flash_device_size = ((uint32_t) 128 * (uint32_t) 1024);
239 ao_panic(AO_PANIC_FLASH);
241 ao_mutex_put(&ao_flash_mutex);
245 ao_flash_wait_write(void)
247 if (ao_flash_write_pending) {
249 uint8_t status = ao_flash_read_status();
250 if ((status & FLASH_STATUS_RDY))
253 ao_flash_write_pending = 0;
257 /* Write the current block to the FLASHPROM */
259 ao_flash_write_block(void)
261 ao_flash_wait_write();
263 ao_flash_instruction.instruction = FLASH_WRITE;
265 /* 13/14 block bits + 9/8 byte bits (always 0) */
266 ao_flash_instruction.address[0] = ao_flash_block >> (16 - ao_flash_block_shift);
267 ao_flash_instruction.address[1] = ao_flash_block << (ao_flash_block_shift - 8);
268 ao_flash_instruction.address[2] = 0;
269 ao_flash_send(&ao_flash_instruction, 4);
270 ao_flash_send(ao_flash_data, FLASH_BLOCK_SIZE);
272 ao_flash_write_pending = 1;
275 /* Read the current block from the FLASHPROM */
277 ao_flash_read_block(void)
279 ao_flash_wait_write();
281 ao_flash_instruction.instruction = FLASH_READ;
283 /* 13/14 block bits + 9/8 byte bits (always 0) */
284 ao_flash_instruction.address[0] = ao_flash_block >> (16 - ao_flash_block_shift);
285 ao_flash_instruction.address[1] = ao_flash_block << (ao_flash_block_shift - 8);
286 ao_flash_instruction.address[2] = 0;
287 ao_flash_send(&ao_flash_instruction, 4);
288 ao_flash_recv(ao_flash_data, FLASH_BLOCK_SIZE);
293 ao_flash_flush_internal(void)
295 if (ao_flash_block_dirty) {
296 ao_flash_write_block();
297 ao_flash_block_dirty = 0;
302 ao_flash_fill(uint16_t block)
304 if (block != ao_flash_block) {
305 ao_flash_flush_internal();
306 ao_flash_block = block;
307 ao_flash_read_block();
312 ao_ee_write(uint32_t pos, uint8_t *buf, uint16_t len) __reentrant
319 if (pos >= FLASH_DATA_SIZE || pos + len > FLASH_DATA_SIZE)
323 /* Compute portion of transfer within
326 this_off = (uint16_t) pos & FLASH_BLOCK_MASK;
327 this_len = FLASH_BLOCK_SIZE - this_off;
328 block = (uint16_t) (pos >> FLASH_BLOCK_SHIFT);
332 /* Transfer the data */
333 ao_mutex_get(&ao_flash_mutex); {
334 if (this_len != FLASH_BLOCK_SIZE)
335 ao_flash_fill(block);
337 ao_flash_flush_internal();
338 ao_flash_block = block;
340 memcpy(ao_flash_data + this_off, buf, this_len);
341 ao_flash_block_dirty = 1;
342 } ao_mutex_put(&ao_flash_mutex);
344 /* See how much is left */
353 ao_ee_read(uint32_t pos, uint8_t *buf, uint16_t len) __reentrant
360 if (pos >= FLASH_DATA_SIZE || pos + len > FLASH_DATA_SIZE)
365 /* Compute portion of transfer within
368 this_off = (uint16_t) pos & FLASH_BLOCK_MASK;
369 this_len = FLASH_BLOCK_SIZE - this_off;
370 block = (uint16_t) (pos >> FLASH_BLOCK_SHIFT);
374 /* Transfer the data */
375 ao_mutex_get(&ao_flash_mutex); {
376 ao_flash_fill(block);
377 memcpy(buf, ao_flash_data + this_off, this_len);
378 } ao_mutex_put(&ao_flash_mutex);
380 /* See how much is left */
389 ao_ee_flush(void) __reentrant
391 ao_mutex_get(&ao_flash_mutex); {
392 ao_flash_flush_internal();
393 } ao_mutex_put(&ao_flash_mutex);
397 * Read/write the config block, which is in
398 * the last block of the flash
401 ao_ee_write_config(uint8_t *buf, uint16_t len) __reentrant
404 if (len > FLASH_BLOCK_SIZE)
406 ao_mutex_get(&ao_flash_mutex); {
407 ao_flash_fill(FLASH_CONFIG_BLOCK);
408 memcpy(ao_flash_data, buf, len);
409 ao_flash_block_dirty = 1;
410 ao_flash_flush_internal();
411 } ao_mutex_put(&ao_flash_mutex);
416 ao_ee_read_config(uint8_t *buf, uint16_t len) __reentrant
419 if (len > FLASH_BLOCK_SIZE)
421 ao_mutex_get(&ao_flash_mutex); {
422 ao_flash_fill(FLASH_CONFIG_BLOCK);
423 memcpy(buf, ao_flash_data, len);
424 } ao_mutex_put(&ao_flash_mutex);
429 flash_dump(void) __reentrant
436 block = ao_cmd_lex_i;
437 if (ao_cmd_status != ao_cmd_success)
444 ao_cmd_put16((uint16_t) i);
447 ao_ee_read(((uint32_t) block << 8) | i, &b, 1);
455 flash_store(void) __reentrant
464 block = ao_cmd_lex_i;
467 addr = ((uint32_t) block << 8) | i;
470 if (ao_cmd_status != ao_cmd_success)
474 if (ao_cmd_status != ao_cmd_success)
477 ao_ee_write(addr, &b, 1);
483 __code struct ao_cmds ao_flash_cmds[] = {
484 { 'e', flash_dump, "e <block> Dump a block of flash data" },
485 { 'w', flash_store, "w <block> <start> <len> <data> ... Write data to flash" },
486 { 0, flash_store, NULL },
490 * To initialize the chip, set up the CS line and
498 P1DIR |= (1 << FLASH_CS_INDEX);
499 P1SEL &= ~(1 << FLASH_CS_INDEX);
501 /* Set up the USART pin assignment */
502 PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2;
504 /* Ensure that USART0 takes precidence over USART1 for pins that
507 P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0;
509 /* Make the SPI pins be controlled by the USART peripheral */
510 P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3));
513 ao_flash_dma_out_id = ao_dma_alloc(&ao_flash_dma_out_done);
516 ao_flash_dma_in_id = ao_dma_alloc(&ao_flash_dma_in_done);
522 U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_MASTER);
524 /* Set the baud rate and signal parameters
526 * The cc1111 is limited to a 24/8 MHz SPI clock,
527 * while the at45db161d.h is limited to 20MHz. So,
528 * use the 3MHz clock (BAUD_E 17, BAUD_M 0)
531 U0GCR = (UxGCR_CPOL_NEGATIVE |
532 UxGCR_CPHA_FIRST_EDGE |
534 (17 << UxGCR_BAUD_E_SHIFT));
535 ao_cmd_register(&ao_flash_cmds[0]);