--- /dev/null
+# Copyright (C) 1991-2005 Altera Corporation\r
+# Your use of Altera Corporation's design tools, logic functions \r
+# and other software and tools, and its AMPP partner logic \r
+# functions, and any output files any of the foregoing \r
+# (including device programming or simulation files), and any \r
+# associated documentation or information are expressly subject \r
+# to the terms and conditions of the Altera Program License \r
+# Subscription Agreement, Altera MegaCore Function License \r
+# Agreement, or other applicable license agreement, including, \r
+# without limitation, that your use is for the sole purpose of \r
+# programming logic devices manufactured by Altera and sold by \r
+# Altera or its authorized distributors. Please refer to the \r
+# applicable agreement for further details.\r
+\r
+\r
+# The default values for assignments are stored in the file\r
+# usrp_sounder_assignment_defaults.qdf\r
+# If this file doesn't exist, and for assignments not listed, see file\r
+# assignment_defaults.qdf\r
+\r
+# Altera recommends that you do not modify this file. This\r
+# file is updated automatically by the Quartus II software\r
+# and any changes you make may be lost or overwritten.\r
+\r
+\r
+# Project-Wide Assignments\r
+# ========================\r
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0\r
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"\r
+set_global_assignment -name LAST_QUARTUS_VERSION 7.0\r
+\r
+# Pin & Location Assignments\r
+# ==========================\r
+set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"\r
+set_location_assignment PIN_29 -to SCLK\r
+set_location_assignment PIN_117 -to SDI\r
+set_location_assignment PIN_28 -to usbclk\r
+set_location_assignment PIN_107 -to usbctl[0]\r
+set_location_assignment PIN_106 -to usbctl[1]\r
+set_location_assignment PIN_105 -to usbctl[2]\r
+set_location_assignment PIN_100 -to usbdata[0]\r
+set_location_assignment PIN_84 -to usbdata[10]\r
+set_location_assignment PIN_83 -to usbdata[11]\r
+set_location_assignment PIN_82 -to usbdata[12]\r
+set_location_assignment PIN_79 -to usbdata[13]\r
+set_location_assignment PIN_78 -to usbdata[14]\r
+set_location_assignment PIN_77 -to usbdata[15]\r
+set_location_assignment PIN_99 -to usbdata[1]\r
+set_location_assignment PIN_98 -to usbdata[2]\r
+set_location_assignment PIN_95 -to usbdata[3]\r
+set_location_assignment PIN_94 -to usbdata[4]\r
+set_location_assignment PIN_93 -to usbdata[5]\r
+set_location_assignment PIN_88 -to usbdata[6]\r
+set_location_assignment PIN_87 -to usbdata[7]\r
+set_location_assignment PIN_86 -to usbdata[8]\r
+set_location_assignment PIN_85 -to usbdata[9]\r
+set_location_assignment PIN_104 -to usbrdy[0]\r
+set_location_assignment PIN_101 -to usbrdy[1]\r
+set_location_assignment PIN_76 -to FX2_1\r
+set_location_assignment PIN_75 -to FX2_2\r
+set_location_assignment PIN_74 -to FX2_3\r
+set_location_assignment PIN_116 -to io_rx_a[0]\r
+set_location_assignment PIN_115 -to io_rx_a[1]\r
+set_location_assignment PIN_114 -to io_rx_a[2]\r
+set_location_assignment PIN_113 -to io_rx_a[3]\r
+set_location_assignment PIN_108 -to io_rx_a[4]\r
+set_location_assignment PIN_195 -to io_rx_a[5]\r
+set_location_assignment PIN_196 -to io_rx_a[6]\r
+set_location_assignment PIN_197 -to io_rx_a[7]\r
+set_location_assignment PIN_200 -to io_rx_a[8]\r
+set_location_assignment PIN_201 -to io_rx_a[9]\r
+set_location_assignment PIN_202 -to io_rx_a[10]\r
+set_location_assignment PIN_203 -to io_rx_a[11]\r
+set_location_assignment PIN_206 -to io_rx_a[12]\r
+set_location_assignment PIN_207 -to io_rx_a[13]\r
+set_location_assignment PIN_208 -to io_rx_a[14]\r
+set_location_assignment PIN_214 -to io_rx_b[0]\r
+set_location_assignment PIN_215 -to io_rx_b[1]\r
+set_location_assignment PIN_216 -to io_rx_b[2]\r
+set_location_assignment PIN_217 -to io_rx_b[3]\r
+set_location_assignment PIN_218 -to io_rx_b[4]\r
+set_location_assignment PIN_219 -to io_rx_b[5]\r
+set_location_assignment PIN_222 -to io_rx_b[6]\r
+set_location_assignment PIN_223 -to io_rx_b[7]\r
+set_location_assignment PIN_224 -to io_rx_b[8]\r
+set_location_assignment PIN_225 -to io_rx_b[9]\r
+set_location_assignment PIN_226 -to io_rx_b[10]\r
+set_location_assignment PIN_227 -to io_rx_b[11]\r
+set_location_assignment PIN_228 -to io_rx_b[12]\r
+set_location_assignment PIN_233 -to io_rx_b[13]\r
+set_location_assignment PIN_234 -to io_rx_b[14]\r
+set_location_assignment PIN_175 -to io_tx_a[0]\r
+set_location_assignment PIN_176 -to io_tx_a[1]\r
+set_location_assignment PIN_177 -to io_tx_a[2]\r
+set_location_assignment PIN_178 -to io_tx_a[3]\r
+set_location_assignment PIN_179 -to io_tx_a[4]\r
+set_location_assignment PIN_180 -to io_tx_a[5]\r
+set_location_assignment PIN_181 -to io_tx_a[6]\r
+set_location_assignment PIN_182 -to io_tx_a[7]\r
+set_location_assignment PIN_183 -to io_tx_a[8]\r
+set_location_assignment PIN_184 -to io_tx_a[9]\r
+set_location_assignment PIN_185 -to io_tx_a[10]\r
+set_location_assignment PIN_186 -to io_tx_a[11]\r
+set_location_assignment PIN_187 -to io_tx_a[12]\r
+set_location_assignment PIN_188 -to io_tx_a[13]\r
+set_location_assignment PIN_193 -to io_tx_a[14]\r
+set_location_assignment PIN_73 -to io_tx_b[0]\r
+set_location_assignment PIN_68 -to io_tx_b[1]\r
+set_location_assignment PIN_67 -to io_tx_b[2]\r
+set_location_assignment PIN_66 -to io_tx_b[3]\r
+set_location_assignment PIN_65 -to io_tx_b[4]\r
+set_location_assignment PIN_64 -to io_tx_b[5]\r
+set_location_assignment PIN_63 -to io_tx_b[6]\r
+set_location_assignment PIN_62 -to io_tx_b[7]\r
+set_location_assignment PIN_61 -to io_tx_b[8]\r
+set_location_assignment PIN_60 -to io_tx_b[9]\r
+set_location_assignment PIN_59 -to io_tx_b[10]\r
+set_location_assignment PIN_58 -to io_tx_b[11]\r
+set_location_assignment PIN_57 -to io_tx_b[12]\r
+set_location_assignment PIN_56 -to io_tx_b[13]\r
+set_location_assignment PIN_55 -to io_tx_b[14]\r
+set_location_assignment PIN_152 -to master_clk\r
+set_location_assignment PIN_144 -to rx_a_a[0]\r
+set_location_assignment PIN_143 -to rx_a_a[1]\r
+set_location_assignment PIN_141 -to rx_a_a[2]\r
+set_location_assignment PIN_140 -to rx_a_a[3]\r
+set_location_assignment PIN_139 -to rx_a_a[4]\r
+set_location_assignment PIN_138 -to rx_a_a[5]\r
+set_location_assignment PIN_137 -to rx_a_a[6]\r
+set_location_assignment PIN_136 -to rx_a_a[7]\r
+set_location_assignment PIN_135 -to rx_a_a[8]\r
+set_location_assignment PIN_134 -to rx_a_a[9]\r
+set_location_assignment PIN_133 -to rx_a_a[10]\r
+set_location_assignment PIN_132 -to rx_a_a[11]\r
+set_location_assignment PIN_23 -to rx_a_b[0]\r
+set_location_assignment PIN_21 -to rx_a_b[1]\r
+set_location_assignment PIN_20 -to rx_a_b[2]\r
+set_location_assignment PIN_19 -to rx_a_b[3]\r
+set_location_assignment PIN_18 -to rx_a_b[4]\r
+set_location_assignment PIN_17 -to rx_a_b[5]\r
+set_location_assignment PIN_16 -to rx_a_b[6]\r
+set_location_assignment PIN_15 -to rx_a_b[7]\r
+set_location_assignment PIN_14 -to rx_a_b[8]\r
+set_location_assignment PIN_13 -to rx_a_b[9]\r
+set_location_assignment PIN_12 -to rx_a_b[10]\r
+set_location_assignment PIN_11 -to rx_a_b[11]\r
+set_location_assignment PIN_131 -to rx_b_a[0]\r
+set_location_assignment PIN_128 -to rx_b_a[1]\r
+set_location_assignment PIN_127 -to rx_b_a[2]\r
+set_location_assignment PIN_126 -to rx_b_a[3]\r
+set_location_assignment PIN_125 -to rx_b_a[4]\r
+set_location_assignment PIN_124 -to rx_b_a[5]\r
+set_location_assignment PIN_123 -to rx_b_a[6]\r
+set_location_assignment PIN_122 -to rx_b_a[7]\r
+set_location_assignment PIN_121 -to rx_b_a[8]\r
+set_location_assignment PIN_120 -to rx_b_a[9]\r
+set_location_assignment PIN_119 -to rx_b_a[10]\r
+set_location_assignment PIN_118 -to rx_b_a[11]\r
+set_location_assignment PIN_8 -to rx_b_b[0]\r
+set_location_assignment PIN_7 -to rx_b_b[1]\r
+set_location_assignment PIN_6 -to rx_b_b[2]\r
+set_location_assignment PIN_5 -to rx_b_b[3]\r
+set_location_assignment PIN_4 -to rx_b_b[4]\r
+set_location_assignment PIN_3 -to rx_b_b[5]\r
+set_location_assignment PIN_2 -to rx_b_b[6]\r
+set_location_assignment PIN_240 -to rx_b_b[7]\r
+set_location_assignment PIN_239 -to rx_b_b[8]\r
+set_location_assignment PIN_238 -to rx_b_b[9]\r
+set_location_assignment PIN_237 -to rx_b_b[10]\r
+set_location_assignment PIN_236 -to rx_b_b[11]\r
+set_location_assignment PIN_156 -to SDO\r
+set_location_assignment PIN_153 -to SEN_FPGA\r
+set_location_assignment PIN_159 -to tx_a[0]\r
+set_location_assignment PIN_160 -to tx_a[1]\r
+set_location_assignment PIN_161 -to tx_a[2]\r
+set_location_assignment PIN_162 -to tx_a[3]\r
+set_location_assignment PIN_163 -to tx_a[4]\r
+set_location_assignment PIN_164 -to tx_a[5]\r
+set_location_assignment PIN_165 -to tx_a[6]\r
+set_location_assignment PIN_166 -to tx_a[7]\r
+set_location_assignment PIN_167 -to tx_a[8]\r
+set_location_assignment PIN_168 -to tx_a[9]\r
+set_location_assignment PIN_169 -to tx_a[10]\r
+set_location_assignment PIN_170 -to tx_a[11]\r
+set_location_assignment PIN_173 -to tx_a[12]\r
+set_location_assignment PIN_174 -to tx_a[13]\r
+set_location_assignment PIN_38 -to tx_b[0]\r
+set_location_assignment PIN_39 -to tx_b[1]\r
+set_location_assignment PIN_41 -to tx_b[2]\r
+set_location_assignment PIN_42 -to tx_b[3]\r
+set_location_assignment PIN_43 -to tx_b[4]\r
+set_location_assignment PIN_44 -to tx_b[5]\r
+set_location_assignment PIN_45 -to tx_b[6]\r
+set_location_assignment PIN_46 -to tx_b[7]\r
+set_location_assignment PIN_47 -to tx_b[8]\r
+set_location_assignment PIN_48 -to tx_b[9]\r
+set_location_assignment PIN_49 -to tx_b[10]\r
+set_location_assignment PIN_50 -to tx_b[11]\r
+set_location_assignment PIN_53 -to tx_b[12]\r
+set_location_assignment PIN_54 -to tx_b[13]\r
+set_location_assignment PIN_158 -to TXSYNC_A\r
+set_location_assignment PIN_37 -to TXSYNC_B\r
+set_location_assignment PIN_235 -to io_rx_b[15]\r
+set_location_assignment PIN_24 -to io_tx_b[15]\r
+set_location_assignment PIN_213 -to io_rx_a[15]\r
+set_location_assignment PIN_194 -to io_tx_a[15]\r
+set_location_assignment PIN_1 -to MYSTERY_SIGNAL\r
+\r
+# Timing Assignments\r
+# ==================\r
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF\r
+\r
+# Analysis & Synthesis Assignments\r
+# ================================\r
+set_global_assignment -name SAVE_DISK_SPACE OFF\r
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"\r
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240\r
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"\r
+set_global_assignment -name FAMILY Cyclone\r
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED\r
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED\r
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED\r
+set_global_assignment -name TOP_LEVEL_ENTITY usrp_sounder\r
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF\r
+set_global_assignment -name USER_LIBRARIES "h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"\r
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON\r
+\r
+# Fitter Assignments\r
+# ==================\r
+set_global_assignment -name DEVICE EP1C12Q240C8\r
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"\r
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"\r
+set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF\r
+set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"\r
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF\r
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF\r
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF\r
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF\r
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA\r
+set_global_assignment -name INC_PLC_MODE OFF\r
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF\r
+set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]\r
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL\r
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\r
+\r
+# Timing Analysis Assignments\r
+# ===========================\r
+set_global_assignment -name MAX_SCC_SIZE 50\r
+\r
+# EDA Netlist Writer Assignments\r
+# ==============================\r
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"\r
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"\r
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"\r
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"\r
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"\r
+\r
+# Assembler Assignments\r
+# =====================\r
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF\r
+set_global_assignment -name GENERATE_RBF_FILE ON\r
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"\r
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF\r
+\r
+# Simulator Assignments\r
+# =====================\r
+set_global_assignment -name START_TIME "0 ns"\r
+set_global_assignment -name GLITCH_INTERVAL "1 ns"\r
+\r
+# Design Assistant Assignments\r
+# ============================\r
+set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF\r
+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF\r
+set_global_assignment -name ASSG_CAT OFF\r
+set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF\r
+set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF\r
+set_global_assignment -name CLK_CAT OFF\r
+set_global_assignment -name CLK_RULE_COMB_CLOCK OFF\r
+set_global_assignment -name CLK_RULE_INV_CLOCK OFF\r
+set_global_assignment -name CLK_RULE_GATING_SCHEME OFF\r
+set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF\r
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF\r
+set_global_assignment -name CLK_RULE_MIX_EDGES OFF\r
+set_global_assignment -name RESET_CAT OFF\r
+set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF\r
+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF\r
+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF\r
+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF\r
+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF\r
+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF\r
+set_global_assignment -name TIMING_CAT OFF\r
+set_global_assignment -name TIMING_RULE_SHIFT_REG OFF\r
+set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_CAT OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF\r
+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF\r
+set_global_assignment -name SIGNALRACE_CAT OFF\r
+set_global_assignment -name ACLK_CAT OFF\r
+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF\r
+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF\r
+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF\r
+set_global_assignment -name HCPY_CAT OFF\r
+set_global_assignment -name HCPY_VREF_PINS OFF\r
+\r
+# SignalTap II Assignments\r
+# ========================\r
+set_global_assignment -name HUB_ENTITY_NAME SLD_HUB\r
+set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST\r
+set_global_assignment -name ENABLE_SIGNALTAP OFF\r
+\r
+# LogicLock Region Assignments\r
+# ============================\r
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF\r
+\r
+# -----------------\r
+# start CLOCK(SCLK)\r
+\r
+ # Timing Assignments\r
+ # ==================\r
+set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK\r
+set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK\r
+\r
+# end CLOCK(SCLK)\r
+# ---------------\r
+\r
+# -----------------------\r
+# start CLOCK(master_clk)\r
+\r
+ # Timing Assignments\r
+ # ==================\r
+set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk\r
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk\r
+\r
+# end CLOCK(master_clk)\r
+# ---------------------\r
+\r
+# -------------------\r
+# start CLOCK(usbclk)\r
+\r
+ # Timing Assignments\r
+ # ==================\r
+set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk\r
+set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk\r
+\r
+# end CLOCK(usbclk)\r
+# -----------------\r
+\r
+# ----------------------\r
+# start ENTITY(usrp_sounder)\r
+\r
+ # Timing Assignments\r
+ # ==================\r
+set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK\r
+set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk\r
+set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk\r
+\r
+# end ENTITY(usrp_sounder)\r
+# --------------------\r
+\r
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top\r
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\r
+\r
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF\r
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE REALISTIC\r
+set_global_assignment -name VERILOG_FILE ../lib/lfsr_constants.v\r
+set_global_assignment -name VERILOG_FILE ../lib/lfsr.v\r
+set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v\r
+set_global_assignment -name VERILOG_FILE ../lib/dacpll.v\r
+set_global_assignment -name VERILOG_FILE ../lib/sounder_rx.v\r
+set_global_assignment -name VERILOG_FILE ../lib/sounder_tx.v\r
+set_global_assignment -name VERILOG_FILE ../lib/sounder_ctrl.v\r
+set_global_assignment -name VERILOG_FILE ../lib/sounder.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/sign_extend.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v\r
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v\r
+set_global_assignment -name VERILOG_FILE usrp_sounder.v\r
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
\ No newline at end of file
projects / debian / gnuradio / blobdiff