Merge commit 'v3.3.0' into upstream
[debian/gnuradio] / gr-radar-mono / src / fpga / top / dacpll.v
diff --git a/gr-radar-mono/src/fpga/top/dacpll.v b/gr-radar-mono/src/fpga/top/dacpll.v
new file mode 100644 (file)
index 0000000..f3941bc
--- /dev/null
@@ -0,0 +1,291 @@
+// megafunction wizard: %ALTPLL%\r
+// GENERATION: STANDARD\r
+// VERSION: WM1.0\r
+// MODULE: altpll \r
+\r
+// ============================================================\r
+// File Name: dacpll.v\r
+// Megafunction Name(s):\r
+//                     altpll\r
+//\r
+// Simulation Library Files(s):\r
+//                     altera_mf\r
+// ============================================================\r
+// ************************************************************\r
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\r
+//\r
+// 7.0 Build 33 02/05/2007 SJ Web Edition\r
+// ************************************************************\r
+\r
+\r
+//Copyright (C) 1991-2007 Altera Corporation\r
+//Your use of Altera Corporation's design tools, logic functions \r
+//and other software and tools, and its AMPP partner logic \r
+//functions, and any output files from any of the foregoing \r
+//(including device programming or simulation files), and any \r
+//associated documentation or information are expressly subject \r
+//to the terms and conditions of the Altera Program License \r
+//Subscription Agreement, Altera MegaCore Function License \r
+//Agreement, or other applicable license agreement, including, \r
+//without limitation, that your use is for the sole purpose of \r
+//programming logic devices manufactured by Altera and sold by \r
+//Altera or its authorized distributors.  Please refer to the \r
+//applicable agreement for further details.\r
+\r
+\r
+// synopsys translate_off\r
+`timescale 1 ps / 1 ps\r
+// synopsys translate_on\r
+module dacpll (\r
+       areset,\r
+       inclk0,\r
+       c0);\r
+\r
+       input     areset;\r
+       input     inclk0;\r
+       output    c0;\r
+\r
+       wire [5:0] sub_wire0;\r
+       wire [0:0] sub_wire4 = 1'h0;\r
+       wire [0:0] sub_wire1 = sub_wire0[0:0];\r
+       wire  c0 = sub_wire1;\r
+       wire  sub_wire2 = inclk0;\r
+       wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};\r
+\r
+       altpll  altpll_component (\r
+                               .inclk (sub_wire3),\r
+                               .areset (areset),\r
+                               .clk (sub_wire0),\r
+                               .activeclock (),\r
+                               .clkbad (),\r
+                               .clkena ({6{1'b1}}),\r
+                               .clkloss (),\r
+                               .clkswitch (1'b0),\r
+                               .configupdate (1'b1),\r
+                               .enable0 (),\r
+                               .enable1 (),\r
+                               .extclk (),\r
+                               .extclkena ({4{1'b1}}),\r
+                               .fbin (1'b1),\r
+                               .fbout (),\r
+                               .locked (),\r
+                               .pfdena (1'b1),\r
+                               .phasecounterselect ({4{1'b1}}),\r
+                               .phasedone (),\r
+                               .phasestep (1'b1),\r
+                               .phaseupdown (1'b1),\r
+                               .pllena (1'b1),\r
+                               .scanaclr (1'b0),\r
+                               .scanclk (1'b0),\r
+                               .scanclkena (1'b1),\r
+                               .scandata (1'b0),\r
+                               .scandataout (),\r
+                               .scandone (),\r
+                               .scanread (1'b0),\r
+                               .scanwrite (1'b0),\r
+                               .sclkout0 (),\r
+                               .sclkout1 (),\r
+                               .vcooverrange (),\r
+                               .vcounderrange ());\r
+       defparam\r
+               altpll_component.clk0_divide_by = 1,\r
+               altpll_component.clk0_duty_cycle = 50,\r
+               altpll_component.clk0_multiply_by = 2,\r
+               altpll_component.clk0_phase_shift = "0000",\r
+               altpll_component.compensate_clock = "CLK0",\r
+               altpll_component.inclk0_input_frequency = 15625,\r
+               altpll_component.intended_device_family = "Cyclone",\r
+               altpll_component.lpm_type = "altpll",\r
+               altpll_component.operation_mode = "NORMAL",\r
+               altpll_component.pll_type = "AUTO",\r
+               altpll_component.port_activeclock = "PORT_UNUSED",\r
+               altpll_component.port_areset = "PORT_USED",\r
+               altpll_component.port_clkbad0 = "PORT_UNUSED",\r
+               altpll_component.port_clkbad1 = "PORT_UNUSED",\r
+               altpll_component.port_clkloss = "PORT_UNUSED",\r
+               altpll_component.port_clkswitch = "PORT_UNUSED",\r
+               altpll_component.port_configupdate = "PORT_UNUSED",\r
+               altpll_component.port_fbin = "PORT_UNUSED",\r
+               altpll_component.port_inclk0 = "PORT_USED",\r
+               altpll_component.port_inclk1 = "PORT_UNUSED",\r
+               altpll_component.port_locked = "PORT_UNUSED",\r
+               altpll_component.port_pfdena = "PORT_UNUSED",\r
+               altpll_component.port_phasecounterselect = "PORT_UNUSED",\r
+               altpll_component.port_phasedone = "PORT_UNUSED",\r
+               altpll_component.port_phasestep = "PORT_UNUSED",\r
+               altpll_component.port_phaseupdown = "PORT_UNUSED",\r
+               altpll_component.port_pllena = "PORT_UNUSED",\r
+               altpll_component.port_scanaclr = "PORT_UNUSED",\r
+               altpll_component.port_scanclk = "PORT_UNUSED",\r
+               altpll_component.port_scanclkena = "PORT_UNUSED",\r
+               altpll_component.port_scandata = "PORT_UNUSED",\r
+               altpll_component.port_scandataout = "PORT_UNUSED",\r
+               altpll_component.port_scandone = "PORT_UNUSED",\r
+               altpll_component.port_scanread = "PORT_UNUSED",\r
+               altpll_component.port_scanwrite = "PORT_UNUSED",\r
+               altpll_component.port_clk0 = "PORT_USED",\r
+               altpll_component.port_clk1 = "PORT_UNUSED",\r
+               altpll_component.port_clk3 = "PORT_UNUSED",\r
+               altpll_component.port_clk4 = "PORT_UNUSED",\r
+               altpll_component.port_clk5 = "PORT_UNUSED",\r
+               altpll_component.port_clkena0 = "PORT_UNUSED",\r
+               altpll_component.port_clkena1 = "PORT_UNUSED",\r
+               altpll_component.port_clkena3 = "PORT_UNUSED",\r
+               altpll_component.port_clkena4 = "PORT_UNUSED",\r
+               altpll_component.port_clkena5 = "PORT_UNUSED",\r
+               altpll_component.port_extclk0 = "PORT_UNUSED",\r
+               altpll_component.port_extclk1 = "PORT_UNUSED",\r
+               altpll_component.port_extclk2 = "PORT_UNUSED",\r
+               altpll_component.port_extclk3 = "PORT_UNUSED";\r
+\r
+\r
+endmodule\r
+\r
+// ============================================================\r
+// CNX file retrieval info\r
+// ============================================================\r
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"\r
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"\r
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"\r
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"\r
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"\r
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"\r
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"\r
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"\r
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"\r
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"\r
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"\r
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"\r
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"\r
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"\r
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"\r
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"\r
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"\r
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"\r
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"\r
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"\r
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"\r
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"\r
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"\r
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"\r
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"\r
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"\r
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"\r
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"\r
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"\r
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"\r
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"\r
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"\r
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"\r
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"\r
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"\r
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"\r
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"\r
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"\r
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"\r
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"\r
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"\r
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"\r
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"\r
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"\r
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"\r
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"\r
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"\r
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"\r
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"\r
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"\r
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"\r
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"\r
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"\r
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"\r
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"\r
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"\r
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"\r
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"\r
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"\r
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"\r
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"\r
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"\r
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"\r
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"\r
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"\r
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"\r
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"\r
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"\r
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"\r
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"\r
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"\r
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"\r
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"\r
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"\r
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"\r
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"\r
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"\r
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"\r
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"\r
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"\r
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"\r
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"\r
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"\r
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\r
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\r
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\r
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.v TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.ppf TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.inc FALSE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.cmp FALSE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.bsf TRUE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_inst.v TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_bb.v TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_waveforms.html TRUE FALSE\r
+// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_wave*.jpg FALSE FALSE\r
+// Retrieval info: LIB_FILE: altera_mf\r