From f69adafb3dd252eaf6b269b7993b29d3c78a91c8 Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Tue, 11 May 2021 09:28:00 +0100 Subject: [PATCH] target/arm: optimize architecture flags In target/arm.h the struct arm do contain 3 flags to retain architecture version for some tweaks. The proposal is to have only one enumerated flag 'arch' for the same purpose. Change-Id: Ia5d5accfed8158ca21eb54af2fdea8e36f0266ae Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/6229 Tested-by: jenkins Reviewed-by: Antonio Borneo --- src/flash/nand/arm_io.c | 4 ++-- src/flash/nor/stm32lx.c | 2 +- src/rtos/riot.c | 2 +- src/target/arm.h | 19 +++++++++++-------- src/target/arm720t.c | 2 +- src/target/arm7tdmi.c | 2 +- src/target/arm9tdmi.c | 2 +- src/target/armv4_5.c | 6 +++--- src/target/cortex_m.c | 16 ++++++++-------- 9 files changed, 29 insertions(+), 26 deletions(-) diff --git a/src/flash/nand/arm_io.c b/src/flash/nand/arm_io.c index e319f9585..705470e77 100644 --- a/src/flash/nand/arm_io.c +++ b/src/flash/nand/arm_io.c @@ -173,7 +173,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) buf_set_u32(reg_params[2].value, 0, 32, size); /* armv4 must exit using a hardware breakpoint */ - if (arm->is_armv4) + if (arm->arch == ARM_ARCH_V4) exit_var = nand->copy_area->address + target_code_size - 4; /* use alg to write data from work area to NAND chip */ @@ -279,7 +279,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size) buf_set_u32(reg_params[2].value, 0, 32, size); /* armv4 must exit using a hardware breakpoint */ - if (arm->is_armv4) + if (arm->arch == ARM_ARCH_V4) exit_var = nand->copy_area->address + target_code_size - 4; /* use alg to write data from NAND chip to work area */ diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c index 1ea1b1d0e..5ca424b87 100644 --- a/src/flash/nor/stm32lx.c +++ b/src/flash/nor/stm32lx.c @@ -718,7 +718,7 @@ static int stm32lx_read_id_code(struct target *target, uint32_t *id) { struct armv7m_common *armv7m = target_to_armv7m(target); int retval; - if (armv7m->arm.is_armv6m == true) + if (armv7m->arm.arch == ARM_ARCH_V6M) retval = target_read_u32(target, DBGMCU_IDCODE_L0, id); else /* read stm32 device id register */ diff --git a/src/rtos/riot.c b/src/rtos/riot.c index dcba8381c..9165fe11b 100644 --- a/src/rtos/riot.c +++ b/src/rtos/riot.c @@ -416,7 +416,7 @@ static int riot_create(struct target *target) /* Stacking is different depending on architecture */ struct armv7m_common *armv7m_target = target_to_armv7m(target); - if (armv7m_target->arm.is_armv6m) + if (armv7m_target->arm.arch == ARM_ARCH_V6M) stacking_info = &rtos_riot_cortex_m0_stacking; else if (is_armv7m(armv7m_target)) stacking_info = &rtos_riot_cortex_m34_stacking; diff --git a/src/target/arm.h b/src/target/arm.h index d97a95edf..f403b8f8a 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -60,6 +60,15 @@ enum arm_core_type { ARM_CORE_TYPE_M_PROFILE, }; +/** ARM Architecture specifying the version and the profile */ +enum arm_arch { + ARM_ARCH_UNKNOWN, + ARM_ARCH_V4, + ARM_ARCH_V6M, + ARM_ARCH_V7M, + ARM_ARCH_V8M, +}; + /** * Represent state of an ARM core. * @@ -191,14 +200,8 @@ struct arm { /** Record the current core state: ARM, Thumb, or otherwise. */ enum arm_state core_state; - /** Flag reporting unavailability of the BKPT instruction. */ - bool is_armv4; - - /** Flag reporting armv6m based core. */ - bool is_armv6m; - - /** Flag reporting armv8m based core. */ - bool is_armv8m; + /** ARM architecture version */ + enum arm_arch arch; /** Floating point or VFP version, 0 if disabled. */ int arm_vfp_version; diff --git a/src/target/arm720t.c b/src/target/arm720t.c index daa44e46a..bff20a334 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -427,7 +427,7 @@ static int arm720t_target_create(struct target *target, Jim_Interp *interp) { struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t)); - arm720t->arm7_9_common.arm.is_armv4 = true; + arm720t->arm7_9_common.arm.arch = ARM_ARCH_V4; return arm720t_init_arch_info(target, arm720t, target->tap); } diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 10263f40a..b0348392f 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -686,7 +686,7 @@ static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp) arm7_9 = calloc(1, sizeof(struct arm7_9_common)); arm7tdmi_init_arch_info(target, arm7_9, target->tap); - arm7_9->arm.is_armv4 = true; + arm7_9->arm.arch = ARM_ARCH_V4; return ERROR_OK; } diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 4810c2b16..2a32f1127 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -781,7 +781,7 @@ static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp) struct arm7_9_common *arm7_9 = calloc(1, sizeof(struct arm7_9_common)); arm9tdmi_init_arch_info(target, arm7_9, target->tap); - arm7_9->arm.is_armv4 = true; + arm7_9->arm.arch = ARM_ARCH_V4; return ERROR_OK; } diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 084a6f9b2..6378ea66e 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -1347,7 +1347,7 @@ int armv4_5_run_algorithm_inner(struct target *target, } /* armv5 and later can terminate with BKPT instruction; less overhead */ - if (!exit_point && arm->is_armv4) { + if (!exit_point && arm->arch == ARM_ARCH_V4) { LOG_ERROR("ARMv4 target needs HW breakpoint location"); return ERROR_FAIL; } @@ -1568,7 +1568,7 @@ int arm_checksum_memory(struct target *target, int timeout = 20000 * (1 + (count / (1024 * 1024))); /* armv4 must exit using a hardware breakpoint */ - if (arm->is_armv4) + if (arm->arch == ARM_ARCH_V4) exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8; retval = target_run_algorithm(target, 0, NULL, 2, reg_params, @@ -1649,7 +1649,7 @@ int arm_blank_check_memory(struct target *target, buf_set_u32(reg_params[2].value, 0, 32, erased_value); /* armv4 must exit using a hardware breakpoint */ - if (arm->is_armv4) + if (arm->arch == ARM_ARCH_V4) exit_var = check_algorithm->address + sizeof(check_code_le) - 4; retval = target_run_algorithm(target, 0, NULL, 3, reg_params, diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 941fef16a..e442fc3b6 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -504,7 +504,7 @@ static int cortex_m_debug_entry(struct target *target) /* examine PE security state */ bool secure_state = false; - if (armv7m->arm.is_armv8m) { + if (armv7m->arm.arch == ARM_ARCH_V8M) { uint32_t dscsr; retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr); @@ -1645,7 +1645,7 @@ static int cortex_m_read_memory(struct target *target, target_addr_t address, { struct armv7m_common *armv7m = target_to_armv7m(target); - if (armv7m->arm.is_armv6m) { + if (armv7m->arm.arch == ARM_ARCH_V6M) { /* armv6m does not handle unaligned memory access */ if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; @@ -1659,7 +1659,7 @@ static int cortex_m_write_memory(struct target *target, target_addr_t address, { struct armv7m_common *armv7m = target_to_armv7m(target); - if (armv7m->arm.is_armv6m) { + if (armv7m->arm.arch == ARM_ARCH_V6M) { /* armv6m does not handle unaligned memory access */ if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; @@ -2005,7 +2005,7 @@ int cortex_m_examine(struct target *target) unsigned int core = (cpuid >> 4) & 0xf; /* Check if it is an ARMv8-M core */ - armv7m->arm.is_armv8m = true; + armv7m->arm.arch = ARM_ARCH_V8M; switch (cpuid & ARM_CPUID_PARTNO_MASK) { case CORTEX_M23_PARTNO: @@ -2021,7 +2021,7 @@ int cortex_m_examine(struct target *target) core = 55; break; default: - armv7m->arm.is_armv8m = false; + armv7m->arm.arch = ARM_ARCH_V7M; break; } @@ -2063,18 +2063,18 @@ int cortex_m_examine(struct target *target) } } else if (core == 0) { /* Cortex-M0 does not support unaligned memory access */ - armv7m->arm.is_armv6m = true; + armv7m->arm.arch = ARM_ARCH_V6M; } /* VECTRESET is supported only on ARMv7-M cores */ - cortex_m->vectreset_supported = !armv7m->arm.is_armv8m && !armv7m->arm.is_armv6m; + cortex_m->vectreset_supported = armv7m->arm.arch == ARM_ARCH_V7M; /* Check for FPU, otherwise mark FPU register as non-existent */ if (armv7m->fp_feature == FP_NONE) for (size_t idx = ARMV7M_FPU_FIRST_REG; idx <= ARMV7M_FPU_LAST_REG; idx++) armv7m->arm.core_cache->reg_list[idx].exist = false; - if (!armv7m->arm.is_armv8m) + if (armv7m->arm.arch != ARM_ARCH_V8M) for (size_t idx = ARMV8M_FIRST_REG; idx <= ARMV8M_LAST_REG; idx++) armv7m->arm.core_cache->reg_list[idx].exist = false; -- 2.30.2