From eb7683d635606d14785c0cb26a5a7496e0bfd23f Mon Sep 17 00:00:00 2001
From: vrokas <vrokas@4a8a32a2-be11-0410-ad9d-d568d2c75423>
Date: Mon, 12 Jan 2004 22:10:38 +0000
Subject: [PATCH] SDCC pic16 port device library initial version

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@3121 4a8a32a2-be11-0410-ad9d-d568d2c75423
---
 device/include/pic16/pic18f242.h | 116 +++++++++++++++
 device/include/pic16/pic18f248.h | 231 +++++++++++++++++++++++++++++
 device/include/pic16/pic18f252.h | 103 +++++++++++++
 device/include/pic16/pic18f258.h | 231 +++++++++++++++++++++++++++++
 device/include/pic16/pic18f442.h | 122 +++++++++++++++
 device/include/pic16/pic18f448.h | 245 +++++++++++++++++++++++++++++++
 device/include/pic16/pic18f452.h | 122 +++++++++++++++
 device/include/pic16/pic18f458.h | 245 +++++++++++++++++++++++++++++++
 8 files changed, 1415 insertions(+)
 create mode 100644 device/include/pic16/pic18f242.h
 create mode 100644 device/include/pic16/pic18f248.h
 create mode 100644 device/include/pic16/pic18f252.h
 create mode 100644 device/include/pic16/pic18f258.h
 create mode 100644 device/include/pic16/pic18f442.h
 create mode 100644 device/include/pic16/pic18f448.h
 create mode 100644 device/include/pic16/pic18f452.h
 create mode 100644 device/include/pic16/pic18f458.h

diff --git a/device/include/pic16/pic18f242.h b/device/include/pic16/pic18f242.h
new file mode 100644
index 00000000..77ab6674
--- /dev/null
+++ b/device/include/pic16/pic18f242.h
@@ -0,0 +1,116 @@
+
+/*
+ * pic18f242.h - 18F242 Device Library Header
+ *
+ * This file is part of the GNU PIC Library.
+ *
+ * January, 2004
+ * The GNU PIC Library is maintained by,
+ * 	Vangelis Rokas <vrokas@otenet.gr>
+ *
+ * $Id$
+ *
+ */
+
+#ifndef __PIC18F242_H__
+#define __PIC18F242_H__
+
+extern sfr at 0xfff TOSU;
+extern sfr at 0xffe TOSH;
+extern sfr at 0xffd TOSL;
+extern sfr at 0xffc STKPTR;
+extern sfr at 0xffb PCLATU;
+extern sfr at 0xffa PCLATH;
+extern sfr at 0xff9 PCL;
+extern sfr at 0xff8 TBLPTRU;
+extern sfr at 0xff7 TBLPTRH;
+extern sfr at 0xff6 TBLPTRL;
+extern sfr at 0xff5 TABLAT;
+extern sfr at 0xff4 PRODH;
+extern sfr at 0xff3 PRODL;
+extern sfr at 0xff2 INTCON;
+extern sfr at 0xfef INDF0;
+extern sfr at 0xfee POSTINC0;
+extern sfr at 0xfed POSTDEC0;
+extern sfr at 0xfec PREINC0;
+extern sfr at 0xfeb PLUSW0;
+extern sfr at 0xfea FSR0H;
+extern sfr at 0xfe9 FSR0L;
+extern sfr at 0xfe8 WREG;
+extern sfr at 0xfe7 INDF1;
+extern sfr at 0xfe6 POSTINC1;
+extern sfr at 0xfe5 POSTDEC1;
+extern sfr at 0xfe4 PREINC1;
+extern sfr at 0xfe3 PLUSW1;
+extern sfr at 0xfe2 FSR1H;
+extern sfr at 0xfe1 FSR1L;
+extern sfr at 0xfe0 BSR;
+extern sfr at 0xfdf INDF2;
+extern sfr at 0xfde POSTINC2;
+extern sfr at 0xfdd POSTDEC2;
+extern sfr at 0xfdc PREINC2;
+extern sfr at 0xfdb PLUSW2;
+extern sfr at 0xfda FSR2H;
+extern sfr at 0xfd9 FSR2L;
+extern sfr at 0xfd8 STATUS;
+extern sfr at 0xfd3 OSCCON;
+extern sfr at 0xfd2 LVDCON;
+extern sfr at 0xfd1 WDTCON;
+extern sfr at 0xfd0 RCON;
+extern sfr at 0xf9f IPR1;
+extern sfr at 0xf9e PIR1;
+extern sfr at 0xf9d PIE1;
+extern sfr at 0xff1 INTCON2;
+extern sfr at 0xff0 INTCON3;
+extern sfr at 0xfa2 IPR2;
+extern sfr at 0xfa1 PIR2;
+extern sfr at 0xfa0 PIE2;
+extern sfr at 0xf80 PORTA;
+extern sfr at 0xf89 LATA;
+extern sfr at 0xf92 TRISA;
+extern sfr at 0xf81 PORTB;
+extern sfr at 0xf93 TRISB;
+extern sfr at 0xf8a LATB;
+extern sfr at 0xf82 PORTC;
+extern sfr at 0xf8b LATC;
+extern sfr at 0xf94 TRISC;
+extern sfr at 0xfc4 ADRESH;
+extern sfr at 0xfc3 ADRESL;
+extern sfr at 0xfc2 ADCON0;
+extern sfr at 0xfc1 ADCON1;
+extern sfr at 0xfbf CCPR1H;
+extern sfr at 0xfbe CCPR1L;
+extern sfr at 0xfbd CCP1CON;
+extern sfr at 0xfbc CCPR2H;
+extern sfr at 0xfbb CCPR2L;
+extern sfr at 0xfba CCP2CON;
+extern sfr at 0xfa9 EEADR;
+extern sfr at 0xfa8 EEDATA;
+extern sfr at 0xfa7 EECON2;
+extern sfr at 0xfa6 EECON1;
+extern sfr at 0xfc9 SSPBUF;
+extern sfr at 0xfc8 SSPADD;
+extern sfr at 0xfc7 SSPSTAT;
+extern sfr at 0xfc6 SSPCON1;
+extern sfr at 0xfc5 SSPCON2;
+extern sfr at 0xfd7 TMR0H;
+extern sfr at 0xfd6 TMR0L;
+extern sfr at 0xfd5 T0CON;
+extern sfr at 0xfcf TMR1H;
+extern sfr at 0xfce TMR1L;
+extern sfr at 0xfcd T1CON;
+extern sfr at 0xfcc TMR2;
+extern sfr at 0xfcb PR2;
+extern sfr at 0xfca T2CON;
+extern sfr at 0xfb3 TMR3H;
+extern sfr at 0xfb2 TMR3L;
+extern sfr at 0xfb1 T3CON;
+extern sfr at 0xfaf SPBRG;
+extern sfr at 0xfae RCREG;
+extern sfr at 0xfad TXREG;
+extern sfr at 0xfac TXSTA;
+extern sfr at 0xfab RCSTA;
+
+
+#endif
+
diff --git a/device/include/pic16/pic18f248.h b/device/include/pic16/pic18f248.h
new file mode 100644
index 00000000..604ddbb3
--- /dev/null
+++ b/device/include/pic16/pic18f248.h
@@ -0,0 +1,231 @@
+
+/*
+ * pic18f248.h - 18F248 Device Library Header
+ *
+ * This file is part of the GNU PIC Library.
+ *
+ * January, 2004
+ * The GNU PIC Library is maintained by,
+ * 	Vangelis Rokas <vrokas@otenet.gr>
+ *
+ * $Id$
+ *
+ */
+
+#ifndef __PIC18F248_H__
+#define __PIC18F248_H__
+
+extern sfr at 0xfff TOSU;
+extern sfr at 0xffe TOSH;
+extern sfr at 0xffd TOSL;
+extern sfr at 0xffc STKPTR;
+extern sfr at 0xffb PCLATU;
+extern sfr at 0xffa PCLATH;
+extern sfr at 0xff9 PCL;
+extern sfr at 0xff8 TBLPTRU;
+extern sfr at 0xff7 TBLPTRH;
+extern sfr at 0xff6 TBLPTRL;
+extern sfr at 0xff5 TABLAT;
+extern sfr at 0xff4 PRODH;
+extern sfr at 0xff3 PRODL;
+extern sfr at 0xff2 INTCON;
+extern sfr at 0xfef INDF0;
+extern sfr at 0xfee POSTINC0;
+extern sfr at 0xfed POSTDEC0;
+extern sfr at 0xfec PREINC0;
+extern sfr at 0xfeb PLUSW0;
+extern sfr at 0xfea FSR0H;
+extern sfr at 0xfe9 FSR0L;
+extern sfr at 0xfe8 WREG;
+extern sfr at 0xfe7 INDF1;
+extern sfr at 0xfe6 POSTINC1;
+extern sfr at 0xfe5 POSTDEC1;
+extern sfr at 0xfe4 PREINC1;
+extern sfr at 0xfe3 PLUSW1;
+extern sfr at 0xfe2 FSR1H;
+extern sfr at 0xfe1 FSR1L;
+extern sfr at 0xfe0 BSR;
+extern sfr at 0xfdf INDF2;
+extern sfr at 0xfde POSTINC2;
+extern sfr at 0xfdd POSTDEC2;
+extern sfr at 0xfdc PREINC2;
+extern sfr at 0xfdb PLUSW2;
+extern sfr at 0xfda FSR2H;
+extern sfr at 0xfd9 FSR2L;
+extern sfr at 0xfd8 STATUS;
+extern sfr at 0xfd3 OSCCON;
+extern sfr at 0xfd2 LVDCON;
+extern sfr at 0xfd1 WDTCON;
+extern sfr at 0xfd0 RCON;
+extern sfr at 0xf9f IPR1;
+extern sfr at 0xf9e PIR1;
+extern sfr at 0xf9d PIE1;
+extern sfr at 0xff1 INTCON2;
+extern sfr at 0xff0 INTCON3;
+extern sfr at 0xfa2 IPR2;
+extern sfr at 0xfa1 PIR2;
+extern sfr at 0xfa0 PIE2;
+extern sfr at 0xfa5 IPR3;
+extern sfr at 0xfa4 PIR3;
+extern sfr at 0xfa3 PIE3;
+extern sfr at 0xf80 PORTA;
+extern sfr at 0xf89 LATA;
+extern sfr at 0xf92 TRISA;
+extern sfr at 0xf81 PORTB;
+extern sfr at 0xf93 TRISB;
+extern sfr at 0xf8a LATB;
+extern sfr at 0xf82 PORTC;
+extern sfr at 0xf8b LATC;
+extern sfr at 0xf94 TRISC;
+extern sfr at 0xfc4 ADRESH;
+extern sfr at 0xfc3 ADRESL;
+extern sfr at 0xfc2 ADCON0;
+extern sfr at 0xfc1 ADCON1;
+extern sfr at 0xf76 TXERRCNT;
+extern sfr at 0xf75 RXERRCNT;
+extern sfr at 0xf74 COMSTAT;
+extern sfr at 0xf73 CIOCON;
+extern sfr at 0xf72 BRGCON3;
+extern sfr at 0xf71 BRGCON2;
+extern sfr at 0xf70 BRGCON1;
+extern sfr at 0xf6f CANCON;
+extern sfr at 0xf6e CANSTAT;
+extern sfr at 0xf6d RXB0D7;
+extern sfr at 0xf6c RXB0D6;
+extern sfr at 0xf6b RXB0D5;
+extern sfr at 0xf6a RXB0D4;
+extern sfr at 0xf69 RXB0D3;
+extern sfr at 0xf68 RXB0D2;
+extern sfr at 0xf67 RXB0D1;
+extern sfr at 0xf66 RXB0D0;
+extern sfr at 0xf65 RXB0DLC;
+extern sfr at 0xf64 RXB0EIDL;
+extern sfr at 0xf63 RXB0EIDH;
+extern sfr at 0xf62 RXB0SIDL;
+extern sfr at 0xf61 RXB0SIDH;
+extern sfr at 0xf60 RXB0CON;
+extern sfr at 0xf5e CANSTATRO1;
+extern sfr at 0xf5d RXB1D7;
+extern sfr at 0xf5c RXB1D6;
+extern sfr at 0xf5b RXB1D5;
+extern sfr at 0xf5a RXB1D4;
+extern sfr at 0xf59 RXB1D3;
+extern sfr at 0xf58 RXB1D2;
+extern sfr at 0xf57 RXB1D1;
+extern sfr at 0xf56 RXB1D0;
+extern sfr at 0xf55 RXB1DLC;
+extern sfr at 0xf54 RXB1EIDL;
+extern sfr at 0xf53 RXB1EIDH;
+extern sfr at 0xf52 RXB1SIDL;
+extern sfr at 0xf51 RXB1SIDH;
+extern sfr at 0xf50 RXB1CON;
+extern sfr at 0xf4e CANSTATRO2;
+extern sfr at 0xf4d TXB0D7;
+extern sfr at 0xf4c TXB0D6;
+extern sfr at 0xf4b TXB0D5;
+extern sfr at 0xf4a TXB0D4;
+extern sfr at 0xf49 TXB0D3;
+extern sfr at 0xf48 TXB0D2;
+extern sfr at 0xf47 TXB0D1;
+extern sfr at 0xf46 TXB0D0;
+extern sfr at 0xf45 TXB0DLC;
+extern sfr at 0xf44 TXB0EIDL;
+extern sfr at 0xf43 TXB0EIDH;
+extern sfr at 0xf42 TXB0SIDL;
+extern sfr at 0xf41 TXB0SIDH;
+extern sfr at 0xf40 TXB0CON;
+extern sfr at 0xf3e CANSTATRO3;
+extern sfr at 0xf3d TXB1D7;
+extern sfr at 0xf3c TXB1D6;
+extern sfr at 0xf3b TXB1D5;
+extern sfr at 0xf3a TXB1D4;
+extern sfr at 0xf39 TXB1D3;
+extern sfr at 0xf38 TXB1D2;
+extern sfr at 0xf37 TXB1D1;
+extern sfr at 0xf36 TXB1D0;
+extern sfr at 0xf35 TXB1DLC;
+extern sfr at 0xf34 TXB1EIDL;
+extern sfr at 0xf33 TXB1EIDH;
+extern sfr at 0xf32 TXB1SIDL;
+extern sfr at 0xf31 TXB1SIDH;
+extern sfr at 0xf30 TXB1CON;
+extern sfr at 0xf2e CANSTATRO4;
+extern sfr at 0xf2d TXB2D7;
+extern sfr at 0xf2c TXB2D6;
+extern sfr at 0xf2b TXB2D5;
+extern sfr at 0xf2a TXB2D4;
+extern sfr at 0xf29 TXB2D3;
+extern sfr at 0xf28 TXB2D2;
+extern sfr at 0xf27 TXB2D1;
+extern sfr at 0xf26 TXB2D0;
+extern sfr at 0xf25 TXB2DLC;
+extern sfr at 0xf24 TXB2EIDL;
+extern sfr at 0xf23 TXB2EIDH;
+extern sfr at 0xf22 TXB2SIDL;
+extern sfr at 0xf21 TXB2SIDH;
+extern sfr at 0xf20 TXB2CON;
+extern sfr at 0xf1f RXM1EIDL;
+extern sfr at 0xf1e RXM1EIDH;
+extern sfr at 0xf1d RXM1SIDL;
+extern sfr at 0xf1c RXM1SIDH;
+extern sfr at 0xf1b RXM0EIDL;
+extern sfr at 0xf1a RXM0EIDH;
+extern sfr at 0xf19 RXM0SIDL;
+extern sfr at 0xf18 RXM0SIDH;
+extern sfr at 0xf17 RXF5EIDL;
+extern sfr at 0xf16 RXF5EIDH;
+extern sfr at 0xf15 RXF5SIDL;
+extern sfr at 0xf14 RXF5SIDH;
+extern sfr at 0xf13 RXF4EIDL;
+extern sfr at 0xf12 RXF4EIDH;
+extern sfr at 0xf11 RXF4SIDL;
+extern sfr at 0xf10 RXF4SIDH;
+extern sfr at 0xf0f RXF3EIDL;
+extern sfr at 0xf0e RXF3EIDH;
+extern sfr at 0xf0d RXF3SIDL;
+extern sfr at 0xf0c RXF3SIDH;
+extern sfr at 0xf0b RXF2EIDL;
+extern sfr at 0xf0a RXF2EIDH;
+extern sfr at 0xf09 RXF2SIDL;
+extern sfr at 0xf08 RXF2SIDH;
+extern sfr at 0xf07 RXF1EIDL;
+extern sfr at 0xf06 RXF1EIDH;
+extern sfr at 0xf05 RXF1SIDL;
+extern sfr at 0xf04 RXF1SIDH;
+extern sfr at 0xf03 RXF0EIDL;
+extern sfr at 0xf02 RXF0EIDH;
+extern sfr at 0xf01 RXF0SIDL;
+extern sfr at 0xf00 RXF0SIDH;
+extern sfr at 0xfbf CCPR1H;
+extern sfr at 0xfbe CCPR1L;
+extern sfr at 0xfbd CCP1CON;
+extern sfr at 0xfa9 EEADR;
+extern sfr at 0xfa8 EEDATA;
+extern sfr at 0xfa7 EECON2;
+extern sfr at 0xfa6 EECON1;
+extern sfr at 0xfc9 SSPBUF;
+extern sfr at 0xfc8 SSPADD;
+extern sfr at 0xfc7 SSPSTAT;
+extern sfr at 0xfc6 SSPCON1;
+extern sfr at 0xfc5 SSPCON2;
+extern sfr at 0xfd7 TMR0H;
+extern sfr at 0xfd6 TMR0L;
+extern sfr at 0xfd5 T0CON;
+extern sfr at 0xfcf TMR1H;
+extern sfr at 0xfce TMR1L;
+extern sfr at 0xfcd T1CON;
+extern sfr at 0xfcc TMR2;
+extern sfr at 0xfcb PR2;
+extern sfr at 0xfca T2CON;
+extern sfr at 0xfb3 TMR3H;
+extern sfr at 0xfb2 TMR3L;
+extern sfr at 0xfb1 T3CON;
+extern sfr at 0xfaf SPBRG;
+extern sfr at 0xfae RCREG;
+extern sfr at 0xfad TXREG;
+extern sfr at 0xfac TXSTA;
+extern sfr at 0xfab RCSTA;
+
+
+#endif
+
diff --git a/device/include/pic16/pic18f252.h b/device/include/pic16/pic18f252.h
new file mode 100644
index 00000000..fc2d453d
--- /dev/null
+++ b/device/include/pic16/pic18f252.h
@@ -0,0 +1,103 @@
+
+#ifndef __PIC18F252_H__
+#define __PIC18F252_H__
+
+extern sfr at 0xfff TOSU;
+extern sfr at 0xffe TOSH;
+extern sfr at 0xffd TOSL;
+extern sfr at 0xffc STKPTR;
+extern sfr at 0xffb PCLATU;
+extern sfr at 0xffa PCLATH;
+extern sfr at 0xff9 PCL;
+extern sfr at 0xff8 TBLPTRU;
+extern sfr at 0xff7 TBLPTRH;
+extern sfr at 0xff6 TBLPTRL;
+extern sfr at 0xff5 TABLAT;
+extern sfr at 0xff4 PRODH;
+extern sfr at 0xff3 PRODL;
+extern sfr at 0xff2 INTCON;
+extern sfr at 0xfef INDF0;
+extern sfr at 0xfee POSTINC0;
+extern sfr at 0xfed POSTDEC0;
+extern sfr at 0xfec PREINC0;
+extern sfr at 0xfeb PLUSW0;
+extern sfr at 0xfea FSR0H;
+extern sfr at 0xfe9 FSR0L;
+extern sfr at 0xfe8 WREG;
+extern sfr at 0xfe7 INDF1;
+extern sfr at 0xfe6 POSTINC1;
+extern sfr at 0xfe5 POSTDEC1;
+extern sfr at 0xfe4 PREINC1;
+extern sfr at 0xfe3 PLUSW1;
+extern sfr at 0xfe2 FSR1H;
+extern sfr at 0xfe1 FSR1L;
+extern sfr at 0xfe0 BSR;
+extern sfr at 0xfdf INDF2;
+extern sfr at 0xfde POSTINC2;
+extern sfr at 0xfdd POSTDEC2;
+extern sfr at 0xfdc PREINC2;
+extern sfr at 0xfdb PLUSW2;
+extern sfr at 0xfda FSR2H;
+extern sfr at 0xfd9 FSR2L;
+extern sfr at 0xfd8 STATUS;
+extern sfr at 0xfd3 OSCCON;
+extern sfr at 0xfd2 LVDCON;
+extern sfr at 0xfd1 WDTCON;
+extern sfr at 0xfd0 RCON;
+extern sfr at 0xf9f IPR1;
+extern sfr at 0xf9e PIR1;
+extern sfr at 0xf9d PIE1;
+extern sfr at 0xff1 INTCON2;
+extern sfr at 0xff0 INTCON3;
+extern sfr at 0xfa2 IPR2;
+extern sfr at 0xfa1 PIR2;
+extern sfr at 0xfa0 PIE2;
+extern sfr at 0xf80 PORTA;
+extern sfr at 0xf89 LATA;
+extern sfr at 0xf92 TRISA;
+extern sfr at 0xf81 PORTB;
+extern sfr at 0xf93 TRISB;
+extern sfr at 0xf8a LATB;
+extern sfr at 0xf82 PORTC;
+extern sfr at 0xf8b LATC;
+extern sfr at 0xf94 TRISC;
+extern sfr at 0xfc4 ADRESH;
+extern sfr at 0xfc3 ADRESL;
+extern sfr at 0xfc2 ADCON0;
+extern sfr at 0xfc1 ADCON1;
+extern sfr at 0xfbf CCPR1H;
+extern sfr at 0xfbe CCPR1L;
+extern sfr at 0xfbd CCP1CON;
+extern sfr at 0xfbc CCPR2H;
+extern sfr at 0xfbb CCPR2L;
+extern sfr at 0xfba CCP2CON;
+extern sfr at 0xfa9 EEADR;
+extern sfr at 0xfa8 EEDATA;
+extern sfr at 0xfa7 EECON2;
+extern sfr at 0xfa6 EECON1;
+extern sfr at 0xfc9 SSPBUF;
+extern sfr at 0xfc8 SSPADD;
+extern sfr at 0xfc7 SSPSTAT;
+extern sfr at 0xfc6 SSPCON1;
+extern sfr at 0xfc5 SSPCON2;
+extern sfr at 0xfd7 TMR0H;
+extern sfr at 0xfd6 TMR0L;
+extern sfr at 0xfd5 T0CON;
+extern sfr at 0xfcf TMR1H;
+extern sfr at 0xfce TMR1L;
+extern sfr at 0xfcd T1CON;
+extern sfr at 0xfcc TMR2;
+extern sfr at 0xfcb PR2;
+extern sfr at 0xfca T2CON;
+extern sfr at 0xfb3 TMR3H;
+extern sfr at 0xfb2 TMR3L;
+extern sfr at 0xfb1 T3CON;
+extern sfr at 0xfaf SPBRG;
+extern sfr at 0xfae RCREG;
+extern sfr at 0xfad TXREG;
+extern sfr at 0xfac TXSTA;
+extern sfr at 0xfab RCSTA;
+
+
+#endif
+
diff --git a/device/include/pic16/pic18f258.h b/device/include/pic16/pic18f258.h
new file mode 100644
index 00000000..b1265f02
--- /dev/null
+++ b/device/include/pic16/pic18f258.h
@@ -0,0 +1,231 @@
+
+/*
+ * pic18f258.h - 18F258 Device Library Header
+ *
+ * This file is part of the GNU PIC Library.
+ *
+ * January, 2004
+ * The GNU PIC Library is maintained by,
+ * 	Vangelis Rokas <vrokas@otenet.gr>
+ *
+ * $Id$
+ *
+ */
+
+#ifndef __PIC18F258_H__
+#define __PIC18F258_H__
+
+extern sfr at 0xfff TOSU;
+extern sfr at 0xffe TOSH;
+extern sfr at 0xffd TOSL;
+extern sfr at 0xffc STKPTR;
+extern sfr at 0xffb PCLATU;
+extern sfr at 0xffa PCLATH;
+extern sfr at 0xff9 PCL;
+extern sfr at 0xff8 TBLPTRU;
+extern sfr at 0xff7 TBLPTRH;
+extern sfr at 0xff6 TBLPTRL;
+extern sfr at 0xff5 TABLAT;
+extern sfr at 0xff4 PRODH;
+extern sfr at 0xff3 PRODL;
+extern sfr at 0xff2 INTCON;
+extern sfr at 0xfef INDF0;
+extern sfr at 0xfee POSTINC0;
+extern sfr at 0xfed POSTDEC0;
+extern sfr at 0xfec PREINC0;
+extern sfr at 0xfeb PLUSW0;
+extern sfr at 0xfea FSR0H;
+extern sfr at 0xfe9 FSR0L;
+extern sfr at 0xfe8 WREG;
+extern sfr at 0xfe7 INDF1;
+extern sfr at 0xfe6 POSTINC1;
+extern sfr at 0xfe5 POSTDEC1;
+extern sfr at 0xfe4 PREINC1;
+extern sfr at 0xfe3 PLUSW1;
+extern sfr at 0xfe2 FSR1H;
+extern sfr at 0xfe1 FSR1L;
+extern sfr at 0xfe0 BSR;
+extern sfr at 0xfdf INDF2;
+extern sfr at 0xfde POSTINC2;
+extern sfr at 0xfdd POSTDEC2;
+extern sfr at 0xfdc PREINC2;
+extern sfr at 0xfdb PLUSW2;
+extern sfr at 0xfda FSR2H;
+extern sfr at 0xfd9 FSR2L;
+extern sfr at 0xfd8 STATUS;
+extern sfr at 0xfd3 OSCCON;
+extern sfr at 0xfd2 LVDCON;
+extern sfr at 0xfd1 WDTCON;
+extern sfr at 0xfd0 RCON;
+extern sfr at 0xf9f IPR1;
+extern sfr at 0xf9e PIR1;
+extern sfr at 0xf9d PIE1;
+extern sfr at 0xff1 INTCON2;
+extern sfr at 0xff0 INTCON3;
+extern sfr at 0xfa2 IPR2;
+extern sfr at 0xfa1 PIR2;
+extern sfr at 0xfa0 PIE2;
+extern sfr at 0xfa5 IPR3;
+extern sfr at 0xfa4 PIR3;
+extern sfr at 0xfa3 PIE3;
+extern sfr at 0xf80 PORTA;
+extern sfr at 0xf89 LATA;
+extern sfr at 0xf92 TRISA;
+extern sfr at 0xf81 PORTB;
+extern sfr at 0xf93 TRISB;
+extern sfr at 0xf8a LATB;
+extern sfr at 0xf82 PORTC;
+extern sfr at 0xf8b LATC;
+extern sfr at 0xf94 TRISC;
+extern sfr at 0xfc4 ADRESH;
+extern sfr at 0xfc3 ADRESL;
+extern sfr at 0xfc2 ADCON0;
+extern sfr at 0xfc1 ADCON1;
+extern sfr at 0xf76 TXERRCNT;
+extern sfr at 0xf75 RXERRCNT;
+extern sfr at 0xf74 COMSTAT;
+extern sfr at 0xf73 CIOCON;
+extern sfr at 0xf72 BRGCON3;
+extern sfr at 0xf71 BRGCON2;
+extern sfr at 0xf70 BRGCON1;
+extern sfr at 0xf6f CANCON;
+extern sfr at 0xf6e CANSTAT;
+extern sfr at 0xf6d RXB0D7;
+extern sfr at 0xf6c RXB0D6;
+extern sfr at 0xf6b RXB0D5;
+extern sfr at 0xf6a RXB0D4;
+extern sfr at 0xf69 RXB0D3;
+extern sfr at 0xf68 RXB0D2;
+extern sfr at 0xf67 RXB0D1;
+extern sfr at 0xf66 RXB0D0;
+extern sfr at 0xf65 RXB0DLC;
+extern sfr at 0xf64 RXB0EIDL;
+extern sfr at 0xf63 RXB0EIDH;
+extern sfr at 0xf62 RXB0SIDL;
+extern sfr at 0xf61 RXB0SIDH;
+extern sfr at 0xf60 RXB0CON;
+extern sfr at 0xf5e CANSTATRO1;
+extern sfr at 0xf5d RXB1D7;
+extern sfr at 0xf5c RXB1D6;
+extern sfr at 0xf5b RXB1D5;
+extern sfr at 0xf5a RXB1D4;
+extern sfr at 0xf59 RXB1D3;
+extern sfr at 0xf58 RXB1D2;
+extern sfr at 0xf57 RXB1D1;
+extern sfr at 0xf56 RXB1D0;
+extern sfr at 0xf55 RXB1DLC;
+extern sfr at 0xf54 RXB1EIDL;
+extern sfr at 0xf53 RXB1EIDH;
+extern sfr at 0xf52 RXB1SIDL;
+extern sfr at 0xf51 RXB1SIDH;
+extern sfr at 0xf50 RXB1CON;
+extern sfr at 0xf4e CANSTATRO2;
+extern sfr at 0xf4d TXB0D7;
+extern sfr at 0xf4c TXB0D6;
+extern sfr at 0xf4b TXB0D5;
+extern sfr at 0xf4a TXB0D4;
+extern sfr at 0xf49 TXB0D3;
+extern sfr at 0xf48 TXB0D2;
+extern sfr at 0xf47 TXB0D1;
+extern sfr at 0xf46 TXB0D0;
+extern sfr at 0xf45 TXB0DLC;
+extern sfr at 0xf44 TXB0EIDL;
+extern sfr at 0xf43 TXB0EIDH;
+extern sfr at 0xf42 TXB0SIDL;
+extern sfr at 0xf41 TXB0SIDH;
+extern sfr at 0xf40 TXB0CON;
+extern sfr at 0xf3e CANSTATRO3;
+extern sfr at 0xf3d TXB1D7;
+extern sfr at 0xf3c TXB1D6;
+extern sfr at 0xf3b TXB1D5;
+extern sfr at 0xf3a TXB1D4;
+extern sfr at 0xf39 TXB1D3;
+extern sfr at 0xf38 TXB1D2;
+extern sfr at 0xf37 TXB1D1;
+extern sfr at 0xf36 TXB1D0;
+extern sfr at 0xf35 TXB1DLC;
+extern sfr at 0xf34 TXB1EIDL;
+extern sfr at 0xf33 TXB1EIDH;
+extern sfr at 0xf32 TXB1SIDL;
+extern sfr at 0xf31 TXB1SIDH;
+extern sfr at 0xf30 TXB1CON;
+extern sfr at 0xf2e CANSTATRO4;
+extern sfr at 0xf2d TXB2D7;
+extern sfr at 0xf2c TXB2D6;
+extern sfr at 0xf2b TXB2D5;
+extern sfr at 0xf2a TXB2D4;
+extern sfr at 0xf29 TXB2D3;
+extern sfr at 0xf28 TXB2D2;
+extern sfr at 0xf27 TXB2D1;
+extern sfr at 0xf26 TXB2D0;
+extern sfr at 0xf25 TXB2DLC;
+extern sfr at 0xf24 TXB2EIDL;
+extern sfr at 0xf23 TXB2EIDH;
+extern sfr at 0xf22 TXB2SIDL;
+extern sfr at 0xf21 TXB2SIDH;
+extern sfr at 0xf20 TXB2CON;
+extern sfr at 0xf1f RXM1EIDL;
+extern sfr at 0xf1e RXM1EIDH;
+extern sfr at 0xf1d RXM1SIDL;
+extern sfr at 0xf1c RXM1SIDH;
+extern sfr at 0xf1b RXM0EIDL;
+extern sfr at 0xf1a RXM0EIDH;
+extern sfr at 0xf19 RXM0SIDL;
+extern sfr at 0xf18 RXM0SIDH;
+extern sfr at 0xf17 RXF5EIDL;
+extern sfr at 0xf16 RXF5EIDH;
+extern sfr at 0xf15 RXF5SIDL;
+extern sfr at 0xf14 RXF5SIDH;
+extern sfr at 0xf13 RXF4EIDL;
+extern sfr at 0xf12 RXF4EIDH;
+extern sfr at 0xf11 RXF4SIDL;
+extern sfr at 0xf10 RXF4SIDH;
+extern sfr at 0xf0f RXF3EIDL;
+extern sfr at 0xf0e RXF3EIDH;
+extern sfr at 0xf0d RXF3SIDL;
+extern sfr at 0xf0c RXF3SIDH;
+extern sfr at 0xf0b RXF2EIDL;
+extern sfr at 0xf0a RXF2EIDH;
+extern sfr at 0xf09 RXF2SIDL;
+extern sfr at 0xf08 RXF2SIDH;
+extern sfr at 0xf07 RXF1EIDL;
+extern sfr at 0xf06 RXF1EIDH;
+extern sfr at 0xf05 RXF1SIDL;
+extern sfr at 0xf04 RXF1SIDH;
+extern sfr at 0xf03 RXF0EIDL;
+extern sfr at 0xf02 RXF0EIDH;
+extern sfr at 0xf01 RXF0SIDL;
+extern sfr at 0xf00 RXF0SIDH;
+extern sfr at 0xfbf CCPR1H;
+extern sfr at 0xfbe CCPR1L;
+extern sfr at 0xfbd CCP1CON;
+extern sfr at 0xfa9 EEADR;
+extern sfr at 0xfa8 EEDATA;
+extern sfr at 0xfa7 EECON2;
+extern sfr at 0xfa6 EECON1;
+extern sfr at 0xfc9 SSPBUF;
+extern sfr at 0xfc8 SSPADD;
+extern sfr at 0xfc7 SSPSTAT;
+extern sfr at 0xfc6 SSPCON1;
+extern sfr at 0xfc5 SSPCON2;
+extern sfr at 0xfd7 TMR0H;
+extern sfr at 0xfd6 TMR0L;
+extern sfr at 0xfd5 T0CON;
+extern sfr at 0xfcf TMR1H;
+extern sfr at 0xfce TMR1L;
+extern sfr at 0xfcd T1CON;
+extern sfr at 0xfcc TMR2;
+extern sfr at 0xfcb PR2;
+extern sfr at 0xfca T2CON;
+extern sfr at 0xfb3 TMR3H;
+extern sfr at 0xfb2 TMR3L;
+extern sfr at 0xfb1 T3CON;
+extern sfr at 0xfaf SPBRG;
+extern sfr at 0xfae RCREG;
+extern sfr at 0xfad TXREG;
+extern sfr at 0xfac TXSTA;
+extern sfr at 0xfab RCSTA;
+
+
+#endif
+
diff --git a/device/include/pic16/pic18f442.h b/device/include/pic16/pic18f442.h
new file mode 100644
index 00000000..120a0b03
--- /dev/null
+++ b/device/include/pic16/pic18f442.h
@@ -0,0 +1,122 @@
+
+/*
+ * pic18f442.h - 18F442 Device Library Header
+ *
+ * This file is part of the GNU PIC Library.
+ *
+ * January, 2004
+ * The GNU PIC Library is maintained by,
+ * 	Vangelis Rokas <vrokas@otenet.gr>
+ *
+ * $Id$
+ *
+ */
+
+#ifndef __PIC18F442_H__
+#define __PIC18F442_H__
+
+extern sfr at 0xfff TOSU;
+extern sfr at 0xffe TOSH;
+extern sfr at 0xffd TOSL;
+extern sfr at 0xffc STKPTR;
+extern sfr at 0xffb PCLATU;
+extern sfr at 0xffa PCLATH;
+extern sfr at 0xff9 PCL;
+extern sfr at 0xff8 TBLPTRU;
+extern sfr at 0xff7 TBLPTRH;
+extern sfr at 0xff6 TBLPTRL;
+extern sfr at 0xff5 TABLAT;
+extern sfr at 0xff4 PRODH;
+extern sfr at 0xff3 PRODL;
+extern sfr at 0xff2 INTCON;
+extern sfr at 0xfef INDF0;
+extern sfr at 0xfee POSTINC0;
+extern sfr at 0xfed POSTDEC0;
+extern sfr at 0xfec PREINC0;
+extern sfr at 0xfeb PLUSW0;
+extern sfr at 0xfea FSR0H;
+extern sfr at 0xfe9 FSR0L;
+extern sfr at 0xfe8 WREG;
+extern sfr at 0xfe7 INDF1;
+extern sfr at 0xfe6 POSTINC1;
+extern sfr at 0xfe5 POSTDEC1;
+extern sfr at 0xfe4 PREINC1;
+extern sfr at 0xfe3 PLUSW1;
+extern sfr at 0xfe2 FSR1H;
+extern sfr at 0xfe1 FSR1L;
+extern sfr at 0xfe0 BSR;
+extern sfr at 0xfdf INDF2;
+extern sfr at 0xfde POSTINC2;
+extern sfr at 0xfdd POSTDEC2;
+extern sfr at 0xfdc PREINC2;
+extern sfr at 0xfdb PLUSW2;
+extern sfr at 0xfda FSR2H;
+extern sfr at 0xfd9 FSR2L;
+extern sfr at 0xfd8 STATUS;
+extern sfr at 0xfd3 OSCCON;
+extern sfr at 0xfd2 LVDCON;
+extern sfr at 0xfd1 WDTCON;
+extern sfr at 0xfd0 RCON;
+extern sfr at 0xf9f IPR1;
+extern sfr at 0xf9e PIR1;
+extern sfr at 0xf9d PIE1;
+extern sfr at 0xff1 INTCON2;
+extern sfr at 0xff0 INTCON3;
+extern sfr at 0xfa2 IPR2;
+extern sfr at 0xfa1 PIR2;
+extern sfr at 0xfa0 PIE2;
+extern sfr at 0xf80 PORTA;
+extern sfr at 0xf89 LATA;
+extern sfr at 0xf92 TRISA;
+extern sfr at 0xf81 PORTB;
+extern sfr at 0xf93 TRISB;
+extern sfr at 0xf8a LATB;
+extern sfr at 0xf82 PORTC;
+extern sfr at 0xf8b LATC;
+extern sfr at 0xf94 TRISC;
+extern sfr at 0xf83 PORTD;
+extern sfr at 0xf8c LATD;
+extern sfr at 0xf95 TRISD;
+extern sfr at 0xf84 PORTE;
+extern sfr at 0xf8d LATE;
+extern sfr at 0xf96 TRISE;
+extern sfr at 0xfc4 ADRESH;
+extern sfr at 0xfc3 ADRESL;
+extern sfr at 0xfc2 ADCON0;
+extern sfr at 0xfc1 ADCON1;
+extern sfr at 0xfbf CCPR1H;
+extern sfr at 0xfbe CCPR1L;
+extern sfr at 0xfbd CCP1CON;
+extern sfr at 0xfbc CCPR2H;
+extern sfr at 0xfbb CCPR2L;
+extern sfr at 0xfba CCP2CON;
+extern sfr at 0xfa9 EEADR;
+extern sfr at 0xfa8 EEDATA;
+extern sfr at 0xfa7 EECON2;
+extern sfr at 0xfa6 EECON1;
+extern sfr at 0xfc9 SSPBUF;
+extern sfr at 0xfc8 SSPADD;
+extern sfr at 0xfc7 SSPSTAT;
+extern sfr at 0xfc6 SSPCON1;
+extern sfr at 0xfc5 SSPCON2;
+extern sfr at 0xfd7 TMR0H;
+extern sfr at 0xfd6 TMR0L;
+extern sfr at 0xfd5 T0CON;
+extern sfr at 0xfcf TMR1H;
+extern sfr at 0xfce TMR1L;
+extern sfr at 0xfcd T1CON;
+extern sfr at 0xfcc TMR2;
+extern sfr at 0xfcb PR2;
+extern sfr at 0xfca T2CON;
+extern sfr at 0xfb3 TMR3H;
+extern sfr at 0xfb2 TMR3L;
+extern sfr at 0xfb1 T3CON;
+extern sfr at 0xfaf SPBRG;
+extern sfr at 0xfae RCREG;
+extern sfr at 0xfad TXREG;
+extern sfr at 0xfac TXSTA;
+extern sfr at 0xfab RCSTA;
+
+
+#endif
+
diff --git a/device/include/pic16/pic18f448.h b/device/include/pic16/pic18f448.h
new file mode 100644
index 00000000..02a3922a
--- /dev/null
+++ b/device/include/pic16/pic18f448.h
@@ -0,0 +1,245 @@
+
+/*
+ * pic18f448.h - 18F448 Device Library Header
+ *
+ * This file is part of the GNU PIC Library.
+ *
+ * January, 2004
+ * The GNU PIC Library is maintained by,
+ * 	Vangelis Rokas <vrokas@otenet.gr>
+ *
+ * $Id$
+ *
+ */
+
+#ifndef __PIC18F448_H__
+#define __PIC18F448_H__
+
+extern sfr at 0xfff TOSU;
+extern sfr at 0xffe TOSH;
+extern sfr at 0xffd TOSL;
+extern sfr at 0xffc STKPTR;
+extern sfr at 0xffb PCLATU;
+extern sfr at 0xffa PCLATH;
+extern sfr at 0xff9 PCL;
+extern sfr at 0xff8 TBLPTRU;
+extern sfr at 0xff7 TBLPTRH;
+extern sfr at 0xff6 TBLPTRL;
+extern sfr at 0xff5 TABLAT;
+extern sfr at 0xff4 PRODH;
+extern sfr at 0xff3 PRODL;
+extern sfr at 0xff2 INTCON;
+extern sfr at 0xfef INDF0;
+extern sfr at 0xfee POSTINC0;
+extern sfr at 0xfed POSTDEC0;
+extern sfr at 0xfec PREINC0;
+extern sfr at 0xfeb PLUSW0;
+extern sfr at 0xfea FSR0H;
+extern sfr at 0xfe9 FSR0L;
+extern sfr at 0xfe8 WREG;
+extern sfr at 0xfe7 INDF1;
+extern sfr at 0xfe6 POSTINC1;
+extern sfr at 0xfe5 POSTDEC1;
+extern sfr at 0xfe4 PREINC1;
+extern sfr at 0xfe3 PLUSW1;
+extern sfr at 0xfe2 FSR1H;
+extern sfr at 0xfe1 FSR1L;
+extern sfr at 0xfe0 BSR;
+extern sfr at 0xfdf INDF2;
+extern sfr at 0xfde POSTINC2;
+extern sfr at 0xfdd POSTDEC2;
+extern sfr at 0xfdc PREINC2;
+extern sfr at 0xfdb PLUSW2;
+extern sfr at 0xfda FSR2H;
+extern sfr at 0xfd9 FSR2L;
+extern sfr at 0xfd8 STATUS;
+extern sfr at 0xfd3 OSCCON;
+extern sfr at 0xfd2 LVDCON;
+extern sfr at 0xfd1 WDTCON;
+extern sfr at 0xfd0 RCON;
+extern sfr at 0xf9f IPR1;
+extern sfr at 0xf9e PIR1;
+extern sfr at 0xf9d PIE1;
+extern sfr at 0xff1 INTCON2;
+extern sfr at 0xff0 INTCON3;
+extern sfr at 0xfa2 IPR2;
+extern sfr at 0xfa1 PIR2;
+extern sfr at 0xfa0 PIE2;
+extern sfr at 0xfa5 IPR3;
+extern sfr at 0xfa4 PIR3;
+extern sfr at 0xfa3 PIE3;
+extern sfr at 0xf80 PORTA;
+extern sfr at 0xf89 LATA;
+extern sfr at 0xf92 TRISA;
+extern sfr at 0xf81 PORTB;
+extern sfr at 0xf93 TRISB;
+extern sfr at 0xf8a LATB;
+extern sfr at 0xf82 PORTC;
+extern sfr at 0xf8b LATC;
+extern sfr at 0xf94 TRISC;
+extern sfr at 0xf83 PORTD;
+extern sfr at 0xf8c LATD;
+extern sfr at 0xf95 TRISD;
+extern sfr at 0xf84 PORTE;
+extern sfr at 0xf8d LATE;
+extern sfr at 0xf96 TRISE;
+extern sfr at 0xfc4 ADRESH;
+extern sfr at 0xfc3 ADRESL;
+extern sfr at 0xfc2 ADCON0;
+extern sfr at 0xfc1 ADCON1;
+extern sfr at 0xf76 TXERRCNT;
+extern sfr at 0xf75 RXERRCNT;
+extern sfr at 0xf74 COMSTAT;
+extern sfr at 0xf73 CIOCON;
+extern sfr at 0xf72 BRGCON3;
+extern sfr at 0xf71 BRGCON2;
+extern sfr at 0xf70 BRGCON1;
+extern sfr at 0xf6f CANCON;
+extern sfr at 0xf6e CANSTAT;
+extern sfr at 0xf6d RXB0D7;
+extern sfr at 0xf6c RXB0D6;
+extern sfr at 0xf6b RXB0D5;
+extern sfr at 0xf6a RXB0D4;
+extern sfr at 0xf69 RXB0D3;
+extern sfr at 0xf68 RXB0D2;
+extern sfr at 0xf67 RXB0D1;
+extern sfr at 0xf66 RXB0D0;
+extern sfr at 0xf65 RXB0DLC;
+extern sfr at 0xf64 RXB0EIDL;
+extern sfr at 0xf63 RXB0EIDH;
+extern sfr at 0xf62 RXB0SIDL;
+extern sfr at 0xf61 RXB0SIDH;
+extern sfr at 0xf60 RXB0CON;
+extern sfr at 0xf5e CANSTATRO1;
+extern sfr at 0xf5d RXB1D7;
+extern sfr at 0xf5c RXB1D6;
+extern sfr at 0xf5b RXB1D5;
+extern sfr at 0xf5a RXB1D4;
+extern sfr at 0xf59 RXB1D3;
+extern sfr at 0xf58 RXB1D2;
+extern sfr at 0xf57 RXB1D1;
+extern sfr at 0xf56 RXB1D0;
+extern sfr at 0xf55 RXB1DLC;
+extern sfr at 0xf54 RXB1EIDL;
+extern sfr at 0xf53 RXB1EIDH;
+extern sfr at 0xf52 RXB1SIDL;
+extern sfr at 0xf51 RXB1SIDH;
+extern sfr at 0xf50 RXB1CON;
+extern sfr at 0xf4e CANSTATRO2;
+extern sfr at 0xf4d TXB0D7;
+extern sfr at 0xf4c TXB0D6;
+extern sfr at 0xf4b TXB0D5;
+extern sfr at 0xf4a TXB0D4;
+extern sfr at 0xf49 TXB0D3;
+extern sfr at 0xf48 TXB0D2;
+extern sfr at 0xf47 TXB0D1;
+extern sfr at 0xf46 TXB0D0;
+extern sfr at 0xf45 TXB0DLC;
+extern sfr at 0xf44 TXB0EIDL;
+extern sfr at 0xf43 TXB0EIDH;
+extern sfr at 0xf42 TXB0SIDL;
+extern sfr at 0xf41 TXB0SIDH;
+extern sfr at 0xf40 TXB0CON;
+extern sfr at 0xf3e CANSTATRO3;
+extern sfr at 0xf3d TXB1D7;
+extern sfr at 0xf3c TXB1D6;
+extern sfr at 0xf3b TXB1D5;
+extern sfr at 0xf3a TXB1D4;
+extern sfr at 0xf39 TXB1D3;
+extern sfr at 0xf38 TXB1D2;
+extern sfr at 0xf37 TXB1D1;
+extern sfr at 0xf36 TXB1D0;
+extern sfr at 0xf35 TXB1DLC;
+extern sfr at 0xf34 TXB1EIDL;
+extern sfr at 0xf33 TXB1EIDH;
+extern sfr at 0xf32 TXB1SIDL;
+extern sfr at 0xf31 TXB1SIDH;
+extern sfr at 0xf30 TXB1CON;
+extern sfr at 0xf2e CANSTATRO4;
+extern sfr at 0xf2d TXB2D7;
+extern sfr at 0xf2c TXB2D6;
+extern sfr at 0xf2b TXB2D5;
+extern sfr at 0xf2a TXB2D4;
+extern sfr at 0xf29 TXB2D3;
+extern sfr at 0xf28 TXB2D2;
+extern sfr at 0xf27 TXB2D1;
+extern sfr at 0xf26 TXB2D0;
+extern sfr at 0xf25 TXB2DLC;
+extern sfr at 0xf24 TXB2EIDL;
+extern sfr at 0xf23 TXB2EIDH;
+extern sfr at 0xf22 TXB2SIDL;
+extern sfr at 0xf21 TXB2SIDH;
+extern sfr at 0xf20 TXB2CON;
+extern sfr at 0xf1f RXM1EIDL;
+extern sfr at 0xf1e RXM1EIDH;
+extern sfr at 0xf1d RXM1SIDL;
+extern sfr at 0xf1c RXM1SIDH;
+extern sfr at 0xf1b RXM0EIDL;
+extern sfr at 0xf1a RXM0EIDH;
+extern sfr at 0xf19 RXM0SIDL;
+extern sfr at 0xf18 RXM0SIDH;
+extern sfr at 0xf17 RXF5EIDL;
+extern sfr at 0xf16 RXF5EIDH;
+extern sfr at 0xf15 RXF5SIDL;
+extern sfr at 0xf14 RXF5SIDH;
+extern sfr at 0xf13 RXF4EIDL;
+extern sfr at 0xf12 RXF4EIDH;
+extern sfr at 0xf11 RXF4SIDL;
+extern sfr at 0xf10 RXF4SIDH;
+extern sfr at 0xf0f RXF3EIDL;
+extern sfr at 0xf0e RXF3EIDH;
+extern sfr at 0xf0d RXF3SIDL;
+extern sfr at 0xf0c RXF3SIDH;
+extern sfr at 0xf0b RXF2EIDL;
+extern sfr at 0xf0a RXF2EIDH;
+extern sfr at 0xf09 RXF2SIDL;
+extern sfr at 0xf08 RXF2SIDH;
+extern sfr at 0xf07 RXF1EIDL;
+extern sfr at 0xf06 RXF1EIDH;
+extern sfr at 0xf05 RXF1SIDL;
+extern sfr at 0xf04 RXF1SIDH;
+extern sfr at 0xf03 RXF0EIDL;
+extern sfr at 0xf02 RXF0EIDH;
+extern sfr at 0xf01 RXF0SIDL;
+extern sfr at 0xf00 RXF0SIDH;
+extern sfr at 0xfbf CCPR1H;
+extern sfr at 0xfbe CCPR1L;
+extern sfr at 0xfbd CCP1CON;
+extern sfr at 0xfbc ECCPR1H;
+extern sfr at 0xfbb ECCPR1L;
+extern sfr at 0xfba ECCP1CON;
+extern sfr at 0xfb7 ECCP1DEL;
+extern sfr at 0xfb6 ECCPAS;
+extern sfr at 0xfb5 CVRCON;
+extern sfr at 0xfb4 CMCON;
+extern sfr at 0xfa9 EEADR;
+extern sfr at 0xfa8 EEDATA;
+extern sfr at 0xfa7 EECON2;
+extern sfr at 0xfa6 EECON1;
+extern sfr at 0xfb0 PSPCON;
+extern sfr at 0xfc9 SSPBUF;
+extern sfr at 0xfc8 SSPADD;
+extern sfr at 0xfc7 SSPSTAT;
+extern sfr at 0xfc6 SSPCON1;
+extern sfr at 0xfc5 SSPCON2;
+extern sfr at 0xfd7 TMR0H;
+extern sfr at 0xfd6 TMR0L;
+extern sfr at 0xfd5 T0CON;
+extern sfr at 0xfcf TMR1H;
+extern sfr at 0xfce TMR1L;
+extern sfr at 0xfcd T1CON;
+extern sfr at 0xfcc TMR2;
+extern sfr at 0xfcb PR2;
+extern sfr at 0xfca T2CON;
+extern sfr at 0xfb3 TMR3H;
+extern sfr at 0xfb2 TMR3L;
+extern sfr at 0xfb1 T3CON;
+extern sfr at 0xfaf SPBRG;
+extern sfr at 0xfae RCREG;
+extern sfr at 0xfad TXREG;
+extern sfr at 0xfac TXSTA;
+extern sfr at 0xfab RCSTA;
+
+
+#endif
+
diff --git a/device/include/pic16/pic18f452.h b/device/include/pic16/pic18f452.h
new file mode 100644
index 00000000..acefe1da
--- /dev/null
+++ b/device/include/pic16/pic18f452.h
@@ -0,0 +1,122 @@
+
+/*
+ * pic18f452.h - 18F452 Device Library Header
+ *
+ * This file is part of the GNU PIC Library.
+ *
+ * January, 2004
+ * The GNU PIC Library is maintained by,
+ * 	Vangelis Rokas <vrokas@otenet.gr>
+ *
+ * $Id$
+ *
+ */
+
+#ifndef __PIC18F452_H__
+#define __PIC18F452_H__
+
+extern sfr at 0xfff TOSU;
+extern sfr at 0xffe TOSH;
+extern sfr at 0xffd TOSL;
+extern sfr at 0xffc STKPTR;
+extern sfr at 0xffb PCLATU;
+extern sfr at 0xffa PCLATH;
+extern sfr at 0xff9 PCL;
+extern sfr at 0xff8 TBLPTRU;
+extern sfr at 0xff7 TBLPTRH;
+extern sfr at 0xff6 TBLPTRL;
+extern sfr at 0xff5 TABLAT;
+extern sfr at 0xff4 PRODH;
+extern sfr at 0xff3 PRODL;
+extern sfr at 0xff2 INTCON;
+extern sfr at 0xfef INDF0;
+extern sfr at 0xfee POSTINC0;
+extern sfr at 0xfed POSTDEC0;
+extern sfr at 0xfec PREINC0;
+extern sfr at 0xfeb PLUSW0;
+extern sfr at 0xfea FSR0H;
+extern sfr at 0xfe9 FSR0L;
+extern sfr at 0xfe8 WREG;
+extern sfr at 0xfe7 INDF1;
+extern sfr at 0xfe6 POSTINC1;
+extern sfr at 0xfe5 POSTDEC1;
+extern sfr at 0xfe4 PREINC1;
+extern sfr at 0xfe3 PLUSW1;
+extern sfr at 0xfe2 FSR1H;
+extern sfr at 0xfe1 FSR1L;
+extern sfr at 0xfe0 BSR;
+extern sfr at 0xfdf INDF2;
+extern sfr at 0xfde POSTINC2;
+extern sfr at 0xfdd POSTDEC2;
+extern sfr at 0xfdc PREINC2;
+extern sfr at 0xfdb PLUSW2;
+extern sfr at 0xfda FSR2H;
+extern sfr at 0xfd9 FSR2L;
+extern sfr at 0xfd8 STATUS;
+extern sfr at 0xfd3 OSCCON;
+extern sfr at 0xfd2 LVDCON;
+extern sfr at 0xfd1 WDTCON;
+extern sfr at 0xfd0 RCON;
+extern sfr at 0xf9f IPR1;
+extern sfr at 0xf9e PIR1;
+extern sfr at 0xf9d PIE1;
+extern sfr at 0xff1 INTCON2;
+extern sfr at 0xff0 INTCON3;
+extern sfr at 0xfa2 IPR2;
+extern sfr at 0xfa1 PIR2;
+extern sfr at 0xfa0 PIE2;
+extern sfr at 0xf80 PORTA;
+extern sfr at 0xf89 LATA;
+extern sfr at 0xf92 TRISA;
+extern sfr at 0xf81 PORTB;
+extern sfr at 0xf93 TRISB;
+extern sfr at 0xf8a LATB;
+extern sfr at 0xf82 PORTC;
+extern sfr at 0xf8b LATC;
+extern sfr at 0xf94 TRISC;
+extern sfr at 0xf83 PORTD;
+extern sfr at 0xf8c LATD;
+extern sfr at 0xf95 TRISD;
+extern sfr at 0xf84 PORTE;
+extern sfr at 0xf8d LATE;
+extern sfr at 0xf96 TRISE;
+extern sfr at 0xfc4 ADRESH;
+extern sfr at 0xfc3 ADRESL;
+extern sfr at 0xfc2 ADCON0;
+extern sfr at 0xfc1 ADCON1;
+extern sfr at 0xfbf CCPR1H;
+extern sfr at 0xfbe CCPR1L;
+extern sfr at 0xfbd CCP1CON;
+extern sfr at 0xfbc CCPR2H;
+extern sfr at 0xfbb CCPR2L;
+extern sfr at 0xfba CCP2CON;
+extern sfr at 0xfa9 EEADR;
+extern sfr at 0xfa8 EEDATA;
+extern sfr at 0xfa7 EECON2;
+extern sfr at 0xfa6 EECON1;
+extern sfr at 0xfc9 SSPBUF;
+extern sfr at 0xfc8 SSPADD;
+extern sfr at 0xfc7 SSPSTAT;
+extern sfr at 0xfc6 SSPCON1;
+extern sfr at 0xfc5 SSPCON2;
+extern sfr at 0xfd7 TMR0H;
+extern sfr at 0xfd6 TMR0L;
+extern sfr at 0xfd5 T0CON;
+extern sfr at 0xfcf TMR1H;
+extern sfr at 0xfce TMR1L;
+extern sfr at 0xfcd T1CON;
+extern sfr at 0xfcc TMR2;
+extern sfr at 0xfcb PR2;
+extern sfr at 0xfca T2CON;
+extern sfr at 0xfb3 TMR3H;
+extern sfr at 0xfb2 TMR3L;
+extern sfr at 0xfb1 T3CON;
+extern sfr at 0xfaf SPBRG;
+extern sfr at 0xfae RCREG;
+extern sfr at 0xfad TXREG;
+extern sfr at 0xfac TXSTA;
+extern sfr at 0xfab RCSTA;
+
+
+#endif
+
diff --git a/device/include/pic16/pic18f458.h b/device/include/pic16/pic18f458.h
new file mode 100644
index 00000000..06497dd8
--- /dev/null
+++ b/device/include/pic16/pic18f458.h
@@ -0,0 +1,245 @@
+
+/*
+ * pic18f458.c - 18F458 Device Library Header
+ *
+ * This file is part of the GNU PIC Library.
+ *
+ * January, 2004
+ * The GNU PIC Library is maintained by,
+ * 	Vangelis Rokas <vrokas@otenet.gr>
+ *
+ * $Id$
+ *
+ */
+
+#ifndef __PIC18F458_H__
+#define __PIC18F458_H__
+
+extern sfr at 0xfff TOSU;
+extern sfr at 0xffe TOSH;
+extern sfr at 0xffd TOSL;
+extern sfr at 0xffc STKPTR;
+extern sfr at 0xffb PCLATU;
+extern sfr at 0xffa PCLATH;
+extern sfr at 0xff9 PCL;
+extern sfr at 0xff8 TBLPTRU;
+extern sfr at 0xff7 TBLPTRH;
+extern sfr at 0xff6 TBLPTRL;
+extern sfr at 0xff5 TABLAT;
+extern sfr at 0xff4 PRODH;
+extern sfr at 0xff3 PRODL;
+extern sfr at 0xff2 INTCON;
+extern sfr at 0xfef INDF0;
+extern sfr at 0xfee POSTINC0;
+extern sfr at 0xfed POSTDEC0;
+extern sfr at 0xfec PREINC0;
+extern sfr at 0xfeb PLUSW0;
+extern sfr at 0xfea FSR0H;
+extern sfr at 0xfe9 FSR0L;
+extern sfr at 0xfe8 WREG;
+extern sfr at 0xfe7 INDF1;
+extern sfr at 0xfe6 POSTINC1;
+extern sfr at 0xfe5 POSTDEC1;
+extern sfr at 0xfe4 PREINC1;
+extern sfr at 0xfe3 PLUSW1;
+extern sfr at 0xfe2 FSR1H;
+extern sfr at 0xfe1 FSR1L;
+extern sfr at 0xfe0 BSR;
+extern sfr at 0xfdf INDF2;
+extern sfr at 0xfde POSTINC2;
+extern sfr at 0xfdd POSTDEC2;
+extern sfr at 0xfdc PREINC2;
+extern sfr at 0xfdb PLUSW2;
+extern sfr at 0xfda FSR2H;
+extern sfr at 0xfd9 FSR2L;
+extern sfr at 0xfd8 STATUS;
+extern sfr at 0xfd3 OSCCON;
+extern sfr at 0xfd2 LVDCON;
+extern sfr at 0xfd1 WDTCON;
+extern sfr at 0xfd0 RCON;
+extern sfr at 0xf9f IPR1;
+extern sfr at 0xf9e PIR1;
+extern sfr at 0xf9d PIE1;
+extern sfr at 0xff1 INTCON2;
+extern sfr at 0xff0 INTCON3;
+extern sfr at 0xfa2 IPR2;
+extern sfr at 0xfa1 PIR2;
+extern sfr at 0xfa0 PIE2;
+extern sfr at 0xfa5 IPR3;
+extern sfr at 0xfa4 PIR3;
+extern sfr at 0xfa3 PIE3;
+extern sfr at 0xf80 PORTA;
+extern sfr at 0xf89 LATA;
+extern sfr at 0xf92 TRISA;
+extern sfr at 0xf81 PORTB;
+extern sfr at 0xf93 TRISB;
+extern sfr at 0xf8a LATB;
+extern sfr at 0xf82 PORTC;
+extern sfr at 0xf8b LATC;
+extern sfr at 0xf94 TRISC;
+extern sfr at 0xf83 PORTD;
+extern sfr at 0xf8c LATD;
+extern sfr at 0xf95 TRISD;
+extern sfr at 0xf84 PORTE;
+extern sfr at 0xf8d LATE;
+extern sfr at 0xf96 TRISE;
+extern sfr at 0xfc4 ADRESH;
+extern sfr at 0xfc3 ADRESL;
+extern sfr at 0xfc2 ADCON0;
+extern sfr at 0xfc1 ADCON1;
+extern sfr at 0xf76 TXERRCNT;
+extern sfr at 0xf75 RXERRCNT;
+extern sfr at 0xf74 COMSTAT;
+extern sfr at 0xf73 CIOCON;
+extern sfr at 0xf72 BRGCON3;
+extern sfr at 0xf71 BRGCON2;
+extern sfr at 0xf70 BRGCON1;
+extern sfr at 0xf6f CANCON;
+extern sfr at 0xf6e CANSTAT;
+extern sfr at 0xf6d RXB0D7;
+extern sfr at 0xf6c RXB0D6;
+extern sfr at 0xf6b RXB0D5;
+extern sfr at 0xf6a RXB0D4;
+extern sfr at 0xf69 RXB0D3;
+extern sfr at 0xf68 RXB0D2;
+extern sfr at 0xf67 RXB0D1;
+extern sfr at 0xf66 RXB0D0;
+extern sfr at 0xf65 RXB0DLC;
+extern sfr at 0xf64 RXB0EIDL;
+extern sfr at 0xf63 RXB0EIDH;
+extern sfr at 0xf62 RXB0SIDL;
+extern sfr at 0xf61 RXB0SIDH;
+extern sfr at 0xf60 RXB0CON;
+extern sfr at 0xf5e CANSTATRO1;
+extern sfr at 0xf5d RXB1D7;
+extern sfr at 0xf5c RXB1D6;
+extern sfr at 0xf5b RXB1D5;
+extern sfr at 0xf5a RXB1D4;
+extern sfr at 0xf59 RXB1D3;
+extern sfr at 0xf58 RXB1D2;
+extern sfr at 0xf57 RXB1D1;
+extern sfr at 0xf56 RXB1D0;
+extern sfr at 0xf55 RXB1DLC;
+extern sfr at 0xf54 RXB1EIDL;
+extern sfr at 0xf53 RXB1EIDH;
+extern sfr at 0xf52 RXB1SIDL;
+extern sfr at 0xf51 RXB1SIDH;
+extern sfr at 0xf50 RXB1CON;
+extern sfr at 0xf4e CANSTATRO2;
+extern sfr at 0xf4d TXB0D7;
+extern sfr at 0xf4c TXB0D6;
+extern sfr at 0xf4b TXB0D5;
+extern sfr at 0xf4a TXB0D4;
+extern sfr at 0xf49 TXB0D3;
+extern sfr at 0xf48 TXB0D2;
+extern sfr at 0xf47 TXB0D1;
+extern sfr at 0xf46 TXB0D0;
+extern sfr at 0xf45 TXB0DLC;
+extern sfr at 0xf44 TXB0EIDL;
+extern sfr at 0xf43 TXB0EIDH;
+extern sfr at 0xf42 TXB0SIDL;
+extern sfr at 0xf41 TXB0SIDH;
+extern sfr at 0xf40 TXB0CON;
+extern sfr at 0xf3e CANSTATRO3;
+extern sfr at 0xf3d TXB1D7;
+extern sfr at 0xf3c TXB1D6;
+extern sfr at 0xf3b TXB1D5;
+extern sfr at 0xf3a TXB1D4;
+extern sfr at 0xf39 TXB1D3;
+extern sfr at 0xf38 TXB1D2;
+extern sfr at 0xf37 TXB1D1;
+extern sfr at 0xf36 TXB1D0;
+extern sfr at 0xf35 TXB1DLC;
+extern sfr at 0xf34 TXB1EIDL;
+extern sfr at 0xf33 TXB1EIDH;
+extern sfr at 0xf32 TXB1SIDL;
+extern sfr at 0xf31 TXB1SIDH;
+extern sfr at 0xf30 TXB1CON;
+extern sfr at 0xf2e CANSTATRO4;
+extern sfr at 0xf2d TXB2D7;
+extern sfr at 0xf2c TXB2D6;
+extern sfr at 0xf2b TXB2D5;
+extern sfr at 0xf2a TXB2D4;
+extern sfr at 0xf29 TXB2D3;
+extern sfr at 0xf28 TXB2D2;
+extern sfr at 0xf27 TXB2D1;
+extern sfr at 0xf26 TXB2D0;
+extern sfr at 0xf25 TXB2DLC;
+extern sfr at 0xf24 TXB2EIDL;
+extern sfr at 0xf23 TXB2EIDH;
+extern sfr at 0xf22 TXB2SIDL;
+extern sfr at 0xf21 TXB2SIDH;
+extern sfr at 0xf20 TXB2CON;
+extern sfr at 0xf1f RXM1EIDL;
+extern sfr at 0xf1e RXM1EIDH;
+extern sfr at 0xf1d RXM1SIDL;
+extern sfr at 0xf1c RXM1SIDH;
+extern sfr at 0xf1b RXM0EIDL;
+extern sfr at 0xf1a RXM0EIDH;
+extern sfr at 0xf19 RXM0SIDL;
+extern sfr at 0xf18 RXM0SIDH;
+extern sfr at 0xf17 RXF5EIDL;
+extern sfr at 0xf16 RXF5EIDH;
+extern sfr at 0xf15 RXF5SIDL;
+extern sfr at 0xf14 RXF5SIDH;
+extern sfr at 0xf13 RXF4EIDL;
+extern sfr at 0xf12 RXF4EIDH;
+extern sfr at 0xf11 RXF4SIDL;
+extern sfr at 0xf10 RXF4SIDH;
+extern sfr at 0xf0f RXF3EIDL;
+extern sfr at 0xf0e RXF3EIDH;
+extern sfr at 0xf0d RXF3SIDL;
+extern sfr at 0xf0c RXF3SIDH;
+extern sfr at 0xf0b RXF2EIDL;
+extern sfr at 0xf0a RXF2EIDH;
+extern sfr at 0xf09 RXF2SIDL;
+extern sfr at 0xf08 RXF2SIDH;
+extern sfr at 0xf07 RXF1EIDL;
+extern sfr at 0xf06 RXF1EIDH;
+extern sfr at 0xf05 RXF1SIDL;
+extern sfr at 0xf04 RXF1SIDH;
+extern sfr at 0xf03 RXF0EIDL;
+extern sfr at 0xf02 RXF0EIDH;
+extern sfr at 0xf01 RXF0SIDL;
+extern sfr at 0xf00 RXF0SIDH;
+extern sfr at 0xfbf CCPR1H;
+extern sfr at 0xfbe CCPR1L;
+extern sfr at 0xfbd CCP1CON;
+extern sfr at 0xfb5 CVRCON;
+extern sfr at 0xfb4 CMCON;
+extern sfr at 0xfbc ECCPR1H;
+extern sfr at 0xfbb ECCPR1L;
+extern sfr at 0xfba ECCP1CON;
+extern sfr at 0xfb7 ECCP1DEL;
+extern sfr at 0xfb6 ECCPAS;
+extern sfr at 0xfa9 EEADR;
+extern sfr at 0xfa8 EEDATA;
+extern sfr at 0xfa7 EECON2;
+extern sfr at 0xfa6 EECON1;
+extern sfr at 0xfb0 PSPCON;
+extern sfr at 0xfc9 SSPBUF;
+extern sfr at 0xfc8 SSPADD;
+extern sfr at 0xfc7 SSPSTAT;
+extern sfr at 0xfc6 SSPCON1;
+extern sfr at 0xfc5 SSPCON2;
+extern sfr at 0xfd7 TMR0H;
+extern sfr at 0xfd6 TMR0L;
+extern sfr at 0xfd5 T0CON;
+extern sfr at 0xfcf TMR1H;
+extern sfr at 0xfce TMR1L;
+extern sfr at 0xfcd T1CON;
+extern sfr at 0xfcc TMR2;
+extern sfr at 0xfcb PR2;
+extern sfr at 0xfca T2CON;
+extern sfr at 0xfb3 TMR3H;
+extern sfr at 0xfb2 TMR3L;
+extern sfr at 0xfb1 T3CON;
+extern sfr at 0xfaf SPBRG;
+extern sfr at 0xfae RCREG;
+extern sfr at 0xfad TXREG;
+extern sfr at 0xfac TXSTA;
+extern sfr at 0xfab RCSTA;
+
+
+#endif
+
-- 
2.47.2