From e5caf64b0706299b02f7b8ac272930fcad75e0df Mon Sep 17 00:00:00 2001 From: vrokas Date: Thu, 29 Jul 2004 22:57:20 +0000 Subject: [PATCH] * src/SDCCmem.c (allocGlobal): don't turn S_REGISTER storage class to S_FIXED for pic16 port and when symbol is not in level 0, allocate for S_REGISTER storage class and pic16 port, too, * src/pic16/device.h: prototype for checkSym, * src/pic16/device.c (pic16_dump_access, checkSym): NEW, * (pic16_assignConfigWordValue): test the value and the mask to validate that the value is suitable for the configuration word, * src/pic16/glue.c (pic16_printIvalFuncPtr): use 'externs' to collect extern declared symbols, don't emit symbol twice, check first if symbol is in publics set first, * src/pic16/main.c (_pic16_keywords[]): added keyword 'register', * added command line '--fstack' which enables an experimental feature for stack access, too buggy to be used yet... * src/pic16/ralloc.c (pic16_accessregWithName): NEW, * (pic16_allocDirReg): when register has storage class S_REGISTER allocate in pic16_dynAccessRegs, * device/include/pic16/pic18f????.h: modified configuration word naming convention, words started as CONFIG0H but should be CONFIG1H git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@3411 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- ChangeLog | 21 ++ device/include/pic16/pic18f1220.h | 270 ++++++++++----------- device/include/pic16/pic18f2220.h | 286 +++++++++++----------- device/include/pic16/pic18f242.h | 238 +++++++++--------- device/include/pic16/pic18f248.h | 228 +++++++++--------- device/include/pic16/pic18f252.h | 286 +++++++++++----------- device/include/pic16/pic18f258.h | 276 ++++++++++----------- device/include/pic16/pic18f442.h | 238 +++++++++--------- device/include/pic16/pic18f448.h | 228 +++++++++--------- device/include/pic16/pic18f452.h | 286 +++++++++++----------- device/include/pic16/pic18f458.h | 276 ++++++++++----------- device/include/pic16/pic18f6520.h | 300 +++++++++++------------ device/include/pic16/pic18f6620.h | 286 +++++++++++----------- device/include/pic16/pic18f6680.h | 326 ++++++++++++------------- device/include/pic16/pic18f6720.h | 364 ++++++++++++++-------------- device/include/pic16/pic18f8520.h | 312 ++++++++++++------------ device/include/pic16/pic18f8620.h | 308 ++++++++++++------------ device/include/pic16/pic18f8680.h | 348 +++++++++++++-------------- device/include/pic16/pic18f8720.h | 384 +++++++++++++++--------------- src/SDCCmem.c | 2 + src/pic16/device.c | 69 +++++- src/pic16/device.h | 7 +- src/pic16/glue.c | 27 +-- src/pic16/main.c | 19 +- src/pic16/main.h | 1 + src/pic16/ralloc.c | 79 +++++- src/pic16/ralloc.h | 1 + 27 files changed, 2808 insertions(+), 2658 deletions(-) diff --git a/ChangeLog b/ChangeLog index 936fd9a1..507494f7 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,24 @@ +2004-07-30 Vangelis Rokas + + * src/SDCCmem.c (allocGlobal): don't turn S_REGISTER storage class + to S_FIXED for pic16 port and when symbol is not in level 0, + allocate for S_REGISTER storage class and pic16 port, too, + * src/pic16/device.h: prototype for checkSym, + * src/pic16/device.c (pic16_dump_access, checkSym): NEW, + * (pic16_assignConfigWordValue): test the value and the mask to + validate that the value is suitable for the configuration word, + * src/pic16/glue.c (pic16_printIvalFuncPtr): use 'externs' to + collect extern declared symbols, don't emit symbol twice, check + first if symbol is in publics set first, + * src/pic16/main.c (_pic16_keywords[]): added keyword 'register', + * added command line '--fstack' which enables an experimental + feature for stack access, too buggy to be used yet... + * src/pic16/ralloc.c (pic16_accessregWithName): NEW, + * (pic16_allocDirReg): when register has storage class S_REGISTER + allocate in pic16_dynAccessRegs, + * device/include/pic16/pic18f????.h: modified configuration word + naming convention, words started as CONFIG0H but should be CONFIG1H + 2004-07-29 Maarten Brock * device/include/mcs51reg.h: fixed bug 970993 diff --git a/device/include/pic16/pic18f1220.h b/device/include/pic16/pic18f1220.h index ee7f9238..28227447 100644 --- a/device/include/pic16/pic18f1220.h +++ b/device/include/pic16/pic18f1220.h @@ -647,141 +647,141 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_11XX_0H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */ -#define _OSC_101X_0H 0xFA /* 101X EXT RC-CLKOUT on RA6 */ -#define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_0H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */ -#define _OSC_INT_Port_on_RA6_Port_on_RA7_0H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */ -#define _OSC_EXT_Port_on_RA6_0H 0xF7 /* EXT RC-Port_on_RA6 */ -#define _OSC_HS_PLL_0H 0xF6 /* HS-PLL enabled freq=4xFosc1 */ -#define _OSC_EC_PORT_0H 0xF5 /* EC-Port on RA6 */ -#define _OSC_EC_CLKOUT_0H 0xF4 /* EC-CLKOUT on RA6 */ -#define _OSC_EXT_CLKOUT_on_RA6_0H 0xF3 /* EXT RC-CLKOUT_on_RA6 */ -#define _OSC_HS_0H 0xF2 /* HS */ -#define _OSC_XT_0H 0xF1 /* XT */ -#define _OSC_LP_0H 0xF0 /* LP */ - -/* Fail Safe Clock Monitor Enable 0H options */ -#define _FCMEN_OFF_0H 0xBF /* Disabled */ -#define _FCMEN_ON_0H 0xFF /* Enabled */ - -/* Internal External Switch Over 0H options */ -#define _IESO_OFF_0H 0x7F /* Disabled */ -#define _IESO_ON_0H 0xFF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_DISABLED_CONTROLLED_1H 0xFE /* Disabled-Controlled by SWDTEN bit */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_32768_1H 0xFF /* 1:32768 */ -#define _WDTPS_1_16384_1H 0xFD /* 1:16384 */ -#define _WDTPS_1_8192_1H 0xFB /* 1:8192 */ -#define _WDTPS_1_4096_1H 0xF9 /* 1:4096 */ -#define _WDTPS_1_2048_1H 0xF7 /* 1:2048 */ -#define _WDTPS_1_1024_1H 0xF5 /* 1:1024 */ -#define _WDTPS_1_512_1H 0xF3 /* 1:512 */ -#define _WDTPS_1_256_1H 0xF1 /* 1:256 */ -#define _WDTPS_1_128_1H 0xEF /* 1:128 */ -#define _WDTPS_1_64_1H 0xED /* 1:64 */ -#define _WDTPS_1_32_1H 0xEB /* 1:32 */ -#define _WDTPS_1_16_1H 0xE9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xE7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xE5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xE3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xE1 /* 1:1 */ - -/* MCLR enable 2H options */ -#define _MCLRE_MCLR_enabled_RA5_input_dis_2H 0xFF /* MCLR enabled__RA5_input_disabled */ -#define _MCLRE_MCLR_disabled_RA5_input_en_2H 0x7F /* MCLR disabled__RA5_input_enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Code Protect 000200-0007FF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 000800-000FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-007FF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 00800-00FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-007FF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 000800-00FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_11XX_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */ +#define _OSC_101X_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */ +#define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_1H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */ +#define _OSC_INT_Port_on_RA6_Port_on_RA7_1H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */ +#define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */ +#define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */ +#define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */ +#define _OSC_EC_CLKOUT_1H 0xF4 /* EC-CLKOUT on RA6 */ +#define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */ +#define _OSC_HS_1H 0xF2 /* HS */ +#define _OSC_XT_1H 0xF1 /* XT */ +#define _OSC_LP_1H 0xF0 /* LP */ + +/* Fail Safe Clock Monitor Enable 1H options */ +#define _FCMEN_OFF_1H 0xBF /* Disabled */ +#define _FCMEN_ON_1H 0xFF /* Enabled */ + +/* Internal External Switch Over 1H options */ +#define _IESO_OFF_1H 0x7F /* Disabled */ +#define _IESO_ON_1H 0xFF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_32768_2H 0xFF /* 1:32768 */ +#define _WDTPS_1_16384_2H 0xFD /* 1:16384 */ +#define _WDTPS_1_8192_2H 0xFB /* 1:8192 */ +#define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */ +#define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */ +#define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */ +#define _WDTPS_1_512_2H 0xF3 /* 1:512 */ +#define _WDTPS_1_256_2H 0xF1 /* 1:256 */ +#define _WDTPS_1_128_2H 0xEF /* 1:128 */ +#define _WDTPS_1_64_2H 0xED /* 1:64 */ +#define _WDTPS_1_32_2H 0xEB /* 1:32 */ +#define _WDTPS_1_16_2H 0xE9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xE7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xE5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xE3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xE1 /* 1:1 */ + +/* MCLR enable 3H options */ +#define _MCLRE_MCLR_enabled_RA5_input_dis_3H 0xFF /* MCLR enabled__RA5_input_disabled */ +#define _MCLRE_MCLR_disabled_RA5_input_en_3H 0x7F /* MCLR disabled__RA5_input_enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Code Protect 000200-0007FF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 000800-000FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-007FF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 00800-00FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-007FF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 000800-00FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f2220.h b/device/include/pic16/pic18f2220.h index 19b53091..48dd054f 100644 --- a/device/include/pic16/pic18f2220.h +++ b/device/include/pic16/pic18f2220.h @@ -831,149 +831,149 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_11XX_0H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */ -#define _OSC_101X_0H 0xFA /* 101X EXT RC-CLKOUT on RA6 */ -#define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_0H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */ -#define _OSC_INT_Port_on_RA6_Port_on_RA7_0H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */ -#define _OSC_EXT_Port_on_RA6_0H 0xF7 /* EXT RC-Port_on_RA6 */ -#define _OSC_HS_PLL_0H 0xF6 /* HS-PLL enabled freq=4xFosc1 */ -#define _OSC_EC_PORT_0H 0xF5 /* EC-Port on RA6 */ -#define _OSC_EC_CLKOUT_0H 0xF4 /* EC-CLKOUT on RA6 */ -#define _OSC_EXT_CLKOUT_on_RA6_0H 0xF3 /* EXT RC-CLKOUT_on_RA6 */ -#define _OSC_HS_0H 0xF2 /* HS */ -#define _OSC_XT_0H 0xF1 /* XT */ -#define _OSC_LP_0H 0xF0 /* LP */ - -/* Fail Safe Clock Monitor Enable 0H options */ -#define _FCMEN_OFF_0H 0xBF /* Disabled */ -#define _FCMEN_ON_0H 0xFF /* Enabled */ - -/* Internal External Switch Over 0H options */ -#define _IESO_OFF_0H 0x7F /* Disabled */ -#define _IESO_ON_0H 0xFF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_DISABLED_CONTROLLED_1H 0xFE /* Disabled-Controlled by SWDTEN bit */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_32768_1H 0xFF /* 1:32768 */ -#define _WDTPS_1_16384_1H 0xFD /* 1:16384 */ -#define _WDTPS_1_8192_1H 0xFB /* 1:8192 */ -#define _WDTPS_1_4096_1H 0xF9 /* 1:4096 */ -#define _WDTPS_1_2048_1H 0xF7 /* 1:2048 */ -#define _WDTPS_1_1024_1H 0xF5 /* 1:1024 */ -#define _WDTPS_1_512_1H 0xF3 /* 1:512 */ -#define _WDTPS_1_256_1H 0xF1 /* 1:256 */ -#define _WDTPS_1_128_1H 0xEF /* 1:128 */ -#define _WDTPS_1_64_1H 0xED /* 1:64 */ -#define _WDTPS_1_32_1H 0xEB /* 1:32 */ -#define _WDTPS_1_16_1H 0xE9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xE7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xE5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xE3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xE1 /* 1:1 */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RB3_2H 0xFE /* RB3 */ - -/* PortB A/D Enable 2H options */ -#define _PBADEN_PORTB_4_0__analog_inputs_on_RSET_2H 0xFF /* PORTB<4:0> configured as analog_inputs_on_RESET */ -#define _PBADEN_PORTB_4_0__digital_I_O_on_REST_2H 0xFD /* PORTB<4:0> configured as digital_I_O_on_RESET */ - -/* MCLR enable 2H options */ -#define _MCLRE_MCLR_Enabled_RE3_Disabled_2H 0xFF /* MCLR Enabled_RE3_Disabled */ -#define _MCLRE_MCLR_Disabled_RE3_Enabled_2H 0x7F /* MCLR Disabled__RE3_Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Code Protect 000200-0007FF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 000800-000FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-007FF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 00800-00FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-007FF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 00800-00FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_11XX_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */ +#define _OSC_101X_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */ +#define _OSC_INT_CLKOUT_on_RA6_Port_on_RA7_1H 0xF9 /* INT RC-CLKOUT_on_RA6_Port_on_RA7 */ +#define _OSC_INT_Port_on_RA6_Port_on_RA7_1H 0xF8 /* INT RC-Port_on_RA6_Port_on_RA7 */ +#define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */ +#define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */ +#define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */ +#define _OSC_EC_CLKOUT_1H 0xF4 /* EC-CLKOUT on RA6 */ +#define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */ +#define _OSC_HS_1H 0xF2 /* HS */ +#define _OSC_XT_1H 0xF1 /* XT */ +#define _OSC_LP_1H 0xF0 /* LP */ + +/* Fail Safe Clock Monitor Enable 1H options */ +#define _FCMEN_OFF_1H 0xBF /* Disabled */ +#define _FCMEN_ON_1H 0xFF /* Enabled */ + +/* Internal External Switch Over 1H options */ +#define _IESO_OFF_1H 0x7F /* Disabled */ +#define _IESO_ON_1H 0xFF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_32768_2H 0xFF /* 1:32768 */ +#define _WDTPS_1_16384_2H 0xFD /* 1:16384 */ +#define _WDTPS_1_8192_2H 0xFB /* 1:8192 */ +#define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */ +#define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */ +#define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */ +#define _WDTPS_1_512_2H 0xF3 /* 1:512 */ +#define _WDTPS_1_256_2H 0xF1 /* 1:256 */ +#define _WDTPS_1_128_2H 0xEF /* 1:128 */ +#define _WDTPS_1_64_2H 0xED /* 1:64 */ +#define _WDTPS_1_32_2H 0xEB /* 1:32 */ +#define _WDTPS_1_16_2H 0xE9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xE7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xE5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xE3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xE1 /* 1:1 */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RB3_3H 0xFE /* RB3 */ + +/* PortB A/D Enable 3H options */ +#define _PBADEN_PORTB_4_0__analog_inputs_on_RSET_3H 0xFF /* PORTB<4:0> configured as analog_inputs_on_RESET */ +#define _PBADEN_PORTB_4_0__digital_I_O_on_REST_3H 0xFD /* PORTB<4:0> configured as digital_I_O_on_RESET */ + +/* MCLR enable 3H options */ +#define _MCLRE_MCLR_Enabled_RE3_Disabled_3H 0xFF /* MCLR Enabled_RE3_Disabled */ +#define _MCLRE_MCLR_Disabled_RE3_Enabled_3H 0x7F /* MCLR Disabled__RE3_Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Code Protect 000200-0007FF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 000800-000FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-007FF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 00800-00FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-007FF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 00800-00FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f242.h b/device/include/pic16/pic18f242.h index 6d60bfcf..d1560a4e 100644 --- a/device/include/pic16/pic18f242.h +++ b/device/include/pic16/pic18f242.h @@ -767,125 +767,125 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RB3_2H 0xFE /* RB3 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RB3_3H 0xFE /* RB3 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f248.h b/device/include/pic16/pic18f248.h index dc2cb4b2..f8d9ee88 100644 --- a/device/include/pic16/pic18f248.h +++ b/device/include/pic16/pic18f248.h @@ -2517,120 +2517,120 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f252.h b/device/include/pic16/pic18f252.h index 10279bd9..f4551ef1 100644 --- a/device/include/pic16/pic18f252.h +++ b/device/include/pic16/pic18f252.h @@ -767,149 +767,149 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RB3_2H 0xFE /* RB3 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 04000-05FFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 06000-07FFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 04000-05FFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 06000-07FFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 04000-05FFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 06000-07FFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RB3_3H 0xFE /* RB3 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 04000-05FFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 06000-07FFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 04000-05FFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 06000-07FFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 04000-05FFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 06000-07FFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f258.h b/device/include/pic16/pic18f258.h index 99edb0df..8e358936 100644 --- a/device/include/pic16/pic18f258.h +++ b/device/include/pic16/pic18f258.h @@ -2517,144 +2517,144 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 04000-05FFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 06000-07FFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 04000-05FFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 06000-07FFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 04000-05FFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 06000-07FFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 04000-05FFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 06000-07FFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 04000-05FFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 06000-07FFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 04000-05FFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 06000-07FFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f442.h b/device/include/pic16/pic18f442.h index f05f522d..6efc0297 100644 --- a/device/include/pic16/pic18f442.h +++ b/device/include/pic16/pic18f442.h @@ -896,125 +896,125 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RB3_2H 0xFE /* RB3 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RB3_3H 0xFE /* RB3 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f448.h b/device/include/pic16/pic18f448.h index 9bdf5d52..310dbf8e 100644 --- a/device/include/pic16/pic18f448.h +++ b/device/include/pic16/pic18f448.h @@ -2744,120 +2744,120 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f452.h b/device/include/pic16/pic18f452.h index 2ba20b7c..fa495374 100644 --- a/device/include/pic16/pic18f452.h +++ b/device/include/pic16/pic18f452.h @@ -896,149 +896,149 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RB3_2H 0xFE /* RB3 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 04000-05FFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 06000-07FFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 04000-05FFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 06000-07FFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 04000-05FFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 06000-07FFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RB3_3H 0xFE /* RB3 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 04000-05FFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 06000-07FFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 04000-05FFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 06000-07FFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 04000-05FFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 06000-07FFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f458.h b/device/include/pic16/pic18f458.h index cdbea4c7..3af1d0c9 100644 --- a/device/include/pic16/pic18f458.h +++ b/device/include/pic16/pic18f458.h @@ -2744,144 +2744,144 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 04000-05FFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 06000-07FFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 04000-05FFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 06000-07FFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 04000-05FFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 06000-07FFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 04000-05FFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 06000-07FFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 04000-05FFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 06000-07FFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 04000-05FFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 06000-07FFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f6520.h b/device/include/pic16/pic18f6520.h index ed2e3ee2..7e03f800 100644 --- a/device/include/pic16/pic18f6520.h +++ b/device/include/pic16/pic18f6520.h @@ -1228,156 +1228,156 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2L 0x300004 -#define __CONFIG2H 0x300005 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_5V_1L 0xFF /* 2.5V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* External Bus Wait 2L options */ -#define _WAIT_OFF_2L 0xFF /* Disabled */ -#define _WAIT_ON_2L 0x7F /* Enabled */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RE7_MICROCONTROLLER__RB3_2H 0xFE /* RE7(Microcontroller)/RB3 */ - -/* Timer1 OSC 2H options */ -#define _T1OSCMX_LOW_2H 0xFD /* Low Power */ - -/* Low Voltage Program 2H options */ -#define _LVP_ON_2H 0xFF /* Enabled */ -#define _LVP_OFF_2H 0xFB /* Disabled */ - -/* Background Debug 2H options */ -#define _BACKBUG_OFF_2H 0xFF /* Disabled */ -#define _BACKBUG_ON_2H 0x7F /* Enabled */ - -/* Stack Overflow Reset 2H options */ -#define _STVR_ON_2H 0xFF /* Enabled */ -#define _STVR_OFF_2H 0xFE /* Disabled */ - -/* Code Protect 00800-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 04000-05FFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 06000-07FFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00800-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 04000-05FFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 06000-07FFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00800-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 04000-05FFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 06000-07FFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3L 0x300004 +#define __CONFIG3H 0x300005 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_5V_2L 0xFF /* 2.5V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* External Bus Wait 3L options */ +#define _WAIT_OFF_3L 0xFF /* Disabled */ +#define _WAIT_ON_3L 0x7F /* Enabled */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RE7_MICROCONTROLLER__RB3_3H 0xFE /* RE7(Microcontroller)/RB3 */ + +/* Timer1 OSC 3H options */ +#define _T1OSCMX_LOW_3H 0xFD /* Low Power */ + +/* Low Voltage Program 3H options */ +#define _LVP_ON_3H 0xFF /* Enabled */ +#define _LVP_OFF_3H 0xFB /* Disabled */ + +/* Background Debug 3H options */ +#define _BACKBUG_OFF_3H 0xFF /* Disabled */ +#define _BACKBUG_ON_3H 0x7F /* Enabled */ + +/* Stack Overflow Reset 3H options */ +#define _STVR_ON_3H 0xFF /* Enabled */ +#define _STVR_OFF_3H 0xFE /* Disabled */ + +/* Code Protect 00800-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 04000-05FFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 06000-07FFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00800-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 04000-05FFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 06000-07FFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00800-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 04000-05FFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 06000-07FFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f6620.h b/device/include/pic16/pic18f6620.h index b99135d6..ad55e4a0 100644 --- a/device/include/pic16/pic18f6620.h +++ b/device/include/pic16/pic18f6620.h @@ -1212,149 +1212,149 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_5V_1L 0xFF /* 2.5V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RE7_2H 0xFE /* RE7 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-03FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 04000-07FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 08000-0BFFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 0C000-0FFFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-03FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 04000-07FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 08000-0BFFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 0C000-0FFFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-03FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 04000-07FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 08000-0BFFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 0C000-0FFFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_5V_2L 0xFF /* 2.5V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RE7_3H 0xFE /* RE7 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-03FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 04000-07FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 08000-0BFFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 0C000-0FFFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-03FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 04000-07FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 08000-0BFFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 0C000-0FFFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-03FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 04000-07FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 08000-0BFFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 0C000-0FFFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f6680.h b/device/include/pic16/pic18f6680.h index 810f5a79..b8f0d075 100644 --- a/device/include/pic16/pic18f6680.h +++ b/device/include/pic16/pic18f6680.h @@ -1702,169 +1702,169 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_CLKOUT_0H 0xFF /* RC-CLKOUT on RA6 */ -#define _OSC_HS_SOFTWARE_0H 0xFE /* HS-Software enabled PLL */ -#define _OSC_EC_CLKOUT_Software_nabld_PLL_0H 0xFD /* EC-CLKOUT on RA6,Software_enabled_PLL */ -#define _OSC_EC_CLKOUT_PLL_enabld_frq_4xFosc1_0H 0xFC /* EC-CLKOUT on RA6,PLL_enabled_freq_4xFosc1 */ -#define _OSC_EXT_Port_on_RA6_0H 0xF7 /* EXT RC-Port_on_RA6 */ -#define _OSC_HS_PLL_0H 0xF6 /* HS-PLL enabled freq=4xFosc1 */ -#define _OSC_EC_PORT_0H 0xF5 /* EC-Port on RA6 */ -#define _OSC_EC_CLKOUT__0H 0xF4 /* EC-CLKOUT on RA6 */ -#define _OSC_EXT_CLKOUT_on_RA6_0H 0xF3 /* EXT RC-CLKOUT_on_RA6 */ -#define _OSC_HS_0H 0xF2 /* HS */ -#define _OSC_XT_0H 0xF1 /* XT */ -#define _OSC_LP_0H 0xF0 /* LP */ - -/* Low Power System Clock Timer1 Enable 0H options */ -#define _OSCSEN_ON_0H 0xDF /* Enabled */ -#define _OSCSEN_OFF_0H 0xFF /* Disabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_DISABLED_CONTROLLED_1H 0xFE /* Disabled-Controlled by SWDTEN bit */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_32768_1H 0xFF /* 1:32768 */ -#define _WDTPS_1_16384_1H 0xFD /* 1:16384 */ -#define _WDTPS_1_8192_1H 0xFB /* 1:8192 */ -#define _WDTPS_1_4096_1H 0xF9 /* 1:4096 */ -#define _WDTPS_1_2048_1H 0xF7 /* 1:2048 */ -#define _WDTPS_1_1024_1H 0xF5 /* 1:1024 */ -#define _WDTPS_1_512_1H 0xF3 /* 1:512 */ -#define _WDTPS_1_256_1H 0xF1 /* 1:256 */ -#define _WDTPS_1_128_1H 0xEF /* 1:128 */ -#define _WDTPS_1_64_1H 0xED /* 1:64 */ -#define _WDTPS_1_32_1H 0xEB /* 1:32 */ -#define _WDTPS_1_16_1H 0xE9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xE7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xE5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xE3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xE1 /* 1:1 */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RB3_2H 0xFE /* RB3 */ - -/* ECCP Mux 2H options */ -#define _ECCPMX_ECCP1_E6E3_2H 0xFF /* ECCP1 and ECCP6 are muxed onto RE6 through RE3 */ -#define _ECCPMX_ECCP1_H7H4_2H 0xFD /* ECCP1 and ECCP6 are muxed onto RH7 through RH4 */ - -/* MCLR enable 2H options */ -#define _MCLRE_MCLR_Enabled_RE3_Disabled_2H 0xFF /* MCLR Enabled_RE3_Disabled */ -#define _MCLRE_MCLR_Disabled_RE3_Enabled_2H 0x7F /* MCLR Disabled__RE3_Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Code Protect 000800-0003FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 0004000-007FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 008000-00BFFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 00C000F-00FFFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00800-003FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 004000-007FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 08000-0BFFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 0C000-0FFFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00800-003FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 004000-07FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 08000-0BFFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 0C000-0FFFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_CLKOUT_1H 0xFF /* RC-CLKOUT on RA6 */ +#define _OSC_HS_SOFTWARE_1H 0xFE /* HS-Software enabled PLL */ +#define _OSC_EC_CLKOUT_Software_nabld_PLL_1H 0xFD /* EC-CLKOUT on RA6,Software_enabled_PLL */ +#define _OSC_EC_CLKOUT_PLL_enabld_frq_4xFosc1_1H 0xFC /* EC-CLKOUT on RA6,PLL_enabled_freq_4xFosc1 */ +#define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */ +#define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */ +#define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */ +#define _OSC_EC_CLKOUT__1H 0xF4 /* EC-CLKOUT on RA6 */ +#define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */ +#define _OSC_HS_1H 0xF2 /* HS */ +#define _OSC_XT_1H 0xF1 /* XT */ +#define _OSC_LP_1H 0xF0 /* LP */ + +/* Low Power System Clock Timer1 Enable 1H options */ +#define _OSCSEN_ON_1H 0xDF /* Enabled */ +#define _OSCSEN_OFF_1H 0xFF /* Disabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_32768_2H 0xFF /* 1:32768 */ +#define _WDTPS_1_16384_2H 0xFD /* 1:16384 */ +#define _WDTPS_1_8192_2H 0xFB /* 1:8192 */ +#define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */ +#define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */ +#define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */ +#define _WDTPS_1_512_2H 0xF3 /* 1:512 */ +#define _WDTPS_1_256_2H 0xF1 /* 1:256 */ +#define _WDTPS_1_128_2H 0xEF /* 1:128 */ +#define _WDTPS_1_64_2H 0xED /* 1:64 */ +#define _WDTPS_1_32_2H 0xEB /* 1:32 */ +#define _WDTPS_1_16_2H 0xE9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xE7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xE5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xE3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xE1 /* 1:1 */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RB3_3H 0xFE /* RB3 */ + +/* ECCP Mux 3H options */ +#define _ECCPMX_ECCP1_E6E3_3H 0xFF /* ECCP1 and ECCP6 are muxed onto RE6 through RE3 */ +#define _ECCPMX_ECCP1_H7H4_3H 0xFD /* ECCP1 and ECCP6 are muxed onto RH7 through RH4 */ + +/* MCLR enable 3H options */ +#define _MCLRE_MCLR_Enabled_RE3_Disabled_3H 0xFF /* MCLR Enabled_RE3_Disabled */ +#define _MCLRE_MCLR_Disabled_RE3_Enabled_3H 0x7F /* MCLR Disabled__RE3_Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Code Protect 000800-0003FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 0004000-007FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 008000-00BFFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 00C000F-00FFFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00800-003FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 004000-007FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 08000-0BFFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 0C000-0FFFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00800-003FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 004000-07FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 08000-0BFFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 0C000-0FFFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f6720.h b/device/include/pic16/pic18f6720.h index 531f8f0e..157a81e8 100644 --- a/device/include/pic16/pic18f6720.h +++ b/device/include/pic16/pic18f6720.h @@ -1212,197 +1212,197 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_5V_1L 0xFF /* 2.5V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RE7_2H 0xFE /* RE7 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-03FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 04000-07FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 08000-0BFFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 0C000-0FFFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Code Protect 10000-13FFF 4L options */ -#define _CP_4_OFF_4L 0xFF /* Disabled */ -#define _CP_4_ON_4L 0xEF /* Enabled */ - -/* Code Protect 14000-17FFF 4L options */ -#define _CP_5_OFF_4L 0xFF /* Disabled */ -#define _CP_5_ON_4L 0xDF /* Enabled */ - -/* Code Protect 18000-1BFFF 4L options */ -#define _CP_6_OFF_4L 0xFF /* Disabled */ -#define _CP_6_ON_4L 0xBF /* Enabled */ - -/* Code Protect 1C000-1FFFF 4L options */ -#define _CP_7_OFF_4L 0xFF /* Disabled */ -#define _CP_7_ON_4L 0x7F /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-03FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 04000-07FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 08000-0BFFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 0C000-0FFFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Table Write Protect 10000-13FFF 5L options */ -#define _WRT_4_OFF_5L 0xFF /* Disabled */ -#define _WRT_4_ON_5L 0xEF /* Enabled */ - -/* Table Write Protect 14000-17FFF 5L options */ -#define _WRT_5_OFF_5L 0xFF /* Disabled */ -#define _WRT_5_ON_5L 0xDF /* Enabled */ - -/* Table Write Protect 18000-1BFFF 5L options */ -#define _WRT_6_OFF_5L 0xFF /* Disabled */ -#define _WRT_6_ON_5L 0xBF /* Enabled */ - -/* Table Write Protect 1C000-1FFFF 5L options */ -#define _WRT_7_OFF_5L 0xFF /* Disabled */ -#define _WRT_7_ON_5L 0x7F /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_5V_2L 0xFF /* 2.5V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RE7_3H 0xFE /* RE7 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-03FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 04000-07FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 08000-0BFFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 0C000-0FFFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Code Protect 10000-13FFF 5L options */ +#define _CP_4_OFF_5L 0xFF /* Disabled */ +#define _CP_4_ON_5L 0xEF /* Enabled */ + +/* Code Protect 14000-17FFF 5L options */ +#define _CP_5_OFF_5L 0xFF /* Disabled */ +#define _CP_5_ON_5L 0xDF /* Enabled */ + +/* Code Protect 18000-1BFFF 5L options */ +#define _CP_6_OFF_5L 0xFF /* Disabled */ +#define _CP_6_ON_5L 0xBF /* Enabled */ + +/* Code Protect 1C000-1FFFF 5L options */ +#define _CP_7_OFF_5L 0xFF /* Disabled */ +#define _CP_7_ON_5L 0x7F /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-03FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 04000-07FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 08000-0BFFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 0C000-0FFFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Table Write Protect 10000-13FFF 6L options */ +#define _WRT_4_OFF_6L 0xFF /* Disabled */ +#define _WRT_4_ON_6L 0xEF /* Enabled */ + +/* Table Write Protect 14000-17FFF 6L options */ +#define _WRT_5_OFF_6L 0xFF /* Disabled */ +#define _WRT_5_ON_6L 0xDF /* Enabled */ + +/* Table Write Protect 18000-1BFFF 6L options */ +#define _WRT_6_OFF_6L 0xFF /* Disabled */ +#define _WRT_6_ON_6L 0xBF /* Enabled */ + +/* Table Write Protect 1C000-1FFFF 6L options */ +#define _WRT_7_OFF_6L 0xFF /* Disabled */ +#define _WRT_7_ON_6L 0x7F /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ -/* Table Read Protect 00200-03FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ +/* Table Read Protect 00200-03FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ -/* Table Read Protect 04000-07FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ +/* Table Read Protect 04000-07FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ -/* Table Read Protect 08000-0BFFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ +/* Table Read Protect 08000-0BFFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ -/* Table Read Protect 0C000-0FFFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ +/* Table Read Protect 0C000-0FFFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ -/* Table Read Protect 10000-13FFF 6L options */ -#define _EBTR_4_OFF_6L 0xFF /* Disabled */ -#define _EBTR_4_ON_6L 0xEF /* Enabled */ +/* Table Read Protect 10000-13FFF 7L options */ +#define _EBTR_4_OFF_7L 0xFF /* Disabled */ +#define _EBTR_4_ON_7L 0xEF /* Enabled */ -/* Table Read Protect 14000-17FFF 6L options */ -#define _EBTR_5_OFF_6L 0xFF /* Disabled */ -#define _EBTR_5_ON_6L 0xDF /* Enabled */ +/* Table Read Protect 14000-17FFF 7L options */ +#define _EBTR_5_OFF_7L 0xFF /* Disabled */ +#define _EBTR_5_ON_7L 0xDF /* Enabled */ -/* Table Read Protect 18000-1BFFF 6L options */ -#define _EBTR_6_OFF_6L 0xFF /* Disabled */ -#define _EBTR_6_ON_6L 0xBF /* Enabled */ +/* Table Read Protect 18000-1BFFF 7L options */ +#define _EBTR_6_OFF_7L 0xFF /* Disabled */ +#define _EBTR_6_ON_7L 0xBF /* Enabled */ -/* Table Read Protect 1C000-1FFFF 6L options */ -#define _EBTR_7_OFF_6L 0xFF /* Disabled */ -#define _EBTR_7_ON_6L 0x7F /* Enabled */ +/* Table Read Protect 1C000-1FFFF 7L options */ +#define _EBTR_7_OFF_7L 0xFF /* Disabled */ +#define _EBTR_7_ON_7L 0x7F /* Enabled */ -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f8520.h b/device/include/pic16/pic18f8520.h index 23612ea6..e36417cd 100644 --- a/device/include/pic16/pic18f8520.h +++ b/device/include/pic16/pic18f8520.h @@ -1324,162 +1324,162 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2L 0x300004 -#define __CONFIG2H 0x300005 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_5V_1L 0xFF /* 2.5V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* Processor Mode 2L options */ -#define _PMODE_MICROCONTROLLER_2L 0xFF /* Microcontroller */ -#define _PMODE_MICROPROCESSOR__2L 0xFE /* Microprocessor */ -#define _PMODE_MICROPROCESSOR_w_Boot_2L 0xFD /* Microprocessor w_Boot */ -#define _PMODE_EXT_2L 0xFC /* Ext Microcontroller */ - -/* External Bus Wait 2L options */ -#define _WAIT_OFF_2L 0xFF /* Disabled */ -#define _WAIT_ON_2L 0x7F /* Enabled */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RE7_MICROCONTROLLER__RB3_2H 0xFE /* RE7(Microcontroller)/RB3 */ - -/* Timer1 OSC 2H options */ -#define _T1OSCMX_LOW_2H 0xFD /* Low Power */ - -/* Low Voltage Program 2H options */ -#define _LVP_ON_2H 0xFF /* Enabled */ -#define _LVP_OFF_2H 0xFB /* Disabled */ - -/* Background Debug 2H options */ -#define _BACKBUG_OFF_2H 0xFF /* Disabled */ -#define _BACKBUG_ON_2H 0x7F /* Enabled */ - -/* Stack Overflow Reset 2H options */ -#define _STVR_ON_2H 0xFF /* Enabled */ -#define _STVR_OFF_2H 0xFE /* Disabled */ - -/* Code Protect 00800-01FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 02000-03FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 04000-05FFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 06000-07FFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00800-01FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 02000-03FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 04000-05FFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 06000-07FFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00800-01FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 02000-03FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 04000-05FFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 06000-07FFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3L 0x300004 +#define __CONFIG3H 0x300005 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_5V_2L 0xFF /* 2.5V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* Processor Mode 3L options */ +#define _PMODE_MICROCONTROLLER_3L 0xFF /* Microcontroller */ +#define _PMODE_MICROPROCESSOR__3L 0xFE /* Microprocessor */ +#define _PMODE_MICROPROCESSOR_w_Boot_3L 0xFD /* Microprocessor w_Boot */ +#define _PMODE_EXT_3L 0xFC /* Ext Microcontroller */ + +/* External Bus Wait 3L options */ +#define _WAIT_OFF_3L 0xFF /* Disabled */ +#define _WAIT_ON_3L 0x7F /* Enabled */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RE7_MICROCONTROLLER__RB3_3H 0xFE /* RE7(Microcontroller)/RB3 */ + +/* Timer1 OSC 3H options */ +#define _T1OSCMX_LOW_3H 0xFD /* Low Power */ + +/* Low Voltage Program 3H options */ +#define _LVP_ON_3H 0xFF /* Enabled */ +#define _LVP_OFF_3H 0xFB /* Disabled */ + +/* Background Debug 3H options */ +#define _BACKBUG_OFF_3H 0xFF /* Disabled */ +#define _BACKBUG_ON_3H 0x7F /* Enabled */ + +/* Stack Overflow Reset 3H options */ +#define _STVR_ON_3H 0xFF /* Enabled */ +#define _STVR_OFF_3H 0xFE /* Disabled */ + +/* Code Protect 00800-01FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 02000-03FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 04000-05FFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 06000-07FFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00800-01FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 02000-03FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 04000-05FFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 06000-07FFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00800-01FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 02000-03FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 04000-05FFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 06000-07FFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f8620.h b/device/include/pic16/pic18f8620.h index 73424e7e..0d8461b8 100644 --- a/device/include/pic16/pic18f8620.h +++ b/device/include/pic16/pic18f8620.h @@ -1324,160 +1324,160 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2L 0x300004 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_5V_1L 0xFF /* 2.5V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* Processor Mode 2L options */ -#define _PMODE_MICROCONTROLLER_2L 0xFF /* Microcontroller */ -#define _PMODE_MICROPROCESSOR__2L 0xFE /* Microprocessor */ -#define _PMODE_MICROPROCESSOR_w_Boot_2L 0xFD /* Microprocessor w_Boot */ -#define _PMODE_EXT_2L 0xFC /* Ext Microcontroller */ - -/* External Bus Wait 2L options */ -#define _WAIT_OFF_2L 0xFF /* Disabled */ -#define _WAIT_ON_2L 0x7F /* Enabled */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RE7_MICROCONTROLLER__RB3_2H 0xFE /* RE7(Microcontroller)/RB3 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-03FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 04000-07FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 08000-0BFFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 0C000-0FFFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-03FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 04000-07FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 08000-0BFFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 0C000-0FFFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00200-03FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 04000-07FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 08000-0BFFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 0C000-0FFFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3L 0x300004 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_5V_2L 0xFF /* 2.5V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* Processor Mode 3L options */ +#define _PMODE_MICROCONTROLLER_3L 0xFF /* Microcontroller */ +#define _PMODE_MICROPROCESSOR__3L 0xFE /* Microprocessor */ +#define _PMODE_MICROPROCESSOR_w_Boot_3L 0xFD /* Microprocessor w_Boot */ +#define _PMODE_EXT_3L 0xFC /* Ext Microcontroller */ + +/* External Bus Wait 3L options */ +#define _WAIT_OFF_3L 0xFF /* Disabled */ +#define _WAIT_ON_3L 0x7F /* Enabled */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RE7_MICROCONTROLLER__RB3_3H 0xFE /* RE7(Microcontroller)/RB3 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-03FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 04000-07FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 08000-0BFFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 0C000-0FFFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-03FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 04000-07FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 08000-0BFFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 0C000-0FFFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00200-03FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 04000-07FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 08000-0BFFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 0C000-0FFFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f8680.h b/device/include/pic16/pic18f8680.h index f4b055eb..c9387369 100644 --- a/device/include/pic16/pic18f8680.h +++ b/device/include/pic16/pic18f8680.h @@ -1814,180 +1814,180 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2L 0x300004 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_CLKOUT_0H 0xFF /* RC-CLKOUT on RA6 */ -#define _OSC_HS_SOFTWARE_0H 0xFE /* HS-Software enabled PLL */ -#define _OSC_EC_CLKOUT_Software_nabld_PLL_0H 0xFD /* EC-CLKOUT on RA6,Software_enabled_PLL */ -#define _OSC_EC_CLKOUT_PLL_enabld_frq_4xFosc1_0H 0xFC /* EC-CLKOUT on RA6,PLL_enabled_freq_4xFosc1 */ -#define _OSC_EXT_Port_on_RA6_0H 0xF7 /* EXT RC-Port_on_RA6 */ -#define _OSC_HS_PLL_0H 0xF6 /* HS-PLL enabled freq=4xFosc1 */ -#define _OSC_EC_PORT_0H 0xF5 /* EC-Port on RA6 */ -#define _OSC_EC_CLKOUT__0H 0xF4 /* EC-CLKOUT on RA6 */ -#define _OSC_EXT_CLKOUT_on_RA6_0H 0xF3 /* EXT RC-CLKOUT_on_RA6 */ -#define _OSC_HS_0H 0xF2 /* HS */ -#define _OSC_XT_0H 0xF1 /* XT */ -#define _OSC_LP_0H 0xF0 /* LP */ - -/* Low Power System Clock Timer1 Enable 0H options */ -#define _OSCSEN_ON_0H 0xDF /* Enabled */ -#define _OSCSEN_OFF_0H 0xFF /* Disabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_0V_1L 0xFF /* 2.0V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_DISABLED_CONTROLLED_1H 0xFE /* Disabled-Controlled by SWDTEN bit */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_32768_1H 0xFF /* 1:32768 */ -#define _WDTPS_1_16384_1H 0xFD /* 1:16384 */ -#define _WDTPS_1_8192_1H 0xFB /* 1:8192 */ -#define _WDTPS_1_4096_1H 0xF9 /* 1:4096 */ -#define _WDTPS_1_2048_1H 0xF7 /* 1:2048 */ -#define _WDTPS_1_1024_1H 0xF5 /* 1:1024 */ -#define _WDTPS_1_512_1H 0xF3 /* 1:512 */ -#define _WDTPS_1_256_1H 0xF1 /* 1:256 */ -#define _WDTPS_1_128_1H 0xEF /* 1:128 */ -#define _WDTPS_1_64_1H 0xED /* 1:64 */ -#define _WDTPS_1_32_1H 0xEB /* 1:32 */ -#define _WDTPS_1_16_1H 0xE9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xE7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xE5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xE3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xE1 /* 1:1 */ - -/* Processor Mode 2L options */ -#define _PMODE_MICROCONTROLLER_2L 0xFF /* Microcontroller */ -#define _PMODE_MICROPROCESSOR__2L 0xFE /* Microprocessor */ -#define _PMODE_MICROPROCESSOR_w_Boot_2L 0xFD /* Microprocessor w_Boot */ -#define _PMODE_EXT_2L 0xFC /* Ext Microcontroller */ - -/* External Bus Wait 2L options */ -#define _WAIT_OFF_2L 0xFF /* Disabled */ -#define _WAIT_ON_2L 0x7F /* Enabled */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RB3_2H 0xFE /* RB3 */ - -/* ECCP Mux 2H options */ -#define _ECCPMX_ECCP1_E6E3_2H 0xFF /* ECCP1 and ECCP6 are muxed onto RE6 through RE3 */ -#define _ECCPMX_ECCP1_H7H4_2H 0xFD /* ECCP1 and ECCP6 are muxed onto RH7 through RH4 */ - -/* MCLR enable 2H options */ -#define _MCLRE_MCLR_Enabled_RE3_Disabled_2H 0xFF /* MCLR Enabled_RE3_Disabled */ -#define _MCLRE_MCLR_Disabled_RE3_Enabled_2H 0x7F /* MCLR Disabled__RE3_Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Code Protect 000800-0003FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 0004000-007FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 008000-00BFFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 00C000F-00FFFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00800-003FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 004000-007FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 08000-0BFFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 0C000-0FFFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ - -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ - -/* Table Read Protect 00800-003FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ - -/* Table Read Protect 004000-07FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ - -/* Table Read Protect 08000-0BFFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ - -/* Table Read Protect 0C000-0FFFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ - -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3L 0x300004 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_CLKOUT_1H 0xFF /* RC-CLKOUT on RA6 */ +#define _OSC_HS_SOFTWARE_1H 0xFE /* HS-Software enabled PLL */ +#define _OSC_EC_CLKOUT_Software_nabld_PLL_1H 0xFD /* EC-CLKOUT on RA6,Software_enabled_PLL */ +#define _OSC_EC_CLKOUT_PLL_enabld_frq_4xFosc1_1H 0xFC /* EC-CLKOUT on RA6,PLL_enabled_freq_4xFosc1 */ +#define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */ +#define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */ +#define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */ +#define _OSC_EC_CLKOUT__1H 0xF4 /* EC-CLKOUT on RA6 */ +#define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */ +#define _OSC_HS_1H 0xF2 /* HS */ +#define _OSC_XT_1H 0xF1 /* XT */ +#define _OSC_LP_1H 0xF0 /* LP */ + +/* Low Power System Clock Timer1 Enable 1H options */ +#define _OSCSEN_ON_1H 0xDF /* Enabled */ +#define _OSCSEN_OFF_1H 0xFF /* Disabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_0V_2L 0xFF /* 2.0V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_32768_2H 0xFF /* 1:32768 */ +#define _WDTPS_1_16384_2H 0xFD /* 1:16384 */ +#define _WDTPS_1_8192_2H 0xFB /* 1:8192 */ +#define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */ +#define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */ +#define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */ +#define _WDTPS_1_512_2H 0xF3 /* 1:512 */ +#define _WDTPS_1_256_2H 0xF1 /* 1:256 */ +#define _WDTPS_1_128_2H 0xEF /* 1:128 */ +#define _WDTPS_1_64_2H 0xED /* 1:64 */ +#define _WDTPS_1_32_2H 0xEB /* 1:32 */ +#define _WDTPS_1_16_2H 0xE9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xE7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xE5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xE3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xE1 /* 1:1 */ + +/* Processor Mode 3L options */ +#define _PMODE_MICROCONTROLLER_3L 0xFF /* Microcontroller */ +#define _PMODE_MICROPROCESSOR__3L 0xFE /* Microprocessor */ +#define _PMODE_MICROPROCESSOR_w_Boot_3L 0xFD /* Microprocessor w_Boot */ +#define _PMODE_EXT_3L 0xFC /* Ext Microcontroller */ + +/* External Bus Wait 3L options */ +#define _WAIT_OFF_3L 0xFF /* Disabled */ +#define _WAIT_ON_3L 0x7F /* Enabled */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RB3_3H 0xFE /* RB3 */ + +/* ECCP Mux 3H options */ +#define _ECCPMX_ECCP1_E6E3_3H 0xFF /* ECCP1 and ECCP6 are muxed onto RE6 through RE3 */ +#define _ECCPMX_ECCP1_H7H4_3H 0xFD /* ECCP1 and ECCP6 are muxed onto RH7 through RH4 */ + +/* MCLR enable 3H options */ +#define _MCLRE_MCLR_Enabled_RE3_Disabled_3H 0xFF /* MCLR Enabled_RE3_Disabled */ +#define _MCLRE_MCLR_Disabled_RE3_Enabled_3H 0x7F /* MCLR Disabled__RE3_Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Code Protect 000800-0003FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 0004000-007FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 008000-00BFFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 00C000F-00FFFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00800-003FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 004000-007FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 08000-0BFFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 0C000-0FFFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ + +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ + +/* Table Read Protect 00800-003FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ + +/* Table Read Protect 004000-07FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ + +/* Table Read Protect 08000-0BFFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ + +/* Table Read Protect 0C000-0FFFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ + +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/device/include/pic16/pic18f8720.h b/device/include/pic16/pic18f8720.h index 6555ff1f..0889196a 100644 --- a/device/include/pic16/pic18f8720.h +++ b/device/include/pic16/pic18f8720.h @@ -1324,208 +1324,208 @@ extern sfr at 0xfff TOSU; /* Configuration registers locations */ -#define __CONFIG0H 0x300001 -#define __CONFIG1L 0x300002 -#define __CONFIG1H 0x300003 -#define __CONFIG2L 0x300004 -#define __CONFIG2H 0x300005 -#define __CONFIG3L 0x300006 -#define __CONFIG4L 0x300008 -#define __CONFIG4H 0x300009 -#define __CONFIG5L 0x30000A -#define __CONFIG5H 0x30000B -#define __CONFIG6L 0x30000C -#define __CONFIG6H 0x30000D - - - -/* Oscillator 0H options */ -#define _OSC_RC_OSC2_0H 0xFF /* RC-OSC2 as RA6 */ -#define _OSC_HS_PLL_0H 0xFE /* HS-PLL Enabled */ -#define _OSC_EC_OSC2_RA6_0H 0xFD /* EC-OSC2 as RA6 */ -#define _OSC_EC_OSC2_Clock_Out_0H 0xFC /* EC-OSC2 as Clock_Out */ -#define _OSC_RC_0H 0xFB /* RC */ -#define _OSC_HS_0H 0xFA /* HS */ -#define _OSC_XT_0H 0xF9 /* XT */ -#define _OSC_LP_0H 0xF8 /* LP */ - -/* Osc. Switch Enable 0H options */ -#define _OSCS_OFF_0H 0xFF /* Disabled */ -#define _OSCS_ON_0H 0xDF /* Enabled */ - -/* Power Up Timer 1L options */ -#define _PUT_OFF_1L 0xFF /* Disabled */ -#define _PUT_ON_1L 0xFE /* Enabled */ - -/* Brown Out Detect 1L options */ -#define _BODEN_ON_1L 0xFF /* Enabled */ -#define _BODEN_OFF_1L 0xFD /* Disabled */ - -/* Brown Out Voltage 1L options */ -#define _BODENV_2_5V_1L 0xFF /* 2.5V */ -#define _BODENV_2_7V_1L 0xFB /* 2.7V */ -#define _BODENV_4_2V_1L 0xF7 /* 4.2V */ -#define _BODENV_4_5V_1L 0xF3 /* 4.5V */ - -/* Watchdog Timer 1H options */ -#define _WDT_ON_1H 0xFF /* Enabled */ -#define _WDT_OFF_1H 0xFE /* Disabled */ - -/* Watchdog Postscaler 1H options */ -#define _WDTPS_1_128_1H 0xFF /* 1:128 */ -#define _WDTPS_1_64_1H 0xFD /* 1:64 */ -#define _WDTPS_1_32_1H 0xFB /* 1:32 */ -#define _WDTPS_1_16_1H 0xF9 /* 1:16 */ -#define _WDTPS_1_8_1H 0xF7 /* 1:8 */ -#define _WDTPS_1_4_1H 0xF5 /* 1:4 */ -#define _WDTPS_1_2_1H 0xF3 /* 1:2 */ -#define _WDTPS_1_1_1H 0xF1 /* 1:1 */ - -/* Processor Mode 2L options */ -#define _PMODE_MICROCONTROLLER_2L 0xFF /* Microcontroller */ -#define _PMODE_MICROPROCESSOR__2L 0xFE /* Microprocessor */ -#define _PMODE_MICROPROCESSOR_w_Boot_2L 0xFD /* Microprocessor w_Boot */ -#define _PMODE_EXT_2L 0xFC /* Ext Microcontroller */ - -/* External Bus Wait 2L options */ -#define _WAIT_OFF_2L 0xFF /* Disabled */ -#define _WAIT_ON_2L 0x7F /* Enabled */ - -/* CCP2 Mux 2H options */ -#define _CCP2MUX_RC1_2H 0xFF /* RC1 */ -#define _CCP2MUX_RE7_MICROCONTROLLER__RB3_2H 0xFE /* RE7(Microcontroller)/RB3 */ - -/* Low Voltage Program 3L options */ -#define _LVP_ON_3L 0xFF /* Enabled */ -#define _LVP_OFF_3L 0xFB /* Disabled */ - -/* Background Debug 3L options */ -#define _BACKBUG_OFF_3L 0xFF /* Disabled */ -#define _BACKBUG_ON_3L 0x7F /* Enabled */ - -/* Stack Overflow Reset 3L options */ -#define _STVR_ON_3L 0xFF /* Enabled */ -#define _STVR_OFF_3L 0xFE /* Disabled */ - -/* Code Protect 00200-03FFF 4L options */ -#define _CP_0_OFF_4L 0xFF /* Disabled */ -#define _CP_0_ON_4L 0xFE /* Enabled */ - -/* Code Protect 04000-07FFF 4L options */ -#define _CP_1_OFF_4L 0xFF /* Disabled */ -#define _CP_1_ON_4L 0xFD /* Enabled */ - -/* Code Protect 08000-0BFFF 4L options */ -#define _CP_2_OFF_4L 0xFF /* Disabled */ -#define _CP_2_ON_4L 0xFB /* Enabled */ - -/* Code Protect 0C000-0FFFF 4L options */ -#define _CP_3_OFF_4L 0xFF /* Disabled */ -#define _CP_3_ON_4L 0xF7 /* Enabled */ - -/* Code Protect 10000-13FFF 4L options */ -#define _CP_4_OFF_4L 0xFF /* Disabled */ -#define _CP_4_ON_4L 0xEF /* Enabled */ - -/* Code Protect 14000-17FFF 4L options */ -#define _CP_5_OFF_4L 0xFF /* Disabled */ -#define _CP_5_ON_4L 0xDF /* Enabled */ - -/* Code Protect 18000-1BFFF 4L options */ -#define _CP_6_OFF_4L 0xFF /* Disabled */ -#define _CP_6_ON_4L 0xBF /* Enabled */ - -/* Code Protect 1C000-1FFFF 4L options */ -#define _CP_7_OFF_4L 0xFF /* Disabled */ -#define _CP_7_ON_4L 0x7F /* Enabled */ - -/* Data EE Read Protect 4H options */ -#define _CPD_OFF_4H 0xFF /* Disabled */ -#define _CPD_ON_4H 0x7F /* Enabled */ - -/* Code Protect Boot 4H options */ -#define _CPB_OFF_4H 0xFF /* Disabled */ -#define _CPB_ON_4H 0xBF /* Enabled */ - -/* Table Write Protect 00200-03FFF 5L options */ -#define _WRT_0_OFF_5L 0xFF /* Disabled */ -#define _WRT_0_ON_5L 0xFE /* Enabled */ - -/* Table Write Protect 04000-07FFF 5L options */ -#define _WRT_1_OFF_5L 0xFF /* Disabled */ -#define _WRT_1_ON_5L 0xFD /* Enabled */ - -/* Table Write Protect 08000-0BFFF 5L options */ -#define _WRT_2_OFF_5L 0xFF /* Disabled */ -#define _WRT_2_ON_5L 0xFB /* Enabled */ - -/* Table Write Protect 0C000-0FFFF 5L options */ -#define _WRT_3_OFF_5L 0xFF /* Disabled */ -#define _WRT_3_ON_5L 0xF7 /* Enabled */ - -/* Table Write Protect 10000-13FFF 5L options */ -#define _WRT_4_OFF_5L 0xFF /* Disabled */ -#define _WRT_4_ON_5L 0xEF /* Enabled */ - -/* Table Write Protect 14000-17FFF 5L options */ -#define _WRT_5_OFF_5L 0xFF /* Disabled */ -#define _WRT_5_ON_5L 0xDF /* Enabled */ - -/* Table Write Protect 18000-1BFFF 5L options */ -#define _WRT_6_OFF_5L 0xFF /* Disabled */ -#define _WRT_6_ON_5L 0xBF /* Enabled */ - -/* Table Write Protect 1C000-1FFFF 5L options */ -#define _WRT_7_OFF_5L 0xFF /* Disabled */ -#define _WRT_7_ON_5L 0x7F /* Enabled */ - -/* Data EE Write Protect 5H options */ -#define _WRTD_OFF_5H 0xFF /* Disabled */ -#define _WRTD_ON_5H 0x7F /* Enabled */ - -/* Table Write Protect Boot 5H options */ -#define _WRTB_OFF_5H 0xFF /* Disabled */ -#define _WRTB_ON_5H 0xBF /* Enabled */ +#define __CONFIG1H 0x300001 +#define __CONFIG2L 0x300002 +#define __CONFIG2H 0x300003 +#define __CONFIG3L 0x300004 +#define __CONFIG3H 0x300005 +#define __CONFIG4L 0x300006 +#define __CONFIG5L 0x300008 +#define __CONFIG5H 0x300009 +#define __CONFIG6L 0x30000A +#define __CONFIG6H 0x30000B +#define __CONFIG7L 0x30000C +#define __CONFIG7H 0x30000D + + + +/* Oscillator 1H options */ +#define _OSC_RC_OSC2_1H 0xFF /* RC-OSC2 as RA6 */ +#define _OSC_HS_PLL_1H 0xFE /* HS-PLL Enabled */ +#define _OSC_EC_OSC2_RA6_1H 0xFD /* EC-OSC2 as RA6 */ +#define _OSC_EC_OSC2_Clock_Out_1H 0xFC /* EC-OSC2 as Clock_Out */ +#define _OSC_RC_1H 0xFB /* RC */ +#define _OSC_HS_1H 0xFA /* HS */ +#define _OSC_XT_1H 0xF9 /* XT */ +#define _OSC_LP_1H 0xF8 /* LP */ + +/* Osc. Switch Enable 1H options */ +#define _OSCS_OFF_1H 0xFF /* Disabled */ +#define _OSCS_ON_1H 0xDF /* Enabled */ + +/* Power Up Timer 2L options */ +#define _PUT_OFF_2L 0xFF /* Disabled */ +#define _PUT_ON_2L 0xFE /* Enabled */ + +/* Brown Out Detect 2L options */ +#define _BODEN_ON_2L 0xFF /* Enabled */ +#define _BODEN_OFF_2L 0xFD /* Disabled */ + +/* Brown Out Voltage 2L options */ +#define _BODENV_2_5V_2L 0xFF /* 2.5V */ +#define _BODENV_2_7V_2L 0xFB /* 2.7V */ +#define _BODENV_4_2V_2L 0xF7 /* 4.2V */ +#define _BODENV_4_5V_2L 0xF3 /* 4.5V */ + +/* Watchdog Timer 2H options */ +#define _WDT_ON_2H 0xFF /* Enabled */ +#define _WDT_OFF_2H 0xFE /* Disabled */ + +/* Watchdog Postscaler 2H options */ +#define _WDTPS_1_128_2H 0xFF /* 1:128 */ +#define _WDTPS_1_64_2H 0xFD /* 1:64 */ +#define _WDTPS_1_32_2H 0xFB /* 1:32 */ +#define _WDTPS_1_16_2H 0xF9 /* 1:16 */ +#define _WDTPS_1_8_2H 0xF7 /* 1:8 */ +#define _WDTPS_1_4_2H 0xF5 /* 1:4 */ +#define _WDTPS_1_2_2H 0xF3 /* 1:2 */ +#define _WDTPS_1_1_2H 0xF1 /* 1:1 */ + +/* Processor Mode 3L options */ +#define _PMODE_MICROCONTROLLER_3L 0xFF /* Microcontroller */ +#define _PMODE_MICROPROCESSOR__3L 0xFE /* Microprocessor */ +#define _PMODE_MICROPROCESSOR_w_Boot_3L 0xFD /* Microprocessor w_Boot */ +#define _PMODE_EXT_3L 0xFC /* Ext Microcontroller */ + +/* External Bus Wait 3L options */ +#define _WAIT_OFF_3L 0xFF /* Disabled */ +#define _WAIT_ON_3L 0x7F /* Enabled */ + +/* CCP2 Mux 3H options */ +#define _CCP2MUX_RC1_3H 0xFF /* RC1 */ +#define _CCP2MUX_RE7_MICROCONTROLLER__RB3_3H 0xFE /* RE7(Microcontroller)/RB3 */ + +/* Low Voltage Program 4L options */ +#define _LVP_ON_4L 0xFF /* Enabled */ +#define _LVP_OFF_4L 0xFB /* Disabled */ + +/* Background Debug 4L options */ +#define _BACKBUG_OFF_4L 0xFF /* Disabled */ +#define _BACKBUG_ON_4L 0x7F /* Enabled */ + +/* Stack Overflow Reset 4L options */ +#define _STVR_ON_4L 0xFF /* Enabled */ +#define _STVR_OFF_4L 0xFE /* Disabled */ + +/* Code Protect 00200-03FFF 5L options */ +#define _CP_0_OFF_5L 0xFF /* Disabled */ +#define _CP_0_ON_5L 0xFE /* Enabled */ + +/* Code Protect 04000-07FFF 5L options */ +#define _CP_1_OFF_5L 0xFF /* Disabled */ +#define _CP_1_ON_5L 0xFD /* Enabled */ + +/* Code Protect 08000-0BFFF 5L options */ +#define _CP_2_OFF_5L 0xFF /* Disabled */ +#define _CP_2_ON_5L 0xFB /* Enabled */ + +/* Code Protect 0C000-0FFFF 5L options */ +#define _CP_3_OFF_5L 0xFF /* Disabled */ +#define _CP_3_ON_5L 0xF7 /* Enabled */ + +/* Code Protect 10000-13FFF 5L options */ +#define _CP_4_OFF_5L 0xFF /* Disabled */ +#define _CP_4_ON_5L 0xEF /* Enabled */ + +/* Code Protect 14000-17FFF 5L options */ +#define _CP_5_OFF_5L 0xFF /* Disabled */ +#define _CP_5_ON_5L 0xDF /* Enabled */ + +/* Code Protect 18000-1BFFF 5L options */ +#define _CP_6_OFF_5L 0xFF /* Disabled */ +#define _CP_6_ON_5L 0xBF /* Enabled */ + +/* Code Protect 1C000-1FFFF 5L options */ +#define _CP_7_OFF_5L 0xFF /* Disabled */ +#define _CP_7_ON_5L 0x7F /* Enabled */ + +/* Data EE Read Protect 5H options */ +#define _CPD_OFF_5H 0xFF /* Disabled */ +#define _CPD_ON_5H 0x7F /* Enabled */ + +/* Code Protect Boot 5H options */ +#define _CPB_OFF_5H 0xFF /* Disabled */ +#define _CPB_ON_5H 0xBF /* Enabled */ + +/* Table Write Protect 00200-03FFF 6L options */ +#define _WRT_0_OFF_6L 0xFF /* Disabled */ +#define _WRT_0_ON_6L 0xFE /* Enabled */ + +/* Table Write Protect 04000-07FFF 6L options */ +#define _WRT_1_OFF_6L 0xFF /* Disabled */ +#define _WRT_1_ON_6L 0xFD /* Enabled */ + +/* Table Write Protect 08000-0BFFF 6L options */ +#define _WRT_2_OFF_6L 0xFF /* Disabled */ +#define _WRT_2_ON_6L 0xFB /* Enabled */ + +/* Table Write Protect 0C000-0FFFF 6L options */ +#define _WRT_3_OFF_6L 0xFF /* Disabled */ +#define _WRT_3_ON_6L 0xF7 /* Enabled */ + +/* Table Write Protect 10000-13FFF 6L options */ +#define _WRT_4_OFF_6L 0xFF /* Disabled */ +#define _WRT_4_ON_6L 0xEF /* Enabled */ + +/* Table Write Protect 14000-17FFF 6L options */ +#define _WRT_5_OFF_6L 0xFF /* Disabled */ +#define _WRT_5_ON_6L 0xDF /* Enabled */ + +/* Table Write Protect 18000-1BFFF 6L options */ +#define _WRT_6_OFF_6L 0xFF /* Disabled */ +#define _WRT_6_ON_6L 0xBF /* Enabled */ + +/* Table Write Protect 1C000-1FFFF 6L options */ +#define _WRT_7_OFF_6L 0xFF /* Disabled */ +#define _WRT_7_ON_6L 0x7F /* Enabled */ + +/* Data EE Write Protect 6H options */ +#define _WRTD_OFF_6H 0xFF /* Disabled */ +#define _WRTD_ON_6H 0x7F /* Enabled */ + +/* Table Write Protect Boot 6H options */ +#define _WRTB_OFF_6H 0xFF /* Disabled */ +#define _WRTB_ON_6H 0xBF /* Enabled */ -/* Config. Write Protect 5H options */ -#define _WRTC_OFF_5H 0xFF /* Disabled */ -#define _WRTC_ON_5H 0xDF /* Enabled */ +/* Config. Write Protect 6H options */ +#define _WRTC_OFF_6H 0xFF /* Disabled */ +#define _WRTC_ON_6H 0xDF /* Enabled */ -/* Table Read Protect 00200-03FFF 6L options */ -#define _EBTR_0_OFF_6L 0xFF /* Disabled */ -#define _EBTR_0_ON_6L 0xFE /* Enabled */ +/* Table Read Protect 00200-03FFF 7L options */ +#define _EBTR_0_OFF_7L 0xFF /* Disabled */ +#define _EBTR_0_ON_7L 0xFE /* Enabled */ -/* Table Read Protect 04000-07FFF 6L options */ -#define _EBTR_1_OFF_6L 0xFF /* Disabled */ -#define _EBTR_1_ON_6L 0xFD /* Enabled */ +/* Table Read Protect 04000-07FFF 7L options */ +#define _EBTR_1_OFF_7L 0xFF /* Disabled */ +#define _EBTR_1_ON_7L 0xFD /* Enabled */ -/* Table Read Protect 08000-0BFFF 6L options */ -#define _EBTR_2_OFF_6L 0xFF /* Disabled */ -#define _EBTR_2_ON_6L 0xFB /* Enabled */ +/* Table Read Protect 08000-0BFFF 7L options */ +#define _EBTR_2_OFF_7L 0xFF /* Disabled */ +#define _EBTR_2_ON_7L 0xFB /* Enabled */ -/* Table Read Protect 0C000-0FFFF 6L options */ -#define _EBTR_3_OFF_6L 0xFF /* Disabled */ -#define _EBTR_3_ON_6L 0xF7 /* Enabled */ +/* Table Read Protect 0C000-0FFFF 7L options */ +#define _EBTR_3_OFF_7L 0xFF /* Disabled */ +#define _EBTR_3_ON_7L 0xF7 /* Enabled */ -/* Table Read Protect 10000-13FFF 6L options */ -#define _EBTR_4_OFF_6L 0xFF /* Disabled */ -#define _EBTR_4_ON_6L 0xEF /* Enabled */ +/* Table Read Protect 10000-13FFF 7L options */ +#define _EBTR_4_OFF_7L 0xFF /* Disabled */ +#define _EBTR_4_ON_7L 0xEF /* Enabled */ -/* Table Read Protect 14000-17FFF 6L options */ -#define _EBTR_5_OFF_6L 0xFF /* Disabled */ -#define _EBTR_5_ON_6L 0xDF /* Enabled */ +/* Table Read Protect 14000-17FFF 7L options */ +#define _EBTR_5_OFF_7L 0xFF /* Disabled */ +#define _EBTR_5_ON_7L 0xDF /* Enabled */ -/* Table Read Protect 18000-1BFFF 6L options */ -#define _EBTR_6_OFF_6L 0xFF /* Disabled */ -#define _EBTR_6_ON_6L 0xBF /* Enabled */ +/* Table Read Protect 18000-1BFFF 7L options */ +#define _EBTR_6_OFF_7L 0xFF /* Disabled */ +#define _EBTR_6_ON_7L 0xBF /* Enabled */ -/* Table Read Protect 1C000-1FFFF 6L options */ -#define _EBTR_7_OFF_6L 0xFF /* Disabled */ -#define _EBTR_7_ON_6L 0x7F /* Enabled */ +/* Table Read Protect 1C000-1FFFF 7L options */ +#define _EBTR_7_OFF_7L 0xFF /* Disabled */ +#define _EBTR_7_ON_7L 0x7F /* Enabled */ -/* Table Read Protect Boot 6H options */ -#define _EBTRB_OFF_6H 0xFF /* Disabled */ -#define _EBTRB_ON_6H 0xBF /* Enabled */ +/* Table Read Protect Boot 7H options */ +#define _EBTRB_OFF_7H 0xFF /* Disabled */ +#define _EBTRB_ON_7H 0xBF /* Enabled */ /* Device ID locations */ diff --git a/src/SDCCmem.c b/src/SDCCmem.c index 2f55cf2d..b2a8c7b5 100644 --- a/src/SDCCmem.c +++ b/src/SDCCmem.c @@ -375,6 +375,7 @@ allocGlobal (symbol * sym) return; } + if(!TARGET_IS_PIC16 || (TARGET_IS_PIC16 && sym->level)) /* register storage class ignored changed to FIXED */ if (SPEC_SCLS (sym->etype) == S_REGISTER) SPEC_SCLS (sym->etype) = S_FIXED; @@ -392,6 +393,7 @@ allocGlobal (symbol * sym) /* if it is fixed, then allocate depending on the */ /* current memory model, same for automatics */ if (SPEC_SCLS (sym->etype) == S_FIXED || + (TARGET_IS_PIC16 && (SPEC_SCLS (sym->etype) == S_REGISTER) && (sym->level==0)) || SPEC_SCLS (sym->etype) == S_AUTO) { if (port->mem.default_globl_map != xdata) { /* set the output class */ diff --git a/src/pic16/device.c b/src/pic16/device.c index bbc23023..3f730a81 100644 --- a/src/pic16/device.c +++ b/src/pic16/device.c @@ -500,6 +500,24 @@ void pic16_dump_equates(FILE *of, set *equs) } +void pic16_dump_access(FILE *of, set *section) +{ + regs *r; + + r = setFirstItem(section); + if(!r)return; + + fprintf(of, "%s", iComments2); + fprintf(of, ";\tAccess bank symbols\n"); + fprintf(of, "%s", iComments2); + + fprintf(of, "\tudata_acs\n"); + for(; r; r = setNextItem(section)) { + fprintf(of, "%s\tres\t%d\n", r->name, r->size); + } +} + + int regCompare(const void *a, const void *b) { const regs *const *i = a; @@ -936,6 +954,33 @@ int checkAddSym(set **set, symbol *sym) return 0; } +int checkSym(set *set, symbol *sym) +{ + symbol *tmp; + + if(!sym)return 0; + +#if DEUG_CHECK + fprintf(stderr, "%s: about to search for SYMbol: %s ... ", __FUNCTION__, sym->name); +#endif + + for(tmp = setFirstItem( set ); tmp; tmp = setNextItem( set )) { + if(!strcmp(tmp->name, sym->name))break; + } + + if(!tmp) { +#if DEBUG_CHECK + fprintf(stderr, "not found\n"); +#endif + return 0; + } + +#if DEBUG_CHECK + fprintf(stderr, "found\n"); +#endif + + return 1; +} /*-----------------------------------------------------------------* * void pic16_groupRegistersInSection - add each register to its * @@ -993,8 +1038,12 @@ void pic16_groupRegistersInSection(set *regset) if(!reg->isFixed) { if(reg->pc_type == PO_GPR_TEMP) checkAddReg(&pic16_int_regs, reg); - else - checkAddReg(&pic16_rel_udata, reg); + else { + if(reg->accessBank) { + checkAddReg(&pic16_acs_udata, reg); + } else + checkAddReg(&pic16_rel_udata, reg); + } } } } @@ -1012,14 +1061,26 @@ void pic16_groupRegistersInSection(set *regset) * This routine will assign a value to that address. * *-----------------------------------------------------------------*/ -void pic16_assignConfigWordValue(int address, int value) +void pic16_assignConfigWordValue(int address, unsigned int value) { int i; for(i=0;icwInfo.confAddrEnd-pic16->cwInfo.confAddrStart+1;i++) { if((address == pic16->cwInfo.confAddrStart+i) && (pic16->cwInfo.crInfo[i].mask != -1)) { -// fprintf(stderr, "setting location 0x%X to value 0x%x\n", /*address*/ pic16->cwInfo.confAddrStart+i, val + +#if 0 + fprintf(stderr, "setting location 0x%X to value 0x%x\tmask: 0x%x\ttest: 0x%x\n", + /*address*/ pic16->cwInfo.confAddrStart+i, (~value)&0xff, + pic16->cwInfo.crInfo[i].mask, + (pic16->cwInfo.crInfo[i].mask) & (~value)); +#endif + + if((((pic16->cwInfo.crInfo[i].mask) & (~value))&0xff) != ((~value)&0xff)) { + fprintf(stderr, "%s:%d a wrong value has been given for configuration register 0x%x\n", + __FILE__, __LINE__, address); + return; + } pic16->cwInfo.crInfo[i].value = value; pic16->cwInfo.crInfo[i].emit = 1; return; diff --git a/src/pic16/device.h b/src/pic16/device.h index 8c387a82..e477ef3a 100644 --- a/src/pic16/device.h +++ b/src/pic16/device.h @@ -46,9 +46,9 @@ typedef struct { typedef struct { - int mask; + unsigned int mask; int emit; - int value; + unsigned int value; } configRegInfo_t; typedef struct { @@ -112,7 +112,7 @@ extern pic16_options_t pic16_options; extern PIC16_device *pic16; /****************************************/ -void pic16_assignConfigWordValue(int address, int value); +void pic16_assignConfigWordValue(int address, unsigned int value); void pic16_assignIdByteValue(int address, char value); int pic16_isREGinBank(regs *reg, int bank); int pic16_REGallBanks(regs *reg); @@ -123,5 +123,6 @@ int PIC16_IS_HWREG_ADDRESS(int address); int checkAddReg(set **set, regs *reg); int checkAddSym(set **set, symbol *reg); +int checkSym(set *set, symbol *reg); #endif /* __DEVICE_H__ */ diff --git a/src/pic16/glue.c b/src/pic16/glue.c index e18ff33c..17767c4e 100644 --- a/src/pic16/glue.c +++ b/src/pic16/glue.c @@ -131,24 +131,25 @@ pic16emitRegularMap (memmap * map, bool addPublics, bool arFlag) for (sym = setFirstItem (map->syms); sym; sym = setNextItem (map->syms)) { -#if 1 +#if 0 fprintf(stderr, "%s\t%s: sym: %s\tused: %d\textern: %d\tstatic: %d\taggregate: %d\tregister: 0x%x\tfunction: %d\n", __FUNCTION__, map->sname, sym->name, sym->used, IS_EXTERN(sym->etype), IS_STATIC(sym->etype), - IS_AGGREGATE(sym->type), SPEC_SCLS(sym->etype), IS_FUNC(sym->type)); + IS_AGGREGATE(sym->type), (SPEC_SCLS(sym->etype) == S_REGISTER), IS_FUNC(sym->type)); printTypeChain( sym->type, stderr ); fprintf(stderr, "\n"); #endif /* if extern then add to externs */ if (IS_EXTERN (sym->etype)) { - /* reduce overhead while linking by not declaring * extern unused external functions (usually declared * in header files) */ if(IS_FUNC(sym->type) && !sym->used)continue; - checkAddSym(&externs, sym); + /* make sure symbol is not in publics section */ + if(!checkSym(publics, sym)) + checkAddSym(&externs, sym); continue; } @@ -573,7 +574,7 @@ void pic16_printGPointerType (const char *iname, const char *oname, const unsign /* set to 0 to disable debug messages */ -#define DEBUG_PRINTIVAL 1 +#define DEBUG_PRINTIVAL 0 /*-----------------------------------------------------------------*/ /* pic16_printIvalType - generates ival for int/char */ @@ -982,15 +983,13 @@ void pic16_printIvalFuncPtr (sym_link * type, initList * ilist, char ptype, void pic16_printPointerType (val->sym->rname, ptype, p); if(IS_FUNC(val->sym->type) && !val->sym->used) { - + + if(!checkSym(publics, val->sym)) + checkAddSym(&externs, val->sym); + /* this has not been declared as extern - * so declare it as a late extern just after the symbol */ - if(ptype == 'p') { - pic16_addpCode2pBlock((pBlock *)p, pic16_newpCodeCharP("declare symbol as extern")); - pic16_addpCode2pBlock((pBlock *)p, pic16_newpCodeAsmDir("extern", "%s", val->sym->rname)); - pic16_addpCode2pBlock((pBlock *)p, pic16_newpCodeCharP("continue variable declaration")); - } else - if(ptype == 'f') { + * so declare it as a 'late extern' just after the symbol */ + if(ptype == 'f') { fprintf((FILE *)p, "declare symbol as extern"); fprintf((FILE *)p, "\textern\t%s\n", val->sym->rname); fprintf((FILE *)p, "continue variable declaration"); @@ -1203,7 +1202,7 @@ pic16emitStaticSeg (memmap * map) sym = setNextItem (map->syms)) { -#if 1 +#if 0 fprintf(stderr, "%s\t%s: sym: %s\tused: %d\tSPEC_ABSA: %d\tSPEC_AGGREGATE: %d\tCODE: %d\n\ CODESPACE: %d\tCONST: %d\tPTRCONST: %d\tSPEC_CONST: %d\n", __FUNCTION__, map->sname, sym->name, sym->used, SPEC_ABSA(sym->etype), IS_AGGREGATE(sym->type), diff --git a/src/pic16/main.c b/src/pic16/main.c index 8598b4f1..727bee62 100644 --- a/src/pic16/main.c +++ b/src/pic16/main.c @@ -46,6 +46,7 @@ static char *_pic16_keywords[] = "bit", "code", "critical", + "register", "data", "far", "idata", @@ -126,14 +127,14 @@ _pic16_regparm (sym_link * l) { /* for this processor it is simple * can pass only the first parameter in a register */ -#if 0 - if(regParmFlg)return 0; - regParmFlg = 1; - return 1; -#else - regParmFlg++;// = 1; - return 1; -#endif + if(pic16_fstack) { + if(regParmFlg)return 0; + regParmFlg = 1; + return 1; + } else { + regParmFlg++;// = 1; + return 1; + } } @@ -293,6 +294,7 @@ extern int pic16_debug_verbose; extern int pic16_ralloc_debug; extern int pic16_pcode_verbose; +int pic16_fstack=0; int pic16_enable_peeps=0; OPTION pic16_optionsTable[]= { @@ -317,6 +319,7 @@ OPTION pic16_optionsTable[]= { { 0, IVT_LOC, NULL, " interrupt vector table location"}, { 0, "--calltree", &pic16_options.dumpcalltree, "dump call tree in .calltree file"}, { 0, MPLAB_COMPAT, &pic16_mplab_comp, "enable compatibility mode for MPLAB utilities (MPASM/MPLINK)"}, + { 0, "--fstack", &pic16_fstack, "enable stack optimizations"}, { 0, NULL, NULL, NULL} }; diff --git a/src/pic16/main.h b/src/pic16/main.h index 5870c9ea..387c61c0 100644 --- a/src/pic16/main.h +++ b/src/pic16/main.h @@ -33,5 +33,6 @@ extern set *sectNames; extern set *sectSyms; extern int pic16_mplab_comp; +extern int pic16_fstack; #endif diff --git a/src/pic16/ralloc.c b/src/pic16/ralloc.c index 27df5684..eeb4e787 100644 --- a/src/pic16/ralloc.c +++ b/src/pic16/ralloc.c @@ -76,10 +76,12 @@ set *pic16_dynProcessorRegs=NULL; set *pic16_dynDirectRegs=NULL; set *pic16_dynDirectBitRegs=NULL; set *pic16_dynInternalRegs=NULL; +set *pic16_dynAccessRegs=NULL; static hTab *dynDirectRegNames=NULL; static hTab *dynAllocRegNames=NULL; static hTab *dynProcRegNames=NULL; +static hTab *dynAccessRegNames=NULL; //static hTab *regHash = NULL; /* a hash table containing ALL registers */ extern set *sectNames; @@ -88,6 +90,7 @@ set *pic16_rel_udata=NULL; /* relocatable uninitialized registers */ set *pic16_fix_udata=NULL; /* absolute uninitialized registers */ set *pic16_equ_data=NULL; /* registers used by equates */ set *pic16_int_regs=NULL; /* internal registers placed in access bank 0 to 0x7f */ +set *pic16_acs_udata=NULL; /* access bank variables */ set *pic16_builtin_functions=NULL; @@ -513,7 +516,7 @@ allocReg (short type) reg->isFree=0; - debugLog ("%s of type %s for register rIdx: %d\n", __FUNCTION__, debugLogRegType (type), dynrIdx-1); +// debugLog ("%s of type %s for register rIdx: %d\n", __FUNCTION__, debugLogRegType (type), dynrIdx-1); // fprintf(stderr,"%s:%d: %s\t%s addr= 0x%x\trIdx= 0x%02x isFree: %d\n", // __FILE__, __LINE__, __FUNCTION__, reg->name, reg->address, reg->rIdx, reg->isFree); @@ -637,6 +640,40 @@ pic16_procregWithName (char *name) } +/*-----------------------------------------------------------------*/ +/* pic16_accessregWithName - search for register by name */ +/*-----------------------------------------------------------------*/ +regs * +pic16_accessregWithName (char *name) +{ + int hkey; + regs *reg; + + if(!name) + return NULL; + + /* hash the name to get a key */ + + hkey = regname2key(name); + +// fprintf(stderr, "%s:%d: name = %s\thash = %d\n", __FUNCTION__, __LINE__, name, hkey); + + reg = hTabFirstItemWK(dynAccessRegNames, hkey); + + while(reg) { + + if(STRCASECMP(reg->name, name) == 0) { + return(reg); + } + + reg = hTabNextItemWK (dynAccessRegNames); + + } + + return NULL; // name wasn't found in the hash table + +} + regs *pic16_regWithName(char *name) { regs *reg; @@ -650,6 +687,9 @@ regs *pic16_regWithName(char *name) reg = pic16_allocregWithName( name ); if(reg)return reg; + reg = pic16_accessregWithName( name ); + if(reg)return reg; + return NULL; } @@ -671,6 +711,18 @@ pic16_allocDirReg (operand *op ) name = OP_SYMBOL (op)->rname[0] ? OP_SYMBOL (op)->rname : OP_SYMBOL (op)->name; + + if(!SPEC_OCLS( OP_SYM_ETYPE(op))) { +#if 1 + if(pic16_debug_verbose) + { + fprintf(stderr, "%s:%d symbol %s(r:%s) is not assigned to a memmap\n", __FILE__, __LINE__, + OP_SYMBOL(op)->name, OP_SYMBOL(op)->rname); + } +#endif + return NULL; + } + if(!IN_DIRSPACE( SPEC_OCLS( OP_SYM_ETYPE(op))) || !IN_FARSPACE(SPEC_OCLS( OP_SYM_ETYPE(op))) ) { @@ -700,14 +752,6 @@ pic16_allocDirReg (operand *op ) return NULL; } - if(!SPEC_OCLS( OP_SYM_ETYPE(op))) { - if(pic16_debug_verbose) - { - fprintf(stderr, "%s:%d symbol %s(r:%s) is not assigned to a memmap\n", __FILE__, __LINE__, - OP_SYMBOL(op)->name, OP_SYMBOL(op)->rname); - } - return NULL; - } debugLog ("%s:%d symbol name %s\n", __FUNCTION__, __LINE__, name); // fprintf(stderr, "%s symbol name %s\n", __FUNCTION__,name); @@ -787,6 +831,17 @@ pic16_allocDirReg (operand *op ) reg = newReg(regtype, PO_DIR, rDirectIdx++, name,getSize (OP_SYMBOL (op)->type),0, op); debugLog ("%d -- added %s to hash, size = %d\n", __LINE__, name,reg->size); + if( SPEC_SCLS( OP_SYM_ETYPE( op ) ) == S_REGISTER ) { + fprintf(stderr, "%s:%d symbol %s is declared as register\n", __FILE__, __LINE__, + name); + + reg->accessBank = 1; + checkAddReg(&pic16_dynAccessRegs, reg); + hTabAddItem(&dynAccessRegNames, regname2key(name), reg); + + return (reg); + } + // if (SPEC_ABSA ( OP_SYM_ETYPE(op)) ) { // fprintf(stderr, " ralloc.c at fixed address: %s - changing to REG_SFR\n",name); @@ -1074,6 +1129,7 @@ static void writeSetUsedRegs(FILE *of, set *dRegs) extern void pic16_groupRegistersInSection(set *regset); extern void pic16_dump_equates(FILE *of, set *equs); +extern void pic16_dump_access(FILE *of, set *section); //extern void pic16_dump_map(void); extern void pic16_dump_usection(FILE *of, set *section, int fix); extern void pic16_dump_isection(FILE *of, set *section, int fix); @@ -1166,6 +1222,8 @@ void pic16_writeUsedRegs(FILE *of) // fprintf(stderr, "%s: pic16_dynProcessorRegs\n", __FUNCTION__); pic16_groupRegistersInSection(pic16_dynProcessorRegs); +// fprintf(stderr, "%s: pic16_dynAccessRegs\n", __FUNCTION__); + pic16_groupRegistersInSection(pic16_dynAccessRegs); /* dump equates */ pic16_dump_equates(of, pic16_equ_data); @@ -1173,6 +1231,9 @@ void pic16_writeUsedRegs(FILE *of) // pic16_dump_esection(of, pic16_rel_eedata, 0); // pic16_dump_esection(of, pic16_fix_eedata, 0); + /* dump access bank symbols */ + pic16_dump_access(of, pic16_acs_udata); + /* dump initialised data */ pic16_dump_isection(of, rel_idataSymSet, 0); pic16_dump_isection(of, fix_idataSymSet, 1); diff --git a/src/pic16/ralloc.h b/src/pic16/ralloc.h index 71124bbb..f41ebc24 100644 --- a/src/pic16/ralloc.h +++ b/src/pic16/ralloc.h @@ -108,6 +108,7 @@ extern set *pic16_rel_udata; extern set *pic16_fix_udata; extern set *pic16_equ_data; extern set *pic16_int_regs; +extern set *pic16_acs_udata; regs *pic16_regWithIdx (int); regs *pic16_typeRegWithIdx(int, int, int); -- 2.47.2