From e15c734f1d268e4d8eb0ea7a96b5fab1288f11c1 Mon Sep 17 00:00:00 2001 From: maartenbrock Date: Fri, 10 Feb 2006 13:37:25 +0000 Subject: [PATCH] * device/include/mcs51/at89c51snd1c.h: updated comments, see patch 1428901 * device/include/mcs51/c8051f330.h, * device/include/mcs51/c8051f350.h: used () with __at, renamed IDLE,STOP to PCON_IDLE,PCON_STOP and added sfr16 definitions * device/lib/_divsint.c, * device/lib/_divuint.c, * device/lib/_divulong.c, * device/lib/_divulong.c: renamed a,b to x,y to avoid confusion, fixed register bank bug for small stackauto git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4035 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- ChangeLog | 12 + device/include/mcs51/at89c51snd1c.h | 4 +- device/include/mcs51/c8051f330.h | 444 +++++++++++++------------- device/include/mcs51/c8051f350.h | 476 +++++++++++++++------------- device/lib/_divsint.c | 93 +++--- device/lib/_divslong.c | 152 +++++---- device/lib/_divuint.c | 85 +++-- device/lib/_divulong.c | 196 ++++++------ 8 files changed, 755 insertions(+), 707 deletions(-) diff --git a/ChangeLog b/ChangeLog index 04ffe1b0..f4901a57 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,15 @@ +2006-02-10 Maarten Brock + + * device/include/mcs51/at89c51snd1c.h: updated comments, see patch 1428901 + * device/include/mcs51/c8051f330.h, + * device/include/mcs51/c8051f350.h: used () with __at, renamed IDLE,STOP to + PCON_IDLE,PCON_STOP and added sfr16 definitions + * device/lib/_divsint.c, + * device/lib/_divuint.c, + * device/lib/_divulong.c, + * device/lib/_divulong.c: renamed a,b to x,y to avoid confusion, fixed + register bank bug for small stackauto + 2006-02-09 Maarten Brock * support/regression/fwk/lib/timeout.c: include for exit() diff --git a/device/include/mcs51/at89c51snd1c.h b/device/include/mcs51/at89c51snd1c.h index cb5b0f1e..472ea4e7 100644 --- a/device/include/mcs51/at89c51snd1c.h +++ b/device/include/mcs51/at89c51snd1c.h @@ -593,8 +593,8 @@ __sbit __at (0x98) RI ; /* Interrupt numbers: address = (number * 8) + 3 */ #define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */ #define TF0_VECTOR 1 /* 0x0b Timer 0 */ -#define IE1_VECTOR 2 /* 0x13 External Interrupt 0 */ -#define TF1_VECTOR 3 /* 0x1b Timer 0 */ +#define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */ +#define TF1_VECTOR 3 /* 0x1b Timer 1 */ #define SIO_VECTOR 4 /* 0x23 Serial port */ #define MP3_VECTOR 5 /* 0x2b MP3 Decoder */ #define AUDIO_VECTOR 6 /* 0x33 Audio Interface */ diff --git a/device/include/mcs51/c8051f330.h b/device/include/mcs51/c8051f330.h index 331d0033..f44e02b0 100644 --- a/device/include/mcs51/c8051f330.h +++ b/device/include/mcs51/c8051f330.h @@ -23,251 +23,271 @@ /* BYTE Registers */ -__sfr __at 0x80 P0 ; /* PORT 0 */ -__sfr __at 0x81 SP ; /* STACK POINTER */ -__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -__sfr __at 0x87 PCON ; /* POWER CONTROL */ -__sfr __at 0x88 TCON ; /* TIMER CONTROL */ -__sfr __at 0x89 TMOD ; /* TIMER MODE */ -__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */ -__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ -__sfr __at 0x90 P1 ; /* PORT 1 */ -__sfr __at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ -__sfr __at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ -__sfr __at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ -__sfr __at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ -__sfr __at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ -__sfr __at 0x96 IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */ -__sfr __at 0x97 IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */ -__sfr __at 0x98 SCON ; /* SERIAL PORT CONTROL */ -__sfr __at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ -__sfr __at 0x99 SBUF ; /* SERIAL PORT BUFFER */ -__sfr __at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ -__sfr __at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */ -__sfr __at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ -__sfr __at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ -__sfr __at 0xA0 P2 ; /* PORT 2 */ -__sfr __at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */ -__sfr __at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ -__sfr __at 0xA3 SPI0DAT ; /* SPI0 DATA */ -__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ -__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ -__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ -__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */ -__sfr __at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */ -__sfr __at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ -__sfr __at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */ -__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -__sfr __at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ -__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ -__sfr __at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ -__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */ -__sfr __at 0xB9 IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */ -__sfr __at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */ -__sfr __at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ -__sfr __at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ -__sfr __at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */ -__sfr __at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */ -__sfr __at 0xC0 SMB0CN ; /* SMBUS CONTROL */ -__sfr __at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ -__sfr __at 0xC2 SMB0DAT ; /* SMBUS DATA */ -__sfr __at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */ -__sfr __at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */ -__sfr __at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */ -__sfr __at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */ -__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */ -__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ -__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -__sfr __at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -__sfr __at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ -__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ -__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -__sfr __at 0xD4 P0SKIP ; /* PORT 0 SKIP */ -__sfr __at 0xD5 P1SKIP ; /* PORT 1 SKIP */ -__sfr __at 0xD8 PCA0CN ; /* PCA CONTROL */ -__sfr __at 0xD9 PCA0MD ; /* PCA MODE */ -__sfr __at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ -__sfr __at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ -__sfr __at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ -__sfr __at 0xE0 ACC ; /* ACCUMULATOR */ -__sfr __at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ -__sfr __at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ -__sfr __at 0xE3 OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */ -__sfr __at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -__sfr __at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -__sfr __at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ -__sfr __at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ -__sfr __at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ -__sfr __at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ -__sfr __at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ -__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */ -__sfr __at 0xF0 B ; /* B REGISTER */ -__sfr __at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ -__sfr __at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ -__sfr __at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ -__sfr __at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ -__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -__sfr __at 0xF8 SPI0CN ; /* SPI0 CONTROL */ -__sfr __at 0xF9 PCA0L ; /* PCA COUNTER LOW */ -__sfr __at 0xFA PCA0H ; /* PCA COUNTER HIGH */ -__sfr __at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ -__sfr __at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ -__sfr __at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */ + +__sfr __at (0x80) P0 ; /* PORT 0 */ +__sfr __at (0x81) SP ; /* STACK POINTER */ +__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */ +__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */ +__sfr __at (0x87) PCON ; /* POWER CONTROL */ +__sfr __at (0x88) TCON ; /* TIMER CONTROL */ +__sfr __at (0x89) TMOD ; /* TIMER MODE */ +__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */ +__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */ +__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */ +__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */ +__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */ +__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */ +__sfr __at (0x90) P1 ; /* PORT 1 */ +__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */ +__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */ +__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */ +__sfr __at (0x96) IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */ +__sfr __at (0x97) IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */ +__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */ +__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */ +__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */ +__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */ +__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */ +__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ +__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ +__sfr __at (0xA0) P2 ; /* PORT 2 */ +__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */ +__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ +__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */ +__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */ +__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */ +__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */ +__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */ +__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */ +__sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */ +__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */ +__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ +__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */ +__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */ +__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */ +__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */ +__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */ +__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */ +__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */ +__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */ +__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */ +__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */ +__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */ +__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */ +__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */ +__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */ +__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */ +__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */ +__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */ +__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */ +__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */ +__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */ +__sfr __at (0xD9) PCA0MD ; /* PCA MODE */ +__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ +__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ +__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ +__sfr __at (0xE0) ACC ; /* ACCUMULATOR */ +__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ +__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ +__sfr __at (0xE3) OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */ +__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */ +__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ +__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ +__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ +__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ +__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */ +__sfr __at (0xF0) B ; /* B REGISTER */ +__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ +__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ +__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ +__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ +__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */ +__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */ +__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */ +__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ +__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ +__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */ + + +/* WORD/DWORD Registers */ + +__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */ +__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */ +__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */ +__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */ +__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */ +__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */ +__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */ +__sfr16 __at (0x9796) IDA0 ; /* CURRENT MODE DAC 0 DATA WORD */ +__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */ +__sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */ +__sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */ +__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */ +__sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */ +__sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */ +__sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */ /* BIT Registers */ /* P0 0x80 */ -__sbit __at 0x80 P0_0 ; -__sbit __at 0x81 P0_1 ; -__sbit __at 0x82 P0_2 ; -__sbit __at 0x83 P0_3 ; -__sbit __at 0x84 P0_4 ; -__sbit __at 0x85 P0_5 ; -__sbit __at 0x86 P0_6 ; -__sbit __at 0x87 P0_7 ; +__sbit __at (0x80) P0_0 ; +__sbit __at (0x81) P0_1 ; +__sbit __at (0x82) P0_2 ; +__sbit __at (0x83) P0_3 ; +__sbit __at (0x84) P0_4 ; +__sbit __at (0x85) P0_5 ; +__sbit __at (0x86) P0_6 ; +__sbit __at (0x87) P0_7 ; /* TCON 0x88 */ -__sbit __at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ -__sbit __at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ -__sbit __at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ -__sbit __at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ -__sbit __at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ -__sbit __at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ -__sbit __at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ -__sbit __at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ +__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ /* P1 0x90 */ -__sbit __at 0x90 P1_0 ; -__sbit __at 0x91 P1_1 ; -__sbit __at 0x92 P1_2 ; -__sbit __at 0x93 P1_3 ; -__sbit __at 0x94 P1_4 ; -__sbit __at 0x95 P1_5 ; -__sbit __at 0x96 P1_6 ; -__sbit __at 0x97 P1_7 ; +__sbit __at (0x90) P1_0 ; +__sbit __at (0x91) P1_1 ; +__sbit __at (0x92) P1_2 ; +__sbit __at (0x93) P1_3 ; +__sbit __at (0x94) P1_4 ; +__sbit __at (0x95) P1_5 ; +__sbit __at (0x96) P1_6 ; +__sbit __at (0x97) P1_7 ; /* SCON 0x98 */ -__sbit __at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -__sbit __at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -__sbit __at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -__sbit __at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -__sbit __at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ -__sbit __at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ -__sbit __at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ -__sbit __at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ -__sbit __at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ -__sbit __at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ -__sbit __at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -__sbit __at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -__sbit __at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ -__sbit __at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */ +__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */ +__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ +__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ +__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */ +__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */ +__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ /* P2 0xA0 */ -__sbit __at 0xA0 P2_0 ; -__sbit __at 0xA1 P2_1 ; -__sbit __at 0xA2 P2_2 ; -__sbit __at 0xA3 P2_3 ; -__sbit __at 0xA4 P2_4 ; -__sbit __at 0xA5 P2_5 ; -__sbit __at 0xA6 P2_6 ; -__sbit __at 0xA7 P2_7 ; +__sbit __at (0xA0) P2_0 ; +__sbit __at (0xA1) P2_1 ; +__sbit __at (0xA2) P2_2 ; +__sbit __at (0xA3) P2_3 ; +__sbit __at (0xA4) P2_4 ; +__sbit __at (0xA5) P2_5 ; +__sbit __at (0xA6) P2_6 ; +__sbit __at (0xA7) P2_7 ; /* IE 0xA8 */ -__sbit __at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ -__sbit __at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ -__sbit __at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ -__sbit __at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ -__sbit __at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -__sbit __at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -__sbit __at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ -__sbit __at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ -__sbit __at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ +__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ +__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ /* IP 0xB8 */ -__sbit __at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ -__sbit __at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ -__sbit __at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ -__sbit __at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ -__sbit __at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ -__sbit __at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ -__sbit __at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ -__sbit __at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */ +__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */ +__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */ +__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */ +__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ +__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */ +__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */ /* SMB0CN 0xC0 */ -__sbit __at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ -__sbit __at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ -__sbit __at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ -__sbit __at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ -__sbit __at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ -__sbit __at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ -__sbit __at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ -__sbit __at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ +__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ /* TMR2CN 0xC8 */ -__sbit __at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ -__sbit __at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ -__sbit __at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ -__sbit __at 0xCD TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/ -__sbit __at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ -__sbit __at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ -__sbit __at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ -__sbit __at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ +__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +__sbit __at (0xCD) TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/ +__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ /* PSW 0xD0 */ -__sbit __at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ -__sbit __at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ -__sbit __at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ -__sbit __at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ -__sbit __at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ -__sbit __at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ -__sbit __at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ -__sbit __at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ +__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */ +__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */ +__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ +__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ +__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */ +__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ +__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */ /* PCA0CN 0xD8 */ -__sbit __at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ -__sbit __at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ -__sbit __at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ -__sbit __at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ -__sbit __at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ +__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ /* ADC0CN 0xE8 */ -__sbit __at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ -__sbit __at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ -__sbit __at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ -__sbit __at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ -__sbit __at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ -__sbit __at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ -__sbit __at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */ -__sbit __at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */ +__sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +__sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +__sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +__sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +__sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ +__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +__sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */ +__sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */ /* SPI0CN 0xF8 */ -__sbit __at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ -__sbit __at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ -__sbit __at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ -__sbit __at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ -__sbit __at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ -__sbit __at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ -__sbit __at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ -__sbit __at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ +__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ +__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ +__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ +__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ /* Predefined SFR Bit Masks */ -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ +#define PCON_IDLE 0x01 /* PCON */ +#define PCON_STOP 0x02 /* PCON */ #define T1M 0x08 /* CKCON */ #define PSWE 0x01 /* PSCTL */ #define PSEE 0x02 /* PSCTL */ diff --git a/device/include/mcs51/c8051f350.h b/device/include/mcs51/c8051f350.h index f78b55b6..84d93cef 100644 --- a/device/include/mcs51/c8051f350.h +++ b/device/include/mcs51/c8051f350.h @@ -23,265 +23,289 @@ /* BYTE Registers */ -__sfr __at 0x80 P0 ; /* PORT 0 */ -__sfr __at 0x81 SP ; /* STACK POINTER */ -__sfr __at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -__sfr __at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -__sfr __at 0x87 PCON ; /* POWER CONTROL */ -__sfr __at 0x88 TCON ; /* TIMER CONTROL */ -__sfr __at 0x89 TMOD ; /* TIMER MODE */ -__sfr __at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -__sfr __at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -__sfr __at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -__sfr __at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -__sfr __at 0x8E CKCON ; /* CLOCK CONTROL */ -__sfr __at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ -__sfr __at 0x90 P1 ; /* PORT 1 */ -__sfr __at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ -__sfr __at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ -__sfr __at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ -__sfr __at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ -__sfr __at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ -__sfr __at 0x96 IDA0 ; /* CURRENT MODE DAC 0 */ -__sfr __at 0x98 SCON ; /* SERIAL PORT CONTROL */ -__sfr __at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ -__sfr __at 0x99 SBUF ; /* SERIAL PORT BUFFER */ -__sfr __at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ -__sfr __at 0x9A ADC0DECL ; /* ADC DECIMATION LOW */ -__sfr __at 0x9B ADC0DECH ; /* ADC DECIMATION HIGH */ -__sfr __at 0x9C CPT0CN ; /* COMPARATOR 0 CONTROL */ -__sfr __at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ -__sfr __at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ -__sfr __at 0xA0 P2 ; /* PORT 2 */ -__sfr __at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */ -__sfr __at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ -__sfr __at 0xA3 SPI0DAT ; /* SPI0 DATA */ -__sfr __at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ -__sfr __at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ -__sfr __at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ -__sfr __at 0xA8 IE ; /* INTERRUPT ENABLE */ -__sfr __at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */ -__sfr __at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ -__sfr __at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */ -__sfr __at 0xAB ADC0CGL ; /* ADC 0 GAIN CALIBRATION LOW */ -__sfr __at 0xAC ADC0CGM ; /* ADC 0 GAIN CALIBRATION MIDDLE */ -__sfr __at 0xAD ADC0CGH ; /* ADC 0 GAIN CALIBRATION HIGH */ -__sfr __at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -__sfr __at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -__sfr __at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ -__sfr __at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ -__sfr __at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ -__sfr __at 0xB8 IP ; /* INTERRUPT PRIORITY */ -__sfr __at 0xB9 IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */ -__sfr __at 0xBA ADC0COL ; /* ADC 0 OFFSET CALIBRATION LOW */ -__sfr __at 0xBB ADC0COM ; /* ADC 0 OFFSET CALIBRATION MIDDLE */ -__sfr __at 0xBC ADC0COH ; /* ADC 0 OFFSET CALIBRATION HIGH */ -__sfr __at 0xBD ADC0BUF ; /* ADC 0 BUFFER CONTROL */ -__sfr __at 0xBE CLKMUL ; /* CLOCK MULTIPLIER */ -__sfr __at 0xBF ADC0DAC ; /* ADC 0 OFFSET DAC */ -__sfr __at 0xC0 SMB0CN ; /* SMBUS CONTROL */ -__sfr __at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ -__sfr __at 0xC2 SMB0DAT ; /* SMBUS DATA */ -__sfr __at 0xC3 ADC0L ; /* ADC 0 OUTPUT LOW BYTE */ -__sfr __at 0xC4 ADC0M ; /* ADC 0 OUTPUT MIDDLE BYTE */ -__sfr __at 0xC5 ADC0H ; /* ADC 0 OUTPUT HIGH BYTE */ -__sfr __at 0xC6 ADC0MUX ; /* ADC 0 MULTIPLEXER */ -__sfr __at 0xC8 T2CON ; /* TIMER 2 CONTROL */ -__sfr __at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ -__sfr __at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -__sfr __at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -__sfr __at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -__sfr __at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -__sfr __at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -__sfr __at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ -__sfr __at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -__sfr __at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ -__sfr __at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -__sfr __at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -__sfr __at 0xD4 P0SKIP ; /* PORT 0 SKIP */ -__sfr __at 0xD5 P1SKIP ; /* PORT 1 SKIP */ -__sfr __at 0xD7 IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */ -__sfr __at 0xD8 PCA0CN ; /* PCA CONTROL */ -__sfr __at 0xD9 PCA0MD ; /* PCA MODE */ -__sfr __at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ -__sfr __at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ -__sfr __at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ -__sfr __at 0xDD IDA1 ; /* CURRENT MODE DAC 1 */ -__sfr __at 0xE0 ACC ; /* ACCUMULATOR */ -__sfr __at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ -__sfr __at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ -__sfr __at 0xE3 PFE0CN ; /* PREFETCH ENGINE CONTROL */ -__sfr __at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -__sfr __at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -__sfr __at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -__sfr __at 0xE8 ADC0STA ; /* ADC 0 STATUS */ -__sfr __at 0xE9 PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ -__sfr __at 0xEA PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ -__sfr __at 0xEB PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ -__sfr __at 0xEC PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ -__sfr __at 0xED PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ -__sfr __at 0xEE PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ -__sfr __at 0xEF RSTSRC ; /* RESET SOURCE */ -__sfr __at 0xF0 B ; /* B REGISTER */ -__sfr __at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ -__sfr __at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ -__sfr __at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ -__sfr __at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ -__sfr __at 0xF3 ADC0MD ; /* ADC 0 MODE */ -__sfr __at 0xF4 ADC0CN ; /* ADC 0 CONTROL */ -__sfr __at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -__sfr __at 0xF7 ADC0CLK ; /* ADC 0 CLOCK */ -__sfr __at 0xF8 SPI0CN ; /* SPI0 CONTROL */ -__sfr __at 0xF9 PCA0L ; /* PCA COUNTER LOW */ -__sfr __at 0xFA PCA0H ; /* PCA COUNTER HIGH */ -__sfr __at 0xFB ADC0CF ; /* ADC 0 CONFIGURATION */ -__sfr __at 0xFC ADC0FL ; /* ADC 0 FAST FILTER OUTPUT LOW */ -__sfr __at 0xFD ADC0FM ; /* ADC 0 FAST FILTER OUTPUT MIDDLE */ -__sfr __at 0xFE ADC0FH ; /* ADC 0 FAST FILTER OUTPUT HIGH */ -__sfr __at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */ + +__sfr __at (0x80) P0 ; /* PORT 0 */ +__sfr __at (0x81) SP ; /* STACK POINTER */ +__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */ +__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */ +__sfr __at (0x87) PCON ; /* POWER CONTROL */ +__sfr __at (0x88) TCON ; /* TIMER CONTROL */ +__sfr __at (0x89) TMOD ; /* TIMER MODE */ +__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */ +__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */ +__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */ +__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */ +__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */ +__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */ +__sfr __at (0x90) P1 ; /* PORT 1 */ +__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */ +__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */ +__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */ +__sfr __at (0x96) IDA0 ; /* CURRENT MODE DAC 0 */ +__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */ +__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */ +__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */ +__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */ +__sfr __at (0x9A) ADC0DECL ; /* ADC DECIMATION LOW */ +__sfr __at (0x9B) ADC0DECH ; /* ADC DECIMATION HIGH */ +__sfr __at (0x9C) CPT0CN ; /* COMPARATOR 0 CONTROL */ +__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ +__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ +__sfr __at (0xA0) P2 ; /* PORT 2 */ +__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */ +__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ +__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */ +__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */ +__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */ +__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */ +__sfr __at (0xAB) ADC0CGL ; /* ADC 0 GAIN CALIBRATION LOW */ +__sfr __at (0xAC) ADC0CGM ; /* ADC 0 GAIN CALIBRATION MIDDLE */ +__sfr __at (0xAD) ADC0CGH ; /* ADC 0 GAIN CALIBRATION HIGH */ +__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */ +__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */ +__sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */ +__sfr __at (0xBA) ADC0COL ; /* ADC 0 OFFSET CALIBRATION LOW */ +__sfr __at (0xBB) ADC0COM ; /* ADC 0 OFFSET CALIBRATION MIDDLE */ +__sfr __at (0xBC) ADC0COH ; /* ADC 0 OFFSET CALIBRATION HIGH */ +__sfr __at (0xBD) ADC0BUF ; /* ADC 0 BUFFER CONTROL */ +__sfr __at (0xBE) CLKMUL ; /* CLOCK MULTIPLIER */ +__sfr __at (0xBF) ADC0DAC ; /* ADC 0 OFFSET DAC */ +__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */ +__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */ +__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */ +__sfr __at (0xC3) ADC0L ; /* ADC 0 OUTPUT LOW BYTE */ +__sfr __at (0xC4) ADC0M ; /* ADC 0 OUTPUT MIDDLE BYTE */ +__sfr __at (0xC5) ADC0H ; /* ADC 0 OUTPUT HIGH BYTE */ +__sfr __at (0xC6) ADC0MUX ; /* ADC 0 MULTIPLEXER */ +__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */ +__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */ +__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */ +__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */ +__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */ +__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */ +__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */ +__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */ +__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */ +__sfr __at (0xD7) IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */ +__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */ +__sfr __at (0xD9) PCA0MD ; /* PCA MODE */ +__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ +__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ +__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ +__sfr __at (0xDD) IDA1 ; /* CURRENT MODE DAC 1 */ +__sfr __at (0xE0) ACC ; /* ACCUMULATOR */ +__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ +__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ +__sfr __at (0xE3) PFE0CN ; /* PREFETCH ENGINE CONTROL */ +__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +__sfr __at (0xE8) ADC0STA ; /* ADC 0 STATUS */ +__sfr __at (0xE9) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ +__sfr __at (0xEA) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ +__sfr __at (0xEB) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ +__sfr __at (0xEC) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ +__sfr __at (0xED) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ +__sfr __at (0xEE) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ +__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */ +__sfr __at (0xF0) B ; /* B REGISTER */ +__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ +__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ +__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ +__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ +__sfr __at (0xF3) ADC0MD ; /* ADC 0 MODE */ +__sfr __at (0xF4) ADC0CN ; /* ADC 0 CONTROL */ +__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +__sfr __at (0xF7) ADC0CLK ; /* ADC 0 CLOCK */ +__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */ +__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */ +__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */ +__sfr __at (0xFB) ADC0CF ; /* ADC 0 CONFIGURATION */ +__sfr __at (0xFC) ADC0FL ; /* ADC 0 FAST FILTER OUTPUT LOW */ +__sfr __at (0xFD) ADC0FM ; /* ADC 0 FAST FILTER OUTPUT MIDDLE */ +__sfr __at (0xFE) ADC0FH ; /* ADC 0 FAST FILTER OUTPUT HIGH */ +__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */ + + +/* WORD/DWORD Registers */ + +__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */ +__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */ +__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */ +__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */ +__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */ +__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */ +__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */ + +__sfr16 __at (0x9B9A) ADC0DEC ; /* ADC 0 DECIMATION RATIO REGISTER WORD */ +/* Unfortunately the C8051F350 does not have an sfr that always reads 0x00 and */ +/* ignores what is written to it. That could have enabled sfr32 definitions for */ +/* the 24 bit ADC0 sfr combinations. */ +__sfr16 __at (0xC5C4) ADC0 ; /* 16 bit ADC 0 SINC3 FILTER OUTPUT WORD */ +__sfr16 __at (0xFEFD) ADC0F ; /* 16 bit ADC 0 FAST FILTER OUTPUT WORD */ + +__sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */ +__sfr16 __at (0xEAE9) PCA0CP0 ; /* PCA CAPTURE 0 WORD */ +__sfr16 __at (0xECEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */ +__sfr16 __at (0xEEED) PCA0CP2 ; /* PCA CAPTURE 2 WORD */ /* BIT Registers */ /* P0 0x80 */ -__sbit __at 0x80 P0_0 ; -__sbit __at 0x81 P0_1 ; -__sbit __at 0x82 P0_2 ; -__sbit __at 0x83 P0_3 ; -__sbit __at 0x84 P0_4 ; -__sbit __at 0x85 P0_5 ; -__sbit __at 0x86 P0_6 ; -__sbit __at 0x87 P0_7 ; +__sbit __at (0x80) P0_0 ; +__sbit __at (0x81) P0_1 ; +__sbit __at (0x82) P0_2 ; +__sbit __at (0x83) P0_3 ; +__sbit __at (0x84) P0_4 ; +__sbit __at (0x85) P0_5 ; +__sbit __at (0x86) P0_6 ; +__sbit __at (0x87) P0_7 ; /* TCON 0x88 */ -__sbit __at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ -__sbit __at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ -__sbit __at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ -__sbit __at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ -__sbit __at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ -__sbit __at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ -__sbit __at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ -__sbit __at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ +__sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +__sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +__sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +__sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +__sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +__sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +__sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +__sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ /* P1 0x90 */ -__sbit __at 0x90 P1_0 ; -__sbit __at 0x91 P1_1 ; -__sbit __at 0x92 P1_2 ; -__sbit __at 0x93 P1_3 ; -__sbit __at 0x94 P1_4 ; -__sbit __at 0x95 P1_5 ; -__sbit __at 0x96 P1_6 ; -__sbit __at 0x97 P1_7 ; +__sbit __at (0x90) P1_0 ; +__sbit __at (0x91) P1_1 ; +__sbit __at (0x92) P1_2 ; +__sbit __at (0x93) P1_3 ; +__sbit __at (0x94) P1_4 ; +__sbit __at (0x95) P1_5 ; +__sbit __at (0x96) P1_6 ; +__sbit __at (0x97) P1_7 ; /* SCON 0x98 */ -__sbit __at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -__sbit __at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -__sbit __at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -__sbit __at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -__sbit __at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ -__sbit __at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ -__sbit __at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ -__sbit __at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ -__sbit __at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ -__sbit __at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ -__sbit __at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -__sbit __at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -__sbit __at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ -__sbit __at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +__sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +__sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +__sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +__sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +__sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */ +__sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */ +__sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ +__sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ +__sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */ +__sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */ +__sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +__sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +__sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +__sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ /* P2 0xA0 */ -__sbit __at 0xA0 P2_0 ; -__sbit __at 0xA1 P2_1 ; -__sbit __at 0xA2 P2_2 ; -__sbit __at 0xA3 P2_3 ; -__sbit __at 0xA4 P2_4 ; -__sbit __at 0xA5 P2_5 ; -__sbit __at 0xA6 P2_6 ; -__sbit __at 0xA7 P2_7 ; +__sbit __at (0xA0) P2_0 ; +__sbit __at (0xA1) P2_1 ; +__sbit __at (0xA2) P2_2 ; +__sbit __at (0xA3) P2_3 ; +__sbit __at (0xA4) P2_4 ; +__sbit __at (0xA5) P2_5 ; +__sbit __at (0xA6) P2_6 ; +__sbit __at (0xA7) P2_7 ; /* IE 0xA8 */ -__sbit __at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ -__sbit __at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ -__sbit __at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ -__sbit __at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ -__sbit __at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -__sbit __at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -__sbit __at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ -__sbit __at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ -__sbit __at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ +__sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +__sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +__sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +__sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +__sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +__sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +__sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +__sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ +__sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ /* IP 0xB8 */ -__sbit __at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ -__sbit __at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ -__sbit __at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ -__sbit __at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ -__sbit __at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ -__sbit __at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ -__sbit __at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ -__sbit __at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */ +__sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +__sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */ +__sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +__sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */ +__sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */ +__sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ +__sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */ +__sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */ /* SMB0CN 0xC0 */ -__sbit __at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ -__sbit __at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ -__sbit __at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ -__sbit __at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ -__sbit __at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ -__sbit __at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ -__sbit __at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ -__sbit __at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ +__sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +__sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +__sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +__sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +__sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +__sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +__sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +__sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ /* TMR2CN 0xC8 */ -__sbit __at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ -__sbit __at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ -__sbit __at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ -__sbit __at 0xCD TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/ -__sbit __at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ -__sbit __at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ -__sbit __at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ -__sbit __at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ +__sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +__sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +__sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +__sbit __at (0xCD) TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/ +__sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +__sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +__sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +__sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ /* PSW 0xD0 */ -__sbit __at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ -__sbit __at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ -__sbit __at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ -__sbit __at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ -__sbit __at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ -__sbit __at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ -__sbit __at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ -__sbit __at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ +__sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +__sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */ +__sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */ +__sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ +__sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ +__sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */ +__sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ +__sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */ /* PCA0CN 0xD8 */ -__sbit __at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ -__sbit __at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ -__sbit __at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ -__sbit __at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ -__sbit __at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ +__sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +__sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +__sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +__sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +__sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ /* ADC0STA 0xE8 */ -__sbit __at 0xE8 AD0OVR ; /* ADC0CN.0 - ADC 0 OVERRUN FLAG */ -__sbit __at 0xE9 AD0ERR ; /* ADC0CN.1 - ADC 0 ERROR FLAG */ -__sbit __at 0xEA AD0CALC ; /* ADC0CN.2 - ADC 0 CALIBRATION COMPLETE FLAG */ -__sbit __at 0xEB AD0FFC ; /* ADC0CN.3 - ADC 0 FAST FILTER CLIP FLAG */ -__sbit __at 0xEC AD0S3C ; /* ADC0CN.4 - ADC 0 SINC3 FILTER CLIP FLAG */ -__sbit __at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ -__sbit __at 0xEE AD0CBSY ; /* ADC0CN.6 - ADC 0 CALIBRATION IN PROGRESS FLAG */ -__sbit __at 0xEF AD0BUSY ; /* ADC0CN.7 - ADC 0 CONVERSION IN PROGRESS FLAG */ +__sbit __at (0xE8) AD0OVR ; /* ADC0CN.0 - ADC 0 OVERRUN FLAG */ +__sbit __at (0xE9) AD0ERR ; /* ADC0CN.1 - ADC 0 ERROR FLAG */ +__sbit __at (0xEA) AD0CALC ; /* ADC0CN.2 - ADC 0 CALIBRATION COMPLETE FLAG */ +__sbit __at (0xEB) AD0FFC ; /* ADC0CN.3 - ADC 0 FAST FILTER CLIP FLAG */ +__sbit __at (0xEC) AD0S3C ; /* ADC0CN.4 - ADC 0 SINC3 FILTER CLIP FLAG */ +__sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +__sbit __at (0xEE) AD0CBSY ; /* ADC0CN.6 - ADC 0 CALIBRATION IN PROGRESS FLAG */ +__sbit __at (0xEF) AD0BUSY ; /* ADC0CN.7 - ADC 0 CONVERSION IN PROGRESS FLAG */ /* SPI0CN 0xF8 */ -__sbit __at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ -__sbit __at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ -__sbit __at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ -__sbit __at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ -__sbit __at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ -__sbit __at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ -__sbit __at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ -__sbit __at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ +__sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ +__sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +__sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +__sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +__sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +__sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ +__sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ +__sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ /* Predefined SFR Bit Masks */ -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ +#define PCON_IDLE 0x01 /* PCON */ +#define PCON_STOP 0x02 /* PCON */ #define T1M 0x08 /* CKCON */ #define PSWE 0x01 /* PSCTL */ #define PSEE 0x02 /* PSCTL */ diff --git a/device/lib/_divsint.c b/device/lib/_divsint.c index ce31bd17..229bb2f4 100644 --- a/device/lib/_divsint.c +++ b/device/lib/_divsint.c @@ -27,7 +27,7 @@ #include #if _SDCC_MANGLES_SUPPORT_FUNS -unsigned unsigned _divuint (unsigned a, unsigned b); +unsigned unsigned _divuint (unsigned x, unsigned y); #endif /* Assembler-functions are provided for: @@ -54,53 +54,53 @@ _divsint_dummy (void) _naked { _asm - #define a0 dpl - #define a1 dph + #define xl dpl + #define xh dph .globl __divsint // _divsint_PARM_2 shares the same memory with _divuint_PARM_2 // and is defined in _divuint.c #if defined(SDCC_PARMS_IN_BANK1) - #define b0 (b1_0) - #define b1 (b1_1) + #define yl (b1_0) + #define yh (b1_1) #else - #define b0 (__divsint_PARM_2) - #define b1 (__divsint_PARM_2 + 1) + #define yl (__divsint_PARM_2) + #define yh (__divsint_PARM_2 + 1) #endif __divsint: - ; a1 in dph - ; b1 in (__divsint_PARM_2 + 1) + ; xh in dph + ; yh in (__divsint_PARM_2 + 1) clr F0 ; Flag 0 in PSW ; available to user for general purpose - mov a,a1 + mov a,xh jnb acc.7,a_not_negative setb F0 clr a clr c - subb a,a0 - mov a0,a + subb a,xl + mov xl,a clr a - subb a,a1 - mov a1,a + subb a,xh + mov xh,a a_not_negative: - mov a,b1 + mov a,yh jnb acc.7,b_not_negative cpl F0 clr a clr c - subb a,b0 - mov b0,a + subb a,yl + mov yl,a clr a - subb a,b1 - mov b1,a + subb a,yh + mov yh,a b_not_negative: @@ -110,11 +110,11 @@ _divsint_dummy (void) _naked clr a clr c - subb a,a0 - mov a0,a + subb a,xl + mov xl,a clr a - subb a,a1 - mov a1,a + subb a,xh + mov xh,a not_negative: ret @@ -129,11 +129,8 @@ _divsint_dummy (void) _naked { _asm - #define a0 dpl - #define a1 dph - - ar0 = 0 ; BUG register set is not considered - ar1 = 1 + #define xl dpl + #define xh dph .globl __divsint @@ -141,25 +138,25 @@ _divsint_dummy (void) _naked clr F0 ; Flag 0 in PSW ; available to user for general purpose - mov a,a1 + mov a,xh jnb acc.7,a_not_negative setb F0 clr a clr c - subb a,a0 - mov a0,a + subb a,xl + mov xl,a clr a - subb a,a1 - mov a1,a + subb a,xh + mov xh,a a_not_negative: mov a,sp add a,#-2 ; 2 bytes return address - mov r0,a ; r0 points to b1 - mov a,@r0 ; b1 + mov r0,a ; r0 points to yh + mov a,@r0 ; a = yh jnb acc.7,b_not_negative @@ -169,18 +166,18 @@ _divsint_dummy (void) _naked clr a clr c - subb a,@r0 ; b0 + subb a,@r0 ; yl mov @r0,a clr a inc r0 - subb a,@r0 ; b1 - mov @r0,a + subb a,@r0 ; a = yh b_not_negative: - mov ar1,@r0 ; b1 + mov r1,a ; yh dec r0 - mov ar0,@r0 ; b0 + mov a,@r0 ; yl + mov r0,a lcall __divint @@ -188,11 +185,11 @@ _divsint_dummy (void) _naked clr a clr c - subb a,a0 - mov a0,a + subb a,xl + mov xl,a clr a - subb a,a1 - mov a1,a + subb a,xh + mov xh,a not_negative: ret @@ -203,13 +200,13 @@ _divsint_dummy (void) _naked #else // _DIVSINT_ASM_ int -_divsint (int a, int b) +_divsint (int x, int y) { register int r; - r = _divuint((a < 0 ? -a : a), - (b < 0 ? -b : b)); - if ( (a < 0) ^ (b < 0)) + r = _divuint((x < 0 ? -x : x), + (y < 0 ? -y : y)); + if ( (x < 0) ^ (y < 0)) return -r; else return r; diff --git a/device/lib/_divslong.c b/device/lib/_divslong.c index 748ef92a..2a8c03d0 100644 --- a/device/lib/_divslong.c +++ b/device/lib/_divslong.c @@ -26,7 +26,7 @@ #include #if _SDCC_MANGLES_SUPPORT_FUNS -unsigned long _divulong (unsigned long a, unsigned long b); +unsigned long _divulong (unsigned long x, unsigned long y); #endif /* Assembler-functions are provided for: @@ -53,30 +53,30 @@ _divslong_dummy (void) _naked { _asm - #define a0 dpl - #define a1 dph - #define a2 b - #define a3 r3 + #define x0 dpl + #define x1 dph + #define x2 b + #define x3 r3 .globl __divslong // _divslong_PARM_2 shares the same memory with _divulong_PARM_2 // and is defined in _divulong.c #if defined(SDCC_PARMS_IN_BANK1) - #define b0 (b1_0) - #define b1 (b1_1) - #define b2 (b1_2) - #define b3 (b1_3) + #define y0 (b1_0) + #define y1 (b1_1) + #define y2 (b1_2) + #define y3 (b1_3) #else - #define b0 (__divslong_PARM_2) - #define b1 (__divslong_PARM_2 + 1) - #define b2 (__divslong_PARM_2 + 2) - #define b3 (__divslong_PARM_2 + 3) + #define y0 (__divslong_PARM_2) + #define y1 (__divslong_PARM_2 + 1) + #define y2 (__divslong_PARM_2 + 2) + #define y3 (__divslong_PARM_2 + 3) #endif __divslong: - ; a3 in acc - ; b3 in (__divslong_PARM_2 + 3) - mov a3,a ; save a3 + ; x3 in acc + ; y3 in (__divslong_PARM_2 + 3) + mov x3,a ; save x3 clr F0 ; Flag 0 in PSW ; available to user for general purpose @@ -86,62 +86,61 @@ _divslong_dummy (void) _naked clr a clr c - subb a,a0 - mov a0,a + subb a,x0 + mov x0,a clr a - subb a,a1 - mov a1,a + subb a,x1 + mov x1,a clr a - subb a,a2 - mov a2,a + subb a,x2 + mov x2,a clr a - subb a,a3 - mov a3,a + subb a,x3 + mov x3,a a_not_negative: - mov a,b3 + mov a,y3 jnb acc.7,b_not_negative cpl F0 clr a clr c - subb a,b0 - mov b0,a + subb a,y0 + mov y0,a clr a - subb a,b1 - mov b1,a + subb a,y1 + mov y1,a clr a - subb a,b2 - mov b2,a + subb a,y2 + mov y2,a clr a - subb a,b3 - mov b3,a + subb a,y3 + mov y3,a b_not_negative: - mov a,a3 ; restore a3 in acc + mov a,x3 ; restore x3 in acc lcall __divulong jnb F0,not_negative - mov a3,a ; save a3 + mov x3,a ; save x3 clr a clr c - subb a,a0 - mov a0,a + subb a,x0 + mov x0,a clr a - subb a,a1 - mov a1,a + subb a,x1 + mov x1,a clr a - subb a,a2 - mov a2,a + subb a,x2 + mov x2,a clr a - subb a,a3 - mov a3,a + subb a,x3 ; x3 ends in acc not_negative: ret @@ -156,17 +155,17 @@ _divslong_dummy (void) _naked { _asm - #define a0 dpl - #define a1 dph - #define a2 b - #define a3 r3 + #define x0 dpl + #define x1 dph + #define x2 b + #define x3 r3 .globl __divslong __divslong: - ; a3 in acc - mov a3,a ; save a3 + ; x3 in acc + mov x3,a ; save x3 clr F0 ; Flag 0 in PSW ; available to user for general purpose @@ -176,24 +175,24 @@ _divslong_dummy (void) _naked clr a clr c - subb a,a0 - mov a0,a + subb a,x0 + mov x0,a clr a - subb a,a1 - mov a1,a + subb a,x1 + mov x1,a clr a - subb a,a2 - mov a2,a + subb a,x2 + mov x2,a clr a - subb a,a3 - mov a3,a + subb a,x3 + mov x3,a a_not_negative: mov a,sp add a,#-2 ; 2 bytes return address - mov r0,a ; r0 points to b3 - mov a,@r0 ; b3 + mov r0,a ; r0 points to y3 + mov a,@r0 ; y3 jnb acc.7,b_not_negative @@ -205,45 +204,44 @@ _divslong_dummy (void) _naked clr a clr c - subb a,@r0 ; b0 + subb a,@r0 ; y0 mov @r0,a clr a inc r0 - subb a,@r0 ; b1 + subb a,@r0 ; y1 mov @r0,a clr a inc r0 - subb a,@r0 ; b2 + subb a,@r0 ; y2 mov @r0,a clr a inc r0 - subb a,@r0 ; b3 + subb a,@r0 ; y3 mov @r0,a b_not_negative: dec r0 dec r0 - dec r0 ; r0 points to b0 + dec r0 ; r0 points to y0 lcall __divlong jnb F0,not_negative - mov a3,a ; save a3 + mov x3,a ; save x3 clr a clr c - subb a,a0 - mov a0,a + subb a,x0 + mov x0,a clr a - subb a,a1 - mov a1,a + subb a,x1 + mov x1,a clr a - subb a,a2 - mov a2,a + subb a,x2 + mov x2,a clr a - subb a,a3 - mov a3,a + subb a,x3 ; x3 ends in acc not_negative: ret @@ -254,13 +252,13 @@ _divslong_dummy (void) _naked #else // _DIVSLONG_ASM long -_divslong (long a, long b) +_divslong (long x, long y) { long r; - r = _divulong((a < 0 ? -a : a), - (b < 0 ? -b : b)); - if ( (a < 0) ^ (b < 0)) + r = _divulong((x < 0 ? -x : x), + (y < 0 ? -y : y)); + if ( (x < 0) ^ (y < 0)) return -r; else return r; diff --git a/device/lib/_divuint.c b/device/lib/_divuint.c index fc839c55..03b91998 100644 --- a/device/lib/_divuint.c +++ b/device/lib/_divuint.c @@ -55,37 +55,39 @@ _divuint_dummy (void) _naked #define count r2 #define reste_l r3 #define reste_h r4 - #define al dpl - #define ah dph + #define xl dpl + #define xh dph -#if defined(SDCC_STACK_AUTO) && !defined(SDCC_PARMS_IN_BANK1) - - ar0 = 0 ; BUG register set is not considered - ar1 = 1 +#if defined(SDCC_PARMS_IN_BANK1) + #define yl (b1_0) + #define yh (b1_1) +#else // SDCC_PARMS_IN_BANK1 + #if defined(SDCC_STACK_AUTO) .globl __divint mov a,sp add a,#-2 ; 2 bytes return address - mov r0,a ; r0 points to bh - mov ar1,@r0 ; load bh + mov r0,a ; r0 points to yh + mov a,@r0 ; load yh + mov r1,a dec r0 - mov ar0,@r0 ; load bl + mov a,@r0 ; load yl + mov r0,a - #define bl r0 - #define bh r1 + #define yl r0 + #define yh r1 __divint: ; entry point for __divsint -#else // SDCC_STACK_AUTO + #else // SDCC_STACK_AUTO -#if !defined(SDCC_PARMS_IN_BANK1) -#if defined(SDCC_NOOVERLAY) + #if defined(SDCC_NOOVERLAY) .area DSEG (DATA) -#else + #else .area OSEG (OVR,DATA) -#endif + #endif .globl __divuint_PARM_2 .globl __divsint_PARM_2 @@ -95,27 +97,24 @@ _divuint_dummy (void) _naked .ds 2 .area CSEG (CODE) -#endif // !SDCC_PARMS_IN_BANK1 -#if defined(SDCC_PARMS_IN_BANK1) - #define bl (b1_0) - #define bh (b1_1) -#else - #define bl (__divuint_PARM_2) - #define bh (__divuint_PARM_2 + 1) + + #define yl (__divuint_PARM_2) + #define yh (__divuint_PARM_2 + 1) + + #endif // SDCC_STACK_AUTO #endif // SDCC_PARMS_IN_BANK1 -#endif // SDCC_STACK_AUTO mov count,#16 clr a mov reste_l,a mov reste_h,a - loop: mov a,al ; a <<= 1 + loop: mov a,xl ; x <<= 1 add a,acc - mov al,a - mov a,ah + mov xl,a + mov a,xh rlc a - mov ah,a + mov xh,a mov a,reste_l ; reste <<= 1 rlc a ; feed in carry @@ -124,18 +123,18 @@ _divuint_dummy (void) _naked rlc a mov reste_h,a - mov a,reste_l ; reste - b - subb a,bl ; here carry is always clear, because + mov a,reste_l ; reste - y + subb a,yl ; here carry is always clear, because ; reste <<= 1 never overflows mov b,a mov a,reste_h - subb a,bh + subb a,yh - jc smaller ; reste >= b? + jc smaller ; reste >= y? - mov reste_h,a ; -> yes; reste = reste - b; + mov reste_h,a ; -> yes; reste = reste - y; mov reste_l,b - orl al,#1 + orl xl,#1 smaller: ; -> no djnz count,loop ret @@ -148,7 +147,7 @@ _divuint_dummy (void) _naked #define MSB_SET(x) ((x >> (8*sizeof(x)-1)) & 1) unsigned int -_divuint (unsigned int a, unsigned int b) +_divuint (unsigned int x, unsigned int y) { unsigned int reste = 0; unsigned char count = 16; @@ -156,22 +155,22 @@ _divuint (unsigned int a, unsigned int b) do { - // reste: a <- 0; - c = MSB_SET(a); - a <<= 1; + // reste: x <- 0; + c = MSB_SET(x); + x <<= 1; reste <<= 1; if (c) reste |= 1; - if (reste >= b) + if (reste >= y) { - reste -= b; - // a <- (result = 1) - a |= 1; + reste -= y; + // x <- (result = 1) + x |= 1; } } while (--count); - return a; + return x; } #endif // defined _DIVUINT_ASM_SMALL || defined _DIVUINT_ASM_SMALL_AUTO diff --git a/device/lib/_divulong.c b/device/lib/_divulong.c index de60a849..53a2b87c 100644 --- a/device/lib/_divulong.c +++ b/device/lib/_divulong.c @@ -54,10 +54,10 @@ _divlong_dummy (void) _naked #define count r2 - #define a0 dpl - #define a1 dph - #define a2 b - #define a3 r3 + #define x0 dpl + #define x1 dph + #define x2 b + #define x3 r3 #define reste0 r4 #define reste1 r5 @@ -80,18 +80,18 @@ _divlong_dummy (void) _naked .area CSEG (CODE) - #define b0 (__divulong_PARM_2) - #define b1 (__divulong_PARM_2 + 1) - #define b2 (__divulong_PARM_2 + 2) - #define b3 (__divulong_PARM_2 + 3) + #define y0 (__divulong_PARM_2) + #define y1 (__divulong_PARM_2 + 1) + #define y2 (__divulong_PARM_2 + 2) + #define y3 (__divulong_PARM_2 + 3) #else - #define b0 (b1_0) - #define b1 (b1_1) - #define b2 (b1_2) - #define b3 (b1_3) + #define y0 (b1_0) + #define y1 (b1_1) + #define y2 (b1_2) + #define y3 (b1_3) #endif // !SDCC_PARMS_IN_BANK1 - ; parameter a comes in a, b, dph, dpl - mov a3,a ; save parameter a3 + ; parameter x comes in a, b, dph, dpl + mov x3,a ; save parameter x3 mov count,#32 clr a @@ -102,36 +102,36 @@ _divlong_dummy (void) _naked ; optimization loop in lp0 until the first bit is shifted into rest - lp0: mov a,a0 ; a <<= 1 - add a,a0 - mov a0,a - mov a,a1 + lp0: mov a,x0 ; x <<= 1 + add a,x0 + mov x0,a + mov a,x1 rlc a - mov a1,a - mov a,a2 + mov x1,a + mov a,x2 rlc a - mov a2,a - mov a,a3 + mov x2,a + mov a,x3 rlc a - mov a3,a + mov x3,a jc in_lp djnz count,lp0 sjmp exit - loop: mov a,a0 ; a <<= 1 - add a,a0 - mov a0,a - mov a,a1 + loop: mov a,x0 ; x <<= 1 + add a,x0 + mov x0,a + mov a,x1 rlc a - mov a1,a - mov a,a2 + mov x1,a + mov a,x2 rlc a - mov a2,a - mov a,a3 + mov x2,a + mov a,x3 rlc a - mov a3,a + mov x3,a in_lp: mov a,reste0 ; reste <<= 1 rlc a ; feed in carry @@ -146,37 +146,37 @@ _divlong_dummy (void) _naked rlc a mov reste3,a - mov a,reste0 ; reste - b - subb a,b0 ; carry is always clear here, because + mov a,reste0 ; reste - y + subb a,y0 ; carry is always clear here, because ; reste <<= 1 never overflows mov a,reste1 - subb a,b1 + subb a,y1 mov a,reste2 - subb a,b2 + subb a,y2 mov a,reste3 - subb a,b3 + subb a,y3 - jc minus ; reste >= b? + jc minus ; reste >= y? - ; -> yes; reste -= b; + ; -> yes; reste -= y; mov a,reste0 - subb a,b0 ; carry is always clear here (jc) + subb a,y0 ; carry is always clear here (jc) mov reste0,a mov a,reste1 - subb a,b1 + subb a,y1 mov reste1,a mov a,reste2 - subb a,b2 + subb a,y2 mov reste2,a mov a,reste3 - subb a,b3 + subb a,y3 mov reste3,a - orl a0,#1 + orl x0,#1 minus: djnz count,loop ; -> no - exit: mov a,a3 ; prepare the return value + exit: mov a,x3 ; prepare the return value ret _endasm ; @@ -195,10 +195,10 @@ _divlong_dummy (void) _naked #define count r2 - #define a0 dpl - #define a1 dph - #define a2 b - #define a3 r3 + #define x0 dpl + #define x1 dph + #define x2 b + #define x3 r3 #define reste0 r4 #define reste1 r5 @@ -207,22 +207,20 @@ _divlong_dummy (void) _naked .globl __divlong ; entry point for __divslong - #define b0 r1 + #define y0 r1 - ar0 = 0 ; BUG register set is not considered - ar1 = 1 - - ; parameter a comes in a, b, dph, dpl - mov a3,a ; save parameter a3 + ; parameter x comes in a, b, dph, dpl + mov x3,a ; save parameter x3 mov a,sp - add a,#-2-3 ; 2 bytes return address, 3 bytes param b - mov r0,a ; r0 points to b0 + add a,#-2-3 ; 2 bytes return address, 3 bytes param y + mov r0,a ; r0 points to y0 __divlong: ; entry point for __divslong - mov ar1,@r0 ; load b0 - inc r0 ; r0 points to b1 + mov a,@r0 ; load y0 + mov r1,a + inc r0 ; r0 points to y1 mov count,#32 clr a @@ -233,36 +231,36 @@ _divlong_dummy (void) _naked ; optimization loop in lp0 until the first bit is shifted into rest - lp0: mov a,a0 ; a <<= 1 - add a,a0 - mov a0,a - mov a,a1 + lp0: mov a,x0 ; x <<= 1 + add a,x0 + mov x0,a + mov a,x1 rlc a - mov a1,a - mov a,a2 + mov x1,a + mov a,x2 rlc a - mov a2,a - mov a,a3 + mov x2,a + mov a,x3 rlc a - mov a3,a + mov x3,a jc in_lp djnz count,lp0 sjmp exit - loop: mov a,a0 ; a <<= 1 - add a,a0 - mov a0,a - mov a,a1 + loop: mov a,x0 ; x <<= 1 + add a,x0 + mov x0,a + mov a,x1 rlc a - mov a1,a - mov a,a2 + mov x1,a + mov a,x2 rlc a - mov a2,a - mov a,a3 + mov x2,a + mov a,x3 rlc a - mov a3,a + mov x3,a in_lp: mov a,reste0 ; reste <<= 1 rlc a ; feed in carry @@ -277,45 +275,45 @@ _divlong_dummy (void) _naked rlc a mov reste3,a - mov a,reste0 ; reste - b - subb a,b0 ; carry is always clear here, because + mov a,reste0 ; reste - y + subb a,y0 ; carry is always clear here, because ; reste <<= 1 never overflows mov a,reste1 - subb a,@r0 ; b1 + subb a,@r0 ; y1 mov a,reste2 inc r0 - subb a,@r0 ; b2 + subb a,@r0 ; y2 mov a,reste3 inc r0 - subb a,@r0 ; b3 + subb a,@r0 ; y3 dec r0 dec r0 - jc minus ; reste >= b? + jc minus ; reste >= y? - ; -> yes; reste -= b; + ; -> yes; reste -= y; mov a,reste0 - subb a,b0 ; carry is always clear here (jc) + subb a,y0 ; carry is always clear here (jc) mov reste0,a mov a,reste1 - subb a,@r0 ; b1 + subb a,@r0 ; y1 mov reste1,a mov a,reste2 inc r0 - subb a,@r0 ; b2 + subb a,@r0 ; y2 mov reste2,a mov a,reste3 inc r0 - subb a,@r0 ; b3 + subb a,@r0 ; y3 mov reste3,a dec r0 dec r0 - orl a0,#1 + orl x0,#1 minus: djnz count,loop ; -> no - exit: mov a,a3 ; prepare the return value + exit: mov a,x3 ; prepare the return value ret _endasm ; @@ -326,7 +324,7 @@ _divlong_dummy (void) _naked #define MSB_SET(x) ((x >> (8*sizeof(x)-1)) & 1) unsigned long -_divulong (unsigned long a, unsigned long b) +_divulong (unsigned long x, unsigned long y) { unsigned long reste = 0L; unsigned char count = 32; @@ -334,22 +332,22 @@ _divulong (unsigned long a, unsigned long b) do { - // reste: a <- 0; - c = MSB_SET(a); - a <<= 1; + // reste: x <- 0; + c = MSB_SET(x); + x <<= 1; reste <<= 1; if (c) reste |= 1L; - if (reste >= b) + if (reste >= y) { - reste -= b; - // a <- (result = 1) - a |= 1L; + reste -= y; + // x <- (result = 1) + x |= 1L; } } while (--count); - return a; + return x; } #endif // _DIVULONG_ASM -- 2.47.2