From a12f1cf34c26ff9f0c1c15ece0d1c6a2d8f3b394 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
Date: Tue, 15 Dec 2015 01:20:57 +0100
Subject: [PATCH] tcl/target: Add Renesas S7G2 config
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Tested with Renesas DK-S7G2M v3.0 board.

Change-Id: Ia6acaf70271ed4eb7bc4e921552cbd2ff83f6acb
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3169
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
---
 tcl/target/renesas_s7g2.cfg | 50 +++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 tcl/target/renesas_s7g2.cfg

diff --git a/tcl/target/renesas_s7g2.cfg b/tcl/target/renesas_s7g2.cfg
new file mode 100644
index 000000000..a09377b2d
--- /dev/null
+++ b/tcl/target/renesas_s7g2.cfg
@@ -0,0 +1,50 @@
+#
+# Renesas Synergy S7 G2 w/ ARM Cortex-M4 @ 240 MHz
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME s7g2
+}
+
+if { [info exists CPU_JTAG_TAPID] } {
+	set _CPU_JTAG_TAPID $CPU_JTAG_TAPID
+} else {
+	set _CPU_JTAG_TAPID 0x5ba00477
+}
+
+if { [info exists CPU_SWD_TAPID] } {
+	set _CPU_SWD_TAPID $CPU_SWD_TAPID
+} else {
+	set _CPU_SWD_TAPID 0x5ba02477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+	set _CPU_TAPID $_CPU_JTAG_TAPID
+} else {
+	set _CPU_TAPID $_CPU_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	# 640 KB On-Chip SRAM
+	set _WORKAREASIZE 0xa0000
+}
+
+$_TARGETNAME configure -work-area-phys 0x1ffe0000 \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { ![using_hla] } {
+	cortex_m reset_config sysresetreq
+}
+
+adapter_khz 1000
-- 
2.30.2