From 9f9ac23c9c02e27449d62e58d260cf97e7a1eb9c Mon Sep 17 00:00:00 2001 From: kbongers Date: Thu, 30 Aug 2001 17:40:56 +0000 Subject: [PATCH] add ds390 processor git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1195 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- sim/ucsim/doc/invoke.html | 2 +- sim/ucsim/s51.src/Makefile.in | 2 +- sim/ucsim/s51.src/glob.cc | 4 + sim/ucsim/s51.src/regs51.h | 3 + sim/ucsim/s51.src/sim51.cc | 3 + sim/ucsim/s51.src/uc390.cc | 305 ++++++++++++++++++++++++++++++++++ sim/ucsim/s51.src/uc390cl.h | 55 ++++++ sim/ucsim/stypes.h | 3 +- 8 files changed, 374 insertions(+), 3 deletions(-) create mode 100644 sim/ucsim/s51.src/uc390.cc create mode 100644 sim/ucsim/s51.src/uc390cl.h diff --git a/sim/ucsim/doc/invoke.html b/sim/ucsim/doc/invoke.html index db9301b3..f6f1c139 100644 --- a/sim/ucsim/doc/invoke.html +++ b/sim/ucsim/doc/invoke.html @@ -30,7 +30,7 @@ them in specified order into the ROM of the simulated system.
Type of CPU. Recognized types are: 51, 8051, 8751, C51, 80C51, 87C51, 31, 8031, C31, 80C31, 52, 8052, 8752, C52, 80C52, 87C52, 32, 8032, C32, 80C32, 51R, 51RA, 51RB, 51RC, C51R, C51RA, C51RB, C51RC, -89C51R, 251, C251. Note that recongition of a CPU type as option does +89C51R, 251, C251, DS390. Note that recongition of a CPU type as option does not mean that the simulator can simulate that kind of CPU. Default type is C51. diff --git a/sim/ucsim/s51.src/Makefile.in b/sim/ucsim/s51.src/Makefile.in index 08e82b54..64e696ca 100644 --- a/sim/ucsim/s51.src/Makefile.in +++ b/sim/ucsim/s51.src/Makefile.in @@ -48,7 +48,7 @@ srcdir = @srcdir@ OBJECTS_SHARED = glob.o sim51.o \ inc.o jmp.o mov.o logic.o arith.o bit.o \ timer0.o timer1.o timer2.o serial.o port.o interrupt.o \ - uc51.o uc52.o uc51r.o uc89c51r.o uc251.o + uc51.o uc52.o uc51r.o uc89c51r.o uc251.o uc390.o OBJECTS_EXE = s51.o OBJECTS = $(OBJECTS_SHARED) $(OBJECTS_EXE) diff --git a/sim/ucsim/s51.src/glob.cc b/sim/ucsim/s51.src/glob.cc index 00cd82ff..85291926 100644 --- a/sim/ucsim/s51.src/glob.cc +++ b/sim/ucsim/s51.src/glob.cc @@ -329,6 +329,9 @@ struct name_entry sfr_tab51[]= {CPU_ALL_52|CPU_251, 0xcb, "RCAP2H"}, {CPU_ALL_52|CPU_251, 0xca, "RCAP2L"}, {CPU_251, 0x84, "DPXL"}, + {CPU_DS390, 0x84, "DPL1"}, + {CPU_DS390, 0x85, "DPH1"}, + {CPU_DS390, 0x86, "DPS"}, {CPU_89C51R|CPU_51R, 0x8e, "AUXR"}, {CPU_51R|CPU_89C51R|CPU_251, 0xa6, "WDTRST"}, {CPU_51R|CPU_89C51R|CPU_251, 0xa9, "SADDR"}, @@ -494,6 +497,7 @@ struct cpu_entry cpus_51[]= {"251" , CPU_251, CPU_CMOS}, {"C251" , CPU_251, CPU_CMOS}, + {"DS390" , CPU_DS390, CPU_CMOS}, {NULL, 0, 0} }; diff --git a/sim/ucsim/s51.src/regs51.h b/sim/ucsim/s51.src/regs51.h index fbea3a95..247ecefe 100644 --- a/sim/ucsim/s51.src/regs51.h +++ b/sim/ucsim/s51.src/regs51.h @@ -62,6 +62,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define AUXR1 0xa2 /* Secondary Aux Register */ #define DPXL 0x84 /* */ +#define DPL1 0x84 /* 2nd Data Pointer Low byte */ +#define DPH1 0x85 /* 2nd Data Pointer High byte */ +#define DPS 0x86 /* DPS 1H=DPTR is DPL1/DPH1,... */ #define WDTRST 0xa6 /* */ #define IE0 0xa8 /* */ #define SADDR 0xa9 /* */ diff --git a/sim/ucsim/s51.src/sim51.cc b/sim/ucsim/s51.src/sim51.cc index 8a7eb973..539cbba4 100644 --- a/sim/ucsim/s51.src/sim51.cc +++ b/sim/ucsim/s51.src/sim51.cc @@ -44,6 +44,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #include "uc51rcl.h" #include "uc89c51rcl.h" #include "uc251cl.h" +#include "uc390cl.h" #include "glob.h" @@ -81,6 +82,8 @@ cl_sim51::mk_controller(void) return(new t_uc89c51r(cpus_51[i].type, cpus_51[i].technology, this)); case CPU_251: return(new t_uc251(cpus_51[i].type, cpus_51[i].technology, this)); + case CPU_DS390: + return(new t_uc390(cpus_51[i].type, cpus_51[i].technology, this)); } return(NULL); } diff --git a/sim/ucsim/s51.src/uc390.cc b/sim/ucsim/s51.src/uc390.cc new file mode 100644 index 00000000..94ad439a --- /dev/null +++ b/sim/ucsim/s51.src/uc390.cc @@ -0,0 +1,305 @@ +/* + * Simulator of microcontrollers (uc390.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + * uc390.cc - module created by Karl Bongers 2001, karl@turbobit.com + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include + +#include "uc390cl.h" +#include "regs51.h" + + +/* + * Making an 390 CPU object + */ + +t_uc390::t_uc390(int Itype, int Itech, class cl_sim *asim): + t_uc52(Itype, Itech, asim) +{ +} + +/* + * 0x05 2 12 INC addr + *____________________________________________________________________________ + * + */ +int +t_uc390::inst_inc_addr(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + + /* mask off the 2Hex bit adjacent to the 1H bit which selects + which DPTR we use. This is a feature of 80C390. + You can do INC DPS and it only effects bit 1. */ + if (code == DPS) + (*addr) ^= 1; /* just toggle */ + else { + (*addr)++; + } + + proc_write(addr); + return(resGO); +} + +/* + * 0xa3 1 24 INC DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc390::inst_inc_dptr(uchar code) +{ + uint dptr; + + unsigned char pl,ph,dps; + + dps = sfr->get(DPS); + if (dps & 1) { + pl = DPL1; + ph = DPH1; + } else { + pl = DPL; + ph = DPH; + } + + if (dps & 1) { /* alternate DPTR */ + if (dps & 0x80) /* decr set */ + dptr= sfr->get(ph)*256 + sfr->get(pl) - 1; + else + dptr= sfr->get(ph)*256 + sfr->get(pl) + 1; + } else { + if (dps & 0x40) /* decr set */ + dptr= sfr->get(ph)*256 + sfr->get(pl) - 1; + else + dptr= sfr->get(ph)*256 + sfr->get(pl) + 1; + } + + sfr->set(event_at.ws= ph, (dptr >> 8) & 0xff); + sfr->set(pl, dptr & 0xff); + + if (dps & 0x20) { /* auto-switch dptr */ + sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + } + tick(1); + return(resGO); +} + +/* + * 0x73 1 24 JMP @A+DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc390::inst_jmp_$a_dptr(uchar code) +{ + unsigned char pl,ph,dps; + + dps = sfr->get(DPS); + if (dps & 1) { + pl = DPL1; + ph = DPH1; + } else { + pl = DPL; + ph = DPH; + } + + PC= (sfr->get(ph)*256 + sfr->get(pl) + + read_mem(MEM_SFR, ACC)) & + (EROM_SIZE - 1); + + tick(1); + return(resGO); +} + +/* + * 0x90 3 24 MOV DPTR,#data + *____________________________________________________________________________ + * + */ + +int +t_uc390::inst_mov_dptr_$data(uchar code) +{ + unsigned char pl,ph,dps; + + dps = sfr->get(DPS); + if (dps & 1) { + pl = DPL1; + ph = DPH1; + } else { + pl = DPL; + ph = DPH; + } + + sfr->set(event_at.ws= ph, fetch()); + sfr->set(pl, fetch()); + + if (dps & 0x20) { /* auto-switch dptr */ + sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + } + + tick(1); + return(resGO); +} + + +/* + * 0x93 1 24 MOVC A,@A+DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc390::inst_movc_a_$a_dptr(uchar code) +{ + unsigned char pl,ph,dps; + + dps = sfr->get(DPS); + if (dps & 1) { + pl = DPL1; + ph = DPH1; + } else { + pl = DPL; + ph = DPH; + } + + sfr->set(ACC, get_mem(MEM_ROM, event_at.rc= + (sfr->get(ph)*256+sfr->get(pl) + + sfr->get(ACC)) & (EROM_SIZE-1))); + +#if 0 + if (dps & 0x10) { /* auto-incr */ + unsigned char t; + t = (sfr->get(pl) + 1) & 0xff; + sfr->set(pl, t); + if (t == 0) { /* overflow */ + t = (sfr->get(ph) + 1) & 0xff; + sfr->set(ph, t); + } + } +#endif + + if (dps & 0x20) { /* auto-switch dptr */ + sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + } + + tick(1); + return(resGO); +} + +/* + * 0xe0 1 24 MOVX A,@DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc390::inst_movx_a_$dptr(uchar code) +{ + unsigned char pl,ph,dps; + + dps = sfr->get(DPS); + if (dps & 1) { + pl = DPL1; + ph = DPH1; + } else { + pl = DPL; + ph = DPH; + } + + sfr->set(event_at.ws= ACC, + get_mem(MEM_XRAM, event_at.rx=sfr->get(ph)*256+sfr->get(pl))); + +#if 0 + if (dps & 0x10) { /* auto-incr */ + unsigned char t; + t = (sfr->get(pl) + 1) & 0xff; + sfr->set(pl, t); + if (t == 0) { /* overflow */ + t = (sfr->get(ph) + 1) & 0xff; + sfr->set(ph, t); + } + } +#endif + + if (dps & 0x20) { /* auto-switch dptr */ + sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + } + tick(1); + return(resGO); +} + +/* + * 0xf0 1 24 MOVX @DPTR,A + *____________________________________________________________________________ + * + */ + +int +t_uc390::inst_movx_$dptr_a(uchar code) +{ + unsigned char pl,ph,dps; + + dps = sfr->get(DPS); + if (dps & 1) { + pl = DPL1; + ph = DPH1; + } else { + pl = DPL; + ph = DPH; + } + + set_mem(MEM_XRAM, event_at.wx= sfr->get(ph)*256+sfr->get(pl), + sfr->get(event_at.rs= ACC)); + +#if 0 + if (dps & 0x10) { /* auto-incr */ + unsigned char t; + t = (sfr->get(pl) + 1) & 0xff; + sfr->set(pl, t); + if (t == 0) { /* overflow */ + t = (sfr->get(ph) + 1) & 0xff; + sfr->set(ph, t); + } + } +#endif + + if (dps & 0x20) { /* auto-switch dptr */ + sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + } + tick(1); + return(resGO); +} + + + +/* End of s51.src/uc390.cc */ diff --git a/sim/ucsim/s51.src/uc390cl.h b/sim/ucsim/s51.src/uc390cl.h new file mode 100644 index 00000000..c57804de --- /dev/null +++ b/sim/ucsim/s51.src/uc390cl.h @@ -0,0 +1,55 @@ +/* + * Simulator of microcontrollers (uc390cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + * uc390cl.h - implemented by Karl Bongers, karl@turbobit.com + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef UC390CL_HEADER +#define UC390CL_HEADER + +#include "ddconfig.h" + +#include "uc52cl.h" + + +class t_uc390: public t_uc52 +{ +public: + t_uc390(int Itype, int Itech, class cl_sim *asim); + +virtual int inst_inc_addr(uchar code); +virtual int inst_inc_dptr(uchar code); +virtual int inst_jmp_$a_dptr(uchar code); +virtual int inst_mov_dptr_$data(uchar code); +virtual int inst_movc_a_$a_dptr(uchar code); +virtual int inst_movx_a_$dptr(uchar code); +virtual int inst_movx_$dptr_a(uchar code); + +}; + + +#endif + +/* End of s51.src/uc390cl.h */ diff --git a/sim/ucsim/stypes.h b/sim/ucsim/stypes.h index 81a50689..f3ee52b0 100644 --- a/sim/ucsim/stypes.h +++ b/sim/ucsim/stypes.h @@ -75,8 +75,9 @@ struct cpu_entry #define CPU_51R 0x0010 #define CPU_89C51R 0x0020 #define CPU_251 0x0040 +#define CPU_DS390 0x0080 #define CPU_ALL_51 (CPU_51|CPU_31) -#define CPU_ALL_52 (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251) +#define CPU_ALL_52 (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251|CPU_DS390) #define CPU_AVR 0x0001 #define CPU_ALL_AVR (CPU_AVR) -- 2.30.2