From 7b340d1916ee8ff306b1d0fa1c3a0921cec831dd Mon Sep 17 00:00:00 2001 From: bela Date: Thu, 19 Sep 2002 10:08:22 +0000 Subject: [PATCH] Philips P89C668 support added by Eric Limpers git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@2103 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- device/include/mcs51reg.h | 450 +++++++++++++++++++++++++++++++------- 1 file changed, 367 insertions(+), 83 deletions(-) diff --git a/device/include/mcs51reg.h b/device/include/mcs51reg.h index f5092e26..56a457e4 100644 --- a/device/include/mcs51reg.h +++ b/device/include/mcs51reg.h @@ -73,6 +73,9 @@ Version 1.0.9 (Sept 9, 2002) Register declarations for the Atmel T89C51RD2 added by Johannes Hoelzl / johannes.hoelzl@gmx.de + Version 1.0.10 (Sept 19, 2002) + Register declarations for the Philips P89C668 added by Eric Limpens / Eric@limpens.net + Adding support for additional microcontrollers: ----------------------------------------------- @@ -90,8 +93,12 @@ c. Define interrupt vectors - 4. Send me the file mcs51reg_update.h ( bela.torok@kssg.ch ). - I'm going to verify/merge new definitions to this file. + 4. Compile a program for the microcontroller using the Preprocessor only, e.g.:, + sdcc -E test.c > t.txt + and check definitions for validity in the t.txt file. + + 5. If everithing seems to be OK send me the mcs51reg_update.h file. --> bela.torok@kssg.ch + I'm going to resolve conflicts & verify/merge new definitions to this file. Microcontroller support: @@ -126,6 +133,7 @@ MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers MICROCONTROLLER_P80C552 Philips P80C552 + MICROCONTROLLER_P89C668 Philips P89C668 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517 @@ -152,7 +160,7 @@ /////////////////////////////////////////////////////// /// Insert header here (for developers only) /// /// remove "//" from the begining of the next line /// -/// #include "mcs51reg_update.h" /// +//#include "mcs51reg_update.h" /// /////////////////////////////////////////////////////// ////////////////////////////////// @@ -907,6 +915,86 @@ // end of definitions for the Philips P80C552 microcontroller +// definitions for the Philips P89C668 +#ifdef MICROCONTROLLER_P89C668 +#ifdef MICROCONTROLLER_DEFINED +#define MCS51REG_ERROR +#endif +#ifndef MICROCONTROLLER_DEFINED +#define MICROCONTROLLER_DEFINED +#endif +#ifdef MCS51REG_ENABLE_WARNINGS +#warning Selected HW: P89C668 +#endif +#define P0 +#define P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0 +#define P1 +#define P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 +#define P2 +#define P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8 +#define P3 +#define P3_EXT__x__x__CEX4__CEX3__x__x__x__x +#define SP +#define DPL +#define DPH +#define TCON +#define TMOD +#define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL +#define TL0 +#define TL1 +#define TH0 +#define TH1 +#define SCON +#define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI +#define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0 +#define SBUF +#define S0BUF SBUF +#define PSW +#define ACC +#define B +#define SADR_AT_0XA9 +#define SADEN_AT_0XB9 +#define S1IST_AT_0XDC +#define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x +#define S1DAT_AT_0XDA +#define S1ADR__x__x__x__x__x__x__x__GC +#define SBUF +#define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2 +#define T2MOD__x__x__x__x__x__x__T2OE__DCEN +#define RCAP2L +#define RCAP2H +#define TL2 +#define TH2 +#define IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0 +#define IEN1__x__x__x__x__x__x__x__ET2 +#define IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0 +#define IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H +#define CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 +#define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +#define AUXR__x__x__x__x__x__x__EXTRAM__A0 +#define AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS +#define WDTRST_AT_0XA6 +#define CCAPM0_AT_0XC2 +#define CCAPM1_AT_0XC3 +#define CCAPM2_AT_0XC4 +#define CCAPM3_AT_0XC5 +#define CCAPM4_AT_0XC6 +#define CCAP0L_AT_0XEA +#define CCAP1L_AT_0XEB +#define CCAP2L_AT_0XEC +#define CCAP3L_AT_0XED +#define CCAP4L_AT_0XEE +#define CH_AT_0XF9 +#define CL_AT_0XE9 +#define CCAP0H_AT_0XFA +#define CCAP1H_AT_0XFB +#define CCAP2H_AT_0XFC +#define CCAP3H_AT_0XFD +#define CCAP4H_AT_0XFE +#endif +// end of definitions for the Philiüs P89C668 + + // definitions for the Infineon / Siemens SAB80515 & SAB80535 #ifdef MICROCONTROLLER_SAB80515 #ifdef MICROCONTROLLER_DEFINED @@ -1185,34 +1273,34 @@ #define P5_AT_0XE8 #define SADEN0 -#define AUXR1 -#define WDTRST -#define WDTPRG -#define AUXR -#define IPH +#define AUXR1__x__x__x__x__GF3__x__x__DPS +#define WDTRST_AT_0XA6 +#define WDTPRG_AT_0XA7 +#define AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0 +#define IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H #define FCON #define EECON #define EETIM #define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x -#define CCON -#define CMOD -#define CCAPM0 -#define CCAPM1 -#define CCAPM2 -#define CCAPM3 -#define CCAPM4 -#define CL -#define CCAP0L -#define CCAP1L -#define CCAP2L -#define CCAP3L -#define CCAP4L -#define CH -#define CCAP0H -#define CCAP1H -#define CCAP2H -#define CCAP3H -#define CCAP4H +#define CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0 +#define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +#define CCAPM0_AT_0XDA +#define CCAPM1_AT_0XDB +#define CCAPM2_AT_0XDC +#define CCAPM3_AT_0XDD +#define CCAPM4_AT_0XDE +#define CL_AT_0XE9 +#define CCAP0L_AT_0XEA +#define CCAP1L_AT_0XEB +#define CCAP2L_AT_0XEC +#define CCAP3L_AT_0XED +#define CCAP4L_AT_0XEE +#define CH_AT_0XF9 +#define CCAP0H_AT_0XFA +#define CCAP1H_AT_0XFB +#define CCAP2H_AT_0XFC +#define CCAP3H_AT_0XFD +#define CCAP4H_AT_0XFE #endif /* MICROCONTROLLER_T89C51RD2 */ /* end of definition for the Atmel T89C51RD2 */ @@ -1405,8 +1493,17 @@ sfr at 0xEF ARCON ; // arithmetic control register SAB80517 sfr at 0x9C AP ; // DS80C390 #endif -#ifdef AUXR -#undef AUXR +#ifdef AUXR__x__x__x__x__x__x__EXTRAM__A0 +#undef AUXR__x__x__x__x__x__x__EXTRAM__A0 +// P89C668 specific, Auxilary +sfr at 0x8E AUXR ; +// not bit addressable: +#define EXTRAM 0x02 +#define A0 0x01 +#endif + +#ifdef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0 +#undef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0 sfr at 0x8E AUXR; #define AO 0x01 #define EXTRAM 0x02 @@ -1428,13 +1525,23 @@ sbit at 0xF6 BREG_F6 ; sbit at 0xF7 BREG_F7 ; #endif -#ifdef AUXR1 -#undef AUXR1 +#ifdef AUXR1__x__x__x__x__GF3__x__x__DPS +#undef AUXR1__x__x__x__x__GF3__x__x__DPS sfr at 0xA2 AUXR1; #define DPS 0x01 #define GF3 0x08 #endif +#ifdef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS +#undef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS +// P89C668 specific, Auxilary 1 +sfr at 0xA2 AUXR1 ; +#define ENBOOT 0x20 +#define GF2 0x08 +#define ALWAYS_ZERO 0x04 +#define DPS 0x01 +#endif + #ifdef BP2 #undef BP2 sfr at 0xC3 BP2 ; @@ -1755,59 +1862,65 @@ sfr at 0xDF C1TMA1 ; // DS80C390 specific sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific #endif -#ifdef CCAP0H -#undef CCAP0H +#ifdef CCAP0H_AT_0XFA +#undef CCAP0H_AT_0XFA sfr at 0xFA CCAP0H; #endif -#ifdef CCAP1H -#undef CCAP1H +#ifdef CCAP1H_AT_0XFB +#undef CCAP1H_AT_0XFB sfr at 0xFB CCAP1H; #endif -#ifdef CCAP2H -#undef CCAP2H +#ifdef CCAP2H_AT_0XFC +#undef CCAP2H_AT_0XFC sfr at 0xFC CCAP2H; #endif -#ifdef CCAP3H -#undef CCAP3H +#ifdef CCAP3H_AT_0XFD +#undef CCAP3H_AT_0XFD sfr at 0xFD CCAP3H; #endif -#ifdef CCAP4H -#undef CCAP4H +#ifdef CCAP4H_AT_0XFE +#undef CCAP4H_AT_0XFE sfr at 0xFE CCAP4H; #endif -#ifdef CCAP0L -#undef CCAP0L +#ifdef CCAP0L_AT_0XEA +#undef CCAP0L_AT_0XEA sfr at 0xEA CCAP0L; #endif -#ifdef CCAP1L -#undef CCAP1L +#ifdef CCAP1L_AT_0XEB +#undef CCAP1L_AT_0XEB sfr at 0xEB CCAP1L; #endif -#ifdef CCAP2L -#undef CCAP2L +#ifdef CCAP2L_AT_0XEC +#undef CCAP2L_AT_0XEC sfr at 0xEC CCAP2L; #endif -#ifdef CCAP3L -#undef CCAP3L +#ifdef CCAP3L_AT_0XED +#undef CCAP3L_AT_0XED sfr at 0xED CCAP3L; #endif -#ifdef CCAP4L -#undef CCAP4L +#ifdef CCAP4L_AT_0XEE +#undef CCAP4L_AT_0XEE sfr at 0xEE CCAP4L; #endif -#ifdef CCAPM0 -#undef CCAPM0 -sfr at 0x0DA CCAPM0; +#ifdef CCAPM0_AT_0XC2 +#undef CCAPM0_AT_0XC2 +// P89C668 specific, Capture module: +sfr at 0xC2 CCAPM0 ; +#endif + +#ifdef CCAPM0_AT_0XDA +#undef CCAPM0_AT_0XDA +sfr at 0xDA CCAPM0; #define ECCF 0x01 #define PWM 0x02 #define TOG 0x04 @@ -1817,26 +1930,46 @@ sfr at 0x0DA CCAPM0; #define ECOM 0x40 #endif -#ifdef CCAPM1 -#undef CCAPM1 -sfr at 0x0DB CCAPM1; +#ifdef CCAPM1_AT_0XC3 +#undef CCAPM1_AT_0XC3 +sfr at 0xC3 CCAPM1 ; +#endif + +#ifdef CCAPM1_AT_0XDB +#undef CCAPM1_AT_0XDB +sfr at 0xDB CCAPM1; +#endif + +#ifdef CCAPM2_AT_0XC4 +#undef CCAPM2_AT_0XC4 +sfr at 0xC4 CCAPM2 ; #endif -#ifdef CCAPM2 -#undef CCAPM2 +#ifdef CCAPM2_AT_0XDC +#undef CCAPM2_AT_0XDC sfr at 0x0DC CCAPM2; #endif -#ifdef CCAPM3 -#undef CCAPM3 +#ifdef CCAPM3_AT_0XC5 +#undef CCAPM3_AT_0XC5 +sfr at 0xC5 CCAPM3 ; +#endif + +#ifdef CCAPM3_AT_0XDD +#undef CCAPM3_AT_0XDD sfr at 0x0DD CCAPM3; #endif -#ifdef CCAPM4 -#undef CCAPM4 +#ifdef CCAPM4_AT_0XDE +#undef CCAPM4_AT_0XDE sfr at 0x0DE CCAPM4; #endif +#ifdef CCAPM4_AT_0XC6 +#undef CCAPM4_AT_0XC6 +sfr at 0xC6 CCAPM4 ; +#endif + #ifdef CCEN #undef CCEN sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific @@ -1882,8 +2015,8 @@ sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 speci sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific #endif -#ifdef CCON -#undef CCON +#ifdef CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0 +#undef CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0 sfr at 0xD8 CCON; // T89C51RD2 specific register // Bit registers sbit at 0xD8 CCF0; @@ -1895,11 +2028,38 @@ sbit at 0xDD CR; sbit at 0xDE CF; #endif -#ifdef CH -#undef CH +#ifdef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 +#undef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0 +// P89C668 specific, PCA Counter control: +sfr at 0xC0 CCON ; +// Bit registers +sbit at 0xC0 CCF0 ; +sbit at 0xC1 CCF1 ; +sbit at 0xC2 CCF2 ; +sbit at 0xC3 CCF3 ; +sbit at 0xC4 CCF4 ; +//sbit at 0xC5 - +sbit at 0xC6 CR ; +sbit at 0xC7 CF ; +#endif + +#ifdef CH_AT_0XF9 +#undef CH_AT_0XF9 sfr at 0xF9 CH; #endif +#ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +#undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +// P89C668 specific, PCA Counter mode: +sfr at 0xC1 CMOD ; +// not bit addressable: +#define CIDL 0x80 +#define WDTE 0x40 +#define CPS1 0x04 +#define CPS0 0x02 +#define ECF 0x01 +#endif + #ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 #undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific @@ -1935,8 +2095,8 @@ sfr at 0x96 CKMOD ; // DS89C420 specific #define T2MH 0x20 #endif -#ifdef CL -#undef CL +#ifdef CL_AT_0XE9 +#undef CL_AT_0XE9 sfr at 0xE9 CL; #endif @@ -2055,8 +2215,8 @@ sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific #endif -#ifdef CMOD -#undef CMOD +#ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF +#undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF sfr at 0xD9 CMOD; #define ECF 0x01 #define CPS0 0x02 @@ -2513,6 +2673,29 @@ sbit at 0xAF EA ; sbit at 0xAF EAL ; // EA as called by Infineon / Siemens #endif +#ifdef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0 +#undef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0 +// P89C668 specific +sfr at 0xA8 IEN0 ; +// Bit registers +sbit at 0xA8 EX0 ; +sbit at 0xA9 ET0 ; +sbit at 0xAA EX1 ; +sbit at 0xAB ET1 ; +sbit at 0xAC ES0 ; +sbit at 0xAD ES1 ; +sbit at 0xAE EC ; +sbit at 0xAF EA ; +#endif + +#ifdef IEN1__x__x__x__x__x__x__x__ET2 +#undef IEN1__x__x__x__x__x__x__x__ET2 +// P89C668 specific bit registers +sfr at 0xE8 IEN1 ; +// Bit registers +sbit at 0xE8 ET2 ; +#endif + #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0 sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific @@ -2610,6 +2793,21 @@ sbit at 0xBD PT2 ; sbit at 0xBE PS1 ; #endif +#ifdef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0 +#undef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0 +// P89C668 specific: +sfr at 0xB8 IP ; +// Bit registers +sbit at 0xB8 PX0 ; +sbit at 0xB9 PT0 ; +sbit at 0xBA PX1 ; +sbit at 0xBB PT1 ; +sbit at 0xBC PS0 ; +sbit at 0xBD PS1 ; +sbit at 0xBE PPC ; +sbit at 0xBF PT2 ; +#endif + #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0 sfr at 0xB8 IP ; @@ -2687,8 +2885,8 @@ sbit at 0xFE PCM2 ; sbit at 0xFF PT2 ; #endif -#ifdef IPH -#undef IPH +#ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H +#undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H sfr at 0xB7 IPH; #define PX0H 0x01 #define PT0H 0x02 @@ -2699,6 +2897,21 @@ sfr at 0xB7 IPH; #define PPCH 0x40 #endif +#ifdef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H +#undef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H +// P89C668 specific: +sfr at 0xB7 IPH ; +// not bit addressable: +#define PX0H 0x01 +#define PT0H 0x02 +#define PX1H 0x04 +#define PT1H 0x08 +#define PS0H 0x10 +#define PS1H 0x20 +#define PPCH 0x40 +#define PT2H 0x80 +#endif + #ifdef IRCON #undef IRCON sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific @@ -2855,6 +3068,19 @@ sbit at 0x86 P0_6 ; sbit at 0x87 P0_7 ; #endif +#ifdef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0 +#undef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0 +// P89C668 alternate names for bits in P0 +sbit at 0x80 AD0 ; +sbit at 0x81 AD1 ; +sbit at 0x82 AD2 ; +sbit at 0x83 AD3 ; +sbit at 0x84 AD4 ; +sbit at 0x85 AD5 ; +sbit at 0x86 AD6 ; +sbit at 0x87 AD7 ; +#endif + #ifdef P1 #undef P1 sfr at 0x90 P1 ; @@ -2882,6 +3108,20 @@ sbit at 0x96 INT4 ; sbit at 0x97 INT5 ; #endif +#ifdef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 +#undef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 +// P89C669 alternate names for bits at P1 +// P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2 +sbit at 0x90 T2 ; +sbit at 0x91 T2EX ; +sbit at 0x92 ECI ; +sbit at 0x93 CEX0 ; +sbit at 0x94 CEX1 ; +sbit at 0x95 CEX2 ; +sbit at 0x96 SCL ; +sbit at 0x97 SDA ; +#endif + #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific sbit at 0x91 INT4_CC1 ; @@ -2927,6 +3167,19 @@ sbit at 0xA6 P2_6 ; sbit at 0xA7 P2_7 ; #endif +#ifdef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8 +#undef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8 +// P89C668 specific bit registers at P2: +sbit at 0xA0 AD8 ; +sbit at 0xA1 AD9 ; +sbit at 0xA2 AD10 ; +sbit at 0xA3 AD11 ; +sbit at 0xA4 AD12 ; +sbit at 0xA5 AD13 ; +sbit at 0xA6 AD14 ; +sbit at 0xA7 AD15 ; +#endif + #ifdef P3 #undef P3 sfr at 0xB0 P3 ; @@ -2956,6 +3209,13 @@ sbit at 0xB7 RD ; #endif #endif +#ifdef P3_EXT__x__x__CEX4__CEX3__x__x__x__x +#undef P3_EXT__x__x__CEX4__CEX3__x__x__x__x +// P89C668 specific bit registers at P3 (alternate names) +sbit at 0xB5 CEX4 ; +sbit at 0xB4 CEX3 ; +#endif + #ifdef P4_AT_0X80 #undef P4_AT_0X80 sfr at 0x80 P4 ; // Port 4 - DS80C390 @@ -3438,6 +3698,12 @@ sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific sfr at 0xDA SIDAT ; // sometimes called SIDAT #endif +#ifdef S1IST_AT_0XDC +#undef S1IST_AT_0XDC +// P89C668 specific +sfr at 0xDC S1IST ; +#endif + #ifdef S1RELL #undef S1RELL sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific @@ -3459,6 +3725,11 @@ sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific #define SC4 0x80 #endif +#ifdef SADR_AT_0XA9 +#undef SADR_AT_0XA9 +sfr at 0xA9 SADDR ; +#endif + #ifdef SADDR0 #undef SADDR0 // DS80C320 specific @@ -3471,6 +3742,11 @@ sfr at 0xA9 SADDR0 ; sfr at 0xAA SADDR1 ; #endif +#ifdef SADEN_AT_0XB9 +#undef SADEN_AT_0XB9 +sfr at 0xB9 SADEN ; +#endif + #ifdef SADEN0 #undef SADEN0 // DS80C320 & DS80C390 specific @@ -3902,12 +4178,12 @@ sbit at 0xDE POR ; sbit at 0xDF SMOD_1 ; #endif -#ifdef WDTPRG -#undef WDTPRG -sfr at 0xA7 WDRPRG; -#define WDRPRG_S0 0x01 -#define WDRPRG_S1 0x02 -#define WDRPRG_S2 0x04 +#ifdef WDTPRG_AT_0XA7 +#undef WDTPRG_AT_0XA7 +sfr at 0xA7 WDTPRG; +#define WDTRPRG_S0 0x01 +#define WDTRPRG_S1 0x02 +#define WDTRPRG_S2 0x04 #endif #ifdef WDTREL @@ -3915,9 +4191,9 @@ sfr at 0xA7 WDRPRG; sfr at 0x86 WDTREL ; // Watchdof Timer reload register #endif -#ifdef WDTRST -#undef WDTRST -sfr at 0xA6 WDRRST; +#ifdef WDTRST_AT_0XA6 +#undef WDTRST_AT_0XA6 +sfr at 0xA6 WDTRST; #endif #ifdef XPAGE @@ -3994,6 +4270,12 @@ sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infi #define TF2_VECTOR 14 // 0x73 T2 overflow #endif +#ifdef MICROCONTROLLER_P89C668 +#define SIO1_VECTOR 5 // 0x2b SIO1 (i2c) +#define PCA_VECTOR 6 // 0x33 (Programmable Counter Array) +#define TF2_VECTOR 7 // 0x3B (Timer 2) +#endif + #ifdef MICROCONTROLLER_SAB80515 #define TF2_VECTOR 5 // 0x2B timer 2 #define EX2_VECTOR 5 // 0x2B external interrupt 2 @@ -4035,9 +4317,11 @@ sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infi #ifdef MICROCONTORLLER_T89C51RD2 #define TF2_VECTOR 5 /* 0x2B timer 2 */ -#define PCA_VECTOR 6 /* 0x33 Programmable Counetr Array interrupt */ +#define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */ #endif /* MICROCONTORLLER_T89C51RD2 */ #endif // End of the header -> #ifndef MCS51REG_H + + -- 2.30.2