From 69682ac49f545217f3070e0ac25b0da92cda1c2c Mon Sep 17 00:00:00 2001 From: jcorgan Date: Sun, 26 Oct 2008 16:05:03 +0000 Subject: [PATCH] Merged r9834:9855 from jcorgan/u2-wip into trunk. Catches up gr-usrp2 with the latest changes in libusrp2, adding all the daughterboard accessor functions. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9856 221aa14e-8319-0410-a670-987f0aec2ac5 --- gr-usrp2/src/usrp2.i | 121 ++++++++++++++++++++++++++++++ gr-usrp2/src/usrp2_base.cc | 6 ++ gr-usrp2/src/usrp2_base.h | 5 ++ gr-usrp2/src/usrp2_sink_base.cc | 54 +++++++++++++ gr-usrp2/src/usrp2_sink_base.h | 50 ++++++++++++ gr-usrp2/src/usrp2_source_base.cc | 66 ++++++++++++++++ gr-usrp2/src/usrp2_source_base.h | 60 +++++++++++++++ usrp2/host/include/usrp2/usrp2.h | 1 - 8 files changed, 362 insertions(+), 1 deletion(-) diff --git a/gr-usrp2/src/usrp2.i b/gr-usrp2/src/usrp2.i index 9f82c4cd..7c75287c 100644 --- a/gr-usrp2/src/usrp2.i +++ b/gr-usrp2/src/usrp2.i @@ -46,6 +46,8 @@ public: ~usrp2_base(); std::string mac_addr() const; + %rename(_real_fpga_master_clock_freq) fpga_master_clock_freq; + bool fpga_master_clock_freq(long *freq); }; // ---------------------------------------------------------------- @@ -62,6 +64,19 @@ public: %rename(_real_set_center_freq) set_center_freq; bool set_center_freq(double frequency, usrp2::tune_result *r); bool set_decim(int decimation_factor); + bool set_scale_iq(int scale_i, int scale_q); + int decim(); + %rename(_real_adc_rate) adc_rate; + bool adc_rate(long *rate); + double gain_min(); + double gain_max(); + double gain_db_per_step(); + double freq_min(); + double freq_max(); + %rename(_real_daughterboard_id) daughterboard_id; + bool daughterboard_id(int *dbid); + unsigned int overruns(); + unsigned int missing(); }; // ---------------------------------------------------------------- @@ -114,6 +129,17 @@ public: %rename(_real_set_center_freq) set_center_freq; bool set_center_freq(double frequency, usrp2::tune_result *r); bool set_interp(int interp_factor); + bool set_scale_iq(int scale_i, int scale_q); + int interp(); + %rename(_real_dac_rate) dac_rate; + bool dac_rate(long *rate); + double gain_min(); + double gain_max(); + double gain_db_per_step(); + double freq_min(); + double freq_max(); + %rename(_real_daughterboard_id) daughterboard_id; + bool daughterboard_id(int *dbid); }; // ---------------------------------------------------------------- @@ -154,6 +180,23 @@ public: // ---------------------------------------------------------------- +// some utility functions to allow Python to deal with pointers +%{ + long *make_long_ptr() { return (long *)malloc(sizeof(long)); } + long deref_long_ptr(long *l) { return *l; } + void free_long_ptr(long *l) { free(l); } + int *make_int_ptr() { return (int *)malloc(sizeof(int)); } + int deref_int_ptr(int *l) { return *l; } + void free_int_ptr(int *l) { free(l); } +%} + +long *make_long_ptr(); +long deref_long_ptr(long *l); +void free_long_ptr(long *l); +int *make_int_ptr(); +int deref_int_ptr(int *l); +void free_int_ptr(int *l); + // create a more pythonic interface %pythoncode %{ @@ -165,8 +208,86 @@ def __set_center_freq(self, freq): else: return None +def __fpga_master_clock_freq(self): + f = make_long_ptr(); + r = self._real_fpga_master_clock_freq(f) + if r: + result = deref_long_ptr(f) + else: + result = None + free_long_ptr(f) + return result + +def __adc_rate(self): + rate = make_long_ptr(); + r = self._real_adc_rate(rate) + if r: + result = deref_long_ptr(rate) + else: + result = None + free_long_ptr(rate) + return result + +def __dac_rate(self): + rate = make_long_ptr(); + r = self._real_dac_rate(rate) + if r: + result = deref_long_ptr(rate) + else: + result = None + free_long_ptr(rate) + return result + +def __gain_range(self): + return [self.gain_min(), + self.gain_max(), + self.gain_db_per_step()] + +# NOTE: USRP1 uses a length three tuple here (3rd value is 'freq step'), +# but it's not really useful. We let an index error happen here +# to identify code using it. +def __freq_range(self): + return [self.freq_min(), + self.freq_max()] + +def __daughterboard_id(self): + dbid = make_int_ptr(); + r = self._real_daughterboard_id(dbid) + if r: + result = deref_int_ptr(dbid) + else: + result = None + free_int_ptr(dbid) + return result + usrp2_source_32fc_sptr.set_center_freq = __set_center_freq usrp2_source_16sc_sptr.set_center_freq = __set_center_freq usrp2_sink_32fc_sptr.set_center_freq = __set_center_freq usrp2_sink_16sc_sptr.set_center_freq = __set_center_freq + +usrp2_source_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq +usrp2_source_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq +usrp2_sink_32fc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq +usrp2_sink_16sc_sptr.fpga_master_clock_freq = __fpga_master_clock_freq + +usrp2_source_32fc_sptr.adc_rate = __adc_rate +usrp2_source_16sc_sptr.adc_rate = __adc_rate +usrp2_sink_32fc_sptr.dac_rate = __dac_rate +usrp2_sink_16sc_sptr.dac_rate = __dac_rate + +usrp2_source_32fc_sptr.gain_range = __gain_range +usrp2_source_16sc_sptr.gain_range = __gain_range +usrp2_sink_32fc_sptr.gain_range = __gain_range +usrp2_sink_16sc_sptr.gain_range = __gain_range + +usrp2_source_32fc_sptr.freq_range = __freq_range +usrp2_source_16sc_sptr.freq_range = __freq_range +usrp2_sink_32fc_sptr.freq_range = __freq_range +usrp2_sink_16sc_sptr.freq_range = __freq_range + +usrp2_source_32fc_sptr.daughterboard_id = __daughterboard_id +usrp2_source_16sc_sptr.daughterboard_id = __daughterboard_id +usrp2_sink_32fc_sptr.daughterboard_id = __daughterboard_id +usrp2_sink_16sc_sptr.daughterboard_id = __daughterboard_id + %} diff --git a/gr-usrp2/src/usrp2_base.cc b/gr-usrp2/src/usrp2_base.cc index 4103862c..0bd97304 100644 --- a/gr-usrp2/src/usrp2_base.cc +++ b/gr-usrp2/src/usrp2_base.cc @@ -55,6 +55,12 @@ usrp2_base::mac_addr() const return d_u2->mac_addr(); } +bool +usrp2_base::fpga_master_clock_freq(long *freq) const +{ + return d_u2->fpga_master_clock_freq(freq); +} + bool usrp2_base::start() { diff --git a/gr-usrp2/src/usrp2_base.h b/gr-usrp2/src/usrp2_base.h index ad99b4ed..ae08283b 100644 --- a/gr-usrp2/src/usrp2_base.h +++ b/gr-usrp2/src/usrp2_base.h @@ -53,6 +53,11 @@ public: */ std::string mac_addr() const; + /*! + * \brief Get USRP2 master clock rate + */ + bool fpga_master_clock_freq(long *freq) const; + /*! * \brief Called by scheduler when starting flowgraph */ diff --git a/gr-usrp2/src/usrp2_sink_base.cc b/gr-usrp2/src/usrp2_sink_base.cc index 0034dd4e..c04914ee 100644 --- a/gr-usrp2/src/usrp2_sink_base.cc +++ b/gr-usrp2/src/usrp2_sink_base.cc @@ -63,3 +63,57 @@ usrp2_sink_base::set_interp(int interp_factor) { return d_u2->set_tx_interp(interp_factor); } + +bool +usrp2_sink_base::set_scale_iq(int scale_i, int scale_q) +{ + return d_u2->set_tx_scale_iq(scale_i, scale_q); +} + +int +usrp2_sink_base::interp() +{ + return d_u2->tx_interp(); +} + +bool +usrp2_sink_base::dac_rate(long *rate) +{ + return d_u2->dac_rate(rate); +} + +double +usrp2_sink_base::gain_min() +{ + return d_u2->tx_gain_min(); +} + +double +usrp2_sink_base::gain_max() +{ + return d_u2->tx_gain_max(); +} + +double +usrp2_sink_base::gain_db_per_step() +{ + return d_u2->tx_gain_db_per_step(); +} + +double +usrp2_sink_base::freq_min() +{ + return d_u2->tx_freq_min(); +} + +double +usrp2_sink_base::freq_max() +{ + return d_u2->tx_freq_max(); +} + +bool +usrp2_sink_base::daughterboard_id(int *dbid) +{ + return d_u2->tx_daughterboard_id(dbid); +} diff --git a/gr-usrp2/src/usrp2_sink_base.h b/gr-usrp2/src/usrp2_sink_base.h index 8396c08f..0c4fe72c 100644 --- a/gr-usrp2/src/usrp2_sink_base.h +++ b/gr-usrp2/src/usrp2_sink_base.h @@ -54,6 +54,56 @@ public: * \brief Set transmit interpolation rate */ bool set_interp(int interp_factor); + + /*! + * \brief Set transmit IQ scale factors + */ + bool set_scale_iq(int scale_i, int scale_q); + + /*! + * \brief Get transmit interpolation rate + */ + int interp(); + + /*! + * \brief Get DAC sample rate in Hz + */ + bool dac_rate(long *rate); + + /*! + * \brief Returns minimum Tx gain + */ + double gain_min(); + + /*! + * \brief Returns maximum Tx gain + */ + double gain_max(); + + /*! + * \brief Returns Tx gain db_per_step + */ + double gain_db_per_step(); + + /*! + * \brief Returns minimum Tx center frequency + */ + double freq_min(); + + /*! + * \brief Returns maximum Tx center frequency + */ + double freq_max(); + + /*! + * \brief Get Tx daughterboard ID + * + * \param[out] dbid returns the daughterboard id. + * + * daughterboard id >= 0 if successful, -1 if no daugherboard installed, + * -2 if invalid EEPROM on daughterboard. + */ + bool daughterboard_id(int *dbid); }; #endif /* INCLUDED_USRP2_SINK_BASE_H */ diff --git a/gr-usrp2/src/usrp2_source_base.cc b/gr-usrp2/src/usrp2_source_base.cc index 0f174bf2..1ed4d55d 100644 --- a/gr-usrp2/src/usrp2_source_base.cc +++ b/gr-usrp2/src/usrp2_source_base.cc @@ -64,6 +64,72 @@ usrp2_source_base::set_decim(int decimation_factor) return d_u2->set_rx_decim(decimation_factor); } +bool +usrp2_source_base::set_scale_iq(int scale_i, int scale_q) +{ + return d_u2->set_rx_scale_iq(scale_i, scale_q); +} + +int +usrp2_source_base::decim() +{ + return d_u2->rx_decim(); +} + +bool +usrp2_source_base::adc_rate(long *rate) +{ + return d_u2->adc_rate(rate); +} + +double +usrp2_source_base::gain_min() +{ + return d_u2->rx_gain_min(); +} + +double +usrp2_source_base::gain_max() +{ + return d_u2->rx_gain_max(); +} + +double +usrp2_source_base::gain_db_per_step() +{ + return d_u2->rx_gain_db_per_step(); +} + +double +usrp2_source_base::freq_min() +{ + return d_u2->rx_freq_min(); +} + +double +usrp2_source_base::freq_max() +{ + return d_u2->rx_freq_max(); +} + +bool +usrp2_source_base::daughterboard_id(int *dbid) +{ + return d_u2->rx_daughterboard_id(dbid); +} + +unsigned int +usrp2_source_base::overruns() +{ + return d_u2->rx_overruns(); +} + +unsigned int +usrp2_source_base::missing() +{ + return d_u2->rx_missing(); +} + bool usrp2_source_base::start() { diff --git a/gr-usrp2/src/usrp2_source_base.h b/gr-usrp2/src/usrp2_source_base.h index f6bf1005..998a022d 100644 --- a/gr-usrp2/src/usrp2_source_base.h +++ b/gr-usrp2/src/usrp2_source_base.h @@ -55,6 +55,66 @@ public: */ bool set_decim(int decimation_factor); + /*! + * \brief Set receive IQ scale factors + */ + bool set_scale_iq(int scale_i, int scale_q); + + /*! + * \brief Get receive decimation rate + */ + int decim(); + + /*! + * \brief Get the ADC sample rate + */ + bool adc_rate(long *rate); + + /*! + * \brief Returns minimum Rx gain + */ + double gain_min(); + + /*! + * \brief Returns maximum Rx gain + */ + double gain_max(); + + /*! + * \brief Returns Rx gain db_per_step + */ + double gain_db_per_step(); + + /*! + * \brief Returns minimum Rx center frequency + */ + double freq_min(); + + /*! + * \brief Returns maximum Rx center frequency + */ + double freq_max(); + + /*! + * \brief Get Rx daughterboard ID + * + * \param[out] dbid returns the daughterboard id. + * + * daughterboard id >= 0 if successful, -1 if no daugherboard installed, + * -2 if invalid EEPROM on daughterboard. + */ + bool daughterboard_id(int *dbid); + + /*! + * \brief Returns number of receiver overruns + */ + unsigned int overruns(); + + /*! + * \brief Returns number of missing sequence numbers + */ + unsigned int missing(); + /*! * \brief Called by scheduler when starting flowgraph */ diff --git a/usrp2/host/include/usrp2/usrp2.h b/usrp2/host/include/usrp2/usrp2.h index 9fc16879..83e14cd3 100644 --- a/usrp2/host/include/usrp2/usrp2.h +++ b/usrp2/host/include/usrp2/usrp2.h @@ -23,7 +23,6 @@ #include #include #include -//#include #include #include -- 2.30.2