From 52df981797010227196dd29cd77831d01e1825a8 Mon Sep 17 00:00:00 2001 From: tecodev Date: Thu, 6 Apr 2006 19:56:14 +0000 Subject: [PATCH] * .version: bumped version to 2.5.6 (pic14 ABI changed) * src/SDCCmain.c: add -DSDCC_PROCESSOR= for pic14 port * src/pic/glue.c (emitSymbolToFile,pic14_constructAbsMap, pic14emitRegularMap,pic14emitMaps): moved output for absolute symbols to pic14_constructAbsMap (pic14printPublics): declare absolute global symbols as global (pic14createInterruptVect), * src/pic/ralloc.c (IS_CONFIG_ADDRESS): support second config word, (newReg): assume new registers unused, use correct name in hashtable (reg->name instead of name), more debugLog output * src/pic/device.h (PIC_device): added fields for verbose output * src/pic/device.c: moved device definition to pic14devices.txt, added routines for runtime parsing of pic14devices.txt, added support for second config word * src/pic/main.c (_process_pragma): removed #pragma maxram, (_pic14_keywords): no longer accept "bit" and "sbit" keywords (_pic14_initPaths): add search paths with "pic" suffix (not "pic14") (_pic14_parseOptions): moved pCodeInitRegisters here (_pic14_do_link): add "pic$(ARCH).lib" to linker arguments * src/pic/pcode.c (AnalyzeBanking): bail out on unset processor, (pCodeInitRegisters): rewrapped comments, perpared new approach to handling the pseudo stack * device/lib/Makefile.in: ignore failures in objects-pic16, * device/lib/pic/{configure,configure.in,Makefile}: added libdev/ * device/lib/pic/NEWS: document new dependency on picXXX.lib * device/lib/pic/Makefile.subdir, * device/lib/pic16/Makefile.subdir: improved clean rules * device/lib/pic/libdev/: NEW, pic14 device libraries * device/lib/pic/libsdcc/_gptr{get,put}{1,2,3,4}.S: use _X not X * device/lib/pic/libsdcc/macros.inc: use _X not X, declare default SFRs * device/include/Makefile.in: create subdir and install pic14 headers * device/include/pic/p16f_common.inc: removed unused declarations * device/include/pic/pic16*.h: added header files for 100+ 14 bit PICs from inc2h.pl v1.6, replaced BIT_AT macros with struct declarations * device/include/pic/pic14devices.txt: definition of supported devices, all above improvements contributed by Zik Saleeba, thanks * support/scripts/inc2h.pl: removed BIT_AT, replaced with structs * support/scripts/sdcc.nsi: also install pic14 device libraries and headers git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4086 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- ChangeLog | 43 + device/include/Makefile.in | 5 + device/include/pic/p16f_common.inc | 52 - device/include/pic/pic14devices.txt | 1035 +++++++++++++ device/include/pic/pic14regs.h | 22 + device/include/pic/pic16c432.h | 418 ++++++ device/include/pic/pic16c433.h | 423 ++++++ device/include/pic/pic16c554.h | 253 ++++ device/include/pic/pic16c557.h | 261 ++++ device/include/pic/pic16c558.h | 255 ++++ device/include/pic/pic16c62.h | 554 +++++++ device/include/pic/pic16c620.h | 372 +++++ device/include/pic/pic16c620a.h | 378 +++++ device/include/pic/pic16c621.h | 373 +++++ device/include/pic/pic16c621a.h | 374 +++++ device/include/pic/pic16c622.h | 373 +++++ device/include/pic/pic16c622a.h | 374 +++++ device/include/pic/pic16c63a.h | 778 ++++++++++ device/include/pic/pic16c65b.h | 817 ++++++++++ device/include/pic/pic16c71.h | 308 ++++ device/include/pic/pic16c710.h | 345 +++++ device/include/pic/pic16c711.h | 345 +++++ device/include/pic/pic16c715.h | 397 +++++ device/include/pic/pic16c717.h | 846 +++++++++++ device/include/pic/pic16c72.h | 639 ++++++++ device/include/pic/pic16c73b.h | 859 +++++++++++ device/include/pic/pic16c745.h | 974 ++++++++++++ device/include/pic/pic16c74b.h | 898 +++++++++++ device/include/pic/pic16c765.h | 1013 +++++++++++++ device/include/pic/pic16c770.h | 846 +++++++++++ device/include/pic/pic16c771.h | 846 +++++++++++ device/include/pic/pic16c773.h | 975 ++++++++++++ device/include/pic/pic16c774.h | 1012 +++++++++++++ device/include/pic/pic16c781.h | 806 ++++++++++ device/include/pic/pic16c782.h | 806 ++++++++++ device/include/pic/pic16c925.h | 879 +++++++++++ device/include/pic/pic16c926.h | 879 +++++++++++ device/include/pic/pic16f505.h | 223 +++ device/include/pic/pic16f627.h | 611 ++++++++ device/include/pic/pic16f627a.h | 615 ++++++++ device/include/pic/pic16f628.h | 611 ++++++++ device/include/pic/pic16f628a.h | 616 ++++++++ device/include/pic/pic16f630.h | 519 +++++++ device/include/pic/pic16f636.h | 691 +++++++++ device/include/pic/pic16f639.h | 687 +++++++++ device/include/pic/pic16f648a.h | 614 ++++++++ device/include/pic/pic16f676.h | 613 ++++++++ device/include/pic/pic16f684.h | 875 +++++++++++ device/include/pic/pic16f685.h | 1173 +++++++++++++++ device/include/pic/pic16f687.h | 1259 ++++++++++++++++ device/include/pic/pic16f688.h | 842 +++++++++++ device/include/pic/pic16f689.h | 1259 ++++++++++++++++ device/include/pic/pic16f690.h | 1396 ++++++++++++++++++ device/include/pic/pic16f716.h | 645 ++++++++ device/include/pic/pic16f72.h | 705 +++++++++ device/include/pic/pic16f73.h | 896 +++++++++++ device/include/pic/pic16f737.h | 1302 ++++++++++++++++ device/include/pic/pic16f74.h | 934 ++++++++++++ device/include/pic/pic16f76.h | 895 +++++++++++ device/include/pic/pic16f767.h | 1296 ++++++++++++++++ device/include/pic/pic16f77.h | 934 ++++++++++++ device/include/pic/pic16f777.h | 1301 ++++++++++++++++ device/include/pic/pic16f785.h | 1038 +++++++++++++ device/include/pic/pic16f818.h | 814 ++++++++++ device/include/pic/pic16f819.h | 815 ++++++++++ device/include/pic/pic16f84.h | 268 ++++ device/include/pic/pic16f84a.h | 266 ++++ device/include/pic/pic16f87.h | 974 ++++++++++++ device/include/pic/pic16f870.h | 768 ++++++++++ device/include/pic/pic16f871.h | 808 ++++++++++ device/include/pic/pic16f872.h | 804 ++++++++++ device/include/pic/pic16f873.h | 966 ++++++++++++ device/include/pic/pic16f873a.h | 1024 +++++++++++++ device/include/pic/pic16f874.h | 1006 +++++++++++++ device/include/pic/pic16f874a.h | 1064 +++++++++++++ device/include/pic/pic16f876.h | 967 ++++++++++++ device/include/pic/pic16f876a.h | 1024 +++++++++++++ device/include/pic/pic16f877.h | 1903 ++++++++++++------------ device/include/pic/pic16f877a.h | 1076 ++++++++++++++ device/include/pic/pic16f88.h | 1057 +++++++++++++ device/include/pic/pic16f913.h | 1849 +++++++++++++++++++++++ device/include/pic/pic16f914.h | 2132 +++++++++++++++++++++++++++ device/include/pic/pic16f916.h | 1849 +++++++++++++++++++++++ device/include/pic/pic16f917.h | 2132 +++++++++++++++++++++++++++ device/lib/Makefile.in | 2 +- device/lib/pic/Makefile | 2 +- device/lib/pic/Makefile.subdir | 2 + device/lib/pic/NEWS | 7 + device/lib/pic/configure | 4 +- device/lib/pic/configure.in | 4 +- device/lib/pic/libdev/Makefile.in | 41 + device/lib/pic/libdev/p16c620a.c | 0 device/lib/pic/libdev/pic16c432.c | 40 + device/lib/pic/libdev/pic16c433.c | 38 + device/lib/pic/libdev/pic16c554.c | 29 + device/lib/pic/libdev/pic16c557.c | 31 + device/lib/pic/libdev/pic16c558.c | 29 + device/lib/pic/libdev/pic16c62.c | 53 + device/lib/pic/libdev/pic16c620.c | 37 + device/lib/pic/libdev/pic16c620a.c | 37 + device/lib/pic/libdev/pic16c621.c | 37 + device/lib/pic/libdev/pic16c621a.c | 37 + device/lib/pic/libdev/pic16c622.c | 37 + device/lib/pic/libdev/pic16c622a.c | 37 + device/lib/pic/libdev/pic16c63a.c | 68 + device/lib/pic/libdev/pic16c65b.c | 73 + device/lib/pic/libdev/pic16c71.c | 32 + device/lib/pic/libdev/pic16c710.c | 34 + device/lib/pic/libdev/pic16c711.c | 34 + device/lib/pic/libdev/pic16c715.c | 38 + device/lib/pic/libdev/pic16c717.c | 77 + device/lib/pic/libdev/pic16c72.c | 58 + device/lib/pic/libdev/pic16c73b.c | 73 + device/lib/pic/libdev/pic16c745.c | 101 ++ device/lib/pic/libdev/pic16c74b.c | 78 + device/lib/pic/libdev/pic16c765.c | 106 ++ device/lib/pic/libdev/pic16c770.c | 77 + device/lib/pic/libdev/pic16c771.c | 77 + device/lib/pic/libdev/pic16c773.c | 80 + device/lib/pic/libdev/pic16c774.c | 85 ++ device/lib/pic/libdev/pic16c781.c | 72 + device/lib/pic/libdev/pic16c782.c | 72 + device/lib/pic/libdev/pic16c925.c | 96 ++ device/lib/pic/libdev/pic16c926.c | 96 ++ device/lib/pic/libdev/pic16f505.c | 24 + device/lib/pic/libdev/pic16f627.c | 61 + device/lib/pic/libdev/pic16f627a.c | 61 + device/lib/pic/libdev/pic16f628.c | 61 + device/lib/pic/libdev/pic16f628a.c | 61 + device/lib/pic/libdev/pic16f630.c | 52 + device/lib/pic/libdev/pic16f636.c | 62 + device/lib/pic/libdev/pic16f639.c | 62 + device/lib/pic/libdev/pic16f648a.c | 61 + device/lib/pic/libdev/pic16f676.c | 58 + device/lib/pic/libdev/pic16f684.c | 76 + device/lib/pic/libdev/pic16f685.c | 94 ++ device/lib/pic/libdev/pic16f687.c | 101 ++ device/lib/pic/libdev/pic16f688.c | 75 + device/lib/pic/libdev/pic16f689.c | 101 ++ device/lib/pic/libdev/pic16f690.c | 114 ++ device/lib/pic/libdev/pic16f716.c | 58 + device/lib/pic/libdev/pic16f72.c | 64 + device/lib/pic/libdev/pic16f73.c | 79 + device/lib/pic/libdev/pic16f737.c | 105 ++ device/lib/pic/libdev/pic16f74.c | 84 ++ device/lib/pic/libdev/pic16f76.c | 79 + device/lib/pic/libdev/pic16f767.c | 103 ++ device/lib/pic/libdev/pic16f77.c | 84 ++ device/lib/pic/libdev/pic16f777.c | 105 ++ device/lib/pic/libdev/pic16f785.c | 83 ++ device/lib/pic/libdev/pic16f818.c | 72 + device/lib/pic/libdev/pic16f819.c | 72 + device/lib/pic/libdev/pic16f84.c | 32 + device/lib/pic/libdev/pic16f84a.c | 32 + device/lib/pic/libdev/pic16f87.c | 79 + device/lib/pic/libdev/pic16f870.c | 71 + device/lib/pic/libdev/pic16f871.c | 76 + device/lib/pic/libdev/pic16f872.c | 72 + device/lib/pic/libdev/pic16f873.c | 83 ++ device/lib/pic/libdev/pic16f873a.c | 87 ++ device/lib/pic/libdev/pic16f874.c | 88 ++ device/lib/pic/libdev/pic16f874a.c | 92 ++ device/lib/pic/libdev/pic16f876.c | 83 ++ device/lib/pic/libdev/pic16f876a.c | 87 ++ device/lib/pic/libdev/pic16f877.c | 88 ++ device/lib/pic/libdev/pic16f877a.c | 92 ++ device/lib/pic/libdev/pic16f88.c | 86 ++ device/lib/pic/libdev/pic16f913.c | 127 ++ device/lib/pic/libdev/pic16f914.c | 143 ++ device/lib/pic/libdev/pic16f916.c | 127 ++ device/lib/pic/libdev/pic16f917.c | 143 ++ device/lib/pic/libsdcc/_gptrget1.S | 6 +- device/lib/pic/libsdcc/_gptrget2.S | 10 +- device/lib/pic/libsdcc/_gptrget3.S | 18 +- device/lib/pic/libsdcc/_gptrget4.S | 26 +- device/lib/pic/libsdcc/_gptrput1.S | 2 +- device/lib/pic/libsdcc/_gptrput2.S | 4 +- device/lib/pic/libsdcc/_gptrput3.S | 6 +- device/lib/pic/libsdcc/_gptrput4.S | 8 +- device/lib/pic/libsdcc/macros.inc | 28 +- device/lib/pic16/Makefile.subdir | 4 + src/SDCCmain.c | 6 + src/pic/device.c | 628 ++++++-- src/pic/device.h | 9 + src/pic/glue.c | 152 +- src/pic/main.c | 54 +- src/pic/pcode.c | 20 +- src/pic/ralloc.c | 13 +- support/scripts/inc2h.pl | 142 +- support/scripts/sdcc.nsi | 16 + 190 files changed, 72580 insertions(+), 1252 deletions(-) create mode 100644 device/include/pic/pic14devices.txt create mode 100644 device/include/pic/pic14regs.h create mode 100644 device/include/pic/pic16c432.h create mode 100644 device/include/pic/pic16c433.h create mode 100644 device/include/pic/pic16c554.h create mode 100644 device/include/pic/pic16c557.h create mode 100644 device/include/pic/pic16c558.h create mode 100644 device/include/pic/pic16c62.h create mode 100644 device/include/pic/pic16c620.h create mode 100644 device/include/pic/pic16c620a.h create mode 100644 device/include/pic/pic16c621.h create mode 100644 device/include/pic/pic16c621a.h create mode 100644 device/include/pic/pic16c622.h create mode 100644 device/include/pic/pic16c622a.h create mode 100644 device/include/pic/pic16c63a.h create mode 100644 device/include/pic/pic16c65b.h create mode 100644 device/include/pic/pic16c71.h create mode 100644 device/include/pic/pic16c710.h create mode 100644 device/include/pic/pic16c711.h create mode 100644 device/include/pic/pic16c715.h create mode 100644 device/include/pic/pic16c717.h create mode 100644 device/include/pic/pic16c72.h create mode 100644 device/include/pic/pic16c73b.h create mode 100644 device/include/pic/pic16c745.h create mode 100644 device/include/pic/pic16c74b.h create mode 100644 device/include/pic/pic16c765.h create mode 100644 device/include/pic/pic16c770.h create mode 100644 device/include/pic/pic16c771.h create mode 100644 device/include/pic/pic16c773.h create mode 100644 device/include/pic/pic16c774.h create mode 100644 device/include/pic/pic16c781.h create mode 100644 device/include/pic/pic16c782.h create mode 100644 device/include/pic/pic16c925.h create mode 100644 device/include/pic/pic16c926.h create mode 100644 device/include/pic/pic16f505.h create mode 100644 device/include/pic/pic16f627.h create mode 100644 device/include/pic/pic16f627a.h create mode 100644 device/include/pic/pic16f628.h create mode 100644 device/include/pic/pic16f628a.h create mode 100644 device/include/pic/pic16f630.h create mode 100644 device/include/pic/pic16f636.h create mode 100644 device/include/pic/pic16f639.h create mode 100644 device/include/pic/pic16f648a.h create mode 100644 device/include/pic/pic16f676.h create mode 100644 device/include/pic/pic16f684.h create mode 100644 device/include/pic/pic16f685.h create mode 100644 device/include/pic/pic16f687.h create mode 100644 device/include/pic/pic16f688.h create mode 100644 device/include/pic/pic16f689.h create mode 100644 device/include/pic/pic16f690.h create mode 100644 device/include/pic/pic16f716.h create mode 100644 device/include/pic/pic16f72.h create mode 100644 device/include/pic/pic16f73.h create mode 100644 device/include/pic/pic16f737.h create mode 100644 device/include/pic/pic16f74.h create mode 100644 device/include/pic/pic16f76.h create mode 100644 device/include/pic/pic16f767.h create mode 100644 device/include/pic/pic16f77.h create mode 100644 device/include/pic/pic16f777.h create mode 100644 device/include/pic/pic16f785.h create mode 100644 device/include/pic/pic16f818.h create mode 100644 device/include/pic/pic16f819.h create mode 100644 device/include/pic/pic16f84.h create mode 100644 device/include/pic/pic16f84a.h create mode 100644 device/include/pic/pic16f87.h create mode 100644 device/include/pic/pic16f870.h create mode 100644 device/include/pic/pic16f871.h create mode 100644 device/include/pic/pic16f872.h create mode 100644 device/include/pic/pic16f873.h create mode 100644 device/include/pic/pic16f873a.h create mode 100644 device/include/pic/pic16f874.h create mode 100644 device/include/pic/pic16f874a.h create mode 100644 device/include/pic/pic16f876.h create mode 100644 device/include/pic/pic16f876a.h create mode 100644 device/include/pic/pic16f877a.h create mode 100644 device/include/pic/pic16f88.h create mode 100644 device/include/pic/pic16f913.h create mode 100644 device/include/pic/pic16f914.h create mode 100644 device/include/pic/pic16f916.h create mode 100644 device/include/pic/pic16f917.h create mode 100644 device/lib/pic/libdev/Makefile.in create mode 100644 device/lib/pic/libdev/p16c620a.c create mode 100644 device/lib/pic/libdev/pic16c432.c create mode 100644 device/lib/pic/libdev/pic16c433.c create mode 100644 device/lib/pic/libdev/pic16c554.c create mode 100644 device/lib/pic/libdev/pic16c557.c create mode 100644 device/lib/pic/libdev/pic16c558.c create mode 100644 device/lib/pic/libdev/pic16c62.c create mode 100644 device/lib/pic/libdev/pic16c620.c create mode 100644 device/lib/pic/libdev/pic16c620a.c create mode 100644 device/lib/pic/libdev/pic16c621.c create mode 100644 device/lib/pic/libdev/pic16c621a.c create mode 100644 device/lib/pic/libdev/pic16c622.c create mode 100644 device/lib/pic/libdev/pic16c622a.c create mode 100644 device/lib/pic/libdev/pic16c63a.c create mode 100644 device/lib/pic/libdev/pic16c65b.c create mode 100644 device/lib/pic/libdev/pic16c71.c create mode 100644 device/lib/pic/libdev/pic16c710.c create mode 100644 device/lib/pic/libdev/pic16c711.c create mode 100644 device/lib/pic/libdev/pic16c715.c create mode 100644 device/lib/pic/libdev/pic16c717.c create mode 100644 device/lib/pic/libdev/pic16c72.c create mode 100644 device/lib/pic/libdev/pic16c73b.c create mode 100644 device/lib/pic/libdev/pic16c745.c create mode 100644 device/lib/pic/libdev/pic16c74b.c create mode 100644 device/lib/pic/libdev/pic16c765.c create mode 100644 device/lib/pic/libdev/pic16c770.c create mode 100644 device/lib/pic/libdev/pic16c771.c create mode 100644 device/lib/pic/libdev/pic16c773.c create mode 100644 device/lib/pic/libdev/pic16c774.c create mode 100644 device/lib/pic/libdev/pic16c781.c create mode 100644 device/lib/pic/libdev/pic16c782.c create mode 100644 device/lib/pic/libdev/pic16c925.c create mode 100644 device/lib/pic/libdev/pic16c926.c create mode 100644 device/lib/pic/libdev/pic16f505.c create mode 100644 device/lib/pic/libdev/pic16f627.c create mode 100644 device/lib/pic/libdev/pic16f627a.c create mode 100644 device/lib/pic/libdev/pic16f628.c create mode 100644 device/lib/pic/libdev/pic16f628a.c create mode 100644 device/lib/pic/libdev/pic16f630.c create mode 100644 device/lib/pic/libdev/pic16f636.c create mode 100644 device/lib/pic/libdev/pic16f639.c create mode 100644 device/lib/pic/libdev/pic16f648a.c create mode 100644 device/lib/pic/libdev/pic16f676.c create mode 100644 device/lib/pic/libdev/pic16f684.c create mode 100644 device/lib/pic/libdev/pic16f685.c create mode 100644 device/lib/pic/libdev/pic16f687.c create mode 100644 device/lib/pic/libdev/pic16f688.c create mode 100644 device/lib/pic/libdev/pic16f689.c create mode 100644 device/lib/pic/libdev/pic16f690.c create mode 100644 device/lib/pic/libdev/pic16f716.c create mode 100644 device/lib/pic/libdev/pic16f72.c create mode 100644 device/lib/pic/libdev/pic16f73.c create mode 100644 device/lib/pic/libdev/pic16f737.c create mode 100644 device/lib/pic/libdev/pic16f74.c create mode 100644 device/lib/pic/libdev/pic16f76.c create mode 100644 device/lib/pic/libdev/pic16f767.c create mode 100644 device/lib/pic/libdev/pic16f77.c create mode 100644 device/lib/pic/libdev/pic16f777.c create mode 100644 device/lib/pic/libdev/pic16f785.c create mode 100644 device/lib/pic/libdev/pic16f818.c create mode 100644 device/lib/pic/libdev/pic16f819.c create mode 100644 device/lib/pic/libdev/pic16f84.c create mode 100644 device/lib/pic/libdev/pic16f84a.c create mode 100644 device/lib/pic/libdev/pic16f87.c create mode 100644 device/lib/pic/libdev/pic16f870.c create mode 100644 device/lib/pic/libdev/pic16f871.c create mode 100644 device/lib/pic/libdev/pic16f872.c create mode 100644 device/lib/pic/libdev/pic16f873.c create mode 100644 device/lib/pic/libdev/pic16f873a.c create mode 100644 device/lib/pic/libdev/pic16f874.c create mode 100644 device/lib/pic/libdev/pic16f874a.c create mode 100644 device/lib/pic/libdev/pic16f876.c create mode 100644 device/lib/pic/libdev/pic16f876a.c create mode 100644 device/lib/pic/libdev/pic16f877.c create mode 100644 device/lib/pic/libdev/pic16f877a.c create mode 100644 device/lib/pic/libdev/pic16f88.c create mode 100644 device/lib/pic/libdev/pic16f913.c create mode 100644 device/lib/pic/libdev/pic16f914.c create mode 100644 device/lib/pic/libdev/pic16f916.c create mode 100644 device/lib/pic/libdev/pic16f917.c diff --git a/ChangeLog b/ChangeLog index 8274bbac..98dc7a47 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,46 @@ +2006-04-06 Raphael Neider + + * .version: bumped version to 2.5.6 (pic14 ABI changed) + * src/SDCCmain.c: add -DSDCC_PROCESSOR= for pic14 port + * src/pic/glue.c (emitSymbolToFile,pic14_constructAbsMap, + pic14emitRegularMap,pic14emitMaps): moved output for absolute symbols to + pic14_constructAbsMap + (pic14printPublics): declare absolute global symbols as global + (pic14createInterruptVect), + * src/pic/ralloc.c (IS_CONFIG_ADDRESS): support second config word, + (newReg): assume new registers unused, use correct name in + hashtable (reg->name instead of name), more debugLog output + * src/pic/device.h (PIC_device): added fields for verbose output + * src/pic/device.c: moved device definition to pic14devices.txt, + added routines for runtime parsing of pic14devices.txt, + added support for second config word + * src/pic/main.c (_process_pragma): removed #pragma maxram, + (_pic14_keywords): no longer accept "bit" and "sbit" keywords + (_pic14_initPaths): add search paths with "pic" suffix (not "pic14") + (_pic14_parseOptions): moved pCodeInitRegisters here + (_pic14_do_link): add "pic$(ARCH).lib" to linker arguments + * src/pic/pcode.c (AnalyzeBanking): bail out on unset processor, + (pCodeInitRegisters): rewrapped comments, perpared new approach to + handling the pseudo stack + * device/lib/Makefile.in: ignore failures in objects-pic16, + * device/lib/pic/{configure,configure.in,Makefile}: added libdev/ + * device/lib/pic/NEWS: document new dependency on picXXX.lib + * device/lib/pic/Makefile.subdir, + * device/lib/pic16/Makefile.subdir: improved clean rules + * device/lib/pic/libdev/: NEW, pic14 device libraries + * device/lib/pic/libsdcc/_gptr{get,put}{1,2,3,4}.S: use _X not X + * device/lib/pic/libsdcc/macros.inc: use _X not X, declare default SFRs + * device/include/Makefile.in: create subdir and install pic14 headers + * device/include/pic/p16f_common.inc: removed unused declarations + * device/include/pic/pic16*.h: added header files for 100+ 14 bit + PICs from inc2h.pl v1.6, + replaced BIT_AT macros with struct declarations + * device/include/pic/pic14devices.txt: definition of supported devices, + all above improvements contributed by Zik Saleeba, thanks + * support/scripts/inc2h.pl: removed BIT_AT, replaced with structs + * support/scripts/sdcc.nsi: also install pic14 device libraries and + headers + 2006-04-06 Maarten Brock * device/include/mcs51/c8051f410.h: added interrupt numbers, diff --git a/device/include/Makefile.in b/device/include/Makefile.in index 30973218..8cbbbe7c 100644 --- a/device/include/Makefile.in +++ b/device/include/Makefile.in @@ -44,6 +44,10 @@ install: all installdirs if [ "`grep mcs51 ../../ports.build`" = mcs51 ]; then \ $(CP) mcs51/*.h $(sdcc_includedir)/mcs51 ; \ fi + if [ "`grep '^pic$$' ../../ports.build`" = pic ]; then \ + $(CP) pic/*.h $(sdcc_includedir)/pic ; \ + $(CP) pic/pic14devices.txt $(sdcc_includedir)/pic ; \ + fi if [ "`grep pic16 ../../ports.build`" = pic16 ]; then \ $(CP) pic16/*.h $(sdcc_includedir)/pic16 ; \ fi @@ -77,6 +81,7 @@ installcheck: installdirs: [ -d $(sdcc_includedir) ] || mkdir -p $(sdcc_includedir) [ -d $(sdcc_includedir)/mcs51 ] || mkdir -p $(sdcc_includedir)/mcs51 + [ -d $(sdcc_includedir)/pic ] || mkdir -p $(sdcc_includedir)/pic [ -d $(sdcc_includedir)/pic16 ] || mkdir -p $(sdcc_includedir)/pic16 [ -d $(sdcc_includedir)/z80 ] || mkdir -p $(sdcc_includedir)/z80 [ -d $(sdcc_includedir)/hc08 ] || mkdir -p $(sdcc_includedir)/hc08 diff --git a/device/include/pic/p16f_common.inc b/device/include/pic/p16f_common.inc index 6f0b03f4..e6260f47 100644 --- a/device/include/pic/p16f_common.inc +++ b/device/include/pic/p16f_common.inc @@ -15,56 +15,4 @@ extern STK03 extern STK04 extern STK05 - extern STK06 - extern STK07 - extern STK08 - extern STK09 - extern STK10 - extern STK11 - extern STK12 - extern STK13 - extern STK14 - -; ----------------------------------------------- -; --- PIC14 special function registers -; ----------------------------------------------- - -INDF EQU 0x0000 -TMR0 EQU 0x0001 -PCL EQU 0x0002 -STATUS EQU 0x0003 -FSR EQU 0x0004 -PORTA EQU 0x0005 -PORTB EQU 0x0006 -; unimplemented EQU 0x0007 -EEDATA EQU 0x0008 -EEADR EQU 0x0009 -PCLATH EQU 0x000a -INTCON EQU 0x000b - -; INDF EQU 0x0080 -OPTION_REG EQU 0x0081 -; PCL EQU 0x0082 -; STATUS EQU 0x0083 -; FSR EQU 0x0084 -TRISA EQU 0x0085 -TRISB EQU 0x0086 -; unimplemented EQU 0x0087 -EECON1 EQU 0x0088 -EECON2 EQU 0x0089 -; PCLATH EQU 0x008a -; INTCON EQU 0x008b - -; ----------------------------------------------- -; --- useful symbolic constants -; ----------------------------------------------- - -C EQU 0 -DC EQU 1 -Z EQU 2 -nPD EQU 3 -nTO EQU 4 -RP0 EQU 5 -RP1 EQU 6 ; possibly unimplemented -IRP EQU 7 ; possibly unimplemented diff --git a/device/include/pic/pic14devices.txt b/device/include/pic/pic14devices.txt new file mode 100644 index 00000000..1db9a6da --- /dev/null +++ b/device/include/pic/pic14devices.txt @@ -0,0 +1,1035 @@ +# +# PIC14: 16Fxxx / 16Cxxx series device file for SDCC +# +# by Zik Saleeba 2006-03-04 +# + +# +# dev = device name +# program = program memory in 14 bit words +# data = data memory in bytes +# eeprom = eeprom storage +# io = io lines +# maxram = maximum memmap address for unique general purpose registers +# bankmsk = mask for memmap bank selecting. 0x80 for two banks usable, +# 0x180 for four. +# confsiz = 1: config at 0x2007, 2: has an extra config register at 0x2008 +# regmap = registers duplicated in multiple banks. First value is a bank bitmask, +# following values are register addresses +# +# + +# +# 16F series +# +processor 16f54 + program 512 + data 25 + eeprom 0 + io 12 + maxram 0x1f + bankmsk 0x00 + confsiz 1 + memmap 0x0007 0x001f 0x000 + +processor 16f57 + program 2K + data 72 + eeprom 0 + io 20 + maxram 0x7f + bankmsk 0x60 + confsiz 1 + regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 + memmap 0x0008 0x000f 0x060 + memmap 0x0010 0x001f 0x000 + memmap 0x0030 0x003f 0x000 + memmap 0x0050 0x005f 0x000 + memmap 0x0070 0x007f 0x000 + +processor 16f59 + program 2K + data 134 + eeprom 0 + io 32 + maxram 0x7f + bankmsk 0xe0 + confsiz 1 + regmap 0xe0 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 + memmap 0x000a 0x000f 0x000 + memmap 0x0010 0x001f 0x0e0 + memmap 0x0030 0x003f 0x000 + memmap 0x0050 0x005f 0x000 + memmap 0x0070 0x007f 0x000 + memmap 0x0090 0x009f 0x000 + memmap 0x00b0 0x00bf 0x000 + memmap 0x00d0 0x00df 0x000 + memmap 0x00e0 0x00ef 0x000 + +processor 16f72 + program 2K + data 128 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x06 0x0a 0x0b + regmap 0x100 0x01 0x81 + memmap 0x0020 0x003f 0x100 + memmap 0x0040 0x007f 0x180 + memmap 0x00a0 0x00bf 0x100 + +processor 16f73 + program 4K + data 192 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x007f 0x100 + memmap 0x00a0 0x00ff 0x100 + +processor 16f74 + program 4K + data 192 + eeprom 0 + io 33 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x007f 0x100 + memmap 0x00a0 0x00ff 0x100 + +processor 16f76 + program 8K + data 368 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01ef 0x000 + +processor 16f77 + program 8K + data 368 + eeprom 0 + io 33 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01ef 0x000 + +processor 16f84, 16f84a + program 1K + data 68 + eeprom 64 + io 13 + maxram 0xcf + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x000C 0x004f 0x080 + +processor 16f87, 16f88 + program 4K + data 368 + eeprom 256 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f505 + program 1K + data 72 + eeprom 0 + io 12 + maxram 0x7f + bankmsk 0x60 + confsiz 1 + regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 + memmap 0x0008 0x000f 0x060 + memmap 0x0010 0x001f 0x000 + memmap 0x0030 0x003f 0x000 + memmap 0x0050 0x005f 0x000 + memmap 0x0070 0x007f 0x000 + +processor 16f506 + program 1K + data 67 + eeprom 0 + io 12 + maxram 0x7f + bankmsk 0x60 + confsiz 1 + regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c + memmap 0x000d 0x000f 0x060 + memmap 0x0010 0x001f 0x000 + memmap 0x0030 0x003f 0x000 + memmap 0x0050 0x005f 0x000 + memmap 0x0070 0x007f 0x000 + +processor 16f627, 16f627a + program 1K + data 224 + eeprom 128 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x014f 0x000 + +processor 16f628, 16f628a + program 2K + data 224 + eeprom 128 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x014f 0x000 + +processor 16f648, 16f648a + program 4K + data 256 + eeprom 256 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f630, 16f676 + program 1K + data 64 + eeprom 128 + io 12 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x005f 0x080 + +processor 16f635 + program 1K + data 64 + eeprom 128 + io 6 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 + memmap 0x0040 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + +processor 16f636, 16f639 + program 2K + data 128 + eeprom 256 + io 12 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x07 0x87 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f684 + program 2K + data 128 + eeprom 256 + io 12 + maxram 0xff + bankmsk 0x80 + confsiz 2 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 16f685, 16f689, 16f690 + program 4K + data 256 + eeprom 256 + io 18 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x06 0x86 0x07 0x87 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f687 + program 2K + data 128 + eeprom 256 + io 18 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x06 0x86 0x07 0x87 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f688 + program 4K + data 256 + eeprom 256 + io 12 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x07 0x87 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f716 + program 2K + data 128 + eeprom 0 + io 13 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 16f737 + program 4K + data 368 + eeprom 0 + io 25 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f747 + program 4K + data 368 + eeprom 0 + io 36 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f767 + program 8K + data 368 + eeprom 0 + io 25 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f777 + program 8K + data 368 + eeprom 0 + io 36 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f785, 16hv785 + program 2K + data 128 + eeprom 256 + io 18 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x05 0x85 0x06 0x86 0x07 0x87 0x8c + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f870, 16f872 + program 2K + data 128 + eeprom 64 + io 22 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x100 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x100 + +processor 16f871 + program 2K + data 128 + eeprom 64 + io 33 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x100 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x100 + +processor 16f873, 16f873a + program 4K + data 192 + eeprom 128 + io 22 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x007f 0x100 + memmap 0x00a0 0x00ff 0x100 + +processor 16f874, 16f874a + program 4K + data 192 + eeprom 128 + io 33 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x007f 0x100 + memmap 0x00a0 0x00ff 0x100 + +processor 16f876, 16f876a + program 8K + data 368 + eeprom 256 + io 22 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f877, 16f877a + program 8K + data 368 + eeprom 256 + io 22 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0110 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f818 + program 1K + data 128 + eeprom 128 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x003f 0x100 + memmap 0x0040 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16f819 + program 2K + data 256 + eeprom 256 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f913 + program 4K + data 256 + eeprom 256 + io 24 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f914 + program 4K + data 256 + eeprom 256 + io 35 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16f916 + program 8K + data 352 + eeprom 256 + io 24 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f917 + program 8K + data 352 + eeprom 256 + io 35 + maxram 0x1ff + bankmsk 0x180 + confsiz 2 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x0190 0x01ef 0x000 + +processor 16f946 + program 8K + data 336 + eeprom 256 + io 53 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01ef 0x000 + + +# +# 16c series +# +processor 16c54, 16c54a, 16c54c, 16cr54a, 16cr54c, 16hv540 + program 512 + data 25 + eeprom 0 + io 12 + maxram 0x1f + bankmsk 0x00 + confsiz 1 + memmap 0x0007 0x001f 0x000 + +processor 16c55, 16c55a + program 512 + data 24 + eeprom 0 + io 20 + maxram 0x1f + bankmsk 0x00 + confsiz 1 + memmap 0x0008 0x001f 0x000 + +processor 16c56, 16c56a, 16cr56a + program 1K + data 25 + eeprom 0 + io 12 + maxram 0x1f + bankmsk 0x00 + confsiz 1 + memmap 0x0007 0x001f 0x000 + +processor 16c57, 16c57c, 16cr57c + program 2K + data 72 + eeprom 0 + io 20 + maxram 0x7f + bankmsk 0x60 + confsiz 1 + regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 + memmap 0x0008 0x000f 0x060 + memmap 0x0010 0x001f 0x000 + memmap 0x0030 0x003f 0x000 + memmap 0x0050 0x005f 0x000 + memmap 0x0070 0x007f 0x000 + +processor 16c58b, 16cr58b + program 2K + data 73 + eeprom 0 + io 12 + maxram 0x7f + bankmsk 0x60 + confsiz 1 + regmap 0x60 0x00 0x01 0x02 0x03 0x04 0x05 0x06 + memmap 0x0007 0x000f 0x060 + memmap 0x0010 0x001f 0x000 + memmap 0x0030 0x003f 0x000 + memmap 0x0050 0x005f 0x000 + memmap 0x0070 0x007f 0x000 + +processor 16c62, 16c72 + program 2K + data 128 + eeprom 0 + io 22 + maxram 0xbf + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00bf 0x000 + +processor 16c63a, 16c73b + program 4K + data 192 + eeprom 0 + io 22 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00ff 0x000 + +processor 16c65b, 16c74b + program 4K + data 192 + eeprom 0 + io 33 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00ff 0x000 + +processor 16c432 + program 2K + data 128 + eeprom 0 + io 12 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 16c433 + program 2K + data 128 + eeprom 0 + io 6 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + +processor 16c554 + program 512 + data 80 + eeprom 0 + io 21 + maxram 0x6f + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + +processor 16c557, 16c558 + program 2K + data 128 + eeprom 0 + io 21 + maxram 0xbf + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00bf 0x000 + +processor 16c620 + program 512 + data 80 + eeprom 0 + io 13 + maxram 0x9f + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + +processor 16c620a, 16cr620a + program 512 + data 96 + eeprom 0 + io 13 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + +processor 16c621 + program 1K + data 80 + eeprom 0 + io 13 + maxram 0x9f + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + +processor 16c621a + program 1K + data 96 + eeprom 0 + io 13 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + +processor 16c622 + program 2K + data 128 + eeprom 0 + io 13 + maxram 0xbf + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00bf 0x000 + +processor 16c622a + program 2K + data 128 + eeprom 0 + io 13 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x080 + memmap 0x00a0 0x00bf 0x000 + + +processor 16c710 + program 512 + data 36 + eeprom 0 + io 13 + maxram 0xaf + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x09 0x0a 0x0b + memmap 0x000c 0x002f 0x080 + +processor 16c71 + program 1K + data 36 + eeprom 0 + io 13 + maxram 0xaf + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x09 0x0a 0x0b + memmap 0x000c 0x002f 0x080 + +processor 16c711 + program 1K + data 68 + eeprom 0 + io 13 + maxram 0xcf + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x09 0x0a 0x0b + memmap 0x000c 0x004f 0x080 + +processor 16c715 + program 2K + data 128 + eeprom 0 + io 13 + maxram 0xff + bankmsk 0x80 + confsiz 1 + regmap 0x80 0x00 0x02 0x03 0x04 0x0a 0x0b + memmap 0x0020 0x007f 0x000 + memmap 0x00a0 0x00bf 0x000 + +processor 16c717, 16c770 + program 2K + data 256 + eeprom 0 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16c771 + program 4K + data 256 + eeprom 0 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16c745 + program 8K + data 320 + eeprom 0 + io 22 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01df 0x000 + +processor 16c765 + program 8K + data 320 + eeprom 0 + io 33 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01df 0x000 + +processor 16c773 + program 4K + data 256 + eeprom 0 + io 21 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16c774 + program 4K + data 256 + eeprom 0 + io 32 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00ef 0x000 + memmap 0x0120 0x016f 0x000 + +processor 16c781 + program 1K + data 128 + eeprom 0 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16c782 + program 2K + data 128 + eeprom 0 + io 16 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16c925 + program 4K + data 176 + eeprom 0 + io 52 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + +processor 16c926 + program 8K + data 336 + eeprom 0 + io 52 + maxram 0x1ff + bankmsk 0x180 + confsiz 1 + regmap 0x180 0x00 0x02 0x03 0x04 0x0a 0x0b + regmap 0x100 0x01 0x81 0x06 0x86 + memmap 0x0020 0x006f 0x000 + memmap 0x0070 0x007f 0x180 + memmap 0x00a0 0x00bf 0x000 + memmap 0x0120 0x016f 0x000 + memmap 0x01a0 0x01bf 0x000 diff --git a/device/include/pic/pic14regs.h b/device/include/pic/pic14regs.h new file mode 100644 index 00000000..9cee5b2e --- /dev/null +++ b/device/include/pic/pic14regs.h @@ -0,0 +1,22 @@ +#ifndef __DEVICE_INCLUDE_PIC14REGS_H__ +#define __DEVICE_INCLUDE_PIC14REGS_H__ 1 + +#if defined(SDCC_PROCESSOR) + #ifndef _CONCAT + #undef _CONCAT2 + #define _CONCAT(a,b) _CONCAT2(a,b) + #define _CONCAT2(a,b) a ## b + #endif + + /* May not paste proc ## .h as pic16f877.h is no valid + * preprocessor token. So this is a bit fragile... */ + #define INC_PIC(proc) <_CONCAT(pic,proc).h> + + #include INC_PIC(SDCC_PROCESSOR) +#else + /* SDCC_PROCESSOR undefined */ + #warning SDCC_PROCESSOR undefined, no processor-specific header included. +#endif + +#endif /* __DEVICE_INCLUDE_PIC14REGS_H__ */ + diff --git a/device/include/pic/pic16c432.h b/device/include/pic/pic16c432.h new file mode 100644 index 00000000..504732b9 --- /dev/null +++ b/device/include/pic/pic16c432.h @@ -0,0 +1,418 @@ +// +// Register Declarations for Microchip 16C432 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C432_H +#define P16C432_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define LININTF_ADDR 0x0090 +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap LININTF_ADDR LININTF_ADDR SFR 0x000 // LININTF +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16C432.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C432 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C432 +// 2. LIST directive in the source file +// LIST P=PIC16C432 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 31 Aug 2000 Initial Release +//1.10 28 Mar 2001 Corrected definition of LINTX + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C432 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (LININTF_ADDR) LININTF; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PORTA Bits -------------------------------------------------------- + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- LININTF Bits ---------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'0FF' +// __BADRAM H'07'-H'09', H'0D'-H'1E' +// __BADRAM H'87'-H'89', H'8D', H'8F', H'91'-H'9E' +// __BADRAM H'C0'-H'EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char :1; + unsigned char :1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LININTF bits -------------------- +typedef union { + struct { + unsigned char LINVDD:1; + unsigned char :1; + unsigned char LINTX:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __LININTF_bits_t; +extern volatile __LININTF_bits_t __at(LININTF_ADDR) LININTF_bits; + +#define LINVDD LININTF_bits.LINVDD +#define LINTX LININTF_bits.LINTX + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define CMIE PIE1_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define CMIF PIR1_bits.CMIF + +// ----- PORTA bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char LINRX:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PORTA_bits_t; +extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits; + +#define LINRX PORTA_bits.LINRX + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16c433.h b/device/include/pic/pic16c433.h new file mode 100644 index 00000000..45615d67 --- /dev/null +++ b/device/include/pic/pic16c433.h @@ -0,0 +1,423 @@ +// +// Register Declarations for Microchip 16C433 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C433_H +#define P16C433_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define GPIO_ADDR 0x0005 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISIO_ADDR 0x0085 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define OSCCAL_ADDR 0x008F +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000 // GPIO +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000 // TRISIO +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C433.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C433 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C433 +// 2. LIST directive in the source file +// LIST P=PIC16C433 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 31 Aug 2000 Original Release +//1.10 28 Mar 2001 Corrected definitions of LINTX and LINRX. +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C433 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (GPIO_ADDR) GPIO; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISIO_ADDR) TRISIO; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCAL_ADDR) OSCCAL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- LIN Port bits (within GPIO) ---------------------------------------- + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCAL Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'06'-H'09', H'0D'-H'1D' +// __BADRAM H'86'-H'89', H'8D', H'90'-H'9E', H'C0'-H'EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3F7F +#define _CP_ALL 0x009F +#define _CP_75 0x15BF +#define _CP_50 0x2ADF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _INTRC_OSC 0x3FFC +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC 0x3FFE +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char GPIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char GPIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define GPIF INTCON_bits.GPIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define GPIE INTCON_bits.GPIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_GPPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_GPPU OPTION_REG_bits.NOT_GPPU + +// ----- OSCCAL bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char CALSLW:1; + unsigned char CALFST:1; + unsigned char CAL0:1; + unsigned char CAL1:1; + unsigned char CAL2:1; + unsigned char CAL3:1; + }; +} __OSCCAL_bits_t; +extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits; + +#define CALSLW OSCCAL_bits.CALSLW +#define CALFST OSCCAL_bits.CALFST +#define CAL0 OSCCAL_bits.CAL0 +#define CAL1 OSCCAL_bits.CAL1 +#define CAL2 OSCCAL_bits.CAL2 +#define CAL3 OSCCAL_bits.CAL3 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define ADIE PIE1_bits.ADIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define ADIF PIR1_bits.ADIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LINRX:1; + unsigned char LINTX:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define LINRX STATUS_bits.LINRX +#define IRP STATUS_bits.IRP +#define LINTX STATUS_bits.LINTX + +#endif diff --git a/device/include/pic/pic16c554.h b/device/include/pic/pic16c554.h new file mode 100644 index 00000000..9201a1c9 --- /dev/null +++ b/device/include/pic/pic16c554.h @@ -0,0 +1,253 @@ +// +// Register Declarations for Microchip 16C554 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C554_H +#define P16C554_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PCON_ADDR 0x008E + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON + + +// LIST +// P16C554.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C554 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C554 +// 2. LIST directive in the source file +// LIST P=PIC16C554 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 04/22/96 Initial Creation + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C554 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PCON_ADDR) PCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'09F' +// __BADRAM H'07'-H'09', H'0C'-H'1F', H'70'-H'7F' +// __BADRAM H'87'-H'89', H'8C'-H'8D', H'8F'-H'9F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ON 0x00CF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char :1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_POR PCON_bits.NOT_POR + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +#endif diff --git a/device/include/pic/pic16c557.h b/device/include/pic/pic16c557.h new file mode 100644 index 00000000..284c92b0 --- /dev/null +++ b/device/include/pic/pic16c557.h @@ -0,0 +1,261 @@ +// +// Register Declarations for Microchip 16C557 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C557_H +#define P16C557_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PCON_ADDR 0x008E + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON + + +// LIST +// P16C557.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C557 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /p=16C557 +// 2. LIST directive in the source file +// LIST P=16C557 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 08/29/01 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C557 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PCON_ADDR) PCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'08'-H'09', H'0C'-H'1F' +// __BADRAM H'88'-H'89', H'8C'-H'8D', H'8F'-H'9F', H'C0'-H'EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char :1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_POR PCON_bits.NOT_POR + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +#endif diff --git a/device/include/pic/pic16c558.h b/device/include/pic/pic16c558.h new file mode 100644 index 00000000..5f6e983c --- /dev/null +++ b/device/include/pic/pic16c558.h @@ -0,0 +1,255 @@ +// +// Register Declarations for Microchip 16C558 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C558_H +#define P16C558_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PCON_ADDR 0x008E + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON + + +// LIST +// P16C558.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C558 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C558 +// 2. LIST directive in the source file +// LIST P=PIC16C558 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 04/22/96 Initial Creation + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C558 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PCON_ADDR) PCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'BF' +// __BADRAM H'07'-H'09', H'0C'-H'1F' +// __BADRAM H'87'-H'89', H'8C'-H'8D', H'8F'-H'9F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char :1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_POR PCON_bits.NOT_POR + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +#endif diff --git a/device/include/pic/pic16c62.h b/device/include/pic/pic16c62.h new file mode 100644 index 00000000..09be42bc --- /dev/null +++ b/device/include/pic/pic16c62.h @@ -0,0 +1,554 @@ +// +// Register Declarations for Microchip 16C62 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C62_H +#define P16C62_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT + + +// LIST +// P16C62.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C62 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C62 +// 2. LIST directive in the source file +// LIST P=PIC16C62 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 10/31/95 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C62 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'BF' +// __BADRAM H'08'-H'09', H'0D', H'18'-H'1F' +// __BADRAM H'88'-H'89', H'8D', H'8F'-H'91',H'95'-H'9F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x3F8F +#define _CP_75 0x3F9F +#define _CP_50 0x3FAF +#define _CP_OFF 0x3FBF +#define _PWRTE_ON 0x3FBF +#define _PWRTE_OFF 0x3FB7 +#define _WDT_ON 0x3FBF +#define _WDT_OFF 0x3FBB +#define _LP_OSC 0x3FBC +#define _XT_OSC 0x3FBD +#define _HS_OSC 0x3FBE +#define _RC_OSC 0x3FBF + +// LIST + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +#endif diff --git a/device/include/pic/pic16c620.h b/device/include/pic/pic16c620.h new file mode 100644 index 00000000..3dac8fd7 --- /dev/null +++ b/device/include/pic/pic16c620.h @@ -0,0 +1,372 @@ +// +// Register Declarations for Microchip 16C620 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C620_H +#define P16C620_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16C620.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C620 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C620 +// 2. LIST directive in the source file +// LIST P=PIC16C620 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.01 11/28/95 Added NOT_BOR to match revised datasheet +//1.00 10/31/95 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C620 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'09F' +// __BADRAM H'07'-H'09', H'0D'-H'1E', H'70'-H'7F' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ON 0x00CF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char :1; + unsigned char :1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define CMIE PIE1_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define CMIF PIR1_bits.CMIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16c620a.h b/device/include/pic/pic16c620a.h new file mode 100644 index 00000000..c86a4b8a --- /dev/null +++ b/device/include/pic/pic16c620a.h @@ -0,0 +1,378 @@ +// +// Register Declarations for Microchip 16CR620A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16CR620A_H +#define P16CR620A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16C620A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C620A and PIC16CR620A microcontrollers. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C620A or +// C:\ MPASM MYFILE.ASM /PIC16CR620A +// 2. LIST directive in the source file +// LIST P=PIC16C620A or +// LIST P=PIC16CR620A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 05/28/97 Initial Release +//1.10 16/08/99 Added unbanked RAM at 70-7F +//1.20 06/12/02 Verification now includes the PIC16CR620A (pas) + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C620A +// IFNDEF __16CR620A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'0FF' +// __BADRAM H'07'-H'09', H'0D'-H'1E' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E' +// __BADRAM H'A0'-H'EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ON 0x00CF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char :1; + unsigned char :1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define CMIE PIE1_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define CMIF PIR1_bits.CMIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16c621.h b/device/include/pic/pic16c621.h new file mode 100644 index 00000000..f7b3b460 --- /dev/null +++ b/device/include/pic/pic16c621.h @@ -0,0 +1,373 @@ +// +// Register Declarations for Microchip 16C621 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C621_H +#define P16C621_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16C621.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C621 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C621 +// 2. LIST directive in the source file +// LIST P=PIC16C621 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.01 11/28/95 Added NOT_BOR to match revised datasheet +//1.00 10/31/95 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C621 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'9F' +// __BADRAM H'07'-H'09', H'0D'-H'01E', H'70'-H'7F' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_50 0x15DF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char :1; + unsigned char :1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define CMIE PIE1_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define CMIF PIR1_bits.CMIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16c621a.h b/device/include/pic/pic16c621a.h new file mode 100644 index 00000000..e0eef08e --- /dev/null +++ b/device/include/pic/pic16c621a.h @@ -0,0 +1,374 @@ +// +// Register Declarations for Microchip 16C621A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C621A_H +#define P16C621A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16C621A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C621A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C621A +// 2. LIST directive in the source file +// LIST P=PIC16C621A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 05/28/97 Initial Release +//1.10 16/08/99 Added unbanked RAM at 70-7F + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C621A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'0FF' +// __BADRAM H'07'-H'09', H'0D'-H'1E' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E' +// __BADRAM H'A0'-H'EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_50 0x15DF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char :1; + unsigned char :1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define CMIE PIE1_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define CMIF PIR1_bits.CMIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16c622.h b/device/include/pic/pic16c622.h new file mode 100644 index 00000000..2bfe1fa8 --- /dev/null +++ b/device/include/pic/pic16c622.h @@ -0,0 +1,373 @@ +// +// Register Declarations for Microchip 16C622 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C622_H +#define P16C622_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16C622.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C622 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C622 +// 2. LIST directive in the source file +// LIST P=PIC16C622 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.01 11/28/95 Added NOT_BOR to match revised datasheet +//1.00 10/31/95 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C622 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'BF' +// __BADRAM H'07'-H'09', H'0D'-H'1E', H'87'-H'89', H'8D', H'8F'-H'9E' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char :1; + unsigned char :1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define CMIE PIE1_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define CMIF PIR1_bits.CMIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16c622a.h b/device/include/pic/pic16c622a.h new file mode 100644 index 00000000..5551fc46 --- /dev/null +++ b/device/include/pic/pic16c622a.h @@ -0,0 +1,374 @@ +// +// Register Declarations for Microchip 16C622A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C622A_H +#define P16C622A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16C622A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C622A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C622A +// 2. LIST directive in the source file +// LIST P=PIC16C622A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 05/28/97 Initial Release +//1.10 16/08/99 Added unbanked RAM at 70-7F + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C622A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'07'-H'09', H'0D'-H'1E', H'87'-H'89', H'8D', H'8F'-H'9E' +// __BADRAM H'C0'-H'EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char :1; + unsigned char :1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define CMIE PIE1_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define CMIF PIR1_bits.CMIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16c63a.h b/device/include/pic/pic16c63a.h new file mode 100644 index 00000000..420bbdf4 --- /dev/null +++ b/device/include/pic/pic16c63a.h @@ -0,0 +1,778 @@ +// +// Register Declarations for Microchip 16C63A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C63A_H +#define P16C63A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG + + +// LIST +// P16C63A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C63A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C63A +// 2. LIST directive in the source file +// LIST P=PIC16C63A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 12/17/97 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C63A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'08'-H'09', H'1E'-H'1F' +// __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16c65b.h b/device/include/pic/pic16c65b.h new file mode 100644 index 00000000..13f48095 --- /dev/null +++ b/device/include/pic/pic16c65b.h @@ -0,0 +1,817 @@ +// +// Register Declarations for Microchip 16C65B Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C65B_H +#define P16C65B_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG + + +// LIST +// P16C65B.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C65B microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C65B +// 2. LIST directive in the source file +// LIST P=PIC16C65B +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 12/17/97 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C65B +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'1E'-H'1F',H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char :1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char :1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16c71.h b/device/include/pic/pic16c71.h new file mode 100644 index 00000000..25ebad37 --- /dev/null +++ b/device/include/pic/pic16c71.h @@ -0,0 +1,308 @@ +// +// Register Declarations for Microchip 16C71 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C71_H +#define P16C71_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define ADCON0_ADDR 0x0008 +#define ADRES_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define ADCON1_ADDR 0x0088 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C71.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C71 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C71 +// 2. LIST directive in the source file +// LIST P=PIC16C71 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 10/31/95 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C71 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (ADCON0_ADDR) ADCON0; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'AF' +// __BADRAM H'07', H'30'-H'7F', H'87' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ON 0x3FEF +#define _CP_OFF 0x3FFF +#define _PWRTE_ON 0x3FFF +#define _PWRTE_OFF 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char ADIF:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define ADIF ADCON0_bits.ADIF +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char ADIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define ADIE INTCON_bits.ADIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +#endif diff --git a/device/include/pic/pic16c710.h b/device/include/pic/pic16c710.h new file mode 100644 index 00000000..4036ebf7 --- /dev/null +++ b/device/include/pic/pic16c710.h @@ -0,0 +1,345 @@ +// +// Register Declarations for Microchip 16C710 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C710_H +#define P16C710_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define ADCON0_ADDR 0x0008 +#define ADRES_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PCON_ADDR 0x0087 +#define ADCON1_ADDR 0x0088 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C710.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C710 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C710 +// 2. LIST directive in the source file +// LIST P=PIC16C710 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 04/10/96 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C710 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (ADCON0_ADDR) ADCON0; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'AF' +// __BADRAM H'07', H'30'-H'7F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ON 0x004F +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char ADIF:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define ADIF ADCON0_bits.ADIF +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char ADIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define ADIE INTCON_bits.ADIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +#endif diff --git a/device/include/pic/pic16c711.h b/device/include/pic/pic16c711.h new file mode 100644 index 00000000..d21b1f50 --- /dev/null +++ b/device/include/pic/pic16c711.h @@ -0,0 +1,345 @@ +// +// Register Declarations for Microchip 16C711 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C711_H +#define P16C711_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define ADCON0_ADDR 0x0008 +#define ADRES_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PCON_ADDR 0x0087 +#define ADCON1_ADDR 0x0088 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C711.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C711 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C711 +// 2. LIST directive in the source file +// LIST P=PIC16C711 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 04/10/96 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C711 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (ADCON0_ADDR) ADCON0; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'CF' +// __BADRAM H'07', H'50'-H'7F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ON 0x004F +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char ADIF:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define ADIF ADCON0_bits.ADIF +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char ADIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define ADIE INTCON_bits.ADIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +#endif diff --git a/device/include/pic/pic16c715.h b/device/include/pic/pic16c715.h new file mode 100644 index 00000000..4fd7ad9e --- /dev/null +++ b/device/include/pic/pic16c715.h @@ -0,0 +1,397 @@ +// +// Register Declarations for Microchip 16C715 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C715_H +#define P16C715_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C715.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C715 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C715 +// 2. LIST directive in the source file +// LIST P=PIC16C715 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.01 05/12/97 Added values for Parity Enable configuration bits +//1.00 04/11/96 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C715 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'07'-H'09', H'0D'-H'1D' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E', H'C0'-H'EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _MPEEN_ON 0x3FFF +#define _MPEEN_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_50 0x15DF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char NOT_MPE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define NOT_MPE PCON_bits.NOT_MPE + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define ADIE PIE1_bits.ADIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define ADIF PIR1_bits.ADIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +#endif diff --git a/device/include/pic/pic16c717.h b/device/include/pic/pic16c717.h new file mode 100644 index 00000000..35cb95de --- /dev/null +++ b/device/include/pic/pic16c717.h @@ -0,0 +1,846 @@ +// +// Register Declarations for Microchip 16C717 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C717_H +#define P16C717_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPUB_ADDR 0x0095 +#define IOCB_ADDR 0x0096 +#define P1DEL_ADDR 0x0097 +#define REFCON_ADDR 0x009B +#define LVDCON_ADDR 0x009C +#define ANSEL_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define PMDATL_ADDR 0x010C +#define PMADRL_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap P1DEL_ADDR P1DEL_ADDR SFR 0x000 // P1DEL +#pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL +#pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16C717.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C717 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C717 +// 2. LIST directive in the source file +// LIST P=PIC16C717 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 14Sep1999 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C717 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (IOCB_ADDR) IOCB; +extern sfr __at (P1DEL_ADDR) P1DEL; +extern sfr __at (REFCON_ADDR) REFCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATL_ADDR) PMDATL; +extern sfr __at (PMADRL_ADDR) PMADRL; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- REFCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'07'-H'09', H'18'-H'1D' +// __BADRAM H'87'-H'89' +// __BADRAM H'8F'-H'90', H'98'-H'9A' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x0CFF +#define _CP_OFF 0x3FFF +#define _VBOR_25 0x3FFF +#define _VBOR_27 0x3BFF +#define _VBOR_42 0x37FF +#define _VBOR_45 0x33FF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _MCLRE_OFF 0x3FDF +#define _MCLRE_ON 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _ER_OSC_CLKOUT 0x3FFF +#define _ER_OSC_NOCLKOUT 0x3FFE +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _EXTCLK_OSC 0x3FFB +#define _HS_OSC 0x3FFA +#define _XT_OSC 0x3FF9 +#define _LP_OSC 0x3FF8 + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char VCFG2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 +#define VCFG2 ADCON1_bits.VCFG2 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char PWM1M0:1; + unsigned char PWM1M1:1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 +#define PWM1M0 CCP1CON_bits.PWM1M0 +#define PWM1M1 CCP1CON_bits.PWM1M1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LV0:1; + unsigned char LV1:1; + unsigned char LV2:1; + unsigned char LV3:1; + unsigned char LVDEN:1; + unsigned char BGST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LV0 LVDCON_bits.LV0 +#define LV1 LVDCON_bits.LV1 +#define LV2 LVDCON_bits.LV2 +#define LV3 LVDCON_bits.LV3 +#define LVDEN LVDCON_bits.LVDEN +#define BGST LVDCON_bits.BGST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define BCLIE PIE2_bits.BCLIE +#define LVDIE PIE2_bits.LVDIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define BCLIF PIR2_bits.BCLIF +#define LVDIF PIR2_bits.LVDIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- REFCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VRLOEN:1; + unsigned char VRHOEN:1; + unsigned char VRLEN:1; + unsigned char VRHEN:1; + }; +} __REFCON_bits_t; +extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; + +#define VRLOEN REFCON_bits.VRLOEN +#define VRHOEN REFCON_bits.VRHOEN +#define VRLEN REFCON_bits.VRLEN +#define VRHEN REFCON_bits.VRHEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +#endif diff --git a/device/include/pic/pic16c72.h b/device/include/pic/pic16c72.h new file mode 100644 index 00000000..1acff688 --- /dev/null +++ b/device/include/pic/pic16c72.h @@ -0,0 +1,639 @@ +// +// Register Declarations for Microchip 16C72 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C72_H +#define P16C72_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C72.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C72 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C72 +// 2. LIST directive in the source file +// LIST P=PIC16C72 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.01 11/28/95 Added NOT_BOR to match revised datasheet +//1.00 10/31/95 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C72 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'BF' +// __BADRAM H'08'-H'09', H'0D', H'18'-H'1D' +// __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char T1INSYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +#endif diff --git a/device/include/pic/pic16c73b.h b/device/include/pic/pic16c73b.h new file mode 100644 index 00000000..e62928be --- /dev/null +++ b/device/include/pic/pic16c73b.h @@ -0,0 +1,859 @@ +// +// Register Declarations for Microchip 16C73B Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C73B_H +#define P16C73B_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C73B.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C73B microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C73B +// 2. LIST directive in the source file +// LIST P=PIC16C73B +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 17/12/97 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C73B +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'08'-H'09' +// __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16c745.h b/device/include/pic/pic16c745.h new file mode 100644 index 00000000..9190e96f --- /dev/null +++ b/device/include/pic/pic16c745.h @@ -0,0 +1,974 @@ +// +// Register Declarations for Microchip 16C745 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C745_H +#define P16C745_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON1_ADDR 0x009F +#define UIR_ADDR 0x0190 +#define UIE_ADDR 0x0191 +#define UEIR_ADDR 0x0192 +#define UEIE_ADDR 0x0193 +#define USTAT_ADDR 0x0194 +#define UCTRL_ADDR 0x0195 +#define UADDR_ADDR 0x0196 +#define USWSTAT_ADDR 0x0197 +#define UEP0_ADDR 0x0198 +#define UEP1_ADDR 0x0199 +#define UEP2_ADDR 0x019A +#define BD0OST_ADDR 0x01A0 +#define BD0OBC_ADDR 0x01A1 +#define BD0OAL_ADDR 0x01A2 +#define BD0IST_ADDR 0x01A4 +#define BD0IBC_ADDR 0x01A5 +#define BD0IAL_ADDR 0x01A6 +#define BD1OST_ADDR 0x01A8 +#define BD1OBC_ADDR 0x01A9 +#define BD1OAL_ADDR 0x01AA +#define BD1IST_ADDR 0x01AC +#define BD1IBC_ADDR 0x01AD +#define BD1IAL_ADDR 0x01AE +#define BD2OST_ADDR 0x01B0 +#define BD2OBC_ADDR 0x01B1 +#define BD2OAL_ADDR 0x01B2 +#define BD2IST_ADDR 0x01B4 +#define BD2IBC_ADDR 0x01B5 +#define BD2IAL_ADDR 0x01B6 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap UIR_ADDR UIR_ADDR SFR 0x000 // UIR +#pragma memmap UIE_ADDR UIE_ADDR SFR 0x000 // UIE +#pragma memmap UEIR_ADDR UEIR_ADDR SFR 0x000 // UEIR +#pragma memmap UEIE_ADDR UEIE_ADDR SFR 0x000 // UEIE +#pragma memmap USTAT_ADDR USTAT_ADDR SFR 0x000 // USTAT +#pragma memmap UCTRL_ADDR UCTRL_ADDR SFR 0x000 // UCTRL +#pragma memmap UADDR_ADDR UADDR_ADDR SFR 0x000 // UADDR +#pragma memmap USWSTAT_ADDR USWSTAT_ADDR SFR 0x000 // USWSTAT +#pragma memmap UEP0_ADDR UEP0_ADDR SFR 0x000 // UEP0 +#pragma memmap UEP1_ADDR UEP1_ADDR SFR 0x000 // UEP1 +#pragma memmap UEP2_ADDR UEP2_ADDR SFR 0x000 // UEP2 +#pragma memmap BD0OST_ADDR BD0OST_ADDR SFR 0x000 // BD0OST +#pragma memmap BD0OBC_ADDR BD0OBC_ADDR SFR 0x000 // BD0OBC +#pragma memmap BD0OAL_ADDR BD0OAL_ADDR SFR 0x000 // BD0OAL +#pragma memmap BD0IST_ADDR BD0IST_ADDR SFR 0x000 // BD0IST +#pragma memmap BD0IBC_ADDR BD0IBC_ADDR SFR 0x000 // BD0IBC +#pragma memmap BD0IAL_ADDR BD0IAL_ADDR SFR 0x000 // BD0IAL +#pragma memmap BD1OST_ADDR BD1OST_ADDR SFR 0x000 // BD1OST +#pragma memmap BD1OBC_ADDR BD1OBC_ADDR SFR 0x000 // BD1OBC +#pragma memmap BD1OAL_ADDR BD1OAL_ADDR SFR 0x000 // BD1OAL +#pragma memmap BD1IST_ADDR BD1IST_ADDR SFR 0x000 // BD1IST +#pragma memmap BD1IBC_ADDR BD1IBC_ADDR SFR 0x000 // BD1IBC +#pragma memmap BD1IAL_ADDR BD1IAL_ADDR SFR 0x000 // BD1IAL +#pragma memmap BD2OST_ADDR BD2OST_ADDR SFR 0x000 // BD2OST +#pragma memmap BD2OBC_ADDR BD2OBC_ADDR SFR 0x000 // BD2OBC +#pragma memmap BD2OAL_ADDR BD2OAL_ADDR SFR 0x000 // BD2OAL +#pragma memmap BD2IST_ADDR BD2IST_ADDR SFR 0x000 // BD2IST +#pragma memmap BD2IBC_ADDR BD2IBC_ADDR SFR 0x000 // BD2IBC +#pragma memmap BD2IAL_ADDR BD2IAL_ADDR SFR 0x000 // BD2IAL + + +// LIST +// P16C745.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C745 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C745 +// 2. LIST directive in the source file +// LIST P=PIC16C745 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 28 Sep 99 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C745 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON1_ADDR) ADCON1; +extern sfr __at (UIR_ADDR) UIR; +extern sfr __at (UIE_ADDR) UIE; +extern sfr __at (UEIR_ADDR) UEIR; +extern sfr __at (UEIE_ADDR) UEIE; +extern sfr __at (USTAT_ADDR) USTAT; +extern sfr __at (UCTRL_ADDR) UCTRL; +extern sfr __at (UADDR_ADDR) UADDR; +extern sfr __at (USWSTAT_ADDR) USWSTAT; +extern sfr __at (UEP0_ADDR) UEP0; +extern sfr __at (UEP1_ADDR) UEP1; +extern sfr __at (UEP2_ADDR) UEP2; + +extern sfr __at (BD0OST_ADDR) BD0OST; +extern sfr __at (BD0OBC_ADDR) BD0OBC; +extern sfr __at (BD0OAL_ADDR) BD0OAL; +extern sfr __at (BD0IST_ADDR) BD0IST; +extern sfr __at (BD0IBC_ADDR) BD0IBC; +extern sfr __at (BD0IAL_ADDR) BD0IAL; + +extern sfr __at (BD1OST_ADDR) BD1OST; +extern sfr __at (BD1OBC_ADDR) BD1OBC; +extern sfr __at (BD1OAL_ADDR) BD1OAL; +extern sfr __at (BD1IST_ADDR) BD1IST; +extern sfr __at (BD1IBC_ADDR) BD1IBC; +extern sfr __at (BD1IAL_ADDR) BD1IAL; + +extern sfr __at (BD2OST_ADDR) BD2OST; +extern sfr __at (BD2OBC_ADDR) BD2OBC; +extern sfr __at (BD2OAL_ADDR) BD2OAL; +extern sfr __at (BD2IST_ADDR) BD2IST; +extern sfr __at (BD2IBC_ADDR) BD2IBC; +extern sfr __at (BD2IAL_ADDR) BD2IAL; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- UIR/UIE Bits ----------------------------------------------------- + + +//----- UEIR/UEIE Bits ----------------------------------------------------- + + +//----- USTAT Bits --------------------------------------------------------- + + +//----- UCTRL Bits --------------------------------------------------------- + +//----- UEP0/UEP1/UEP2 Bits ------------------------------------------------ + + +//----- Buffer descriptor Bits --------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'01FF' +// __BADRAM H'8', H'9', H'13', H'14', H'88', H'89', H'8F'-H'91' +// __BADRAM H'93'-H'97', H'9A'-H'9E' +// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18C'-H'18F', H'19B'-H'19F' +// __BADRAM H'1E0'-H'1EF' +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _HS_OSC 0x3FFC +#define _EC_OSC 0x3FFD +#define _H4_OSC 0x3FFE +#define _E4_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char DC2B0:1; + unsigned char DC2B1:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define DC2B0 CCP2CON_bits.DC2B0 +#define DC2B1 CCP2CON_bits.DC2B1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char USBIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define USBIE PIE1_bits.USBIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char USBIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define USBIF PIR1_bits.USBIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- UCTRL bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char SUSPND:1; + unsigned char RESUME:1; + unsigned char DEV_ATT:1; + unsigned char PKT_DIS:1; + unsigned char SE0:1; + unsigned char :1; + unsigned char :1; + }; +} __UCTRL_bits_t; +extern volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits; + +#define SUSPND UCTRL_bits.SUSPND +#define RESUME UCTRL_bits.RESUME +#define DEV_ATT UCTRL_bits.DEV_ATT +#define PKT_DIS UCTRL_bits.PKT_DIS +#define SE0 UCTRL_bits.SE0 + +// ----- UEIE bits -------------------- +typedef union { + struct { + unsigned char PID_ERR:1; + unsigned char CRC5:1; + unsigned char CRC16:1; + unsigned char DFN8:1; + unsigned char BTO_ERR:1; + unsigned char WRT_ERR:1; + unsigned char OWN_ERR:1; + unsigned char BTS_ERR:1; + }; +} __UEIE_bits_t; +extern volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits; + +#define PID_ERR UEIE_bits.PID_ERR +#define CRC5 UEIE_bits.CRC5 +#define CRC16 UEIE_bits.CRC16 +#define DFN8 UEIE_bits.DFN8 +#define BTO_ERR UEIE_bits.BTO_ERR +#define WRT_ERR UEIE_bits.WRT_ERR +#define OWN_ERR UEIE_bits.OWN_ERR +#define BTS_ERR UEIE_bits.BTS_ERR + +// ----- UEP2 bits -------------------- +typedef union { + struct { + unsigned char EP_STALL:1; + unsigned char EP_IN_EN:1; + unsigned char EP_OUT_EN:1; + unsigned char EP_CTL_DIS:1; + unsigned char PID2:1; + unsigned char PID3:1; + unsigned char DATA01:1; + unsigned char UOWN:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char BSTALL:1; + unsigned char DTS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char OWN:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char PID0:1; + unsigned char PID1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __UEP2_bits_t; +extern volatile __UEP2_bits_t __at(UEP2_ADDR) UEP2_bits; + +#define EP_STALL UEP2_bits.EP_STALL +#define EP_IN_EN UEP2_bits.EP_IN_EN +#define EP_OUT_EN UEP2_bits.EP_OUT_EN +#define BSTALL UEP2_bits.BSTALL +#define PID0 UEP2_bits.PID0 +#define EP_CTL_DIS UEP2_bits.EP_CTL_DIS +#define DTS UEP2_bits.DTS +#define PID1 UEP2_bits.PID1 +#define PID2 UEP2_bits.PID2 +#define PID3 UEP2_bits.PID3 +#define DATA01 UEP2_bits.DATA01 +#define UOWN UEP2_bits.UOWN +#define OWN UEP2_bits.OWN + +// ----- UIE bits -------------------- +typedef union { + struct { + unsigned char USB_RST:1; + unsigned char UERR:1; + unsigned char ACTIVITY:1; + unsigned char TOK_DNE:1; + unsigned char UIDLE:1; + unsigned char STALL:1; + unsigned char :1; + unsigned char :1; + }; +} __UIE_bits_t; +extern volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits; + +#define USB_RST UIE_bits.USB_RST +#define UERR UIE_bits.UERR +#define ACTIVITY UIE_bits.ACTIVITY +#define TOK_DNE UIE_bits.TOK_DNE +#define UIDLE UIE_bits.UIDLE +#define STALL UIE_bits.STALL + +// ----- USTAT bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char IN:1; + unsigned char ENDP0:1; + unsigned char ENDP1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __USTAT_bits_t; +extern volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits; + +#define IN USTAT_bits.IN +#define ENDP0 USTAT_bits.ENDP0 +#define ENDP1 USTAT_bits.ENDP1 + +#endif diff --git a/device/include/pic/pic16c74b.h b/device/include/pic/pic16c74b.h new file mode 100644 index 00000000..eb042734 --- /dev/null +++ b/device/include/pic/pic16c74b.h @@ -0,0 +1,898 @@ +// +// Register Declarations for Microchip 16C74B Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C74B_H +#define P16C74B_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C74B.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C74B microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C74B +// 2. LIST directive in the source file +// LIST P=PIC16C74B +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 12/17/97 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C74B +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16c765.h b/device/include/pic/pic16c765.h new file mode 100644 index 00000000..6774d392 --- /dev/null +++ b/device/include/pic/pic16c765.h @@ -0,0 +1,1013 @@ +// +// Register Declarations for Microchip 16C765 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C765_H +#define P16C765_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON1_ADDR 0x009F +#define UIR_ADDR 0x0190 +#define UIE_ADDR 0x0191 +#define UEIR_ADDR 0x0192 +#define UEIE_ADDR 0x0193 +#define USTAT_ADDR 0x0194 +#define UCTRL_ADDR 0x0195 +#define UADDR_ADDR 0x0196 +#define USWSTAT_ADDR 0x0197 +#define UEP0_ADDR 0x0198 +#define UEP1_ADDR 0x0199 +#define UEP2_ADDR 0x019A +#define BD0OST_ADDR 0x01A0 +#define BD0OBC_ADDR 0x01A1 +#define BD0OAL_ADDR 0x01A2 +#define BD0IST_ADDR 0x01A4 +#define BD0IBC_ADDR 0x01A5 +#define BD0IAL_ADDR 0x01A6 +#define BD1OST_ADDR 0x01A8 +#define BD1OBC_ADDR 0x01A9 +#define BD1OAL_ADDR 0x01AA +#define BD1IST_ADDR 0x01AC +#define BD1IBC_ADDR 0x01AD +#define BD1IAL_ADDR 0x01AE +#define BD2OST_ADDR 0x01B0 +#define BD2OBC_ADDR 0x01B1 +#define BD2OAL_ADDR 0x01B2 +#define BD2IST_ADDR 0x01B4 +#define BD2IBC_ADDR 0x01B5 +#define BD2IAL_ADDR 0x01B6 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap UIR_ADDR UIR_ADDR SFR 0x000 // UIR +#pragma memmap UIE_ADDR UIE_ADDR SFR 0x000 // UIE +#pragma memmap UEIR_ADDR UEIR_ADDR SFR 0x000 // UEIR +#pragma memmap UEIE_ADDR UEIE_ADDR SFR 0x000 // UEIE +#pragma memmap USTAT_ADDR USTAT_ADDR SFR 0x000 // USTAT +#pragma memmap UCTRL_ADDR UCTRL_ADDR SFR 0x000 // UCTRL +#pragma memmap UADDR_ADDR UADDR_ADDR SFR 0x000 // UADDR +#pragma memmap USWSTAT_ADDR USWSTAT_ADDR SFR 0x000 // USWSTAT +#pragma memmap UEP0_ADDR UEP0_ADDR SFR 0x000 // UEP0 +#pragma memmap UEP1_ADDR UEP1_ADDR SFR 0x000 // UEP1 +#pragma memmap UEP2_ADDR UEP2_ADDR SFR 0x000 // UEP2 +#pragma memmap BD0OST_ADDR BD0OST_ADDR SFR 0x000 // BD0OST +#pragma memmap BD0OBC_ADDR BD0OBC_ADDR SFR 0x000 // BD0OBC +#pragma memmap BD0OAL_ADDR BD0OAL_ADDR SFR 0x000 // BD0OAL +#pragma memmap BD0IST_ADDR BD0IST_ADDR SFR 0x000 // BD0IST +#pragma memmap BD0IBC_ADDR BD0IBC_ADDR SFR 0x000 // BD0IBC +#pragma memmap BD0IAL_ADDR BD0IAL_ADDR SFR 0x000 // BD0IAL +#pragma memmap BD1OST_ADDR BD1OST_ADDR SFR 0x000 // BD1OST +#pragma memmap BD1OBC_ADDR BD1OBC_ADDR SFR 0x000 // BD1OBC +#pragma memmap BD1OAL_ADDR BD1OAL_ADDR SFR 0x000 // BD1OAL +#pragma memmap BD1IST_ADDR BD1IST_ADDR SFR 0x000 // BD1IST +#pragma memmap BD1IBC_ADDR BD1IBC_ADDR SFR 0x000 // BD1IBC +#pragma memmap BD1IAL_ADDR BD1IAL_ADDR SFR 0x000 // BD1IAL +#pragma memmap BD2OST_ADDR BD2OST_ADDR SFR 0x000 // BD2OST +#pragma memmap BD2OBC_ADDR BD2OBC_ADDR SFR 0x000 // BD2OBC +#pragma memmap BD2OAL_ADDR BD2OAL_ADDR SFR 0x000 // BD2OAL +#pragma memmap BD2IST_ADDR BD2IST_ADDR SFR 0x000 // BD2IST +#pragma memmap BD2IBC_ADDR BD2IBC_ADDR SFR 0x000 // BD2IBC +#pragma memmap BD2IAL_ADDR BD2IAL_ADDR SFR 0x000 // BD2IAL + + +// LIST +// P16C765.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C765 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C765 +// 2. LIST directive in the source file +// LIST P=PIC16C765 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 28 Sep 99 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C765 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON1_ADDR) ADCON1; +extern sfr __at (UIR_ADDR) UIR; +extern sfr __at (UIE_ADDR) UIE; +extern sfr __at (UEIR_ADDR) UEIR; +extern sfr __at (UEIE_ADDR) UEIE; +extern sfr __at (USTAT_ADDR) USTAT; +extern sfr __at (UCTRL_ADDR) UCTRL; +extern sfr __at (UADDR_ADDR) UADDR; +extern sfr __at (USWSTAT_ADDR) USWSTAT; +extern sfr __at (UEP0_ADDR) UEP0; +extern sfr __at (UEP1_ADDR) UEP1; +extern sfr __at (UEP2_ADDR) UEP2; + +extern sfr __at (BD0OST_ADDR) BD0OST; +extern sfr __at (BD0OBC_ADDR) BD0OBC; +extern sfr __at (BD0OAL_ADDR) BD0OAL; +extern sfr __at (BD0IST_ADDR) BD0IST; +extern sfr __at (BD0IBC_ADDR) BD0IBC; +extern sfr __at (BD0IAL_ADDR) BD0IAL; + +extern sfr __at (BD1OST_ADDR) BD1OST; +extern sfr __at (BD1OBC_ADDR) BD1OBC; +extern sfr __at (BD1OAL_ADDR) BD1OAL; +extern sfr __at (BD1IST_ADDR) BD1IST; +extern sfr __at (BD1IBC_ADDR) BD1IBC; +extern sfr __at (BD1IAL_ADDR) BD1IAL; + +extern sfr __at (BD2OST_ADDR) BD2OST; +extern sfr __at (BD2OBC_ADDR) BD2OBC; +extern sfr __at (BD2OAL_ADDR) BD2OAL; +extern sfr __at (BD2IST_ADDR) BD2IST; +extern sfr __at (BD2IBC_ADDR) BD2IBC; +extern sfr __at (BD2IAL_ADDR) BD2IAL; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- UIR/UIE Bits ----------------------------------------------------- + + +//----- UEIR/UEIE Bits ----------------------------------------------------- + + +//----- USTAT Bits --------------------------------------------------------- + + +//----- UCTRL Bits --------------------------------------------------------- + +//----- UEP0/UEP1/UEP2 Bits ------------------------------------------------ + + +//----- Buffer descriptor Bits --------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'01FF' +// __BADRAM H'13', H'14', H'8F'-H'91' +// __BADRAM H'93'-H'97', H'9A'-H'9E' +// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18C'-H'18F', H'19B'-H'19F' +// __BADRAM H'1E0'-H'1EF' +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x00CF +#define _CP_75 0x15DF +#define _CP_50 0x2AEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _HS_OSC 0x3FFC +#define _EC_OSC 0x3FFD +#define _H4_OSC 0x3FFE +#define _E4_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char DC2B0:1; + unsigned char DC2B1:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define DC2B0 CCP2CON_bits.DC2B0 +#define DC2B1 CCP2CON_bits.DC2B1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char USBIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define USBIE PIE1_bits.USBIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char USBIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define USBIF PIR1_bits.USBIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- UCTRL bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char SUSPND:1; + unsigned char RESUME:1; + unsigned char DEV_ATT:1; + unsigned char PKT_DIS:1; + unsigned char SE0:1; + unsigned char :1; + unsigned char :1; + }; +} __UCTRL_bits_t; +extern volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits; + +#define SUSPND UCTRL_bits.SUSPND +#define RESUME UCTRL_bits.RESUME +#define DEV_ATT UCTRL_bits.DEV_ATT +#define PKT_DIS UCTRL_bits.PKT_DIS +#define SE0 UCTRL_bits.SE0 + +// ----- UEIE bits -------------------- +typedef union { + struct { + unsigned char PID_ERR:1; + unsigned char CRC5:1; + unsigned char CRC16:1; + unsigned char DFN8:1; + unsigned char BTO_ERR:1; + unsigned char WRT_ERR:1; + unsigned char OWN_ERR:1; + unsigned char BTS_ERR:1; + }; +} __UEIE_bits_t; +extern volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits; + +#define PID_ERR UEIE_bits.PID_ERR +#define CRC5 UEIE_bits.CRC5 +#define CRC16 UEIE_bits.CRC16 +#define DFN8 UEIE_bits.DFN8 +#define BTO_ERR UEIE_bits.BTO_ERR +#define WRT_ERR UEIE_bits.WRT_ERR +#define OWN_ERR UEIE_bits.OWN_ERR +#define BTS_ERR UEIE_bits.BTS_ERR + +// ----- UEP2 bits -------------------- +typedef union { + struct { + unsigned char EP_STALL:1; + unsigned char EP_IN_EN:1; + unsigned char EP_OUT_EN:1; + unsigned char EP_CTL_DIS:1; + unsigned char PID2:1; + unsigned char PID3:1; + unsigned char DATA01:1; + unsigned char UOWN:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char BSTALL:1; + unsigned char DTS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char OWN:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char PID0:1; + unsigned char PID1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __UEP2_bits_t; +extern volatile __UEP2_bits_t __at(UEP2_ADDR) UEP2_bits; + +#define EP_STALL UEP2_bits.EP_STALL +#define EP_IN_EN UEP2_bits.EP_IN_EN +#define EP_OUT_EN UEP2_bits.EP_OUT_EN +#define BSTALL UEP2_bits.BSTALL +#define PID0 UEP2_bits.PID0 +#define EP_CTL_DIS UEP2_bits.EP_CTL_DIS +#define DTS UEP2_bits.DTS +#define PID1 UEP2_bits.PID1 +#define PID2 UEP2_bits.PID2 +#define PID3 UEP2_bits.PID3 +#define DATA01 UEP2_bits.DATA01 +#define UOWN UEP2_bits.UOWN +#define OWN UEP2_bits.OWN + +// ----- UIE bits -------------------- +typedef union { + struct { + unsigned char USB_RST:1; + unsigned char UERR:1; + unsigned char ACTIVITY:1; + unsigned char TOK_DNE:1; + unsigned char UIDLE:1; + unsigned char STALL:1; + unsigned char :1; + unsigned char :1; + }; +} __UIE_bits_t; +extern volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits; + +#define USB_RST UIE_bits.USB_RST +#define UERR UIE_bits.UERR +#define ACTIVITY UIE_bits.ACTIVITY +#define TOK_DNE UIE_bits.TOK_DNE +#define UIDLE UIE_bits.UIDLE +#define STALL UIE_bits.STALL + +// ----- USTAT bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char IN:1; + unsigned char ENDP0:1; + unsigned char ENDP1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __USTAT_bits_t; +extern volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits; + +#define IN USTAT_bits.IN +#define ENDP0 USTAT_bits.ENDP0 +#define ENDP1 USTAT_bits.ENDP1 + +#endif diff --git a/device/include/pic/pic16c770.h b/device/include/pic/pic16c770.h new file mode 100644 index 00000000..eca09073 --- /dev/null +++ b/device/include/pic/pic16c770.h @@ -0,0 +1,846 @@ +// +// Register Declarations for Microchip 16C770 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C770_H +#define P16C770_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPUB_ADDR 0x0095 +#define IOCB_ADDR 0x0096 +#define P1DEL_ADDR 0x0097 +#define REFCON_ADDR 0x009B +#define LVDCON_ADDR 0x009C +#define ANSEL_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define PMDATL_ADDR 0x010C +#define PMADRL_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap P1DEL_ADDR P1DEL_ADDR SFR 0x000 // P1DEL +#pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL +#pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16C770.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C770 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C770 +// 2. LIST directive in the source file +// LIST P=PIC16C770 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 14Sep1999 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C770 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (IOCB_ADDR) IOCB; +extern sfr __at (P1DEL_ADDR) P1DEL; +extern sfr __at (REFCON_ADDR) REFCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATL_ADDR) PMDATL; +extern sfr __at (PMADRL_ADDR) PMADRL; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- REFCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'07'-H'09', H'18'-H'1D' +// __BADRAM H'87'-H'89' +// __BADRAM H'8F'-H'90', H'98'-H'9A' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x0CFF +#define _CP_OFF 0x3FFF +#define _VBOR_25 0x3FFF +#define _VBOR_27 0x3BFF +#define _VBOR_42 0x37FF +#define _VBOR_45 0x33FF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _MCLRE_OFF 0x3FDF +#define _MCLRE_ON 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _ER_OSC_CLKOUT 0x3FFF +#define _ER_OSC_NOCLKOUT 0x3FFE +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _EXTCLK_OSC 0x3FFB +#define _HS_OSC 0x3FFA +#define _XT_OSC 0x3FF9 +#define _LP_OSC 0x3FF8 + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char VCFG2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 +#define VCFG2 ADCON1_bits.VCFG2 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char PWM1M0:1; + unsigned char PWM1M1:1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 +#define PWM1M0 CCP1CON_bits.PWM1M0 +#define PWM1M1 CCP1CON_bits.PWM1M1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LV0:1; + unsigned char LV1:1; + unsigned char LV2:1; + unsigned char LV3:1; + unsigned char LVDEN:1; + unsigned char BGST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LV0 LVDCON_bits.LV0 +#define LV1 LVDCON_bits.LV1 +#define LV2 LVDCON_bits.LV2 +#define LV3 LVDCON_bits.LV3 +#define LVDEN LVDCON_bits.LVDEN +#define BGST LVDCON_bits.BGST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define BCLIE PIE2_bits.BCLIE +#define LVDIE PIE2_bits.LVDIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define BCLIF PIR2_bits.BCLIF +#define LVDIF PIR2_bits.LVDIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- REFCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VRLOEN:1; + unsigned char VRHOEN:1; + unsigned char VRLEN:1; + unsigned char VRHEN:1; + }; +} __REFCON_bits_t; +extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; + +#define VRLOEN REFCON_bits.VRLOEN +#define VRHOEN REFCON_bits.VRHOEN +#define VRLEN REFCON_bits.VRLEN +#define VRHEN REFCON_bits.VRHEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +#endif diff --git a/device/include/pic/pic16c771.h b/device/include/pic/pic16c771.h new file mode 100644 index 00000000..7e2c20ae --- /dev/null +++ b/device/include/pic/pic16c771.h @@ -0,0 +1,846 @@ +// +// Register Declarations for Microchip 16C771 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C771_H +#define P16C771_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPUB_ADDR 0x0095 +#define IOCB_ADDR 0x0096 +#define P1DEL_ADDR 0x0097 +#define REFCON_ADDR 0x009B +#define LVDCON_ADDR 0x009C +#define ANSEL_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define PMDATL_ADDR 0x010C +#define PMADRL_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap P1DEL_ADDR P1DEL_ADDR SFR 0x000 // P1DEL +#pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL +#pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16C771.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C771 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C771 +// 2. LIST directive in the source file +// LIST P=PIC16C771 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 14Sep1999 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C771 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (IOCB_ADDR) IOCB; +extern sfr __at (P1DEL_ADDR) P1DEL; +extern sfr __at (REFCON_ADDR) REFCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATL_ADDR) PMDATL; +extern sfr __at (PMADRL_ADDR) PMADRL; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- REFCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'07'-H'09', H'18'-H'1D' +// __BADRAM H'87'-H'89' +// __BADRAM H'8F'-H'90', H'98'-H'9A' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x0CFF +#define _CP_OFF 0x3FFF +#define _VBOR_25 0x3FFF +#define _VBOR_27 0x3BFF +#define _VBOR_42 0x37FF +#define _VBOR_45 0x33FF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _MCLRE_OFF 0x3FDF +#define _MCLRE_ON 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _ER_OSC_CLKOUT 0x3FFF +#define _ER_OSC_NOCLKOUT 0x3FFE +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _EXTCLK_OSC 0x3FFB +#define _HS_OSC 0x3FFA +#define _XT_OSC 0x3FF9 +#define _LP_OSC 0x3FF8 + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char VCFG2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 +#define VCFG2 ADCON1_bits.VCFG2 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char PWM1M0:1; + unsigned char PWM1M1:1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 +#define PWM1M0 CCP1CON_bits.PWM1M0 +#define PWM1M1 CCP1CON_bits.PWM1M1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LV0:1; + unsigned char LV1:1; + unsigned char LV2:1; + unsigned char LV3:1; + unsigned char LVDEN:1; + unsigned char BGST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LV0 LVDCON_bits.LV0 +#define LV1 LVDCON_bits.LV1 +#define LV2 LVDCON_bits.LV2 +#define LV3 LVDCON_bits.LV3 +#define LVDEN LVDCON_bits.LVDEN +#define BGST LVDCON_bits.BGST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define BCLIE PIE2_bits.BCLIE +#define LVDIE PIE2_bits.LVDIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define BCLIF PIR2_bits.BCLIF +#define LVDIF PIR2_bits.LVDIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- REFCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VRLOEN:1; + unsigned char VRHOEN:1; + unsigned char VRLEN:1; + unsigned char VRHEN:1; + }; +} __REFCON_bits_t; +extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; + +#define VRLOEN REFCON_bits.VRLOEN +#define VRHOEN REFCON_bits.VRHOEN +#define VRLEN REFCON_bits.VRLEN +#define VRHEN REFCON_bits.VRHEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +#endif diff --git a/device/include/pic/pic16c773.h b/device/include/pic/pic16c773.h new file mode 100644 index 00000000..8fd02333 --- /dev/null +++ b/device/include/pic/pic16c773.h @@ -0,0 +1,975 @@ +// +// Register Declarations for Microchip 16C773 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C773_H +#define P16C773_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define REFCON_ADDR 0x009B +#define LVDCON_ADDR 0x009C +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C773.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C773 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C773 +// 2. LIST directive in the source file +// LIST P=PIC16C773 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 08/07/98 Initial Release +//1.01 25Jan99 Fixed LVVx bits + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C773 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (REFCON_ADDR) REFCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- REFCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09' +// __BADRAM H'88'-H'89', H'8F'-H'90', H'95'-H'97', H'9A', H'9D' +// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x0CCF +#define _CP_75 0x1DDF +#define _CP_50 0x2EEF +#define _CP_OFF 0x3FFF +#define _VBOR_25 0x3FFF +#define _VBOR_27 0x3BFF +#define _VBOR_42 0x37FF +#define _VBOR_45 0x33FF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char VCFG2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 +#define VCFG2 ADCON1_bits.VCFG2 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LV0:1; + unsigned char LV1:1; + unsigned char LV2:1; + unsigned char LV3:1; + unsigned char LVDEN:1; + unsigned char BGST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LV0 LVDCON_bits.LV0 +#define LV1 LVDCON_bits.LV1 +#define LV2 LVDCON_bits.LV2 +#define LV3 LVDCON_bits.LV3 +#define LVDEN LVDCON_bits.LVDEN +#define BGST LVDCON_bits.BGST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define LVDIE PIE2_bits.LVDIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define LVDIF PIR2_bits.LVDIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- REFCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VRLOEN:1; + unsigned char VRHOEN:1; + unsigned char VRLEN:1; + unsigned char VRHEN:1; + }; +} __REFCON_bits_t; +extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; + +#define VRLOEN REFCON_bits.VRLOEN +#define VRHOEN REFCON_bits.VRHOEN +#define VRLEN REFCON_bits.VRLEN +#define VRHEN REFCON_bits.VRHEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16c774.h b/device/include/pic/pic16c774.h new file mode 100644 index 00000000..8af3ef06 --- /dev/null +++ b/device/include/pic/pic16c774.h @@ -0,0 +1,1012 @@ +// +// Register Declarations for Microchip 16C774 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C774_H +#define P16C774_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define REFCON_ADDR 0x009B +#define LVDCON_ADDR 0x009C +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16C774.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C774 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C774 +// 2. LIST directive in the source file +// LIST P=PIC16C774 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 08/07/98 Initial Release +//1.01 25Jan99 Fixed LVVx bits + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C774 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (REFCON_ADDR) REFCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- REFCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A', H'9D' +// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x0CCF +#define _CP_75 0x1DDF +#define _CP_50 0x2EEF +#define _CP_OFF 0x3FFF +#define _VBOR_25 0x3FFF +#define _VBOR_27 0x3BFF +#define _VBOR_42 0x37FF +#define _VBOR_45 0x33FF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char VCFG2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 +#define VCFG2 ADCON1_bits.VCFG2 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LV0:1; + unsigned char LV1:1; + unsigned char LV2:1; + unsigned char LV3:1; + unsigned char LVDEN:1; + unsigned char BGST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LV0 LVDCON_bits.LV0 +#define LV1 LVDCON_bits.LV1 +#define LV2 LVDCON_bits.LV2 +#define LV3 LVDCON_bits.LV3 +#define LVDEN LVDCON_bits.LVDEN +#define BGST LVDCON_bits.BGST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define LVDIE PIE2_bits.LVDIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char LVDIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define LVDIF PIR2_bits.LVDIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- REFCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VRLOEN:1; + unsigned char VRHOEN:1; + unsigned char VRLEN:1; + unsigned char VRHEN:1; + }; +} __REFCON_bits_t; +extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; + +#define VRLOEN REFCON_bits.VRLOEN +#define VRHOEN REFCON_bits.VRHOEN +#define VRLEN REFCON_bits.VRLEN +#define VRHEN REFCON_bits.VRHEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16c781.h b/device/include/pic/pic16c781.h new file mode 100644 index 00000000..ebf98c27 --- /dev/null +++ b/device/include/pic/pic16c781.h @@ -0,0 +1,806 @@ +// +// Register Declarations for Microchip 16C781 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C781_H +#define P16C781_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define WPUB_ADDR 0x0095 +#define IOCB_ADDR 0x0096 +#define REFCON_ADDR 0x009B +#define LVDCON_ADDR 0x009C +#define ANSEL_ADDR 0x009D +#define ADCON1_ADDR 0x009F +#define PMDATL_ADDR 0x010C +#define PMADRL_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define CALCON_ADDR 0x0110 +#define PSMCCON0_ADDR 0x0111 +#define PSMCCON1_ADDR 0x0112 +#define CM1CON0_ADDR 0x0119 +#define CM2CON0_ADDR 0x011A +#define CM2CON1_ADDR 0x011B +#define OPACON_ADDR 0x011C +#define DAC_ADDR 0x011E +#define DACON0_ADDR 0x011F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL +#pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap CALCON_ADDR CALCON_ADDR SFR 0x000 // CALCON +#pragma memmap PSMCCON0_ADDR PSMCCON0_ADDR SFR 0x000 // PSMCCON0 +#pragma memmap PSMCCON1_ADDR PSMCCON1_ADDR SFR 0x000 // PSMCCON1 +#pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0 +#pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0 +#pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1 +#pragma memmap OPACON_ADDR OPACON_ADDR SFR 0x000 // OPACON +#pragma memmap DAC_ADDR DAC_ADDR SFR 0x000 // DAC +#pragma memmap DACON0_ADDR DACON0_ADDR SFR 0x000 // DACON0 +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16C782.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C782 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C782 +// 2. LIST directive in the source file +// LIST P=PIC16C782 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 16May2001 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C781 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (IOCB_ADDR) IOCB; +extern sfr __at (REFCON_ADDR) REFCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATL_ADDR) PMDATL; +extern sfr __at (PMADRL_ADDR) PMADRL; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; +extern sfr __at (CALCON_ADDR) CALCON; +extern sfr __at (PSMCCON0_ADDR) PSMCCON0; +extern sfr __at (PSMCCON1_ADDR) PSMCCON1; +extern sfr __at (CM1CON0_ADDR) CM1CON0; +extern sfr __at (CM2CON0_ADDR) CM2CON0; +extern sfr __at (CM2CON1_ADDR) CM2CON1; +extern sfr __at (OPACON_ADDR) OPACON; +extern sfr __at (DAC_ADDR) DAC; +extern sfr __at (DACON0_ADDR) DACON0; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- REFCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- CALCON Bits -------------------------------------------------------- + + +//----- PSMCCON0 Bits ------------------------------------------------------ + + +//----- PSMCCON1 Bits ------------------------------------------------------ + + +//----- CM1CON0 Bits ------------------------------------------------------ + + +//----- CM2CON0 Bits ------------------------------------------------------ + + +//----- CM2CON1 Bits ------------------------------------------------------ + + +//----- OPACON Bits ------------------------------------------------------- + + +//----- DACON0 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits ------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'07'-H'09', H'0D', H'11'-H'1D' +// __BADRAM H'87'-H'89', H'8D' +// __BADRAM H'8F'-H'94', H'97'-H'9A', H'9E', H'C0'-H'EF' +// __BADRAM H'105', H'107'-H'109', H'113'-H'118' +// __BADRAM H'11D', H'120'-H'16F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x0CFF +#define _CP_OFF 0x3FFF +#define _VBOR_25 0x3FFF +#define _VBOR_27 0x3BFF +#define _VBOR_42 0x37FF +#define _VBOR_45 0x33FF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _MCLRE_OFF 0x3FDF +#define _MCLRE_ON 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _ER_OSC_CLKOUT 0x3FFF +#define _ER_OSC_NOCLKOUT 0x3FFE +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _EXTCLK_OSC 0x3FFB +#define _HS_OSC 0x3FFA +#define _XT_OSC 0x3FF9 +#define _LP_OSC 0x3FF8 + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 + +// ----- CALCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CALREF:1; + unsigned char CALERR:1; + unsigned char CAL:1; + }; +} __CALCON_bits_t; +extern volatile __CALCON_bits_t __at(CALCON_ADDR) CALCON_bits; + +#define CALREF CALCON_bits.CALREF +#define CALERR CALCON_bits.CALERR +#define CAL CALCON_bits.CAL + +// ----- CM1CON0 bits -------------------- +typedef union { + struct { + unsigned char C1CH0:1; + unsigned char C1CH1:1; + unsigned char C1R:1; + unsigned char C1SP:1; + unsigned char C1POL:1; + unsigned char C1OE:1; + unsigned char C1OUT:1; + unsigned char C1ON:1; + }; +} __CM1CON0_bits_t; +extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; + +#define C1CH0 CM1CON0_bits.C1CH0 +#define C1CH1 CM1CON0_bits.C1CH1 +#define C1R CM1CON0_bits.C1R +#define C1SP CM1CON0_bits.C1SP +#define C1POL CM1CON0_bits.C1POL +#define C1OE CM1CON0_bits.C1OE +#define C1OUT CM1CON0_bits.C1OUT +#define C1ON CM1CON0_bits.C1ON + +// ----- CM2CON0 bits -------------------- +typedef union { + struct { + unsigned char C2CH0:1; + unsigned char C2CH1:1; + unsigned char C2R:1; + unsigned char C2SP:1; + unsigned char C2POL:1; + unsigned char C2OE:1; + unsigned char C2OUT:1; + unsigned char C2ON:1; + }; +} __CM2CON0_bits_t; +extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; + +#define C2CH0 CM2CON0_bits.C2CH0 +#define C2CH1 CM2CON0_bits.C2CH1 +#define C2R CM2CON0_bits.C2R +#define C2SP CM2CON0_bits.C2SP +#define C2POL CM2CON0_bits.C2POL +#define C2OE CM2CON0_bits.C2OE +#define C2OUT CM2CON0_bits.C2OUT +#define C2ON CM2CON0_bits.C2ON + +// ----- CM2CON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char MC2OUT:1; + unsigned char MC1OUT:1; + }; +} __CM2CON1_bits_t; +extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; + +#define C2SYNC CM2CON1_bits.C2SYNC +#define MC2OUT CM2CON1_bits.MC2OUT +#define MC1OUT CM2CON1_bits.MC1OUT + +// ----- DACON0 bits -------------------- +typedef union { + struct { + unsigned char DARS0:1; + unsigned char DARS1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char DAOE:1; + unsigned char DAON:1; + }; +} __DACON0_bits_t; +extern volatile __DACON0_bits_t __at(DACON0_ADDR) DACON0_bits; + +#define DARS0 DACON0_bits.DARS0 +#define DARS1 DACON0_bits.DARS1 +#define DAOE DACON0_bits.DAOE +#define DAON DACON0_bits.DAON + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LV0:1; + unsigned char LV1:1; + unsigned char LV2:1; + unsigned char LV3:1; + unsigned char LVDEN:1; + unsigned char BGST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LV0 LVDCON_bits.LV0 +#define LV1 LVDCON_bits.LV1 +#define LV2 LVDCON_bits.LV2 +#define LV3 LVDCON_bits.LV3 +#define LVDEN LVDCON_bits.LVDEN +#define BGST LVDCON_bits.BGST + +// ----- OPACON bits -------------------- +typedef union { + struct { + unsigned char GBWP:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMPEN:1; + unsigned char OPAON:1; + }; +} __OPACON_bits_t; +extern volatile __OPACON_bits_t __at(OPACON_ADDR) OPACON_bits; + +#define GBWP OPACON_bits.GBWP +#define CMPEN OPACON_bits.CMPEN +#define OPAON OPACON_bits.OPAON + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char WDTON:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF +#define WDTON PCON_bits.WDTON + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char ADIE:1; + unsigned char LVDIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define C1IE PIE1_bits.C1IE +#define C2IE PIE1_bits.C2IE +#define ADIE PIE1_bits.ADIE +#define LVDIE PIE1_bits.LVDIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char ADIF:1; + unsigned char LVDIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define C1IF PIR1_bits.C1IF +#define C2IF PIR1_bits.C2IF +#define ADIF PIR1_bits.ADIF +#define LVDIF PIR1_bits.LVDIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- PSMCCON0 bits -------------------- +typedef union { + struct { + unsigned char DC0:1; + unsigned char DC1:1; + unsigned char MAXDC0:1; + unsigned char MAXDC1:1; + unsigned char MINDC0:1; + unsigned char MINDC1:1; + unsigned char SMCCL0:1; + unsigned char SMCCL1:1; + }; +} __PSMCCON0_bits_t; +extern volatile __PSMCCON0_bits_t __at(PSMCCON0_ADDR) PSMCCON0_bits; + +#define DC0 PSMCCON0_bits.DC0 +#define DC1 PSMCCON0_bits.DC1 +#define MAXDC0 PSMCCON0_bits.MAXDC0 +#define MAXDC1 PSMCCON0_bits.MAXDC1 +#define MINDC0 PSMCCON0_bits.MINDC0 +#define MINDC1 PSMCCON0_bits.MINDC1 +#define SMCCL0 PSMCCON0_bits.SMCCL0 +#define SMCCL1 PSMCCON0_bits.SMCCL1 + +// ----- PSMCCON1 bits -------------------- +typedef union { + struct { + unsigned char SMCCS:1; + unsigned char PWM:1; + unsigned char SMCOM:1; + unsigned char SCEN:1; + unsigned char :1; + unsigned char S1BPOL:1; + unsigned char S1APOL:1; + unsigned char SMCON:1; + }; + struct { + unsigned char :1; + unsigned char PSM:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char NOT_PSM:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PSMCCON1_bits_t; +extern volatile __PSMCCON1_bits_t __at(PSMCCON1_ADDR) PSMCCON1_bits; + +#define SMCCS PSMCCON1_bits.SMCCS +#define PWM PSMCCON1_bits.PWM +#define PSM PSMCCON1_bits.PSM +#define NOT_PSM PSMCCON1_bits.NOT_PSM +#define SMCOM PSMCCON1_bits.SMCOM +#define SCEN PSMCCON1_bits.SCEN +#define S1BPOL PSMCCON1_bits.S1BPOL +#define S1APOL PSMCCON1_bits.S1APOL +#define SMCON PSMCCON1_bits.SMCON + +// ----- REFCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char VREFOE:1; + unsigned char VREFEN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __REFCON_bits_t; +extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; + +#define VREFOE REFCON_bits.VREFOE +#define VREFEN REFCON_bits.VREFEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE + +#endif diff --git a/device/include/pic/pic16c782.h b/device/include/pic/pic16c782.h new file mode 100644 index 00000000..959ce284 --- /dev/null +++ b/device/include/pic/pic16c782.h @@ -0,0 +1,806 @@ +// +// Register Declarations for Microchip 16C782 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C782_H +#define P16C782_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define WPUB_ADDR 0x0095 +#define IOCB_ADDR 0x0096 +#define REFCON_ADDR 0x009B +#define LVDCON_ADDR 0x009C +#define ANSEL_ADDR 0x009D +#define ADCON1_ADDR 0x009F +#define PMDATL_ADDR 0x010C +#define PMADRL_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define CALCON_ADDR 0x0110 +#define PSMCCON0_ADDR 0x0111 +#define PSMCCON1_ADDR 0x0112 +#define CM1CON0_ADDR 0x0119 +#define CM2CON0_ADDR 0x011A +#define CM2CON1_ADDR 0x011B +#define OPACON_ADDR 0x011C +#define DAC_ADDR 0x011E +#define DACON0_ADDR 0x011F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL +#pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap CALCON_ADDR CALCON_ADDR SFR 0x000 // CALCON +#pragma memmap PSMCCON0_ADDR PSMCCON0_ADDR SFR 0x000 // PSMCCON0 +#pragma memmap PSMCCON1_ADDR PSMCCON1_ADDR SFR 0x000 // PSMCCON1 +#pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0 +#pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0 +#pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1 +#pragma memmap OPACON_ADDR OPACON_ADDR SFR 0x000 // OPACON +#pragma memmap DAC_ADDR DAC_ADDR SFR 0x000 // DAC +#pragma memmap DACON0_ADDR DACON0_ADDR SFR 0x000 // DACON0 +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16C782.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C782 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C782 +// 2. LIST directive in the source file +// LIST P=PIC16C782 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 16May2001 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C782 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (IOCB_ADDR) IOCB; +extern sfr __at (REFCON_ADDR) REFCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATL_ADDR) PMDATL; +extern sfr __at (PMADRL_ADDR) PMADRL; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; +extern sfr __at (CALCON_ADDR) CALCON; +extern sfr __at (PSMCCON0_ADDR) PSMCCON0; +extern sfr __at (PSMCCON1_ADDR) PSMCCON1; +extern sfr __at (CM1CON0_ADDR) CM1CON0; +extern sfr __at (CM2CON0_ADDR) CM2CON0; +extern sfr __at (CM2CON1_ADDR) CM2CON1; +extern sfr __at (OPACON_ADDR) OPACON; +extern sfr __at (DAC_ADDR) DAC; +extern sfr __at (DACON0_ADDR) DACON0; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- REFCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- CALCON Bits -------------------------------------------------------- + + +//----- PSMCCON0 Bits ------------------------------------------------------ + + +//----- PSMCCON1 Bits ------------------------------------------------------ + + +//----- CM1CON0 Bits ------------------------------------------------------ + + +//----- CM2CON0 Bits ------------------------------------------------------ + + +//----- CM2CON1 Bits ------------------------------------------------------ + + +//----- OPACON Bits ------------------------------------------------------- + + +//----- DACON0 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits ------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'07'-H'09', H'0D', H'11'-H'1D' +// __BADRAM H'87'-H'89', H'8D' +// __BADRAM H'8F'-H'94', H'97'-H'9A', H'9E', H'C0'-H'EF' +// __BADRAM H'105', H'107'-H'109', H'113'-H'118' +// __BADRAM H'11D', H'120'-H'16F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x0CFF +#define _CP_OFF 0x3FFF +#define _VBOR_25 0x3FFF +#define _VBOR_27 0x3BFF +#define _VBOR_42 0x37FF +#define _VBOR_45 0x33FF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _MCLRE_OFF 0x3FDF +#define _MCLRE_ON 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _ER_OSC_CLKOUT 0x3FFF +#define _ER_OSC_NOCLKOUT 0x3FFE +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _EXTCLK_OSC 0x3FFB +#define _HS_OSC 0x3FFA +#define _XT_OSC 0x3FF9 +#define _LP_OSC 0x3FF8 + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 + +// ----- CALCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CALREF:1; + unsigned char CALERR:1; + unsigned char CAL:1; + }; +} __CALCON_bits_t; +extern volatile __CALCON_bits_t __at(CALCON_ADDR) CALCON_bits; + +#define CALREF CALCON_bits.CALREF +#define CALERR CALCON_bits.CALERR +#define CAL CALCON_bits.CAL + +// ----- CM1CON0 bits -------------------- +typedef union { + struct { + unsigned char C1CH0:1; + unsigned char C1CH1:1; + unsigned char C1R:1; + unsigned char C1SP:1; + unsigned char C1POL:1; + unsigned char C1OE:1; + unsigned char C1OUT:1; + unsigned char C1ON:1; + }; +} __CM1CON0_bits_t; +extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; + +#define C1CH0 CM1CON0_bits.C1CH0 +#define C1CH1 CM1CON0_bits.C1CH1 +#define C1R CM1CON0_bits.C1R +#define C1SP CM1CON0_bits.C1SP +#define C1POL CM1CON0_bits.C1POL +#define C1OE CM1CON0_bits.C1OE +#define C1OUT CM1CON0_bits.C1OUT +#define C1ON CM1CON0_bits.C1ON + +// ----- CM2CON0 bits -------------------- +typedef union { + struct { + unsigned char C2CH0:1; + unsigned char C2CH1:1; + unsigned char C2R:1; + unsigned char C2SP:1; + unsigned char C2POL:1; + unsigned char C2OE:1; + unsigned char C2OUT:1; + unsigned char C2ON:1; + }; +} __CM2CON0_bits_t; +extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; + +#define C2CH0 CM2CON0_bits.C2CH0 +#define C2CH1 CM2CON0_bits.C2CH1 +#define C2R CM2CON0_bits.C2R +#define C2SP CM2CON0_bits.C2SP +#define C2POL CM2CON0_bits.C2POL +#define C2OE CM2CON0_bits.C2OE +#define C2OUT CM2CON0_bits.C2OUT +#define C2ON CM2CON0_bits.C2ON + +// ----- CM2CON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char MC2OUT:1; + unsigned char MC1OUT:1; + }; +} __CM2CON1_bits_t; +extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; + +#define C2SYNC CM2CON1_bits.C2SYNC +#define MC2OUT CM2CON1_bits.MC2OUT +#define MC1OUT CM2CON1_bits.MC1OUT + +// ----- DACON0 bits -------------------- +typedef union { + struct { + unsigned char DARS0:1; + unsigned char DARS1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char DAOE:1; + unsigned char DAON:1; + }; +} __DACON0_bits_t; +extern volatile __DACON0_bits_t __at(DACON0_ADDR) DACON0_bits; + +#define DARS0 DACON0_bits.DARS0 +#define DARS1 DACON0_bits.DARS1 +#define DAOE DACON0_bits.DAOE +#define DAON DACON0_bits.DAON + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LV0:1; + unsigned char LV1:1; + unsigned char LV2:1; + unsigned char LV3:1; + unsigned char LVDEN:1; + unsigned char BGST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LV0 LVDCON_bits.LV0 +#define LV1 LVDCON_bits.LV1 +#define LV2 LVDCON_bits.LV2 +#define LV3 LVDCON_bits.LV3 +#define LVDEN LVDCON_bits.LVDEN +#define BGST LVDCON_bits.BGST + +// ----- OPACON bits -------------------- +typedef union { + struct { + unsigned char GBWP:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char CMPEN:1; + unsigned char OPAON:1; + }; +} __OPACON_bits_t; +extern volatile __OPACON_bits_t __at(OPACON_ADDR) OPACON_bits; + +#define GBWP OPACON_bits.GBWP +#define CMPEN OPACON_bits.CMPEN +#define OPAON OPACON_bits.OPAON + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char WDTON:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF +#define WDTON PCON_bits.WDTON + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char ADIE:1; + unsigned char LVDIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define C1IE PIE1_bits.C1IE +#define C2IE PIE1_bits.C2IE +#define ADIE PIE1_bits.ADIE +#define LVDIE PIE1_bits.LVDIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char ADIF:1; + unsigned char LVDIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define C1IF PIR1_bits.C1IF +#define C2IF PIR1_bits.C2IF +#define ADIF PIR1_bits.ADIF +#define LVDIF PIR1_bits.LVDIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- PSMCCON0 bits -------------------- +typedef union { + struct { + unsigned char DC0:1; + unsigned char DC1:1; + unsigned char MAXDC0:1; + unsigned char MAXDC1:1; + unsigned char MINDC0:1; + unsigned char MINDC1:1; + unsigned char SMCCL0:1; + unsigned char SMCCL1:1; + }; +} __PSMCCON0_bits_t; +extern volatile __PSMCCON0_bits_t __at(PSMCCON0_ADDR) PSMCCON0_bits; + +#define DC0 PSMCCON0_bits.DC0 +#define DC1 PSMCCON0_bits.DC1 +#define MAXDC0 PSMCCON0_bits.MAXDC0 +#define MAXDC1 PSMCCON0_bits.MAXDC1 +#define MINDC0 PSMCCON0_bits.MINDC0 +#define MINDC1 PSMCCON0_bits.MINDC1 +#define SMCCL0 PSMCCON0_bits.SMCCL0 +#define SMCCL1 PSMCCON0_bits.SMCCL1 + +// ----- PSMCCON1 bits -------------------- +typedef union { + struct { + unsigned char SMCCS:1; + unsigned char PWM:1; + unsigned char SMCOM:1; + unsigned char SCEN:1; + unsigned char :1; + unsigned char S1BPOL:1; + unsigned char S1APOL:1; + unsigned char SMCON:1; + }; + struct { + unsigned char :1; + unsigned char PSM:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char NOT_PSM:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PSMCCON1_bits_t; +extern volatile __PSMCCON1_bits_t __at(PSMCCON1_ADDR) PSMCCON1_bits; + +#define SMCCS PSMCCON1_bits.SMCCS +#define PWM PSMCCON1_bits.PWM +#define PSM PSMCCON1_bits.PSM +#define NOT_PSM PSMCCON1_bits.NOT_PSM +#define SMCOM PSMCCON1_bits.SMCOM +#define SCEN PSMCCON1_bits.SCEN +#define S1BPOL PSMCCON1_bits.S1BPOL +#define S1APOL PSMCCON1_bits.S1APOL +#define SMCON PSMCCON1_bits.SMCON + +// ----- REFCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char VREFOE:1; + unsigned char VREFEN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __REFCON_bits_t; +extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; + +#define VREFOE REFCON_bits.VREFOE +#define VREFEN REFCON_bits.VREFEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE + +#endif diff --git a/device/include/pic/pic16c925.h b/device/include/pic/pic16c925.h new file mode 100644 index 00000000..1cfc8d90 --- /dev/null +++ b/device/include/pic/pic16c925.h @@ -0,0 +1,879 @@ +// +// Register Declarations for Microchip 16C925 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C925_H +#define P16C925_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define PORTF_ADDR 0x0107 +#define PORTG_ADDR 0x0108 +#define PMCON1_ADDR 0x010C +#define LCDSE_ADDR 0x010D +#define LCDPS_ADDR 0x010E +#define LCDCON_ADDR 0x010F +#define LCDD00_ADDR 0x0110 +#define LCDD01_ADDR 0x0111 +#define LCDD02_ADDR 0x0112 +#define LCDD03_ADDR 0x0113 +#define LCDD04_ADDR 0x0114 +#define LCDD05_ADDR 0x0115 +#define LCDD06_ADDR 0x0116 +#define LCDD07_ADDR 0x0117 +#define LCDD08_ADDR 0x0118 +#define LCDD09_ADDR 0x0119 +#define LCDD10_ADDR 0x011A +#define LCDD11_ADDR 0x011B +#define LCDD12_ADDR 0x011C +#define LCDD13_ADDR 0x011D +#define LCDD14_ADDR 0x011E +#define LCDD15_ADDR 0x011F +#define TRISF_ADDR 0x0187 +#define TRISG_ADDR 0x0188 +#define PMDATA_ADDR 0x018C +#define PMDATH_ADDR 0x018D +#define PMADR_ADDR 0x018E +#define PMADRH_ADDR 0x018F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PORTF_ADDR PORTF_ADDR SFR 0x000 // PORTF +#pragma memmap PORTG_ADDR PORTG_ADDR SFR 0x000 // PORTG +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 +#pragma memmap LCDSE_ADDR LCDSE_ADDR SFR 0x000 // LCDSE +#pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS +#pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON +#pragma memmap LCDD00_ADDR LCDD00_ADDR SFR 0x000 // LCDD00 +#pragma memmap LCDD01_ADDR LCDD01_ADDR SFR 0x000 // LCDD01 +#pragma memmap LCDD02_ADDR LCDD02_ADDR SFR 0x000 // LCDD02 +#pragma memmap LCDD03_ADDR LCDD03_ADDR SFR 0x000 // LCDD03 +#pragma memmap LCDD04_ADDR LCDD04_ADDR SFR 0x000 // LCDD04 +#pragma memmap LCDD05_ADDR LCDD05_ADDR SFR 0x000 // LCDD05 +#pragma memmap LCDD06_ADDR LCDD06_ADDR SFR 0x000 // LCDD06 +#pragma memmap LCDD07_ADDR LCDD07_ADDR SFR 0x000 // LCDD07 +#pragma memmap LCDD08_ADDR LCDD08_ADDR SFR 0x000 // LCDD08 +#pragma memmap LCDD09_ADDR LCDD09_ADDR SFR 0x000 // LCDD09 +#pragma memmap LCDD10_ADDR LCDD10_ADDR SFR 0x000 // LCDD10 +#pragma memmap LCDD11_ADDR LCDD11_ADDR SFR 0x000 // LCDD11 +#pragma memmap LCDD12_ADDR LCDD12_ADDR SFR 0x000 // LCDD12 +#pragma memmap LCDD13_ADDR LCDD13_ADDR SFR 0x000 // LCDD13 +#pragma memmap LCDD14_ADDR LCDD14_ADDR SFR 0x000 // LCDD14 +#pragma memmap LCDD15_ADDR LCDD15_ADDR SFR 0x000 // LCDD15 +#pragma memmap TRISF_ADDR TRISF_ADDR SFR 0x000 // TRISF +#pragma memmap TRISG_ADDR TRISG_ADDR SFR 0x000 // TRISG +#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH + + +// LIST +// P16C925.INC Standard Header File, Version 1.02 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C925 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C925 +// 2. LIST directive in the source file +// LIST P=PIC16C925 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 11/21/00 Initial Release +//1.01 02/27/01 Changes to reflect design changes to data memory map: +// 1.) Locations of PMDATA and PMCON1 swapped. +// 2.) Locations of PMDATH and PMADR swapped. +//1.02 03/02/01 PORTF, PORTG, TRISF, and TRISG addresses corrected. +//1.03 03/06/01 RD bit in PMCON1 defined. +//1.04 03/12/01 Locations of PMDATH and PMADR restored to before v1.01. +//1.05 10/19/01 Locations of PMDATH and PMADR restored to before v1.04. +//1.06 06/03/01 Values for _CP_ALL, _CP_75, _CP_50, and _BODEN_OFF corrected. + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C925 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PORTF_ADDR) PORTF; +extern sfr __at (PORTG_ADDR) PORTG; +extern sfr __at (PMCON1_ADDR) PMCON1; +extern sfr __at (LCDSE_ADDR) LCDSE; +extern sfr __at (LCDPS_ADDR) LCDPS; +extern sfr __at (LCDCON_ADDR) LCDCON; +extern sfr __at (LCDD00_ADDR) LCDD00; +extern sfr __at (LCDD01_ADDR) LCDD01; +extern sfr __at (LCDD02_ADDR) LCDD02; +extern sfr __at (LCDD03_ADDR) LCDD03; +extern sfr __at (LCDD04_ADDR) LCDD04; +extern sfr __at (LCDD05_ADDR) LCDD05; +extern sfr __at (LCDD06_ADDR) LCDD06; +extern sfr __at (LCDD07_ADDR) LCDD07; +extern sfr __at (LCDD08_ADDR) LCDD08; +extern sfr __at (LCDD09_ADDR) LCDD09; +extern sfr __at (LCDD10_ADDR) LCDD10; +extern sfr __at (LCDD11_ADDR) LCDD11; +extern sfr __at (LCDD12_ADDR) LCDD12; +extern sfr __at (LCDD13_ADDR) LCDD13; +extern sfr __at (LCDD14_ADDR) LCDD14; +extern sfr __at (LCDD15_ADDR) LCDD15; + +extern sfr __at (TRISF_ADDR) TRISF; +extern sfr __at (TRISG_ADDR) TRISG; +extern sfr __at (PMDATA_ADDR) PMDATA; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADR_ADDR) PMADR; +extern sfr __at (PMADRH_ADDR) PMADRH; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- LCDSE Bits --------------------------------------------------------- + + +//----- LCDPS Bits --------------------------------------------------------- + + +//----- LCDCON Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'0D', H'18'-H'1D' +// __BADRAM H'8D', H'8F'-H'91', H'95'-H'9D' +// __BADRAM H'105', H'109', H'120'-H'16F' +// __BADRAM H'185', H'189', H'190'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x3FCF +#define _CP_75 0x3FDF +#define _CP_50 0x3FEF +#define _CP_OFF 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _BODEN_ON 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LCDCON bits -------------------- +typedef union { + struct { + unsigned char LMUX0:1; + unsigned char LMUX1:1; + unsigned char CS0:1; + unsigned char CS1:1; + unsigned char BIAS:1; + unsigned char WERR:1; + unsigned char SLPEN:1; + unsigned char LCDEN:1; + }; +} __LCDCON_bits_t; +extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; + +#define LMUX0 LCDCON_bits.LMUX0 +#define LMUX1 LCDCON_bits.LMUX1 +#define CS0 LCDCON_bits.CS0 +#define CS1 LCDCON_bits.CS1 +#define BIAS LCDCON_bits.BIAS +#define WERR LCDCON_bits.WERR +#define SLPEN LCDCON_bits.SLPEN +#define LCDEN LCDCON_bits.LCDEN + +// ----- LCDPS bits -------------------- +typedef union { + struct { + unsigned char LP0:1; + unsigned char LP1:1; + unsigned char LP2:1; + unsigned char LP3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __LCDPS_bits_t; +extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; + +#define LP0 LCDPS_bits.LP0 +#define LP1 LCDPS_bits.LP1 +#define LP2 LCDPS_bits.LP2 +#define LP3 LCDPS_bits.LP3 + +// ----- LCDSE bits -------------------- +typedef union { + struct { + unsigned char SE0:1; + unsigned char SE5:1; + unsigned char SE9:1; + unsigned char SE12:1; + unsigned char SE16:1; + unsigned char SE20:1; + unsigned char SE27:1; + unsigned char SE29:1; + }; +} __LCDSE_bits_t; +extern volatile __LCDSE_bits_t __at(LCDSE_ADDR) LCDSE_bits; + +#define SE0 LCDSE_bits.SE0 +#define SE5 LCDSE_bits.SE5 +#define SE9 LCDSE_bits.SE9 +#define SE12 LCDSE_bits.SE12 +#define SE16 LCDSE_bits.SE16 +#define SE20 LCDSE_bits.SE20 +#define SE27 LCDSE_bits.SE27 +#define SE29 LCDSE_bits.SE29 + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOR:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char LCDIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE +#define LCDIE PIE1_bits.LCDIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char LCDIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF +#define LCDIF PIR1_bits.LCDIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +#endif diff --git a/device/include/pic/pic16c926.h b/device/include/pic/pic16c926.h new file mode 100644 index 00000000..07238872 --- /dev/null +++ b/device/include/pic/pic16c926.h @@ -0,0 +1,879 @@ +// +// Register Declarations for Microchip 16C926 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16C926_H +#define P16C926_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define PORTF_ADDR 0x0107 +#define PORTG_ADDR 0x0108 +#define PMCON1_ADDR 0x010C +#define LCDSE_ADDR 0x010D +#define LCDPS_ADDR 0x010E +#define LCDCON_ADDR 0x010F +#define LCDD00_ADDR 0x0110 +#define LCDD01_ADDR 0x0111 +#define LCDD02_ADDR 0x0112 +#define LCDD03_ADDR 0x0113 +#define LCDD04_ADDR 0x0114 +#define LCDD05_ADDR 0x0115 +#define LCDD06_ADDR 0x0116 +#define LCDD07_ADDR 0x0117 +#define LCDD08_ADDR 0x0118 +#define LCDD09_ADDR 0x0119 +#define LCDD10_ADDR 0x011A +#define LCDD11_ADDR 0x011B +#define LCDD12_ADDR 0x011C +#define LCDD13_ADDR 0x011D +#define LCDD14_ADDR 0x011E +#define LCDD15_ADDR 0x011F +#define TRISF_ADDR 0x0187 +#define TRISG_ADDR 0x0188 +#define PMDATA_ADDR 0x018C +#define PMDATH_ADDR 0x018D +#define PMADR_ADDR 0x018E +#define PMADRH_ADDR 0x018F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PORTF_ADDR PORTF_ADDR SFR 0x000 // PORTF +#pragma memmap PORTG_ADDR PORTG_ADDR SFR 0x000 // PORTG +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 +#pragma memmap LCDSE_ADDR LCDSE_ADDR SFR 0x000 // LCDSE +#pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS +#pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON +#pragma memmap LCDD00_ADDR LCDD00_ADDR SFR 0x000 // LCDD00 +#pragma memmap LCDD01_ADDR LCDD01_ADDR SFR 0x000 // LCDD01 +#pragma memmap LCDD02_ADDR LCDD02_ADDR SFR 0x000 // LCDD02 +#pragma memmap LCDD03_ADDR LCDD03_ADDR SFR 0x000 // LCDD03 +#pragma memmap LCDD04_ADDR LCDD04_ADDR SFR 0x000 // LCDD04 +#pragma memmap LCDD05_ADDR LCDD05_ADDR SFR 0x000 // LCDD05 +#pragma memmap LCDD06_ADDR LCDD06_ADDR SFR 0x000 // LCDD06 +#pragma memmap LCDD07_ADDR LCDD07_ADDR SFR 0x000 // LCDD07 +#pragma memmap LCDD08_ADDR LCDD08_ADDR SFR 0x000 // LCDD08 +#pragma memmap LCDD09_ADDR LCDD09_ADDR SFR 0x000 // LCDD09 +#pragma memmap LCDD10_ADDR LCDD10_ADDR SFR 0x000 // LCDD10 +#pragma memmap LCDD11_ADDR LCDD11_ADDR SFR 0x000 // LCDD11 +#pragma memmap LCDD12_ADDR LCDD12_ADDR SFR 0x000 // LCDD12 +#pragma memmap LCDD13_ADDR LCDD13_ADDR SFR 0x000 // LCDD13 +#pragma memmap LCDD14_ADDR LCDD14_ADDR SFR 0x000 // LCDD14 +#pragma memmap LCDD15_ADDR LCDD15_ADDR SFR 0x000 // LCDD15 +#pragma memmap TRISF_ADDR TRISF_ADDR SFR 0x000 // TRISF +#pragma memmap TRISG_ADDR TRISG_ADDR SFR 0x000 // TRISG +#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH + + +// LIST +// P16C926.INC Standard Header File, Version 1.02 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16C926 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16C926 +// 2. LIST directive in the source file +// LIST P=PIC16C926 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 10/11/00 Initial Release +//1.01 02/27/01 Changes to reflect design changes to data memory map: +// 1.) Locations of PMDATA and PMCON1 swapped. +// 2.) Locations of PMDATH and PMADR swapped. +//1.02 03/02/01 PORTF, PORTG, TRISF, and TRISG addresses corrected. +//1.03 03/06/01 RD bit in PMCON1 defined. +//1.04 03/12/01 Locations of PMDATH and PMADR restored to before v1.01. +//1.05 10/19/01 Locations of PMDATH and PMADR restored to before v1.04. +//1.06 06/03/01 Values for _CP_ALL, _CP_75, _CP_50, and _BODEN_OFF corrected. + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16C926 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PORTF_ADDR) PORTF; +extern sfr __at (PORTG_ADDR) PORTG; +extern sfr __at (PMCON1_ADDR) PMCON1; +extern sfr __at (LCDSE_ADDR) LCDSE; +extern sfr __at (LCDPS_ADDR) LCDPS; +extern sfr __at (LCDCON_ADDR) LCDCON; +extern sfr __at (LCDD00_ADDR) LCDD00; +extern sfr __at (LCDD01_ADDR) LCDD01; +extern sfr __at (LCDD02_ADDR) LCDD02; +extern sfr __at (LCDD03_ADDR) LCDD03; +extern sfr __at (LCDD04_ADDR) LCDD04; +extern sfr __at (LCDD05_ADDR) LCDD05; +extern sfr __at (LCDD06_ADDR) LCDD06; +extern sfr __at (LCDD07_ADDR) LCDD07; +extern sfr __at (LCDD08_ADDR) LCDD08; +extern sfr __at (LCDD09_ADDR) LCDD09; +extern sfr __at (LCDD10_ADDR) LCDD10; +extern sfr __at (LCDD11_ADDR) LCDD11; +extern sfr __at (LCDD12_ADDR) LCDD12; +extern sfr __at (LCDD13_ADDR) LCDD13; +extern sfr __at (LCDD14_ADDR) LCDD14; +extern sfr __at (LCDD15_ADDR) LCDD15; + +extern sfr __at (TRISF_ADDR) TRISF; +extern sfr __at (TRISG_ADDR) TRISG; +extern sfr __at (PMDATA_ADDR) PMDATA; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADR_ADDR) PMADR; +extern sfr __at (PMADRH_ADDR) PMADRH; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- LCDSE Bits --------------------------------------------------------- + + +//----- LCDPS Bits --------------------------------------------------------- + + +//----- LCDCON Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'0D', H'18'-H'1D' +// __BADRAM H'8D', H'8F'-H'91', H'95'-H'9D' +// __BADRAM H'105', H'109' +// __BADRAM H'185', H'189', H'190'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x3FCF +#define _CP_75 0x3FDF +#define _CP_50 0x3FEF +#define _CP_OFF 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _BODEN_ON 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LCDCON bits -------------------- +typedef union { + struct { + unsigned char LMUX0:1; + unsigned char LMUX1:1; + unsigned char CS0:1; + unsigned char CS1:1; + unsigned char BIAS:1; + unsigned char WERR:1; + unsigned char SLPEN:1; + unsigned char LCDEN:1; + }; +} __LCDCON_bits_t; +extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; + +#define LMUX0 LCDCON_bits.LMUX0 +#define LMUX1 LCDCON_bits.LMUX1 +#define CS0 LCDCON_bits.CS0 +#define CS1 LCDCON_bits.CS1 +#define BIAS LCDCON_bits.BIAS +#define WERR LCDCON_bits.WERR +#define SLPEN LCDCON_bits.SLPEN +#define LCDEN LCDCON_bits.LCDEN + +// ----- LCDPS bits -------------------- +typedef union { + struct { + unsigned char LP0:1; + unsigned char LP1:1; + unsigned char LP2:1; + unsigned char LP3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __LCDPS_bits_t; +extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; + +#define LP0 LCDPS_bits.LP0 +#define LP1 LCDPS_bits.LP1 +#define LP2 LCDPS_bits.LP2 +#define LP3 LCDPS_bits.LP3 + +// ----- LCDSE bits -------------------- +typedef union { + struct { + unsigned char SE0:1; + unsigned char SE5:1; + unsigned char SE9:1; + unsigned char SE12:1; + unsigned char SE16:1; + unsigned char SE20:1; + unsigned char SE27:1; + unsigned char SE29:1; + }; +} __LCDSE_bits_t; +extern volatile __LCDSE_bits_t __at(LCDSE_ADDR) LCDSE_bits; + +#define SE0 LCDSE_bits.SE0 +#define SE5 LCDSE_bits.SE5 +#define SE9 LCDSE_bits.SE9 +#define SE12 LCDSE_bits.SE12 +#define SE16 LCDSE_bits.SE16 +#define SE20 LCDSE_bits.SE20 +#define SE27 LCDSE_bits.SE27 +#define SE29 LCDSE_bits.SE29 + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOR:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char LCDIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE +#define LCDIE PIE1_bits.LCDIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char LCDIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF +#define LCDIF PIR1_bits.LCDIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +#endif diff --git a/device/include/pic/pic16f505.h b/device/include/pic/pic16f505.h new file mode 100644 index 00000000..06fca79b --- /dev/null +++ b/device/include/pic/pic16f505.h @@ -0,0 +1,223 @@ +// +// Register Declarations for Microchip 16F505 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F505_H +#define P16F505_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define OSCCAL_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define OPTION_REG_ADDR 0x0081 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG + + +// LIST +// P16F505.INC Standard Header File, Version 1.10 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F505 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /P16F505 +// 2. LIST directive in the source file +// LIST P=16F505 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 12/09/03 Initial Release +//1.01 04/14/04 Update for EC osc mode + + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F505 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files ----------------------------------------------------- + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (OSCCAL_ADDR) OSCCAL; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; // not verified + +//----- STATUS Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- OSCCAL Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'7F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _MCLRE_ON 0x0FFF +#define _MCLRE_OFF 0x0FDF +#define _CP_ON 0x002F +#define _CP_OFF 0x0FFF +#define _WDT_ON 0x0FFF +#define _WDT_OFF 0x0FF7 +#define _LP_OSC 0x0FF8 +#define _XT_OSC 0x0FF9 +#define _HS_OSC 0x0FFA +#define _EC_RB4EN 0x0FFB +#define _IntRC_OSC_RB4EN 0x0FFC +#define _IntRC_OSC_CLKOUTEN 0x0FFD +#define _ExtRC_OSC_RB4EN 0x0FFE +#define _ExtRC_OSC_CLKOUTEN 0x0FFF + +// LIST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char NOT_RBPU:1; + unsigned char NOT_RBWU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU +#define NOT_RBWU OPTION_REG_bits.NOT_RBWU + +// ----- OSCCAL bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char CAL0:1; + unsigned char CAL1:1; + unsigned char CAL2:1; + unsigned char CAL3:1; + unsigned char CAL4:1; + unsigned char CAL5:1; + unsigned char CAL6:1; + }; +} __OSCCAL_bits_t; +extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits; + +#define CAL0 OSCCAL_bits.CAL0 +#define CAL1 OSCCAL_bits.CAL1 +#define CAL2 OSCCAL_bits.CAL2 +#define CAL3 OSCCAL_bits.CAL3 +#define CAL4 OSCCAL_bits.CAL4 +#define CAL5 OSCCAL_bits.CAL5 +#define CAL6 OSCCAL_bits.CAL6 + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char PA0:1; + unsigned char :1; + unsigned char RBWUF:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define PA0 STATUS_bits.PA0 +#define RBWUF STATUS_bits.RBWUF + +#endif diff --git a/device/include/pic/pic16f627.h b/device/include/pic/pic16f627.h new file mode 100644 index 00000000..9acb7b38 --- /dev/null +++ b/device/include/pic/pic16f627.h @@ -0,0 +1,611 @@ +// +// Register Declarations for Microchip 16F627 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F627_H +#define P16F627_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16F627.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F627 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F627 +// 2. LIST directive in the source file +// LIST P=PIC16F627 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.01 13 Sept 2001 Added _DATA_CP_ON and _DATA_CP_OFF +//1.00 10 Feb 1999 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F627 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + +//----- T2CON Bits --------------------------------------------------------- + +//----- CCP1CON Bits --------------------------------------------------------- + +//----- RCSTA Bits --------------------------------------------------------- + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- TXSTA Bits ---------------------------------------------------------- + +//----- EECON1 Bits --------------------------------------------------------- + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'01FF' +// __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' +// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F' +// __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x03FF +#define _CP_75 0x17FF +#define _CP_50 0x2BFF +#define _CP_OFF 0x3FFF +#define _DATA_CP_ON 0x3EFF +#define _DATA_CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _ER_OSC_CLKOUT 0x3FFF +#define _ER_OSC_NOCLKOUT 0x3FFE +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _EXTCLK_OSC 0x3FEF +#define _LP_OSC 0x3FEC +#define _XT_OSC 0x3FED +#define _HS_OSC 0x3FEE + +// LIST + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char :1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char CMIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define CMIE PIE1_bits.CMIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char :1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char CMIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define CMIF PIR1_bits.CMIF +#define EEIF PIR1_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADEN RCSTA_bits.ADEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16f627a.h b/device/include/pic/pic16f627a.h new file mode 100644 index 00000000..bd34d9bf --- /dev/null +++ b/device/include/pic/pic16f627a.h @@ -0,0 +1,615 @@ +// +// Register Declarations for Microchip 16F627A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F627A_H +#define P16F627A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16F627A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F627A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F627A +// 2. LIST directive in the source file +// LIST P=PIC16F627A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.01 14 Nov 2002 Updated to reflect BOD terminology changed to BOR +//1.00 22 Aug 2002 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F627A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + +//----- T2CON Bits --------------------------------------------------------- + +//----- CCP1CON Bits --------------------------------------------------------- + +//----- RCSTA Bits --------------------------------------------------------- + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- TXSTA Bits ---------------------------------------------------------- + +//----- EECON1 Bits --------------------------------------------------------- + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'01FF' +// __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' +// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F' +// __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF //Backwards compatability to 16F62X +#define _BODEN_OFF 0x3FBF //Backwards compatability to 16F62X +#define _BOREN_ON 0x3FFF +#define _BOREN_OFF 0x3FBF +#define _CP_ON 0x1FFF +#define _CP_OFF 0x3FFF +#define _DATA_CP_ON 0x3EFF +#define _DATA_CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _RC_OSC_CLKOUT 0x3FFF +#define _RC_OSC_NOCLKOUT 0x3FFE +#define _ER_OSC_CLKOUT 0x3FFF //Backwards compatability to 16F62X +#define _ER_OSC_NOCLKOUT 0x3FFE //Backwards compatability to 16F62X +#define _INTOSC_OSC_CLKOUT 0x3FFD +#define _INTOSC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD //Backwards compatability to 16F62X +#define _INTRC_OSC_NOCLKOUT 0x3FFC //Backwards compatability to 16F62X +#define _EXTCLK_OSC 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +// LIST + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char :1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char CMIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define CMIE PIE1_bits.CMIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char :1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char CMIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define CMIF PIR1_bits.CMIF +#define EEIF PIR1_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADEN RCSTA_bits.ADEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16f628.h b/device/include/pic/pic16f628.h new file mode 100644 index 00000000..5c2803e7 --- /dev/null +++ b/device/include/pic/pic16f628.h @@ -0,0 +1,611 @@ +// +// Register Declarations for Microchip 16F628 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F628_H +#define P16F628_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16F628.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F628 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F628 +// 2. LIST directive in the source file +// LIST P=PIC16F628 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.01 13 Sept 2001 Added _DATA_CP_ON and _DATA_CP_OFF +//1.00 10 Feb 1999 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F628 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + +//----- T2CON Bits --------------------------------------------------------- + +//----- CCP1CON Bits --------------------------------------------------------- + +//----- RCSTA Bits --------------------------------------------------------- + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- TXSTA Bits ---------------------------------------------------------- + +//----- EECON1 Bits --------------------------------------------------------- + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'01FF' +// __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' +// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F' +// __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x03FF +#define _CP_75 0x17FF +#define _CP_50 0x2BFF +#define _CP_OFF 0x3FFF +#define _DATA_CP_ON 0x3EFF +#define _DATA_CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _ER_OSC_CLKOUT 0x3FFF +#define _ER_OSC_NOCLKOUT 0x3FFE +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _EXTCLK_OSC 0x3FEF +#define _LP_OSC 0x3FEC +#define _XT_OSC 0x3FED +#define _HS_OSC 0x3FEE + +// LIST + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char :1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char CMIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define CMIE PIE1_bits.CMIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char :1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char CMIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define CMIF PIR1_bits.CMIF +#define EEIF PIR1_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADEN RCSTA_bits.ADEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16f628a.h b/device/include/pic/pic16f628a.h new file mode 100644 index 00000000..44ab2c2e --- /dev/null +++ b/device/include/pic/pic16f628a.h @@ -0,0 +1,616 @@ +// +// Register Declarations for Microchip 16F628A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F628A_H +#define P16F628A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16F628A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F628A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F628A +// 2. LIST directive in the source file +// LIST P=PIC16F628A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.01 14 Nov 2002 Updated to reflect BOD terminology changed to BOR +//1.00 22 Aug 2002 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F628A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + +//----- T2CON Bits --------------------------------------------------------- + +//----- CCP1CON Bits --------------------------------------------------------- + +//----- RCSTA Bits --------------------------------------------------------- + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- TXSTA Bits ---------------------------------------------------------- + +//----- EECON1 Bits --------------------------------------------------------- + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'01FF' +// __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' +// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F' +// __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF //Backwards compatability to 16F62X +#define _BODEN_OFF 0x3FBF //Backwards compatability to 16F62X +#define _BOREN_ON 0x3FFF +#define _BOREN_OFF 0x3FBF +#define _CP_ON 0x1FFF +#define _CP_OFF 0x3FFF +#define _DATA_CP_ON 0x3EFF +#define _DATA_CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _RC_OSC_CLKOUT 0x3FFF +#define _RC_OSC_NOCLKOUT 0x3FFE +#define _ER_OSC_CLKOUT 0x3FFF //Backwards compatability to 16F62X +#define _ER_OSC_NOCLKOUT 0x3FFE //Backwards compatability to 16F62X +#define _INTOSC_OSC_CLKOUT 0x3FFD +#define _INTOSC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD //Backwards compatability to 16F62X +#define _INTRC_OSC_NOCLKOUT 0x3FFC //Backwards compatability to 16F62X +#define _EXTCLK_OSC 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +// LIST + + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char :1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char CMIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define CMIE PIE1_bits.CMIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char :1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char CMIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define CMIF PIR1_bits.CMIF +#define EEIF PIR1_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADEN RCSTA_bits.ADEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16f630.h b/device/include/pic/pic16f630.h new file mode 100644 index 00000000..d2dd5dd9 --- /dev/null +++ b/device/include/pic/pic16f630.h @@ -0,0 +1,519 @@ +// +// Register Declarations for Microchip 16F630 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F630_H +#define P16F630_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define CMCON_ADDR 0x0019 +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define OSCCAL_ADDR 0x0090 +#define WPUA_ADDR 0x0095 +#define WPU_ADDR 0x0095 +#define IOCA_ADDR 0x0096 +#define IOC_ADDR 0x0096 +#define VRCON_ADDR 0x0099 +#define EEDATA_ADDR 0x009A +#define EEDAT_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL +#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F630.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F630 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F630 +// 2. LIST directive in the source file +// LIST P=PIC16F630 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 05/13/02 Original + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F630 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; + +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; + +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; + +extern sfr __at (PCON_ADDR) PCON; + +extern sfr __at (OSCCAL_ADDR) OSCCAL; + +extern sfr __at (WPUA_ADDR) WPUA; +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (IOCA_ADDR) IOCA; +extern sfr __at (IOC_ADDR) IOC; + +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEDAT_ADDR) EEDAT; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- CMCON Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCAL Bits -------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- EECON1 ------------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'18', H'1A'-H'1F', H'60'-H'7F' +// __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'9E'-H'9F', H'E0'-H'FF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CPD 0x3EFF +#define _CPD_OFF 0x3FFF +#define _CP 0x3F7F +#define _CP_OFF 0x3FFF +#define _BODEN 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF + +// LIST + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char CINV:1; + unsigned char :1; + unsigned char COUT:1; + unsigned char :1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define CINV CMCON_bits.CINV +#define COUT CMCON_bits.COUT + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RAIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RAIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RAIF INTCON_bits.RAIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RAIE INTCON_bits.RAIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_GPPU:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RAPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_GPPU OPTION_REG_bits.NOT_GPPU +#define NOT_RAPU OPTION_REG_bits.NOT_RAPU + +// ----- OSCCAL bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char CAL0:1; + unsigned char CAL1:1; + unsigned char CAL2:1; + unsigned char CAL3:1; + unsigned char CAL4:1; + unsigned char CAL5:1; + }; +} __OSCCAL_bits_t; +extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits; + +#define CAL0 OSCCAL_bits.CAL0 +#define CAL1 OSCCAL_bits.CAL1 +#define CAL2 OSCCAL_bits.CAL2 +#define CAL3 OSCCAL_bits.CAL3 +#define CAL4 OSCCAL_bits.CAL4 +#define CAL5 OSCCAL_bits.CAL5 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char T1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char EEIE:1; + }; + struct { + unsigned char TMR1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define T1IE PIE1_bits.T1IE +#define TMR1IE PIE1_bits.TMR1IE +#define CMIE PIE1_bits.CMIE +#define ADIE PIE1_bits.ADIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char T1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char EEIF:1; + }; + struct { + unsigned char TMR1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define T1IF PIR1_bits.T1IF +#define TMR1IF PIR1_bits.TMR1IF +#define CMIF PIR1_bits.CMIF +#define ADIF PIR1_bits.ADIF +#define EEIF PIR1_bits.EEIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char :1; + unsigned char VREN:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define RD VRCON_bits.RD +#define VR1 VRCON_bits.VR1 +#define WR VRCON_bits.WR +#define VR2 VRCON_bits.VR2 +#define WREN VRCON_bits.WREN +#define VR3 VRCON_bits.VR3 +#define WRERR VRCON_bits.WRERR +#define VRR VRCON_bits.VRR +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16f636.h b/device/include/pic/pic16f636.h new file mode 100644 index 00000000..b53946e9 --- /dev/null +++ b/device/include/pic/pic16f636.h @@ -0,0 +1,691 @@ +// +// Register Declarations for Microchip 16F636 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F636_H +#define P16F636_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define WDTCON_ADDR 0x0018 +#define CMCON0_ADDR 0x0019 +#define CMCON1_ADDR 0x001A +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define LVDCON_ADDR 0x0094 +#define WPUDA_ADDR 0x0095 +#define IOCA_ADDR 0x0096 +#define WDA_ADDR 0x0097 +#define VRCON_ADDR 0x0099 +#define EEDAT_ADDR 0x009A +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define CRCON_ADDR 0x0110 +#define CRDAT0_ADDR 0x0111 +#define CRDAT1_ADDR 0x0112 +#define CRDAT2_ADDR 0x0113 +#define CRDAT3_ADDR 0x0114 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0 +#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap WPUDA_ADDR WPUDA_ADDR SFR 0x000 // WPUDA +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap WDA_ADDR WDA_ADDR SFR 0x000 // WDA +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap CRCON_ADDR CRCON_ADDR SFR 0x000 // CRCON +#pragma memmap CRDAT0_ADDR CRDAT0_ADDR SFR 0x000 // CRDAT0 +#pragma memmap CRDAT1_ADDR CRDAT1_ADDR SFR 0x000 // CRDAT1 +#pragma memmap CRDAT2_ADDR CRDAT2_ADDR SFR 0x000 // CRDAT2 +#pragma memmap CRDAT3_ADDR CRDAT3_ADDR SFR 0x000 // CRDAT3 + + +// LIST +// P16F636.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F636 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F636 +// 2. LIST directive in the source file +// LIST P=PIC16F636 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 12/07/03 Original +//1.10 04/19/04 Update to match first release datasheet --kjd +//1.20 06/07/04 Update and correct badram definitions --kjd +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F636 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ +//Bank 0 +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; + +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; + +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (CMCON0_ADDR) CMCON0; +extern sfr __at (CMCON1_ADDR) CMCON1; + +//Bank 1 +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; + +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; + +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (WPUDA_ADDR) WPUDA; +extern sfr __at (IOCA_ADDR) IOCA; +extern sfr __at (WDA_ADDR) WDA; + +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (EEDAT_ADDR) EEDAT; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//Bank 2 +extern sfr __at (CRCON_ADDR) CRCON; +extern sfr __at (CRDAT0_ADDR) CRDAT0; +extern sfr __at (CRDAT1_ADDR) CRDAT1; +extern sfr __at (CRDAT2_ADDR) CRDAT2; +extern sfr __at (CRDAT3_ADDR) CRDAT3; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- CMCON0 Bits ------------------------------------------------------- + + +//----- CMCON1 Bits ------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits -------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- IOCA -------------------------------------------------------------- + + +//----- EECON1 ------------------------------------------------------------- + + +//----- VRCON --------------------------------------------------------- + + + +//----- CRCON ------------------------------------------------------------- + + +//----- LVDCON ------------------------------------------------------------- + + +//----- WDA ------------------------------------------------------------- + + +//----- WPUDA ------------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F' +// __BADRAM H'86', H'88'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'C0'-H'EF' +// __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106', H'108'-H'109', H'186' +// __BADRAM H'188'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== +#define _WUREN_ON 0x2FFF +#define _WUREN_OFF 0x3FFF +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF + +// LIST + +// ----- CMCON0 bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON0_bits_t; +extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; + +#define CM0 CMCON0_bits.CM0 +#define CM1 CMCON0_bits.CM1 +#define CM2 CMCON0_bits.CM2 +#define CIS CMCON0_bits.CIS +#define C1INV CMCON0_bits.C1INV +#define C2INV CMCON0_bits.C2INV +#define C1OUT CMCON0_bits.C1OUT +#define C2OUT CMCON0_bits.C2OUT + +// ----- CMCON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __CMCON1_bits_t; +extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; + +#define C2SYNC CMCON1_bits.C2SYNC +#define T1GSS CMCON1_bits.T1GSS + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RAIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RAIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RAIF INTCON_bits.RAIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RAIE INTCON_bits.RAIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RAPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RAPU OPTION_REG_bits.NOT_RAPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char IOCA5:1; + unsigned char ENC_DEC:1; + unsigned char VREN:1; + }; + struct { + unsigned char IOCA0:1; + unsigned char IOCA1:1; + unsigned char IOCA2:1; + unsigned char IOCA3:1; + unsigned char IOCA4:1; + unsigned char VRR:1; + unsigned char :1; + unsigned char GO:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char LVDEN:1; + unsigned char IRVST:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char WDA4:1; + unsigned char WDA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char CRREG0:1; + unsigned char CRREG1:1; + unsigned char LVDL2:1; + unsigned char :1; + unsigned char WPUDA4:1; + unsigned char WPUDA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char LVDL0:1; + unsigned char LVDL1:1; + unsigned char WDA2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char WDA0:1; + unsigned char WDA1:1; + unsigned char WPUDA2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char WPUDA0:1; + unsigned char WPUDA1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define IOCA0 OSCTUNE_bits.IOCA0 +#define RD OSCTUNE_bits.RD +#define VR0 OSCTUNE_bits.VR0 +#define CRREG0 OSCTUNE_bits.CRREG0 +#define LVDL0 OSCTUNE_bits.LVDL0 +#define WDA0 OSCTUNE_bits.WDA0 +#define WPUDA0 OSCTUNE_bits.WPUDA0 +#define TUN1 OSCTUNE_bits.TUN1 +#define IOCA1 OSCTUNE_bits.IOCA1 +#define WR OSCTUNE_bits.WR +#define VR1 OSCTUNE_bits.VR1 +#define CRREG1 OSCTUNE_bits.CRREG1 +#define LVDL1 OSCTUNE_bits.LVDL1 +#define WDA1 OSCTUNE_bits.WDA1 +#define WPUDA1 OSCTUNE_bits.WPUDA1 +#define TUN2 OSCTUNE_bits.TUN2 +#define IOCA2 OSCTUNE_bits.IOCA2 +#define WREN OSCTUNE_bits.WREN +#define VR2 OSCTUNE_bits.VR2 +#define LVDL2 OSCTUNE_bits.LVDL2 +#define WDA2 OSCTUNE_bits.WDA2 +#define WPUDA2 OSCTUNE_bits.WPUDA2 +#define TUN3 OSCTUNE_bits.TUN3 +#define IOCA3 OSCTUNE_bits.IOCA3 +#define WRERR OSCTUNE_bits.WRERR +#define VR3 OSCTUNE_bits.VR3 +#define TUN4 OSCTUNE_bits.TUN4 +#define IOCA4 OSCTUNE_bits.IOCA4 +#define LVDEN OSCTUNE_bits.LVDEN +#define WDA4 OSCTUNE_bits.WDA4 +#define WPUDA4 OSCTUNE_bits.WPUDA4 +#define IOCA5 OSCTUNE_bits.IOCA5 +#define VRR OSCTUNE_bits.VRR +#define IRVST OSCTUNE_bits.IRVST +#define WDA5 OSCTUNE_bits.WDA5 +#define WPUDA5 OSCTUNE_bits.WPUDA5 +#define ENC_DEC OSCTUNE_bits.ENC_DEC +#define VREN OSCTUNE_bits.VREN +#define GO OSCTUNE_bits.GO + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char NOT_WUR:1; + unsigned char SBODEN:1; + unsigned char ULPWUE:1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define NOT_WUR PCON_bits.NOT_WUR +#define SBODEN PCON_bits.SBODEN +#define ULPWUE PCON_bits.ULPWUE + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char :1; + unsigned char OSFIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char CRIE:1; + unsigned char LVDIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define OSFIE PIE1_bits.OSFIE +#define C1IE PIE1_bits.C1IE +#define C2IE PIE1_bits.C2IE +#define CRIE PIE1_bits.CRIE +#define LVDIE PIE1_bits.LVDIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char :1; + unsigned char OSFIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char CRIF:1; + unsigned char LVDIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define OSFIF PIR1_bits.OSFIF +#define C1IF PIR1_bits.C1IF +#define C2IF PIR1_bits.C2IF +#define CRIF PIR1_bits.CRIF +#define LVDIF PIR1_bits.LVDIF +#define EEIF PIR1_bits.EEIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char T1GINV:1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +#endif diff --git a/device/include/pic/pic16f639.h b/device/include/pic/pic16f639.h new file mode 100644 index 00000000..3c546e7d --- /dev/null +++ b/device/include/pic/pic16f639.h @@ -0,0 +1,687 @@ +// +// Register Declarations for Microchip 16F639 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F639_H +#define P16F639_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define WDTCON_ADDR 0x0018 +#define CMCON0_ADDR 0x0019 +#define CMCON1_ADDR 0x001A +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define LVDCON_ADDR 0x0094 +#define WPUDA_ADDR 0x0095 +#define IOCA_ADDR 0x0096 +#define WDA_ADDR 0x0097 +#define VRCON_ADDR 0x0099 +#define EEDAT_ADDR 0x009A +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define CRCON_ADDR 0x0110 +#define CRDAT0_ADDR 0x0111 +#define CRDAT1_ADDR 0x0112 +#define CRDAT2_ADDR 0x0113 +#define CRDAT3_ADDR 0x0114 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0 +#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap WPUDA_ADDR WPUDA_ADDR SFR 0x000 // WPUDA +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap WDA_ADDR WDA_ADDR SFR 0x000 // WDA +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap CRCON_ADDR CRCON_ADDR SFR 0x000 // CRCON +#pragma memmap CRDAT0_ADDR CRDAT0_ADDR SFR 0x000 // CRDAT0 +#pragma memmap CRDAT1_ADDR CRDAT1_ADDR SFR 0x000 // CRDAT1 +#pragma memmap CRDAT2_ADDR CRDAT2_ADDR SFR 0x000 // CRDAT2 +#pragma memmap CRDAT3_ADDR CRDAT3_ADDR SFR 0x000 // CRDAT3 + + +// LIST +// P16F639.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F639 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F639 +// 2. LIST directive in the source file +// LIST P=PIC16F639 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 10/28/04 Original based on P16F636.INC +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F639 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ +//Bank 0 +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; + +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; + +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (CMCON0_ADDR) CMCON0; +extern sfr __at (CMCON1_ADDR) CMCON1; + +//Bank 1 +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; + +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; + +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (WPUDA_ADDR) WPUDA; +extern sfr __at (IOCA_ADDR) IOCA; +extern sfr __at (WDA_ADDR) WDA; + +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (EEDAT_ADDR) EEDAT; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//Bank 2 +extern sfr __at (CRCON_ADDR) CRCON; +extern sfr __at (CRDAT0_ADDR) CRDAT0; +extern sfr __at (CRDAT1_ADDR) CRDAT1; +extern sfr __at (CRDAT2_ADDR) CRDAT2; +extern sfr __at (CRDAT3_ADDR) CRDAT3; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- CMCON0 Bits ------------------------------------------------------- + + +//----- CMCON1 Bits ------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits -------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- IOCA -------------------------------------------------------------- + + +//----- EECON1 ------------------------------------------------------------- + + +//----- VRCON --------------------------------------------------------- + + + +//----- CRCON ------------------------------------------------------------- + + +//----- LVDCON ------------------------------------------------------------- + + +//----- WDA ------------------------------------------------------------- + + +//----- WPUDA ------------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F' +// __BADRAM H'86', H'88'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'C0'-H'EF' +// __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106', H'108'-H'109', H'186' +// __BADRAM H'188'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== +#define _WUREN_ON 0x2FFF +#define _WUREN_OFF 0x3FFF +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF + +// LIST + +// ----- CMCON0 bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON0_bits_t; +extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; + +#define CM0 CMCON0_bits.CM0 +#define CM1 CMCON0_bits.CM1 +#define CM2 CMCON0_bits.CM2 +#define CIS CMCON0_bits.CIS +#define C1INV CMCON0_bits.C1INV +#define C2INV CMCON0_bits.C2INV +#define C1OUT CMCON0_bits.C1OUT +#define C2OUT CMCON0_bits.C2OUT + +// ----- CMCON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __CMCON1_bits_t; +extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; + +#define C2SYNC CMCON1_bits.C2SYNC +#define T1GSS CMCON1_bits.T1GSS + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RAIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RAIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RAIF INTCON_bits.RAIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RAIE INTCON_bits.RAIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RAPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RAPU OPTION_REG_bits.NOT_RAPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char IOCA5:1; + unsigned char ENC_DEC:1; + unsigned char VREN:1; + }; + struct { + unsigned char IOCA0:1; + unsigned char IOCA1:1; + unsigned char IOCA2:1; + unsigned char IOCA3:1; + unsigned char IOCA4:1; + unsigned char VRR:1; + unsigned char :1; + unsigned char GO:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char LVDEN:1; + unsigned char IRVST:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char WDA4:1; + unsigned char WDA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char CRREG0:1; + unsigned char CRREG1:1; + unsigned char LVDL2:1; + unsigned char :1; + unsigned char WPUDA4:1; + unsigned char WPUDA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char LVDL0:1; + unsigned char LVDL1:1; + unsigned char WDA2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char WDA0:1; + unsigned char WDA1:1; + unsigned char WPUDA2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char WPUDA0:1; + unsigned char WPUDA1:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define IOCA0 OSCTUNE_bits.IOCA0 +#define RD OSCTUNE_bits.RD +#define VR0 OSCTUNE_bits.VR0 +#define CRREG0 OSCTUNE_bits.CRREG0 +#define LVDL0 OSCTUNE_bits.LVDL0 +#define WDA0 OSCTUNE_bits.WDA0 +#define WPUDA0 OSCTUNE_bits.WPUDA0 +#define TUN1 OSCTUNE_bits.TUN1 +#define IOCA1 OSCTUNE_bits.IOCA1 +#define WR OSCTUNE_bits.WR +#define VR1 OSCTUNE_bits.VR1 +#define CRREG1 OSCTUNE_bits.CRREG1 +#define LVDL1 OSCTUNE_bits.LVDL1 +#define WDA1 OSCTUNE_bits.WDA1 +#define WPUDA1 OSCTUNE_bits.WPUDA1 +#define TUN2 OSCTUNE_bits.TUN2 +#define IOCA2 OSCTUNE_bits.IOCA2 +#define WREN OSCTUNE_bits.WREN +#define VR2 OSCTUNE_bits.VR2 +#define LVDL2 OSCTUNE_bits.LVDL2 +#define WDA2 OSCTUNE_bits.WDA2 +#define WPUDA2 OSCTUNE_bits.WPUDA2 +#define TUN3 OSCTUNE_bits.TUN3 +#define IOCA3 OSCTUNE_bits.IOCA3 +#define WRERR OSCTUNE_bits.WRERR +#define VR3 OSCTUNE_bits.VR3 +#define TUN4 OSCTUNE_bits.TUN4 +#define IOCA4 OSCTUNE_bits.IOCA4 +#define LVDEN OSCTUNE_bits.LVDEN +#define WDA4 OSCTUNE_bits.WDA4 +#define WPUDA4 OSCTUNE_bits.WPUDA4 +#define IOCA5 OSCTUNE_bits.IOCA5 +#define VRR OSCTUNE_bits.VRR +#define IRVST OSCTUNE_bits.IRVST +#define WDA5 OSCTUNE_bits.WDA5 +#define WPUDA5 OSCTUNE_bits.WPUDA5 +#define ENC_DEC OSCTUNE_bits.ENC_DEC +#define VREN OSCTUNE_bits.VREN +#define GO OSCTUNE_bits.GO + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char NOT_WUR:1; + unsigned char SBODEN:1; + unsigned char ULPWUE:1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define NOT_WUR PCON_bits.NOT_WUR +#define SBODEN PCON_bits.SBODEN +#define ULPWUE PCON_bits.ULPWUE + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char :1; + unsigned char OSFIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char CRIE:1; + unsigned char LVDIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define OSFIE PIE1_bits.OSFIE +#define C1IE PIE1_bits.C1IE +#define C2IE PIE1_bits.C2IE +#define CRIE PIE1_bits.CRIE +#define LVDIE PIE1_bits.LVDIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char :1; + unsigned char OSFIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char CRIF:1; + unsigned char LVDIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define OSFIF PIR1_bits.OSFIF +#define C1IF PIR1_bits.C1IF +#define C2IF PIR1_bits.C2IF +#define CRIF PIR1_bits.CRIF +#define LVDIF PIR1_bits.LVDIF +#define EEIF PIR1_bits.EEIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char T1GINV:1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +#endif diff --git a/device/include/pic/pic16f648a.h b/device/include/pic/pic16f648a.h new file mode 100644 index 00000000..327369e1 --- /dev/null +++ b/device/include/pic/pic16f648a.h @@ -0,0 +1,614 @@ +// +// Register Declarations for Microchip 16F648A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F648A_H +#define P16F648A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CMCON_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define VRCON_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON + + +// LIST +// P16F648A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F648A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F648A +// 2. LIST directive in the source file +// LIST P=PIC16F648A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.00 14 Nov 2002 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F648A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +extern sfr __at (VRCON_ADDR) VRCON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + +//----- T2CON Bits --------------------------------------------------------- + +//----- CCP1CON Bits --------------------------------------------------------- + +//----- RCSTA Bits --------------------------------------------------------- + +//----- CMCON Bits --------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- TXSTA Bits ---------------------------------------------------------- + +//----- EECON1 Bits --------------------------------------------------------- + +//----- VRCON Bits --------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'01FF' +// __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' +// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF //Backwards compatability to 16F62X +#define _BODEN_OFF 0x3FBF //Backwards compatability to 16F62X +#define _BOREN_ON 0x3FFF +#define _BOREN_OFF 0x3FBF +#define _CP_ON 0x1FFF +#define _CP_OFF 0x3FFF +#define _DATA_CP_ON 0x3EFF +#define _DATA_CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _RC_OSC_CLKOUT 0x3FFF +#define _RC_OSC_NOCLKOUT 0x3FFE +#define _ER_OSC_CLKOUT 0x3FFF //Backwards compatability to 16F62X +#define _ER_OSC_NOCLKOUT 0x3FFE //Backwards compatability to 16F62X +#define _INTOSC_OSC_CLKOUT 0x3FFD +#define _INTOSC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD //Backwards compatability to 16F62X +#define _INTRC_OSC_NOCLKOUT 0x3FFC //Backwards compatability to 16F62X +#define _EXTCLK_OSC 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +// LIST + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char OSCF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define OSCF PCON_bits.OSCF + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char :1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char CMIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define CMIE PIE1_bits.CMIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char :1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char CMIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define CMIF PIR1_bits.CMIF +#define EEIF PIR1_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADEN RCSTA_bits.ADEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char VROE:1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VROE VRCON_bits.VROE +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16f676.h b/device/include/pic/pic16f676.h new file mode 100644 index 00000000..0d9abb50 --- /dev/null +++ b/device/include/pic/pic16f676.h @@ -0,0 +1,613 @@ +// +// Register Declarations for Microchip 16F676 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F676_H +#define P16F676_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define CMCON_ADDR 0x0019 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define OSCCAL_ADDR 0x0090 +#define ANSEL_ADDR 0x0091 +#define WPU_ADDR 0x0095 +#define WPUA_ADDR 0x0095 +#define IOC_ADDR 0x0096 +#define IOCA_ADDR 0x0096 +#define VRCON_ADDR 0x0099 +#define EEDATA_ADDR 0x009A +#define EEDAT_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16F676.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F676 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F676 +// 2. LIST directive in the source file +// LIST P=PIC16F676 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 05/13/02 Original + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F676 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; + +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; + +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; + +extern sfr __at (CMCON_ADDR) CMCON; + +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; + +extern sfr __at (PCON_ADDR) PCON; + +extern sfr __at (OSCCAL_ADDR) OSCCAL; +extern sfr __at (ANSEL_ADDR) ANSEL; + +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (WPUA_ADDR) WPUA; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (IOCA_ADDR) IOCA; + +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEDAT_ADDR) EEDAT; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- CMCON Bits -------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCAL Bits -------------------------------------------------------- + + +//----- ANSEL -------------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- EECON1 ------------------------------------------------------------- + + +//----- ADCON1 ------------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F' +// __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'92'-H'94', H'97'-H'98', H'E0'-H'FF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CPD 0x3EFF +#define _CPD_OFF 0x3FFF +#define _CP 0x3F7F +#define _CP_OFF 0x3FFF +#define _BODEN 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char :1; + unsigned char VCFG:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define VCFG ADCON0_bits.VCFG +#define ADFM ADCON0_bits.ADFM + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char CINV:1; + unsigned char :1; + unsigned char COUT:1; + unsigned char :1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define CINV CMCON_bits.CINV +#define COUT CMCON_bits.COUT + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RAIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RAIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RAIF INTCON_bits.RAIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RAIE INTCON_bits.RAIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_GPPU:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RAPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_GPPU OPTION_REG_bits.NOT_GPPU +#define NOT_RAPU OPTION_REG_bits.NOT_RAPU + +// ----- OSCCAL bits -------------------- +typedef union { + struct { + unsigned char ANS0:1; + unsigned char ANS1:1; + unsigned char CAL0:1; + unsigned char CAL1:1; + unsigned char CAL2:1; + unsigned char CAL3:1; + unsigned char CAL4:1; + unsigned char CAL5:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char ANS2:1; + unsigned char ANS3:1; + unsigned char ANS4:1; + unsigned char ANS5:1; + unsigned char ANS6:1; + unsigned char ANS7:1; + }; +} __OSCCAL_bits_t; +extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits; + +#define ANS0 OSCCAL_bits.ANS0 +#define ANS1 OSCCAL_bits.ANS1 +#define CAL0 OSCCAL_bits.CAL0 +#define ANS2 OSCCAL_bits.ANS2 +#define CAL1 OSCCAL_bits.CAL1 +#define ANS3 OSCCAL_bits.ANS3 +#define CAL2 OSCCAL_bits.CAL2 +#define ANS4 OSCCAL_bits.ANS4 +#define CAL3 OSCCAL_bits.CAL3 +#define ANS5 OSCCAL_bits.ANS5 +#define CAL4 OSCCAL_bits.CAL4 +#define ANS6 OSCCAL_bits.ANS6 +#define CAL5 OSCCAL_bits.CAL5 +#define ANS7 OSCCAL_bits.ANS7 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char T1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char EEIE:1; + }; + struct { + unsigned char TMR1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define T1IE PIE1_bits.T1IE +#define TMR1IE PIE1_bits.TMR1IE +#define CMIE PIE1_bits.CMIE +#define ADIE PIE1_bits.ADIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char T1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char EEIF:1; + }; + struct { + unsigned char TMR1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define T1IF PIR1_bits.T1IF +#define TMR1IF PIR1_bits.TMR1IF +#define CMIF PIR1_bits.CMIF +#define ADIF PIR1_bits.ADIF +#define EEIF PIR1_bits.EEIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char ADCS0:1; + unsigned char VRR:1; + unsigned char ADCS2:1; + unsigned char VREN:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char ADCS1:1; + unsigned char :1; + unsigned char :1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define RD VRCON_bits.RD +#define VR1 VRCON_bits.VR1 +#define WR VRCON_bits.WR +#define VR2 VRCON_bits.VR2 +#define WREN VRCON_bits.WREN +#define VR3 VRCON_bits.VR3 +#define WRERR VRCON_bits.WRERR +#define ADCS0 VRCON_bits.ADCS0 +#define VRR VRCON_bits.VRR +#define ADCS1 VRCON_bits.ADCS1 +#define ADCS2 VRCON_bits.ADCS2 +#define VREN VRCON_bits.VREN + +#endif diff --git a/device/include/pic/pic16f684.h b/device/include/pic/pic16f684.h new file mode 100644 index 00000000..c84287b8 --- /dev/null +++ b/device/include/pic/pic16f684.h @@ -0,0 +1,875 @@ +// +// Register Declarations for Microchip 16F684 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F684_H +#define P16F684_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0013 +#define CCPR1H_ADDR 0x0014 +#define CCP1CON_ADDR 0x0015 +#define PWM1CON_ADDR 0x0016 +#define ECCPAS_ADDR 0x0017 +#define WDTCON_ADDR 0x0018 +#define CMCON0_ADDR 0x0019 +#define CMCON1_ADDR 0x001A +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define ANSEL_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define WPU_ADDR 0x0095 +#define WPUA_ADDR 0x0095 +#define IOC_ADDR 0x0096 +#define IOCA_ADDR 0x0096 +#define VRCON_ADDR 0x0099 +#define EEDAT_ADDR 0x009A +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON +#pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0 +#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1 +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16F684.INC Standard Header File, Version 1.03 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F684 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F684 +// 2. LIST directive in the source file +// LIST P=PIC16F684 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 03/20/03 Original +//1.01 08/04/03 Updated CMCON1 address +//1.02 08/05/03 Updated names to match datasheet +//1.03 08/11/03 Updated ULPWUE bit name to match datasheet +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F684 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; + +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; + +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (PWM1CON_ADDR) PWM1CON; +extern sfr __at (ECCPAS_ADDR) ECCPAS; +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (CMCON0_ADDR) CMCON0; +extern sfr __at (CMCON1_ADDR) CMCON1; + +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; + +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (PR2_ADDR) PR2; + +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (WPUA_ADDR) WPUA; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (IOCA_ADDR) IOCA; + +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (EEDAT_ADDR) EEDAT; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- PWM1CON Bits ------------------------------------------------------- + + +//----- ECCPAS Bits -------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- CMCON0 Bits ------------------------------------------------------- + + +//----- CMCON1 Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits -------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- ANSEL -------------------------------------------------------------- + + +//----- IOC -------------------------------------------------------------- + + +//----- IOCA -------------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- EECON1 ------------------------------------------------------------- + + +//----- ADCON1 ------------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'FF' +// __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D' +// __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char :1; + unsigned char VCFG:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define VCFG ADCON0_bits.VCFG +#define ADFM ADCON0_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char P1M0:1; + unsigned char P1M1:1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 +#define P1M0 CCP1CON_bits.P1M0 +#define P1M1 CCP1CON_bits.P1M1 + +// ----- CMCON0 bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON0_bits_t; +extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; + +#define CM0 CMCON0_bits.CM0 +#define CM1 CMCON0_bits.CM1 +#define CM2 CMCON0_bits.CM2 +#define CIS CMCON0_bits.CIS +#define C1INV CMCON0_bits.C1INV +#define C2INV CMCON0_bits.C2INV +#define C1OUT CMCON0_bits.C1OUT +#define C2OUT CMCON0_bits.C2OUT + +// ----- CMCON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __CMCON1_bits_t; +extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; + +#define C2SYNC CMCON1_bits.C2SYNC +#define T1GSS CMCON1_bits.T1GSS + +// ----- ECCPAS bits -------------------- +typedef union { + struct { + unsigned char PSSBD0:1; + unsigned char PSSBD1:1; + unsigned char PSSAC0:1; + unsigned char PSSAC1:1; + unsigned char ECCPAS0:1; + unsigned char ECCPAS1:1; + unsigned char ECCPAS2:1; + unsigned char ECCPASE:1; + }; +} __ECCPAS_bits_t; +extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits; + +#define PSSBD0 ECCPAS_bits.PSSBD0 +#define PSSBD1 ECCPAS_bits.PSSBD1 +#define PSSAC0 ECCPAS_bits.PSSAC0 +#define PSSAC1 ECCPAS_bits.PSSAC1 +#define ECCPAS0 ECCPAS_bits.ECCPAS0 +#define ECCPAS1 ECCPAS_bits.ECCPAS1 +#define ECCPAS2 ECCPAS_bits.ECCPAS2 +#define ECCPASE ECCPAS_bits.ECCPASE + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RAIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RAIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RAIF INTCON_bits.RAIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RAIE INTCON_bits.RAIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RAPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RAPU OPTION_REG_bits.NOT_RAPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char ANS5:1; + unsigned char ANS6:1; + unsigned char ANS7:1; + }; + struct { + unsigned char ANS0:1; + unsigned char ANS1:1; + unsigned char ANS2:1; + unsigned char ANS3:1; + unsigned char ANS4:1; + unsigned char IOC5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOC0:1; + unsigned char IOC1:1; + unsigned char IOC2:1; + unsigned char IOC3:1; + unsigned char IOC4:1; + unsigned char IOCA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOCA0:1; + unsigned char IOCA1:1; + unsigned char IOCA2:1; + unsigned char IOCA3:1; + unsigned char IOCA4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define ANS0 OSCTUNE_bits.ANS0 +#define IOC0 OSCTUNE_bits.IOC0 +#define IOCA0 OSCTUNE_bits.IOCA0 +#define TUN1 OSCTUNE_bits.TUN1 +#define ANS1 OSCTUNE_bits.ANS1 +#define IOC1 OSCTUNE_bits.IOC1 +#define IOCA1 OSCTUNE_bits.IOCA1 +#define TUN2 OSCTUNE_bits.TUN2 +#define ANS2 OSCTUNE_bits.ANS2 +#define IOC2 OSCTUNE_bits.IOC2 +#define IOCA2 OSCTUNE_bits.IOCA2 +#define TUN3 OSCTUNE_bits.TUN3 +#define ANS3 OSCTUNE_bits.ANS3 +#define IOC3 OSCTUNE_bits.IOC3 +#define IOCA3 OSCTUNE_bits.IOCA3 +#define TUN4 OSCTUNE_bits.TUN4 +#define ANS4 OSCTUNE_bits.ANS4 +#define IOC4 OSCTUNE_bits.IOC4 +#define IOCA4 OSCTUNE_bits.IOCA4 +#define ANS5 OSCTUNE_bits.ANS5 +#define IOC5 OSCTUNE_bits.IOC5 +#define IOCA5 OSCTUNE_bits.IOCA5 +#define ANS6 OSCTUNE_bits.ANS6 +#define ANS7 OSCTUNE_bits.ANS7 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBODEN:1; + unsigned char ULPWUE:1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define SBODEN PCON_bits.SBODEN +#define ULPWUE PCON_bits.ULPWUE + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char T1IE:1; + unsigned char T2IE:1; + unsigned char OSFIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char CCP1IE:1; + unsigned char ADIE:1; + unsigned char EEIE:1; + }; + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define T1IE PIE1_bits.T1IE +#define TMR1IE PIE1_bits.TMR1IE +#define T2IE PIE1_bits.T2IE +#define TMR2IE PIE1_bits.TMR2IE +#define OSFIE PIE1_bits.OSFIE +#define C1IE PIE1_bits.C1IE +#define C2IE PIE1_bits.C2IE +#define CCP1IE PIE1_bits.CCP1IE +#define ADIE PIE1_bits.ADIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char T1IF:1; + unsigned char T2IF:1; + unsigned char OSFIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char CCP1IF:1; + unsigned char ADIF:1; + unsigned char EEIF:1; + }; + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define T1IF PIR1_bits.T1IF +#define TMR1IF PIR1_bits.TMR1IF +#define T2IF PIR1_bits.T2IF +#define TMR2IF PIR1_bits.TMR2IF +#define OSFIF PIR1_bits.OSFIF +#define C1IF PIR1_bits.C1IF +#define C2IF PIR1_bits.C2IF +#define CCP1IF PIR1_bits.CCP1IF +#define ADIF PIR1_bits.ADIF +#define EEIF PIR1_bits.EEIF + +// ----- PWM1CON bits -------------------- +typedef union { + struct { + unsigned char PDC0:1; + unsigned char PDC1:1; + unsigned char PDC2:1; + unsigned char PDC3:1; + unsigned char PDC4:1; + unsigned char PDC5:1; + unsigned char PDC6:1; + unsigned char PRSEN:1; + }; +} __PWM1CON_bits_t; +extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits; + +#define PDC0 PWM1CON_bits.PDC0 +#define PDC1 PWM1CON_bits.PDC1 +#define PDC2 PWM1CON_bits.PDC2 +#define PDC3 PWM1CON_bits.PDC3 +#define PDC4 PWM1CON_bits.PDC4 +#define PDC5 PWM1CON_bits.PDC5 +#define PDC6 PWM1CON_bits.PDC6 +#define PRSEN PWM1CON_bits.PRSEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char T1GINV:1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char ADCS0:1; + unsigned char VRR:1; + unsigned char ADCS2:1; + unsigned char VREN:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char ADCS1:1; + unsigned char :1; + unsigned char :1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define RD VRCON_bits.RD +#define VR1 VRCON_bits.VR1 +#define WR VRCON_bits.WR +#define VR2 VRCON_bits.VR2 +#define WREN VRCON_bits.WREN +#define VR3 VRCON_bits.VR3 +#define WRERR VRCON_bits.WRERR +#define ADCS0 VRCON_bits.ADCS0 +#define VRR VRCON_bits.VRR +#define ADCS1 VRCON_bits.ADCS1 +#define ADCS2 VRCON_bits.ADCS2 +#define VREN VRCON_bits.VREN + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +#endif diff --git a/device/include/pic/pic16f685.h b/device/include/pic/pic16f685.h new file mode 100644 index 00000000..c24b771b --- /dev/null +++ b/device/include/pic/pic16f685.h @@ -0,0 +1,1173 @@ +// +// Register Declarations for Microchip 16F685 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F685_H +#define P16F685_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define PWM1CON_ADDR 0x001C +#define ECCPAS_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define PR2_ADDR 0x0092 +#define WPU_ADDR 0x0095 +#define WPUA_ADDR 0x0095 +#define IOC_ADDR 0x0096 +#define IOCA_ADDR 0x0096 +#define WDTCON_ADDR 0x0097 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define WPUB_ADDR 0x0115 +#define IOCB_ADDR 0x0116 +#define VRCON_ADDR 0x0118 +#define CM1CON0_ADDR 0x0119 +#define CM2CON0_ADDR 0x011A +#define CM2CON1_ADDR 0x011B +#define ANSEL_ADDR 0x011E +#define ANSELH_ADDR 0x011F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D +#define PSTRCON_ADDR 0x019D +#define SRCON_ADDR 0x019E + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON +#pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0 +#pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0 +#pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1 +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ANSELH_ADDR ANSELH_ADDR SFR 0x000 // ANSELH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap PSTRCON_ADDR PSTRCON_ADDR SFR 0x000 // PSTRCON +#pragma memmap SRCON_ADDR SRCON_ADDR SFR 0x000 // SRCON + + +// LIST +// P16F685.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F685 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F685 +// 2. LIST directive in the source file +// LIST P=PIC16F685 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 10/12/04 Original +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F685 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; + + +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; + + +extern sfr __at (PWM1CON_ADDR) PWM1CON; +extern sfr __at (ECCPAS_ADDR) ECCPAS; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; + +extern sfr __at (PR2_ADDR) PR2; + + +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (WPUA_ADDR) WPUA; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (IOCA_ADDR) IOCA; +extern sfr __at (WDTCON_ADDR) WDTCON; + + + +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + + + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + + +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (IOCB_ADDR) IOCB; + +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (CM1CON0_ADDR) CM1CON0; +extern sfr __at (CM2CON0_ADDR) CM2CON0; +extern sfr __at (CM2CON1_ADDR) CM2CON1; + +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ANSELH_ADDR) ANSELH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + + +extern sfr __at (PSTRCON_ADDR) PSTRCON; +extern sfr __at (SRCON_ADDR) SRCON; + + + +//----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- PWM1CON Bits ------------------------------------------------------- + + +//----- ECCPAS Bits -------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISA Bits -------------------------------------------------------- + + +//----- TRISB Bits -------------------------------------------------------- + + +//----- TRISC Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits -------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- WPUA -------------------------------------------------------------- + + + +//----- IOC -------------------------------------------------------------- + + +//----- IOCA -------------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- ADCON1 ------------------------------------------------------------- + + +//----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- +//----- WPUB Bits ---------------------------------------------------------- + + +//----- IOCB -------------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- CM1CON0 Bits ------------------------------------------------------- + + + +//----- CM2CON0 Bits ------------------------------------------------------- + + + +//----- CM2CON1 Bits ------------------------------------------------------- + + +//----- ANSEL -------------------------------------------------------------- + + +//----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- +//----- EECON1 ------------------------------------------------------------- + + +//----- PSTRCON ------------------------------------------------------------- + + +//----- SRCON --------------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09', H'13'-H'14', H'18'-H'1B' +// __BADRAM H'88'-H'89', H'91', H'93'-H'94', H'98'-H'9D' +// __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D' +// __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char CHS3:1; + unsigned char VCFG:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define CHS3 ADCON0_bits.CHS3 +#define VCFG ADCON0_bits.VCFG +#define ADFM ADCON0_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char P1M0:1; + unsigned char P1M1:1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 +#define P1M0 CCP1CON_bits.P1M0 +#define P1M1 CCP1CON_bits.P1M1 + +// ----- CM1CON0 bits -------------------- +typedef union { + struct { + unsigned char C1CH0:1; + unsigned char C1CH1:1; + unsigned char C1R:1; + unsigned char :1; + unsigned char C1POL:1; + unsigned char C1OE:1; + unsigned char C1OUT:1; + unsigned char C1ON:1; + }; +} __CM1CON0_bits_t; +extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; + +#define C1CH0 CM1CON0_bits.C1CH0 +#define C1CH1 CM1CON0_bits.C1CH1 +#define C1R CM1CON0_bits.C1R +#define C1POL CM1CON0_bits.C1POL +#define C1OE CM1CON0_bits.C1OE +#define C1OUT CM1CON0_bits.C1OUT +#define C1ON CM1CON0_bits.C1ON + +// ----- CM2CON0 bits -------------------- +typedef union { + struct { + unsigned char C2CH0:1; + unsigned char C2CH1:1; + unsigned char C2R:1; + unsigned char :1; + unsigned char C2POL:1; + unsigned char C2OE:1; + unsigned char C2OUT:1; + unsigned char C2ON:1; + }; +} __CM2CON0_bits_t; +extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; + +#define C2CH0 CM2CON0_bits.C2CH0 +#define C2CH1 CM2CON0_bits.C2CH1 +#define C2R CM2CON0_bits.C2R +#define C2POL CM2CON0_bits.C2POL +#define C2OE CM2CON0_bits.C2OE +#define C2OUT CM2CON0_bits.C2OUT +#define C2ON CM2CON0_bits.C2ON + +// ----- CM2CON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char ANS2:1; + unsigned char ANS3:1; + unsigned char ANS4:1; + unsigned char ANS5:1; + unsigned char MC2OUT:1; + unsigned char MC1OUT:1; + }; + struct { + unsigned char ANS0:1; + unsigned char ANS1:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char STRSYNC:1; + unsigned char C1SEN:1; + unsigned char ANS6:1; + unsigned char ANS7:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char STRC:1; + unsigned char STRD:1; + unsigned char C2REN:1; + unsigned char :1; + unsigned char SR0:1; + unsigned char EEPGD:1; + }; + struct { + unsigned char STRA:1; + unsigned char STRB:1; + unsigned char PULSR:1; + unsigned char PULSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char SR1:1; + }; +} __CM2CON1_bits_t; +extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; + +#define C2SYNC CM2CON1_bits.C2SYNC +#define ANS0 CM2CON1_bits.ANS0 +#define RD CM2CON1_bits.RD +#define STRA CM2CON1_bits.STRA +#define T1GSS CM2CON1_bits.T1GSS +#define ANS1 CM2CON1_bits.ANS1 +#define WR CM2CON1_bits.WR +#define STRB CM2CON1_bits.STRB +#define ANS2 CM2CON1_bits.ANS2 +#define WREN CM2CON1_bits.WREN +#define STRC CM2CON1_bits.STRC +#define PULSR CM2CON1_bits.PULSR +#define ANS3 CM2CON1_bits.ANS3 +#define WRERR CM2CON1_bits.WRERR +#define STRD CM2CON1_bits.STRD +#define PULSS CM2CON1_bits.PULSS +#define ANS4 CM2CON1_bits.ANS4 +#define STRSYNC CM2CON1_bits.STRSYNC +#define C2REN CM2CON1_bits.C2REN +#define ANS5 CM2CON1_bits.ANS5 +#define C1SEN CM2CON1_bits.C1SEN +#define MC2OUT CM2CON1_bits.MC2OUT +#define ANS6 CM2CON1_bits.ANS6 +#define SR0 CM2CON1_bits.SR0 +#define MC1OUT CM2CON1_bits.MC1OUT +#define ANS7 CM2CON1_bits.ANS7 +#define EEPGD CM2CON1_bits.EEPGD +#define SR1 CM2CON1_bits.SR1 + +// ----- ECCPAS bits -------------------- +typedef union { + struct { + unsigned char PSSBD0:1; + unsigned char PSSBD1:1; + unsigned char PSSAC0:1; + unsigned char PSSAC1:1; + unsigned char ECCPAS0:1; + unsigned char ECCPAS1:1; + unsigned char ECCPAS2:1; + unsigned char ECCPASE:1; + }; +} __ECCPAS_bits_t; +extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits; + +#define PSSBD0 ECCPAS_bits.PSSBD0 +#define PSSBD1 ECCPAS_bits.PSSBD1 +#define PSSAC0 ECCPAS_bits.PSSAC0 +#define PSSAC1 ECCPAS_bits.PSSAC1 +#define ECCPAS0 ECCPAS_bits.ECCPAS0 +#define ECCPAS1 ECCPAS_bits.ECCPAS1 +#define ECCPAS2 ECCPAS_bits.ECCPAS2 +#define ECCPASE ECCPAS_bits.ECCPASE + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RABIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RABIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RABIF INTCON_bits.RABIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RABIE INTCON_bits.RABIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RABPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RABPU OPTION_REG_bits.NOT_RABPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char WPUA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char WPUA0:1; + unsigned char WPUA1:1; + unsigned char WPUA2:1; + unsigned char IOC3:1; + unsigned char WPUA4:1; + unsigned char IOC5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOC0:1; + unsigned char IOC1:1; + unsigned char IOC2:1; + unsigned char IOCA3:1; + unsigned char IOC4:1; + unsigned char IOCA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOCA0:1; + unsigned char IOCA1:1; + unsigned char IOCA2:1; + unsigned char :1; + unsigned char IOCA4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define WPUA0 OSCTUNE_bits.WPUA0 +#define IOC0 OSCTUNE_bits.IOC0 +#define IOCA0 OSCTUNE_bits.IOCA0 +#define TUN1 OSCTUNE_bits.TUN1 +#define WPUA1 OSCTUNE_bits.WPUA1 +#define IOC1 OSCTUNE_bits.IOC1 +#define IOCA1 OSCTUNE_bits.IOCA1 +#define TUN2 OSCTUNE_bits.TUN2 +#define WPUA2 OSCTUNE_bits.WPUA2 +#define IOC2 OSCTUNE_bits.IOC2 +#define IOCA2 OSCTUNE_bits.IOCA2 +#define TUN3 OSCTUNE_bits.TUN3 +#define IOC3 OSCTUNE_bits.IOC3 +#define IOCA3 OSCTUNE_bits.IOCA3 +#define TUN4 OSCTUNE_bits.TUN4 +#define WPUA4 OSCTUNE_bits.WPUA4 +#define IOC4 OSCTUNE_bits.IOC4 +#define IOCA4 OSCTUNE_bits.IOCA4 +#define WPUA5 OSCTUNE_bits.WPUA5 +#define IOC5 OSCTUNE_bits.IOC5 +#define IOCA5 OSCTUNE_bits.IOCA5 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBODEN:1; + unsigned char ULPWUE:1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define SBODEN PCON_bits.SBODEN +#define ULPWUE PCON_bits.ULPWUE + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char T1IE:1; + unsigned char T2IE:1; + unsigned char CCPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define T1IE PIE1_bits.T1IE +#define TMR1IE PIE1_bits.TMR1IE +#define T2IE PIE1_bits.T2IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCPIE PIE1_bits.CCPIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE +#define C1IE PIE2_bits.C1IE +#define C2IE PIE2_bits.C2IE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char T1IF:1; + unsigned char T2IF:1; + unsigned char CCP1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define T1IF PIR1_bits.T1IF +#define TMR1IF PIR1_bits.TMR1IF +#define T2IF PIR1_bits.T2IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF +#define C1IF PIR2_bits.C1IF +#define C2IF PIR2_bits.C2IF +#define OSFIF PIR2_bits.OSFIF + +// ----- PWM1CON bits -------------------- +typedef union { + struct { + unsigned char PDC0:1; + unsigned char PDC1:1; + unsigned char PDC2:1; + unsigned char PDC3:1; + unsigned char PDC4:1; + unsigned char PDC5:1; + unsigned char PDC6:1; + unsigned char PRSEN:1; + }; +} __PWM1CON_bits_t; +extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits; + +#define PDC0 PWM1CON_bits.PDC0 +#define PDC1 PWM1CON_bits.PDC1 +#define PDC2 PWM1CON_bits.PDC2 +#define PDC3 PWM1CON_bits.PDC3 +#define PDC4 PWM1CON_bits.PDC4 +#define PDC5 PWM1CON_bits.PDC5 +#define PDC6 PWM1CON_bits.PDC6 +#define PRSEN PWM1CON_bits.PRSEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char T1GINV:1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISA bits -------------------- +typedef union { + struct { + unsigned char TRISA0:1; + unsigned char TRISA1:1; + unsigned char TRISA2:1; + unsigned char TRISA3:1; + unsigned char TRISA4:1; + unsigned char TRISA5:1; + unsigned char :1; + unsigned char :1; + }; +} __TRISA_bits_t; +extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits; + +#define TRISA0 TRISA_bits.TRISA0 +#define TRISA1 TRISA_bits.TRISA1 +#define TRISA2 TRISA_bits.TRISA2 +#define TRISA3 TRISA_bits.TRISA3 +#define TRISA4 TRISA_bits.TRISA4 +#define TRISA5 TRISA_bits.TRISA5 + +// ----- TRISB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TRISB4:1; + unsigned char TRISB5:1; + unsigned char TRISB6:1; + unsigned char TRISB7:1; + }; +} __TRISB_bits_t; +extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; + +#define TRISB4 TRISB_bits.TRISB4 +#define TRISB5 TRISB_bits.TRISB5 +#define TRISB6 TRISB_bits.TRISB6 +#define TRISB7 TRISB_bits.TRISB7 + +// ----- TRISC bits -------------------- +typedef union { + struct { + unsigned char TRISC0:1; + unsigned char TRISC1:1; + unsigned char TRISC2:1; + unsigned char TRISC3:1; + unsigned char TRISC4:1; + unsigned char TRISC5:1; + unsigned char TRISC6:1; + unsigned char TRISC7:1; + }; +} __TRISC_bits_t; +extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits; + +#define TRISC0 TRISC_bits.TRISC0 +#define TRISC1 TRISC_bits.TRISC1 +#define TRISC2 TRISC_bits.TRISC2 +#define TRISC3 TRISC_bits.TRISC3 +#define TRISC4 TRISC_bits.TRISC4 +#define TRISC5 TRISC_bits.TRISC5 +#define TRISC6 TRISC_bits.TRISC6 +#define TRISC7 TRISC_bits.TRISC7 + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char VP6EN:1; + unsigned char VRR:1; + unsigned char C2VREN:1; + unsigned char C1VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VP6EN VRCON_bits.VP6EN +#define VRR VRCON_bits.VRR +#define C2VREN VRCON_bits.C2VREN +#define C1VREN VRCON_bits.C1VREN + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char ADCS1:1; + unsigned char ADCS2:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 +#define ADCS0 WDTCON_bits.ADCS0 +#define ADCS1 WDTCON_bits.ADCS1 +#define ADCS2 WDTCON_bits.ADCS2 + +// ----- WPUB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char WPUB4:1; + unsigned char WPUB5:1; + unsigned char WPUB6:1; + unsigned char WPUB7:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOCB4:1; + unsigned char IOCB5:1; + unsigned char IOCB6:1; + unsigned char IOCB7:1; + }; +} __WPUB_bits_t; +extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + +#define WPUB4 WPUB_bits.WPUB4 +#define IOCB4 WPUB_bits.IOCB4 +#define WPUB5 WPUB_bits.WPUB5 +#define IOCB5 WPUB_bits.IOCB5 +#define WPUB6 WPUB_bits.WPUB6 +#define IOCB6 WPUB_bits.IOCB6 +#define WPUB7 WPUB_bits.WPUB7 +#define IOCB7 WPUB_bits.IOCB7 + +#endif diff --git a/device/include/pic/pic16f687.h b/device/include/pic/pic16f687.h new file mode 100644 index 00000000..eae5e92d --- /dev/null +++ b/device/include/pic/pic16f687.h @@ -0,0 +1,1259 @@ +// +// Register Declarations for Microchip 16F687 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F687_H +#define P16F687_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define SSPADD_ADDR 0x0093 +#define MSK_ADDR 0x0093 +#define SSPMSK_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPU_ADDR 0x0095 +#define WPUA_ADDR 0x0095 +#define IOC_ADDR 0x0096 +#define IOCA_ADDR 0x0096 +#define WDTCON_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define SPBRGH_ADDR 0x009A +#define BAUDCTL_ADDR 0x009B +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define WPUB_ADDR 0x0115 +#define IOCB_ADDR 0x0116 +#define VRCON_ADDR 0x0118 +#define CM1CON0_ADDR 0x0119 +#define CM2CON0_ADDR 0x011A +#define CM2CON1_ADDR 0x011B +#define ANSEL_ADDR 0x011E +#define ANSELH_ADDR 0x011F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D +#define SRCON_ADDR 0x019E + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap MSK_ADDR MSK_ADDR SFR 0x000 // MSK +#pragma memmap SSPMSK_ADDR SSPMSK_ADDR SFR 0x000 // SSPMSK +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap SPBRGH_ADDR SPBRGH_ADDR SFR 0x000 // SPBRGH +#pragma memmap BAUDCTL_ADDR BAUDCTL_ADDR SFR 0x000 // BAUDCTL +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0 +#pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0 +#pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1 +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ANSELH_ADDR ANSELH_ADDR SFR 0x000 // ANSELH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap SRCON_ADDR SRCON_ADDR SFR 0x000 // SRCON + + +// LIST +// P16F687.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F687 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F687 +// 2. LIST directive in the source file +// LIST P=PIC16F687 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 10/12/04 Original +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F687 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; + + +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; + + +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; + +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; + +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (MSK_ADDR) MSK; +extern sfr __at (SSPMSK_ADDR) SSPMSK; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (WPUA_ADDR) WPUA; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (IOCA_ADDR) IOCA; +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (SPBRGH_ADDR) SPBRGH; +extern sfr __at (BAUDCTL_ADDR) BAUDCTL; + + +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + + + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + + +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (IOCB_ADDR) IOCB; + +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (CM1CON0_ADDR) CM1CON0; +extern sfr __at (CM2CON0_ADDR) CM2CON0; +extern sfr __at (CM2CON1_ADDR) CM2CON1; + +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ANSELH_ADDR) ANSELH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + + +extern sfr __at (SRCON_ADDR) SRCON; + + + +//----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + + +//----- SSPCON Bits ------------------------------------------------------- + + + +//----- RCSTA Bits --------------------------------------------------------- + + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISA Bits -------------------------------------------------------- + + +//----- TRISB Bits -------------------------------------------------------- + + +//----- TRISC Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits -------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- SSPSTAT Bits -------------------------------------------------------- + + +//----- WPUA -------------------------------------------------------------- + + + +//----- IOC -------------------------------------------------------------- + + +//----- IOCA -------------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- TXSTA Bits ------------------------------------------------------- + + +//----- SPBRG Bits ------------------------------------------------------- + + +//----- SPBRGH Bits ------------------------------------------------------- + + +//----- BAUDCTL Bits ------------------------------------------------------- + + + + +//----- ADCON1 ------------------------------------------------------------- + + +//----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- +//----- WPUB Bits ---------------------------------------------------------- + + +//----- IOCB -------------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- CM1CON0 Bits ------------------------------------------------------- + + + +//----- CM2CON0 Bits ------------------------------------------------------- + + + +//----- CM2CON1 Bits ------------------------------------------------------- + + +//----- ANSEL -------------------------------------------------------------- + + +//----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- +//----- EECON1 ------------------------------------------------------------- + + +//----- SRCON --------------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'17', H'1B'- H'1D' +// __BADRAM H'88'-H'89', H'91'-H'92', H'9C'-H'9D', H'C0'-H'EF' +// __BADRAM H'108'-H'109', H'10F'-H'114', H'117', H'11C'-H'11D', H'120'-H'16F' +// __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char CHS3:1; + unsigned char VCFG:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define CHS3 ADCON0_bits.CHS3 +#define VCFG ADCON0_bits.VCFG +#define ADFM ADCON0_bits.ADFM + +// ----- BAUDCTL bits -------------------- +typedef union { + struct { + unsigned char ABDEN:1; + unsigned char WUE:1; + unsigned char :1; + unsigned char BRG16:1; + unsigned char CKTXP:1; + unsigned char ADCS1:1; + unsigned char RCIDL:1; + unsigned char ABDOVF:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char :1; + unsigned char ADCS2:1; + unsigned char :1; + }; +} __BAUDCTL_bits_t; +extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits; + +#define ABDEN BAUDCTL_bits.ABDEN +#define WUE BAUDCTL_bits.WUE +#define BRG16 BAUDCTL_bits.BRG16 +#define CKTXP BAUDCTL_bits.CKTXP +#define ADCS0 BAUDCTL_bits.ADCS0 +#define ADCS1 BAUDCTL_bits.ADCS1 +#define RCIDL BAUDCTL_bits.RCIDL +#define ADCS2 BAUDCTL_bits.ADCS2 +#define ABDOVF BAUDCTL_bits.ABDOVF + +// ----- CM1CON0 bits -------------------- +typedef union { + struct { + unsigned char C1CH0:1; + unsigned char C1CH1:1; + unsigned char C1R:1; + unsigned char :1; + unsigned char C1POL:1; + unsigned char C1OE:1; + unsigned char C1OUT:1; + unsigned char C1ON:1; + }; +} __CM1CON0_bits_t; +extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; + +#define C1CH0 CM1CON0_bits.C1CH0 +#define C1CH1 CM1CON0_bits.C1CH1 +#define C1R CM1CON0_bits.C1R +#define C1POL CM1CON0_bits.C1POL +#define C1OE CM1CON0_bits.C1OE +#define C1OUT CM1CON0_bits.C1OUT +#define C1ON CM1CON0_bits.C1ON + +// ----- CM2CON0 bits -------------------- +typedef union { + struct { + unsigned char C2CH0:1; + unsigned char C2CH1:1; + unsigned char C2R:1; + unsigned char :1; + unsigned char C2POL:1; + unsigned char C2OE:1; + unsigned char C2OUT:1; + unsigned char C2ON:1; + }; +} __CM2CON0_bits_t; +extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; + +#define C2CH0 CM2CON0_bits.C2CH0 +#define C2CH1 CM2CON0_bits.C2CH1 +#define C2R CM2CON0_bits.C2R +#define C2POL CM2CON0_bits.C2POL +#define C2OE CM2CON0_bits.C2OE +#define C2OUT CM2CON0_bits.C2OUT +#define C2ON CM2CON0_bits.C2ON + +// ----- CM2CON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char ANS2:1; + unsigned char ANS3:1; + unsigned char ANS4:1; + unsigned char ANS5:1; + unsigned char MC2OUT:1; + unsigned char MC1OUT:1; + }; + struct { + unsigned char ANS0:1; + unsigned char ANS1:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char C2REN:1; + unsigned char C1SEN:1; + unsigned char ANS6:1; + unsigned char ANS7:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char PULSR:1; + unsigned char PULSS:1; + unsigned char :1; + unsigned char :1; + unsigned char SR0:1; + unsigned char EEPGD:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char SR1:1; + }; +} __CM2CON1_bits_t; +extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; + +#define C2SYNC CM2CON1_bits.C2SYNC +#define ANS0 CM2CON1_bits.ANS0 +#define RD CM2CON1_bits.RD +#define T1GSS CM2CON1_bits.T1GSS +#define ANS1 CM2CON1_bits.ANS1 +#define WR CM2CON1_bits.WR +#define ANS2 CM2CON1_bits.ANS2 +#define WREN CM2CON1_bits.WREN +#define PULSR CM2CON1_bits.PULSR +#define ANS3 CM2CON1_bits.ANS3 +#define WRERR CM2CON1_bits.WRERR +#define PULSS CM2CON1_bits.PULSS +#define ANS4 CM2CON1_bits.ANS4 +#define C2REN CM2CON1_bits.C2REN +#define ANS5 CM2CON1_bits.ANS5 +#define C1SEN CM2CON1_bits.C1SEN +#define MC2OUT CM2CON1_bits.MC2OUT +#define ANS6 CM2CON1_bits.ANS6 +#define SR0 CM2CON1_bits.SR0 +#define MC1OUT CM2CON1_bits.MC1OUT +#define ANS7 CM2CON1_bits.ANS7 +#define EEPGD CM2CON1_bits.EEPGD +#define SR1 CM2CON1_bits.SR1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RABIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RABIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RABIF INTCON_bits.RABIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RABIE INTCON_bits.RABIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RABPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RABPU OPTION_REG_bits.NOT_RABPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBODEN:1; + unsigned char ULPWUE:1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define SBODEN PCON_bits.SBODEN +#define ULPWUE PCON_bits.ULPWUE + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char T1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; + struct { + unsigned char TMR1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define T1IE PIE1_bits.T1IE +#define TMR1IE PIE1_bits.TMR1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE +#define C1IE PIE2_bits.C1IE +#define C2IE PIE2_bits.C2IE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char T1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; + struct { + unsigned char TMR1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define T1IF PIR1_bits.T1IF +#define TMR1IF PIR1_bits.TMR1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF +#define C1IF PIR2_bits.C1IF +#define C2IF PIR2_bits.C2IF +#define OSFIF PIR2_bits.OSFIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define SPEN RCSTA_bits.SPEN + +// ----- SPBRG bits -------------------- +typedef union { + struct { + unsigned char BRG0:1; + unsigned char BRG1:1; + unsigned char BRG2:1; + unsigned char BRG3:1; + unsigned char BRG4:1; + unsigned char BRG5:1; + unsigned char BRG6:1; + unsigned char BRG7:1; + }; +} __SPBRG_bits_t; +extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits; + +#define BRG0 SPBRG_bits.BRG0 +#define BRG1 SPBRG_bits.BRG1 +#define BRG2 SPBRG_bits.BRG2 +#define BRG3 SPBRG_bits.BRG3 +#define BRG4 SPBRG_bits.BRG4 +#define BRG5 SPBRG_bits.BRG5 +#define BRG6 SPBRG_bits.BRG6 +#define BRG7 SPBRG_bits.BRG7 + +// ----- SPBRGH bits -------------------- +typedef union { + struct { + unsigned char BRG8:1; + unsigned char BRG9:1; + unsigned char BRG10:1; + unsigned char BRG11:1; + unsigned char BRG12:1; + unsigned char BRG13:1; + unsigned char BRG14:1; + unsigned char BRG15:1; + }; +} __SPBRGH_bits_t; +extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits; + +#define BRG8 SPBRGH_bits.BRG8 +#define BRG9 SPBRGH_bits.BRG9 +#define BRG10 SPBRGH_bits.BRG10 +#define BRG11 SPBRGH_bits.BRG11 +#define BRG12 SPBRGH_bits.BRG12 +#define BRG13 SPBRGH_bits.BRG13 +#define BRG14 SPBRGH_bits.BRG14 +#define BRG15 SPBRGH_bits.BRG15 + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R_W_NOT:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D_A_NOT:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char WPUA0:1; + unsigned char WPUA1:1; + unsigned char WPUA2:1; + unsigned char IOC3:1; + unsigned char WPUA4:1; + unsigned char WPUA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOC0:1; + unsigned char IOC1:1; + unsigned char IOC2:1; + unsigned char IOCA3:1; + unsigned char IOC4:1; + unsigned char IOC5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOCA0:1; + unsigned char IOCA1:1; + unsigned char IOCA2:1; + unsigned char :1; + unsigned char IOCA4:1; + unsigned char IOCA5:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define WPUA0 SSPSTAT_bits.WPUA0 +#define IOC0 SSPSTAT_bits.IOC0 +#define IOCA0 SSPSTAT_bits.IOCA0 +#define UA SSPSTAT_bits.UA +#define WPUA1 SSPSTAT_bits.WPUA1 +#define IOC1 SSPSTAT_bits.IOC1 +#define IOCA1 SSPSTAT_bits.IOCA1 +#define R_W_NOT SSPSTAT_bits.R_W_NOT +#define WPUA2 SSPSTAT_bits.WPUA2 +#define IOC2 SSPSTAT_bits.IOC2 +#define IOCA2 SSPSTAT_bits.IOCA2 +#define S SSPSTAT_bits.S +#define IOC3 SSPSTAT_bits.IOC3 +#define IOCA3 SSPSTAT_bits.IOCA3 +#define P SSPSTAT_bits.P +#define WPUA4 SSPSTAT_bits.WPUA4 +#define IOC4 SSPSTAT_bits.IOC4 +#define IOCA4 SSPSTAT_bits.IOCA4 +#define D_A_NOT SSPSTAT_bits.D_A_NOT +#define WPUA5 SSPSTAT_bits.WPUA5 +#define IOC5 SSPSTAT_bits.IOC5 +#define IOCA5 SSPSTAT_bits.IOCA5 +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char T1GINV:1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- TRISA bits -------------------- +typedef union { + struct { + unsigned char TRISA0:1; + unsigned char TRISA1:1; + unsigned char TRISA2:1; + unsigned char TRISA3:1; + unsigned char TRISA4:1; + unsigned char TRISA5:1; + unsigned char :1; + unsigned char :1; + }; +} __TRISA_bits_t; +extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits; + +#define TRISA0 TRISA_bits.TRISA0 +#define TRISA1 TRISA_bits.TRISA1 +#define TRISA2 TRISA_bits.TRISA2 +#define TRISA3 TRISA_bits.TRISA3 +#define TRISA4 TRISA_bits.TRISA4 +#define TRISA5 TRISA_bits.TRISA5 + +// ----- TRISB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TRISB4:1; + unsigned char TRISB5:1; + unsigned char TRISB6:1; + unsigned char TRISB7:1; + }; +} __TRISB_bits_t; +extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; + +#define TRISB4 TRISB_bits.TRISB4 +#define TRISB5 TRISB_bits.TRISB5 +#define TRISB6 TRISB_bits.TRISB6 +#define TRISB7 TRISB_bits.TRISB7 + +// ----- TRISC bits -------------------- +typedef union { + struct { + unsigned char TRISC0:1; + unsigned char TRISC1:1; + unsigned char TRISC2:1; + unsigned char TRISC3:1; + unsigned char TRISC4:1; + unsigned char TRISC5:1; + unsigned char TRISC6:1; + unsigned char TRISC7:1; + }; +} __TRISC_bits_t; +extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits; + +#define TRISC0 TRISC_bits.TRISC0 +#define TRISC1 TRISC_bits.TRISC1 +#define TRISC2 TRISC_bits.TRISC2 +#define TRISC3 TRISC_bits.TRISC3 +#define TRISC4 TRISC_bits.TRISC4 +#define TRISC5 TRISC_bits.TRISC5 +#define TRISC6 TRISC_bits.TRISC6 +#define TRISC7 TRISC_bits.TRISC7 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char SENB:1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SENB TXSTA_bits.SENB +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char VP6EN:1; + unsigned char VRR:1; + unsigned char C2VREN:1; + unsigned char C1VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VP6EN VRCON_bits.VP6EN +#define VRR VRCON_bits.VRR +#define C2VREN VRCON_bits.C2VREN +#define C1VREN VRCON_bits.C1VREN + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +// ----- WPUB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char WPUB4:1; + unsigned char WPUB5:1; + unsigned char WPUB6:1; + unsigned char WPUB7:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOCB4:1; + unsigned char IOCB5:1; + unsigned char IOCB6:1; + unsigned char IOCB7:1; + }; +} __WPUB_bits_t; +extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + +#define WPUB4 WPUB_bits.WPUB4 +#define IOCB4 WPUB_bits.IOCB4 +#define WPUB5 WPUB_bits.WPUB5 +#define IOCB5 WPUB_bits.IOCB5 +#define WPUB6 WPUB_bits.WPUB6 +#define IOCB6 WPUB_bits.IOCB6 +#define WPUB7 WPUB_bits.WPUB7 +#define IOCB7 WPUB_bits.IOCB7 + +#endif diff --git a/device/include/pic/pic16f688.h b/device/include/pic/pic16f688.h new file mode 100644 index 00000000..7742adee --- /dev/null +++ b/device/include/pic/pic16f688.h @@ -0,0 +1,842 @@ +// +// Register Declarations for Microchip 16F688 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F688_H +#define P16F688_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define BAUDCTL_ADDR 0x0011 +#define SPBRGH_ADDR 0x0012 +#define SPBRG_ADDR 0x0013 +#define RCREG_ADDR 0x0014 +#define TXREG_ADDR 0x0015 +#define TXSTA_ADDR 0x0016 +#define RCSTA_ADDR 0x0017 +#define WDTCON_ADDR 0x0018 +#define CMCON0_ADDR 0x0019 +#define CMCON1_ADDR 0x001A +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define ANSEL_ADDR 0x0091 +#define WPU_ADDR 0x0095 +#define WPUA_ADDR 0x0095 +#define IOC_ADDR 0x0096 +#define IOCA_ADDR 0x0096 +#define EEDATH_ADDR 0x0097 +#define EEADRH_ADDR 0x0098 +#define VRCON_ADDR 0x0099 +#define EEDAT_ADDR 0x009A +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap BAUDCTL_ADDR BAUDCTL_ADDR SFR 0x000 // BAUDCTL +#pragma memmap SPBRGH_ADDR SPBRGH_ADDR SFR 0x000 // SPBRGH +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0 +#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1 +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16F688.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F688 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F688 +// 2. LIST directive in the source file +// LIST P=PIC16F688 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 07/28/03 Original +//1.01 09/02/03 Modified to match datasheet +//1.02 09/19/03 Changed CMCON1 from 0x20 to 0x1A (pas) +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F688 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; + +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; + +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (BAUDCTL_ADDR) BAUDCTL; +extern sfr __at (SPBRGH_ADDR) SPBRGH; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (CMCON0_ADDR) CMCON0; +extern sfr __at (CMCON1_ADDR) CMCON1; + +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; + +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (ANSEL_ADDR) ANSEL; + +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (WPUA_ADDR) WPUA; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (IOCA_ADDR) IOCA; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (EEDAT_ADDR) EEDAT; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- BAUDCTL Bits -------------------------------------------------------- + + +//----- TXSTA Bits -------------------------------------------------------- + + +//----- RCSTA Bits -------------------------------------------------------- + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- CMCON0 Bits ------------------------------------------------------- + + +//----- CMCON1 Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits -------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- ANSEL -------------------------------------------------------------- + + +//----- IOC -------------------------------------------------------------- + + +//----- IOCA -------------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- EECON1 ------------------------------------------------------------- + + +//----- ADCON1 ------------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D' +// __BADRAM H'86', H'88'-H'89', H'8D', H'92'-H'94' +// __BADRAM H'106', H'108'-H'109', H'10C'-H'11F' +// __BADRAM H'186', H'188'-H'189', H'18C'-H'18D', H'190'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char :1; + unsigned char VCFG:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define VCFG ADCON0_bits.VCFG +#define ADFM ADCON0_bits.ADFM + +// ----- BAUDCTL bits -------------------- +typedef union { + struct { + unsigned char ABDEN:1; + unsigned char WUE:1; + unsigned char :1; + unsigned char BRG16:1; + unsigned char SCKP:1; + unsigned char :1; + unsigned char RCIDL:1; + unsigned char ABDOVF:1; + }; +} __BAUDCTL_bits_t; +extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits; + +#define ABDEN BAUDCTL_bits.ABDEN +#define WUE BAUDCTL_bits.WUE +#define BRG16 BAUDCTL_bits.BRG16 +#define SCKP BAUDCTL_bits.SCKP +#define RCIDL BAUDCTL_bits.RCIDL +#define ABDOVF BAUDCTL_bits.ABDOVF + +// ----- CMCON0 bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON0_bits_t; +extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; + +#define CM0 CMCON0_bits.CM0 +#define CM1 CMCON0_bits.CM1 +#define CM2 CMCON0_bits.CM2 +#define CIS CMCON0_bits.CIS +#define C1INV CMCON0_bits.C1INV +#define C2INV CMCON0_bits.C2INV +#define C1OUT CMCON0_bits.C1OUT +#define C2OUT CMCON0_bits.C2OUT + +// ----- CMCON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __CMCON1_bits_t; +extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; + +#define C2SYNC CMCON1_bits.C2SYNC +#define T1GSS CMCON1_bits.T1GSS + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RAIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RAIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RAIF INTCON_bits.RAIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RAIE INTCON_bits.RAIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RAPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RAPU OPTION_REG_bits.NOT_RAPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char ANS5:1; + unsigned char ANS6:1; + unsigned char ANS7:1; + }; + struct { + unsigned char ANS0:1; + unsigned char ANS1:1; + unsigned char ANS2:1; + unsigned char ANS3:1; + unsigned char ANS4:1; + unsigned char IOC5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOC0:1; + unsigned char IOC1:1; + unsigned char IOC2:1; + unsigned char IOC3:1; + unsigned char IOC4:1; + unsigned char IOCA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOCA0:1; + unsigned char IOCA1:1; + unsigned char IOCA2:1; + unsigned char IOCA3:1; + unsigned char IOCA4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define ANS0 OSCTUNE_bits.ANS0 +#define IOC0 OSCTUNE_bits.IOC0 +#define IOCA0 OSCTUNE_bits.IOCA0 +#define TUN1 OSCTUNE_bits.TUN1 +#define ANS1 OSCTUNE_bits.ANS1 +#define IOC1 OSCTUNE_bits.IOC1 +#define IOCA1 OSCTUNE_bits.IOCA1 +#define TUN2 OSCTUNE_bits.TUN2 +#define ANS2 OSCTUNE_bits.ANS2 +#define IOC2 OSCTUNE_bits.IOC2 +#define IOCA2 OSCTUNE_bits.IOCA2 +#define TUN3 OSCTUNE_bits.TUN3 +#define ANS3 OSCTUNE_bits.ANS3 +#define IOC3 OSCTUNE_bits.IOC3 +#define IOCA3 OSCTUNE_bits.IOCA3 +#define TUN4 OSCTUNE_bits.TUN4 +#define ANS4 OSCTUNE_bits.ANS4 +#define IOC4 OSCTUNE_bits.IOC4 +#define IOCA4 OSCTUNE_bits.IOCA4 +#define ANS5 OSCTUNE_bits.ANS5 +#define IOC5 OSCTUNE_bits.IOC5 +#define IOCA5 OSCTUNE_bits.IOCA5 +#define ANS6 OSCTUNE_bits.ANS6 +#define ANS7 OSCTUNE_bits.ANS7 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBODEN:1; + unsigned char ULPWUE:1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define SBODEN PCON_bits.SBODEN +#define ULPWUE PCON_bits.ULPWUE + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char T1IE:1; + unsigned char TXIE:1; + unsigned char OSFIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char EEIE:1; + }; + struct { + unsigned char TMR1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define T1IE PIE1_bits.T1IE +#define TMR1IE PIE1_bits.TMR1IE +#define TXIE PIE1_bits.TXIE +#define OSFIE PIE1_bits.OSFIE +#define C1IE PIE1_bits.C1IE +#define C2IE PIE1_bits.C2IE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char T1IF:1; + unsigned char TXIF:1; + unsigned char OSFIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char EEIF:1; + }; + struct { + unsigned char TMR1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define T1IF PIR1_bits.T1IF +#define TMR1IF PIR1_bits.TMR1IF +#define TXIF PIR1_bits.TXIF +#define OSFIF PIR1_bits.OSFIF +#define C1IF PIR1_bits.C1IF +#define C2IF PIR1_bits.C2IF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define EEIF PIR1_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define SWDTEN RCSTA_bits.SWDTEN +#define OERR RCSTA_bits.OERR +#define WDTPS0 RCSTA_bits.WDTPS0 +#define FERR RCSTA_bits.FERR +#define WDTPS1 RCSTA_bits.WDTPS1 +#define ADDEN RCSTA_bits.ADDEN +#define WDTPS2 RCSTA_bits.WDTPS2 +#define CREN RCSTA_bits.CREN +#define WDTPS3 RCSTA_bits.WDTPS3 +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char T1GINV:1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char SENDB:1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SENDB TXSTA_bits.SENDB +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char ADCS0:1; + unsigned char VRR:1; + unsigned char ADCS2:1; + unsigned char VREN:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char ADCS1:1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define RD VRCON_bits.RD +#define VR1 VRCON_bits.VR1 +#define WR VRCON_bits.WR +#define VR2 VRCON_bits.VR2 +#define WREN VRCON_bits.WREN +#define VR3 VRCON_bits.VR3 +#define WRERR VRCON_bits.WRERR +#define ADCS0 VRCON_bits.ADCS0 +#define VRR VRCON_bits.VRR +#define ADCS1 VRCON_bits.ADCS1 +#define ADCS2 VRCON_bits.ADCS2 +#define VREN VRCON_bits.VREN +#define EEPGD VRCON_bits.EEPGD + +#endif diff --git a/device/include/pic/pic16f689.h b/device/include/pic/pic16f689.h new file mode 100644 index 00000000..12cef2f4 --- /dev/null +++ b/device/include/pic/pic16f689.h @@ -0,0 +1,1259 @@ +// +// Register Declarations for Microchip 16F689 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F689_H +#define P16F689_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define SSPADD_ADDR 0x0093 +#define MSK_ADDR 0x0093 +#define SSPMSK_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPU_ADDR 0x0095 +#define WPUA_ADDR 0x0095 +#define IOC_ADDR 0x0096 +#define IOCA_ADDR 0x0096 +#define WDTCON_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define SPBRGH_ADDR 0x009A +#define BAUDCTL_ADDR 0x009B +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define WPUB_ADDR 0x0115 +#define IOCB_ADDR 0x0116 +#define VRCON_ADDR 0x0118 +#define CM1CON0_ADDR 0x0119 +#define CM2CON0_ADDR 0x011A +#define CM2CON1_ADDR 0x011B +#define ANSEL_ADDR 0x011E +#define ANSELH_ADDR 0x011F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D +#define SRCON_ADDR 0x019E + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap MSK_ADDR MSK_ADDR SFR 0x000 // MSK +#pragma memmap SSPMSK_ADDR SSPMSK_ADDR SFR 0x000 // SSPMSK +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap SPBRGH_ADDR SPBRGH_ADDR SFR 0x000 // SPBRGH +#pragma memmap BAUDCTL_ADDR BAUDCTL_ADDR SFR 0x000 // BAUDCTL +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0 +#pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0 +#pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1 +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ANSELH_ADDR ANSELH_ADDR SFR 0x000 // ANSELH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap SRCON_ADDR SRCON_ADDR SFR 0x000 // SRCON + + +// LIST +// P16F689.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F689 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F689 +// 2. LIST directive in the source file +// LIST P=PIC16F689 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 10/12/04 Original +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F689 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; + + +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; + + +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; + +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; + +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (MSK_ADDR) MSK; +extern sfr __at (SSPMSK_ADDR) SSPMSK; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (WPUA_ADDR) WPUA; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (IOCA_ADDR) IOCA; +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (SPBRGH_ADDR) SPBRGH; +extern sfr __at (BAUDCTL_ADDR) BAUDCTL; + + +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + + + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + + +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (IOCB_ADDR) IOCB; + +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (CM1CON0_ADDR) CM1CON0; +extern sfr __at (CM2CON0_ADDR) CM2CON0; +extern sfr __at (CM2CON1_ADDR) CM2CON1; + +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ANSELH_ADDR) ANSELH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + + +extern sfr __at (SRCON_ADDR) SRCON; + + + +//----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + + +//----- SSPCON Bits ------------------------------------------------------- + + + +//----- RCSTA Bits --------------------------------------------------------- + + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISA Bits -------------------------------------------------------- + + +//----- TRISB Bits -------------------------------------------------------- + + +//----- TRISC Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits -------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- SSPSTAT Bits -------------------------------------------------------- + + +//----- WPUA -------------------------------------------------------------- + + + +//----- IOC -------------------------------------------------------------- + + +//----- IOCA -------------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- TXSTA Bits ------------------------------------------------------- + + +//----- SPBRG Bits ------------------------------------------------------- + + +//----- SPBRGH Bits ------------------------------------------------------- + + +//----- BAUDCTL Bits ------------------------------------------------------- + + + + +//----- ADCON1 ------------------------------------------------------------- + + +//----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- +//----- WPUB Bits ---------------------------------------------------------- + + +//----- IOCB -------------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- CM1CON0 Bits ------------------------------------------------------- + + + +//----- CM2CON0 Bits ------------------------------------------------------- + + + +//----- CM2CON1 Bits ------------------------------------------------------- + + +//----- ANSEL -------------------------------------------------------------- + + +//----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- +//----- EECON1 ------------------------------------------------------------- + + +//----- SRCON --------------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'17', H'1B'-H'1D' +// __BADRAM H'88'-H'89', H'91'-H'92', H'9C'-H'9D' +// __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D' +// __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char CHS3:1; + unsigned char VCFG:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define CHS3 ADCON0_bits.CHS3 +#define VCFG ADCON0_bits.VCFG +#define ADFM ADCON0_bits.ADFM + +// ----- BAUDCTL bits -------------------- +typedef union { + struct { + unsigned char ABDEN:1; + unsigned char WUE:1; + unsigned char :1; + unsigned char BRG16:1; + unsigned char CKTXP:1; + unsigned char ADCS1:1; + unsigned char RCIDL:1; + unsigned char ABDOVF:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char :1; + unsigned char ADCS2:1; + unsigned char :1; + }; +} __BAUDCTL_bits_t; +extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits; + +#define ABDEN BAUDCTL_bits.ABDEN +#define WUE BAUDCTL_bits.WUE +#define BRG16 BAUDCTL_bits.BRG16 +#define CKTXP BAUDCTL_bits.CKTXP +#define ADCS0 BAUDCTL_bits.ADCS0 +#define ADCS1 BAUDCTL_bits.ADCS1 +#define RCIDL BAUDCTL_bits.RCIDL +#define ADCS2 BAUDCTL_bits.ADCS2 +#define ABDOVF BAUDCTL_bits.ABDOVF + +// ----- CM1CON0 bits -------------------- +typedef union { + struct { + unsigned char C1CH0:1; + unsigned char C1CH1:1; + unsigned char C1R:1; + unsigned char :1; + unsigned char C1POL:1; + unsigned char C1OE:1; + unsigned char C1OUT:1; + unsigned char C1ON:1; + }; +} __CM1CON0_bits_t; +extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; + +#define C1CH0 CM1CON0_bits.C1CH0 +#define C1CH1 CM1CON0_bits.C1CH1 +#define C1R CM1CON0_bits.C1R +#define C1POL CM1CON0_bits.C1POL +#define C1OE CM1CON0_bits.C1OE +#define C1OUT CM1CON0_bits.C1OUT +#define C1ON CM1CON0_bits.C1ON + +// ----- CM2CON0 bits -------------------- +typedef union { + struct { + unsigned char C2CH0:1; + unsigned char C2CH1:1; + unsigned char C2R:1; + unsigned char :1; + unsigned char C2POL:1; + unsigned char C2OE:1; + unsigned char C2OUT:1; + unsigned char C2ON:1; + }; +} __CM2CON0_bits_t; +extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; + +#define C2CH0 CM2CON0_bits.C2CH0 +#define C2CH1 CM2CON0_bits.C2CH1 +#define C2R CM2CON0_bits.C2R +#define C2POL CM2CON0_bits.C2POL +#define C2OE CM2CON0_bits.C2OE +#define C2OUT CM2CON0_bits.C2OUT +#define C2ON CM2CON0_bits.C2ON + +// ----- CM2CON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char ANS2:1; + unsigned char ANS3:1; + unsigned char ANS4:1; + unsigned char ANS5:1; + unsigned char MC2OUT:1; + unsigned char MC1OUT:1; + }; + struct { + unsigned char ANS0:1; + unsigned char ANS1:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char C2REN:1; + unsigned char C1SEN:1; + unsigned char ANS6:1; + unsigned char ANS7:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char PULSR:1; + unsigned char PULSS:1; + unsigned char :1; + unsigned char :1; + unsigned char SR0:1; + unsigned char EEPGD:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char SR1:1; + }; +} __CM2CON1_bits_t; +extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; + +#define C2SYNC CM2CON1_bits.C2SYNC +#define ANS0 CM2CON1_bits.ANS0 +#define RD CM2CON1_bits.RD +#define T1GSS CM2CON1_bits.T1GSS +#define ANS1 CM2CON1_bits.ANS1 +#define WR CM2CON1_bits.WR +#define ANS2 CM2CON1_bits.ANS2 +#define WREN CM2CON1_bits.WREN +#define PULSR CM2CON1_bits.PULSR +#define ANS3 CM2CON1_bits.ANS3 +#define WRERR CM2CON1_bits.WRERR +#define PULSS CM2CON1_bits.PULSS +#define ANS4 CM2CON1_bits.ANS4 +#define C2REN CM2CON1_bits.C2REN +#define ANS5 CM2CON1_bits.ANS5 +#define C1SEN CM2CON1_bits.C1SEN +#define MC2OUT CM2CON1_bits.MC2OUT +#define ANS6 CM2CON1_bits.ANS6 +#define SR0 CM2CON1_bits.SR0 +#define MC1OUT CM2CON1_bits.MC1OUT +#define ANS7 CM2CON1_bits.ANS7 +#define EEPGD CM2CON1_bits.EEPGD +#define SR1 CM2CON1_bits.SR1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RABIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RABIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RABIF INTCON_bits.RABIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RABIE INTCON_bits.RABIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RABPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RABPU OPTION_REG_bits.NOT_RABPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBODEN:1; + unsigned char ULPWUE:1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define SBODEN PCON_bits.SBODEN +#define ULPWUE PCON_bits.ULPWUE + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char T1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; + struct { + unsigned char TMR1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define T1IE PIE1_bits.T1IE +#define TMR1IE PIE1_bits.TMR1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE +#define C1IE PIE2_bits.C1IE +#define C2IE PIE2_bits.C2IE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char T1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; + struct { + unsigned char TMR1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define T1IF PIR1_bits.T1IF +#define TMR1IF PIR1_bits.TMR1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF +#define C1IF PIR2_bits.C1IF +#define C2IF PIR2_bits.C2IF +#define OSFIF PIR2_bits.OSFIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define SPEN RCSTA_bits.SPEN + +// ----- SPBRG bits -------------------- +typedef union { + struct { + unsigned char BRG0:1; + unsigned char BRG1:1; + unsigned char BRG2:1; + unsigned char BRG3:1; + unsigned char BRG4:1; + unsigned char BRG5:1; + unsigned char BRG6:1; + unsigned char BRG7:1; + }; +} __SPBRG_bits_t; +extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits; + +#define BRG0 SPBRG_bits.BRG0 +#define BRG1 SPBRG_bits.BRG1 +#define BRG2 SPBRG_bits.BRG2 +#define BRG3 SPBRG_bits.BRG3 +#define BRG4 SPBRG_bits.BRG4 +#define BRG5 SPBRG_bits.BRG5 +#define BRG6 SPBRG_bits.BRG6 +#define BRG7 SPBRG_bits.BRG7 + +// ----- SPBRGH bits -------------------- +typedef union { + struct { + unsigned char BRG8:1; + unsigned char BRG9:1; + unsigned char BRG10:1; + unsigned char BRG11:1; + unsigned char BRG12:1; + unsigned char BRG13:1; + unsigned char BRG14:1; + unsigned char BRG15:1; + }; +} __SPBRGH_bits_t; +extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits; + +#define BRG8 SPBRGH_bits.BRG8 +#define BRG9 SPBRGH_bits.BRG9 +#define BRG10 SPBRGH_bits.BRG10 +#define BRG11 SPBRGH_bits.BRG11 +#define BRG12 SPBRGH_bits.BRG12 +#define BRG13 SPBRGH_bits.BRG13 +#define BRG14 SPBRGH_bits.BRG14 +#define BRG15 SPBRGH_bits.BRG15 + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R_W_NOT:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D_A_NOT:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char WPUA0:1; + unsigned char WPUA1:1; + unsigned char WPUA2:1; + unsigned char IOC3:1; + unsigned char WPUA4:1; + unsigned char WPUA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOC0:1; + unsigned char IOC1:1; + unsigned char IOC2:1; + unsigned char IOCA3:1; + unsigned char IOC4:1; + unsigned char IOC5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOCA0:1; + unsigned char IOCA1:1; + unsigned char IOCA2:1; + unsigned char :1; + unsigned char IOCA4:1; + unsigned char IOCA5:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define WPUA0 SSPSTAT_bits.WPUA0 +#define IOC0 SSPSTAT_bits.IOC0 +#define IOCA0 SSPSTAT_bits.IOCA0 +#define UA SSPSTAT_bits.UA +#define WPUA1 SSPSTAT_bits.WPUA1 +#define IOC1 SSPSTAT_bits.IOC1 +#define IOCA1 SSPSTAT_bits.IOCA1 +#define R_W_NOT SSPSTAT_bits.R_W_NOT +#define WPUA2 SSPSTAT_bits.WPUA2 +#define IOC2 SSPSTAT_bits.IOC2 +#define IOCA2 SSPSTAT_bits.IOCA2 +#define S SSPSTAT_bits.S +#define IOC3 SSPSTAT_bits.IOC3 +#define IOCA3 SSPSTAT_bits.IOCA3 +#define P SSPSTAT_bits.P +#define WPUA4 SSPSTAT_bits.WPUA4 +#define IOC4 SSPSTAT_bits.IOC4 +#define IOCA4 SSPSTAT_bits.IOCA4 +#define D_A_NOT SSPSTAT_bits.D_A_NOT +#define WPUA5 SSPSTAT_bits.WPUA5 +#define IOC5 SSPSTAT_bits.IOC5 +#define IOCA5 SSPSTAT_bits.IOCA5 +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char T1GINV:1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- TRISA bits -------------------- +typedef union { + struct { + unsigned char TRISA0:1; + unsigned char TRISA1:1; + unsigned char TRISA2:1; + unsigned char TRISA3:1; + unsigned char TRISA4:1; + unsigned char TRISA5:1; + unsigned char :1; + unsigned char :1; + }; +} __TRISA_bits_t; +extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits; + +#define TRISA0 TRISA_bits.TRISA0 +#define TRISA1 TRISA_bits.TRISA1 +#define TRISA2 TRISA_bits.TRISA2 +#define TRISA3 TRISA_bits.TRISA3 +#define TRISA4 TRISA_bits.TRISA4 +#define TRISA5 TRISA_bits.TRISA5 + +// ----- TRISB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TRISB4:1; + unsigned char TRISB5:1; + unsigned char TRISB6:1; + unsigned char TRISB7:1; + }; +} __TRISB_bits_t; +extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; + +#define TRISB4 TRISB_bits.TRISB4 +#define TRISB5 TRISB_bits.TRISB5 +#define TRISB6 TRISB_bits.TRISB6 +#define TRISB7 TRISB_bits.TRISB7 + +// ----- TRISC bits -------------------- +typedef union { + struct { + unsigned char TRISC0:1; + unsigned char TRISC1:1; + unsigned char TRISC2:1; + unsigned char TRISC3:1; + unsigned char TRISC4:1; + unsigned char TRISC5:1; + unsigned char TRISC6:1; + unsigned char TRISC7:1; + }; +} __TRISC_bits_t; +extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits; + +#define TRISC0 TRISC_bits.TRISC0 +#define TRISC1 TRISC_bits.TRISC1 +#define TRISC2 TRISC_bits.TRISC2 +#define TRISC3 TRISC_bits.TRISC3 +#define TRISC4 TRISC_bits.TRISC4 +#define TRISC5 TRISC_bits.TRISC5 +#define TRISC6 TRISC_bits.TRISC6 +#define TRISC7 TRISC_bits.TRISC7 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char SENB:1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SENB TXSTA_bits.SENB +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char VP6EN:1; + unsigned char VRR:1; + unsigned char C2VREN:1; + unsigned char C1VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VP6EN VRCON_bits.VP6EN +#define VRR VRCON_bits.VRR +#define C2VREN VRCON_bits.C2VREN +#define C1VREN VRCON_bits.C1VREN + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +// ----- WPUB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char WPUB4:1; + unsigned char WPUB5:1; + unsigned char WPUB6:1; + unsigned char WPUB7:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOCB4:1; + unsigned char IOCB5:1; + unsigned char IOCB6:1; + unsigned char IOCB7:1; + }; +} __WPUB_bits_t; +extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + +#define WPUB4 WPUB_bits.WPUB4 +#define IOCB4 WPUB_bits.IOCB4 +#define WPUB5 WPUB_bits.WPUB5 +#define IOCB5 WPUB_bits.IOCB5 +#define WPUB6 WPUB_bits.WPUB6 +#define IOCB6 WPUB_bits.IOCB6 +#define WPUB7 WPUB_bits.WPUB7 +#define IOCB7 WPUB_bits.IOCB7 + +#endif diff --git a/device/include/pic/pic16f690.h b/device/include/pic/pic16f690.h new file mode 100644 index 00000000..a3751f8b --- /dev/null +++ b/device/include/pic/pic16f690.h @@ -0,0 +1,1396 @@ +// +// Register Declarations for Microchip 16F690 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F690_H +#define P16F690_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define PWM1CON_ADDR 0x001C +#define ECCPAS_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define MSK_ADDR 0x0093 +#define SSPMSK_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPU_ADDR 0x0095 +#define WPUA_ADDR 0x0095 +#define IOC_ADDR 0x0096 +#define IOCA_ADDR 0x0096 +#define WDTCON_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define SPBRGH_ADDR 0x009A +#define BAUDCTL_ADDR 0x009B +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define WPUB_ADDR 0x0115 +#define IOCB_ADDR 0x0116 +#define VRCON_ADDR 0x0118 +#define CM1CON0_ADDR 0x0119 +#define CM2CON0_ADDR 0x011A +#define CM2CON1_ADDR 0x011B +#define ANSEL_ADDR 0x011E +#define ANSELH_ADDR 0x011F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D +#define PSTRCON_ADDR 0x019D +#define SRCON_ADDR 0x019E + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON +#pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap MSK_ADDR MSK_ADDR SFR 0x000 // MSK +#pragma memmap SSPMSK_ADDR SSPMSK_ADDR SFR 0x000 // SSPMSK +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap SPBRGH_ADDR SPBRGH_ADDR SFR 0x000 // SPBRGH +#pragma memmap BAUDCTL_ADDR BAUDCTL_ADDR SFR 0x000 // BAUDCTL +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0 +#pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0 +#pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1 +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ANSELH_ADDR ANSELH_ADDR SFR 0x000 // ANSELH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap PSTRCON_ADDR PSTRCON_ADDR SFR 0x000 // PSTRCON +#pragma memmap SRCON_ADDR SRCON_ADDR SFR 0x000 // SRCON + + +// LIST +// P16F690.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F690 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F690 +// 2. LIST directive in the source file +// LIST P=PIC16F690 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 10/12/04 Original +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F690 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; + +extern sfr __at (PWM1CON_ADDR) PWM1CON; +extern sfr __at (ECCPAS_ADDR) ECCPAS; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; + +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (MSK_ADDR) MSK; +extern sfr __at (SSPMSK_ADDR) SSPMSK; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (WPUA_ADDR) WPUA; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (IOCA_ADDR) IOCA; +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (SPBRGH_ADDR) SPBRGH; +extern sfr __at (BAUDCTL_ADDR) BAUDCTL; + + +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + + + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + + +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (IOCB_ADDR) IOCB; + +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (CM1CON0_ADDR) CM1CON0; +extern sfr __at (CM2CON0_ADDR) CM2CON0; +extern sfr __at (CM2CON1_ADDR) CM2CON1; + +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ANSELH_ADDR) ANSELH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + + +extern sfr __at (PSTRCON_ADDR) PSTRCON; +extern sfr __at (SRCON_ADDR) SRCON; + + + +//----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits ------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- PWM1CON Bits ------------------------------------------------------- + + +//----- ECCPAS Bits -------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISA Bits -------------------------------------------------------- + + +//----- TRISB Bits -------------------------------------------------------- + + +//----- TRISC Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits -------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- SSPSTAT Bits -------------------------------------------------------- + + +//----- WPUA -------------------------------------------------------------- + + + +//----- IOC -------------------------------------------------------------- + + +//----- IOCA -------------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- TXSTA Bits ------------------------------------------------------- + + +//----- SPBRG Bits ------------------------------------------------------- + + +//----- SPBRGH Bits ------------------------------------------------------- + + +//----- BAUDCTL Bits ------------------------------------------------------- + + + + +//----- ADCON1 ------------------------------------------------------------- + + +//----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- +//----- WPUB Bits ---------------------------------------------------------- + + +//----- IOCB -------------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- CM1CON0 Bits ------------------------------------------------------- + + + +//----- CM2CON0 Bits ------------------------------------------------------- + + + +//----- CM2CON1 Bits ------------------------------------------------------- + + +//----- ANSEL -------------------------------------------------------------- + + +//----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- +//----- EECON1 ------------------------------------------------------------- + + +//----- PSTRCON ------------------------------------------------------------- + + +//----- SRCON --------------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09', H'1B' +// __BADRAM H'88'-H'89', H'91', H'9C'-H'9D' +// __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D' +// __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char CHS3:1; + unsigned char VCFG:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define CHS3 ADCON0_bits.CHS3 +#define VCFG ADCON0_bits.VCFG +#define ADFM ADCON0_bits.ADFM + +// ----- BAUDCTL bits -------------------- +typedef union { + struct { + unsigned char ABDEN:1; + unsigned char WUE:1; + unsigned char :1; + unsigned char BRG16:1; + unsigned char CKTXP:1; + unsigned char ADCS1:1; + unsigned char RCIDL:1; + unsigned char ABDOVF:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char :1; + unsigned char ADCS2:1; + unsigned char :1; + }; +} __BAUDCTL_bits_t; +extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits; + +#define ABDEN BAUDCTL_bits.ABDEN +#define WUE BAUDCTL_bits.WUE +#define BRG16 BAUDCTL_bits.BRG16 +#define CKTXP BAUDCTL_bits.CKTXP +#define ADCS0 BAUDCTL_bits.ADCS0 +#define ADCS1 BAUDCTL_bits.ADCS1 +#define RCIDL BAUDCTL_bits.RCIDL +#define ADCS2 BAUDCTL_bits.ADCS2 +#define ABDOVF BAUDCTL_bits.ABDOVF + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char P1M0:1; + unsigned char P1M1:1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 +#define P1M0 CCP1CON_bits.P1M0 +#define P1M1 CCP1CON_bits.P1M1 + +// ----- CM1CON0 bits -------------------- +typedef union { + struct { + unsigned char C1CH0:1; + unsigned char C1CH1:1; + unsigned char C1R:1; + unsigned char :1; + unsigned char C1POL:1; + unsigned char C1OE:1; + unsigned char C1OUT:1; + unsigned char C1ON:1; + }; +} __CM1CON0_bits_t; +extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; + +#define C1CH0 CM1CON0_bits.C1CH0 +#define C1CH1 CM1CON0_bits.C1CH1 +#define C1R CM1CON0_bits.C1R +#define C1POL CM1CON0_bits.C1POL +#define C1OE CM1CON0_bits.C1OE +#define C1OUT CM1CON0_bits.C1OUT +#define C1ON CM1CON0_bits.C1ON + +// ----- CM2CON0 bits -------------------- +typedef union { + struct { + unsigned char C2CH0:1; + unsigned char C2CH1:1; + unsigned char C2R:1; + unsigned char :1; + unsigned char C2POL:1; + unsigned char C2OE:1; + unsigned char C2OUT:1; + unsigned char C2ON:1; + }; +} __CM2CON0_bits_t; +extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; + +#define C2CH0 CM2CON0_bits.C2CH0 +#define C2CH1 CM2CON0_bits.C2CH1 +#define C2R CM2CON0_bits.C2R +#define C2POL CM2CON0_bits.C2POL +#define C2OE CM2CON0_bits.C2OE +#define C2OUT CM2CON0_bits.C2OUT +#define C2ON CM2CON0_bits.C2ON + +// ----- CM2CON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char ANS2:1; + unsigned char ANS3:1; + unsigned char ANS4:1; + unsigned char ANS5:1; + unsigned char MC2OUT:1; + unsigned char MC1OUT:1; + }; + struct { + unsigned char ANS0:1; + unsigned char ANS1:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char STRSYNC:1; + unsigned char C1SEN:1; + unsigned char ANS6:1; + unsigned char ANS7:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char STRC:1; + unsigned char STRD:1; + unsigned char C2REN:1; + unsigned char :1; + unsigned char SR0:1; + unsigned char EEPGD:1; + }; + struct { + unsigned char STRA:1; + unsigned char STRB:1; + unsigned char PULSR:1; + unsigned char PULSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char SR1:1; + }; +} __CM2CON1_bits_t; +extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; + +#define C2SYNC CM2CON1_bits.C2SYNC +#define ANS0 CM2CON1_bits.ANS0 +#define RD CM2CON1_bits.RD +#define STRA CM2CON1_bits.STRA +#define T1GSS CM2CON1_bits.T1GSS +#define ANS1 CM2CON1_bits.ANS1 +#define WR CM2CON1_bits.WR +#define STRB CM2CON1_bits.STRB +#define ANS2 CM2CON1_bits.ANS2 +#define WREN CM2CON1_bits.WREN +#define STRC CM2CON1_bits.STRC +#define PULSR CM2CON1_bits.PULSR +#define ANS3 CM2CON1_bits.ANS3 +#define WRERR CM2CON1_bits.WRERR +#define STRD CM2CON1_bits.STRD +#define PULSS CM2CON1_bits.PULSS +#define ANS4 CM2CON1_bits.ANS4 +#define STRSYNC CM2CON1_bits.STRSYNC +#define C2REN CM2CON1_bits.C2REN +#define ANS5 CM2CON1_bits.ANS5 +#define C1SEN CM2CON1_bits.C1SEN +#define MC2OUT CM2CON1_bits.MC2OUT +#define ANS6 CM2CON1_bits.ANS6 +#define SR0 CM2CON1_bits.SR0 +#define MC1OUT CM2CON1_bits.MC1OUT +#define ANS7 CM2CON1_bits.ANS7 +#define EEPGD CM2CON1_bits.EEPGD +#define SR1 CM2CON1_bits.SR1 + +// ----- ECCPAS bits -------------------- +typedef union { + struct { + unsigned char PSSBD0:1; + unsigned char PSSBD1:1; + unsigned char PSSAC0:1; + unsigned char PSSAC1:1; + unsigned char ECCPAS0:1; + unsigned char ECCPAS1:1; + unsigned char ECCPAS2:1; + unsigned char ECCPASE:1; + }; +} __ECCPAS_bits_t; +extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits; + +#define PSSBD0 ECCPAS_bits.PSSBD0 +#define PSSBD1 ECCPAS_bits.PSSBD1 +#define PSSAC0 ECCPAS_bits.PSSAC0 +#define PSSAC1 ECCPAS_bits.PSSAC1 +#define ECCPAS0 ECCPAS_bits.ECCPAS0 +#define ECCPAS1 ECCPAS_bits.ECCPAS1 +#define ECCPAS2 ECCPAS_bits.ECCPAS2 +#define ECCPASE ECCPAS_bits.ECCPASE + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RABIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RABIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RABIF INTCON_bits.RABIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RABIE INTCON_bits.RABIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RABPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RABPU OPTION_REG_bits.NOT_RABPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBODEN:1; + unsigned char ULPWUE:1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_POR PCON_bits.NOT_POR +#define SBODEN PCON_bits.SBODEN +#define ULPWUE PCON_bits.ULPWUE + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char T1IE:1; + unsigned char T2IE:1; + unsigned char CCPIE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define T1IE PIE1_bits.T1IE +#define TMR1IE PIE1_bits.TMR1IE +#define T2IE PIE1_bits.T2IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCPIE PIE1_bits.CCPIE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE +#define C1IE PIE2_bits.C1IE +#define C2IE PIE2_bits.C2IE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char T1IF:1; + unsigned char T2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define T1IF PIR1_bits.T1IF +#define TMR1IF PIR1_bits.TMR1IF +#define T2IF PIR1_bits.T2IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF +#define C1IF PIR2_bits.C1IF +#define C2IF PIR2_bits.C2IF +#define OSFIF PIR2_bits.OSFIF + +// ----- PWM1CON bits -------------------- +typedef union { + struct { + unsigned char PDC0:1; + unsigned char PDC1:1; + unsigned char PDC2:1; + unsigned char PDC3:1; + unsigned char PDC4:1; + unsigned char PDC5:1; + unsigned char PDC6:1; + unsigned char PRSEN:1; + }; +} __PWM1CON_bits_t; +extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits; + +#define PDC0 PWM1CON_bits.PDC0 +#define PDC1 PWM1CON_bits.PDC1 +#define PDC2 PWM1CON_bits.PDC2 +#define PDC3 PWM1CON_bits.PDC3 +#define PDC4 PWM1CON_bits.PDC4 +#define PDC5 PWM1CON_bits.PDC5 +#define PDC6 PWM1CON_bits.PDC6 +#define PRSEN PWM1CON_bits.PRSEN + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define SPEN RCSTA_bits.SPEN + +// ----- SPBRG bits -------------------- +typedef union { + struct { + unsigned char BRG0:1; + unsigned char BRG1:1; + unsigned char BRG2:1; + unsigned char BRG3:1; + unsigned char BRG4:1; + unsigned char BRG5:1; + unsigned char BRG6:1; + unsigned char BRG7:1; + }; +} __SPBRG_bits_t; +extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits; + +#define BRG0 SPBRG_bits.BRG0 +#define BRG1 SPBRG_bits.BRG1 +#define BRG2 SPBRG_bits.BRG2 +#define BRG3 SPBRG_bits.BRG3 +#define BRG4 SPBRG_bits.BRG4 +#define BRG5 SPBRG_bits.BRG5 +#define BRG6 SPBRG_bits.BRG6 +#define BRG7 SPBRG_bits.BRG7 + +// ----- SPBRGH bits -------------------- +typedef union { + struct { + unsigned char BRG8:1; + unsigned char BRG9:1; + unsigned char BRG10:1; + unsigned char BRG11:1; + unsigned char BRG12:1; + unsigned char BRG13:1; + unsigned char BRG14:1; + unsigned char BRG15:1; + }; +} __SPBRGH_bits_t; +extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits; + +#define BRG8 SPBRGH_bits.BRG8 +#define BRG9 SPBRGH_bits.BRG9 +#define BRG10 SPBRGH_bits.BRG10 +#define BRG11 SPBRGH_bits.BRG11 +#define BRG12 SPBRGH_bits.BRG12 +#define BRG13 SPBRGH_bits.BRG13 +#define BRG14 SPBRGH_bits.BRG14 +#define BRG15 SPBRGH_bits.BRG15 + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R_W_NOT:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D_A_NOT:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char WPUA0:1; + unsigned char WPUA1:1; + unsigned char WPUA2:1; + unsigned char IOC3:1; + unsigned char WPUA4:1; + unsigned char WPUA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOC0:1; + unsigned char IOC1:1; + unsigned char IOC2:1; + unsigned char IOCA3:1; + unsigned char IOC4:1; + unsigned char IOC5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOCA0:1; + unsigned char IOCA1:1; + unsigned char IOCA2:1; + unsigned char :1; + unsigned char IOCA4:1; + unsigned char IOCA5:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define WPUA0 SSPSTAT_bits.WPUA0 +#define IOC0 SSPSTAT_bits.IOC0 +#define IOCA0 SSPSTAT_bits.IOCA0 +#define UA SSPSTAT_bits.UA +#define WPUA1 SSPSTAT_bits.WPUA1 +#define IOC1 SSPSTAT_bits.IOC1 +#define IOCA1 SSPSTAT_bits.IOCA1 +#define R_W_NOT SSPSTAT_bits.R_W_NOT +#define WPUA2 SSPSTAT_bits.WPUA2 +#define IOC2 SSPSTAT_bits.IOC2 +#define IOCA2 SSPSTAT_bits.IOCA2 +#define S SSPSTAT_bits.S +#define IOC3 SSPSTAT_bits.IOC3 +#define IOCA3 SSPSTAT_bits.IOCA3 +#define P SSPSTAT_bits.P +#define WPUA4 SSPSTAT_bits.WPUA4 +#define IOC4 SSPSTAT_bits.IOC4 +#define IOCA4 SSPSTAT_bits.IOCA4 +#define D_A_NOT SSPSTAT_bits.D_A_NOT +#define WPUA5 SSPSTAT_bits.WPUA5 +#define IOC5 SSPSTAT_bits.IOC5 +#define IOCA5 SSPSTAT_bits.IOCA5 +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char T1GINV:1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISA bits -------------------- +typedef union { + struct { + unsigned char TRISA0:1; + unsigned char TRISA1:1; + unsigned char TRISA2:1; + unsigned char TRISA3:1; + unsigned char TRISA4:1; + unsigned char TRISA5:1; + unsigned char :1; + unsigned char :1; + }; +} __TRISA_bits_t; +extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits; + +#define TRISA0 TRISA_bits.TRISA0 +#define TRISA1 TRISA_bits.TRISA1 +#define TRISA2 TRISA_bits.TRISA2 +#define TRISA3 TRISA_bits.TRISA3 +#define TRISA4 TRISA_bits.TRISA4 +#define TRISA5 TRISA_bits.TRISA5 + +// ----- TRISB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TRISB4:1; + unsigned char TRISB5:1; + unsigned char TRISB6:1; + unsigned char TRISB7:1; + }; +} __TRISB_bits_t; +extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; + +#define TRISB4 TRISB_bits.TRISB4 +#define TRISB5 TRISB_bits.TRISB5 +#define TRISB6 TRISB_bits.TRISB6 +#define TRISB7 TRISB_bits.TRISB7 + +// ----- TRISC bits -------------------- +typedef union { + struct { + unsigned char TRISC0:1; + unsigned char TRISC1:1; + unsigned char TRISC2:1; + unsigned char TRISC3:1; + unsigned char TRISC4:1; + unsigned char TRISC5:1; + unsigned char TRISC6:1; + unsigned char TRISC7:1; + }; +} __TRISC_bits_t; +extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits; + +#define TRISC0 TRISC_bits.TRISC0 +#define TRISC1 TRISC_bits.TRISC1 +#define TRISC2 TRISC_bits.TRISC2 +#define TRISC3 TRISC_bits.TRISC3 +#define TRISC4 TRISC_bits.TRISC4 +#define TRISC5 TRISC_bits.TRISC5 +#define TRISC6 TRISC_bits.TRISC6 +#define TRISC7 TRISC_bits.TRISC7 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char SENB:1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SENB TXSTA_bits.SENB +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char VP6EN:1; + unsigned char VRR:1; + unsigned char C2VREN:1; + unsigned char C1VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VP6EN VRCON_bits.VP6EN +#define VRR VRCON_bits.VRR +#define C2VREN VRCON_bits.C2VREN +#define C1VREN VRCON_bits.C1VREN + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +// ----- WPUB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char WPUB4:1; + unsigned char WPUB5:1; + unsigned char WPUB6:1; + unsigned char WPUB7:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOCB4:1; + unsigned char IOCB5:1; + unsigned char IOCB6:1; + unsigned char IOCB7:1; + }; +} __WPUB_bits_t; +extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + +#define WPUB4 WPUB_bits.WPUB4 +#define IOCB4 WPUB_bits.IOCB4 +#define WPUB5 WPUB_bits.WPUB5 +#define IOCB5 WPUB_bits.IOCB5 +#define WPUB6 WPUB_bits.WPUB6 +#define IOCB6 WPUB_bits.IOCB6 +#define WPUB7 WPUB_bits.WPUB7 +#define IOCB7 WPUB_bits.IOCB7 + +#endif diff --git a/device/include/pic/pic16f716.h b/device/include/pic/pic16f716.h new file mode 100644 index 00000000..47785af1 --- /dev/null +++ b/device/include/pic/pic16f716.h @@ -0,0 +1,645 @@ +// +// Register Declarations for Microchip 16F716 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F716_H +#define P16F716_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define DATACCP_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define PWM1CON_ADDR 0x0018 +#define ECCPAS_ADDR 0x0019 +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISCP_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define ADCON1_ADDR 0x009F + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap DATACCP_ADDR DATACCP_ADDR SFR 0x000 // DATACCP +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON +#pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISCP_ADDR TRISCP_ADDR SFR 0x000 // TRISCP +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 + + +// LIST +// P16F716.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F716 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F716 +// 2. LIST directive in the source file +// LIST P=PIC16F716 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 16 Apr 2003 Initial Release +//1.01 30 Apr 2003 Added references for backward compatibility to PIC16C716 + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F716 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (DATACCP_ADDR) DATACCP; // C712/C716 compatibility + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (PWM1CON_ADDR) PWM1CON; +extern sfr __at (ECCPAS_ADDR) ECCPAS; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISCP_ADDR) TRISCP; // C712/C716 compatibility + +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (ADCON1_ADDR) ADCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- PORTB Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- PWM1CON Bits ------------------------------------------------------- + + +//----- ECCPAS Bits -------------------------------------------------------- + + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISB Bits -------------------------------------------------------- + + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'BF' +// __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1A'-H'1D' +// __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'9E' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF // C712/C716 compatibility +#define _BODEN_OFF 0x3FBF // C712/C716 compatibility +#define _BOREN_ON 0x3FFF +#define _BOREN_OFF 0x3FBF +#define _VBOR_25 0x3F7F +#define _VBOR_40 0x3FFF +#define _CP_ON 0x1FFF +#define _CP_ALL 0x1FFF // C712/C716 compatibility +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char P1M0:1; + unsigned char P1M1:1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 +#define P1M0 CCP1CON_bits.P1M0 +#define P1M1 CCP1CON_bits.P1M1 + +// ----- ECCPAS bits -------------------- +typedef union { + struct { + unsigned char PSSBD0:1; + unsigned char PSSBD1:1; + unsigned char PSSAC0:1; + unsigned char PSSAC1:1; + unsigned char ECCPAS0:1; + unsigned char ECCPAS1:1; + unsigned char :1; + unsigned char ECCPASE:1; + }; +} __ECCPAS_bits_t; +extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits; + +#define PSSBD0 ECCPAS_bits.PSSBD0 +#define PSSBD1 ECCPAS_bits.PSSBD1 +#define PSSAC0 ECCPAS_bits.PSSAC0 +#define PSSAC1 ECCPAS_bits.PSSAC1 +#define ECCPAS0 ECCPAS_bits.ECCPAS0 +#define ECCPAS1 ECCPAS_bits.ECCPAS1 +#define ECCPASE ECCPAS_bits.ECCPASE + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define ADIE PIE1_bits.ADIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define ADIF PIR1_bits.ADIF + +// ----- PORTB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char DT1CK:1; + unsigned char :1; + unsigned char DCCP:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PORTB_bits_t; +extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits; + +#define DT1CK PORTB_bits.DT1CK +#define DCCP PORTB_bits.DCCP + +// ----- PWM1CON bits -------------------- +typedef union { + struct { + unsigned char PDC0:1; + unsigned char PDC1:1; + unsigned char PDC2:1; + unsigned char PDC3:1; + unsigned char PDC4:1; + unsigned char PDC5:1; + unsigned char PDC6:1; + unsigned char PRSEN:1; + }; +} __PWM1CON_bits_t; +extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits; + +#define PDC0 PWM1CON_bits.PDC0 +#define PDC1 PWM1CON_bits.PDC1 +#define PDC2 PWM1CON_bits.PDC2 +#define PDC3 PWM1CON_bits.PDC3 +#define PDC4 PWM1CON_bits.PDC4 +#define PDC5 PWM1CON_bits.PDC5 +#define PDC6 PWM1CON_bits.PDC6 +#define PRSEN PWM1CON_bits.PRSEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define T1SYNC T1CON_bits.T1SYNC +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char TT1CK:1; + unsigned char :1; + unsigned char TCCP:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __TRISB_bits_t; +extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; + +#define TT1CK TRISB_bits.TT1CK +#define TCCP TRISB_bits.TCCP + +#endif diff --git a/device/include/pic/pic16f72.h b/device/include/pic/pic16f72.h new file mode 100644 index 00000000..7d049949 --- /dev/null +++ b/device/include/pic/pic16f72.h @@ -0,0 +1,705 @@ +// +// Register Declarations for Microchip 16F72 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F72_H +#define P16F72_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define ADCON1_ADDR 0x009F +#define PMDATL_ADDR 0x010C +#define PMADRL_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL +#pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16F72.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F72 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F72 +// 2. LIST directive in the source file +// LIST P=PIC16F72 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 03/22/02 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F72 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATL_ADDR) PMDATL; +extern sfr __at (PMADRL_ADDR) PMADRL; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09', H'0D', H'18'-H'1D' +// __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'19F' + + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BOREN_ON 0x3FFF +#define _BODEN_ON 0x3FFF // Backward compatibility only +#define _BOREN_OFF 0x3FBF +#define _BODEN_OFF 0x3FBF // Backward compatibility only +#define _CP_ALL 0x3FEF +#define _CP_OFF 0x3FFF +#define _PWRTEN_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF // Backward compatibility only +#define _PWRTEN_ON 0x3FF7 +#define _PWRTE_ON 0x3FF7 // Backward compatibility only +#define _WDTEN_ON 0x3FFF +#define _WDTEN_OFF 0x3FFB +#define _WDT_ON 0x3FFF // Backward compatibility only +#define _WDT_OFF 0x3FFB // Backward compatibility only +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char TMR0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char TMR0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T0IF:1; + unsigned char :1; + unsigned char :1; + unsigned char T0IE:1; + unsigned char :1; + unsigned char :1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define TMR0IF INTCON_bits.TMR0IF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define TMR0IE INTCON_bits.TMR0IE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +#endif diff --git a/device/include/pic/pic16f73.h b/device/include/pic/pic16f73.h new file mode 100644 index 00000000..3cae1115 --- /dev/null +++ b/device/include/pic/pic16f73.h @@ -0,0 +1,896 @@ +// +// Register Declarations for Microchip 16F73 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F73_H +#define P16F73_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON1_ADDR 0x009F +#define PMDATA_ADDR 0x010C +#define PMADR_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA +#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16F73.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F73 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F73 +// 2. LIST directive in the source file +// LIST P=PIC16F73 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 00/00/00 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F73 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATA_ADDR) PMDATA; +extern sfr __at (PMADR_ADDR) PMADR; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09' +// __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x3FEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f737.h b/device/include/pic/pic16f737.h new file mode 100644 index 00000000..eef19024 --- /dev/null +++ b/device/include/pic/pic16f737.h @@ -0,0 +1,1302 @@ +// +// Register Declarations for Microchip 16F737 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F737_H +#define P16F737_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define CCPR3L_ADDR 0x0095 +#define CCPR3H_ADDR 0x0096 +#define CCP3CON_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON2_ADDR 0x009B +#define CMCON_ADDR 0x009C +#define CVRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define WDTCON_ADDR 0x0105 +#define LVDCON_ADDR 0x0109 +#define PMDATA_ADDR 0x010C +#define PMADR_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap CCPR3L_ADDR CCPR3L_ADDR SFR 0x000 // CCPR3L +#pragma memmap CCPR3H_ADDR CCPR3H_ADDR SFR 0x000 // CCPR3H +#pragma memmap CCP3CON_ADDR CCP3CON_ADDR SFR 0x000 // CCP3CON +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON2_ADDR ADCON2_ADDR SFR 0x000 // ADCON2 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA +#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16F737.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F737 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F737 +// 2. LIST directive in the source file +// LIST P=PIC16F737 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.00 05/05/03 Initial Release +//1.01 10/21/03 Made changes to Program Memory register names. +//1.02 04/07/04 Added INT0IE & INT0IF bit names. + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F737 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (CCPR3L_ADDR) CCPR3L; +extern sfr __at (CCPR3H_ADDR) CCPR3H; +extern sfr __at (CCP3CON_ADDR) CCP3CON; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON2_ADDR) ADCON2; +extern sfr __at (CMCON_ADDR) CMCON; +extern sfr __at (CVRCON_ADDR) CVRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (PMDATA_ADDR) PMDATA; +extern sfr __at (PMADR_ADDR) PMADR; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits ------------------------------------------------------- + +//----- OSCTUNE Bits ------------------------------------------------------- + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- CCP3CON Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON2 Bits --------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- CVRCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08' +// __BADRAM H'88', H'9A' +// __BADRAM H'107'-H'108' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CONFIG1 0x2007 +#define _CONFIG2 0x2008 + +//Configuration Byte 1 Options +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _CCP2_RC1 0x3FFF +#define _CCP2_RB3 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _VBOR_2_0 0x3FFF +#define _VBOR_2_7 0x3F7F +#define _VBOR_4_2 0x3EFF +#define _VBOR_4_5 0x3E7F +#define _BOREN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) +#define _BOREN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) +#define _MCLR_ON 0x3FFF +#define _MCLR_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _EXTRC_CLKOUT 0x3FFF +#define _EXTRC_IO 0x3FFE +#define _INTRC_CLKOUT 0x3FFD +#define _INTRC_IO 0x3FFC +#define _EXTCLK 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +//Configuration Byte 2 Options +#define _BORSEN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) +#define _BORSEN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3FFD +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x3FFE + + +//**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) +//BOREN_1 & BORSEN_1 = BOR enabled and always on +//BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware +//BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) +//BOREN_0 & BORSEN_0 = BOR disabled + + +// To use the Configuration Bits, place the following lines in your source code +// in the following format, and change the configuration value to the desired +// setting (such as CP_OFF to CP_ALL). These are currently commented out here +// and each __CONFIG line should have the preceding semicolon removed when +// pasted into your source code. + +//Program Configuration Register 1 +// __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC + +//Program Configuration Register 2 +// __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF + + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char ADCS2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 +#define ADCS2 ADCON1_bits.ADCS2 +#define ADFM ADCON1_bits.ADFM + +// ----- ADCON2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ACQT0:1; + unsigned char ACQT1:1; + unsigned char ACQT2:1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON2_bits_t; +extern volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits; + +#define ACQT0 ADCON2_bits.ACQT0 +#define ACQT1 ADCON2_bits.ACQT1 +#define ACQT2 ADCON2_bits.ACQT2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- CCP3CON bits -------------------- +typedef union { + struct { + unsigned char CCP3M0:1; + unsigned char CCP3M1:1; + unsigned char CCP3M2:1; + unsigned char CCP3M3:1; + unsigned char CCP3Y:1; + unsigned char CCP3X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP3CON_bits_t; +extern volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits; + +#define CCP3M0 CCP3CON_bits.CCP3M0 +#define CCP3M1 CCP3CON_bits.CCP3M1 +#define CCP3M2 CCP3CON_bits.CCP3M2 +#define CCP3M3 CCP3CON_bits.CCP3M3 +#define CCP3Y CCP3CON_bits.CCP3Y +#define CCP3X CCP3CON_bits.CCP3X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- CVRCON bits -------------------- +typedef union { + struct { + unsigned char CVR0:1; + unsigned char CVR1:1; + unsigned char CVR2:1; + unsigned char CVR3:1; + unsigned char :1; + unsigned char CVRR:1; + unsigned char CVROE:1; + unsigned char CVREN:1; + }; +} __CVRCON_bits_t; +extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; + +#define CVR0 CVRCON_bits.CVR0 +#define CVR1 CVRCON_bits.CVR1 +#define CVR2 CVRCON_bits.CVR2 +#define CVR3 CVRCON_bits.CVR3 +#define CVRR CVRCON_bits.CVRR +#define CVROE CVRCON_bits.CVROE +#define CVREN CVRCON_bits.CVREN + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; + struct { + unsigned char :1; + unsigned char INT0IF:1; + unsigned char TMR0IF:1; + unsigned char :1; + unsigned char INT0IE:1; + unsigned char TMR0IE:1; + unsigned char :1; + unsigned char :1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define INT0IF INTCON_bits.INT0IF +#define T0IF INTCON_bits.T0IF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define INT0IE INTCON_bits.INT0IE +#define T0IE INTCON_bits.T0IE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LVDL0:1; + unsigned char LVDL1:1; + unsigned char LVDL2:1; + unsigned char LVDL3:1; + unsigned char LVDEN:1; + unsigned char IRVST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LVDL0 LVDCON_bits.LVDL0 +#define LVDL1 LVDCON_bits.LVDL1 +#define LVDL2 LVDCON_bits.LVDL2 +#define LVDL3 LVDCON_bits.LVDL3 +#define LVDEN LVDCON_bits.LVDEN +#define IRVST LVDCON_bits.IRVST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS0:1; + unsigned char SCS1:1; + unsigned char IOFS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS0 OSCCON_bits.SCS0 +#define SCS1 OSCCON_bits.SCS1 +#define IOFS OSCCON_bits.IOFS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char TUN5:1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 +#define TUN5 OSCTUNE_bits.TUN5 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char SBOREN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define SBOREN PCON_bits.SBOREN + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char CCP3IE:1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char :1; + unsigned char LVDIE:1; + unsigned char CMIE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define CCP3IE PIE2_bits.CCP3IE +#define BCLIE PIE2_bits.BCLIE +#define LVDIE PIE2_bits.LVDIE +#define CMIE PIE2_bits.CMIE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char CCP3IF:1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char :1; + unsigned char LVDIF:1; + unsigned char CMIF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define CCP3IF PIR2_bits.CCP3IF +#define BCLIF PIR2_bits.BCLIF +#define LVDIF PIR2_bits.LVDIF +#define CMIF PIR2_bits.CMIF +#define OSFIF PIR2_bits.OSFIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char T1RUN:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define T1RUN T1CON_bits.T1RUN + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char TRISE3:1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define TRISE3 TRISE_bits.TRISE3 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char SWDTE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define SWDTE WDTCON_bits.SWDTE +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +#endif diff --git a/device/include/pic/pic16f74.h b/device/include/pic/pic16f74.h new file mode 100644 index 00000000..acb47e26 --- /dev/null +++ b/device/include/pic/pic16f74.h @@ -0,0 +1,934 @@ +// +// Register Declarations for Microchip 16F74 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F74_H +#define P16F74_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON1_ADDR 0x009F +#define PMDATA_ADDR 0x010C +#define PMADR_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA +#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16F74.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F74 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F74 +// 2. LIST directive in the source file +// LIST P=PIC16F74 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 00/00/00 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F74 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATA_ADDR) PMDATA; +extern sfr __at (PMADR_ADDR) PMADR; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x3FEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f76.h b/device/include/pic/pic16f76.h new file mode 100644 index 00000000..96e4cd7c --- /dev/null +++ b/device/include/pic/pic16f76.h @@ -0,0 +1,895 @@ +// +// Register Declarations for Microchip 16F76 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F76_H +#define P16F76_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON1_ADDR 0x009F +#define PMDATA_ADDR 0x010C +#define PMADR_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA +#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16F76.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F76 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F76 +// 2. LIST directive in the source file +// LIST P=PIC16F76 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 00/00/00 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F76 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATA_ADDR) PMDATA; +extern sfr __at (PMADR_ADDR) PMADR; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09', H'88'-H'89' +// __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' +// __BADRAM H'105', H'107'-H'109' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x3FEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f767.h b/device/include/pic/pic16f767.h new file mode 100644 index 00000000..3e6c95fe --- /dev/null +++ b/device/include/pic/pic16f767.h @@ -0,0 +1,1296 @@ +// +// Register Declarations for Microchip 16F767 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F767_H +#define P16F767_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define CCPR3L_ADDR 0x0095 +#define CCPR3H_ADDR 0x0096 +#define CCP3CON_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON2_ADDR 0x009B +#define CMCON_ADDR 0x009C +#define CVRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define WDTCON_ADDR 0x0105 +#define LVDCON_ADDR 0x0109 +#define PMDATA_ADDR 0x010C +#define PMADR_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap CCPR3L_ADDR CCPR3L_ADDR SFR 0x000 // CCPR3L +#pragma memmap CCPR3H_ADDR CCPR3H_ADDR SFR 0x000 // CCPR3H +#pragma memmap CCP3CON_ADDR CCP3CON_ADDR SFR 0x000 // CCP3CON +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON2_ADDR ADCON2_ADDR SFR 0x000 // ADCON2 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA +#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16F767.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F767 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F767 +// 2. LIST directive in the source file +// LIST P=PIC16F767 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.00 05/05/03 Initial Release +//1.01 10/21/03 Made changes to Program Memory register names. +//1.02 04/07/04 Added INT0IE & INT0IF bit names. + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F767 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (CCPR3L_ADDR) CCPR3L; +extern sfr __at (CCPR3H_ADDR) CCPR3H; +extern sfr __at (CCP3CON_ADDR) CCP3CON; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON2_ADDR) ADCON2; +extern sfr __at (CMCON_ADDR) CMCON; +extern sfr __at (CVRCON_ADDR) CVRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (PMDATA_ADDR) PMDATA; +extern sfr __at (PMADR_ADDR) PMADR; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits ------------------------------------------------------- + +//----- OSCTUNE Bits ------------------------------------------------------- + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- CCP3CON Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON2 Bits --------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- CVRCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08' +// __BADRAM H'88', H'9A' +// __BADRAM H'107'-H'108' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CONFIG1 0x2007 +#define _CONFIG2 0x2008 + +//Configuration Byte 1 Options +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _CCP2_RC1 0x3FFF +#define _CCP2_RB3 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _VBOR_2_0 0x3FFF +#define _VBOR_2_7 0x3F7F +#define _VBOR_4_2 0x3EFF +#define _VBOR_4_5 0x3E7F +#define _BOREN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) +#define _BOREN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) +#define _MCLR_ON 0x3FFF +#define _MCLR_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _EXTRC_CLKOUT 0x3FFF +#define _EXTRC_IO 0x3FFE +#define _INTRC_CLKOUT 0x3FFD +#define _INTRC_IO 0x3FFC +#define _EXTCLK 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +//Configuration Byte 2 Options +#define _BORSEN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) +#define _BORSEN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3FFD +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x3FFE + + +//**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) +//BOREN_1 & BORSEN_1 = BOR enabled and always on +//BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware +//BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) +//BOREN_0 & BORSEN_0 = BOR disabled + + +// To use the Configuration Bits, place the following lines in your source code +// in the following format, and change the configuration value to the desired +// setting (such as CP_OFF to CP_ALL). These are currently commented out here +// and each __CONFIG line should have the preceding semicolon removed when +// pasted into your source code. + +//Program Configuration Register 1 +// __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC + +//Program Configuration Register 2 +// __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF + + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char ADCS2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 +#define ADCS2 ADCON1_bits.ADCS2 +#define ADFM ADCON1_bits.ADFM + +// ----- ADCON2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ACQT0:1; + unsigned char ACQT1:1; + unsigned char ACQT2:1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON2_bits_t; +extern volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits; + +#define ACQT0 ADCON2_bits.ACQT0 +#define ACQT1 ADCON2_bits.ACQT1 +#define ACQT2 ADCON2_bits.ACQT2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- CCP3CON bits -------------------- +typedef union { + struct { + unsigned char CCP3M0:1; + unsigned char CCP3M1:1; + unsigned char CCP3M2:1; + unsigned char CCP3M3:1; + unsigned char CCP3Y:1; + unsigned char CCP3X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP3CON_bits_t; +extern volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits; + +#define CCP3M0 CCP3CON_bits.CCP3M0 +#define CCP3M1 CCP3CON_bits.CCP3M1 +#define CCP3M2 CCP3CON_bits.CCP3M2 +#define CCP3M3 CCP3CON_bits.CCP3M3 +#define CCP3Y CCP3CON_bits.CCP3Y +#define CCP3X CCP3CON_bits.CCP3X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- CVRCON bits -------------------- +typedef union { + struct { + unsigned char CVR0:1; + unsigned char CVR1:1; + unsigned char CVR2:1; + unsigned char CVR3:1; + unsigned char :1; + unsigned char CVRR:1; + unsigned char CVROE:1; + unsigned char CVREN:1; + }; +} __CVRCON_bits_t; +extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; + +#define CVR0 CVRCON_bits.CVR0 +#define CVR1 CVRCON_bits.CVR1 +#define CVR2 CVRCON_bits.CVR2 +#define CVR3 CVRCON_bits.CVR3 +#define CVRR CVRCON_bits.CVRR +#define CVROE CVRCON_bits.CVROE +#define CVREN CVRCON_bits.CVREN + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; + struct { + unsigned char :1; + unsigned char INT0IF:1; + unsigned char TMR0IF:1; + unsigned char :1; + unsigned char INT0IE:1; + unsigned char TMR0IE:1; + unsigned char :1; + unsigned char :1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define INT0IF INTCON_bits.INT0IF +#define T0IF INTCON_bits.T0IF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define INT0IE INTCON_bits.INT0IE +#define T0IE INTCON_bits.T0IE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LVDL0:1; + unsigned char LVDL1:1; + unsigned char LVDL2:1; + unsigned char LVDL3:1; + unsigned char LVDEN:1; + unsigned char IRVST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LVDL0 LVDCON_bits.LVDL0 +#define LVDL1 LVDCON_bits.LVDL1 +#define LVDL2 LVDCON_bits.LVDL2 +#define LVDL3 LVDCON_bits.LVDL3 +#define LVDEN LVDCON_bits.LVDEN +#define IRVST LVDCON_bits.IRVST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS0:1; + unsigned char SCS1:1; + unsigned char IOFS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS0 OSCCON_bits.SCS0 +#define SCS1 OSCCON_bits.SCS1 +#define IOFS OSCCON_bits.IOFS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char TUN5:1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 +#define TUN5 OSCTUNE_bits.TUN5 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char SBOREN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define SBOREN PCON_bits.SBOREN + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char CCP3IE:1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char :1; + unsigned char LVDIE:1; + unsigned char CMIE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define CCP3IE PIE2_bits.CCP3IE +#define BCLIE PIE2_bits.BCLIE +#define LVDIE PIE2_bits.LVDIE +#define CMIE PIE2_bits.CMIE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char CCP3IF:1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char :1; + unsigned char LVDIF:1; + unsigned char CMIF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define CCP3IF PIR2_bits.CCP3IF +#define BCLIF PIR2_bits.BCLIF +#define LVDIF PIR2_bits.LVDIF +#define CMIF PIR2_bits.CMIF +#define OSFIF PIR2_bits.OSFIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char T1RUN:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define T1RUN T1CON_bits.T1RUN + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char TRISE3:1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define TRISE3 TRISE_bits.TRISE3 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char SWDTE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define SWDTE WDTCON_bits.SWDTE +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +#endif diff --git a/device/include/pic/pic16f77.h b/device/include/pic/pic16f77.h new file mode 100644 index 00000000..069bc240 --- /dev/null +++ b/device/include/pic/pic16f77.h @@ -0,0 +1,934 @@ +// +// Register Declarations for Microchip 16F77 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F77_H +#define P16F77_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRES_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON1_ADDR 0x009F +#define PMDATA_ADDR 0x010C +#define PMADR_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA +#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16F77.INC Standard Header File, Version 1.01 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F77 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F77 +// 2. LIST directive in the source file +// LIST P=PIC16F77 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 00/00/00 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F77 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRES_ADDR) ADRES; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (PMDATA_ADDR) PMDATA; +extern sfr __at (PMADR_ADDR) PMADR; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' +// __BADRAM H'105', H'107'-H'109' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _CP_ALL 0x3FEF +#define _CP_OFF 0x3FFF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char :1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f777.h b/device/include/pic/pic16f777.h new file mode 100644 index 00000000..7580a6cd --- /dev/null +++ b/device/include/pic/pic16f777.h @@ -0,0 +1,1301 @@ +// +// Register Declarations for Microchip 16F777 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F777_H +#define P16F777_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define CCPR3L_ADDR 0x0095 +#define CCPR3H_ADDR 0x0096 +#define CCP3CON_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADCON2_ADDR 0x009B +#define CMCON_ADDR 0x009C +#define CVRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define WDTCON_ADDR 0x0105 +#define LVDCON_ADDR 0x0109 +#define PMDATA_ADDR 0x010C +#define PMADR_ADDR 0x010D +#define PMDATH_ADDR 0x010E +#define PMADRH_ADDR 0x010F +#define PMCON1_ADDR 0x018C + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap CCPR3L_ADDR CCPR3L_ADDR SFR 0x000 // CCPR3L +#pragma memmap CCPR3H_ADDR CCPR3H_ADDR SFR 0x000 // CCPR3H +#pragma memmap CCP3CON_ADDR CCP3CON_ADDR SFR 0x000 // CCP3CON +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADCON2_ADDR ADCON2_ADDR SFR 0x000 // ADCON2 +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA +#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR +#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH +#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH +#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1 + + +// LIST +// P16F777.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F777 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F777 +// 2. LIST directive in the source file +// LIST P=PIC16F777 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.00 05/05/03 Initial Release +//1.01 10/21/03 Made changes to Program Memory register names. +//1.02 04/07/04 Added INT0IE & INT0IF bit names. + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F777 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (CCPR3L_ADDR) CCPR3L; +extern sfr __at (CCPR3H_ADDR) CCPR3H; +extern sfr __at (CCP3CON_ADDR) CCP3CON; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADCON2_ADDR) ADCON2; +extern sfr __at (CMCON_ADDR) CMCON; +extern sfr __at (CVRCON_ADDR) CVRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (PMDATA_ADDR) PMDATA; +extern sfr __at (PMADR_ADDR) PMADR; +extern sfr __at (PMDATH_ADDR) PMDATH; +extern sfr __at (PMADRH_ADDR) PMADRH; + +extern sfr __at (PMCON1_ADDR) PMCON1; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits ------------------------------------------------------- + +//----- OSCTUNE Bits ------------------------------------------------------- + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- CCP3CON Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON2 Bits --------------------------------------------------------- + + +//----- CMCON Bits --------------------------------------------------------- + + +//----- CVRCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- PMCON1 Bits -------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'9A' +// __BADRAM H'107'-H'108' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CONFIG1 0x2007 +#define _CONFIG2 0x2008 + +//Configuration Byte 1 Options +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _CCP2_RC1 0x3FFF +#define _CCP2_RB3 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _VBOR_2_0 0x3FFF +#define _VBOR_2_7 0x3F7F +#define _VBOR_4_2 0x3EFF +#define _VBOR_4_5 0x3E7F +#define _BOREN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) +#define _BOREN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) +#define _MCLR_ON 0x3FFF +#define _MCLR_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _EXTRC_CLKOUT 0x3FFF +#define _EXTRC_IO 0x3FFE +#define _INTRC_CLKOUT 0x3FFD +#define _INTRC_IO 0x3FFC +#define _EXTCLK 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +//Configuration Byte 2 Options +#define _BORSEN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) +#define _BORSEN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3FFD +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x3FFE + + +//**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) +//BOREN_1 & BORSEN_1 = BOR enabled and always on +//BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware +//BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) +//BOREN_0 & BORSEN_0 = BOR disabled + + +// To use the Configuration Bits, place the following lines in your source code +// in the following format, and change the configuration value to the desired +// setting (such as CP_OFF to CP_ALL). These are currently commented out here +// and each __CONFIG line should have the preceding semicolon removed when +// pasted into your source code. + +//Program Configuration Register 1 +// __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC + +//Program Configuration Register 2 +// __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF + + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char CHS3:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define CHS3 ADCON0_bits.CHS3 +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char ADCS2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 +#define ADCS2 ADCON1_bits.ADCS2 +#define ADFM ADCON1_bits.ADFM + +// ----- ADCON2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ACQT0:1; + unsigned char ACQT1:1; + unsigned char ACQT2:1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON2_bits_t; +extern volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits; + +#define ACQT0 ADCON2_bits.ACQT0 +#define ACQT1 ADCON2_bits.ACQT1 +#define ACQT2 ADCON2_bits.ACQT2 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- CCP3CON bits -------------------- +typedef union { + struct { + unsigned char CCP3M0:1; + unsigned char CCP3M1:1; + unsigned char CCP3M2:1; + unsigned char CCP3M3:1; + unsigned char CCP3Y:1; + unsigned char CCP3X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP3CON_bits_t; +extern volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits; + +#define CCP3M0 CCP3CON_bits.CCP3M0 +#define CCP3M1 CCP3CON_bits.CCP3M1 +#define CCP3M2 CCP3CON_bits.CCP3M2 +#define CCP3M3 CCP3CON_bits.CCP3M3 +#define CCP3Y CCP3CON_bits.CCP3Y +#define CCP3X CCP3CON_bits.CCP3X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- CVRCON bits -------------------- +typedef union { + struct { + unsigned char CVR0:1; + unsigned char CVR1:1; + unsigned char CVR2:1; + unsigned char CVR3:1; + unsigned char :1; + unsigned char CVRR:1; + unsigned char CVROE:1; + unsigned char CVREN:1; + }; +} __CVRCON_bits_t; +extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; + +#define CVR0 CVRCON_bits.CVR0 +#define CVR1 CVRCON_bits.CVR1 +#define CVR2 CVRCON_bits.CVR2 +#define CVR3 CVRCON_bits.CVR3 +#define CVRR CVRCON_bits.CVRR +#define CVROE CVRCON_bits.CVROE +#define CVREN CVRCON_bits.CVREN + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; + struct { + unsigned char :1; + unsigned char INT0IF:1; + unsigned char TMR0IF:1; + unsigned char :1; + unsigned char INT0IE:1; + unsigned char TMR0IE:1; + unsigned char :1; + unsigned char :1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define INT0IF INTCON_bits.INT0IF +#define T0IF INTCON_bits.T0IF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define INT0IE INTCON_bits.INT0IE +#define T0IE INTCON_bits.T0IE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LVDL0:1; + unsigned char LVDL1:1; + unsigned char LVDL2:1; + unsigned char LVDL3:1; + unsigned char LVDEN:1; + unsigned char IRVST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LVDL0 LVDCON_bits.LVDL0 +#define LVDL1 LVDCON_bits.LVDL1 +#define LVDL2 LVDCON_bits.LVDL2 +#define LVDL3 LVDCON_bits.LVDL3 +#define LVDEN LVDCON_bits.LVDEN +#define IRVST LVDCON_bits.IRVST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS0:1; + unsigned char SCS1:1; + unsigned char IOFS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS0 OSCCON_bits.SCS0 +#define SCS1 OSCCON_bits.SCS1 +#define IOFS OSCCON_bits.IOFS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char TUN5:1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 +#define TUN5 OSCTUNE_bits.TUN5 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char SBOREN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define SBOREN PCON_bits.SBOREN + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char CCP3IE:1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char :1; + unsigned char LVDIE:1; + unsigned char CMIE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define CCP3IE PIE2_bits.CCP3IE +#define BCLIE PIE2_bits.BCLIE +#define LVDIE PIE2_bits.LVDIE +#define CMIE PIE2_bits.CMIE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char CCP3IF:1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char :1; + unsigned char LVDIF:1; + unsigned char CMIF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define CCP3IF PIR2_bits.CCP3IF +#define BCLIF PIR2_bits.BCLIF +#define LVDIF PIR2_bits.LVDIF +#define CMIF PIR2_bits.CMIF +#define OSFIF PIR2_bits.OSFIF + +// ----- PMCON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PMCON1_bits_t; +extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; + +#define RD PMCON1_bits.RD + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char T1RUN:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define T1RUN T1CON_bits.T1RUN + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char TRISE3:1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define TRISE3 TRISE_bits.TRISE3 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char SWDTE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define SWDTE WDTCON_bits.SWDTE +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +#endif diff --git a/device/include/pic/pic16f785.h b/device/include/pic/pic16f785.h new file mode 100644 index 00000000..a968c2ca --- /dev/null +++ b/device/include/pic/pic16f785.h @@ -0,0 +1,1038 @@ +// +// Register Declarations for Microchip 16F785 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F785_H +#define P16F785_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0013 +#define CCPR1H_ADDR 0x0014 +#define CCP1CON_ADDR 0x0015 +#define WDTCON_ADDR 0x0018 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define ANSEL_ADDR 0x0091 +#define ANSEL0_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define ANSEL1_ADDR 0x0093 +#define WPU_ADDR 0x0095 +#define WPUA_ADDR 0x0095 +#define IOC_ADDR 0x0096 +#define IOCA_ADDR 0x0096 +#define REFCON_ADDR 0x0098 +#define VRCON_ADDR 0x0099 +#define EEDAT_ADDR 0x009A +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define PWMCON1_ADDR 0x0110 +#define PWMCON0_ADDR 0x0111 +#define PWMCLK_ADDR 0x0112 +#define PWMPH1_ADDR 0x0113 +#define PWMPH2_ADDR 0x0114 +#define CM1CON0_ADDR 0x0119 +#define CM2CON0_ADDR 0x011A +#define CM2CON1_ADDR 0x011B +#define OPA1CON_ADDR 0x011C +#define OPA2CON_ADDR 0x011D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap ANSEL0_ADDR ANSEL0_ADDR SFR 0x000 // ANSEL0 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap ANSEL1_ADDR ANSEL1_ADDR SFR 0x000 // ANSEL1 +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA +#pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap PWMCON1_ADDR PWMCON1_ADDR SFR 0x000 // PWMCON1 +#pragma memmap PWMCON0_ADDR PWMCON0_ADDR SFR 0x000 // PWMCON0 +#pragma memmap PWMCLK_ADDR PWMCLK_ADDR SFR 0x000 // PWMCLK +#pragma memmap PWMPH1_ADDR PWMPH1_ADDR SFR 0x000 // PWMPH1 +#pragma memmap PWMPH2_ADDR PWMPH2_ADDR SFR 0x000 // PWMPH2 +#pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0 +#pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0 +#pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1 +#pragma memmap OPA1CON_ADDR OPA1CON_ADDR SFR 0x000 // OPA1CON +#pragma memmap OPA2CON_ADDR OPA2CON_ADDR SFR 0x000 // OPA2CON + + +// LIST +// P16F785.INC Standard Header File, Version 1.10 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F785 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F785 +// 2. LIST directive in the source file +// LIST P=PIC16F785 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== +//1.00 03/26/04 Original +//1.10 07/12/04 Updated for changes to REFCON and VRCON +//1.20 08/26/04 Updated for changes from BOD to BOR +//1.30 09/23/04 Corrected addresses for OPA1CON and OPA2CON +//1.40 10/25/04 Added WPUA3 bit to WPUA register +// Deleted OVRLP bit from PWMCON1 register +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F785 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; + +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; + +extern sfr __at (WDTCON_ADDR) WDTCON; + +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; + +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; + +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (ANSEL0_ADDR) ANSEL0; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (ANSEL1_ADDR) ANSEL1; + +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (WPUA_ADDR) WPUA; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (IOCA_ADDR) IOCA; + +extern sfr __at (REFCON_ADDR) REFCON; +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (EEDAT_ADDR) EEDAT; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + + +extern sfr __at (PWMCON1_ADDR) PWMCON1; +extern sfr __at (PWMCON0_ADDR) PWMCON0; +extern sfr __at (PWMCLK_ADDR) PWMCLK; +extern sfr __at (PWMPH1_ADDR) PWMPH1; +extern sfr __at (PWMPH2_ADDR) PWMPH2; + +extern sfr __at (CM1CON0_ADDR) CM1CON0; +extern sfr __at (CM2CON0_ADDR) CM2CON0; +extern sfr __at (CM2CON1_ADDR) CM2CON1; +extern sfr __at (OPA1CON_ADDR) OPA1CON; +extern sfr __at (OPA2CON_ADDR) OPA2CON; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits -------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- ANSEL or ANSEL0 ---------------------------------------------------- + + +//----- ANSEL1 ------------------------------------------------------------- + + +//----- WPUA -------------------------------------------------------------- + + +//----- IOC -------------------------------------------------------------- + + +//----- IOCA -------------------------------------------------------------- + + +//----- REFCON ------------------------------------------------------------- + + +//----- VRCON Bits --------------------------------------------------------- + + +//----- EECON1 ------------------------------------------------------------- + + +//----- ADCON1 ------------------------------------------------------------- + + +//----- PWMCON1 ------------------------------------------------------------- + + +//----- PWMCON0 ------------------------------------------------------------- + + +//----- PWMCLK ------------------------------------------------------------- + + +//----- PWMPH1 & PWMPH2 ---------------------------------------------------- + + +//----- CM1CON0 ------------------------------------------------------------- + + +//----- CM2CON0 ------------------------------------------------------------- + + +//----- CM2CON1 ------------------------------------------------------------- + + +//----- OPA1CON & OPA2CON --------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09', H'0D', H'16'-H'17', H'19'-H'1D' +// __BADRAM H'88'-H'89', H'8D', H'94', H'97', H'C0'-H'EF' +// __BADRAM H'108'-H'109', H'10C'-H'10F', H'115'-H'118', H'11E'-H'16F' +// __BADRAM H'188'-H'189', H'18C'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _BOR_ON 0x3FFF +#define _BOR_NSLEEP 0x3EFF +#define _BOR_SBOREN 0x3DFF +#define _BOR_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FEF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char CHS3:1; + unsigned char VCFG:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define CHS3 ADCON0_bits.CHS3 +#define VCFG ADCON0_bits.VCFG +#define ADFM ADCON0_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char DC1B0:1; + unsigned char DC1B1:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define DC1B0 CCP1CON_bits.DC1B0 +#define DC1B1 CCP1CON_bits.DC1B1 + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RAIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RAIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RAIF INTCON_bits.RAIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RAIE INTCON_bits.RAIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RAPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RAPU OPTION_REG_bits.NOT_RAPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char ANS5:1; + unsigned char ANS6:1; + unsigned char ANS7:1; + }; + struct { + unsigned char ANS0:1; + unsigned char ANS1:1; + unsigned char ANS2:1; + unsigned char ANS3:1; + unsigned char ANS4:1; + unsigned char WPUA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char ANS8:1; + unsigned char ANS9:1; + unsigned char ANS10:1; + unsigned char ANS11:1; + unsigned char WPUA4:1; + unsigned char IOC5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char WPUA0:1; + unsigned char WPUA1:1; + unsigned char WPUA2:1; + unsigned char WPUA3:1; + unsigned char IOC4:1; + unsigned char IOCA5:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOC0:1; + unsigned char IOC1:1; + unsigned char IOC2:1; + unsigned char IOC3:1; + unsigned char IOCA4:1; + unsigned char BGST:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char IOCA0:1; + unsigned char IOCA1:1; + unsigned char IOCA2:1; + unsigned char IOCA3:1; + unsigned char VRBB:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char CVROE:1; + unsigned char VROE:1; + unsigned char VREN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define ANS0 OSCTUNE_bits.ANS0 +#define ANS8 OSCTUNE_bits.ANS8 +#define WPUA0 OSCTUNE_bits.WPUA0 +#define IOC0 OSCTUNE_bits.IOC0 +#define IOCA0 OSCTUNE_bits.IOCA0 +#define TUN1 OSCTUNE_bits.TUN1 +#define ANS1 OSCTUNE_bits.ANS1 +#define ANS9 OSCTUNE_bits.ANS9 +#define WPUA1 OSCTUNE_bits.WPUA1 +#define IOC1 OSCTUNE_bits.IOC1 +#define IOCA1 OSCTUNE_bits.IOCA1 +#define CVROE OSCTUNE_bits.CVROE +#define TUN2 OSCTUNE_bits.TUN2 +#define ANS2 OSCTUNE_bits.ANS2 +#define ANS10 OSCTUNE_bits.ANS10 +#define WPUA2 OSCTUNE_bits.WPUA2 +#define IOC2 OSCTUNE_bits.IOC2 +#define IOCA2 OSCTUNE_bits.IOCA2 +#define VROE OSCTUNE_bits.VROE +#define TUN3 OSCTUNE_bits.TUN3 +#define ANS3 OSCTUNE_bits.ANS3 +#define ANS11 OSCTUNE_bits.ANS11 +#define WPUA3 OSCTUNE_bits.WPUA3 +#define IOC3 OSCTUNE_bits.IOC3 +#define IOCA3 OSCTUNE_bits.IOCA3 +#define VREN OSCTUNE_bits.VREN +#define TUN4 OSCTUNE_bits.TUN4 +#define ANS4 OSCTUNE_bits.ANS4 +#define WPUA4 OSCTUNE_bits.WPUA4 +#define IOC4 OSCTUNE_bits.IOC4 +#define IOCA4 OSCTUNE_bits.IOCA4 +#define VRBB OSCTUNE_bits.VRBB +#define ANS5 OSCTUNE_bits.ANS5 +#define WPUA5 OSCTUNE_bits.WPUA5 +#define IOC5 OSCTUNE_bits.IOC5 +#define IOCA5 OSCTUNE_bits.IOCA5 +#define BGST OSCTUNE_bits.BGST +#define ANS6 OSCTUNE_bits.ANS6 +#define ANS7 OSCTUNE_bits.ANS7 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BOD:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBODEN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char SBOREN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BOD PCON_bits.NOT_BOD +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define SBODEN PCON_bits.SBODEN +#define SBOREN PCON_bits.SBOREN + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char T1IE:1; + unsigned char T2IE:1; + unsigned char OSFIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char CCP1IE:1; + unsigned char ADIE:1; + unsigned char EEIE:1; + }; + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define T1IE PIE1_bits.T1IE +#define TMR1IE PIE1_bits.TMR1IE +#define T2IE PIE1_bits.T2IE +#define TMR2IE PIE1_bits.TMR2IE +#define OSFIE PIE1_bits.OSFIE +#define C1IE PIE1_bits.C1IE +#define C2IE PIE1_bits.C2IE +#define CCP1IE PIE1_bits.CCP1IE +#define ADIE PIE1_bits.ADIE +#define EEIE PIE1_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char T1IF:1; + unsigned char T2IF:1; + unsigned char OSFIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char CCP1IF:1; + unsigned char ADIF:1; + unsigned char EEIF:1; + }; + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define T1IF PIR1_bits.T1IF +#define TMR1IF PIR1_bits.TMR1IF +#define T2IF PIR1_bits.T2IF +#define TMR2IF PIR1_bits.TMR2IF +#define OSFIF PIR1_bits.OSFIF +#define C1IF PIR1_bits.C1IF +#define C2IF PIR1_bits.C2IF +#define CCP1IF PIR1_bits.CCP1IF +#define ADIF PIR1_bits.ADIF +#define EEIF PIR1_bits.EEIF + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char TMR1GE:1; + unsigned char T1GINV:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char T1GE:1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define TMR1GE T1CON_bits.TMR1GE +#define T1GE T1CON_bits.T1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char ADCS0:1; + unsigned char VRR:1; + unsigned char C2VREN:1; + unsigned char C1VREN:1; + }; + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char CMDLY4:1; + unsigned char ADCS1:1; + unsigned char ADCS2:1; + unsigned char PRSEN:1; + }; + struct { + unsigned char CMDLY0:1; + unsigned char CMDLY1:1; + unsigned char CMDLY2:1; + unsigned char CMDLY3:1; + unsigned char BLANK1:1; + unsigned char COMOD0:1; + unsigned char COMOD1:1; + unsigned char PWMASE:1; + }; + struct { + unsigned char PH1EN:1; + unsigned char PH2EN:1; + unsigned char SYNC0:1; + unsigned char SYNC1:1; + unsigned char PER4:1; + unsigned char BLANK2:1; + unsigned char PASEN:1; + unsigned char POL:1; + }; + struct { + unsigned char PER0:1; + unsigned char PER1:1; + unsigned char PER2:1; + unsigned char PER3:1; + unsigned char PH4:1; + unsigned char PWMP0:1; + unsigned char PWMP1:1; + unsigned char C1ON:1; + }; + struct { + unsigned char PH0:1; + unsigned char PH1:1; + unsigned char PH2:1; + unsigned char PH3:1; + unsigned char C1POL:1; + unsigned char C1EN:1; + unsigned char C2EN:1; + unsigned char C2ON:1; + }; + struct { + unsigned char C1CH0:1; + unsigned char C1CH1:1; + unsigned char C1R:1; + unsigned char C1SP:1; + unsigned char C2POL:1; + unsigned char C1OE:1; + unsigned char C1OUT:1; + unsigned char MC1OUT:1; + }; + struct { + unsigned char C2CH0:1; + unsigned char C2CH1:1; + unsigned char C2R:1; + unsigned char C2SP:1; + unsigned char :1; + unsigned char C2OE:1; + unsigned char C2OUT:1; + unsigned char OPAON:1; + }; + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char MC2OUT:1; + unsigned char :1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define RD VRCON_bits.RD +#define CMDLY0 VRCON_bits.CMDLY0 +#define PH1EN VRCON_bits.PH1EN +#define PER0 VRCON_bits.PER0 +#define PH0 VRCON_bits.PH0 +#define C1CH0 VRCON_bits.C1CH0 +#define C2CH0 VRCON_bits.C2CH0 +#define C2SYNC VRCON_bits.C2SYNC +#define VR1 VRCON_bits.VR1 +#define WR VRCON_bits.WR +#define CMDLY1 VRCON_bits.CMDLY1 +#define PH2EN VRCON_bits.PH2EN +#define PER1 VRCON_bits.PER1 +#define PH1 VRCON_bits.PH1 +#define C1CH1 VRCON_bits.C1CH1 +#define C2CH1 VRCON_bits.C2CH1 +#define T1GSS VRCON_bits.T1GSS +#define VR2 VRCON_bits.VR2 +#define WREN VRCON_bits.WREN +#define CMDLY2 VRCON_bits.CMDLY2 +#define SYNC0 VRCON_bits.SYNC0 +#define PER2 VRCON_bits.PER2 +#define PH2 VRCON_bits.PH2 +#define C1R VRCON_bits.C1R +#define C2R VRCON_bits.C2R +#define VR3 VRCON_bits.VR3 +#define WRERR VRCON_bits.WRERR +#define CMDLY3 VRCON_bits.CMDLY3 +#define SYNC1 VRCON_bits.SYNC1 +#define PER3 VRCON_bits.PER3 +#define PH3 VRCON_bits.PH3 +#define C1SP VRCON_bits.C1SP +#define C2SP VRCON_bits.C2SP +#define ADCS0 VRCON_bits.ADCS0 +#define CMDLY4 VRCON_bits.CMDLY4 +#define BLANK1 VRCON_bits.BLANK1 +#define PER4 VRCON_bits.PER4 +#define PH4 VRCON_bits.PH4 +#define C1POL VRCON_bits.C1POL +#define C2POL VRCON_bits.C2POL +#define VRR VRCON_bits.VRR +#define ADCS1 VRCON_bits.ADCS1 +#define COMOD0 VRCON_bits.COMOD0 +#define BLANK2 VRCON_bits.BLANK2 +#define PWMP0 VRCON_bits.PWMP0 +#define C1EN VRCON_bits.C1EN +#define C1OE VRCON_bits.C1OE +#define C2OE VRCON_bits.C2OE +#define C2VREN VRCON_bits.C2VREN +#define ADCS2 VRCON_bits.ADCS2 +#define COMOD1 VRCON_bits.COMOD1 +#define PASEN VRCON_bits.PASEN +#define PWMP1 VRCON_bits.PWMP1 +#define C2EN VRCON_bits.C2EN +#define C1OUT VRCON_bits.C1OUT +#define C2OUT VRCON_bits.C2OUT +#define MC2OUT VRCON_bits.MC2OUT +#define C1VREN VRCON_bits.C1VREN +#define PRSEN VRCON_bits.PRSEN +#define PWMASE VRCON_bits.PWMASE +#define POL VRCON_bits.POL +#define C1ON VRCON_bits.C1ON +#define C2ON VRCON_bits.C2ON +#define MC1OUT VRCON_bits.MC1OUT +#define OPAON VRCON_bits.OPAON + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +#endif diff --git a/device/include/pic/pic16f818.h b/device/include/pic/pic16f818.h new file mode 100644 index 00000000..bd027233 --- /dev/null +++ b/device/include/pic/pic16f818.h @@ -0,0 +1,814 @@ +// +// Register Declarations for Microchip 16F818 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F818_H +#define P16F818_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F818.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F818 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F818 +// 2. LIST directive in the source file +// LIST P=PIC16F818 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 06/15/02 Initial Release +//1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F818 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits ------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'07'-H'09', H'18'-H'1D' +// __BADRAM H'87'-H'89', H'91', H'95'-H'9D' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _CCP1_RB2 0x3FFF +#define _CCP1_RB3 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _WRT_ENABLE_OFF 0x3FFF +#define _WRT_ENABLE_512 0x3DFF +#define _WRT_ENABLE_1024 0x3BFF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _MCLR_ON 0x3FFF +#define _MCLR_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _EXTRC_CLKOUT 0x3FFF +#define _EXTRC_IO 0x3FFE +#define _INTRC_CLKOUT 0x3FFD +#define _INTRC_IO 0x3FFC +#define _EXTCLK 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADCS2 ADCON1_bits.ADCS2 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char FREE:1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define FREE EECON1_bits.FREE +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char TMR0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char TMR0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char IOFS:1; + unsigned char :1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define IOFS OSCCON_bits.IOFS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char TUN5:1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 +#define TUN5 OSCTUNE_bits.TUN5 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +#endif diff --git a/device/include/pic/pic16f819.h b/device/include/pic/pic16f819.h new file mode 100644 index 00000000..8d03bdf1 --- /dev/null +++ b/device/include/pic/pic16f819.h @@ -0,0 +1,815 @@ +// +// Register Declarations for Microchip 16F819 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F819_H +#define P16F819_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F819.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F819 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F819 +// 2. LIST directive in the source file +// LIST P=PIC16F819 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 06/15/02 Initial Release +//1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F819 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits ------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'07'-H'09', H'18'-H'1D' +// __BADRAM H'87'-H'89', H'91', H'95'-H'9D' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _CCP1_RB2 0x3FFF +#define _CCP1_RB3 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _WRT_ENABLE_OFF 0x3FFF +#define _WRT_ENABLE_512 0x3DFF +#define _WRT_ENABLE_1024 0x3BFF +#define _WRT_ENABLE_1536 0x39FF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _MCLR_ON 0x3FFF +#define _MCLR_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _EXTRC_CLKOUT 0x3FFF +#define _EXTRC_IO 0x3FFE +#define _INTRC_CLKOUT 0x3FFD +#define _INTRC_IO 0x3FFC +#define _EXTCLK 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADCS2 ADCON1_bits.ADCS2 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char FREE:1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define FREE EECON1_bits.FREE +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char TMR0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char TMR0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char IOFS:1; + unsigned char :1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define IOFS OSCCON_bits.IOFS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char TUN5:1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 +#define TUN5 OSCTUNE_bits.TUN5 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +#endif diff --git a/device/include/pic/pic16f84.h b/device/include/pic/pic16f84.h new file mode 100644 index 00000000..506a3c15 --- /dev/null +++ b/device/include/pic/pic16f84.h @@ -0,0 +1,268 @@ +// +// Register Declarations for Microchip 16F84 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F84_H +#define P16F84_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define EEDATA_ADDR 0x0008 +#define EEADR_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define EECON1_ADDR 0x0088 +#define EECON2_ADDR 0x0089 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F84.INC Standard Header File, Version 2.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F84 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F84 +// 2. LIST directive in the source file +// LIST P=PIC16F84 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//2.00 07/24/96 Renamed to reflect the name change to PIC16F84. +//1.01 05/17/96 Corrected BADRAM map +//1.00 10/31/95 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F84 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'CF' +// __BADRAM H'07', H'50'-H'7F', H'87' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ON 0x000F +#define _CP_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _PWRTE_OFF 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEIF EECON1_bits.EEIF + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char EEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define EEIE INTCON_bits.EEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +#endif diff --git a/device/include/pic/pic16f84a.h b/device/include/pic/pic16f84a.h new file mode 100644 index 00000000..dad3cc35 --- /dev/null +++ b/device/include/pic/pic16f84a.h @@ -0,0 +1,266 @@ +// +// Register Declarations for Microchip 16F84A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F84A_H +#define P16F84A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define EEDATA_ADDR 0x0008 +#define EEADR_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define EECON1_ADDR 0x0088 +#define EECON2_ADDR 0x0089 + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F84A.INC Standard Header File, Version 2.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F84 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F84A +// 2. LIST directive in the source file +// LIST P=PIC16F84A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 2/15/99 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F84A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'CF' +// __BADRAM H'07', H'50'-H'7F', H'87' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ON 0x000F +#define _CP_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _PWRTE_OFF 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEIF EECON1_bits.EEIF + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char EEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define EEIE INTCON_bits.EEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +#endif diff --git a/device/include/pic/pic16f87.h b/device/include/pic/pic16f87.h new file mode 100644 index 00000000..22a3ecdb --- /dev/null +++ b/device/include/pic/pic16f87.h @@ -0,0 +1,974 @@ +// +// Register Declarations for Microchip 16F87 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F87_H +#define P16F87_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define CMCON_ADDR 0x009C +#define CVRCON_ADDR 0x009D +#define WDTCON_ADDR 0x0105 +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F87.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F87 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F87 +// 2. LIST directive in the source file +// LIST P=PIC16F87 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 07/29/02 Initial Release +//1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS +//1.02 01/10/03 Added bit names for TXSTA & RCSTA registers. +//1.03 01/24/03 Changed Config bit CCP1_RB2 to CCP1_RB0 +//1.04 12/02/03 Modified the WRT1:WRT0 bit definition in Config Word 1. +//1.05 02/08/04 Changed bit in _CONFIG1 example from CCP1_RB2 to CCP1_RB0. + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F87 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (CMCON_ADDR) CMCON; +extern sfr __at (CVRCON_ADDR) CVRCON; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + +//----- INTCON Bits -------------------------------------------------------- + +//----- PIR1 Bits ---------------------------------------------------------- + +//----- PIR2 Bits ---------------------------------------------------------- + +//----- T1CON Bits --------------------------------------------------------- + +//----- T2CON Bits --------------------------------------------------------- + +//----- SSPCON Bits -------------------------------------------------------- + +//----- CCP1CON Bits ------------------------------------------------------- + +//----- RCSTA Bits --------------------------------------------------------- + +//----- OPTION Bits ----------------------------------------------------- + +//----- PIE1 Bits ---------------------------------------------------------- + +//----- PIE2 Bits ---------------------------------------------------------- + +//----- PCON Bits ---------------------------------------------------------- + +//----- OSCCON Bits ------------------------------------------------------- + +//----- OSCTUNE Bits ------------------------------------------------------- + +//----- SSPSTAT Bits ------------------------------------------------------- + +//----- TXSTA Bits --------------------------------------------------------- + +//----- WDTCON Bits -------------------------------------------------------- + +//----- CMCON Bits --------------------------------------------------------- + +//----- CVRCON Bits -------------------------------------------------------- + +//----- EECON1 Bits -------------------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'07'-H'09', H'1B'-H'1F' +// __BADRAM H'87'-H'89', H'91', H'95'-H'97', H'9A', H'9E'-H'9F' +// __BADRAM H'107'-H'109' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CONFIG1 0x2007 +#define _CONFIG2 0x2008 + +//Configuration Byte 1 Options +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _CCP1_RB0 0x3FFF +#define _CCP1_RB3 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _WRT_PROTECT_OFF 0x3FFF //No program memory write protection +#define _WRT_PROTECT_256 0x3DFF //First 256 program memory protected +#define _WRT_PROTECT_2048 0x3BFF //First 2048 program memory protected +#define _WRT_PROTECT_ALL 0x39FF //All of program memory protected +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _MCLR_ON 0x3FFF +#define _MCLR_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _EXTRC_CLKOUT 0x3FFF +#define _EXTRC_IO 0x3FFE +#define _INTRC_CLKOUT 0x3FFD +#define _INTRC_IO 0x3FFC +#define _EXTCLK 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +//Configuration Byte 2 Options +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3FFD +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x3FFE + + + +// To use the Configuration Bits, place the following lines in your source code +// in the following format, and change the configuration value to the desired +// setting (such as CP_OFF to CP_ALL). These are currently commented out here +// and each __CONFIG line should have the preceding semicolon removed when +// pasted into your source code. + +//Program Configuration Register 1 +// __CONFIG _CONFIG1, _CP_OFF & _CCP1_RB0 & _DEBUG_OFF & _WRT_PROTECT_OFF & _CPD_OFF & _LVP_OFF & _BODEN_OFF & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC + +//Program Configuration Register 2 +// __CONFIG _CONFIG2, _IESO_OFF & _FCMEN_OFF + + + + + + +// LIST + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- CVRCON bits -------------------- +typedef union { + struct { + unsigned char CVR0:1; + unsigned char CVR1:1; + unsigned char CVR2:1; + unsigned char CVR3:1; + unsigned char :1; + unsigned char CVRR:1; + unsigned char CVROE:1; + unsigned char CVREN:1; + }; +} __CVRCON_bits_t; +extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; + +#define CVR0 CVRCON_bits.CVR0 +#define CVR1 CVRCON_bits.CVR1 +#define CVR2 CVRCON_bits.CVR2 +#define CVR3 CVRCON_bits.CVR3 +#define CVRR CVRCON_bits.CVRR +#define CVROE CVRCON_bits.CVROE +#define CVREN CVRCON_bits.CVREN + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char FREE:1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define FREE EECON1_bits.FREE +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char TMR0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char TMR0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS0:1; + unsigned char SCS1:1; + unsigned char IOFS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS0 OSCCON_bits.SCS0 +#define SCS1 OSCCON_bits.SCS1 +#define IOFS OSCCON_bits.IOFS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char TUN5:1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 +#define TUN5 OSCTUNE_bits.TUN5 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char :1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE +#define CMIE PIE2_bits.CMIE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char :1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF +#define CMIF PIR2_bits.CMIF +#define OSFIF PIR2_bits.OSFIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char T1RUN:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define T1RUN T1CON_bits.T1RUN + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char SWDTE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define SWDTE WDTCON_bits.SWDTE +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +#endif diff --git a/device/include/pic/pic16f870.h b/device/include/pic/pic16f870.h new file mode 100644 index 00000000..7b7a0de6 --- /dev/null +++ b/device/include/pic/pic16f870.h @@ -0,0 +1,768 @@ +// +// Register Declarations for Microchip 16F870 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F870_H +#define P16F870_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F870.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F870 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F870 +// 2. LIST directive in the source file +// LIST P=PIC16F870 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 08/07/98 Initial Release - cloned from 16F873 + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F870 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; + +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09', H'13'-H'14', H'1B'-H'1D' +// __BADRAM H'88'-H'89',H'8F'-H'91', H'93'-H'97', H'9A'-H'9D', H'C0'-H'EF' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F', H'1C0'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x0FCF +#define _CP_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _DEBUG_OFF 0x3FFF +#define _WRT_ENABLE_ON 0x3FFF +#define _WRT_ENABLE_OFF 0x3DFF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char :1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char :1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f871.h b/device/include/pic/pic16f871.h new file mode 100644 index 00000000..1c5c1f72 --- /dev/null +++ b/device/include/pic/pic16f871.h @@ -0,0 +1,808 @@ +// +// Register Declarations for Microchip 16F871 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F871_H +#define P16F871_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define PR2_ADDR 0x0092 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F871.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F871 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F871 +// 2. LIST directive in the source file +// LIST P=PIC16F871 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 08/07/98 Initial Release - cloned from 16F873 + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F871 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + + +//----- PCON Bits ---------------------------------------------------------- + + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'13'-H'14', H'1B'-H'1D' +// __BADRAM H'8F'-H'91', H'93'-H'97', H'9A'-H'9D', H'C0'-H'EF' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F', H'1C0'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x0FCF +#define _CP_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _DEBUG_OFF 0x3FFF +#define _WRT_ENABLE_ON 0x3FFF +#define _WRT_ENABLE_OFF 0x3DFF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char :1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char :1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f872.h b/device/include/pic/pic16f872.h new file mode 100644 index 00000000..497b5f50 --- /dev/null +++ b/device/include/pic/pic16f872.h @@ -0,0 +1,804 @@ +// +// Register Declarations for Microchip 16F872 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F872_H +#define P16F872_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F872.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F872 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F872 +// 2. LIST directive in the source file +// LIST P=PIC16F872 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 01/25/98 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F872 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'008'-H'009', H'018'-H'01D', H'088'-H'089' +// __BADRAM H'08F'-H'090', H'095'-H'09D', H'0C0'-H'0EF' +// __BADRAM H'105', H'107'-H'109' +// __BADRAM H'110'-H'11F', H'185' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F',H'1C0'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +// Code protection for the PIC16C872 is different than for other PIC16C87X devices. +// The CP_ALL and CP_OFF switches operate as expected. +// CP_HALF protects the lower half of program memory. The upper half is open. +// CP_UPPER_256 protects everything EXCEPT the top 256 words. +//========================================================================== + +#define _CP_ALL 0x0FCF +#define _CP_HALF 0x1FDF +#define _CP_UPPER_256 0x2FEF +#define _CP_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _DEBUG_OFF 0x3FFF +#define _WRT_ENABLE_ON 0x3FFF +#define _WRT_ENABLE_OFF 0x3DFF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define BCLIE PIE2_bits.BCLIE +#define EEIE PIE2_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char :1; + unsigned char :1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define BCLIF PIR2_bits.BCLIF +#define EEIF PIR2_bits.EEIF + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +#endif diff --git a/device/include/pic/pic16f873.h b/device/include/pic/pic16f873.h new file mode 100644 index 00000000..8325503a --- /dev/null +++ b/device/include/pic/pic16f873.h @@ -0,0 +1,966 @@ +// +// Register Declarations for Microchip 16F873 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F873_H +#define P16F873_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F873.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F873 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F873 +// 2. LIST directive in the source file +// LIST P=PIC16F873 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.12 01/12/00 Changed some bit names, a register name, configuration bits +// to match datasheet (DS30292B) +//1.11 10/18/98 Changes to file registers to match updated DOS +//1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1 +//1.00 08/07/98 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F873 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x0FCF +#define _CP_HALF 0x1FDF +#define _CP_UPPER_256 0x2FEF +#define _CP_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _DEBUG_OFF 0x3FFF +#define _WRT_ENABLE_ON 0x3FFF +#define _WRT_ENABLE_OFF 0x3DFF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define EEIE PIE2_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define EEIF PIR2_bits.EEIF +#define CMIF PIR2_bits.CMIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f873a.h b/device/include/pic/pic16f873a.h new file mode 100644 index 00000000..a957dcd3 --- /dev/null +++ b/device/include/pic/pic16f873a.h @@ -0,0 +1,1024 @@ +// +// Register Declarations for Microchip 16F873A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F873A_H +#define P16F873A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define CMCON_ADDR 0x009C +#define CVRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F873A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F877A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F873A +// 2. LIST directive in the source file +// LIST P=PIC16F873A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section. +//1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE +//1.00 04/19/01 Initial Release (BD - generated from PIC16F877a.inc) + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F873A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (CMCON_ADDR) CMCON; +extern sfr __at (CVRCON_ADDR) CVRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- CMCON Bits --------------------------------------------------------- + +//----- CVRCON Bits -------------------------------------------------------- + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _WRT_OFF 0x3FFF // No prog memmory write protection +#define _WRT_256 0x3DFF // First 256 prog memmory write protected +#define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected +#define _WRT_HALF 0x39FF // First half memmory write protected +#define _CPD_OFF 0x3FFF +#define _CPD_ON 0x3EFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _RC_OSC 0x3FFF +#define _HS_OSC 0x3FFE +#define _XT_OSC 0x3FFD +#define _LP_OSC 0x3FFC + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- CVRCON bits -------------------- +typedef union { + struct { + unsigned char CVR0:1; + unsigned char CVR1:1; + unsigned char CVR2:1; + unsigned char CVR3:1; + unsigned char :1; + unsigned char CVRR:1; + unsigned char CVROE:1; + unsigned char CVREN:1; + }; +} __CVRCON_bits_t; +extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; + +#define CVR0 CVRCON_bits.CVR0 +#define CVR1 CVRCON_bits.CVR1 +#define CVR2 CVRCON_bits.CVR2 +#define CVR3 CVRCON_bits.CVR3 +#define CVRR CVRCON_bits.CVRR +#define CVROE CVRCON_bits.CVROE +#define CVREN CVRCON_bits.CVREN + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define EEIE PIE2_bits.EEIE +#define CMIE PIE2_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define EEIF PIR2_bits.EEIF +#define CMIF PIR2_bits.CMIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f874.h b/device/include/pic/pic16f874.h new file mode 100644 index 00000000..eeedfcba --- /dev/null +++ b/device/include/pic/pic16f874.h @@ -0,0 +1,1006 @@ +// +// Register Declarations for Microchip 16F874 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F874_H +#define P16F874_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F874.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F874 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F874 +// 2. LIST directive in the source file +// LIST P=PIC16F874 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.12 01/12/00 Changed some bit names, a register name, configuration bits +// to match datasheet (DS30292B) +//1.11 10/18/98 Changes to file registers to match updated DOS +//1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1 +//1.00 08/07/98 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F874 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits -------------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x0FCF +#define _CP_HALF 0x1FDF +#define _CP_UPPER_256 0x2FEF +#define _CP_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _DEBUG_OFF 0x3FFF +#define _WRT_ENABLE_ON 0x3FFF +#define _WRT_ENABLE_OFF 0x3DFF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define EEIE PIE2_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define EEIF PIR2_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f874a.h b/device/include/pic/pic16f874a.h new file mode 100644 index 00000000..3bd55dda --- /dev/null +++ b/device/include/pic/pic16f874a.h @@ -0,0 +1,1064 @@ +// +// Register Declarations for Microchip 16F874A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F874A_H +#define P16F874A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define CMCON_ADDR 0x009C +#define CVRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F874A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F877A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F874A +// 2. LIST directive in the source file +// LIST P=PIC16F874A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section. +//1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE +//1.00 04/19/01 Initial Release (BD - generated from PIC16F877A.inc) + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F874A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (CMCON_ADDR) CMCON; +extern sfr __at (CVRCON_ADDR) CVRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- CMCON Bits --------------------------------------------------------- + +//----- CVRCON Bits -------------------------------------------------------- + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B' +// __BADRAM H'105', H'107'-H'109', H'110'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _WRT_OFF 0x3FFF // No prog memmory write protection +#define _WRT_256 0x3DFF // First 256 prog memmory write protected +#define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected +#define _WRT_HALF 0x39FF // First half memmory write protected +#define _CPD_OFF 0x3FFF +#define _CPD_ON 0x3EFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _RC_OSC 0x3FFF +#define _HS_OSC 0x3FFE +#define _XT_OSC 0x3FFD +#define _LP_OSC 0x3FFC + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- CVRCON bits -------------------- +typedef union { + struct { + unsigned char CVR0:1; + unsigned char CVR1:1; + unsigned char CVR2:1; + unsigned char CVR3:1; + unsigned char :1; + unsigned char CVRR:1; + unsigned char CVROE:1; + unsigned char CVREN:1; + }; +} __CVRCON_bits_t; +extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; + +#define CVR0 CVRCON_bits.CVR0 +#define CVR1 CVRCON_bits.CVR1 +#define CVR2 CVRCON_bits.CVR2 +#define CVR3 CVRCON_bits.CVR3 +#define CVRR CVRCON_bits.CVRR +#define CVROE CVRCON_bits.CVROE +#define CVREN CVRCON_bits.CVREN + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define EEIE PIE2_bits.EEIE +#define CMIE PIE2_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define EEIF PIR2_bits.EEIF +#define CMIF PIR2_bits.CMIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f876.h b/device/include/pic/pic16f876.h new file mode 100644 index 00000000..7bf738a1 --- /dev/null +++ b/device/include/pic/pic16f876.h @@ -0,0 +1,967 @@ +// +// Register Declarations for Microchip 16F876 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F876_H +#define P16F876_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F876.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F876 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F876 +// 2. LIST directive in the source file +// LIST P=PIC16F876 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.12 01/12/00 Changed some bit names, a register name, configuration bits +// to match datasheet (DS30292B) +//1.00 08/07/98 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F876 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; + +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ---------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08'-H'09' +// __BADRAM H'88'-H'89', H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' +// __BADRAM H'105', H'107'-H'109' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x0FCF +#define _CP_HALF 0x1FDF +#define _CP_UPPER_256 0x2FEF +#define _CP_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _DEBUG_OFF 0x3FFF +#define _WRT_ENABLE_ON 0x3FFF +#define _WRT_ENABLE_OFF 0x3DFF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define EEIE PIE2_bits.EEIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define EEIF PIR2_bits.EEIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f876a.h b/device/include/pic/pic16f876a.h new file mode 100644 index 00000000..c0f1ac1c --- /dev/null +++ b/device/include/pic/pic16f876a.h @@ -0,0 +1,1024 @@ +// +// Register Declarations for Microchip 16F876A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F876A_H +#define P16F876A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define CMCON_ADDR 0x009C +#define CVRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F876A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F877A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F876A +// 2. LIST directive in the source file +// LIST P=PIC16F876A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section. +//1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE +//1.00 04/19/01 Initial Release (BD - generated from PIC16F877.inc) + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F876A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (CMCON_ADDR) CMCON; +extern sfr __at (CVRCON_ADDR) CVRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- CMCON Bits --------------------------------------------------------- + +//----- CVRCON Bits -------------------------------------------------------- + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B' +// __BADRAM H'105', H'107'-H'109' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _WRT_OFF 0x3FFF // No prog memmory write protection +#define _WRT_256 0x3DFF // First 256 prog memmory write protected +#define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected +#define _WRT_HALF 0x39FF // First half memmory write protected +#define _CPD_OFF 0x3FFF +#define _CPD_ON 0x3EFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _RC_OSC 0x3FFF +#define _HS_OSC 0x3FFE +#define _XT_OSC 0x3FFD +#define _LP_OSC 0x3FFC + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- CVRCON bits -------------------- +typedef union { + struct { + unsigned char CVR0:1; + unsigned char CVR1:1; + unsigned char CVR2:1; + unsigned char CVR3:1; + unsigned char :1; + unsigned char CVRR:1; + unsigned char CVROE:1; + unsigned char CVREN:1; + }; +} __CVRCON_bits_t; +extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; + +#define CVR0 CVRCON_bits.CVR0 +#define CVR1 CVRCON_bits.CVR1 +#define CVR2 CVRCON_bits.CVR2 +#define CVR3 CVRCON_bits.CVR3 +#define CVRR CVRCON_bits.CVRR +#define CVROE CVRCON_bits.CVROE +#define CVREN CVRCON_bits.CVREN + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define EEIE PIE2_bits.EEIE +#define CMIE PIE2_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define EEIF PIR2_bits.EEIF +#define CMIF PIR2_bits.CMIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f877.h b/device/include/pic/pic16f877.h index 325e1364..85147971 100644 --- a/device/include/pic/pic16f877.h +++ b/device/include/pic/pic16f877.h @@ -1,940 +1,1005 @@ -/* - -Small Device C Compiler (SDCC) - PIC16F877 Device Library Header 2004 - -Note an alterative header file can be generated from -inc files using peal script support/scripts/inc2h.pl - -*/ - -#ifndef PIC16F877_H -#define PIC16F877_H - - -/***************************************************************************** - RAM - *****************************************************************************/ - -#pragma maxram 0x1FF - -#pragma memmap 0x0020 0x006f RAM 0x000 -#pragma memmap 0x0070 0x007f RAM 0x180 -#pragma memmap 0x00a0 0x00ef RAM 0x000 -#pragma memmap 0x0110 0x016f RAM 0x000 -#pragma memmap 0x0190 0x01ef RAM 0x000 - - -/***************************************************************************** - Special Function Register Addresses - *****************************************************************************/ - -enum { - indf_addr = 0x0000, - tmr0_addr = 0x0001, - pcl_addr = 0x0002, - status_addr = 0x0003, - fsr_addr = 0x0004, - porta_addr = 0x0005, - portb_addr = 0x0006, - portc_addr = 0x0007, - portd_addr = 0x0008, - porte_addr = 0x0009, - pclath_addr = 0x000a, - intcon_addr = 0x000b, - pir1_addr = 0x000c, - pir2_addr = 0x000d, - tmr1l_addr = 0x000e, - tmr1h_addr = 0x000f, - t1con_addr = 0x0010, - tmr2_addr = 0x0011, - t2con_addr = 0x0012, - sspbuf_addr = 0x0013, - sspcon_addr = 0x0014, - ccpr1l_addr = 0x0015, - ccpr1h_addr = 0x0016, - ccp1con_addr = 0x0017, - rcsta_addr = 0x0018, - txreg_addr = 0x0019, - rcreg_addr = 0x001a, - ccpr2l_addr = 0x001b, - ccpr2h_addr = 0x001c, - ccp2con_addr = 0x001d, - adresh_addr = 0x001e, - adcon0_addr = 0x001f, - option_reg_addr = 0x0081, - trisa_addr = 0x0085, - trisb_addr = 0x0086, - trisc_addr = 0x0087, - trisd_addr = 0x0088, - trise_addr = 0x0089, - pie1_addr = 0x008c, - pie2_addr = 0x008d, - pcon_addr = 0x008e, - sspcon2_addr = 0x0091, - pr2_addr = 0x0092, - sspadd_addr = 0x0093, - sspstat_addr = 0x0094, - txsta_addr = 0x0098, - spbrg_addr = 0x0099, - adresl_addr = 0x009e, - adcon1_addr = 0x009f, - eedata_addr = 0x010c, - eeadr_addr = 0x010d, - eedath_addr = 0x010e, - eeadrh_addr = 0x010f, - eecon1_addr = 0x018c, - eecon2_addr = 0x018d, - config_addr = 0x2007 -}; - -/* Special function register memory map - memmap start_addr end_addr type bank_mask */ -#pragma memmap 0x001 0x001 SFR 0x080 -#pragma memmap 0x002 0x004 SFR 0x180 -#pragma memmap 0x005 0x005 SFR 0x000 -#pragma memmap 0x006 0x006 SFR 0x080 -#pragma memmap 0x007 0x009 SFR 0x000 -#pragma memmap 0x00a 0x00b SFR 0x180 -#pragma memmap 0x00c 0x01f SFR 0x000 -#pragma memmap 0x081 0x081 SFR 0x100 -#pragma memmap 0x085 0x085 SFR 0x000 -#pragma memmap 0x086 0x086 SFR 0x100 -#pragma memmap 0x087 0x089 SFR 0x000 -#pragma memmap 0x08c 0x08e SFR 0x000 -#pragma memmap 0x091 0x094 SFR 0x000 -#pragma memmap 0x098 0x099 SFR 0x000 -#pragma memmap 0x09c 0x09f SFR 0x000 -#pragma memmap 0x10c 0x10f SFR 0x000 -#pragma memmap 0x18c 0x18d SFR 0x000 - - -/***************************************************************************** - Misc Registers - *****************************************************************************/ - -/* ---- STATUS Bits -------------------------------------------------------- */ -typedef union { - struct { - unsigned c :1; /* Carry/borrow bit (ADDWF,ADDLW,SUBWF,SUBLW instructions) */ - unsigned dc :1; /* Digit carry/borrow bit (ADDWF,ADDLW,SUBWF,SUBLW instructions) */ - unsigned z :1; /* Zero bit */ - unsigned not_pd :1; /* Power down bit */ - unsigned not_to :1; /* Timeout bit */ - unsigned rp0 :1; /* Register bank select bits for direct addressing */ - unsigned rp1 :1; - unsigned irp :1; /* Register bank select bits for indirect addressing */ - }; - unsigned char r; -} status_t; - -static volatile status_t at status_addr status_b; -#define C status_b.c -#define DC status_b.dc -#define Z status_b.z -#define NOT_PD status_b.not_pd -#define NOT_TO status_b.not_to -#define RP0 status_b.rp0 -#define RP1 status_b.rp1 -#define IRP status_b.irp - -/* ---- OPTION_REG Bits ----------------------------------------------------- */ +// +// Register Declarations for Microchip 16F877 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F877_H +#define P16F877_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F877.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F877 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F877 +// 2. LIST directive in the source file +// LIST P=PIC16F877 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.12 01/12/00 Changed some bit names, a register name, configuration bits +// to match datasheet (DS30292B) +//1.00 08/07/98 Initial Release + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F877 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' +// __BADRAM H'105', H'107'-H'109' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x0FCF +#define _CP_HALF 0x1FDF +#define _CP_UPPER_256 0x2FEF +#define _CP_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _DEBUG_OFF 0x3FFF +#define _WRT_ENABLE_ON 0x3FFF +#define _WRT_ENABLE_OFF 0x3DFF +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _LP_OSC 0x3FFC +#define _XT_OSC 0x3FFD +#define _HS_OSC 0x3FFE +#define _RC_OSC 0x3FFF + +// LIST + +// ----- ADCON0 bits -------------------- typedef union { - struct { - unsigned ps0 :1; /* Prescaler rate select bits */ - unsigned ps1 :1; - unsigned ps2 :1; - unsigned psa :1; /* Prescaler assignment bit */ - unsigned t0se :1; /* TMR0 source edge select bit */ - unsigned t0cs :1; /* TMR0 clock source select bit */ - unsigned intedg :1; /* Interrupt edge select bit */ - unsigned not_rbpu :1; /* PortB pullup enable bit */ - }; - struct { - unsigned ps:3; - }; - unsigned char r; -} option_reg_t; - -static volatile option_reg_t at option_reg_addr option_reg_b; -#define PS0 option_reg_b.ps0 -#define PS1 option_reg_b.ps1 -#define PS2 option_reg_b.ps2 -#define PSA option_reg_b.psa -#define T0SE option_reg_b.t0se -#define T0CS option_reg_b.t0cs -#define INTEDG option_reg_b.intedg -#define NOT_RBPU option_reg_b.not_rbpu - -/* ---- PCON Bits ---------------------------------------------------------- */ + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- typedef union { - struct { - unsigned not_bor :1; /* Brown out reset status bit */ - unsigned not_por :1; /* Power on reset bit */ - }; - unsigned char r; -} pcon_t; - -static volatile pcon_t at pcon_addr pcon_b; -#define NOT_BOR pcon_b.not_bor -#define NOT_POR pcon_b.not_por - -/* ---- Misc Registers ----------------------------------------------------- */ -static volatile unsigned char at indf_addr indf; -sfr at status_addr status; -sfr at pcl_addr pcl; -sfr at pclath_addr pclath; -sfr at fsr_addr fsr; -sfr at option_reg_addr option_reg; -sfr at pcon_addr pcon; -sfr at pr2_addr pr2; - -#define INDF indf -#define STATUS status -#define PCL pcl -#define PCLATH pclath -#define FSR fsr -#define OPTION_REG option_reg -#define PCON pcon -#define INDF indf -#define PR2 pr2 - - -/***************************************************************************** - Ports - *****************************************************************************/ - -typedef struct { - unsigned b0 :1; - unsigned b1 :1; - unsigned b2 :1; - unsigned b3 :1; - unsigned b4 :1; - unsigned b5 :1; - unsigned b6 :1; - unsigned b7 :1; -} bits_t; - + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- typedef union { - bits_t; - unsigned char r; -} port_t; - + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- typedef union { - bits_t; - unsigned char r; -} tris_t; - -/* --- PORTA Bits ---------------------------------------------------------- */ -static volatile port_t at porta_addr porta_b; -#define PA0 porta_b.b0 -#define PA1 porta_b.b1 -#define PA2 porta_b.b2 -#define PA3 porta_b.b3 -#define PA4 porta_b.b4 -#define PA5 porta_b.b5 -#define PA6 porta_b.b6 -#define PA7 porta_b.b7 - -/* --- PORTB Bits ---------------------------------------------------------- */ -static volatile port_t at portb_addr portb_b; -#define PB0 portb_b.b0 -#define PB1 portb_b.b1 -#define PB2 portb_b.b2 -#define PB3 portb_b.b3 -#define PB4 portb_b.b4 -#define PB5 portb_b.b5 -#define PB6 portb_b.b6 -#define PB7 portb_b.b7 - -/* --- PORTC Bits ---------------------------------------------------------- */ -static volatile port_t at portc_addr portc_b; -#define PC0 portc_b.b0 -#define PC1 portc_b.b1 -#define PC2 portc_b.b2 -#define PC3 portc_b.b3 -#define PC4 portc_b.b4 -#define PC5 portc_b.b5 -#define PC6 portc_b.b6 -#define PC7 portc_b.b7 - -/* --- PORTD Bits ---------------------------------------------------------- */ -static volatile port_t at portd_addr portd_b; -#define PD0 portd_b.b0 -#define PD1 portd_b.b1 -#define PD2 portd_b.b2 -#define PD3 portd_b.b3 -#define PD4 portd_b.b4 -#define PD5 portd_b.b5 -#define PD6 portd_b.b6 -#define PD7 portd_b.b7 - -/* --- PORTE Bits ---------------------------------------------------------- */ -static volatile port_t at porte_addr porte_b; -#define RE0 porte_b.b0 -#define RE1 porte_b.b1 -#define RE2 porte_b.b2 - -/* --- TRISA Bits ---------------------------------------------------------- */ -static volatile tris_t at trisa_addr trisa_b; -#define TRISA0 trisa_b.b0 -#define TRISA1 trisa_b.b1 -#define TRISA2 trisa_b.b2 -#define TRISA3 trisa_b.b3 -#define TRISA4 trisa_b.b4 -#define TRISA5 trisa_b.b5 -#define TRISA6 trisa_b.b6 -#define TRISA7 trisa_b.b7 - -/* --- TRISB Bits ---------------------------------------------------------- */ -static tris_t at trisb_addr trisb_b; -#define TRISB0 trisb_b.b0 -#define TRISB1 trisb_b.b1 -#define TRISB2 trisb_b.b2 -#define TRISB3 trisb_b.b3 -#define TRISB4 trisb_b.b4 -#define TRISB5 trisb_b.b5 -#define TRISB6 trisb_b.b6 -#define TRISB7 trisb_b.b7 - -/* --- TRISC Bits ---------------------------------------------------------- */ -static volatile tris_t at trisc_addr trisc_b; -#define TRISC0 trisc_b.b0 -#define TRISC1 trisc_b.b1 -#define TRISC2 trisc_b.b2 -#define TRISC3 trisc_b.b3 -#define TRISC4 trisc_b.b4 -#define TRISC5 trisc_b.b5 -#define TRISC6 trisc_b.b6 -#define TRISC7 trisc_b.b7 - -/* --- TRISD Bits ---------------------------------------------------------- */ -static volatile tris_t at trisd_addr trisd_b; -#define TRISD0 trisd_b.b0 -#define TRISD1 trisd_b.b1 -#define TRISD2 trisd_b.b2 -#define TRISD3 trisd_b.b3 -#define TRISD4 trisd_b.b4 -#define TRISD5 trisd_b.b5 -#define TRISD6 trisd_b.b6 -#define TRISD7 trisd_b.b7 - -/* --- TRISE Bits ---------------------------------------------------------- */ + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- EECON1 bits -------------------- typedef union { - struct { - unsigned bit0 :1; /* Data direction bits */ - unsigned bit1 :1; - unsigned bit2 :1; - unsigned :1; - unsigned pspmode :1; /* Parrallel slave port mode select bit */ - unsigned ibov :1; /* Input buffer overflow detect bit */ - unsigned obf :1; /* Output buffer full status bit */ - unsigned ibf :1; /* Input buffer full status bit */ - }; - struct { - unsigned trise:3; - }; - bits_t; - unsigned char r; -} trise_t; - -static volatile trise_t at trise_addr trise_b; -#define TRISE0 trise_b.bit0 -#define TRISE1 trise_b.bit1 -#define TRISE2 trise_b.bit2 -#define PSPMODE trise_b.pspmode -#define IBOV trise_b.ibov -#define OBF trise_b.obf -#define IBF trise_b.ibf - -/* ---- Port Registers ----------------------------------------------------- */ -sfr at porta_addr porta; -sfr at portb_addr portb; -sfr at portc_addr portc; -sfr at portd_addr portd; -sfr at porte_addr porte; -sfr at trisa_addr trisa; -sfr at trisb_addr trisb; -sfr at trisc_addr trisc; -sfr at trisd_addr trisd; -sfr at trise_addr trise; -#define PORTA porta -#define PORTB portb -#define PORTC portc -#define PORTD portd -#define PORTE porte -#define TRISA trisa -#define TRISB trisb -#define TRISC trisc -#define TRISD trisd -#define TRISE trise - - -/***************************************************************************** - Interrupts - *****************************************************************************/ - -/* ---- INTCON Bits -------------------------------------------------------- */ + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- typedef union { - struct { - unsigned rbif :1; /* RB port change interrupt flag bit */ - unsigned ntf :1; /* RB0/INT external interrupt flag bit */ - unsigned tmr0if :1; /* TMR0 overflow interrupt flag bit */ - unsigned rbie :1; /* RB port change interrupt enable bit */ - unsigned inte :1; /* RB0/INT external interrupt enable */ - unsigned tmr0ie :1; /* TMR0 over flow interrupt enble bit */ - unsigned peie :1; /* Peripheral interrupt enable bit */ - unsigned gie :1; /* Global interrupt enable bit */ - }; - unsigned char r; -} intcon_t; - -static volatile intcon_t at intcon_addr intcon_b; -#define RBIF intcon_b.rbif -#define NTF intcon_b.ntf -#define T0IF intcon_b.tmr0if -#define RBIE intcon_b.rbie -#define INTE intcon_b.inte -#define T0IE intcon_b.tmr0ie -#define PEIE intcon_b.peie -#define GIE intcon_b.gie - -/* ---- PIR1 Bits ---------------------------------------------------------- */ + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- typedef union { - struct { - unsigned tmr1if :1; /* Tmr1 overflow interrupt flag bit */ - unsigned tmr2if :1; /* TMR2 to PR2 match interrupt flag bit */ - unsigned ccp1if :1; /* CCP1 interrupt flag bit */ - unsigned sspif :1; /* Synchronous serial port interrupt flag bit */ - unsigned txif :1; /* USART transmit interrupt flag bit */ - unsigned rcif :1; /* USART receiver interrupt flag bit */ - unsigned adif :1; /* A/D converter interrupt flag bit */ - unsigned pspif :1; /* Parrallel slave port read/write interrupt flag bit */ - }; - unsigned char r; -} pir1_t; - -static volatile pir1_t at pir1_addr pir1_b; -#define TMR1IF pir1_b.tmr1if -#define TMR2IF pir1_b.tmr2if -#define CCP1IF pir1_b.ccp1if -#define SSPIF pir1_b.sspif -#define TXIF pir1_b.txif -#define RCIF pir1_b.rcif -#define ADIF pir1_b.adif -#define PSPIF pir1_b.pspif - -/* ---- PIR2 Bits ---------------------------------------------------------- */ + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- typedef union { - struct { - unsigned ccp2if :1; /* CCP2 interrupt enable bit */ - unsigned :1; - unsigned :1; - unsigned bclif :1; /* Bus collision interrupt enable bit */ - unsigned eeif :1; /* EEPROM write operation interrupt enable bit */ - unsigned :1; - unsigned cmif :1; /* Comparitor interrupt flag bit */ - }; - unsigned char r; -} pir2_t; - -static volatile pir2_t at pir2_addr pir2_b; -#define CCP2IF pir2_b.ccp2if -#define BCLIF pir2_b.bclif -#define EEIF pir2_b.eeif - -/* ---- PIE1 Bits ---------------------------------------------------------- */ + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- typedef union { - struct { - unsigned tmr1ie :1; /* Tmr1 overflow interrupt enable bit */ - unsigned tmr2ie :1; /* TMR2 to PR2 match interrupt enable bit */ - unsigned ccp1ie :1; /* CCP1 interrupt enable bit */ - unsigned sspie :1; /* Synchronous serial port interrupt enable bit */ - unsigned txie :1; /* USART transmit interrupt enable bit */ - unsigned rcie :1; /* USART receiver interrupt enable bit */ - unsigned adie :1; /* A/D converter interrupt enable bit */ - unsigned pspie :1; /* Parrallel slave port read/write interrupt enable bit */ - }; - unsigned char r; -} pie1_t; - -static volatile pie1_t at pie1_addr pie1_b; -#define TMR1IE pie1_b.tmr1ie -#define TMR2IE pie1_b.tmr2ie -#define CCP1IE pie1_b.ccp1ie -#define SSPIE pie1_b.sspie -#define TXIE pie1_b.txie -#define RCIE pie1_b.rcie -#define ADIE pie1_b.adie -#define PSPIE pie1_b.pspie - -/* ---- PIE2 Bits ---------------------------------------------------------- */ + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- typedef union { - struct { - unsigned ccp2ie :1; /* CCP2 interrupt enable bit */ - unsigned :1; - unsigned :1; - unsigned bclie :1; /* Bus collision interrupt enable bit */ - unsigned eeie :1; /* EEPROM write operation interrupt enable bit */ - unsigned :1; - unsigned cmie :1; /* Comparitor interrupt enable bit */ - }; - unsigned char r; -} pie2_t; - -static volatile pie2_t at pie2_addr pie2_b; -#define CCP2IE pie2_b.ccp2ie -#define BCLIE pie2_b.bclie -#define EEIE pie2_b.eeie -#define CMIE pie2_b.cmie - -/* ---- Interrupt Registers ------------------------------------------------ */ -sfr at intcon_addr intcon; -sfr at pir1_addr pir1; -sfr at pir2_addr pir2; -sfr at pie1_addr pie1; -sfr at pie2_addr pie2; - -#define INTCON intcon -#define PIR1 pir1 -#define PIR2 pir2 -#define PIE1 pie1 -#define PIE2 pie2 - -/***************************************************************************** - Timers - *****************************************************************************/ - -/* ---- T1CON Bits --------------------------------------------------------- */ + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define EEIE PIE2_bits.EEIE + +// ----- PIR1 bits -------------------- typedef union { - struct { - unsigned tmr1on :1; /* Timer1 on bit */ - unsigned tmr1cs :1; /* Timer1 clock source select bit */ - unsigned t1sync :1; /* Timer1 external clock input synchronization control bit */ - unsigned t1oscen :1; /* Timer1 oscilator enable control bit */ - unsigned t1ckps0 :1; /* Timer1 input clock prescale select bits */ - unsigned t1ckps1 :1; - }; - struct { - unsigned :1; - unsigned :1; - unsigned :1; - unsigned :1; - unsigned t1ckps :2; /* Timer1 input clock prescale select bits */ - }; - bits_t; - unsigned char r; -} t1con_t; - -static volatile t1con_t at t1con_addr t1con_b; -#define TMR1ON t1con_b.tmr1on -#define TMR1CS t1con_b.tmr1cs -#define T1SYNC t1con_b.t1sync -#define NOT_T1SYNC t1con_b.t1sync -#define T1OSCEN t1con_b.t1oscen -#define T1CKPS0 t1con_b.t1ckps0 -#define T1CKPS1 t1con_b.t1ckps1 - -/* ---- T2CON Bits --------------------------------------------------------- */ + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- typedef union { - struct { - unsigned t2ckps0 :1; /* Timer2 clock prescale select bits */ - unsigned t2ckps1 :1; - unsigned tmr2on :1; /* Timer2 on bit */ - unsigned toutps0 :1; - unsigned toutps1 :1; /* Timer2 output postscale selet bits */ - unsigned toutps2 :1; - unsigned toutps3 :1; - }; - struct { - unsigned t2ckps :2; /* Timer2 clock prescale select bits */ - unsigned :1; - unsigned toutps :4; /* Timer2 output postscale selet bits */ - }; - unsigned char r; -} t2con_t; - -static volatile t2con_t at t2con_addr t2con_b; -#define T2CKPS0 t2con_b.t2ckps0 -#define T2CKPS1 t2con_b.t2ckps1 -#define TMR2ON t2con_b.tmr2on -#define TOUTPS0 t2con_b.toutps0 -#define TOUTPS1 t2con_b.toutps1 -#define TOUTPS2 t2con_b.toutps2 -#define TOUTPS3 t2con_b.toutps3 - -/* ---- Timer Registers ---------------------------------------------------- */ -sfr at tmr0_addr tmr0; -sfr at tmr1l_addr tmr1l; -sfr at tmr1h_addr tmr1h; -sfr at tmr2_addr tmr2; -sfr at t1con_addr t1con; -sfr at t2con_addr t2con; - -#define TMR0 tmr0 -#define TMR1L tmr1l -#define TMR1H tmr1h -#define TMR2 tmr2 -#define T1CON t1con -#define T2CON t2con - - -/***************************************************************************** - Comparitors - *****************************************************************************/ - -/* ----- CCPCON Bits -------------------------------------------------------- */ + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define EEIF PIR2_bits.EEIF + +// ----- RCSTA bits -------------------- typedef union { - struct { - unsigned ccpm0 :1; /* CCPx mode select bits */ - unsigned ccpm1 :1; - unsigned ccpm2 :1; - unsigned ccpm3 :1; - unsigned ccpy :1; /* PWM least significant bits */ - unsigned ccpx :1; - }; - struct { - unsigned ccpm :4; /* CCPx mode select bits */ - }; - unsigned char r; -} ccpcon_t; - -static volatile ccpcon_t at ccp1con_addr ccp1con_b; -#define CCP1M0 ccp1con_b.ccpm0 -#define CCP1M1 ccp1con_b.ccpm1 -#define CCP1M2 ccp1con_b.ccpm2 -#define CCP1M3 ccp1con_b.ccpm3 -#define CCP1Y ccp1con_b.ccpy -#define CCP1X ccp1con_b.ccpx - -static volatile ccpcon_t at ccp2con_addr ccp2con_b; -#define CCP2M0 ccp2con_b.ccpm0 -#define CCP2M1 ccp2con_b.ccpm1 -#define CCP2M2 ccp2con_b.ccpm2 -#define CCP2M3 ccp2con_b.ccpm3 -#define CCP2Y ccp2con_b.ccpy -#define CCP2X ccp2con_b.ccpx - -/* ---- Timer Registers ---------------------------------------------------- */ -sfr at ccpr1l_addr CCPR1L; -sfr at ccpr1h_addr CCPR1H; -sfr at ccp1con_addr CCP1CON; -sfr at ccpr2l_addr CCPR2L; -sfr at ccpr2h_addr CCPR2H; -sfr at ccp2con_addr CCP2CON; - - -/***************************************************************************** - SSP - *****************************************************************************/ - -/* ---- SSPCON Bits -------------------------------------------------------- */ + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- typedef union { - struct { - unsigned sspm0 :1; /* Synchronous serial port mode select bits */ - unsigned sspm1 :1; - unsigned sspm2 :1; - unsigned sspm3 :1; - unsigned ckp :1; /* Clock polarity select bits */ - unsigned sspen :1; /* Synchronous serial port enable bits */ - unsigned sspov :1; /* Receive overflow indicator bit */ - unsigned wcol :1; /* Write collision dedect bit */ - }; - struct { - unsigned sspm :4; /* Synchronous serial port mode select bits */ - }; - unsigned char r; -} sspcon_t; - -static volatile sspcon_t at sspcon_addr sspcon_b; -#define SSPM0 sspcon_b.sspm0 -#define SSPM1 sspcon_b.sspm1 -#define SSPM2 sspcon_b.sspm2 -#define SSPM3 sspcon_b.sspm3 -#define CKP sspcon_b.ckp -#define SSPEN sspcon_b.sspen -#define SSPOV sspcon_b.sspov -#define WCOL sspcon_b.wcol - -/* ---- SSPCON2 Bits -------------------------------------------------------- */ + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- typedef union { - struct { - unsigned sen :1; /* START condition enabled/stretch enabled bit */ - unsigned rsen :1; /* Repeated START condition enabled bit */ - unsigned pen :1; /* STOP condition enable bit */ - unsigned rcen :1; /* Receive enable bit */ - unsigned acken :1; /* Acknowledge sequence enable bit */ - unsigned ackdt :1; /* Acknowledge data bit (master receive mode only) */ - unsigned ackstat :1; /* Acknowledge status bit (master transmit mode only) */ - unsigned gcen :1; /* General call enable bit */ - }; - unsigned char r; -} sspcon2_t; - -static volatile sspcon2_t at sspcon2_addr sspcon2_b; -#define SEN sspcon2_b.sen -#define RSEN sspcon2_b.rsen -#define PEN sspcon2_b.pen -#define RCEN sspcon2_b.rcen -#define ACKEN sspcon2_b.acken -#define ACKDT sspcon2_b.ackdt -#define ACKSTAT sspcon2_b.ackstat -#define GCEN sspcon2_b.gcen - -/* ---- SSPSTAT Bits ------------------------------------------------------- */ + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- typedef union { - struct { - unsigned bf :1; /* Buffer full status bit (Receive mode only) */ - unsigned ua :1; /* Update address bit used in I2C mode only */ - unsigned r_w :1; /* Read write bit information used in I2C mode only */ - unsigned s :1; /* Start bit used in I2C mode only */ - unsigned p :1; /* Stop bit used in I2C mode only */ - unsigned d_a :1; /* Data address bit used in I2C mode only */ - unsigned cke :1; /* SPI clock select edge bit */ - unsigned smp :1; /* Sample bit */ - }; - unsigned char r; -} sspstat_t; - -static volatile sspstat_t at sspstat_addr sspstat_b; -#define BF sspstat_b.bf -#define UA sspstat_b.ua -#define R_W sspstat_b.r_w -#define R sspstat_b.r_w -#define I2C_READ sspstat_b.r_w -#define NOT_W sspstat_b.r_w -#define NOT_WRITE sspstat_b.r_w -#define READ_WRITE sspstat_b.r_w -#define S sspstat_b.s -#define I2C_START sspstat_b.s -#define P sspstat_b.p -#define I2C_STOP sspstat_b.p -#define D_A sspstat_b.d_a -#define D sspstat_b.d_a -#define I2C_DATA sspstat_b.d_a -#define NOT_A sspstat_b.d_a -#define NOT_ADDRESS sspstat_b.d_a -#define DATA_ADDRESS sspstat_b.d_a -#define CKE sspstat_b.cke -#define SMP sspstat_b.smp - -/* ---- SSP Registers ------------------------------------------------------ */ -sfr at sspbuf_addr sspbuf; -sfr at sspcon_addr sspcon; -sfr at sspcon2_addr sspcon2; -sfr at sspadd_addr sspadd; -sfr at sspstat_addr sspstat; -sfr at sspstat_addr sspstat; -sfr at sspcon2_addr sspcon2; -sfr at sspcon_addr sspcon; - -#define SSPBUF sspbuf -#define SSPCON sspcon -#define SSPCON2 sspcon2 -#define SSPADD sspadd -#define SSPSTAT sspstat - -/***************************************************************************** - USART - *****************************************************************************/ - -/* ---- RCSTA Bits --------------------------------------------------------- */ + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- typedef union { - struct { - unsigned rx9d :1; /* 9the bit of received data (can be parity bit but must be calculated by user firmware */ - unsigned oerr :1; /* Overrun error bit */ - unsigned ferr :1; /* Framing error bit */ - unsigned adden :1; /* Address detect enable bit */ - unsigned cren :1; /* Continuous receive enable bit */ - unsigned sren :1; /* Single receive enable bit */ - unsigned rx9 :1; /* 9th bit receive enable bit */ - unsigned spen :1; /* Serial port enbale bit */ - }; - unsigned char r; -} rcsta_t; - -static volatile rcsta_t at rcsta_addr rcsta_b; -#define SPEN rcsta_b.spen -#define RX9 rcsta_b.rx9 -#define SREN rcsta_b.sren -#define CREN rcsta_b.cren -#define ADDEN rcsta_b.adden -#define FERR rcsta_b.ferr -#define OERR rcsta_b.oerr -#define RX9D rcsta_b.rx9d - -/* ---- TXSTA Bits --------------------------------------------------------- */ + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- typedef union { - struct { - unsigned tx9d :1; /* 9th bit of transmit data, can be parity */ - unsigned trmt :1; /* Transmit shift register status bit */ - unsigned brgh :1; /* High baud rate select bit */ - unsigned :1; - unsigned sync :1; /* USART mode select bit */ - unsigned txen :1; /* Transmit enable bit */ - unsigned tx9 :1; /* 9th bit transmit enable */ - unsigned csrc :1; /* Clock source select bit */ - }; - unsigned char r; -} txsta_t; - -static volatile txsta_t at txsta_addr txsta_b; -#define CSRC txsta_b.csrc -#define TX9 txsta_b.tx9 -#define TXEN txsta_b.txen -#define SYNC txsta_b.sync -#define BRGH txsta_b.brgh -#define TRMT txsta_b.trmt -#define TX9D txsta_b.tx9d - -/* ---- USART Registers ---------------------------------------------------- */ -sfr at spbrg_addr spbrg; -sfr at rcreg_addr rcreg; -sfr at txreg_addr txreg; -sfr at rcsta_addr rcsta; -sfr at txsta_addr txsta; -#define SPBRG spbrg -#define RCREG rcreg -#define TXREG txreg -#define RCSTA rcsta -#define TXSTA txsta - - -/***************************************************************************** - ADC - *****************************************************************************/ - -/* ---- ADCON0 Bits -------------------------------------------------------- */ + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- typedef union { - struct { - unsigned adon :1; /* A/D on bit */ - unsigned :1; - unsigned go_done :1; /* A/D conversion start bit and not done status bit */ - unsigned chs0 :1; /* Analog chanel select bits */ - unsigned chs1 :1; - unsigned chs2 :1; - unsigned adcs0 :1; /* A/D conversion clock select bits */ - unsigned adcs1 :1; - }; - struct { - unsigned :1; - unsigned :1; - unsigned chs :3; /* Analog chanel select bits */ - unsigned adcs :2; /* A/D conversion clock select bits */ - }; - unsigned char r; -} adcon0_t; - -static volatile adcon0_t at adcon0_addr adcon0_b; -#define GO adcon0_b.go_done -#define NOT_DONE adcon0_b.go_done -#define GO_DONE adcon0_b.go_done -#define ADON adcon0_b.adon -#define CHS0 adcon0_b.chs0 -#define CHS1 adcon0_b.chs1 -#define CHS2 adcon0_b.chs2 -#define ADCS0 adcon0_b.adcs0 -#define ADCS1 adcon0_b.adcs1 - -/* ---- ADCON1 Bits -------------------------------------------------------- */ + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- typedef union { - struct { - unsigned pcfg0 :1; /* A/D port configuration control bits */ - unsigned pcfg1 :1; - unsigned pcfg2 :1; - unsigned pcfg3 :1; - unsigned :2; - unsigned adcs2 :1; /* A/D convertion clock select bit */ - unsigned adfm :1; /* A/D result format select bit */ - }; - struct { - unsigned pcfg :4; /* A/D port configuration control bits */ - }; - unsigned char r; -} adcon1_t; - -static volatile adcon1_t at adcon1_addr adcon1_b; -#define PCFG0 adcon1_b.pcfg0 -#define PCFG1 adcon1_b.pcfg1 -#define PCFG2 adcon1_b.pcfg2 -#define PCFG3 adcon1_b.pcfg3 -#define ADFM adcon1_b.adfm - -/* ---- ADC Registers ---------------------------------------------------- */ -sfr at adresh_addr adresh; -sfr at adresh_addr adresl; -sfr at adcon0_addr adcon0; -sfr at adcon1_addr adcon1; -#define ADRESH adresh -#define ADRESL adresl -#define ADCON0 adcon0 -#define ADCON1 adcon1 - - -/***************************************************************************** - EEPROM - *****************************************************************************/ - -/* ---- EECON1 Bits -------------------------------------------------------- */ + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- typedef union { - struct { - unsigned rd :1; /* Read control bit */ - unsigned wr :1; /* Write control bit */ - unsigned wren :1; /* EEPROM write enable bit */ - unsigned wrerr :1; /* EEPROM error flag bit */ - unsigned :3; - unsigned eepgd :1; /* Program data EEPROM select bit */ - }; - unsigned char r; -} eecon1_t; - -static volatile eecon1_t at eecon1_addr eecon1_b; -#define RD eecon1_b.rd -#define WR eecon1_b.wr -#define WREN eecon1_b.wren -#define WRERR eecon1_b.wrerr -#define EEPGD eecon1_b.eepgd - -/* ---- EEPROM Registers ------------------------------------------------- */ -sfr at eedata_addr eedata; -sfr at eeadr_addr eeadr; -sfr at eedath_addr eedath; -sfr at eeadrh_addr eeadrh; -sfr at eecon1_addr eecon1; -sfr at eecon2_addr eecon2; - -#define EEDATA eedata -#define EEADR eeadr -#define EEDATH eedath -#define EEADRH eeadrh -#define EECON1 eecon1 -#define EECON2 eecon2 - - -/***************************************************************************** - Config Bits - *****************************************************************************/ -enum { - cp_all = 0x0fcf, - cp_half = 0x1fdf, - cp_upper_256 = 0x2fef, - cp_off = 0x3fff, - debug_on = 0x37ff, - debug_off = 0x3fff, - wrt_enable_on = 0x3fff, - wrt_enable_off = 0x3dff, - cpd_on = 0x3eff, - cpd_off = 0x3fff, - lvp_on = 0x3fff, - lvp_off = 0x3f7f, - boden_on = 0x3fff, - boden_off = 0x3fbf, - pwrte_off = 0x3fff, - pwrte_on = 0x3ff7, - wdt_on = 0x3fff, - wdt_off = 0x3ffb, - lp_osc = 0x3ffc, - xt_osc = 0x3ffd, - hs_osc = 0x3ffe, - rc_osc = 0x3fff -}; - -#endif /* PIC16F877_H */ + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f877a.h b/device/include/pic/pic16f877a.h new file mode 100644 index 00000000..ec39d139 --- /dev/null +++ b/device/include/pic/pic16f877a.h @@ -0,0 +1,1076 @@ +// +// Register Declarations for Microchip 16F877A Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F877A_H +#define P16F877A_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define SSPCON2_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define CMCON_ADDR 0x009C +#define CVRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2 +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F877A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F877A microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F877A +// 2. LIST directive in the source file +// LIST P=PIC16F877A +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section. +//1.01 09/13/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE +//1.00 04/19/01 Initial Release (BD - generated from PIC16F877.inc) + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F877A +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (SSPCON2_ADDR) SSPCON2; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (CMCON_ADDR) CMCON; +extern sfr __at (CVRCON_ADDR) CVRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- TRISE Bits --------------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- SSPCON2 Bits -------------------------------------------------------- + + +//----- SSPSTAT Bits ------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- CMCON Bits --------------------------------------------------------- + +//----- CVRCON Bits -------------------------------------------------------- + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- EECON1 Bits -------------------------------------------------------- + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B' +// __BADRAM H'105', H'107'-H'109' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _WRT_OFF 0x3FFF // No prog memmory write protection +#define _WRT_256 0x3DFF // First 256 prog memmory write protected +#define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected +#define _WRT_HALF 0x39FF // First half memmory write protected +#define _CPD_OFF 0x3FFF +#define _CPD_ON 0x3EFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _RC_OSC 0x3FFF +#define _HS_OSC 0x3FFE +#define _XT_OSC 0x3FFD +#define _LP_OSC 0x3FFC + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char PCFG0:1; + unsigned char PCFG1:1; + unsigned char PCFG2:1; + unsigned char PCFG3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define PCFG0 ADCON1_bits.PCFG0 +#define PCFG1 ADCON1_bits.PCFG1 +#define PCFG2 ADCON1_bits.PCFG2 +#define PCFG3 ADCON1_bits.PCFG3 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- CVRCON bits -------------------- +typedef union { + struct { + unsigned char CVR0:1; + unsigned char CVR1:1; + unsigned char CVR2:1; + unsigned char CVR3:1; + unsigned char :1; + unsigned char CVRR:1; + unsigned char CVROE:1; + unsigned char CVREN:1; + }; +} __CVRCON_bits_t; +extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; + +#define CVR0 CVRCON_bits.CVR0 +#define CVR1 CVRCON_bits.CVR1 +#define CVR2 CVRCON_bits.CVR2 +#define CVR3 CVRCON_bits.CVR3 +#define CVRR CVRCON_bits.CVRR +#define CVROE CVRCON_bits.CVROE +#define CVREN CVRCON_bits.CVREN + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char TMR0IF:1; + unsigned char :1; + unsigned char :1; + unsigned char TMR0IE:1; + unsigned char :1; + unsigned char :1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char PSPIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define PSPIE PIE1_bits.PSPIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIE:1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char :1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define BCLIE PIE2_bits.BCLIE +#define EEIE PIE2_bits.EEIE +#define CMIE PIE2_bits.CMIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char PSPIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define PSPIF PIR1_bits.PSPIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char :1; + unsigned char BCLIF:1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char :1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define BCLIF PIR2_bits.BCLIF +#define EEIF PIR2_bits.EEIF +#define CMIF PIR2_bits.CMIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPCON2 bits -------------------- +typedef union { + struct { + unsigned char SEN:1; + unsigned char RSEN:1; + unsigned char PEN:1; + unsigned char RCEN:1; + unsigned char ACKEN:1; + unsigned char ACKDT:1; + unsigned char ACKSTAT:1; + unsigned char GCEN:1; + }; +} __SSPCON2_bits_t; +extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; + +#define SEN SSPCON2_bits.SEN +#define RSEN SSPCON2_bits.RSEN +#define PEN SSPCON2_bits.PEN +#define RCEN SSPCON2_bits.RCEN +#define ACKEN SSPCON2_bits.ACKEN +#define ACKDT SSPCON2_bits.ACKDT +#define ACKSTAT SSPCON2_bits.ACKSTAT +#define GCEN SSPCON2_bits.GCEN + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TRISE bits -------------------- +typedef union { + struct { + unsigned char TRISE0:1; + unsigned char TRISE1:1; + unsigned char TRISE2:1; + unsigned char :1; + unsigned char PSPMODE:1; + unsigned char IBOV:1; + unsigned char OBF:1; + unsigned char IBF:1; + }; +} __TRISE_bits_t; +extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + +#define TRISE0 TRISE_bits.TRISE0 +#define TRISE1 TRISE_bits.TRISE1 +#define TRISE2 TRISE_bits.TRISE2 +#define PSPMODE TRISE_bits.PSPMODE +#define IBOV TRISE_bits.IBOV +#define OBF TRISE_bits.OBF +#define IBF TRISE_bits.IBF + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +#endif diff --git a/device/include/pic/pic16f88.h b/device/include/pic/pic16f88.h new file mode 100644 index 00000000..1b6cb402 --- /dev/null +++ b/device/include/pic/pic16f88.h @@ -0,0 +1,1057 @@ +// +// Register Declarations for Microchip 16F88 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F88_H +#define P16F88_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define ANSEL_ADDR 0x009B +#define CMCON_ADDR 0x009C +#define CVRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define WDTCON_ADDR 0x0105 +#define EEDATA_ADDR 0x010C +#define EEADR_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON +#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA +#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F88.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F88 microcontroller. These names are taken to match +// the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F88 +// 2. LIST directive in the source file +// LIST P=PIC16F88 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: + +//1.00 07/29/02 Initial Release +//1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS +//1.02 01/10/03 Added bit names for TXSTA & RCSTA registers. +//1.03 01/24/03 Changed Config bit CCP1_RB2 to CCP1_RB0 +//1.04 12/02/03 Modified the WRT1:WRT0 bit definition in Config Word 1. +//1.05 02/08/04 Changed bit in _CONFIG1 example from CCP1_RB2 to CCP1_RB0. + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F88 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (CMCON_ADDR) CMCON; +extern sfr __at (CVRCON_ADDR) CVRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (EEDATA_ADDR) EEDATA; +extern sfr __at (EEADR_ADDR) EEADR; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + +//----- INTCON Bits -------------------------------------------------------- + +//----- PIR1 Bits ---------------------------------------------------------- + +//----- PIR2 Bits ---------------------------------------------------------- + +//----- T1CON Bits --------------------------------------------------------- + +//----- T2CON Bits --------------------------------------------------------- + +//----- SSPCON Bits -------------------------------------------------------- + +//----- CCP1CON Bits ------------------------------------------------------- + +//----- RCSTA Bits --------------------------------------------------------- + +//----- ADCON0 Bits -------------------------------------------------------- + +//----- OPTION Bits ----------------------------------------------------- + +//----- PIE1 Bits ---------------------------------------------------------- + +//----- PIE2 Bits ---------------------------------------------------------- + +//----- PCON Bits ---------------------------------------------------------- + +//----- OSCCON Bits ------------------------------------------------------- + +//----- OSCTUNE Bits ------------------------------------------------------- + +//----- SSPSTAT Bits ------------------------------------------------------- + +//----- TXSTA Bits --------------------------------------------------------- + +//----- ADCON1 Bits -------------------------------------------------------- + +//----- WDTCON Bits -------------------------------------------------------- + +//----- CMCON Bits --------------------------------------------------------- + +//----- CVRCON Bits -------------------------------------------------------- + +//----- EECON1 Bits -------------------------------------------------------- + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'07'-H'09', H'1B'-H'1D' +// __BADRAM H'87'-H'89', H'91', H'95'-H'97', H'9A' +// __BADRAM H'107'-H'109' +// __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CONFIG1 0x2007 +#define _CONFIG2 0x2008 + +//Configuration Byte 1 Options +#define _CP_ALL 0x1FFF +#define _CP_OFF 0x3FFF +#define _CCP1_RB0 0x3FFF +#define _CCP1_RB3 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _DEBUG_ON 0x37FF +#define _WRT_PROTECT_OFF 0x3FFF //No program memory write protection +#define _WRT_PROTECT_256 0x3DFF //First 256 program memory protected +#define _WRT_PROTECT_2048 0x3BFF //First 2048 program memory protected +#define _WRT_PROTECT_ALL 0x39FF //All of program memory protected +#define _CPD_ON 0x3EFF +#define _CPD_OFF 0x3FFF +#define _LVP_ON 0x3FFF +#define _LVP_OFF 0x3F7F +#define _BODEN_ON 0x3FFF +#define _BODEN_OFF 0x3FBF +#define _MCLR_ON 0x3FFF +#define _MCLR_OFF 0x3FDF +#define _PWRTE_OFF 0x3FFF +#define _PWRTE_ON 0x3FF7 +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FFB +#define _EXTRC_CLKOUT 0x3FFF +#define _EXTRC_IO 0x3FFE +#define _INTRC_CLKOUT 0x3FFD +#define _INTRC_IO 0x3FFC +#define _EXTCLK 0x3FEF +#define _HS_OSC 0x3FEE +#define _XT_OSC 0x3FED +#define _LP_OSC 0x3FEC + +//Configuration Byte 2 Options +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3FFD +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x3FFE + + + +// To use the Configuration Bits, place the following lines in your source code +// in the following format, and change the configuration value to the desired +// setting (such as CP_OFF to CP_ALL). These are currently commented out here +// and each __CONFIG line should have the preceding semicolon removed when +// pasted into your source code. + +//Program Configuration Register 1 +// __CONFIG _CONFIG1, _CP_OFF & _CCP1_RB0 & _DEBUG_OFF & _WRT_PROTECT_OFF & _CPD_OFF & _LVP_OFF & _BODEN_OFF & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC + +//Program Configuration Register 2 +// __CONFIG _CONFIG2, _IESO_OFF & _FCMEN_OFF + + + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char :1; + unsigned char GO:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define GO ADCON0_bits.GO +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define ADCS0 ADCON0_bits.ADCS0 +#define ADCS1 ADCON0_bits.ADCS1 + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char ADCS2:1; + unsigned char ADFM:1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define VCFG0 ADCON1_bits.VCFG0 +#define VCFG1 ADCON1_bits.VCFG1 +#define ADCS2 ADCON1_bits.ADCS2 +#define ADFM ADCON1_bits.ADFM + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CMCON bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON_bits_t; +extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; + +#define CM0 CMCON_bits.CM0 +#define CM1 CMCON_bits.CM1 +#define CM2 CMCON_bits.CM2 +#define CIS CMCON_bits.CIS +#define C1INV CMCON_bits.C1INV +#define C2INV CMCON_bits.C2INV +#define C1OUT CMCON_bits.C1OUT +#define C2OUT CMCON_bits.C2OUT + +// ----- CVRCON bits -------------------- +typedef union { + struct { + unsigned char CVR0:1; + unsigned char CVR1:1; + unsigned char CVR2:1; + unsigned char CVR3:1; + unsigned char :1; + unsigned char CVRR:1; + unsigned char CVROE:1; + unsigned char CVREN:1; + }; +} __CVRCON_bits_t; +extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; + +#define CVR0 CVRCON_bits.CVR0 +#define CVR1 CVRCON_bits.CVR1 +#define CVR2 CVRCON_bits.CVR2 +#define CVR3 CVRCON_bits.CVR3 +#define CVRR CVRCON_bits.CVRR +#define CVROE CVRCON_bits.CVROE +#define CVREN CVRCON_bits.CVREN + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char FREE:1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define WR EECON1_bits.WR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define FREE EECON1_bits.FREE +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char TMR0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char TMR0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS0:1; + unsigned char SCS1:1; + unsigned char IOFS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS0 OSCCON_bits.SCS0 +#define SCS1 OSCCON_bits.SCS1 +#define IOFS OSCCON_bits.IOFS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char TUN5:1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 +#define TUN5 OSCTUNE_bits.TUN5 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char :1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIE:1; + unsigned char :1; + unsigned char CMIE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define EEIE PIE2_bits.EEIE +#define CMIE PIE2_bits.CMIE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char :1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEIF:1; + unsigned char :1; + unsigned char CMIF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define EEIF PIR2_bits.EEIF +#define CMIF PIR2_bits.CMIF +#define OSFIF PIR2_bits.OSFIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char T1RUN:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define T1RUN T1CON_bits.T1RUN + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char SWDTE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define SWDTE WDTCON_bits.SWDTE +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +#endif diff --git a/device/include/pic/pic16f913.h b/device/include/pic/pic16f913.h new file mode 100644 index 00000000..4d0af39f --- /dev/null +++ b/device/include/pic/pic16f913.h @@ -0,0 +1,1849 @@ +// +// Register Declarations for Microchip 16F913 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F913_H +#define P16F913_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define ANSEL_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPUB_ADDR 0x0095 +#define WPU_ADDR 0x0095 +#define IOCB_ADDR 0x0096 +#define IOC_ADDR 0x0096 +#define CMCON1_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define CMCON0_ADDR 0x009C +#define VRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define WDTCON_ADDR 0x0105 +#define LCDCON_ADDR 0x0107 +#define LCDPS_ADDR 0x0108 +#define LVDCON_ADDR 0x0109 +#define EEDATL_ADDR 0x010C +#define EEADRL_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define LCDDATA0_ADDR 0x0110 +#define LCDDATA1_ADDR 0x0111 +#define LCDDATA3_ADDR 0x0113 +#define LCDDATA4_ADDR 0x0114 +#define LCDDATA6_ADDR 0x0116 +#define LCDDATA7_ADDR 0x0117 +#define LCDDATA9_ADDR 0x0119 +#define LCDDATA10_ADDR 0x011A +#define LCDSE0_ADDR 0x011C +#define LCDSE1_ADDR 0x011D +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0 +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON +#pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap EEDATL_ADDR EEDATL_ADDR SFR 0x000 // EEDATL +#pragma memmap EEADRL_ADDR EEADRL_ADDR SFR 0x000 // EEADRL +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap LCDDATA0_ADDR LCDDATA0_ADDR SFR 0x000 // LCDDATA0 +#pragma memmap LCDDATA1_ADDR LCDDATA1_ADDR SFR 0x000 // LCDDATA1 +#pragma memmap LCDDATA3_ADDR LCDDATA3_ADDR SFR 0x000 // LCDDATA3 +#pragma memmap LCDDATA4_ADDR LCDDATA4_ADDR SFR 0x000 // LCDDATA4 +#pragma memmap LCDDATA6_ADDR LCDDATA6_ADDR SFR 0x000 // LCDDATA6 +#pragma memmap LCDDATA7_ADDR LCDDATA7_ADDR SFR 0x000 // LCDDATA7 +#pragma memmap LCDDATA9_ADDR LCDDATA9_ADDR SFR 0x000 // LCDDATA9 +#pragma memmap LCDDATA10_ADDR LCDDATA10_ADDR SFR 0x000 // LCDDATA10 +#pragma memmap LCDSE0_ADDR LCDSE0_ADDR SFR 0x000 // LCDSE0 +#pragma memmap LCDSE1_ADDR LCDSE1_ADDR SFR 0x000 // LCDSE1 +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F913.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F913 microcontroller. +// These names are taken to match the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F913 +// 2. LIST directive in the source file +// LIST P=PIC16F913 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.00 06/11/04 Initial Release +//1.01 06/18/04 Corrected typo in 'bad ram' section +//1.02 08/16/04 Added EECON2 + + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F913 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (IOCB_ADDR) IOCB; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (CMCON1_ADDR) CMCON1; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (CMCON0_ADDR) CMCON0; +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (LCDCON_ADDR) LCDCON; +extern sfr __at (LCDPS_ADDR) LCDPS; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (EEDATL_ADDR) EEDATL; +extern sfr __at (EEADRL_ADDR) EEADRL; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; +extern sfr __at (LCDDATA0_ADDR) LCDDATA0; +extern sfr __at (LCDDATA1_ADDR) LCDDATA1; +extern sfr __at (LCDDATA3_ADDR) LCDDATA3; +extern sfr __at (LCDDATA4_ADDR) LCDDATA4; +extern sfr __at (LCDDATA6_ADDR) LCDDATA6; +extern sfr __at (LCDDATA7_ADDR) LCDDATA7; +extern sfr __at (LCDDATA9_ADDR) LCDDATA9; +extern sfr __at (LCDDATA10_ADDR) LCDDATA10; +extern sfr __at (LCDSE0_ADDR) LCDSE0; +extern sfr __at (LCDSE1_ADDR) LCDSE1; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits ------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + + +//----- ANSEL Bits --------------------------------------------------------- + + + +//----- SSPSTAT Bits ------------------------------------------------------- + + + +//----- WPUB Bits ------------------------------------------------------- + + +//----- WPU Bits ------------------------------------------------------- + + + +//----- IOCB Bits ------------------------------------------------------- + + + +//----- IOC Bits ------------------------------------------------------- + + + +//----- CMCON1 Bits -------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- CMCON0 Bits --------------------------------------------------------- + + +//----- VRCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- LCDCON Bits -------------------------------------------------------- + + +//----- LCDPS Bits --------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- LCDDATA0 Bits ------------------------------------------------------- + + + +//----- LCDDATA1 Bits ------------------------------------------------------- + + + + +//----- LCDDATA3 Bits ------------------------------------------------------- + + + +//----- LCDDATA4 Bits ------------------------------------------------------- + + + + +//----- LCDDATA6 Bits ------------------------------------------------------- + + + +//----- LCDDATA7 Bits ------------------------------------------------------- + + + + +//----- LCDDATA9 Bits ------------------------------------------------------- + + + +//----- LCDDATA10 Bits ------------------------------------------------------- + + + + +//----- LCDSE0 Bits -------------------------------------------------------- + + + +//----- LCDSE1 Bits -------------------------------------------------------- + + + + +//----- EECON1 Bits -------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08', H'1B'-H'1D' +// __BADRAM H'88', H'9A'-H'9B' +// __BADRAM H'112', H'115', H'118', H'11B',H'11E'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CONFIG 0x2007 + +//Configuration Byte 1 Options +#define _DEBUG_ON 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_ON 0x3FEF +#define _PWRTE_OFF 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char NOT_DONE:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define VCFG0 ADCON0_bits.VCFG0 +#define VCFG1 ADCON0_bits.VCFG1 +#define ADFM ADCON0_bits.ADFM + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + unsigned char ADCS2:1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define ADCS0 ADCON1_bits.ADCS0 +#define ADCS1 ADCON1_bits.ADCS1 +#define ADCS2 ADCON1_bits.ADCS2 + +// ----- ANSEL bits -------------------- +typedef union { + struct { + unsigned char AN0:1; + unsigned char AN1:1; + unsigned char AN2:1; + unsigned char AN3:1; + unsigned char AN4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ANSEL_bits_t; +extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits; + +#define AN0 ANSEL_bits.AN0 +#define AN1 ANSEL_bits.AN1 +#define AN2 ANSEL_bits.AN2 +#define AN3 ANSEL_bits.AN3 +#define AN4 ANSEL_bits.AN4 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CMCON0 bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON0_bits_t; +extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; + +#define CM0 CMCON0_bits.CM0 +#define CM1 CMCON0_bits.CM1 +#define CM2 CMCON0_bits.CM2 +#define CIS CMCON0_bits.CIS +#define C1INV CMCON0_bits.C1INV +#define C2INV CMCON0_bits.C2INV +#define C1OUT CMCON0_bits.C1OUT +#define C2OUT CMCON0_bits.C2OUT + +// ----- CMCON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __CMCON1_bits_t; +extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; + +#define C2SYNC CMCON1_bits.C2SYNC +#define T1GSS CMCON1_bits.T1GSS + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; + struct { + unsigned char EERD:1; + unsigned char EEWR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define EERD EECON1_bits.EERD +#define WR EECON1_bits.WR +#define EEWR EECON1_bits.EEWR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char TMR0IF:1; + unsigned char :1; + unsigned char :1; + unsigned char TMR0IE:1; + unsigned char :1; + unsigned char :1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- IOC bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOC4:1; + unsigned char IOC5:1; + unsigned char IOC6:1; + unsigned char IOC7:1; + }; +} __IOC_bits_t; +extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits; + +#define IOC4 IOC_bits.IOC4 +#define IOC5 IOC_bits.IOC5 +#define IOC6 IOC_bits.IOC6 +#define IOC7 IOC_bits.IOC7 + +// ----- IOCB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOCB4:1; + unsigned char IOCB5:1; + unsigned char IOCB6:1; + unsigned char IOCB7:1; + }; +} __IOCB_bits_t; +extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits; + +#define IOCB4 IOCB_bits.IOCB4 +#define IOCB5 IOCB_bits.IOCB5 +#define IOCB6 IOCB_bits.IOCB6 +#define IOCB7 IOCB_bits.IOCB7 + +// ----- LCDCON bits -------------------- +typedef union { + struct { + unsigned char LMUX0:1; + unsigned char LMUX1:1; + unsigned char CS0:1; + unsigned char CS1:1; + unsigned char VLCDEN:1; + unsigned char WERR:1; + unsigned char SLPEN:1; + unsigned char LCDEN:1; + }; +} __LCDCON_bits_t; +extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; + +#define LMUX0 LCDCON_bits.LMUX0 +#define LMUX1 LCDCON_bits.LMUX1 +#define CS0 LCDCON_bits.CS0 +#define CS1 LCDCON_bits.CS1 +#define VLCDEN LCDCON_bits.VLCDEN +#define WERR LCDCON_bits.WERR +#define SLPEN LCDCON_bits.SLPEN +#define LCDEN LCDCON_bits.LCDEN + +// ----- LCDDATA0 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM0:1; + unsigned char SEG1COM0:1; + unsigned char SEG2COM0:1; + unsigned char SEG3COM0:1; + unsigned char SEG4COM0:1; + unsigned char SEG5COM0:1; + unsigned char SEG6COM0:1; + unsigned char SEG7COM0:1; + }; + struct { + unsigned char S0C0:1; + unsigned char S1C0:1; + unsigned char S2C0:1; + unsigned char S3C0:1; + unsigned char S4C0:1; + unsigned char S5C0:1; + unsigned char S6C0:1; + unsigned char S7C0:1; + }; +} __LCDDATA0_bits_t; +extern volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits; + +#define SEG0COM0 LCDDATA0_bits.SEG0COM0 +#define S0C0 LCDDATA0_bits.S0C0 +#define SEG1COM0 LCDDATA0_bits.SEG1COM0 +#define S1C0 LCDDATA0_bits.S1C0 +#define SEG2COM0 LCDDATA0_bits.SEG2COM0 +#define S2C0 LCDDATA0_bits.S2C0 +#define SEG3COM0 LCDDATA0_bits.SEG3COM0 +#define S3C0 LCDDATA0_bits.S3C0 +#define SEG4COM0 LCDDATA0_bits.SEG4COM0 +#define S4C0 LCDDATA0_bits.S4C0 +#define SEG5COM0 LCDDATA0_bits.SEG5COM0 +#define S5C0 LCDDATA0_bits.S5C0 +#define SEG6COM0 LCDDATA0_bits.SEG6COM0 +#define S6C0 LCDDATA0_bits.S6C0 +#define SEG7COM0 LCDDATA0_bits.SEG7COM0 +#define S7C0 LCDDATA0_bits.S7C0 + +// ----- LCDDATA1 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM0:1; + unsigned char SEG9COM0:1; + unsigned char SEG10COM0:1; + unsigned char SEG11COM0:1; + unsigned char SEG12COM0:1; + unsigned char SEG13COM0:1; + unsigned char SEG14COM0:1; + unsigned char SEG15COM0:1; + }; + struct { + unsigned char S8C0:1; + unsigned char S9C0:1; + unsigned char S10C0:1; + unsigned char S11C0:1; + unsigned char S12C0:1; + unsigned char S13C0:1; + unsigned char S14C0:1; + unsigned char S15C0:1; + }; +} __LCDDATA1_bits_t; +extern volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits; + +#define SEG8COM0 LCDDATA1_bits.SEG8COM0 +#define S8C0 LCDDATA1_bits.S8C0 +#define SEG9COM0 LCDDATA1_bits.SEG9COM0 +#define S9C0 LCDDATA1_bits.S9C0 +#define SEG10COM0 LCDDATA1_bits.SEG10COM0 +#define S10C0 LCDDATA1_bits.S10C0 +#define SEG11COM0 LCDDATA1_bits.SEG11COM0 +#define S11C0 LCDDATA1_bits.S11C0 +#define SEG12COM0 LCDDATA1_bits.SEG12COM0 +#define S12C0 LCDDATA1_bits.S12C0 +#define SEG13COM0 LCDDATA1_bits.SEG13COM0 +#define S13C0 LCDDATA1_bits.S13C0 +#define SEG14COM0 LCDDATA1_bits.SEG14COM0 +#define S14C0 LCDDATA1_bits.S14C0 +#define SEG15COM0 LCDDATA1_bits.SEG15COM0 +#define S15C0 LCDDATA1_bits.S15C0 + +// ----- LCDDATA10 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM3:1; + unsigned char SEG9COM3:1; + unsigned char SEG10COM3:1; + unsigned char SEG11COM3:1; + unsigned char SEG12COM3:1; + unsigned char SEG13COM3:1; + unsigned char SEG14COM3:1; + unsigned char SEG15COM3:1; + }; + struct { + unsigned char S8C3:1; + unsigned char S9C3:1; + unsigned char S10C3:1; + unsigned char S11C3:1; + unsigned char S12C3:1; + unsigned char S13C3:1; + unsigned char S14C3:1; + unsigned char S15C3:1; + }; +} __LCDDATA10_bits_t; +extern volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits; + +#define SEG8COM3 LCDDATA10_bits.SEG8COM3 +#define S8C3 LCDDATA10_bits.S8C3 +#define SEG9COM3 LCDDATA10_bits.SEG9COM3 +#define S9C3 LCDDATA10_bits.S9C3 +#define SEG10COM3 LCDDATA10_bits.SEG10COM3 +#define S10C3 LCDDATA10_bits.S10C3 +#define SEG11COM3 LCDDATA10_bits.SEG11COM3 +#define S11C3 LCDDATA10_bits.S11C3 +#define SEG12COM3 LCDDATA10_bits.SEG12COM3 +#define S12C3 LCDDATA10_bits.S12C3 +#define SEG13COM3 LCDDATA10_bits.SEG13COM3 +#define S13C3 LCDDATA10_bits.S13C3 +#define SEG14COM3 LCDDATA10_bits.SEG14COM3 +#define S14C3 LCDDATA10_bits.S14C3 +#define SEG15COM3 LCDDATA10_bits.SEG15COM3 +#define S15C3 LCDDATA10_bits.S15C3 + +// ----- LCDDATA3 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM1:1; + unsigned char SEG1COM1:1; + unsigned char SEG2COM1:1; + unsigned char SEG3COM1:1; + unsigned char SEG4COM1:1; + unsigned char SEG5COM1:1; + unsigned char SEG6COM1:1; + unsigned char SEG7COM1:1; + }; + struct { + unsigned char S0C1:1; + unsigned char S1C1:1; + unsigned char S2C1:1; + unsigned char S3C1:1; + unsigned char S4C1:1; + unsigned char S5C1:1; + unsigned char S6C1:1; + unsigned char S7C1:1; + }; +} __LCDDATA3_bits_t; +extern volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits; + +#define SEG0COM1 LCDDATA3_bits.SEG0COM1 +#define S0C1 LCDDATA3_bits.S0C1 +#define SEG1COM1 LCDDATA3_bits.SEG1COM1 +#define S1C1 LCDDATA3_bits.S1C1 +#define SEG2COM1 LCDDATA3_bits.SEG2COM1 +#define S2C1 LCDDATA3_bits.S2C1 +#define SEG3COM1 LCDDATA3_bits.SEG3COM1 +#define S3C1 LCDDATA3_bits.S3C1 +#define SEG4COM1 LCDDATA3_bits.SEG4COM1 +#define S4C1 LCDDATA3_bits.S4C1 +#define SEG5COM1 LCDDATA3_bits.SEG5COM1 +#define S5C1 LCDDATA3_bits.S5C1 +#define SEG6COM1 LCDDATA3_bits.SEG6COM1 +#define S6C1 LCDDATA3_bits.S6C1 +#define SEG7COM1 LCDDATA3_bits.SEG7COM1 +#define S7C1 LCDDATA3_bits.S7C1 + +// ----- LCDDATA4 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM1:1; + unsigned char SEG9COM1:1; + unsigned char SEG10COM1:1; + unsigned char SEG11COM1:1; + unsigned char SEG12COM1:1; + unsigned char SEG13COM1:1; + unsigned char SEG14COM1:1; + unsigned char SEG15COM1:1; + }; + struct { + unsigned char S8C1:1; + unsigned char S9C1:1; + unsigned char S10C1:1; + unsigned char S11C1:1; + unsigned char S12C1:1; + unsigned char S13C1:1; + unsigned char S14C1:1; + unsigned char S15C1:1; + }; +} __LCDDATA4_bits_t; +extern volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits; + +#define SEG8COM1 LCDDATA4_bits.SEG8COM1 +#define S8C1 LCDDATA4_bits.S8C1 +#define SEG9COM1 LCDDATA4_bits.SEG9COM1 +#define S9C1 LCDDATA4_bits.S9C1 +#define SEG10COM1 LCDDATA4_bits.SEG10COM1 +#define S10C1 LCDDATA4_bits.S10C1 +#define SEG11COM1 LCDDATA4_bits.SEG11COM1 +#define S11C1 LCDDATA4_bits.S11C1 +#define SEG12COM1 LCDDATA4_bits.SEG12COM1 +#define S12C1 LCDDATA4_bits.S12C1 +#define SEG13COM1 LCDDATA4_bits.SEG13COM1 +#define S13C1 LCDDATA4_bits.S13C1 +#define SEG14COM1 LCDDATA4_bits.SEG14COM1 +#define S14C1 LCDDATA4_bits.S14C1 +#define SEG15COM1 LCDDATA4_bits.SEG15COM1 +#define S15C1 LCDDATA4_bits.S15C1 + +// ----- LCDDATA6 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM2:1; + unsigned char SEG1COM2:1; + unsigned char SEG2COM2:1; + unsigned char SEG3COM2:1; + unsigned char SEG4COM2:1; + unsigned char SEG5COM2:1; + unsigned char SEG6COM2:1; + unsigned char SEG7COM2:1; + }; + struct { + unsigned char S0C2:1; + unsigned char S1C2:1; + unsigned char S2C2:1; + unsigned char S3C2:1; + unsigned char S4C2:1; + unsigned char S5C2:1; + unsigned char S6C2:1; + unsigned char S7C2:1; + }; +} __LCDDATA6_bits_t; +extern volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits; + +#define SEG0COM2 LCDDATA6_bits.SEG0COM2 +#define S0C2 LCDDATA6_bits.S0C2 +#define SEG1COM2 LCDDATA6_bits.SEG1COM2 +#define S1C2 LCDDATA6_bits.S1C2 +#define SEG2COM2 LCDDATA6_bits.SEG2COM2 +#define S2C2 LCDDATA6_bits.S2C2 +#define SEG3COM2 LCDDATA6_bits.SEG3COM2 +#define S3C2 LCDDATA6_bits.S3C2 +#define SEG4COM2 LCDDATA6_bits.SEG4COM2 +#define S4C2 LCDDATA6_bits.S4C2 +#define SEG5COM2 LCDDATA6_bits.SEG5COM2 +#define S5C2 LCDDATA6_bits.S5C2 +#define SEG6COM2 LCDDATA6_bits.SEG6COM2 +#define S6C2 LCDDATA6_bits.S6C2 +#define SEG7COM2 LCDDATA6_bits.SEG7COM2 +#define S7C2 LCDDATA6_bits.S7C2 + +// ----- LCDDATA7 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM2:1; + unsigned char SEG9COM2:1; + unsigned char SEG10COM2:1; + unsigned char SEG11COM2:1; + unsigned char SEG12COM2:1; + unsigned char SEG13COM2:1; + unsigned char SEG14COM2:1; + unsigned char SEG15COM2:1; + }; + struct { + unsigned char S8C2:1; + unsigned char S9C2:1; + unsigned char S10C2:1; + unsigned char S11C2:1; + unsigned char S12C2:1; + unsigned char S13C2:1; + unsigned char S14C2:1; + unsigned char S15C2:1; + }; +} __LCDDATA7_bits_t; +extern volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits; + +#define SEG8COM2 LCDDATA7_bits.SEG8COM2 +#define S8C2 LCDDATA7_bits.S8C2 +#define SEG9COM2 LCDDATA7_bits.SEG9COM2 +#define S9C2 LCDDATA7_bits.S9C2 +#define SEG10COM2 LCDDATA7_bits.SEG10COM2 +#define S10C2 LCDDATA7_bits.S10C2 +#define SEG11COM2 LCDDATA7_bits.SEG11COM2 +#define S11C2 LCDDATA7_bits.S11C2 +#define SEG12COM2 LCDDATA7_bits.SEG12COM2 +#define S12C2 LCDDATA7_bits.S12C2 +#define SEG13COM2 LCDDATA7_bits.SEG13COM2 +#define S13C2 LCDDATA7_bits.S13C2 +#define SEG14COM2 LCDDATA7_bits.SEG14COM2 +#define S14C2 LCDDATA7_bits.S14C2 +#define SEG15COM2 LCDDATA7_bits.SEG15COM2 +#define S15C2 LCDDATA7_bits.S15C2 + +// ----- LCDDATA9 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM3:1; + unsigned char SEG1COM3:1; + unsigned char SEG2COM3:1; + unsigned char SEG3COM3:1; + unsigned char SEG4COM3:1; + unsigned char SEG5COM3:1; + unsigned char SEG6COM3:1; + unsigned char SEG7COM3:1; + }; + struct { + unsigned char S0C3:1; + unsigned char S1C3:1; + unsigned char S2C3:1; + unsigned char S3C3:1; + unsigned char S4C3:1; + unsigned char S5C3:1; + unsigned char S6C3:1; + unsigned char S7C3:1; + }; +} __LCDDATA9_bits_t; +extern volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits; + +#define SEG0COM3 LCDDATA9_bits.SEG0COM3 +#define S0C3 LCDDATA9_bits.S0C3 +#define SEG1COM3 LCDDATA9_bits.SEG1COM3 +#define S1C3 LCDDATA9_bits.S1C3 +#define SEG2COM3 LCDDATA9_bits.SEG2COM3 +#define S2C3 LCDDATA9_bits.S2C3 +#define SEG3COM3 LCDDATA9_bits.SEG3COM3 +#define S3C3 LCDDATA9_bits.S3C3 +#define SEG4COM3 LCDDATA9_bits.SEG4COM3 +#define S4C3 LCDDATA9_bits.S4C3 +#define SEG5COM3 LCDDATA9_bits.SEG5COM3 +#define S5C3 LCDDATA9_bits.S5C3 +#define SEG6COM3 LCDDATA9_bits.SEG6COM3 +#define S6C3 LCDDATA9_bits.S6C3 +#define SEG7COM3 LCDDATA9_bits.SEG7COM3 +#define S7C3 LCDDATA9_bits.S7C3 + +// ----- LCDPS bits -------------------- +typedef union { + struct { + unsigned char LP0:1; + unsigned char LP1:1; + unsigned char LP2:1; + unsigned char LP3:1; + unsigned char WA:1; + unsigned char LCDA:1; + unsigned char BIASMD:1; + unsigned char WFT:1; + }; +} __LCDPS_bits_t; +extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; + +#define LP0 LCDPS_bits.LP0 +#define LP1 LCDPS_bits.LP1 +#define LP2 LCDPS_bits.LP2 +#define LP3 LCDPS_bits.LP3 +#define WA LCDPS_bits.WA +#define LCDA LCDPS_bits.LCDA +#define BIASMD LCDPS_bits.BIASMD +#define WFT LCDPS_bits.WFT + +// ----- LCDSE0 bits -------------------- +typedef union { + struct { + unsigned char SE0:1; + unsigned char SE1:1; + unsigned char SE2:1; + unsigned char SE3:1; + unsigned char SE4:1; + unsigned char SE5:1; + unsigned char SE6:1; + unsigned char SE7:1; + }; + struct { + unsigned char SEGEN0:1; + unsigned char SEGEN1:1; + unsigned char SEGEN2:1; + unsigned char SEGEN3:1; + unsigned char SEGEN4:1; + unsigned char SEGEN5:1; + unsigned char SEGEN6:1; + unsigned char SEGEN7:1; + }; +} __LCDSE0_bits_t; +extern volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits; + +#define SE0 LCDSE0_bits.SE0 +#define SEGEN0 LCDSE0_bits.SEGEN0 +#define SE1 LCDSE0_bits.SE1 +#define SEGEN1 LCDSE0_bits.SEGEN1 +#define SE2 LCDSE0_bits.SE2 +#define SEGEN2 LCDSE0_bits.SEGEN2 +#define SE3 LCDSE0_bits.SE3 +#define SEGEN3 LCDSE0_bits.SEGEN3 +#define SE4 LCDSE0_bits.SE4 +#define SEGEN4 LCDSE0_bits.SEGEN4 +#define SE5 LCDSE0_bits.SE5 +#define SEGEN5 LCDSE0_bits.SEGEN5 +#define SE6 LCDSE0_bits.SE6 +#define SEGEN6 LCDSE0_bits.SEGEN6 +#define SE7 LCDSE0_bits.SE7 +#define SEGEN7 LCDSE0_bits.SEGEN7 + +// ----- LCDSE1 bits -------------------- +typedef union { + struct { + unsigned char SE8:1; + unsigned char SE9:1; + unsigned char SE10:1; + unsigned char SE11:1; + unsigned char SE12:1; + unsigned char SE13:1; + unsigned char SE14:1; + unsigned char SE15:1; + }; + struct { + unsigned char SEGEN8:1; + unsigned char SEGEN9:1; + unsigned char SEGEN10:1; + unsigned char SEGEN11:1; + unsigned char SEGEN12:1; + unsigned char SEGEN13:1; + unsigned char SEGEN14:1; + unsigned char SEGEN15:1; + }; +} __LCDSE1_bits_t; +extern volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits; + +#define SE8 LCDSE1_bits.SE8 +#define SEGEN8 LCDSE1_bits.SEGEN8 +#define SE9 LCDSE1_bits.SE9 +#define SEGEN9 LCDSE1_bits.SEGEN9 +#define SE10 LCDSE1_bits.SE10 +#define SEGEN10 LCDSE1_bits.SEGEN10 +#define SE11 LCDSE1_bits.SE11 +#define SEGEN11 LCDSE1_bits.SEGEN11 +#define SE12 LCDSE1_bits.SE12 +#define SEGEN12 LCDSE1_bits.SEGEN12 +#define SE13 LCDSE1_bits.SE13 +#define SEGEN13 LCDSE1_bits.SEGEN13 +#define SE14 LCDSE1_bits.SE14 +#define SEGEN14 LCDSE1_bits.SEGEN14 +#define SE15 LCDSE1_bits.SE15 +#define SEGEN15 LCDSE1_bits.SEGEN15 + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LVDL0:1; + unsigned char LVDL1:1; + unsigned char LVDL2:1; + unsigned char :1; + unsigned char LVDEN:1; + unsigned char IRVST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LVDL0 LVDCON_bits.LVDL0 +#define LVDL1 LVDCON_bits.LVDL1 +#define LVDL2 LVDCON_bits.LVDL2 +#define LVDEN LVDCON_bits.LVDEN +#define IRVST LVDCON_bits.IRVST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBOREN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define SBOREN PCON_bits.SBOREN + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define EEIE PIE1_bits.EEIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char LVDIE:1; + unsigned char :1; + unsigned char LCDIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define LVDIE PIE2_bits.LVDIE +#define LCDIE PIE2_bits.LCDIE +#define C1IE PIE2_bits.C1IE +#define C2IE PIE2_bits.C2IE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define EEIF PIR1_bits.EEIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char LVDIF:1; + unsigned char :1; + unsigned char LCDIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define LVDIF PIR2_bits.LVDIF +#define LCDIF PIR2_bits.LCDIF +#define C1IF PIR2_bits.C1IF +#define C2IF PIR2_bits.C2IF +#define OSFIF PIR2_bits.OSFIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char T1GE:1; + unsigned char T1GINV:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define T1GE T1CON_bits.T1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char :1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VREN VRCON_bits.VREN + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char SWDTE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define SWDTE WDTCON_bits.SWDTE +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +// ----- WPU bits -------------------- +typedef union { + struct { + unsigned char WPU0:1; + unsigned char WPU1:1; + unsigned char WPU2:1; + unsigned char WPU3:1; + unsigned char WPU4:1; + unsigned char WPU5:1; + unsigned char WPU6:1; + unsigned char WPU7:1; + }; +} __WPU_bits_t; +extern volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits; + +#define WPU0 WPU_bits.WPU0 +#define WPU1 WPU_bits.WPU1 +#define WPU2 WPU_bits.WPU2 +#define WPU3 WPU_bits.WPU3 +#define WPU4 WPU_bits.WPU4 +#define WPU5 WPU_bits.WPU5 +#define WPU6 WPU_bits.WPU6 +#define WPU7 WPU_bits.WPU7 + +// ----- WPUB bits -------------------- +typedef union { + struct { + unsigned char WPUB0:1; + unsigned char WPUB1:1; + unsigned char WPUB2:1; + unsigned char WPUB3:1; + unsigned char WPUB4:1; + unsigned char WPUB5:1; + unsigned char WPUB6:1; + unsigned char WPUB7:1; + }; +} __WPUB_bits_t; +extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + +#define WPUB0 WPUB_bits.WPUB0 +#define WPUB1 WPUB_bits.WPUB1 +#define WPUB2 WPUB_bits.WPUB2 +#define WPUB3 WPUB_bits.WPUB3 +#define WPUB4 WPUB_bits.WPUB4 +#define WPUB5 WPUB_bits.WPUB5 +#define WPUB6 WPUB_bits.WPUB6 +#define WPUB7 WPUB_bits.WPUB7 + +#endif diff --git a/device/include/pic/pic16f914.h b/device/include/pic/pic16f914.h new file mode 100644 index 00000000..d031173e --- /dev/null +++ b/device/include/pic/pic16f914.h @@ -0,0 +1,2132 @@ +// +// Register Declarations for Microchip 16F914 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F914_H +#define P16F914_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define ANSEL_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPUB_ADDR 0x0095 +#define WPU_ADDR 0x0095 +#define IOCB_ADDR 0x0096 +#define IOC_ADDR 0x0096 +#define CMCON1_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define CMCON0_ADDR 0x009C +#define VRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define WDTCON_ADDR 0x0105 +#define LCDCON_ADDR 0x0107 +#define LCDPS_ADDR 0x0108 +#define LVDCON_ADDR 0x0109 +#define EEDATL_ADDR 0x010C +#define EEADRL_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define LCDDATA0_ADDR 0x0110 +#define LCDDATA1_ADDR 0x0111 +#define LCDDATA2_ADDR 0x0112 +#define LCDDATA3_ADDR 0x0113 +#define LCDDATA4_ADDR 0x0114 +#define LCDDATA5_ADDR 0x0115 +#define LCDDATA6_ADDR 0x0116 +#define LCDDATA7_ADDR 0x0117 +#define LCDDATA8_ADDR 0x0118 +#define LCDDATA9_ADDR 0x0119 +#define LCDDATA10_ADDR 0x011A +#define LCDDATA11_ADDR 0x011B +#define LCDSE0_ADDR 0x011C +#define LCDSE1_ADDR 0x011D +#define LCDSE2_ADDR 0x011E +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0 +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON +#pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap EEDATL_ADDR EEDATL_ADDR SFR 0x000 // EEDATL +#pragma memmap EEADRL_ADDR EEADRL_ADDR SFR 0x000 // EEADRL +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap LCDDATA0_ADDR LCDDATA0_ADDR SFR 0x000 // LCDDATA0 +#pragma memmap LCDDATA1_ADDR LCDDATA1_ADDR SFR 0x000 // LCDDATA1 +#pragma memmap LCDDATA2_ADDR LCDDATA2_ADDR SFR 0x000 // LCDDATA2 +#pragma memmap LCDDATA3_ADDR LCDDATA3_ADDR SFR 0x000 // LCDDATA3 +#pragma memmap LCDDATA4_ADDR LCDDATA4_ADDR SFR 0x000 // LCDDATA4 +#pragma memmap LCDDATA5_ADDR LCDDATA5_ADDR SFR 0x000 // LCDDATA5 +#pragma memmap LCDDATA6_ADDR LCDDATA6_ADDR SFR 0x000 // LCDDATA6 +#pragma memmap LCDDATA7_ADDR LCDDATA7_ADDR SFR 0x000 // LCDDATA7 +#pragma memmap LCDDATA8_ADDR LCDDATA8_ADDR SFR 0x000 // LCDDATA8 +#pragma memmap LCDDATA9_ADDR LCDDATA9_ADDR SFR 0x000 // LCDDATA9 +#pragma memmap LCDDATA10_ADDR LCDDATA10_ADDR SFR 0x000 // LCDDATA10 +#pragma memmap LCDDATA11_ADDR LCDDATA11_ADDR SFR 0x000 // LCDDATA11 +#pragma memmap LCDSE0_ADDR LCDSE0_ADDR SFR 0x000 // LCDSE0 +#pragma memmap LCDSE1_ADDR LCDSE1_ADDR SFR 0x000 // LCDSE1 +#pragma memmap LCDSE2_ADDR LCDSE2_ADDR SFR 0x000 // LCDSE2 +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F914.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F914 microcontroller. +// These names are taken to match the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F914 +// 2. LIST directive in the source file +// LIST P=PIC16F914 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.00 06/11/04 Initial Release +//1.01 08/16/04 Added EECON2 + + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F914 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (IOCB_ADDR) IOCB; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (CMCON1_ADDR) CMCON1; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (CMCON0_ADDR) CMCON0; +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (LCDCON_ADDR) LCDCON; +extern sfr __at (LCDPS_ADDR) LCDPS; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (EEDATL_ADDR) EEDATL; +extern sfr __at (EEADRL_ADDR) EEADRL; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; +extern sfr __at (LCDDATA0_ADDR) LCDDATA0; +extern sfr __at (LCDDATA1_ADDR) LCDDATA1; +extern sfr __at (LCDDATA2_ADDR) LCDDATA2; +extern sfr __at (LCDDATA3_ADDR) LCDDATA3; +extern sfr __at (LCDDATA4_ADDR) LCDDATA4; +extern sfr __at (LCDDATA5_ADDR) LCDDATA5; +extern sfr __at (LCDDATA6_ADDR) LCDDATA6; +extern sfr __at (LCDDATA7_ADDR) LCDDATA7; +extern sfr __at (LCDDATA8_ADDR) LCDDATA8; +extern sfr __at (LCDDATA9_ADDR) LCDDATA9; +extern sfr __at (LCDDATA10_ADDR) LCDDATA10; +extern sfr __at (LCDDATA11_ADDR) LCDDATA11; +extern sfr __at (LCDSE0_ADDR) LCDSE0; +extern sfr __at (LCDSE1_ADDR) LCDSE1; +extern sfr __at (LCDSE2_ADDR) LCDSE2; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits ------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + + +//----- ANSEL Bits --------------------------------------------------------- + + + +//----- SSPSTAT Bits ------------------------------------------------------- + + + +//----- WPUB Bits ------------------------------------------------------- + + +//----- WPU Bits ------------------------------------------------------- + + + +//----- IOCB Bits ------------------------------------------------------- + + + +//----- IOC Bits ------------------------------------------------------- + + + +//----- CMCON1 Bits -------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- CMCON0 Bits --------------------------------------------------------- + + +//----- VRCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- LCDCON Bits -------------------------------------------------------- + + +//----- LCDPS Bits --------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- LCDDATA0 Bits ------------------------------------------------------- + + + +//----- LCDDATA1 Bits ------------------------------------------------------- + + + +//----- LCDDATA2 Bits ------------------------------------------------------- + + + +//----- LCDDATA3 Bits ------------------------------------------------------- + + + +//----- LCDDATA4 Bits ------------------------------------------------------- + + + +//----- LCDDATA5 Bits ------------------------------------------------------- + + + +//----- LCDDATA6 Bits ------------------------------------------------------- + + + +//----- LCDDATA7 Bits ------------------------------------------------------- + + + +//----- LCDDATA8 Bits ------------------------------------------------------- + + + +//----- LCDDATA9 Bits ------------------------------------------------------- + + + +//----- LCDDATA10 Bits ------------------------------------------------------- + + + +//----- LCDDATA11 Bits ------------------------------------------------------- + + + +//----- LCDSE0 Bits -------------------------------------------------------- + + + +//----- LCDSE1 Bits -------------------------------------------------------- + + + +//----- LCDSE2 Bits -------------------------------------------------------- + + + +//----- EECON1 Bits -------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'9A'-H'9B' +// __BADRAM H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CONFIG 0x2007 + +//Configuration Byte 1 Options +#define _DEBUG_ON 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_ON 0x3FEF +#define _PWRTE_OFF 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char NOT_DONE:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define VCFG0 ADCON0_bits.VCFG0 +#define VCFG1 ADCON0_bits.VCFG1 +#define ADFM ADCON0_bits.ADFM + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + unsigned char ADCS2:1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define ADCS0 ADCON1_bits.ADCS0 +#define ADCS1 ADCON1_bits.ADCS1 +#define ADCS2 ADCON1_bits.ADCS2 + +// ----- ANSEL bits -------------------- +typedef union { + struct { + unsigned char AN0:1; + unsigned char AN1:1; + unsigned char AN2:1; + unsigned char AN3:1; + unsigned char AN4:1; + unsigned char AN5:1; + unsigned char AN6:1; + unsigned char AN7:1; + }; +} __ANSEL_bits_t; +extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits; + +#define AN0 ANSEL_bits.AN0 +#define AN1 ANSEL_bits.AN1 +#define AN2 ANSEL_bits.AN2 +#define AN3 ANSEL_bits.AN3 +#define AN4 ANSEL_bits.AN4 +#define AN5 ANSEL_bits.AN5 +#define AN6 ANSEL_bits.AN6 +#define AN7 ANSEL_bits.AN7 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- CMCON0 bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON0_bits_t; +extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; + +#define CM0 CMCON0_bits.CM0 +#define CM1 CMCON0_bits.CM1 +#define CM2 CMCON0_bits.CM2 +#define CIS CMCON0_bits.CIS +#define C1INV CMCON0_bits.C1INV +#define C2INV CMCON0_bits.C2INV +#define C1OUT CMCON0_bits.C1OUT +#define C2OUT CMCON0_bits.C2OUT + +// ----- CMCON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __CMCON1_bits_t; +extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; + +#define C2SYNC CMCON1_bits.C2SYNC +#define T1GSS CMCON1_bits.T1GSS + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; + struct { + unsigned char EERD:1; + unsigned char EEWR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define EERD EECON1_bits.EERD +#define WR EECON1_bits.WR +#define EEWR EECON1_bits.EEWR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char TMR0IF:1; + unsigned char :1; + unsigned char :1; + unsigned char TMR0IE:1; + unsigned char :1; + unsigned char :1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- IOC bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOC4:1; + unsigned char IOC5:1; + unsigned char IOC6:1; + unsigned char IOC7:1; + }; +} __IOC_bits_t; +extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits; + +#define IOC4 IOC_bits.IOC4 +#define IOC5 IOC_bits.IOC5 +#define IOC6 IOC_bits.IOC6 +#define IOC7 IOC_bits.IOC7 + +// ----- IOCB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOCB4:1; + unsigned char IOCB5:1; + unsigned char IOCB6:1; + unsigned char IOCB7:1; + }; +} __IOCB_bits_t; +extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits; + +#define IOCB4 IOCB_bits.IOCB4 +#define IOCB5 IOCB_bits.IOCB5 +#define IOCB6 IOCB_bits.IOCB6 +#define IOCB7 IOCB_bits.IOCB7 + +// ----- LCDCON bits -------------------- +typedef union { + struct { + unsigned char LMUX0:1; + unsigned char LMUX1:1; + unsigned char CS0:1; + unsigned char CS1:1; + unsigned char VLCDEN:1; + unsigned char WERR:1; + unsigned char SLPEN:1; + unsigned char LCDEN:1; + }; +} __LCDCON_bits_t; +extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; + +#define LMUX0 LCDCON_bits.LMUX0 +#define LMUX1 LCDCON_bits.LMUX1 +#define CS0 LCDCON_bits.CS0 +#define CS1 LCDCON_bits.CS1 +#define VLCDEN LCDCON_bits.VLCDEN +#define WERR LCDCON_bits.WERR +#define SLPEN LCDCON_bits.SLPEN +#define LCDEN LCDCON_bits.LCDEN + +// ----- LCDDATA0 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM0:1; + unsigned char SEG1COM0:1; + unsigned char SEG2COM0:1; + unsigned char SEG3COM0:1; + unsigned char SEG4COM0:1; + unsigned char SEG5COM0:1; + unsigned char SEG6COM0:1; + unsigned char SEG7COM0:1; + }; + struct { + unsigned char S0C0:1; + unsigned char S1C0:1; + unsigned char S2C0:1; + unsigned char S3C0:1; + unsigned char S4C0:1; + unsigned char S5C0:1; + unsigned char S6C0:1; + unsigned char S7C0:1; + }; +} __LCDDATA0_bits_t; +extern volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits; + +#define SEG0COM0 LCDDATA0_bits.SEG0COM0 +#define S0C0 LCDDATA0_bits.S0C0 +#define SEG1COM0 LCDDATA0_bits.SEG1COM0 +#define S1C0 LCDDATA0_bits.S1C0 +#define SEG2COM0 LCDDATA0_bits.SEG2COM0 +#define S2C0 LCDDATA0_bits.S2C0 +#define SEG3COM0 LCDDATA0_bits.SEG3COM0 +#define S3C0 LCDDATA0_bits.S3C0 +#define SEG4COM0 LCDDATA0_bits.SEG4COM0 +#define S4C0 LCDDATA0_bits.S4C0 +#define SEG5COM0 LCDDATA0_bits.SEG5COM0 +#define S5C0 LCDDATA0_bits.S5C0 +#define SEG6COM0 LCDDATA0_bits.SEG6COM0 +#define S6C0 LCDDATA0_bits.S6C0 +#define SEG7COM0 LCDDATA0_bits.SEG7COM0 +#define S7C0 LCDDATA0_bits.S7C0 + +// ----- LCDDATA1 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM0:1; + unsigned char SEG9COM0:1; + unsigned char SEG10COM0:1; + unsigned char SEG11COM0:1; + unsigned char SEG12COM0:1; + unsigned char SEG13COM0:1; + unsigned char SEG14COM0:1; + unsigned char SEG15COM0:1; + }; + struct { + unsigned char S8C0:1; + unsigned char S9C0:1; + unsigned char S10C0:1; + unsigned char S11C0:1; + unsigned char S12C0:1; + unsigned char S13C0:1; + unsigned char S14C0:1; + unsigned char S15C0:1; + }; +} __LCDDATA1_bits_t; +extern volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits; + +#define SEG8COM0 LCDDATA1_bits.SEG8COM0 +#define S8C0 LCDDATA1_bits.S8C0 +#define SEG9COM0 LCDDATA1_bits.SEG9COM0 +#define S9C0 LCDDATA1_bits.S9C0 +#define SEG10COM0 LCDDATA1_bits.SEG10COM0 +#define S10C0 LCDDATA1_bits.S10C0 +#define SEG11COM0 LCDDATA1_bits.SEG11COM0 +#define S11C0 LCDDATA1_bits.S11C0 +#define SEG12COM0 LCDDATA1_bits.SEG12COM0 +#define S12C0 LCDDATA1_bits.S12C0 +#define SEG13COM0 LCDDATA1_bits.SEG13COM0 +#define S13C0 LCDDATA1_bits.S13C0 +#define SEG14COM0 LCDDATA1_bits.SEG14COM0 +#define S14C0 LCDDATA1_bits.S14C0 +#define SEG15COM0 LCDDATA1_bits.SEG15COM0 +#define S15C0 LCDDATA1_bits.S15C0 + +// ----- LCDDATA10 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM3:1; + unsigned char SEG9COM3:1; + unsigned char SEG10COM3:1; + unsigned char SEG11COM3:1; + unsigned char SEG12COM3:1; + unsigned char SEG13COM3:1; + unsigned char SEG14COM3:1; + unsigned char SEG15COM3:1; + }; + struct { + unsigned char S8C3:1; + unsigned char S9C3:1; + unsigned char S10C3:1; + unsigned char S11C3:1; + unsigned char S12C3:1; + unsigned char S13C3:1; + unsigned char S14C3:1; + unsigned char S15C3:1; + }; +} __LCDDATA10_bits_t; +extern volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits; + +#define SEG8COM3 LCDDATA10_bits.SEG8COM3 +#define S8C3 LCDDATA10_bits.S8C3 +#define SEG9COM3 LCDDATA10_bits.SEG9COM3 +#define S9C3 LCDDATA10_bits.S9C3 +#define SEG10COM3 LCDDATA10_bits.SEG10COM3 +#define S10C3 LCDDATA10_bits.S10C3 +#define SEG11COM3 LCDDATA10_bits.SEG11COM3 +#define S11C3 LCDDATA10_bits.S11C3 +#define SEG12COM3 LCDDATA10_bits.SEG12COM3 +#define S12C3 LCDDATA10_bits.S12C3 +#define SEG13COM3 LCDDATA10_bits.SEG13COM3 +#define S13C3 LCDDATA10_bits.S13C3 +#define SEG14COM3 LCDDATA10_bits.SEG14COM3 +#define S14C3 LCDDATA10_bits.S14C3 +#define SEG15COM3 LCDDATA10_bits.SEG15COM3 +#define S15C3 LCDDATA10_bits.S15C3 + +// ----- LCDDATA11 bits -------------------- +typedef union { + struct { + unsigned char SEG16COM3:1; + unsigned char SEG17COM3:1; + unsigned char SEG18COM3:1; + unsigned char SEG19COM3:1; + unsigned char SEG20COM3:1; + unsigned char SEG21COM3:1; + unsigned char SEG22COM3:1; + unsigned char SEG23COM3:1; + }; + struct { + unsigned char S16C3:1; + unsigned char S17C3:1; + unsigned char S18C3:1; + unsigned char S19C3:1; + unsigned char S20C3:1; + unsigned char S21C3:1; + unsigned char S22C3:1; + unsigned char S23C3:1; + }; +} __LCDDATA11_bits_t; +extern volatile __LCDDATA11_bits_t __at(LCDDATA11_ADDR) LCDDATA11_bits; + +#define SEG16COM3 LCDDATA11_bits.SEG16COM3 +#define S16C3 LCDDATA11_bits.S16C3 +#define SEG17COM3 LCDDATA11_bits.SEG17COM3 +#define S17C3 LCDDATA11_bits.S17C3 +#define SEG18COM3 LCDDATA11_bits.SEG18COM3 +#define S18C3 LCDDATA11_bits.S18C3 +#define SEG19COM3 LCDDATA11_bits.SEG19COM3 +#define S19C3 LCDDATA11_bits.S19C3 +#define SEG20COM3 LCDDATA11_bits.SEG20COM3 +#define S20C3 LCDDATA11_bits.S20C3 +#define SEG21COM3 LCDDATA11_bits.SEG21COM3 +#define S21C3 LCDDATA11_bits.S21C3 +#define SEG22COM3 LCDDATA11_bits.SEG22COM3 +#define S22C3 LCDDATA11_bits.S22C3 +#define SEG23COM3 LCDDATA11_bits.SEG23COM3 +#define S23C3 LCDDATA11_bits.S23C3 + +// ----- LCDDATA2 bits -------------------- +typedef union { + struct { + unsigned char SEG16COM0:1; + unsigned char SEG17COM0:1; + unsigned char SEG18COM0:1; + unsigned char SEG19COM0:1; + unsigned char SEG20COM0:1; + unsigned char SEG21COM0:1; + unsigned char SEG22COM0:1; + unsigned char SEG23COM0:1; + }; + struct { + unsigned char S16C0:1; + unsigned char S17C0:1; + unsigned char S18C0:1; + unsigned char S19C0:1; + unsigned char S20C0:1; + unsigned char S21C0:1; + unsigned char S22C0:1; + unsigned char S23C0:1; + }; +} __LCDDATA2_bits_t; +extern volatile __LCDDATA2_bits_t __at(LCDDATA2_ADDR) LCDDATA2_bits; + +#define SEG16COM0 LCDDATA2_bits.SEG16COM0 +#define S16C0 LCDDATA2_bits.S16C0 +#define SEG17COM0 LCDDATA2_bits.SEG17COM0 +#define S17C0 LCDDATA2_bits.S17C0 +#define SEG18COM0 LCDDATA2_bits.SEG18COM0 +#define S18C0 LCDDATA2_bits.S18C0 +#define SEG19COM0 LCDDATA2_bits.SEG19COM0 +#define S19C0 LCDDATA2_bits.S19C0 +#define SEG20COM0 LCDDATA2_bits.SEG20COM0 +#define S20C0 LCDDATA2_bits.S20C0 +#define SEG21COM0 LCDDATA2_bits.SEG21COM0 +#define S21C0 LCDDATA2_bits.S21C0 +#define SEG22COM0 LCDDATA2_bits.SEG22COM0 +#define S22C0 LCDDATA2_bits.S22C0 +#define SEG23COM0 LCDDATA2_bits.SEG23COM0 +#define S23C0 LCDDATA2_bits.S23C0 + +// ----- LCDDATA3 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM1:1; + unsigned char SEG1COM1:1; + unsigned char SEG2COM1:1; + unsigned char SEG3COM1:1; + unsigned char SEG4COM1:1; + unsigned char SEG5COM1:1; + unsigned char SEG6COM1:1; + unsigned char SEG7COM1:1; + }; + struct { + unsigned char S0C1:1; + unsigned char S1C1:1; + unsigned char S2C1:1; + unsigned char S3C1:1; + unsigned char S4C1:1; + unsigned char S5C1:1; + unsigned char S6C1:1; + unsigned char S7C1:1; + }; +} __LCDDATA3_bits_t; +extern volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits; + +#define SEG0COM1 LCDDATA3_bits.SEG0COM1 +#define S0C1 LCDDATA3_bits.S0C1 +#define SEG1COM1 LCDDATA3_bits.SEG1COM1 +#define S1C1 LCDDATA3_bits.S1C1 +#define SEG2COM1 LCDDATA3_bits.SEG2COM1 +#define S2C1 LCDDATA3_bits.S2C1 +#define SEG3COM1 LCDDATA3_bits.SEG3COM1 +#define S3C1 LCDDATA3_bits.S3C1 +#define SEG4COM1 LCDDATA3_bits.SEG4COM1 +#define S4C1 LCDDATA3_bits.S4C1 +#define SEG5COM1 LCDDATA3_bits.SEG5COM1 +#define S5C1 LCDDATA3_bits.S5C1 +#define SEG6COM1 LCDDATA3_bits.SEG6COM1 +#define S6C1 LCDDATA3_bits.S6C1 +#define SEG7COM1 LCDDATA3_bits.SEG7COM1 +#define S7C1 LCDDATA3_bits.S7C1 + +// ----- LCDDATA4 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM1:1; + unsigned char SEG9COM1:1; + unsigned char SEG10COM1:1; + unsigned char SEG11COM1:1; + unsigned char SEG12COM1:1; + unsigned char SEG13COM1:1; + unsigned char SEG14COM1:1; + unsigned char SEG15COM1:1; + }; + struct { + unsigned char S8C1:1; + unsigned char S9C1:1; + unsigned char S10C1:1; + unsigned char S11C1:1; + unsigned char S12C1:1; + unsigned char S13C1:1; + unsigned char S14C1:1; + unsigned char S15C1:1; + }; +} __LCDDATA4_bits_t; +extern volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits; + +#define SEG8COM1 LCDDATA4_bits.SEG8COM1 +#define S8C1 LCDDATA4_bits.S8C1 +#define SEG9COM1 LCDDATA4_bits.SEG9COM1 +#define S9C1 LCDDATA4_bits.S9C1 +#define SEG10COM1 LCDDATA4_bits.SEG10COM1 +#define S10C1 LCDDATA4_bits.S10C1 +#define SEG11COM1 LCDDATA4_bits.SEG11COM1 +#define S11C1 LCDDATA4_bits.S11C1 +#define SEG12COM1 LCDDATA4_bits.SEG12COM1 +#define S12C1 LCDDATA4_bits.S12C1 +#define SEG13COM1 LCDDATA4_bits.SEG13COM1 +#define S13C1 LCDDATA4_bits.S13C1 +#define SEG14COM1 LCDDATA4_bits.SEG14COM1 +#define S14C1 LCDDATA4_bits.S14C1 +#define SEG15COM1 LCDDATA4_bits.SEG15COM1 +#define S15C1 LCDDATA4_bits.S15C1 + +// ----- LCDDATA5 bits -------------------- +typedef union { + struct { + unsigned char SEG16COM1:1; + unsigned char SEG17COM1:1; + unsigned char SEG18COM1:1; + unsigned char SEG19COM1:1; + unsigned char SEG20COM1:1; + unsigned char SEG21COM1:1; + unsigned char SEG22COM1:1; + unsigned char SEG23COM1:1; + }; + struct { + unsigned char S16C1:1; + unsigned char S17C1:1; + unsigned char S18C1:1; + unsigned char S19C1:1; + unsigned char S20C1:1; + unsigned char S21C1:1; + unsigned char S22C1:1; + unsigned char S23C1:1; + }; +} __LCDDATA5_bits_t; +extern volatile __LCDDATA5_bits_t __at(LCDDATA5_ADDR) LCDDATA5_bits; + +#define SEG16COM1 LCDDATA5_bits.SEG16COM1 +#define S16C1 LCDDATA5_bits.S16C1 +#define SEG17COM1 LCDDATA5_bits.SEG17COM1 +#define S17C1 LCDDATA5_bits.S17C1 +#define SEG18COM1 LCDDATA5_bits.SEG18COM1 +#define S18C1 LCDDATA5_bits.S18C1 +#define SEG19COM1 LCDDATA5_bits.SEG19COM1 +#define S19C1 LCDDATA5_bits.S19C1 +#define SEG20COM1 LCDDATA5_bits.SEG20COM1 +#define S20C1 LCDDATA5_bits.S20C1 +#define SEG21COM1 LCDDATA5_bits.SEG21COM1 +#define S21C1 LCDDATA5_bits.S21C1 +#define SEG22COM1 LCDDATA5_bits.SEG22COM1 +#define S22C1 LCDDATA5_bits.S22C1 +#define SEG23COM1 LCDDATA5_bits.SEG23COM1 +#define S23C1 LCDDATA5_bits.S23C1 + +// ----- LCDDATA6 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM2:1; + unsigned char SEG1COM2:1; + unsigned char SEG2COM2:1; + unsigned char SEG3COM2:1; + unsigned char SEG4COM2:1; + unsigned char SEG5COM2:1; + unsigned char SEG6COM2:1; + unsigned char SEG7COM2:1; + }; + struct { + unsigned char S0C2:1; + unsigned char S1C2:1; + unsigned char S2C2:1; + unsigned char S3C2:1; + unsigned char S4C2:1; + unsigned char S5C2:1; + unsigned char S6C2:1; + unsigned char S7C2:1; + }; +} __LCDDATA6_bits_t; +extern volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits; + +#define SEG0COM2 LCDDATA6_bits.SEG0COM2 +#define S0C2 LCDDATA6_bits.S0C2 +#define SEG1COM2 LCDDATA6_bits.SEG1COM2 +#define S1C2 LCDDATA6_bits.S1C2 +#define SEG2COM2 LCDDATA6_bits.SEG2COM2 +#define S2C2 LCDDATA6_bits.S2C2 +#define SEG3COM2 LCDDATA6_bits.SEG3COM2 +#define S3C2 LCDDATA6_bits.S3C2 +#define SEG4COM2 LCDDATA6_bits.SEG4COM2 +#define S4C2 LCDDATA6_bits.S4C2 +#define SEG5COM2 LCDDATA6_bits.SEG5COM2 +#define S5C2 LCDDATA6_bits.S5C2 +#define SEG6COM2 LCDDATA6_bits.SEG6COM2 +#define S6C2 LCDDATA6_bits.S6C2 +#define SEG7COM2 LCDDATA6_bits.SEG7COM2 +#define S7C2 LCDDATA6_bits.S7C2 + +// ----- LCDDATA7 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM2:1; + unsigned char SEG9COM2:1; + unsigned char SEG10COM2:1; + unsigned char SEG11COM2:1; + unsigned char SEG12COM2:1; + unsigned char SEG13COM2:1; + unsigned char SEG14COM2:1; + unsigned char SEG15COM2:1; + }; + struct { + unsigned char S8C2:1; + unsigned char S9C2:1; + unsigned char S10C2:1; + unsigned char S11C2:1; + unsigned char S12C2:1; + unsigned char S13C2:1; + unsigned char S14C2:1; + unsigned char S15C2:1; + }; +} __LCDDATA7_bits_t; +extern volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits; + +#define SEG8COM2 LCDDATA7_bits.SEG8COM2 +#define S8C2 LCDDATA7_bits.S8C2 +#define SEG9COM2 LCDDATA7_bits.SEG9COM2 +#define S9C2 LCDDATA7_bits.S9C2 +#define SEG10COM2 LCDDATA7_bits.SEG10COM2 +#define S10C2 LCDDATA7_bits.S10C2 +#define SEG11COM2 LCDDATA7_bits.SEG11COM2 +#define S11C2 LCDDATA7_bits.S11C2 +#define SEG12COM2 LCDDATA7_bits.SEG12COM2 +#define S12C2 LCDDATA7_bits.S12C2 +#define SEG13COM2 LCDDATA7_bits.SEG13COM2 +#define S13C2 LCDDATA7_bits.S13C2 +#define SEG14COM2 LCDDATA7_bits.SEG14COM2 +#define S14C2 LCDDATA7_bits.S14C2 +#define SEG15COM2 LCDDATA7_bits.SEG15COM2 +#define S15C2 LCDDATA7_bits.S15C2 + +// ----- LCDDATA8 bits -------------------- +typedef union { + struct { + unsigned char SEG16COM2:1; + unsigned char SEG17COM2:1; + unsigned char SEG18COM2:1; + unsigned char SEG19COM2:1; + unsigned char SEG20COM2:1; + unsigned char SEG21COM2:1; + unsigned char SEG22COM2:1; + unsigned char SEG23COM2:1; + }; + struct { + unsigned char S16C2:1; + unsigned char S17C2:1; + unsigned char S18C2:1; + unsigned char S19C2:1; + unsigned char S20C2:1; + unsigned char S21C2:1; + unsigned char S22C2:1; + unsigned char S23C2:1; + }; +} __LCDDATA8_bits_t; +extern volatile __LCDDATA8_bits_t __at(LCDDATA8_ADDR) LCDDATA8_bits; + +#define SEG16COM2 LCDDATA8_bits.SEG16COM2 +#define S16C2 LCDDATA8_bits.S16C2 +#define SEG17COM2 LCDDATA8_bits.SEG17COM2 +#define S17C2 LCDDATA8_bits.S17C2 +#define SEG18COM2 LCDDATA8_bits.SEG18COM2 +#define S18C2 LCDDATA8_bits.S18C2 +#define SEG19COM2 LCDDATA8_bits.SEG19COM2 +#define S19C2 LCDDATA8_bits.S19C2 +#define SEG20COM2 LCDDATA8_bits.SEG20COM2 +#define S20C2 LCDDATA8_bits.S20C2 +#define SEG21COM2 LCDDATA8_bits.SEG21COM2 +#define S21C2 LCDDATA8_bits.S21C2 +#define SEG22COM2 LCDDATA8_bits.SEG22COM2 +#define S22C2 LCDDATA8_bits.S22C2 +#define SEG23COM2 LCDDATA8_bits.SEG23COM2 +#define S23C2 LCDDATA8_bits.S23C2 + +// ----- LCDDATA9 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM3:1; + unsigned char SEG1COM3:1; + unsigned char SEG2COM3:1; + unsigned char SEG3COM3:1; + unsigned char SEG4COM3:1; + unsigned char SEG5COM3:1; + unsigned char SEG6COM3:1; + unsigned char SEG7COM3:1; + }; + struct { + unsigned char S0C3:1; + unsigned char S1C3:1; + unsigned char S2C3:1; + unsigned char S3C3:1; + unsigned char S4C3:1; + unsigned char S5C3:1; + unsigned char S6C3:1; + unsigned char S7C3:1; + }; +} __LCDDATA9_bits_t; +extern volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits; + +#define SEG0COM3 LCDDATA9_bits.SEG0COM3 +#define S0C3 LCDDATA9_bits.S0C3 +#define SEG1COM3 LCDDATA9_bits.SEG1COM3 +#define S1C3 LCDDATA9_bits.S1C3 +#define SEG2COM3 LCDDATA9_bits.SEG2COM3 +#define S2C3 LCDDATA9_bits.S2C3 +#define SEG3COM3 LCDDATA9_bits.SEG3COM3 +#define S3C3 LCDDATA9_bits.S3C3 +#define SEG4COM3 LCDDATA9_bits.SEG4COM3 +#define S4C3 LCDDATA9_bits.S4C3 +#define SEG5COM3 LCDDATA9_bits.SEG5COM3 +#define S5C3 LCDDATA9_bits.S5C3 +#define SEG6COM3 LCDDATA9_bits.SEG6COM3 +#define S6C3 LCDDATA9_bits.S6C3 +#define SEG7COM3 LCDDATA9_bits.SEG7COM3 +#define S7C3 LCDDATA9_bits.S7C3 + +// ----- LCDPS bits -------------------- +typedef union { + struct { + unsigned char LP0:1; + unsigned char LP1:1; + unsigned char LP2:1; + unsigned char LP3:1; + unsigned char WA:1; + unsigned char LCDA:1; + unsigned char BIASMD:1; + unsigned char WFT:1; + }; +} __LCDPS_bits_t; +extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; + +#define LP0 LCDPS_bits.LP0 +#define LP1 LCDPS_bits.LP1 +#define LP2 LCDPS_bits.LP2 +#define LP3 LCDPS_bits.LP3 +#define WA LCDPS_bits.WA +#define LCDA LCDPS_bits.LCDA +#define BIASMD LCDPS_bits.BIASMD +#define WFT LCDPS_bits.WFT + +// ----- LCDSE0 bits -------------------- +typedef union { + struct { + unsigned char SE0:1; + unsigned char SE1:1; + unsigned char SE2:1; + unsigned char SE3:1; + unsigned char SE4:1; + unsigned char SE5:1; + unsigned char SE6:1; + unsigned char SE7:1; + }; + struct { + unsigned char SEGEN0:1; + unsigned char SEGEN1:1; + unsigned char SEGEN2:1; + unsigned char SEGEN3:1; + unsigned char SEGEN4:1; + unsigned char SEGEN5:1; + unsigned char SEGEN6:1; + unsigned char SEGEN7:1; + }; +} __LCDSE0_bits_t; +extern volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits; + +#define SE0 LCDSE0_bits.SE0 +#define SEGEN0 LCDSE0_bits.SEGEN0 +#define SE1 LCDSE0_bits.SE1 +#define SEGEN1 LCDSE0_bits.SEGEN1 +#define SE2 LCDSE0_bits.SE2 +#define SEGEN2 LCDSE0_bits.SEGEN2 +#define SE3 LCDSE0_bits.SE3 +#define SEGEN3 LCDSE0_bits.SEGEN3 +#define SE4 LCDSE0_bits.SE4 +#define SEGEN4 LCDSE0_bits.SEGEN4 +#define SE5 LCDSE0_bits.SE5 +#define SEGEN5 LCDSE0_bits.SEGEN5 +#define SE6 LCDSE0_bits.SE6 +#define SEGEN6 LCDSE0_bits.SEGEN6 +#define SE7 LCDSE0_bits.SE7 +#define SEGEN7 LCDSE0_bits.SEGEN7 + +// ----- LCDSE1 bits -------------------- +typedef union { + struct { + unsigned char SE8:1; + unsigned char SE9:1; + unsigned char SE10:1; + unsigned char SE11:1; + unsigned char SE12:1; + unsigned char SE13:1; + unsigned char SE14:1; + unsigned char SE15:1; + }; + struct { + unsigned char SEGEN8:1; + unsigned char SEGEN9:1; + unsigned char SEGEN10:1; + unsigned char SEGEN11:1; + unsigned char SEGEN12:1; + unsigned char SEGEN13:1; + unsigned char SEGEN14:1; + unsigned char SEGEN15:1; + }; +} __LCDSE1_bits_t; +extern volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits; + +#define SE8 LCDSE1_bits.SE8 +#define SEGEN8 LCDSE1_bits.SEGEN8 +#define SE9 LCDSE1_bits.SE9 +#define SEGEN9 LCDSE1_bits.SEGEN9 +#define SE10 LCDSE1_bits.SE10 +#define SEGEN10 LCDSE1_bits.SEGEN10 +#define SE11 LCDSE1_bits.SE11 +#define SEGEN11 LCDSE1_bits.SEGEN11 +#define SE12 LCDSE1_bits.SE12 +#define SEGEN12 LCDSE1_bits.SEGEN12 +#define SE13 LCDSE1_bits.SE13 +#define SEGEN13 LCDSE1_bits.SEGEN13 +#define SE14 LCDSE1_bits.SE14 +#define SEGEN14 LCDSE1_bits.SEGEN14 +#define SE15 LCDSE1_bits.SE15 +#define SEGEN15 LCDSE1_bits.SEGEN15 + +// ----- LCDSE2 bits -------------------- +typedef union { + struct { + unsigned char SE16:1; + unsigned char SE17:1; + unsigned char SE18:1; + unsigned char SE19:1; + unsigned char SE20:1; + unsigned char SE21:1; + unsigned char SE22:1; + unsigned char SE23:1; + }; + struct { + unsigned char SEGEN16:1; + unsigned char SEGEN17:1; + unsigned char SEGEN18:1; + unsigned char SEGEN19:1; + unsigned char SEGEN20:1; + unsigned char SEGEN21:1; + unsigned char SEGEN22:1; + unsigned char SEGEN23:1; + }; +} __LCDSE2_bits_t; +extern volatile __LCDSE2_bits_t __at(LCDSE2_ADDR) LCDSE2_bits; + +#define SE16 LCDSE2_bits.SE16 +#define SEGEN16 LCDSE2_bits.SEGEN16 +#define SE17 LCDSE2_bits.SE17 +#define SEGEN17 LCDSE2_bits.SEGEN17 +#define SE18 LCDSE2_bits.SE18 +#define SEGEN18 LCDSE2_bits.SEGEN18 +#define SE19 LCDSE2_bits.SE19 +#define SEGEN19 LCDSE2_bits.SEGEN19 +#define SE20 LCDSE2_bits.SE20 +#define SEGEN20 LCDSE2_bits.SEGEN20 +#define SE21 LCDSE2_bits.SE21 +#define SEGEN21 LCDSE2_bits.SEGEN21 +#define SE22 LCDSE2_bits.SE22 +#define SEGEN22 LCDSE2_bits.SEGEN22 +#define SE23 LCDSE2_bits.SE23 +#define SEGEN23 LCDSE2_bits.SEGEN23 + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LVDL0:1; + unsigned char LVDL1:1; + unsigned char LVDL2:1; + unsigned char :1; + unsigned char LVDEN:1; + unsigned char IRVST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LVDL0 LVDCON_bits.LVDL0 +#define LVDL1 LVDCON_bits.LVDL1 +#define LVDL2 LVDCON_bits.LVDL2 +#define LVDEN LVDCON_bits.LVDEN +#define IRVST LVDCON_bits.IRVST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBOREN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define SBOREN PCON_bits.SBOREN + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define EEIE PIE1_bits.EEIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char LVDIE:1; + unsigned char :1; + unsigned char LCDIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define LVDIE PIE2_bits.LVDIE +#define LCDIE PIE2_bits.LCDIE +#define C1IE PIE2_bits.C1IE +#define C2IE PIE2_bits.C2IE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define EEIF PIR1_bits.EEIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char LVDIF:1; + unsigned char :1; + unsigned char LCDIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define LVDIF PIR2_bits.LVDIF +#define LCDIF PIR2_bits.LCDIF +#define C1IF PIR2_bits.C1IF +#define C2IF PIR2_bits.C2IF +#define OSFIF PIR2_bits.OSFIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char T1GE:1; + unsigned char T1GINV:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define T1GE T1CON_bits.T1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char :1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VREN VRCON_bits.VREN + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char SWDTE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define SWDTE WDTCON_bits.SWDTE +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +// ----- WPU bits -------------------- +typedef union { + struct { + unsigned char WPU0:1; + unsigned char WPU1:1; + unsigned char WPU2:1; + unsigned char WPU3:1; + unsigned char WPU4:1; + unsigned char WPU5:1; + unsigned char WPU6:1; + unsigned char WPU7:1; + }; +} __WPU_bits_t; +extern volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits; + +#define WPU0 WPU_bits.WPU0 +#define WPU1 WPU_bits.WPU1 +#define WPU2 WPU_bits.WPU2 +#define WPU3 WPU_bits.WPU3 +#define WPU4 WPU_bits.WPU4 +#define WPU5 WPU_bits.WPU5 +#define WPU6 WPU_bits.WPU6 +#define WPU7 WPU_bits.WPU7 + +// ----- WPUB bits -------------------- +typedef union { + struct { + unsigned char WPUB0:1; + unsigned char WPUB1:1; + unsigned char WPUB2:1; + unsigned char WPUB3:1; + unsigned char WPUB4:1; + unsigned char WPUB5:1; + unsigned char WPUB6:1; + unsigned char WPUB7:1; + }; +} __WPUB_bits_t; +extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + +#define WPUB0 WPUB_bits.WPUB0 +#define WPUB1 WPUB_bits.WPUB1 +#define WPUB2 WPUB_bits.WPUB2 +#define WPUB3 WPUB_bits.WPUB3 +#define WPUB4 WPUB_bits.WPUB4 +#define WPUB5 WPUB_bits.WPUB5 +#define WPUB6 WPUB_bits.WPUB6 +#define WPUB7 WPUB_bits.WPUB7 + +#endif diff --git a/device/include/pic/pic16f916.h b/device/include/pic/pic16f916.h new file mode 100644 index 00000000..a9ed537a --- /dev/null +++ b/device/include/pic/pic16f916.h @@ -0,0 +1,1849 @@ +// +// Register Declarations for Microchip 16F916 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F916_H +#define P16F916_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define ANSEL_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPUB_ADDR 0x0095 +#define WPU_ADDR 0x0095 +#define IOCB_ADDR 0x0096 +#define IOC_ADDR 0x0096 +#define CMCON1_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define CMCON0_ADDR 0x009C +#define VRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define WDTCON_ADDR 0x0105 +#define LCDCON_ADDR 0x0107 +#define LCDPS_ADDR 0x0108 +#define LVDCON_ADDR 0x0109 +#define EEDATL_ADDR 0x010C +#define EEADRL_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define LCDDATA0_ADDR 0x0110 +#define LCDDATA1_ADDR 0x0111 +#define LCDDATA3_ADDR 0x0113 +#define LCDDATA4_ADDR 0x0114 +#define LCDDATA6_ADDR 0x0116 +#define LCDDATA7_ADDR 0x0117 +#define LCDDATA9_ADDR 0x0119 +#define LCDDATA10_ADDR 0x011A +#define LCDSE0_ADDR 0x011C +#define LCDSE1_ADDR 0x011D +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0 +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON +#pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap EEDATL_ADDR EEDATL_ADDR SFR 0x000 // EEDATL +#pragma memmap EEADRL_ADDR EEADRL_ADDR SFR 0x000 // EEADRL +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap LCDDATA0_ADDR LCDDATA0_ADDR SFR 0x000 // LCDDATA0 +#pragma memmap LCDDATA1_ADDR LCDDATA1_ADDR SFR 0x000 // LCDDATA1 +#pragma memmap LCDDATA3_ADDR LCDDATA3_ADDR SFR 0x000 // LCDDATA3 +#pragma memmap LCDDATA4_ADDR LCDDATA4_ADDR SFR 0x000 // LCDDATA4 +#pragma memmap LCDDATA6_ADDR LCDDATA6_ADDR SFR 0x000 // LCDDATA6 +#pragma memmap LCDDATA7_ADDR LCDDATA7_ADDR SFR 0x000 // LCDDATA7 +#pragma memmap LCDDATA9_ADDR LCDDATA9_ADDR SFR 0x000 // LCDDATA9 +#pragma memmap LCDDATA10_ADDR LCDDATA10_ADDR SFR 0x000 // LCDDATA10 +#pragma memmap LCDSE0_ADDR LCDSE0_ADDR SFR 0x000 // LCDSE0 +#pragma memmap LCDSE1_ADDR LCDSE1_ADDR SFR 0x000 // LCDSE1 +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F916.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F916 microcontroller. +// These names are taken to match the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F916 +// 2. LIST directive in the source file +// LIST P=PIC16F916 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.00 06/11/04 Initial Release +//1.01 06/18/04 Corrected typo in 'bad ram' section +//1.02 08/16/04 Added EECON2 + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F916 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (IOCB_ADDR) IOCB; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (CMCON1_ADDR) CMCON1; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (CMCON0_ADDR) CMCON0; +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (LCDCON_ADDR) LCDCON; +extern sfr __at (LCDPS_ADDR) LCDPS; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (EEDATL_ADDR) EEDATL; +extern sfr __at (EEADRL_ADDR) EEADRL; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; +extern sfr __at (LCDDATA0_ADDR) LCDDATA0; +extern sfr __at (LCDDATA1_ADDR) LCDDATA1; +extern sfr __at (LCDDATA3_ADDR) LCDDATA3; +extern sfr __at (LCDDATA4_ADDR) LCDDATA4; +extern sfr __at (LCDDATA6_ADDR) LCDDATA6; +extern sfr __at (LCDDATA7_ADDR) LCDDATA7; +extern sfr __at (LCDDATA9_ADDR) LCDDATA9; +extern sfr __at (LCDDATA10_ADDR) LCDDATA10; +extern sfr __at (LCDSE0_ADDR) LCDSE0; +extern sfr __at (LCDSE1_ADDR) LCDSE1; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits ------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + + +//----- ANSEL Bits --------------------------------------------------------- + + + +//----- SSPSTAT Bits ------------------------------------------------------- + + + +//----- WPUB Bits ------------------------------------------------------- + + +//----- WPU Bits ------------------------------------------------------- + + + +//----- IOCB Bits ------------------------------------------------------- + + + +//----- IOC Bits ------------------------------------------------------- + + + +//----- CMCON1 Bits -------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- CMCON0 Bits --------------------------------------------------------- + + +//----- VRCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- LCDCON Bits -------------------------------------------------------- + + +//----- LCDPS Bits --------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- LCDDATA0 Bits ------------------------------------------------------- + + + +//----- LCDDATA1 Bits ------------------------------------------------------- + + + + +//----- LCDDATA3 Bits ------------------------------------------------------- + + + +//----- LCDDATA4 Bits ------------------------------------------------------- + + + + +//----- LCDDATA6 Bits ------------------------------------------------------- + + + +//----- LCDDATA7 Bits ------------------------------------------------------- + + + + +//----- LCDDATA9 Bits ------------------------------------------------------- + + + +//----- LCDDATA10 Bits ------------------------------------------------------- + + + + +//----- LCDSE0 Bits -------------------------------------------------------- + + + +//----- LCDSE1 Bits -------------------------------------------------------- + + + + +//----- EECON1 Bits -------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'08', H'1B'-H'1D' +// __BADRAM H'88', H'9A'-H'9B' +// __BADRAM H'112', H'115', H'118', H'11B',H'11E'-H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CONFIG 0x2007 + +//Configuration Byte 1 Options +#define _DEBUG_ON 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_ON 0x3FEF +#define _PWRTE_OFF 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char NOT_DONE:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define VCFG0 ADCON0_bits.VCFG0 +#define VCFG1 ADCON0_bits.VCFG1 +#define ADFM ADCON0_bits.ADFM + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + unsigned char ADCS2:1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define ADCS0 ADCON1_bits.ADCS0 +#define ADCS1 ADCON1_bits.ADCS1 +#define ADCS2 ADCON1_bits.ADCS2 + +// ----- ANSEL bits -------------------- +typedef union { + struct { + unsigned char AN0:1; + unsigned char AN1:1; + unsigned char AN2:1; + unsigned char AN3:1; + unsigned char AN4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ANSEL_bits_t; +extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits; + +#define AN0 ANSEL_bits.AN0 +#define AN1 ANSEL_bits.AN1 +#define AN2 ANSEL_bits.AN2 +#define AN3 ANSEL_bits.AN3 +#define AN4 ANSEL_bits.AN4 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CMCON0 bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON0_bits_t; +extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; + +#define CM0 CMCON0_bits.CM0 +#define CM1 CMCON0_bits.CM1 +#define CM2 CMCON0_bits.CM2 +#define CIS CMCON0_bits.CIS +#define C1INV CMCON0_bits.C1INV +#define C2INV CMCON0_bits.C2INV +#define C1OUT CMCON0_bits.C1OUT +#define C2OUT CMCON0_bits.C2OUT + +// ----- CMCON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __CMCON1_bits_t; +extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; + +#define C2SYNC CMCON1_bits.C2SYNC +#define T1GSS CMCON1_bits.T1GSS + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; + struct { + unsigned char EERD:1; + unsigned char EEWR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define EERD EECON1_bits.EERD +#define WR EECON1_bits.WR +#define EEWR EECON1_bits.EEWR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char TMR0IF:1; + unsigned char :1; + unsigned char :1; + unsigned char TMR0IE:1; + unsigned char :1; + unsigned char :1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- IOC bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOC4:1; + unsigned char IOC5:1; + unsigned char IOC6:1; + unsigned char IOC7:1; + }; +} __IOC_bits_t; +extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits; + +#define IOC4 IOC_bits.IOC4 +#define IOC5 IOC_bits.IOC5 +#define IOC6 IOC_bits.IOC6 +#define IOC7 IOC_bits.IOC7 + +// ----- IOCB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOCB4:1; + unsigned char IOCB5:1; + unsigned char IOCB6:1; + unsigned char IOCB7:1; + }; +} __IOCB_bits_t; +extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits; + +#define IOCB4 IOCB_bits.IOCB4 +#define IOCB5 IOCB_bits.IOCB5 +#define IOCB6 IOCB_bits.IOCB6 +#define IOCB7 IOCB_bits.IOCB7 + +// ----- LCDCON bits -------------------- +typedef union { + struct { + unsigned char LMUX0:1; + unsigned char LMUX1:1; + unsigned char CS0:1; + unsigned char CS1:1; + unsigned char VLCDEN:1; + unsigned char WERR:1; + unsigned char SLPEN:1; + unsigned char LCDEN:1; + }; +} __LCDCON_bits_t; +extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; + +#define LMUX0 LCDCON_bits.LMUX0 +#define LMUX1 LCDCON_bits.LMUX1 +#define CS0 LCDCON_bits.CS0 +#define CS1 LCDCON_bits.CS1 +#define VLCDEN LCDCON_bits.VLCDEN +#define WERR LCDCON_bits.WERR +#define SLPEN LCDCON_bits.SLPEN +#define LCDEN LCDCON_bits.LCDEN + +// ----- LCDDATA0 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM0:1; + unsigned char SEG1COM0:1; + unsigned char SEG2COM0:1; + unsigned char SEG3COM0:1; + unsigned char SEG4COM0:1; + unsigned char SEG5COM0:1; + unsigned char SEG6COM0:1; + unsigned char SEG7COM0:1; + }; + struct { + unsigned char S0C0:1; + unsigned char S1C0:1; + unsigned char S2C0:1; + unsigned char S3C0:1; + unsigned char S4C0:1; + unsigned char S5C0:1; + unsigned char S6C0:1; + unsigned char S7C0:1; + }; +} __LCDDATA0_bits_t; +extern volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits; + +#define SEG0COM0 LCDDATA0_bits.SEG0COM0 +#define S0C0 LCDDATA0_bits.S0C0 +#define SEG1COM0 LCDDATA0_bits.SEG1COM0 +#define S1C0 LCDDATA0_bits.S1C0 +#define SEG2COM0 LCDDATA0_bits.SEG2COM0 +#define S2C0 LCDDATA0_bits.S2C0 +#define SEG3COM0 LCDDATA0_bits.SEG3COM0 +#define S3C0 LCDDATA0_bits.S3C0 +#define SEG4COM0 LCDDATA0_bits.SEG4COM0 +#define S4C0 LCDDATA0_bits.S4C0 +#define SEG5COM0 LCDDATA0_bits.SEG5COM0 +#define S5C0 LCDDATA0_bits.S5C0 +#define SEG6COM0 LCDDATA0_bits.SEG6COM0 +#define S6C0 LCDDATA0_bits.S6C0 +#define SEG7COM0 LCDDATA0_bits.SEG7COM0 +#define S7C0 LCDDATA0_bits.S7C0 + +// ----- LCDDATA1 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM0:1; + unsigned char SEG9COM0:1; + unsigned char SEG10COM0:1; + unsigned char SEG11COM0:1; + unsigned char SEG12COM0:1; + unsigned char SEG13COM0:1; + unsigned char SEG14COM0:1; + unsigned char SEG15COM0:1; + }; + struct { + unsigned char S8C0:1; + unsigned char S9C0:1; + unsigned char S10C0:1; + unsigned char S11C0:1; + unsigned char S12C0:1; + unsigned char S13C0:1; + unsigned char S14C0:1; + unsigned char S15C0:1; + }; +} __LCDDATA1_bits_t; +extern volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits; + +#define SEG8COM0 LCDDATA1_bits.SEG8COM0 +#define S8C0 LCDDATA1_bits.S8C0 +#define SEG9COM0 LCDDATA1_bits.SEG9COM0 +#define S9C0 LCDDATA1_bits.S9C0 +#define SEG10COM0 LCDDATA1_bits.SEG10COM0 +#define S10C0 LCDDATA1_bits.S10C0 +#define SEG11COM0 LCDDATA1_bits.SEG11COM0 +#define S11C0 LCDDATA1_bits.S11C0 +#define SEG12COM0 LCDDATA1_bits.SEG12COM0 +#define S12C0 LCDDATA1_bits.S12C0 +#define SEG13COM0 LCDDATA1_bits.SEG13COM0 +#define S13C0 LCDDATA1_bits.S13C0 +#define SEG14COM0 LCDDATA1_bits.SEG14COM0 +#define S14C0 LCDDATA1_bits.S14C0 +#define SEG15COM0 LCDDATA1_bits.SEG15COM0 +#define S15C0 LCDDATA1_bits.S15C0 + +// ----- LCDDATA10 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM3:1; + unsigned char SEG9COM3:1; + unsigned char SEG10COM3:1; + unsigned char SEG11COM3:1; + unsigned char SEG12COM3:1; + unsigned char SEG13COM3:1; + unsigned char SEG14COM3:1; + unsigned char SEG15COM3:1; + }; + struct { + unsigned char S8C3:1; + unsigned char S9C3:1; + unsigned char S10C3:1; + unsigned char S11C3:1; + unsigned char S12C3:1; + unsigned char S13C3:1; + unsigned char S14C3:1; + unsigned char S15C3:1; + }; +} __LCDDATA10_bits_t; +extern volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits; + +#define SEG8COM3 LCDDATA10_bits.SEG8COM3 +#define S8C3 LCDDATA10_bits.S8C3 +#define SEG9COM3 LCDDATA10_bits.SEG9COM3 +#define S9C3 LCDDATA10_bits.S9C3 +#define SEG10COM3 LCDDATA10_bits.SEG10COM3 +#define S10C3 LCDDATA10_bits.S10C3 +#define SEG11COM3 LCDDATA10_bits.SEG11COM3 +#define S11C3 LCDDATA10_bits.S11C3 +#define SEG12COM3 LCDDATA10_bits.SEG12COM3 +#define S12C3 LCDDATA10_bits.S12C3 +#define SEG13COM3 LCDDATA10_bits.SEG13COM3 +#define S13C3 LCDDATA10_bits.S13C3 +#define SEG14COM3 LCDDATA10_bits.SEG14COM3 +#define S14C3 LCDDATA10_bits.S14C3 +#define SEG15COM3 LCDDATA10_bits.SEG15COM3 +#define S15C3 LCDDATA10_bits.S15C3 + +// ----- LCDDATA3 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM1:1; + unsigned char SEG1COM1:1; + unsigned char SEG2COM1:1; + unsigned char SEG3COM1:1; + unsigned char SEG4COM1:1; + unsigned char SEG5COM1:1; + unsigned char SEG6COM1:1; + unsigned char SEG7COM1:1; + }; + struct { + unsigned char S0C1:1; + unsigned char S1C1:1; + unsigned char S2C1:1; + unsigned char S3C1:1; + unsigned char S4C1:1; + unsigned char S5C1:1; + unsigned char S6C1:1; + unsigned char S7C1:1; + }; +} __LCDDATA3_bits_t; +extern volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits; + +#define SEG0COM1 LCDDATA3_bits.SEG0COM1 +#define S0C1 LCDDATA3_bits.S0C1 +#define SEG1COM1 LCDDATA3_bits.SEG1COM1 +#define S1C1 LCDDATA3_bits.S1C1 +#define SEG2COM1 LCDDATA3_bits.SEG2COM1 +#define S2C1 LCDDATA3_bits.S2C1 +#define SEG3COM1 LCDDATA3_bits.SEG3COM1 +#define S3C1 LCDDATA3_bits.S3C1 +#define SEG4COM1 LCDDATA3_bits.SEG4COM1 +#define S4C1 LCDDATA3_bits.S4C1 +#define SEG5COM1 LCDDATA3_bits.SEG5COM1 +#define S5C1 LCDDATA3_bits.S5C1 +#define SEG6COM1 LCDDATA3_bits.SEG6COM1 +#define S6C1 LCDDATA3_bits.S6C1 +#define SEG7COM1 LCDDATA3_bits.SEG7COM1 +#define S7C1 LCDDATA3_bits.S7C1 + +// ----- LCDDATA4 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM1:1; + unsigned char SEG9COM1:1; + unsigned char SEG10COM1:1; + unsigned char SEG11COM1:1; + unsigned char SEG12COM1:1; + unsigned char SEG13COM1:1; + unsigned char SEG14COM1:1; + unsigned char SEG15COM1:1; + }; + struct { + unsigned char S8C1:1; + unsigned char S9C1:1; + unsigned char S10C1:1; + unsigned char S11C1:1; + unsigned char S12C1:1; + unsigned char S13C1:1; + unsigned char S14C1:1; + unsigned char S15C1:1; + }; +} __LCDDATA4_bits_t; +extern volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits; + +#define SEG8COM1 LCDDATA4_bits.SEG8COM1 +#define S8C1 LCDDATA4_bits.S8C1 +#define SEG9COM1 LCDDATA4_bits.SEG9COM1 +#define S9C1 LCDDATA4_bits.S9C1 +#define SEG10COM1 LCDDATA4_bits.SEG10COM1 +#define S10C1 LCDDATA4_bits.S10C1 +#define SEG11COM1 LCDDATA4_bits.SEG11COM1 +#define S11C1 LCDDATA4_bits.S11C1 +#define SEG12COM1 LCDDATA4_bits.SEG12COM1 +#define S12C1 LCDDATA4_bits.S12C1 +#define SEG13COM1 LCDDATA4_bits.SEG13COM1 +#define S13C1 LCDDATA4_bits.S13C1 +#define SEG14COM1 LCDDATA4_bits.SEG14COM1 +#define S14C1 LCDDATA4_bits.S14C1 +#define SEG15COM1 LCDDATA4_bits.SEG15COM1 +#define S15C1 LCDDATA4_bits.S15C1 + +// ----- LCDDATA6 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM2:1; + unsigned char SEG1COM2:1; + unsigned char SEG2COM2:1; + unsigned char SEG3COM2:1; + unsigned char SEG4COM2:1; + unsigned char SEG5COM2:1; + unsigned char SEG6COM2:1; + unsigned char SEG7COM2:1; + }; + struct { + unsigned char S0C2:1; + unsigned char S1C2:1; + unsigned char S2C2:1; + unsigned char S3C2:1; + unsigned char S4C2:1; + unsigned char S5C2:1; + unsigned char S6C2:1; + unsigned char S7C2:1; + }; +} __LCDDATA6_bits_t; +extern volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits; + +#define SEG0COM2 LCDDATA6_bits.SEG0COM2 +#define S0C2 LCDDATA6_bits.S0C2 +#define SEG1COM2 LCDDATA6_bits.SEG1COM2 +#define S1C2 LCDDATA6_bits.S1C2 +#define SEG2COM2 LCDDATA6_bits.SEG2COM2 +#define S2C2 LCDDATA6_bits.S2C2 +#define SEG3COM2 LCDDATA6_bits.SEG3COM2 +#define S3C2 LCDDATA6_bits.S3C2 +#define SEG4COM2 LCDDATA6_bits.SEG4COM2 +#define S4C2 LCDDATA6_bits.S4C2 +#define SEG5COM2 LCDDATA6_bits.SEG5COM2 +#define S5C2 LCDDATA6_bits.S5C2 +#define SEG6COM2 LCDDATA6_bits.SEG6COM2 +#define S6C2 LCDDATA6_bits.S6C2 +#define SEG7COM2 LCDDATA6_bits.SEG7COM2 +#define S7C2 LCDDATA6_bits.S7C2 + +// ----- LCDDATA7 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM2:1; + unsigned char SEG9COM2:1; + unsigned char SEG10COM2:1; + unsigned char SEG11COM2:1; + unsigned char SEG12COM2:1; + unsigned char SEG13COM2:1; + unsigned char SEG14COM2:1; + unsigned char SEG15COM2:1; + }; + struct { + unsigned char S8C2:1; + unsigned char S9C2:1; + unsigned char S10C2:1; + unsigned char S11C2:1; + unsigned char S12C2:1; + unsigned char S13C2:1; + unsigned char S14C2:1; + unsigned char S15C2:1; + }; +} __LCDDATA7_bits_t; +extern volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits; + +#define SEG8COM2 LCDDATA7_bits.SEG8COM2 +#define S8C2 LCDDATA7_bits.S8C2 +#define SEG9COM2 LCDDATA7_bits.SEG9COM2 +#define S9C2 LCDDATA7_bits.S9C2 +#define SEG10COM2 LCDDATA7_bits.SEG10COM2 +#define S10C2 LCDDATA7_bits.S10C2 +#define SEG11COM2 LCDDATA7_bits.SEG11COM2 +#define S11C2 LCDDATA7_bits.S11C2 +#define SEG12COM2 LCDDATA7_bits.SEG12COM2 +#define S12C2 LCDDATA7_bits.S12C2 +#define SEG13COM2 LCDDATA7_bits.SEG13COM2 +#define S13C2 LCDDATA7_bits.S13C2 +#define SEG14COM2 LCDDATA7_bits.SEG14COM2 +#define S14C2 LCDDATA7_bits.S14C2 +#define SEG15COM2 LCDDATA7_bits.SEG15COM2 +#define S15C2 LCDDATA7_bits.S15C2 + +// ----- LCDDATA9 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM3:1; + unsigned char SEG1COM3:1; + unsigned char SEG2COM3:1; + unsigned char SEG3COM3:1; + unsigned char SEG4COM3:1; + unsigned char SEG5COM3:1; + unsigned char SEG6COM3:1; + unsigned char SEG7COM3:1; + }; + struct { + unsigned char S0C3:1; + unsigned char S1C3:1; + unsigned char S2C3:1; + unsigned char S3C3:1; + unsigned char S4C3:1; + unsigned char S5C3:1; + unsigned char S6C3:1; + unsigned char S7C3:1; + }; +} __LCDDATA9_bits_t; +extern volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits; + +#define SEG0COM3 LCDDATA9_bits.SEG0COM3 +#define S0C3 LCDDATA9_bits.S0C3 +#define SEG1COM3 LCDDATA9_bits.SEG1COM3 +#define S1C3 LCDDATA9_bits.S1C3 +#define SEG2COM3 LCDDATA9_bits.SEG2COM3 +#define S2C3 LCDDATA9_bits.S2C3 +#define SEG3COM3 LCDDATA9_bits.SEG3COM3 +#define S3C3 LCDDATA9_bits.S3C3 +#define SEG4COM3 LCDDATA9_bits.SEG4COM3 +#define S4C3 LCDDATA9_bits.S4C3 +#define SEG5COM3 LCDDATA9_bits.SEG5COM3 +#define S5C3 LCDDATA9_bits.S5C3 +#define SEG6COM3 LCDDATA9_bits.SEG6COM3 +#define S6C3 LCDDATA9_bits.S6C3 +#define SEG7COM3 LCDDATA9_bits.SEG7COM3 +#define S7C3 LCDDATA9_bits.S7C3 + +// ----- LCDPS bits -------------------- +typedef union { + struct { + unsigned char LP0:1; + unsigned char LP1:1; + unsigned char LP2:1; + unsigned char LP3:1; + unsigned char WA:1; + unsigned char LCDA:1; + unsigned char BIASMD:1; + unsigned char WFT:1; + }; +} __LCDPS_bits_t; +extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; + +#define LP0 LCDPS_bits.LP0 +#define LP1 LCDPS_bits.LP1 +#define LP2 LCDPS_bits.LP2 +#define LP3 LCDPS_bits.LP3 +#define WA LCDPS_bits.WA +#define LCDA LCDPS_bits.LCDA +#define BIASMD LCDPS_bits.BIASMD +#define WFT LCDPS_bits.WFT + +// ----- LCDSE0 bits -------------------- +typedef union { + struct { + unsigned char SE0:1; + unsigned char SE1:1; + unsigned char SE2:1; + unsigned char SE3:1; + unsigned char SE4:1; + unsigned char SE5:1; + unsigned char SE6:1; + unsigned char SE7:1; + }; + struct { + unsigned char SEGEN0:1; + unsigned char SEGEN1:1; + unsigned char SEGEN2:1; + unsigned char SEGEN3:1; + unsigned char SEGEN4:1; + unsigned char SEGEN5:1; + unsigned char SEGEN6:1; + unsigned char SEGEN7:1; + }; +} __LCDSE0_bits_t; +extern volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits; + +#define SE0 LCDSE0_bits.SE0 +#define SEGEN0 LCDSE0_bits.SEGEN0 +#define SE1 LCDSE0_bits.SE1 +#define SEGEN1 LCDSE0_bits.SEGEN1 +#define SE2 LCDSE0_bits.SE2 +#define SEGEN2 LCDSE0_bits.SEGEN2 +#define SE3 LCDSE0_bits.SE3 +#define SEGEN3 LCDSE0_bits.SEGEN3 +#define SE4 LCDSE0_bits.SE4 +#define SEGEN4 LCDSE0_bits.SEGEN4 +#define SE5 LCDSE0_bits.SE5 +#define SEGEN5 LCDSE0_bits.SEGEN5 +#define SE6 LCDSE0_bits.SE6 +#define SEGEN6 LCDSE0_bits.SEGEN6 +#define SE7 LCDSE0_bits.SE7 +#define SEGEN7 LCDSE0_bits.SEGEN7 + +// ----- LCDSE1 bits -------------------- +typedef union { + struct { + unsigned char SE8:1; + unsigned char SE9:1; + unsigned char SE10:1; + unsigned char SE11:1; + unsigned char SE12:1; + unsigned char SE13:1; + unsigned char SE14:1; + unsigned char SE15:1; + }; + struct { + unsigned char SEGEN8:1; + unsigned char SEGEN9:1; + unsigned char SEGEN10:1; + unsigned char SEGEN11:1; + unsigned char SEGEN12:1; + unsigned char SEGEN13:1; + unsigned char SEGEN14:1; + unsigned char SEGEN15:1; + }; +} __LCDSE1_bits_t; +extern volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits; + +#define SE8 LCDSE1_bits.SE8 +#define SEGEN8 LCDSE1_bits.SEGEN8 +#define SE9 LCDSE1_bits.SE9 +#define SEGEN9 LCDSE1_bits.SEGEN9 +#define SE10 LCDSE1_bits.SE10 +#define SEGEN10 LCDSE1_bits.SEGEN10 +#define SE11 LCDSE1_bits.SE11 +#define SEGEN11 LCDSE1_bits.SEGEN11 +#define SE12 LCDSE1_bits.SE12 +#define SEGEN12 LCDSE1_bits.SEGEN12 +#define SE13 LCDSE1_bits.SE13 +#define SEGEN13 LCDSE1_bits.SEGEN13 +#define SE14 LCDSE1_bits.SE14 +#define SEGEN14 LCDSE1_bits.SEGEN14 +#define SE15 LCDSE1_bits.SE15 +#define SEGEN15 LCDSE1_bits.SEGEN15 + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LVDL0:1; + unsigned char LVDL1:1; + unsigned char LVDL2:1; + unsigned char :1; + unsigned char LVDEN:1; + unsigned char IRVST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LVDL0 LVDCON_bits.LVDL0 +#define LVDL1 LVDCON_bits.LVDL1 +#define LVDL2 LVDCON_bits.LVDL2 +#define LVDEN LVDCON_bits.LVDEN +#define IRVST LVDCON_bits.IRVST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBOREN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define SBOREN PCON_bits.SBOREN + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define EEIE PIE1_bits.EEIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char LVDIE:1; + unsigned char :1; + unsigned char LCDIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define LVDIE PIE2_bits.LVDIE +#define LCDIE PIE2_bits.LCDIE +#define C1IE PIE2_bits.C1IE +#define C2IE PIE2_bits.C2IE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define EEIF PIR1_bits.EEIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char LVDIF:1; + unsigned char :1; + unsigned char LCDIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define LVDIF PIR2_bits.LVDIF +#define LCDIF PIR2_bits.LCDIF +#define C1IF PIR2_bits.C1IF +#define C2IF PIR2_bits.C2IF +#define OSFIF PIR2_bits.OSFIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char T1GE:1; + unsigned char T1GINV:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define T1GE T1CON_bits.T1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char :1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VREN VRCON_bits.VREN + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char SWDTE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define SWDTE WDTCON_bits.SWDTE +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +// ----- WPU bits -------------------- +typedef union { + struct { + unsigned char WPU0:1; + unsigned char WPU1:1; + unsigned char WPU2:1; + unsigned char WPU3:1; + unsigned char WPU4:1; + unsigned char WPU5:1; + unsigned char WPU6:1; + unsigned char WPU7:1; + }; +} __WPU_bits_t; +extern volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits; + +#define WPU0 WPU_bits.WPU0 +#define WPU1 WPU_bits.WPU1 +#define WPU2 WPU_bits.WPU2 +#define WPU3 WPU_bits.WPU3 +#define WPU4 WPU_bits.WPU4 +#define WPU5 WPU_bits.WPU5 +#define WPU6 WPU_bits.WPU6 +#define WPU7 WPU_bits.WPU7 + +// ----- WPUB bits -------------------- +typedef union { + struct { + unsigned char WPUB0:1; + unsigned char WPUB1:1; + unsigned char WPUB2:1; + unsigned char WPUB3:1; + unsigned char WPUB4:1; + unsigned char WPUB5:1; + unsigned char WPUB6:1; + unsigned char WPUB7:1; + }; +} __WPUB_bits_t; +extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + +#define WPUB0 WPUB_bits.WPUB0 +#define WPUB1 WPUB_bits.WPUB1 +#define WPUB2 WPUB_bits.WPUB2 +#define WPUB3 WPUB_bits.WPUB3 +#define WPUB4 WPUB_bits.WPUB4 +#define WPUB5 WPUB_bits.WPUB5 +#define WPUB6 WPUB_bits.WPUB6 +#define WPUB7 WPUB_bits.WPUB7 + +#endif diff --git a/device/include/pic/pic16f917.h b/device/include/pic/pic16f917.h new file mode 100644 index 00000000..d6206372 --- /dev/null +++ b/device/include/pic/pic16f917.h @@ -0,0 +1,2132 @@ +// +// Register Declarations for Microchip 16F917 Processor +// +// +// This header file was automatically generated by: +// +// inc2h.pl V1.6 +// +// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved +// +// SDCC is licensed under the GNU Public license (GPL) v2. Note that +// this license covers the code to the compiler and other executables, +// but explicitly does not cover any code or objects generated by sdcc. +// We have not yet decided on a license for the run time libraries, but +// it will not put any requirements on code linked against it. See: +// +// http://www.gnu.org/copyleft/gpl/html +// +// See http://sdcc.sourceforge.net/ for the latest information on sdcc. +// +// +#ifndef P16F917_H +#define P16F917_H + +// +// Register addresses. +// +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define PORTA_ADDR 0x0005 +#define PORTB_ADDR 0x0006 +#define PORTC_ADDR 0x0007 +#define PORTD_ADDR 0x0008 +#define PORTE_ADDR 0x0009 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define PIR2_ADDR 0x000D +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define TMR2_ADDR 0x0011 +#define T2CON_ADDR 0x0012 +#define SSPBUF_ADDR 0x0013 +#define SSPCON_ADDR 0x0014 +#define CCPR1L_ADDR 0x0015 +#define CCPR1H_ADDR 0x0016 +#define CCP1CON_ADDR 0x0017 +#define RCSTA_ADDR 0x0018 +#define TXREG_ADDR 0x0019 +#define RCREG_ADDR 0x001A +#define CCPR2L_ADDR 0x001B +#define CCPR2H_ADDR 0x001C +#define CCP2CON_ADDR 0x001D +#define ADRESH_ADDR 0x001E +#define ADCON0_ADDR 0x001F +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISB_ADDR 0x0086 +#define TRISC_ADDR 0x0087 +#define TRISD_ADDR 0x0088 +#define TRISE_ADDR 0x0089 +#define PIE1_ADDR 0x008C +#define PIE2_ADDR 0x008D +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define ANSEL_ADDR 0x0091 +#define PR2_ADDR 0x0092 +#define SSPADD_ADDR 0x0093 +#define SSPSTAT_ADDR 0x0094 +#define WPUB_ADDR 0x0095 +#define WPU_ADDR 0x0095 +#define IOCB_ADDR 0x0096 +#define IOC_ADDR 0x0096 +#define CMCON1_ADDR 0x0097 +#define TXSTA_ADDR 0x0098 +#define SPBRG_ADDR 0x0099 +#define CMCON0_ADDR 0x009C +#define VRCON_ADDR 0x009D +#define ADRESL_ADDR 0x009E +#define ADCON1_ADDR 0x009F +#define WDTCON_ADDR 0x0105 +#define LCDCON_ADDR 0x0107 +#define LCDPS_ADDR 0x0108 +#define LVDCON_ADDR 0x0109 +#define EEDATL_ADDR 0x010C +#define EEADRL_ADDR 0x010D +#define EEDATH_ADDR 0x010E +#define EEADRH_ADDR 0x010F +#define LCDDATA0_ADDR 0x0110 +#define LCDDATA1_ADDR 0x0111 +#define LCDDATA2_ADDR 0x0112 +#define LCDDATA3_ADDR 0x0113 +#define LCDDATA4_ADDR 0x0114 +#define LCDDATA5_ADDR 0x0115 +#define LCDDATA6_ADDR 0x0116 +#define LCDDATA7_ADDR 0x0117 +#define LCDDATA8_ADDR 0x0118 +#define LCDDATA9_ADDR 0x0119 +#define LCDDATA10_ADDR 0x011A +#define LCDDATA11_ADDR 0x011B +#define LCDSE0_ADDR 0x011C +#define LCDSE1_ADDR 0x011D +#define LCDSE2_ADDR 0x011E +#define EECON1_ADDR 0x018C +#define EECON2_ADDR 0x018D + +// +// Memory organization. +// + +#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF +#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0 +#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL +#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS +#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR +#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA +#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB +#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC +#pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD +#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE +#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH +#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON +#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1 +#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2 +#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L +#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H +#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON +#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2 +#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON +#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF +#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON +#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L +#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H +#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON +#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA +#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG +#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG +#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L +#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H +#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON +#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH +#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0 +#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG +#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA +#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB +#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC +#pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD +#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE +#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1 +#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2 +#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON +#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON +#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE +#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL +#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2 +#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD +#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT +#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB +#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU +#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB +#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC +#pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1 +#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA +#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG +#pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0 +#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON +#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL +#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1 +#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON +#pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON +#pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS +#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON +#pragma memmap EEDATL_ADDR EEDATL_ADDR SFR 0x000 // EEDATL +#pragma memmap EEADRL_ADDR EEADRL_ADDR SFR 0x000 // EEADRL +#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH +#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH +#pragma memmap LCDDATA0_ADDR LCDDATA0_ADDR SFR 0x000 // LCDDATA0 +#pragma memmap LCDDATA1_ADDR LCDDATA1_ADDR SFR 0x000 // LCDDATA1 +#pragma memmap LCDDATA2_ADDR LCDDATA2_ADDR SFR 0x000 // LCDDATA2 +#pragma memmap LCDDATA3_ADDR LCDDATA3_ADDR SFR 0x000 // LCDDATA3 +#pragma memmap LCDDATA4_ADDR LCDDATA4_ADDR SFR 0x000 // LCDDATA4 +#pragma memmap LCDDATA5_ADDR LCDDATA5_ADDR SFR 0x000 // LCDDATA5 +#pragma memmap LCDDATA6_ADDR LCDDATA6_ADDR SFR 0x000 // LCDDATA6 +#pragma memmap LCDDATA7_ADDR LCDDATA7_ADDR SFR 0x000 // LCDDATA7 +#pragma memmap LCDDATA8_ADDR LCDDATA8_ADDR SFR 0x000 // LCDDATA8 +#pragma memmap LCDDATA9_ADDR LCDDATA9_ADDR SFR 0x000 // LCDDATA9 +#pragma memmap LCDDATA10_ADDR LCDDATA10_ADDR SFR 0x000 // LCDDATA10 +#pragma memmap LCDDATA11_ADDR LCDDATA11_ADDR SFR 0x000 // LCDDATA11 +#pragma memmap LCDSE0_ADDR LCDSE0_ADDR SFR 0x000 // LCDSE0 +#pragma memmap LCDSE1_ADDR LCDSE1_ADDR SFR 0x000 // LCDSE1 +#pragma memmap LCDSE2_ADDR LCDSE2_ADDR SFR 0x000 // LCDSE2 +#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1 +#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2 + + +// LIST +// P16F917.INC Standard Header File, Version 1.00 Microchip Technology, Inc. +// NOLIST + +// This header file defines configurations, registers, and other useful bits of +// information for the PIC16F917 microcontroller. +// These names are taken to match the data sheets as closely as possible. + +// Note that the processor must be selected before this file is +// included. The processor may be selected the following ways: + +// 1. Command line switch: +// C:\ MPASM MYFILE.ASM /PIC16F917 +// 2. LIST directive in the source file +// LIST P=PIC16F917 +// 3. Processor Type entry in the MPASM full-screen interface + +//========================================================================== +// +// Revision History +// +//========================================================================== + +//Rev: Date: Reason: +//1.00 06/11/04 Initial Release +//1.01 08/16/04 Added EECON2 + + +//========================================================================== +// +// Verify Processor +// +//========================================================================== + +// IFNDEF __16F917 +// MESSG "Processor-header file mismatch. Verify selected processor." +// ENDIF + +//========================================================================== +// +// Register Definitions +// +//========================================================================== + +#define W 0x0000 +#define F 0x0001 + +//----- Register Files------------------------------------------------------ + +extern data __at (INDF_ADDR) volatile char INDF; +extern sfr __at (TMR0_ADDR) TMR0; +extern data __at (PCL_ADDR) volatile char PCL; +extern sfr __at (STATUS_ADDR) STATUS; +extern sfr __at (FSR_ADDR) FSR; +extern sfr __at (PORTA_ADDR) PORTA; +extern sfr __at (PORTB_ADDR) PORTB; +extern sfr __at (PORTC_ADDR) PORTC; +extern sfr __at (PORTD_ADDR) PORTD; +extern sfr __at (PORTE_ADDR) PORTE; +extern sfr __at (PCLATH_ADDR) PCLATH; +extern sfr __at (INTCON_ADDR) INTCON; +extern sfr __at (PIR1_ADDR) PIR1; +extern sfr __at (PIR2_ADDR) PIR2; +extern sfr __at (TMR1L_ADDR) TMR1L; +extern sfr __at (TMR1H_ADDR) TMR1H; +extern sfr __at (T1CON_ADDR) T1CON; +extern sfr __at (TMR2_ADDR) TMR2; +extern sfr __at (T2CON_ADDR) T2CON; +extern sfr __at (SSPBUF_ADDR) SSPBUF; +extern sfr __at (SSPCON_ADDR) SSPCON; +extern sfr __at (CCPR1L_ADDR) CCPR1L; +extern sfr __at (CCPR1H_ADDR) CCPR1H; +extern sfr __at (CCP1CON_ADDR) CCP1CON; +extern sfr __at (RCSTA_ADDR) RCSTA; +extern sfr __at (TXREG_ADDR) TXREG; +extern sfr __at (RCREG_ADDR) RCREG; +extern sfr __at (CCPR2L_ADDR) CCPR2L; +extern sfr __at (CCPR2H_ADDR) CCPR2H; +extern sfr __at (CCP2CON_ADDR) CCP2CON; +extern sfr __at (ADRESH_ADDR) ADRESH; +extern sfr __at (ADCON0_ADDR) ADCON0; + +extern sfr __at (OPTION_REG_ADDR) OPTION_REG; +extern sfr __at (TRISA_ADDR) TRISA; +extern sfr __at (TRISB_ADDR) TRISB; +extern sfr __at (TRISC_ADDR) TRISC; +extern sfr __at (TRISD_ADDR) TRISD; +extern sfr __at (TRISE_ADDR) TRISE; +extern sfr __at (PIE1_ADDR) PIE1; +extern sfr __at (PIE2_ADDR) PIE2; +extern sfr __at (PCON_ADDR) PCON; +extern sfr __at (OSCCON_ADDR) OSCCON; +extern sfr __at (OSCTUNE_ADDR) OSCTUNE; +extern sfr __at (ANSEL_ADDR) ANSEL; +extern sfr __at (PR2_ADDR) PR2; +extern sfr __at (SSPADD_ADDR) SSPADD; +extern sfr __at (SSPSTAT_ADDR) SSPSTAT; +extern sfr __at (WPUB_ADDR) WPUB; +extern sfr __at (WPU_ADDR) WPU; +extern sfr __at (IOCB_ADDR) IOCB; +extern sfr __at (IOC_ADDR) IOC; +extern sfr __at (CMCON1_ADDR) CMCON1; +extern sfr __at (TXSTA_ADDR) TXSTA; +extern sfr __at (SPBRG_ADDR) SPBRG; +extern sfr __at (CMCON0_ADDR) CMCON0; +extern sfr __at (VRCON_ADDR) VRCON; +extern sfr __at (ADRESL_ADDR) ADRESL; +extern sfr __at (ADCON1_ADDR) ADCON1; + +extern sfr __at (WDTCON_ADDR) WDTCON; +extern sfr __at (LCDCON_ADDR) LCDCON; +extern sfr __at (LCDPS_ADDR) LCDPS; +extern sfr __at (LVDCON_ADDR) LVDCON; +extern sfr __at (EEDATL_ADDR) EEDATL; +extern sfr __at (EEADRL_ADDR) EEADRL; +extern sfr __at (EEDATH_ADDR) EEDATH; +extern sfr __at (EEADRH_ADDR) EEADRH; +extern sfr __at (LCDDATA0_ADDR) LCDDATA0; +extern sfr __at (LCDDATA1_ADDR) LCDDATA1; +extern sfr __at (LCDDATA2_ADDR) LCDDATA2; +extern sfr __at (LCDDATA3_ADDR) LCDDATA3; +extern sfr __at (LCDDATA4_ADDR) LCDDATA4; +extern sfr __at (LCDDATA5_ADDR) LCDDATA5; +extern sfr __at (LCDDATA6_ADDR) LCDDATA6; +extern sfr __at (LCDDATA7_ADDR) LCDDATA7; +extern sfr __at (LCDDATA8_ADDR) LCDDATA8; +extern sfr __at (LCDDATA9_ADDR) LCDDATA9; +extern sfr __at (LCDDATA10_ADDR) LCDDATA10; +extern sfr __at (LCDDATA11_ADDR) LCDDATA11; +extern sfr __at (LCDSE0_ADDR) LCDSE0; +extern sfr __at (LCDSE1_ADDR) LCDSE1; +extern sfr __at (LCDSE2_ADDR) LCDSE2; + +extern sfr __at (EECON1_ADDR) EECON1; +extern sfr __at (EECON2_ADDR) EECON2; + + +//----- STATUS Bits -------------------------------------------------------- + + +//----- INTCON Bits -------------------------------------------------------- + + +//----- PIR1 Bits ---------------------------------------------------------- + + +//----- PIR2 Bits ---------------------------------------------------------- + + +//----- T1CON Bits --------------------------------------------------------- + + +//----- T2CON Bits --------------------------------------------------------- + + +//----- SSPCON Bits -------------------------------------------------------- + + +//----- CCP1CON Bits ------------------------------------------------------- + + +//----- RCSTA Bits --------------------------------------------------------- + + +//----- CCP2CON Bits ------------------------------------------------------- + + +//----- ADCON0 Bits -------------------------------------------------------- + + +//----- OPTION Bits ----------------------------------------------------- + + +//----- PIE1 Bits ---------------------------------------------------------- + + +//----- PIE2 Bits ---------------------------------------------------------- + + +//----- PCON Bits ---------------------------------------------------------- + + +//----- OSCCON Bits ------------------------------------------------------- + + +//----- OSCTUNE Bits ------------------------------------------------------- + + + +//----- ANSEL Bits --------------------------------------------------------- + + + +//----- SSPSTAT Bits ------------------------------------------------------- + + + +//----- WPUB Bits ------------------------------------------------------- + + +//----- WPU Bits ------------------------------------------------------- + + + +//----- IOCB Bits ------------------------------------------------------- + + + +//----- IOC Bits ------------------------------------------------------- + + + +//----- CMCON1 Bits -------------------------------------------------------- + + +//----- TXSTA Bits --------------------------------------------------------- + + + +//----- CMCON0 Bits --------------------------------------------------------- + + +//----- VRCON Bits -------------------------------------------------------- + + +//----- ADCON1 Bits -------------------------------------------------------- + + +//----- WDTCON Bits -------------------------------------------------------- + + +//----- LCDCON Bits -------------------------------------------------------- + + +//----- LCDPS Bits --------------------------------------------------------- + + +//----- LVDCON Bits -------------------------------------------------------- + + +//----- LCDDATA0 Bits ------------------------------------------------------- + + + +//----- LCDDATA1 Bits ------------------------------------------------------- + + + +//----- LCDDATA2 Bits ------------------------------------------------------- + + + +//----- LCDDATA3 Bits ------------------------------------------------------- + + + +//----- LCDDATA4 Bits ------------------------------------------------------- + + + +//----- LCDDATA5 Bits ------------------------------------------------------- + + + +//----- LCDDATA6 Bits ------------------------------------------------------- + + + +//----- LCDDATA7 Bits ------------------------------------------------------- + + + +//----- LCDDATA8 Bits ------------------------------------------------------- + + + +//----- LCDDATA9 Bits ------------------------------------------------------- + + + +//----- LCDDATA10 Bits ------------------------------------------------------- + + + +//----- LCDDATA11 Bits ------------------------------------------------------- + + + +//----- LCDSE0 Bits -------------------------------------------------------- + + + +//----- LCDSE1 Bits -------------------------------------------------------- + + + +//----- LCDSE2 Bits -------------------------------------------------------- + + + +//----- EECON1 Bits -------------------------------------------------------- + + + +//========================================================================== +// +// RAM Definition +// +//========================================================================== + +// __MAXRAM H'1FF' +// __BADRAM H'9A'-H'9B' +// __BADRAM H'11F' +// __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' + +//========================================================================== +// +// Configuration Bits +// +//========================================================================== + +#define _CONFIG 0x2007 + +//Configuration Byte 1 Options +#define _DEBUG_ON 0x2FFF +#define _DEBUG_OFF 0x3FFF +#define _FCMEN_ON 0x3FFF +#define _FCMEN_OFF 0x37FF +#define _IESO_ON 0x3FFF +#define _IESO_OFF 0x3BFF +#define _BOD_ON 0x3FFF +#define _BOD_NSLEEP 0x3EFF +#define _BOD_SBODEN 0x3DFF +#define _BOD_OFF 0x3CFF +#define _CPD_ON 0x3F7F +#define _CPD_OFF 0x3FFF +#define _CP_ON 0x3FBF +#define _CP_OFF 0x3FFF +#define _MCLRE_ON 0x3FFF +#define _MCLRE_OFF 0x3FDF +#define _PWRTE_ON 0x3FEF +#define _PWRTE_OFF 0x3FFF +#define _WDT_ON 0x3FFF +#define _WDT_OFF 0x3FF7 +#define _LP_OSC 0x3FF8 +#define _XT_OSC 0x3FF9 +#define _HS_OSC 0x3FFA +#define _EC_OSC 0x3FFB +#define _INTRC_OSC_NOCLKOUT 0x3FFC +#define _INTRC_OSC_CLKOUT 0x3FFD +#define _EXTRC_OSC_NOCLKOUT 0x3FFE +#define _EXTRC_OSC_CLKOUT 0x3FFF +#define _INTOSCIO 0x3FFC +#define _INTOSC 0x3FFD +#define _EXTRCIO 0x3FFE +#define _EXTRC 0x3FFF + + +// LIST + +// ----- ADCON0 bits -------------------- +typedef union { + struct { + unsigned char ADON:1; + unsigned char NOT_DONE:1; + unsigned char CHS0:1; + unsigned char CHS1:1; + unsigned char CHS2:1; + unsigned char VCFG0:1; + unsigned char VCFG1:1; + unsigned char ADFM:1; + }; + struct { + unsigned char :1; + unsigned char GO_DONE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __ADCON0_bits_t; +extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; + +#define ADON ADCON0_bits.ADON +#define NOT_DONE ADCON0_bits.NOT_DONE +#define GO_DONE ADCON0_bits.GO_DONE +#define CHS0 ADCON0_bits.CHS0 +#define CHS1 ADCON0_bits.CHS1 +#define CHS2 ADCON0_bits.CHS2 +#define VCFG0 ADCON0_bits.VCFG0 +#define VCFG1 ADCON0_bits.VCFG1 +#define ADFM ADCON0_bits.ADFM + +// ----- ADCON1 bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char ADCS0:1; + unsigned char ADCS1:1; + unsigned char ADCS2:1; + unsigned char :1; + }; +} __ADCON1_bits_t; +extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; + +#define ADCS0 ADCON1_bits.ADCS0 +#define ADCS1 ADCON1_bits.ADCS1 +#define ADCS2 ADCON1_bits.ADCS2 + +// ----- ANSEL bits -------------------- +typedef union { + struct { + unsigned char AN0:1; + unsigned char AN1:1; + unsigned char AN2:1; + unsigned char AN3:1; + unsigned char AN4:1; + unsigned char AN5:1; + unsigned char AN6:1; + unsigned char AN7:1; + }; +} __ANSEL_bits_t; +extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits; + +#define AN0 ANSEL_bits.AN0 +#define AN1 ANSEL_bits.AN1 +#define AN2 ANSEL_bits.AN2 +#define AN3 ANSEL_bits.AN3 +#define AN4 ANSEL_bits.AN4 +#define AN5 ANSEL_bits.AN5 +#define AN6 ANSEL_bits.AN6 +#define AN7 ANSEL_bits.AN7 + +// ----- CCP1CON bits -------------------- +typedef union { + struct { + unsigned char CCP1M0:1; + unsigned char CCP1M1:1; + unsigned char CCP1M2:1; + unsigned char CCP1M3:1; + unsigned char CCP1Y:1; + unsigned char CCP1X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP1CON_bits_t; +extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; + +#define CCP1M0 CCP1CON_bits.CCP1M0 +#define CCP1M1 CCP1CON_bits.CCP1M1 +#define CCP1M2 CCP1CON_bits.CCP1M2 +#define CCP1M3 CCP1CON_bits.CCP1M3 +#define CCP1Y CCP1CON_bits.CCP1Y +#define CCP1X CCP1CON_bits.CCP1X + +// ----- CCP2CON bits -------------------- +typedef union { + struct { + unsigned char CCP2M0:1; + unsigned char CCP2M1:1; + unsigned char CCP2M2:1; + unsigned char CCP2M3:1; + unsigned char CCP2Y:1; + unsigned char CCP2X:1; + unsigned char :1; + unsigned char :1; + }; +} __CCP2CON_bits_t; +extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; + +#define CCP2M0 CCP2CON_bits.CCP2M0 +#define CCP2M1 CCP2CON_bits.CCP2M1 +#define CCP2M2 CCP2CON_bits.CCP2M2 +#define CCP2M3 CCP2CON_bits.CCP2M3 +#define CCP2Y CCP2CON_bits.CCP2Y +#define CCP2X CCP2CON_bits.CCP2X + +// ----- CMCON0 bits -------------------- +typedef union { + struct { + unsigned char CM0:1; + unsigned char CM1:1; + unsigned char CM2:1; + unsigned char CIS:1; + unsigned char C1INV:1; + unsigned char C2INV:1; + unsigned char C1OUT:1; + unsigned char C2OUT:1; + }; +} __CMCON0_bits_t; +extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; + +#define CM0 CMCON0_bits.CM0 +#define CM1 CMCON0_bits.CM1 +#define CM2 CMCON0_bits.CM2 +#define CIS CMCON0_bits.CIS +#define C1INV CMCON0_bits.C1INV +#define C2INV CMCON0_bits.C2INV +#define C1OUT CMCON0_bits.C1OUT +#define C2OUT CMCON0_bits.C2OUT + +// ----- CMCON1 bits -------------------- +typedef union { + struct { + unsigned char C2SYNC:1; + unsigned char T1GSS:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __CMCON1_bits_t; +extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; + +#define C2SYNC CMCON1_bits.C2SYNC +#define T1GSS CMCON1_bits.T1GSS + +// ----- EECON1 bits -------------------- +typedef union { + struct { + unsigned char RD:1; + unsigned char WR:1; + unsigned char WREN:1; + unsigned char WRERR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char EEPGD:1; + }; + struct { + unsigned char EERD:1; + unsigned char EEWR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __EECON1_bits_t; +extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; + +#define RD EECON1_bits.RD +#define EERD EECON1_bits.EERD +#define WR EECON1_bits.WR +#define EEWR EECON1_bits.EEWR +#define WREN EECON1_bits.WREN +#define WRERR EECON1_bits.WRERR +#define EEPGD EECON1_bits.EEPGD + +// ----- INTCON bits -------------------- +typedef union { + struct { + unsigned char RBIF:1; + unsigned char INTF:1; + unsigned char T0IF:1; + unsigned char RBIE:1; + unsigned char INTE:1; + unsigned char T0IE:1; + unsigned char PEIE:1; + unsigned char GIE:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char TMR0IF:1; + unsigned char :1; + unsigned char :1; + unsigned char TMR0IE:1; + unsigned char :1; + unsigned char :1; + }; +} __INTCON_bits_t; +extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; + +#define RBIF INTCON_bits.RBIF +#define INTF INTCON_bits.INTF +#define T0IF INTCON_bits.T0IF +#define TMR0IF INTCON_bits.TMR0IF +#define RBIE INTCON_bits.RBIE +#define INTE INTCON_bits.INTE +#define T0IE INTCON_bits.T0IE +#define TMR0IE INTCON_bits.TMR0IE +#define PEIE INTCON_bits.PEIE +#define GIE INTCON_bits.GIE + +// ----- IOC bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOC4:1; + unsigned char IOC5:1; + unsigned char IOC6:1; + unsigned char IOC7:1; + }; +} __IOC_bits_t; +extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits; + +#define IOC4 IOC_bits.IOC4 +#define IOC5 IOC_bits.IOC5 +#define IOC6 IOC_bits.IOC6 +#define IOC7 IOC_bits.IOC7 + +// ----- IOCB bits -------------------- +typedef union { + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char IOCB4:1; + unsigned char IOCB5:1; + unsigned char IOCB6:1; + unsigned char IOCB7:1; + }; +} __IOCB_bits_t; +extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits; + +#define IOCB4 IOCB_bits.IOCB4 +#define IOCB5 IOCB_bits.IOCB5 +#define IOCB6 IOCB_bits.IOCB6 +#define IOCB7 IOCB_bits.IOCB7 + +// ----- LCDCON bits -------------------- +typedef union { + struct { + unsigned char LMUX0:1; + unsigned char LMUX1:1; + unsigned char CS0:1; + unsigned char CS1:1; + unsigned char VLCDEN:1; + unsigned char WERR:1; + unsigned char SLPEN:1; + unsigned char LCDEN:1; + }; +} __LCDCON_bits_t; +extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; + +#define LMUX0 LCDCON_bits.LMUX0 +#define LMUX1 LCDCON_bits.LMUX1 +#define CS0 LCDCON_bits.CS0 +#define CS1 LCDCON_bits.CS1 +#define VLCDEN LCDCON_bits.VLCDEN +#define WERR LCDCON_bits.WERR +#define SLPEN LCDCON_bits.SLPEN +#define LCDEN LCDCON_bits.LCDEN + +// ----- LCDDATA0 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM0:1; + unsigned char SEG1COM0:1; + unsigned char SEG2COM0:1; + unsigned char SEG3COM0:1; + unsigned char SEG4COM0:1; + unsigned char SEG5COM0:1; + unsigned char SEG6COM0:1; + unsigned char SEG7COM0:1; + }; + struct { + unsigned char S0C0:1; + unsigned char S1C0:1; + unsigned char S2C0:1; + unsigned char S3C0:1; + unsigned char S4C0:1; + unsigned char S5C0:1; + unsigned char S6C0:1; + unsigned char S7C0:1; + }; +} __LCDDATA0_bits_t; +extern volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits; + +#define SEG0COM0 LCDDATA0_bits.SEG0COM0 +#define S0C0 LCDDATA0_bits.S0C0 +#define SEG1COM0 LCDDATA0_bits.SEG1COM0 +#define S1C0 LCDDATA0_bits.S1C0 +#define SEG2COM0 LCDDATA0_bits.SEG2COM0 +#define S2C0 LCDDATA0_bits.S2C0 +#define SEG3COM0 LCDDATA0_bits.SEG3COM0 +#define S3C0 LCDDATA0_bits.S3C0 +#define SEG4COM0 LCDDATA0_bits.SEG4COM0 +#define S4C0 LCDDATA0_bits.S4C0 +#define SEG5COM0 LCDDATA0_bits.SEG5COM0 +#define S5C0 LCDDATA0_bits.S5C0 +#define SEG6COM0 LCDDATA0_bits.SEG6COM0 +#define S6C0 LCDDATA0_bits.S6C0 +#define SEG7COM0 LCDDATA0_bits.SEG7COM0 +#define S7C0 LCDDATA0_bits.S7C0 + +// ----- LCDDATA1 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM0:1; + unsigned char SEG9COM0:1; + unsigned char SEG10COM0:1; + unsigned char SEG11COM0:1; + unsigned char SEG12COM0:1; + unsigned char SEG13COM0:1; + unsigned char SEG14COM0:1; + unsigned char SEG15COM0:1; + }; + struct { + unsigned char S8C0:1; + unsigned char S9C0:1; + unsigned char S10C0:1; + unsigned char S11C0:1; + unsigned char S12C0:1; + unsigned char S13C0:1; + unsigned char S14C0:1; + unsigned char S15C0:1; + }; +} __LCDDATA1_bits_t; +extern volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits; + +#define SEG8COM0 LCDDATA1_bits.SEG8COM0 +#define S8C0 LCDDATA1_bits.S8C0 +#define SEG9COM0 LCDDATA1_bits.SEG9COM0 +#define S9C0 LCDDATA1_bits.S9C0 +#define SEG10COM0 LCDDATA1_bits.SEG10COM0 +#define S10C0 LCDDATA1_bits.S10C0 +#define SEG11COM0 LCDDATA1_bits.SEG11COM0 +#define S11C0 LCDDATA1_bits.S11C0 +#define SEG12COM0 LCDDATA1_bits.SEG12COM0 +#define S12C0 LCDDATA1_bits.S12C0 +#define SEG13COM0 LCDDATA1_bits.SEG13COM0 +#define S13C0 LCDDATA1_bits.S13C0 +#define SEG14COM0 LCDDATA1_bits.SEG14COM0 +#define S14C0 LCDDATA1_bits.S14C0 +#define SEG15COM0 LCDDATA1_bits.SEG15COM0 +#define S15C0 LCDDATA1_bits.S15C0 + +// ----- LCDDATA10 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM3:1; + unsigned char SEG9COM3:1; + unsigned char SEG10COM3:1; + unsigned char SEG11COM3:1; + unsigned char SEG12COM3:1; + unsigned char SEG13COM3:1; + unsigned char SEG14COM3:1; + unsigned char SEG15COM3:1; + }; + struct { + unsigned char S8C3:1; + unsigned char S9C3:1; + unsigned char S10C3:1; + unsigned char S11C3:1; + unsigned char S12C3:1; + unsigned char S13C3:1; + unsigned char S14C3:1; + unsigned char S15C3:1; + }; +} __LCDDATA10_bits_t; +extern volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits; + +#define SEG8COM3 LCDDATA10_bits.SEG8COM3 +#define S8C3 LCDDATA10_bits.S8C3 +#define SEG9COM3 LCDDATA10_bits.SEG9COM3 +#define S9C3 LCDDATA10_bits.S9C3 +#define SEG10COM3 LCDDATA10_bits.SEG10COM3 +#define S10C3 LCDDATA10_bits.S10C3 +#define SEG11COM3 LCDDATA10_bits.SEG11COM3 +#define S11C3 LCDDATA10_bits.S11C3 +#define SEG12COM3 LCDDATA10_bits.SEG12COM3 +#define S12C3 LCDDATA10_bits.S12C3 +#define SEG13COM3 LCDDATA10_bits.SEG13COM3 +#define S13C3 LCDDATA10_bits.S13C3 +#define SEG14COM3 LCDDATA10_bits.SEG14COM3 +#define S14C3 LCDDATA10_bits.S14C3 +#define SEG15COM3 LCDDATA10_bits.SEG15COM3 +#define S15C3 LCDDATA10_bits.S15C3 + +// ----- LCDDATA11 bits -------------------- +typedef union { + struct { + unsigned char SEG16COM3:1; + unsigned char SEG17COM3:1; + unsigned char SEG18COM3:1; + unsigned char SEG19COM3:1; + unsigned char SEG20COM3:1; + unsigned char SEG21COM3:1; + unsigned char SEG22COM3:1; + unsigned char SEG23COM3:1; + }; + struct { + unsigned char S16C3:1; + unsigned char S17C3:1; + unsigned char S18C3:1; + unsigned char S19C3:1; + unsigned char S20C3:1; + unsigned char S21C3:1; + unsigned char S22C3:1; + unsigned char S23C3:1; + }; +} __LCDDATA11_bits_t; +extern volatile __LCDDATA11_bits_t __at(LCDDATA11_ADDR) LCDDATA11_bits; + +#define SEG16COM3 LCDDATA11_bits.SEG16COM3 +#define S16C3 LCDDATA11_bits.S16C3 +#define SEG17COM3 LCDDATA11_bits.SEG17COM3 +#define S17C3 LCDDATA11_bits.S17C3 +#define SEG18COM3 LCDDATA11_bits.SEG18COM3 +#define S18C3 LCDDATA11_bits.S18C3 +#define SEG19COM3 LCDDATA11_bits.SEG19COM3 +#define S19C3 LCDDATA11_bits.S19C3 +#define SEG20COM3 LCDDATA11_bits.SEG20COM3 +#define S20C3 LCDDATA11_bits.S20C3 +#define SEG21COM3 LCDDATA11_bits.SEG21COM3 +#define S21C3 LCDDATA11_bits.S21C3 +#define SEG22COM3 LCDDATA11_bits.SEG22COM3 +#define S22C3 LCDDATA11_bits.S22C3 +#define SEG23COM3 LCDDATA11_bits.SEG23COM3 +#define S23C3 LCDDATA11_bits.S23C3 + +// ----- LCDDATA2 bits -------------------- +typedef union { + struct { + unsigned char SEG16COM0:1; + unsigned char SEG17COM0:1; + unsigned char SEG18COM0:1; + unsigned char SEG19COM0:1; + unsigned char SEG20COM0:1; + unsigned char SEG21COM0:1; + unsigned char SEG22COM0:1; + unsigned char SEG23COM0:1; + }; + struct { + unsigned char S16C0:1; + unsigned char S17C0:1; + unsigned char S18C0:1; + unsigned char S19C0:1; + unsigned char S20C0:1; + unsigned char S21C0:1; + unsigned char S22C0:1; + unsigned char S23C0:1; + }; +} __LCDDATA2_bits_t; +extern volatile __LCDDATA2_bits_t __at(LCDDATA2_ADDR) LCDDATA2_bits; + +#define SEG16COM0 LCDDATA2_bits.SEG16COM0 +#define S16C0 LCDDATA2_bits.S16C0 +#define SEG17COM0 LCDDATA2_bits.SEG17COM0 +#define S17C0 LCDDATA2_bits.S17C0 +#define SEG18COM0 LCDDATA2_bits.SEG18COM0 +#define S18C0 LCDDATA2_bits.S18C0 +#define SEG19COM0 LCDDATA2_bits.SEG19COM0 +#define S19C0 LCDDATA2_bits.S19C0 +#define SEG20COM0 LCDDATA2_bits.SEG20COM0 +#define S20C0 LCDDATA2_bits.S20C0 +#define SEG21COM0 LCDDATA2_bits.SEG21COM0 +#define S21C0 LCDDATA2_bits.S21C0 +#define SEG22COM0 LCDDATA2_bits.SEG22COM0 +#define S22C0 LCDDATA2_bits.S22C0 +#define SEG23COM0 LCDDATA2_bits.SEG23COM0 +#define S23C0 LCDDATA2_bits.S23C0 + +// ----- LCDDATA3 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM1:1; + unsigned char SEG1COM1:1; + unsigned char SEG2COM1:1; + unsigned char SEG3COM1:1; + unsigned char SEG4COM1:1; + unsigned char SEG5COM1:1; + unsigned char SEG6COM1:1; + unsigned char SEG7COM1:1; + }; + struct { + unsigned char S0C1:1; + unsigned char S1C1:1; + unsigned char S2C1:1; + unsigned char S3C1:1; + unsigned char S4C1:1; + unsigned char S5C1:1; + unsigned char S6C1:1; + unsigned char S7C1:1; + }; +} __LCDDATA3_bits_t; +extern volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits; + +#define SEG0COM1 LCDDATA3_bits.SEG0COM1 +#define S0C1 LCDDATA3_bits.S0C1 +#define SEG1COM1 LCDDATA3_bits.SEG1COM1 +#define S1C1 LCDDATA3_bits.S1C1 +#define SEG2COM1 LCDDATA3_bits.SEG2COM1 +#define S2C1 LCDDATA3_bits.S2C1 +#define SEG3COM1 LCDDATA3_bits.SEG3COM1 +#define S3C1 LCDDATA3_bits.S3C1 +#define SEG4COM1 LCDDATA3_bits.SEG4COM1 +#define S4C1 LCDDATA3_bits.S4C1 +#define SEG5COM1 LCDDATA3_bits.SEG5COM1 +#define S5C1 LCDDATA3_bits.S5C1 +#define SEG6COM1 LCDDATA3_bits.SEG6COM1 +#define S6C1 LCDDATA3_bits.S6C1 +#define SEG7COM1 LCDDATA3_bits.SEG7COM1 +#define S7C1 LCDDATA3_bits.S7C1 + +// ----- LCDDATA4 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM1:1; + unsigned char SEG9COM1:1; + unsigned char SEG10COM1:1; + unsigned char SEG11COM1:1; + unsigned char SEG12COM1:1; + unsigned char SEG13COM1:1; + unsigned char SEG14COM1:1; + unsigned char SEG15COM1:1; + }; + struct { + unsigned char S8C1:1; + unsigned char S9C1:1; + unsigned char S10C1:1; + unsigned char S11C1:1; + unsigned char S12C1:1; + unsigned char S13C1:1; + unsigned char S14C1:1; + unsigned char S15C1:1; + }; +} __LCDDATA4_bits_t; +extern volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits; + +#define SEG8COM1 LCDDATA4_bits.SEG8COM1 +#define S8C1 LCDDATA4_bits.S8C1 +#define SEG9COM1 LCDDATA4_bits.SEG9COM1 +#define S9C1 LCDDATA4_bits.S9C1 +#define SEG10COM1 LCDDATA4_bits.SEG10COM1 +#define S10C1 LCDDATA4_bits.S10C1 +#define SEG11COM1 LCDDATA4_bits.SEG11COM1 +#define S11C1 LCDDATA4_bits.S11C1 +#define SEG12COM1 LCDDATA4_bits.SEG12COM1 +#define S12C1 LCDDATA4_bits.S12C1 +#define SEG13COM1 LCDDATA4_bits.SEG13COM1 +#define S13C1 LCDDATA4_bits.S13C1 +#define SEG14COM1 LCDDATA4_bits.SEG14COM1 +#define S14C1 LCDDATA4_bits.S14C1 +#define SEG15COM1 LCDDATA4_bits.SEG15COM1 +#define S15C1 LCDDATA4_bits.S15C1 + +// ----- LCDDATA5 bits -------------------- +typedef union { + struct { + unsigned char SEG16COM1:1; + unsigned char SEG17COM1:1; + unsigned char SEG18COM1:1; + unsigned char SEG19COM1:1; + unsigned char SEG20COM1:1; + unsigned char SEG21COM1:1; + unsigned char SEG22COM1:1; + unsigned char SEG23COM1:1; + }; + struct { + unsigned char S16C1:1; + unsigned char S17C1:1; + unsigned char S18C1:1; + unsigned char S19C1:1; + unsigned char S20C1:1; + unsigned char S21C1:1; + unsigned char S22C1:1; + unsigned char S23C1:1; + }; +} __LCDDATA5_bits_t; +extern volatile __LCDDATA5_bits_t __at(LCDDATA5_ADDR) LCDDATA5_bits; + +#define SEG16COM1 LCDDATA5_bits.SEG16COM1 +#define S16C1 LCDDATA5_bits.S16C1 +#define SEG17COM1 LCDDATA5_bits.SEG17COM1 +#define S17C1 LCDDATA5_bits.S17C1 +#define SEG18COM1 LCDDATA5_bits.SEG18COM1 +#define S18C1 LCDDATA5_bits.S18C1 +#define SEG19COM1 LCDDATA5_bits.SEG19COM1 +#define S19C1 LCDDATA5_bits.S19C1 +#define SEG20COM1 LCDDATA5_bits.SEG20COM1 +#define S20C1 LCDDATA5_bits.S20C1 +#define SEG21COM1 LCDDATA5_bits.SEG21COM1 +#define S21C1 LCDDATA5_bits.S21C1 +#define SEG22COM1 LCDDATA5_bits.SEG22COM1 +#define S22C1 LCDDATA5_bits.S22C1 +#define SEG23COM1 LCDDATA5_bits.SEG23COM1 +#define S23C1 LCDDATA5_bits.S23C1 + +// ----- LCDDATA6 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM2:1; + unsigned char SEG1COM2:1; + unsigned char SEG2COM2:1; + unsigned char SEG3COM2:1; + unsigned char SEG4COM2:1; + unsigned char SEG5COM2:1; + unsigned char SEG6COM2:1; + unsigned char SEG7COM2:1; + }; + struct { + unsigned char S0C2:1; + unsigned char S1C2:1; + unsigned char S2C2:1; + unsigned char S3C2:1; + unsigned char S4C2:1; + unsigned char S5C2:1; + unsigned char S6C2:1; + unsigned char S7C2:1; + }; +} __LCDDATA6_bits_t; +extern volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits; + +#define SEG0COM2 LCDDATA6_bits.SEG0COM2 +#define S0C2 LCDDATA6_bits.S0C2 +#define SEG1COM2 LCDDATA6_bits.SEG1COM2 +#define S1C2 LCDDATA6_bits.S1C2 +#define SEG2COM2 LCDDATA6_bits.SEG2COM2 +#define S2C2 LCDDATA6_bits.S2C2 +#define SEG3COM2 LCDDATA6_bits.SEG3COM2 +#define S3C2 LCDDATA6_bits.S3C2 +#define SEG4COM2 LCDDATA6_bits.SEG4COM2 +#define S4C2 LCDDATA6_bits.S4C2 +#define SEG5COM2 LCDDATA6_bits.SEG5COM2 +#define S5C2 LCDDATA6_bits.S5C2 +#define SEG6COM2 LCDDATA6_bits.SEG6COM2 +#define S6C2 LCDDATA6_bits.S6C2 +#define SEG7COM2 LCDDATA6_bits.SEG7COM2 +#define S7C2 LCDDATA6_bits.S7C2 + +// ----- LCDDATA7 bits -------------------- +typedef union { + struct { + unsigned char SEG8COM2:1; + unsigned char SEG9COM2:1; + unsigned char SEG10COM2:1; + unsigned char SEG11COM2:1; + unsigned char SEG12COM2:1; + unsigned char SEG13COM2:1; + unsigned char SEG14COM2:1; + unsigned char SEG15COM2:1; + }; + struct { + unsigned char S8C2:1; + unsigned char S9C2:1; + unsigned char S10C2:1; + unsigned char S11C2:1; + unsigned char S12C2:1; + unsigned char S13C2:1; + unsigned char S14C2:1; + unsigned char S15C2:1; + }; +} __LCDDATA7_bits_t; +extern volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits; + +#define SEG8COM2 LCDDATA7_bits.SEG8COM2 +#define S8C2 LCDDATA7_bits.S8C2 +#define SEG9COM2 LCDDATA7_bits.SEG9COM2 +#define S9C2 LCDDATA7_bits.S9C2 +#define SEG10COM2 LCDDATA7_bits.SEG10COM2 +#define S10C2 LCDDATA7_bits.S10C2 +#define SEG11COM2 LCDDATA7_bits.SEG11COM2 +#define S11C2 LCDDATA7_bits.S11C2 +#define SEG12COM2 LCDDATA7_bits.SEG12COM2 +#define S12C2 LCDDATA7_bits.S12C2 +#define SEG13COM2 LCDDATA7_bits.SEG13COM2 +#define S13C2 LCDDATA7_bits.S13C2 +#define SEG14COM2 LCDDATA7_bits.SEG14COM2 +#define S14C2 LCDDATA7_bits.S14C2 +#define SEG15COM2 LCDDATA7_bits.SEG15COM2 +#define S15C2 LCDDATA7_bits.S15C2 + +// ----- LCDDATA8 bits -------------------- +typedef union { + struct { + unsigned char SEG16COM2:1; + unsigned char SEG17COM2:1; + unsigned char SEG18COM2:1; + unsigned char SEG19COM2:1; + unsigned char SEG20COM2:1; + unsigned char SEG21COM2:1; + unsigned char SEG22COM2:1; + unsigned char SEG23COM2:1; + }; + struct { + unsigned char S16C2:1; + unsigned char S17C2:1; + unsigned char S18C2:1; + unsigned char S19C2:1; + unsigned char S20C2:1; + unsigned char S21C2:1; + unsigned char S22C2:1; + unsigned char S23C2:1; + }; +} __LCDDATA8_bits_t; +extern volatile __LCDDATA8_bits_t __at(LCDDATA8_ADDR) LCDDATA8_bits; + +#define SEG16COM2 LCDDATA8_bits.SEG16COM2 +#define S16C2 LCDDATA8_bits.S16C2 +#define SEG17COM2 LCDDATA8_bits.SEG17COM2 +#define S17C2 LCDDATA8_bits.S17C2 +#define SEG18COM2 LCDDATA8_bits.SEG18COM2 +#define S18C2 LCDDATA8_bits.S18C2 +#define SEG19COM2 LCDDATA8_bits.SEG19COM2 +#define S19C2 LCDDATA8_bits.S19C2 +#define SEG20COM2 LCDDATA8_bits.SEG20COM2 +#define S20C2 LCDDATA8_bits.S20C2 +#define SEG21COM2 LCDDATA8_bits.SEG21COM2 +#define S21C2 LCDDATA8_bits.S21C2 +#define SEG22COM2 LCDDATA8_bits.SEG22COM2 +#define S22C2 LCDDATA8_bits.S22C2 +#define SEG23COM2 LCDDATA8_bits.SEG23COM2 +#define S23C2 LCDDATA8_bits.S23C2 + +// ----- LCDDATA9 bits -------------------- +typedef union { + struct { + unsigned char SEG0COM3:1; + unsigned char SEG1COM3:1; + unsigned char SEG2COM3:1; + unsigned char SEG3COM3:1; + unsigned char SEG4COM3:1; + unsigned char SEG5COM3:1; + unsigned char SEG6COM3:1; + unsigned char SEG7COM3:1; + }; + struct { + unsigned char S0C3:1; + unsigned char S1C3:1; + unsigned char S2C3:1; + unsigned char S3C3:1; + unsigned char S4C3:1; + unsigned char S5C3:1; + unsigned char S6C3:1; + unsigned char S7C3:1; + }; +} __LCDDATA9_bits_t; +extern volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits; + +#define SEG0COM3 LCDDATA9_bits.SEG0COM3 +#define S0C3 LCDDATA9_bits.S0C3 +#define SEG1COM3 LCDDATA9_bits.SEG1COM3 +#define S1C3 LCDDATA9_bits.S1C3 +#define SEG2COM3 LCDDATA9_bits.SEG2COM3 +#define S2C3 LCDDATA9_bits.S2C3 +#define SEG3COM3 LCDDATA9_bits.SEG3COM3 +#define S3C3 LCDDATA9_bits.S3C3 +#define SEG4COM3 LCDDATA9_bits.SEG4COM3 +#define S4C3 LCDDATA9_bits.S4C3 +#define SEG5COM3 LCDDATA9_bits.SEG5COM3 +#define S5C3 LCDDATA9_bits.S5C3 +#define SEG6COM3 LCDDATA9_bits.SEG6COM3 +#define S6C3 LCDDATA9_bits.S6C3 +#define SEG7COM3 LCDDATA9_bits.SEG7COM3 +#define S7C3 LCDDATA9_bits.S7C3 + +// ----- LCDPS bits -------------------- +typedef union { + struct { + unsigned char LP0:1; + unsigned char LP1:1; + unsigned char LP2:1; + unsigned char LP3:1; + unsigned char WA:1; + unsigned char LCDA:1; + unsigned char BIASMD:1; + unsigned char WFT:1; + }; +} __LCDPS_bits_t; +extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; + +#define LP0 LCDPS_bits.LP0 +#define LP1 LCDPS_bits.LP1 +#define LP2 LCDPS_bits.LP2 +#define LP3 LCDPS_bits.LP3 +#define WA LCDPS_bits.WA +#define LCDA LCDPS_bits.LCDA +#define BIASMD LCDPS_bits.BIASMD +#define WFT LCDPS_bits.WFT + +// ----- LCDSE0 bits -------------------- +typedef union { + struct { + unsigned char SE0:1; + unsigned char SE1:1; + unsigned char SE2:1; + unsigned char SE3:1; + unsigned char SE4:1; + unsigned char SE5:1; + unsigned char SE6:1; + unsigned char SE7:1; + }; + struct { + unsigned char SEGEN0:1; + unsigned char SEGEN1:1; + unsigned char SEGEN2:1; + unsigned char SEGEN3:1; + unsigned char SEGEN4:1; + unsigned char SEGEN5:1; + unsigned char SEGEN6:1; + unsigned char SEGEN7:1; + }; +} __LCDSE0_bits_t; +extern volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits; + +#define SE0 LCDSE0_bits.SE0 +#define SEGEN0 LCDSE0_bits.SEGEN0 +#define SE1 LCDSE0_bits.SE1 +#define SEGEN1 LCDSE0_bits.SEGEN1 +#define SE2 LCDSE0_bits.SE2 +#define SEGEN2 LCDSE0_bits.SEGEN2 +#define SE3 LCDSE0_bits.SE3 +#define SEGEN3 LCDSE0_bits.SEGEN3 +#define SE4 LCDSE0_bits.SE4 +#define SEGEN4 LCDSE0_bits.SEGEN4 +#define SE5 LCDSE0_bits.SE5 +#define SEGEN5 LCDSE0_bits.SEGEN5 +#define SE6 LCDSE0_bits.SE6 +#define SEGEN6 LCDSE0_bits.SEGEN6 +#define SE7 LCDSE0_bits.SE7 +#define SEGEN7 LCDSE0_bits.SEGEN7 + +// ----- LCDSE1 bits -------------------- +typedef union { + struct { + unsigned char SE8:1; + unsigned char SE9:1; + unsigned char SE10:1; + unsigned char SE11:1; + unsigned char SE12:1; + unsigned char SE13:1; + unsigned char SE14:1; + unsigned char SE15:1; + }; + struct { + unsigned char SEGEN8:1; + unsigned char SEGEN9:1; + unsigned char SEGEN10:1; + unsigned char SEGEN11:1; + unsigned char SEGEN12:1; + unsigned char SEGEN13:1; + unsigned char SEGEN14:1; + unsigned char SEGEN15:1; + }; +} __LCDSE1_bits_t; +extern volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits; + +#define SE8 LCDSE1_bits.SE8 +#define SEGEN8 LCDSE1_bits.SEGEN8 +#define SE9 LCDSE1_bits.SE9 +#define SEGEN9 LCDSE1_bits.SEGEN9 +#define SE10 LCDSE1_bits.SE10 +#define SEGEN10 LCDSE1_bits.SEGEN10 +#define SE11 LCDSE1_bits.SE11 +#define SEGEN11 LCDSE1_bits.SEGEN11 +#define SE12 LCDSE1_bits.SE12 +#define SEGEN12 LCDSE1_bits.SEGEN12 +#define SE13 LCDSE1_bits.SE13 +#define SEGEN13 LCDSE1_bits.SEGEN13 +#define SE14 LCDSE1_bits.SE14 +#define SEGEN14 LCDSE1_bits.SEGEN14 +#define SE15 LCDSE1_bits.SE15 +#define SEGEN15 LCDSE1_bits.SEGEN15 + +// ----- LCDSE2 bits -------------------- +typedef union { + struct { + unsigned char SE16:1; + unsigned char SE17:1; + unsigned char SE18:1; + unsigned char SE19:1; + unsigned char SE20:1; + unsigned char SE21:1; + unsigned char SE22:1; + unsigned char SE23:1; + }; + struct { + unsigned char SEGEN16:1; + unsigned char SEGEN17:1; + unsigned char SEGEN18:1; + unsigned char SEGEN19:1; + unsigned char SEGEN20:1; + unsigned char SEGEN21:1; + unsigned char SEGEN22:1; + unsigned char SEGEN23:1; + }; +} __LCDSE2_bits_t; +extern volatile __LCDSE2_bits_t __at(LCDSE2_ADDR) LCDSE2_bits; + +#define SE16 LCDSE2_bits.SE16 +#define SEGEN16 LCDSE2_bits.SEGEN16 +#define SE17 LCDSE2_bits.SE17 +#define SEGEN17 LCDSE2_bits.SEGEN17 +#define SE18 LCDSE2_bits.SE18 +#define SEGEN18 LCDSE2_bits.SEGEN18 +#define SE19 LCDSE2_bits.SE19 +#define SEGEN19 LCDSE2_bits.SEGEN19 +#define SE20 LCDSE2_bits.SE20 +#define SEGEN20 LCDSE2_bits.SEGEN20 +#define SE21 LCDSE2_bits.SE21 +#define SEGEN21 LCDSE2_bits.SEGEN21 +#define SE22 LCDSE2_bits.SE22 +#define SEGEN22 LCDSE2_bits.SEGEN22 +#define SE23 LCDSE2_bits.SE23 +#define SEGEN23 LCDSE2_bits.SEGEN23 + +// ----- LVDCON bits -------------------- +typedef union { + struct { + unsigned char LVDL0:1; + unsigned char LVDL1:1; + unsigned char LVDL2:1; + unsigned char :1; + unsigned char LVDEN:1; + unsigned char IRVST:1; + unsigned char :1; + unsigned char :1; + }; +} __LVDCON_bits_t; +extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; + +#define LVDL0 LVDCON_bits.LVDL0 +#define LVDL1 LVDCON_bits.LVDL1 +#define LVDL2 LVDCON_bits.LVDL2 +#define LVDEN LVDCON_bits.LVDEN +#define IRVST LVDCON_bits.IRVST + +// ----- OPTION_REG bits -------------------- +typedef union { + struct { + unsigned char PS0:1; + unsigned char PS1:1; + unsigned char PS2:1; + unsigned char PSA:1; + unsigned char T0SE:1; + unsigned char T0CS:1; + unsigned char INTEDG:1; + unsigned char NOT_RBPU:1; + }; +} __OPTION_REG_bits_t; +extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; + +#define PS0 OPTION_REG_bits.PS0 +#define PS1 OPTION_REG_bits.PS1 +#define PS2 OPTION_REG_bits.PS2 +#define PSA OPTION_REG_bits.PSA +#define T0SE OPTION_REG_bits.T0SE +#define T0CS OPTION_REG_bits.T0CS +#define INTEDG OPTION_REG_bits.INTEDG +#define NOT_RBPU OPTION_REG_bits.NOT_RBPU + +// ----- OSCCON bits -------------------- +typedef union { + struct { + unsigned char SCS:1; + unsigned char LTS:1; + unsigned char HTS:1; + unsigned char OSTS:1; + unsigned char IRCF0:1; + unsigned char IRCF1:1; + unsigned char IRCF2:1; + unsigned char :1; + }; +} __OSCCON_bits_t; +extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; + +#define SCS OSCCON_bits.SCS +#define LTS OSCCON_bits.LTS +#define HTS OSCCON_bits.HTS +#define OSTS OSCCON_bits.OSTS +#define IRCF0 OSCCON_bits.IRCF0 +#define IRCF1 OSCCON_bits.IRCF1 +#define IRCF2 OSCCON_bits.IRCF2 + +// ----- OSCTUNE bits -------------------- +typedef union { + struct { + unsigned char TUN0:1; + unsigned char TUN1:1; + unsigned char TUN2:1; + unsigned char TUN3:1; + unsigned char TUN4:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __OSCTUNE_bits_t; +extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; + +#define TUN0 OSCTUNE_bits.TUN0 +#define TUN1 OSCTUNE_bits.TUN1 +#define TUN2 OSCTUNE_bits.TUN2 +#define TUN3 OSCTUNE_bits.TUN3 +#define TUN4 OSCTUNE_bits.TUN4 + +// ----- PCON bits -------------------- +typedef union { + struct { + unsigned char NOT_BO:1; + unsigned char NOT_POR:1; + unsigned char :1; + unsigned char :1; + unsigned char SBOREN:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char NOT_BOR:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __PCON_bits_t; +extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; + +#define NOT_BO PCON_bits.NOT_BO +#define NOT_BOR PCON_bits.NOT_BOR +#define NOT_POR PCON_bits.NOT_POR +#define SBOREN PCON_bits.SBOREN + +// ----- PIE1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IE:1; + unsigned char TMR2IE:1; + unsigned char CCP1IE:1; + unsigned char SSPIE:1; + unsigned char TXIE:1; + unsigned char RCIE:1; + unsigned char ADIE:1; + unsigned char EEIE:1; + }; +} __PIE1_bits_t; +extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; + +#define TMR1IE PIE1_bits.TMR1IE +#define TMR2IE PIE1_bits.TMR2IE +#define CCP1IE PIE1_bits.CCP1IE +#define SSPIE PIE1_bits.SSPIE +#define TXIE PIE1_bits.TXIE +#define RCIE PIE1_bits.RCIE +#define ADIE PIE1_bits.ADIE +#define EEIE PIE1_bits.EEIE + +// ----- PIE2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IE:1; + unsigned char :1; + unsigned char LVDIE:1; + unsigned char :1; + unsigned char LCDIE:1; + unsigned char C1IE:1; + unsigned char C2IE:1; + unsigned char OSFIE:1; + }; +} __PIE2_bits_t; +extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; + +#define CCP2IE PIE2_bits.CCP2IE +#define LVDIE PIE2_bits.LVDIE +#define LCDIE PIE2_bits.LCDIE +#define C1IE PIE2_bits.C1IE +#define C2IE PIE2_bits.C2IE +#define OSFIE PIE2_bits.OSFIE + +// ----- PIR1 bits -------------------- +typedef union { + struct { + unsigned char TMR1IF:1; + unsigned char TMR2IF:1; + unsigned char CCP1IF:1; + unsigned char SSPIF:1; + unsigned char TXIF:1; + unsigned char RCIF:1; + unsigned char ADIF:1; + unsigned char EEIF:1; + }; +} __PIR1_bits_t; +extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; + +#define TMR1IF PIR1_bits.TMR1IF +#define TMR2IF PIR1_bits.TMR2IF +#define CCP1IF PIR1_bits.CCP1IF +#define SSPIF PIR1_bits.SSPIF +#define TXIF PIR1_bits.TXIF +#define RCIF PIR1_bits.RCIF +#define ADIF PIR1_bits.ADIF +#define EEIF PIR1_bits.EEIF + +// ----- PIR2 bits -------------------- +typedef union { + struct { + unsigned char CCP2IF:1; + unsigned char :1; + unsigned char LVDIF:1; + unsigned char :1; + unsigned char LCDIF:1; + unsigned char C1IF:1; + unsigned char C2IF:1; + unsigned char OSFIF:1; + }; +} __PIR2_bits_t; +extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; + +#define CCP2IF PIR2_bits.CCP2IF +#define LVDIF PIR2_bits.LVDIF +#define LCDIF PIR2_bits.LCDIF +#define C1IF PIR2_bits.C1IF +#define C2IF PIR2_bits.C2IF +#define OSFIF PIR2_bits.OSFIF + +// ----- RCSTA bits -------------------- +typedef union { + struct { + unsigned char RX9D:1; + unsigned char OERR:1; + unsigned char FERR:1; + unsigned char ADDEN:1; + unsigned char CREN:1; + unsigned char SREN:1; + unsigned char RX9:1; + unsigned char SPEN:1; + }; + struct { + unsigned char RCD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC9:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_RC8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char RC8_9:1; + unsigned char :1; + }; +} __RCSTA_bits_t; +extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; + +#define RX9D RCSTA_bits.RX9D +#define RCD8 RCSTA_bits.RCD8 +#define OERR RCSTA_bits.OERR +#define FERR RCSTA_bits.FERR +#define ADDEN RCSTA_bits.ADDEN +#define CREN RCSTA_bits.CREN +#define SREN RCSTA_bits.SREN +#define RX9 RCSTA_bits.RX9 +#define RC9 RCSTA_bits.RC9 +#define NOT_RC8 RCSTA_bits.NOT_RC8 +#define RC8_9 RCSTA_bits.RC8_9 +#define SPEN RCSTA_bits.SPEN + +// ----- SSPCON bits -------------------- +typedef union { + struct { + unsigned char SSPM0:1; + unsigned char SSPM1:1; + unsigned char SSPM2:1; + unsigned char SSPM3:1; + unsigned char CKP:1; + unsigned char SSPEN:1; + unsigned char SSPOV:1; + unsigned char WCOL:1; + }; +} __SSPCON_bits_t; +extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; + +#define SSPM0 SSPCON_bits.SSPM0 +#define SSPM1 SSPCON_bits.SSPM1 +#define SSPM2 SSPCON_bits.SSPM2 +#define SSPM3 SSPCON_bits.SSPM3 +#define CKP SSPCON_bits.CKP +#define SSPEN SSPCON_bits.SSPEN +#define SSPOV SSPCON_bits.SSPOV +#define WCOL SSPCON_bits.WCOL + +// ----- SSPSTAT bits -------------------- +typedef union { + struct { + unsigned char BF:1; + unsigned char UA:1; + unsigned char R:1; + unsigned char S:1; + unsigned char P:1; + unsigned char D:1; + unsigned char CKE:1; + unsigned char SMP:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char I2C_READ:1; + unsigned char I2C_START:1; + unsigned char I2C_STOP:1; + unsigned char I2C_DATA:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_W:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char NOT_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char R_W:1; + unsigned char :1; + unsigned char :1; + unsigned char D_A:1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char READ_WRITE:1; + unsigned char :1; + unsigned char :1; + unsigned char DATA_ADDRESS:1; + unsigned char :1; + unsigned char :1; + }; +} __SSPSTAT_bits_t; +extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; + +#define BF SSPSTAT_bits.BF +#define UA SSPSTAT_bits.UA +#define R SSPSTAT_bits.R +#define I2C_READ SSPSTAT_bits.I2C_READ +#define NOT_W SSPSTAT_bits.NOT_W +#define NOT_WRITE SSPSTAT_bits.NOT_WRITE +#define R_W SSPSTAT_bits.R_W +#define READ_WRITE SSPSTAT_bits.READ_WRITE +#define S SSPSTAT_bits.S +#define I2C_START SSPSTAT_bits.I2C_START +#define P SSPSTAT_bits.P +#define I2C_STOP SSPSTAT_bits.I2C_STOP +#define D SSPSTAT_bits.D +#define I2C_DATA SSPSTAT_bits.I2C_DATA +#define NOT_A SSPSTAT_bits.NOT_A +#define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS +#define D_A SSPSTAT_bits.D_A +#define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS +#define CKE SSPSTAT_bits.CKE +#define SMP SSPSTAT_bits.SMP + +// ----- STATUS bits -------------------- +typedef union { + struct { + unsigned char C:1; + unsigned char DC:1; + unsigned char Z:1; + unsigned char NOT_PD:1; + unsigned char NOT_TO:1; + unsigned char RP0:1; + unsigned char RP1:1; + unsigned char IRP:1; + }; +} __STATUS_bits_t; +extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + +#define C STATUS_bits.C +#define DC STATUS_bits.DC +#define Z STATUS_bits.Z +#define NOT_PD STATUS_bits.NOT_PD +#define NOT_TO STATUS_bits.NOT_TO +#define RP0 STATUS_bits.RP0 +#define RP1 STATUS_bits.RP1 +#define IRP STATUS_bits.IRP + +// ----- T1CON bits -------------------- +typedef union { + struct { + unsigned char TMR1ON:1; + unsigned char TMR1CS:1; + unsigned char NOT_T1SYNC:1; + unsigned char T1OSCEN:1; + unsigned char T1CKPS0:1; + unsigned char T1CKPS1:1; + unsigned char T1GE:1; + unsigned char T1GINV:1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1INSYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char T1SYNC:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __T1CON_bits_t; +extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + +#define TMR1ON T1CON_bits.TMR1ON +#define TMR1CS T1CON_bits.TMR1CS +#define NOT_T1SYNC T1CON_bits.NOT_T1SYNC +#define T1INSYNC T1CON_bits.T1INSYNC +#define T1SYNC T1CON_bits.T1SYNC +#define T1OSCEN T1CON_bits.T1OSCEN +#define T1CKPS0 T1CON_bits.T1CKPS0 +#define T1CKPS1 T1CON_bits.T1CKPS1 +#define T1GE T1CON_bits.T1GE +#define T1GINV T1CON_bits.T1GINV + +// ----- T2CON bits -------------------- +typedef union { + struct { + unsigned char T2CKPS0:1; + unsigned char T2CKPS1:1; + unsigned char TMR2ON:1; + unsigned char TOUTPS0:1; + unsigned char TOUTPS1:1; + unsigned char TOUTPS2:1; + unsigned char TOUTPS3:1; + unsigned char :1; + }; +} __T2CON_bits_t; +extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + +#define T2CKPS0 T2CON_bits.T2CKPS0 +#define T2CKPS1 T2CON_bits.T2CKPS1 +#define TMR2ON T2CON_bits.TMR2ON +#define TOUTPS0 T2CON_bits.TOUTPS0 +#define TOUTPS1 T2CON_bits.TOUTPS1 +#define TOUTPS2 T2CON_bits.TOUTPS2 +#define TOUTPS3 T2CON_bits.TOUTPS3 + +// ----- TXSTA bits -------------------- +typedef union { + struct { + unsigned char TX9D:1; + unsigned char TRMT:1; + unsigned char BRGH:1; + unsigned char :1; + unsigned char SYNC:1; + unsigned char TXEN:1; + unsigned char TX9:1; + unsigned char CSRC:1; + }; + struct { + unsigned char TXD8:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char NOT_TX8:1; + unsigned char :1; + }; + struct { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TX8_9:1; + unsigned char :1; + }; +} __TXSTA_bits_t; +extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + +#define TX9D TXSTA_bits.TX9D +#define TXD8 TXSTA_bits.TXD8 +#define TRMT TXSTA_bits.TRMT +#define BRGH TXSTA_bits.BRGH +#define SYNC TXSTA_bits.SYNC +#define TXEN TXSTA_bits.TXEN +#define TX9 TXSTA_bits.TX9 +#define NOT_TX8 TXSTA_bits.NOT_TX8 +#define TX8_9 TXSTA_bits.TX8_9 +#define CSRC TXSTA_bits.CSRC + +// ----- VRCON bits -------------------- +typedef union { + struct { + unsigned char VR0:1; + unsigned char VR1:1; + unsigned char VR2:1; + unsigned char VR3:1; + unsigned char :1; + unsigned char VRR:1; + unsigned char :1; + unsigned char VREN:1; + }; +} __VRCON_bits_t; +extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + +#define VR0 VRCON_bits.VR0 +#define VR1 VRCON_bits.VR1 +#define VR2 VRCON_bits.VR2 +#define VR3 VRCON_bits.VR3 +#define VRR VRCON_bits.VRR +#define VREN VRCON_bits.VREN + +// ----- WDTCON bits -------------------- +typedef union { + struct { + unsigned char SWDTEN:1; + unsigned char WDTPS0:1; + unsigned char WDTPS1:1; + unsigned char WDTPS2:1; + unsigned char WDTPS3:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; + struct { + unsigned char SWDTE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + }; +} __WDTCON_bits_t; +extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + +#define SWDTEN WDTCON_bits.SWDTEN +#define SWDTE WDTCON_bits.SWDTE +#define WDTPS0 WDTCON_bits.WDTPS0 +#define WDTPS1 WDTCON_bits.WDTPS1 +#define WDTPS2 WDTCON_bits.WDTPS2 +#define WDTPS3 WDTCON_bits.WDTPS3 + +// ----- WPU bits -------------------- +typedef union { + struct { + unsigned char WPU0:1; + unsigned char WPU1:1; + unsigned char WPU2:1; + unsigned char WPU3:1; + unsigned char WPU4:1; + unsigned char WPU5:1; + unsigned char WPU6:1; + unsigned char WPU7:1; + }; +} __WPU_bits_t; +extern volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits; + +#define WPU0 WPU_bits.WPU0 +#define WPU1 WPU_bits.WPU1 +#define WPU2 WPU_bits.WPU2 +#define WPU3 WPU_bits.WPU3 +#define WPU4 WPU_bits.WPU4 +#define WPU5 WPU_bits.WPU5 +#define WPU6 WPU_bits.WPU6 +#define WPU7 WPU_bits.WPU7 + +// ----- WPUB bits -------------------- +typedef union { + struct { + unsigned char WPUB0:1; + unsigned char WPUB1:1; + unsigned char WPUB2:1; + unsigned char WPUB3:1; + unsigned char WPUB4:1; + unsigned char WPUB5:1; + unsigned char WPUB6:1; + unsigned char WPUB7:1; + }; +} __WPUB_bits_t; +extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + +#define WPUB0 WPUB_bits.WPUB0 +#define WPUB1 WPUB_bits.WPUB1 +#define WPUB2 WPUB_bits.WPUB2 +#define WPUB3 WPUB_bits.WPUB3 +#define WPUB4 WPUB_bits.WPUB4 +#define WPUB5 WPUB_bits.WPUB5 +#define WPUB6 WPUB_bits.WPUB6 +#define WPUB7 WPUB_bits.WPUB7 + +#endif diff --git a/device/lib/Makefile.in b/device/lib/Makefile.in index cce303f8..f9d0b9f8 100644 --- a/device/lib/Makefile.in +++ b/device/lib/Makefile.in @@ -253,7 +253,7 @@ model-pic16: fi objects-pic16: build-dir port-specific-objects-pic16 clean_intermediate-pic16 - cd $(PORTDIR); ls *$(OEXT) > $(PORT).lib + -cd $(PORTDIR); ls *$(OEXT) > $(PORT).lib # yes, we do reuse the *-pic16 rules for pic14 model-pic14: diff --git a/device/lib/pic/Makefile b/device/lib/pic/Makefile index e97c01a4..2493bae8 100644 --- a/device/lib/pic/Makefile +++ b/device/lib/pic/Makefile @@ -25,7 +25,7 @@ all % : else -SUBDIRS = libsdcc +SUBDIRS = libsdcc libdev builddir = build installdir = bin export installdir diff --git a/device/lib/pic/Makefile.subdir b/device/lib/pic/Makefile.subdir index 22848ea9..1d228e37 100644 --- a/device/lib/pic/Makefile.subdir +++ b/device/lib/pic/Makefile.subdir @@ -56,6 +56,8 @@ clean : recurse $(Q)-$(RM) .dummy $(foreach suf,asm d p lst hex cod sym,$(OBJS:.o=.$(suf))) @-echo "dummy" > .dummy $(Q)-$(RM) .dummy $(OBJS) $(LIB_LIB) + $(Q)-$(RM) $(TARGETS) + $(Q)-$(RM) $(addprefix $(topsrcdir)/$(installdir)/,$(notdir $(TARGETS))) $(Q)-[ ! -d "$(topsrcdir)/$(builddir)" ] || $(RMDIR) "$(topsrcdir)/$(builddir)" clean-intermediate : recurse diff --git a/device/lib/pic/NEWS b/device/lib/pic/NEWS index 31d82b28..9f64fa41 100644 --- a/device/lib/pic/NEWS +++ b/device/lib/pic/NEWS @@ -1,3 +1,10 @@ +--- 2006-03-21 Raphael Neider + +Added device specific SFR definitions in libdev/. +From now on all projects should be linked not only with +libsdcc.lib but also with pic$(ARCH).lib where ARCH is +something like p16f877. + --- 2005-10-27 Raphael Neider Generic pointer support routines and additional arithmetic halpers diff --git a/device/lib/pic/configure b/device/lib/pic/configure index 9c6b1cdf..483cd92e 100755 --- a/device/lib/pic/configure +++ b/device/lib/pic/configure @@ -1633,8 +1633,7 @@ fi # Checks for typedefs, structures, and compiler characteristics. # Checks for library functions. - - ac_config_files="$ac_config_files Makefile.common" + ac_config_files="$ac_config_files Makefile.common libdev/Makefile" cat >confcache <<\_ACEOF # This file is a shell script that caches the results of configure @@ -2187,6 +2186,7 @@ do case "$ac_config_target" in # Handling of arguments. "Makefile.common" ) CONFIG_FILES="$CONFIG_FILES Makefile.common" ;; + "libdev/Makefile" ) CONFIG_FILES="$CONFIG_FILES libdev/Makefile" ;; *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5 echo "$as_me: error: invalid argument: $ac_config_target" >&2;} { (exit 1); exit 1; }; };; diff --git a/device/lib/pic/configure.in b/device/lib/pic/configure.in index 2465fa75..f0928a23 100644 --- a/device/lib/pic/configure.in +++ b/device/lib/pic/configure.in @@ -43,6 +43,6 @@ AC_PROG_MAKE_SET # Checks for typedefs, structures, and compiler characteristics. # Checks for library functions. - -AC_CONFIG_FILES([Makefile.common]) +AC_CONFIG_FILES([Makefile.common + libdev/Makefile]) AC_OUTPUT diff --git a/device/lib/pic/libdev/Makefile.in b/device/lib/pic/libdev/Makefile.in new file mode 100644 index 00000000..a4291536 --- /dev/null +++ b/device/lib/pic/libdev/Makefile.in @@ -0,0 +1,41 @@ +SDCC_BASE = ../../../.. +INSTALL_DIR = ../bin + +CC = $(SDCC_BASE)/bin/sdcc +LIB = @GPLIB@ +CP = @CP@ +RM = @RM@ +RMDIR = @RMDIR@ + +CPPFLAGS = -I../../../include/pic + +C_SRC = $(wildcard pic16*.c) +OBJS = $(C_SRC:.c=.o) +LIBS = $(addprefix $(INSTALL_DIR)/,$(OBJS:.o=.lib)) + +all : $(LIBS) + +ifeq (0,1) +# useful while fixing .inc files +GPUTILS = /opt/modules/gputils-0.13.3/share/gputils +pic%.c : $(GPUTILS)/header/p%.inc + -$(SDCC_BASE)/support/scripts/inc2h.pl $* $(GPUTILS) \ + > $(SDCC_BASE)/device/include/pic/pic$*.h +endif + +pic%.o : pic%.c + -$(CC) $(CPPFLAGS) $(CFLAGS) -mpic14 -p$* -o "$@" -c "$<" + +$(INSTALL_DIR)/%.lib : %.o + -$(LIB) -c "$@" "$<"; + +install : all + +clean : clean-intermediate + $(Q)-$(RM) *.asm + $(Q)-$(RM) $(OBJS) $(LIBS) + $(Q)-$(RMDIR) ../build/libdev + +clean-intermediate : + $(Q)-$(RM) *.lst *.d *.adb + diff --git a/device/lib/pic/libdev/p16c620a.c b/device/lib/pic/libdev/p16c620a.c new file mode 100644 index 00000000..e69de29b diff --git a/device/lib/pic/libdev/pic16c432.c b/device/lib/pic/libdev/pic16c432.c new file mode 100644 index 00000000..d46b443b --- /dev/null +++ b/device/lib/pic/libdev/pic16c432.c @@ -0,0 +1,40 @@ +/* Register definitions for pic16c432. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (LININTF_ADDR) LININTF; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LININTF_bits_t __at(LININTF_ADDR) LININTF_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16c433.c b/device/lib/pic/libdev/pic16c433.c new file mode 100644 index 00000000..e8e1b6f5 --- /dev/null +++ b/device/lib/pic/libdev/pic16c433.c @@ -0,0 +1,38 @@ +/* Register definitions for pic16c433. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (GPIO_ADDR) GPIO; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISIO_ADDR) TRISIO; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCAL_ADDR) OSCCAL; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16c554.c b/device/lib/pic/libdev/pic16c554.c new file mode 100644 index 00000000..bacf1dd3 --- /dev/null +++ b/device/lib/pic/libdev/pic16c554.c @@ -0,0 +1,29 @@ +/* Register definitions for pic16c554. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PCON_ADDR) PCON; + +// +// bitfield definitions +// +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16c557.c b/device/lib/pic/libdev/pic16c557.c new file mode 100644 index 00000000..9dc46e07 --- /dev/null +++ b/device/lib/pic/libdev/pic16c557.c @@ -0,0 +1,31 @@ +/* Register definitions for pic16c557. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PCON_ADDR) PCON; + +// +// bitfield definitions +// +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16c558.c b/device/lib/pic/libdev/pic16c558.c new file mode 100644 index 00000000..b17bb7d6 --- /dev/null +++ b/device/lib/pic/libdev/pic16c558.c @@ -0,0 +1,29 @@ +/* Register definitions for pic16c558. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PCON_ADDR) PCON; + +// +// bitfield definitions +// +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16c62.c b/device/lib/pic/libdev/pic16c62.c new file mode 100644 index 00000000..25f63aa9 --- /dev/null +++ b/device/lib/pic/libdev/pic16c62.c @@ -0,0 +1,53 @@ +/* Register definitions for pic16c62. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; + +// +// bitfield definitions +// +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + diff --git a/device/lib/pic/libdev/pic16c620.c b/device/lib/pic/libdev/pic16c620.c new file mode 100644 index 00000000..32fc0f8f --- /dev/null +++ b/device/lib/pic/libdev/pic16c620.c @@ -0,0 +1,37 @@ +/* Register definitions for pic16c620. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16c620a.c b/device/lib/pic/libdev/pic16c620a.c new file mode 100644 index 00000000..2c84b1cc --- /dev/null +++ b/device/lib/pic/libdev/pic16c620a.c @@ -0,0 +1,37 @@ +/* Register definitions for pic16c620a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16c621.c b/device/lib/pic/libdev/pic16c621.c new file mode 100644 index 00000000..d497b6c4 --- /dev/null +++ b/device/lib/pic/libdev/pic16c621.c @@ -0,0 +1,37 @@ +/* Register definitions for pic16c621. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16c621a.c b/device/lib/pic/libdev/pic16c621a.c new file mode 100644 index 00000000..febeb048 --- /dev/null +++ b/device/lib/pic/libdev/pic16c621a.c @@ -0,0 +1,37 @@ +/* Register definitions for pic16c621a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16c622.c b/device/lib/pic/libdev/pic16c622.c new file mode 100644 index 00000000..3b9cb7cb --- /dev/null +++ b/device/lib/pic/libdev/pic16c622.c @@ -0,0 +1,37 @@ +/* Register definitions for pic16c622. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16c622a.c b/device/lib/pic/libdev/pic16c622a.c new file mode 100644 index 00000000..65b54cea --- /dev/null +++ b/device/lib/pic/libdev/pic16c622a.c @@ -0,0 +1,37 @@ +/* Register definitions for pic16c622a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16c63a.c b/device/lib/pic/libdev/pic16c63a.c new file mode 100644 index 00000000..595fc7e6 --- /dev/null +++ b/device/lib/pic/libdev/pic16c63a.c @@ -0,0 +1,68 @@ +/* Register definitions for pic16c63a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; + +// +// bitfield definitions +// +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16c65b.c b/device/lib/pic/libdev/pic16c65b.c new file mode 100644 index 00000000..eca7a808 --- /dev/null +++ b/device/lib/pic/libdev/pic16c65b.c @@ -0,0 +1,73 @@ +/* Register definitions for pic16c65b. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; + +// +// bitfield definitions +// +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16c71.c b/device/lib/pic/libdev/pic16c71.c new file mode 100644 index 00000000..809c3663 --- /dev/null +++ b/device/lib/pic/libdev/pic16c71.c @@ -0,0 +1,32 @@ +/* Register definitions for pic16c71. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16c710.c b/device/lib/pic/libdev/pic16c710.c new file mode 100644 index 00000000..687905ad --- /dev/null +++ b/device/lib/pic/libdev/pic16c710.c @@ -0,0 +1,34 @@ +/* Register definitions for pic16c710. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PCON_ADDR) PCON; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16c711.c b/device/lib/pic/libdev/pic16c711.c new file mode 100644 index 00000000..d4a55c35 --- /dev/null +++ b/device/lib/pic/libdev/pic16c711.c @@ -0,0 +1,34 @@ +/* Register definitions for pic16c711. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PCON_ADDR) PCON; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16c715.c b/device/lib/pic/libdev/pic16c715.c new file mode 100644 index 00000000..e6fd4a56 --- /dev/null +++ b/device/lib/pic/libdev/pic16c715.c @@ -0,0 +1,38 @@ +/* Register definitions for pic16c715. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16c717.c b/device/lib/pic/libdev/pic16c717.c new file mode 100644 index 00000000..d64af4db --- /dev/null +++ b/device/lib/pic/libdev/pic16c717.c @@ -0,0 +1,77 @@ +/* Register definitions for pic16c717. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (P1DEL_ADDR) P1DEL; +sfr __at (REFCON_ADDR) REFCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATL_ADDR) PMDATL; +sfr __at (PMADRL_ADDR) PMADRL; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + diff --git a/device/lib/pic/libdev/pic16c72.c b/device/lib/pic/libdev/pic16c72.c new file mode 100644 index 00000000..0945cff2 --- /dev/null +++ b/device/lib/pic/libdev/pic16c72.c @@ -0,0 +1,58 @@ +/* Register definitions for pic16c72. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + diff --git a/device/lib/pic/libdev/pic16c73b.c b/device/lib/pic/libdev/pic16c73b.c new file mode 100644 index 00000000..9d3e79e7 --- /dev/null +++ b/device/lib/pic/libdev/pic16c73b.c @@ -0,0 +1,73 @@ +/* Register definitions for pic16c73b. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16c745.c b/device/lib/pic/libdev/pic16c745.c new file mode 100644 index 00000000..e0801fb8 --- /dev/null +++ b/device/lib/pic/libdev/pic16c745.c @@ -0,0 +1,101 @@ +/* Register definitions for pic16c745. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (UIR_ADDR) UIR; +sfr __at (UIE_ADDR) UIE; +sfr __at (UEIR_ADDR) UEIR; +sfr __at (UEIE_ADDR) UEIE; +sfr __at (USTAT_ADDR) USTAT; +sfr __at (UCTRL_ADDR) UCTRL; +sfr __at (UADDR_ADDR) UADDR; +sfr __at (USWSTAT_ADDR) USWSTAT; +sfr __at (UEP0_ADDR) UEP0; +sfr __at (UEP1_ADDR) UEP1; +sfr __at (UEP2_ADDR) UEP2; +sfr __at (BD0OST_ADDR) BD0OST; +sfr __at (BD0OBC_ADDR) BD0OBC; +sfr __at (BD0OAL_ADDR) BD0OAL; +sfr __at (BD0IST_ADDR) BD0IST; +sfr __at (BD0IBC_ADDR) BD0IBC; +sfr __at (BD0IAL_ADDR) BD0IAL; +sfr __at (BD1OST_ADDR) BD1OST; +sfr __at (BD1OBC_ADDR) BD1OBC; +sfr __at (BD1OAL_ADDR) BD1OAL; +sfr __at (BD1IST_ADDR) BD1IST; +sfr __at (BD1IBC_ADDR) BD1IBC; +sfr __at (BD1IAL_ADDR) BD1IAL; +sfr __at (BD2OST_ADDR) BD2OST; +sfr __at (BD2OBC_ADDR) BD2OBC; +sfr __at (BD2OAL_ADDR) BD2OAL; +sfr __at (BD2IST_ADDR) BD2IST; +sfr __at (BD2IBC_ADDR) BD2IBC; +sfr __at (BD2IAL_ADDR) BD2IAL; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits; +volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits; +volatile __UEP2_bits_t __at(UEP2_ADDR) UEP2_bits; +volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits; +volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits; + diff --git a/device/lib/pic/libdev/pic16c74b.c b/device/lib/pic/libdev/pic16c74b.c new file mode 100644 index 00000000..ed2a4155 --- /dev/null +++ b/device/lib/pic/libdev/pic16c74b.c @@ -0,0 +1,78 @@ +/* Register definitions for pic16c74b. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16c765.c b/device/lib/pic/libdev/pic16c765.c new file mode 100644 index 00000000..9ae79133 --- /dev/null +++ b/device/lib/pic/libdev/pic16c765.c @@ -0,0 +1,106 @@ +/* Register definitions for pic16c765. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (UIR_ADDR) UIR; +sfr __at (UIE_ADDR) UIE; +sfr __at (UEIR_ADDR) UEIR; +sfr __at (UEIE_ADDR) UEIE; +sfr __at (USTAT_ADDR) USTAT; +sfr __at (UCTRL_ADDR) UCTRL; +sfr __at (UADDR_ADDR) UADDR; +sfr __at (USWSTAT_ADDR) USWSTAT; +sfr __at (UEP0_ADDR) UEP0; +sfr __at (UEP1_ADDR) UEP1; +sfr __at (UEP2_ADDR) UEP2; +sfr __at (BD0OST_ADDR) BD0OST; +sfr __at (BD0OBC_ADDR) BD0OBC; +sfr __at (BD0OAL_ADDR) BD0OAL; +sfr __at (BD0IST_ADDR) BD0IST; +sfr __at (BD0IBC_ADDR) BD0IBC; +sfr __at (BD0IAL_ADDR) BD0IAL; +sfr __at (BD1OST_ADDR) BD1OST; +sfr __at (BD1OBC_ADDR) BD1OBC; +sfr __at (BD1OAL_ADDR) BD1OAL; +sfr __at (BD1IST_ADDR) BD1IST; +sfr __at (BD1IBC_ADDR) BD1IBC; +sfr __at (BD1IAL_ADDR) BD1IAL; +sfr __at (BD2OST_ADDR) BD2OST; +sfr __at (BD2OBC_ADDR) BD2OBC; +sfr __at (BD2OAL_ADDR) BD2OAL; +sfr __at (BD2IST_ADDR) BD2IST; +sfr __at (BD2IBC_ADDR) BD2IBC; +sfr __at (BD2IAL_ADDR) BD2IAL; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits; +volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits; +volatile __UEP2_bits_t __at(UEP2_ADDR) UEP2_bits; +volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits; +volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits; + diff --git a/device/lib/pic/libdev/pic16c770.c b/device/lib/pic/libdev/pic16c770.c new file mode 100644 index 00000000..cc0e913c --- /dev/null +++ b/device/lib/pic/libdev/pic16c770.c @@ -0,0 +1,77 @@ +/* Register definitions for pic16c770. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (P1DEL_ADDR) P1DEL; +sfr __at (REFCON_ADDR) REFCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATL_ADDR) PMDATL; +sfr __at (PMADRL_ADDR) PMADRL; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + diff --git a/device/lib/pic/libdev/pic16c771.c b/device/lib/pic/libdev/pic16c771.c new file mode 100644 index 00000000..45120f93 --- /dev/null +++ b/device/lib/pic/libdev/pic16c771.c @@ -0,0 +1,77 @@ +/* Register definitions for pic16c771. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (P1DEL_ADDR) P1DEL; +sfr __at (REFCON_ADDR) REFCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATL_ADDR) PMDATL; +sfr __at (PMADRL_ADDR) PMADRL; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + diff --git a/device/lib/pic/libdev/pic16c773.c b/device/lib/pic/libdev/pic16c773.c new file mode 100644 index 00000000..69f82f27 --- /dev/null +++ b/device/lib/pic/libdev/pic16c773.c @@ -0,0 +1,80 @@ +/* Register definitions for pic16c773. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (REFCON_ADDR) REFCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16c774.c b/device/lib/pic/libdev/pic16c774.c new file mode 100644 index 00000000..ce34d4f4 --- /dev/null +++ b/device/lib/pic/libdev/pic16c774.c @@ -0,0 +1,85 @@ +/* Register definitions for pic16c774. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (REFCON_ADDR) REFCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16c781.c b/device/lib/pic/libdev/pic16c781.c new file mode 100644 index 00000000..d9ff6b29 --- /dev/null +++ b/device/lib/pic/libdev/pic16c781.c @@ -0,0 +1,72 @@ +/* Register definitions for pic16c781. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (REFCON_ADDR) REFCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATL_ADDR) PMDATL; +sfr __at (PMADRL_ADDR) PMADRL; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (CALCON_ADDR) CALCON; +sfr __at (PSMCCON0_ADDR) PSMCCON0; +sfr __at (PSMCCON1_ADDR) PSMCCON1; +sfr __at (CM1CON0_ADDR) CM1CON0; +sfr __at (CM2CON0_ADDR) CM2CON0; +sfr __at (CM2CON1_ADDR) CM2CON1; +sfr __at (OPACON_ADDR) OPACON; +sfr __at (DAC_ADDR) DAC; +sfr __at (DACON0_ADDR) DACON0; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CALCON_bits_t __at(CALCON_ADDR) CALCON_bits; +volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; +volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; +volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; +volatile __DACON0_bits_t __at(DACON0_ADDR) DACON0_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPACON_bits_t __at(OPACON_ADDR) OPACON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __PSMCCON0_bits_t __at(PSMCCON0_ADDR) PSMCCON0_bits; +volatile __PSMCCON1_bits_t __at(PSMCCON1_ADDR) PSMCCON1_bits; +volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + diff --git a/device/lib/pic/libdev/pic16c782.c b/device/lib/pic/libdev/pic16c782.c new file mode 100644 index 00000000..ebd00713 --- /dev/null +++ b/device/lib/pic/libdev/pic16c782.c @@ -0,0 +1,72 @@ +/* Register definitions for pic16c782. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (REFCON_ADDR) REFCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATL_ADDR) PMDATL; +sfr __at (PMADRL_ADDR) PMADRL; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (CALCON_ADDR) CALCON; +sfr __at (PSMCCON0_ADDR) PSMCCON0; +sfr __at (PSMCCON1_ADDR) PSMCCON1; +sfr __at (CM1CON0_ADDR) CM1CON0; +sfr __at (CM2CON0_ADDR) CM2CON0; +sfr __at (CM2CON1_ADDR) CM2CON1; +sfr __at (OPACON_ADDR) OPACON; +sfr __at (DAC_ADDR) DAC; +sfr __at (DACON0_ADDR) DACON0; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CALCON_bits_t __at(CALCON_ADDR) CALCON_bits; +volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; +volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; +volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; +volatile __DACON0_bits_t __at(DACON0_ADDR) DACON0_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPACON_bits_t __at(OPACON_ADDR) OPACON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __PSMCCON0_bits_t __at(PSMCCON0_ADDR) PSMCCON0_bits; +volatile __PSMCCON1_bits_t __at(PSMCCON1_ADDR) PSMCCON1_bits; +volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; + diff --git a/device/lib/pic/libdev/pic16c925.c b/device/lib/pic/libdev/pic16c925.c new file mode 100644 index 00000000..362b47d7 --- /dev/null +++ b/device/lib/pic/libdev/pic16c925.c @@ -0,0 +1,96 @@ +/* Register definitions for pic16c925. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PORTF_ADDR) PORTF; +sfr __at (PORTG_ADDR) PORTG; +sfr __at (PMCON1_ADDR) PMCON1; +sfr __at (LCDSE_ADDR) LCDSE; +sfr __at (LCDPS_ADDR) LCDPS; +sfr __at (LCDCON_ADDR) LCDCON; +sfr __at (LCDD00_ADDR) LCDD00; +sfr __at (LCDD01_ADDR) LCDD01; +sfr __at (LCDD02_ADDR) LCDD02; +sfr __at (LCDD03_ADDR) LCDD03; +sfr __at (LCDD04_ADDR) LCDD04; +sfr __at (LCDD05_ADDR) LCDD05; +sfr __at (LCDD06_ADDR) LCDD06; +sfr __at (LCDD07_ADDR) LCDD07; +sfr __at (LCDD08_ADDR) LCDD08; +sfr __at (LCDD09_ADDR) LCDD09; +sfr __at (LCDD10_ADDR) LCDD10; +sfr __at (LCDD11_ADDR) LCDD11; +sfr __at (LCDD12_ADDR) LCDD12; +sfr __at (LCDD13_ADDR) LCDD13; +sfr __at (LCDD14_ADDR) LCDD14; +sfr __at (LCDD15_ADDR) LCDD15; +sfr __at (TRISF_ADDR) TRISF; +sfr __at (TRISG_ADDR) TRISG; +sfr __at (PMDATA_ADDR) PMDATA; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADR_ADDR) PMADR; +sfr __at (PMADRH_ADDR) PMADRH; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; +volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; +volatile __LCDSE_bits_t __at(LCDSE_ADDR) LCDSE_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + diff --git a/device/lib/pic/libdev/pic16c926.c b/device/lib/pic/libdev/pic16c926.c new file mode 100644 index 00000000..7eb9b3a1 --- /dev/null +++ b/device/lib/pic/libdev/pic16c926.c @@ -0,0 +1,96 @@ +/* Register definitions for pic16c926. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PORTF_ADDR) PORTF; +sfr __at (PORTG_ADDR) PORTG; +sfr __at (PMCON1_ADDR) PMCON1; +sfr __at (LCDSE_ADDR) LCDSE; +sfr __at (LCDPS_ADDR) LCDPS; +sfr __at (LCDCON_ADDR) LCDCON; +sfr __at (LCDD00_ADDR) LCDD00; +sfr __at (LCDD01_ADDR) LCDD01; +sfr __at (LCDD02_ADDR) LCDD02; +sfr __at (LCDD03_ADDR) LCDD03; +sfr __at (LCDD04_ADDR) LCDD04; +sfr __at (LCDD05_ADDR) LCDD05; +sfr __at (LCDD06_ADDR) LCDD06; +sfr __at (LCDD07_ADDR) LCDD07; +sfr __at (LCDD08_ADDR) LCDD08; +sfr __at (LCDD09_ADDR) LCDD09; +sfr __at (LCDD10_ADDR) LCDD10; +sfr __at (LCDD11_ADDR) LCDD11; +sfr __at (LCDD12_ADDR) LCDD12; +sfr __at (LCDD13_ADDR) LCDD13; +sfr __at (LCDD14_ADDR) LCDD14; +sfr __at (LCDD15_ADDR) LCDD15; +sfr __at (TRISF_ADDR) TRISF; +sfr __at (TRISG_ADDR) TRISG; +sfr __at (PMDATA_ADDR) PMDATA; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADR_ADDR) PMADR; +sfr __at (PMADRH_ADDR) PMADRH; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; +volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; +volatile __LCDSE_bits_t __at(LCDSE_ADDR) LCDSE_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; + diff --git a/device/lib/pic/libdev/pic16f505.c b/device/lib/pic/libdev/pic16f505.c new file mode 100644 index 00000000..e418e78f --- /dev/null +++ b/device/lib/pic/libdev/pic16f505.c @@ -0,0 +1,24 @@ +/* Register definitions for pic16f505. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (OSCCAL_ADDR) OSCCAL; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (OPTION_REG_ADDR) OPTION_REG; + +// +// bitfield definitions +// +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16f627.c b/device/lib/pic/libdev/pic16f627.c new file mode 100644 index 00000000..3b557b32 --- /dev/null +++ b/device/lib/pic/libdev/pic16f627.c @@ -0,0 +1,61 @@ +/* Register definitions for pic16f627. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16f627a.c b/device/lib/pic/libdev/pic16f627a.c new file mode 100644 index 00000000..fc92320a --- /dev/null +++ b/device/lib/pic/libdev/pic16f627a.c @@ -0,0 +1,61 @@ +/* Register definitions for pic16f627a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16f628.c b/device/lib/pic/libdev/pic16f628.c new file mode 100644 index 00000000..c980c331 --- /dev/null +++ b/device/lib/pic/libdev/pic16f628.c @@ -0,0 +1,61 @@ +/* Register definitions for pic16f628. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16f628a.c b/device/lib/pic/libdev/pic16f628a.c new file mode 100644 index 00000000..1ad3a4ab --- /dev/null +++ b/device/lib/pic/libdev/pic16f628a.c @@ -0,0 +1,61 @@ +/* Register definitions for pic16f628a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16f630.c b/device/lib/pic/libdev/pic16f630.c new file mode 100644 index 00000000..289f37d4 --- /dev/null +++ b/device/lib/pic/libdev/pic16f630.c @@ -0,0 +1,52 @@ +/* Register definitions for pic16f630. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCAL_ADDR) OSCCAL; +sfr __at (WPUA_ADDR) WPUA; +sfr __at (WPU_ADDR) WPU; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (IOC_ADDR) IOC; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEDAT_ADDR) EEDAT; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16f636.c b/device/lib/pic/libdev/pic16f636.c new file mode 100644 index 00000000..e0cab903 --- /dev/null +++ b/device/lib/pic/libdev/pic16f636.c @@ -0,0 +1,62 @@ +/* Register definitions for pic16f636. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (CMCON0_ADDR) CMCON0; +sfr __at (CMCON1_ADDR) CMCON1; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (WPUDA_ADDR) WPUDA; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (WDA_ADDR) WDA; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (EEDAT_ADDR) EEDAT; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (CRCON_ADDR) CRCON; +sfr __at (CRDAT0_ADDR) CRDAT0; +sfr __at (CRDAT1_ADDR) CRDAT1; +sfr __at (CRDAT2_ADDR) CRDAT2; +sfr __at (CRDAT3_ADDR) CRDAT3; + +// +// bitfield definitions +// +volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; +volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + diff --git a/device/lib/pic/libdev/pic16f639.c b/device/lib/pic/libdev/pic16f639.c new file mode 100644 index 00000000..c7013b68 --- /dev/null +++ b/device/lib/pic/libdev/pic16f639.c @@ -0,0 +1,62 @@ +/* Register definitions for pic16f639. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (CMCON0_ADDR) CMCON0; +sfr __at (CMCON1_ADDR) CMCON1; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (WPUDA_ADDR) WPUDA; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (WDA_ADDR) WDA; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (EEDAT_ADDR) EEDAT; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (CRCON_ADDR) CRCON; +sfr __at (CRDAT0_ADDR) CRDAT0; +sfr __at (CRDAT1_ADDR) CRDAT1; +sfr __at (CRDAT2_ADDR) CRDAT2; +sfr __at (CRDAT3_ADDR) CRDAT3; + +// +// bitfield definitions +// +volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; +volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + diff --git a/device/lib/pic/libdev/pic16f648a.c b/device/lib/pic/libdev/pic16f648a.c new file mode 100644 index 00000000..32f7009e --- /dev/null +++ b/device/lib/pic/libdev/pic16f648a.c @@ -0,0 +1,61 @@ +/* Register definitions for pic16f648a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (VRCON_ADDR) VRCON; + +// +// bitfield definitions +// +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16f676.c b/device/lib/pic/libdev/pic16f676.c new file mode 100644 index 00000000..0617afad --- /dev/null +++ b/device/lib/pic/libdev/pic16f676.c @@ -0,0 +1,58 @@ +/* Register definitions for pic16f676. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCAL_ADDR) OSCCAL; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (WPU_ADDR) WPU; +sfr __at (WPUA_ADDR) WPUA; +sfr __at (IOC_ADDR) IOC; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEDAT_ADDR) EEDAT; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16f684.c b/device/lib/pic/libdev/pic16f684.c new file mode 100644 index 00000000..c0aaf195 --- /dev/null +++ b/device/lib/pic/libdev/pic16f684.c @@ -0,0 +1,76 @@ +/* Register definitions for pic16f684. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (PWM1CON_ADDR) PWM1CON; +sfr __at (ECCPAS_ADDR) ECCPAS; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (CMCON0_ADDR) CMCON0; +sfr __at (CMCON1_ADDR) CMCON1; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (PR2_ADDR) PR2; +sfr __at (WPU_ADDR) WPU; +sfr __at (WPUA_ADDR) WPUA; +sfr __at (IOC_ADDR) IOC; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (EEDAT_ADDR) EEDAT; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; +volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; +volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + diff --git a/device/lib/pic/libdev/pic16f685.c b/device/lib/pic/libdev/pic16f685.c new file mode 100644 index 00000000..12181047 --- /dev/null +++ b/device/lib/pic/libdev/pic16f685.c @@ -0,0 +1,94 @@ +/* Register definitions for pic16f685. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (PWM1CON_ADDR) PWM1CON; +sfr __at (ECCPAS_ADDR) ECCPAS; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (PR2_ADDR) PR2; +sfr __at (WPU_ADDR) WPU; +sfr __at (WPUA_ADDR) WPUA; +sfr __at (IOC_ADDR) IOC; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (CM1CON0_ADDR) CM1CON0; +sfr __at (CM2CON0_ADDR) CM2CON0; +sfr __at (CM2CON1_ADDR) CM2CON1; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ANSELH_ADDR) ANSELH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (PSTRCON_ADDR) PSTRCON; +sfr __at (SRCON_ADDR) SRCON; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; +volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; +volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; +volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits; +volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; +volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; +volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + diff --git a/device/lib/pic/libdev/pic16f687.c b/device/lib/pic/libdev/pic16f687.c new file mode 100644 index 00000000..ccbdfc5b --- /dev/null +++ b/device/lib/pic/libdev/pic16f687.c @@ -0,0 +1,101 @@ +/* Register definitions for pic16f687. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (MSK_ADDR) MSK; +sfr __at (SSPMSK_ADDR) SSPMSK; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPU_ADDR) WPU; +sfr __at (WPUA_ADDR) WPUA; +sfr __at (IOC_ADDR) IOC; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (SPBRGH_ADDR) SPBRGH; +sfr __at (BAUDCTL_ADDR) BAUDCTL; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (CM1CON0_ADDR) CM1CON0; +sfr __at (CM2CON0_ADDR) CM2CON0; +sfr __at (CM2CON1_ADDR) CM2CON1; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ANSELH_ADDR) ANSELH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (SRCON_ADDR) SRCON; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits; +volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; +volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; +volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits; +volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits; +volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; +volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; +volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + diff --git a/device/lib/pic/libdev/pic16f688.c b/device/lib/pic/libdev/pic16f688.c new file mode 100644 index 00000000..6c1dfeaf --- /dev/null +++ b/device/lib/pic/libdev/pic16f688.c @@ -0,0 +1,75 @@ +/* Register definitions for pic16f688. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (BAUDCTL_ADDR) BAUDCTL; +sfr __at (SPBRGH_ADDR) SPBRGH; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (CMCON0_ADDR) CMCON0; +sfr __at (CMCON1_ADDR) CMCON1; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (WPU_ADDR) WPU; +sfr __at (WPUA_ADDR) WPUA; +sfr __at (IOC_ADDR) IOC; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (EEDAT_ADDR) EEDAT; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits; +volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; +volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; + diff --git a/device/lib/pic/libdev/pic16f689.c b/device/lib/pic/libdev/pic16f689.c new file mode 100644 index 00000000..3aed3f2f --- /dev/null +++ b/device/lib/pic/libdev/pic16f689.c @@ -0,0 +1,101 @@ +/* Register definitions for pic16f689. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (MSK_ADDR) MSK; +sfr __at (SSPMSK_ADDR) SSPMSK; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPU_ADDR) WPU; +sfr __at (WPUA_ADDR) WPUA; +sfr __at (IOC_ADDR) IOC; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (SPBRGH_ADDR) SPBRGH; +sfr __at (BAUDCTL_ADDR) BAUDCTL; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (CM1CON0_ADDR) CM1CON0; +sfr __at (CM2CON0_ADDR) CM2CON0; +sfr __at (CM2CON1_ADDR) CM2CON1; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ANSELH_ADDR) ANSELH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (SRCON_ADDR) SRCON; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits; +volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; +volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; +volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits; +volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits; +volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; +volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; +volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + diff --git a/device/lib/pic/libdev/pic16f690.c b/device/lib/pic/libdev/pic16f690.c new file mode 100644 index 00000000..b0d8b4b4 --- /dev/null +++ b/device/lib/pic/libdev/pic16f690.c @@ -0,0 +1,114 @@ +/* Register definitions for pic16f690. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (PWM1CON_ADDR) PWM1CON; +sfr __at (ECCPAS_ADDR) ECCPAS; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (MSK_ADDR) MSK; +sfr __at (SSPMSK_ADDR) SSPMSK; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPU_ADDR) WPU; +sfr __at (WPUA_ADDR) WPUA; +sfr __at (IOC_ADDR) IOC; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (SPBRGH_ADDR) SPBRGH; +sfr __at (BAUDCTL_ADDR) BAUDCTL; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (CM1CON0_ADDR) CM1CON0; +sfr __at (CM2CON0_ADDR) CM2CON0; +sfr __at (CM2CON1_ADDR) CM2CON1; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ANSELH_ADDR) ANSELH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (PSTRCON_ADDR) PSTRCON; +sfr __at (SRCON_ADDR) SRCON; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits; +volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits; +volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits; +volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits; +volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits; +volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; +volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; +volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + diff --git a/device/lib/pic/libdev/pic16f716.c b/device/lib/pic/libdev/pic16f716.c new file mode 100644 index 00000000..b3bcd1df --- /dev/null +++ b/device/lib/pic/libdev/pic16f716.c @@ -0,0 +1,58 @@ +/* Register definitions for pic16f716. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (DATACCP_ADDR) DATACCP; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (PWM1CON_ADDR) PWM1CON; +sfr __at (ECCPAS_ADDR) ECCPAS; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISCP_ADDR) TRISCP; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (ADCON1_ADDR) ADCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits; +volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits; + diff --git a/device/lib/pic/libdev/pic16f72.c b/device/lib/pic/libdev/pic16f72.c new file mode 100644 index 00000000..82406c98 --- /dev/null +++ b/device/lib/pic/libdev/pic16f72.c @@ -0,0 +1,64 @@ +/* Register definitions for pic16f72. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATL_ADDR) PMDATL; +sfr __at (PMADRL_ADDR) PMADRL; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + diff --git a/device/lib/pic/libdev/pic16f73.c b/device/lib/pic/libdev/pic16f73.c new file mode 100644 index 00000000..872f835a --- /dev/null +++ b/device/lib/pic/libdev/pic16f73.c @@ -0,0 +1,79 @@ +/* Register definitions for pic16f73. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATA_ADDR) PMDATA; +sfr __at (PMADR_ADDR) PMADR; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f737.c b/device/lib/pic/libdev/pic16f737.c new file mode 100644 index 00000000..b59c6f9e --- /dev/null +++ b/device/lib/pic/libdev/pic16f737.c @@ -0,0 +1,105 @@ +/* Register definitions for pic16f737. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (CCPR3L_ADDR) CCPR3L; +sfr __at (CCPR3H_ADDR) CCPR3H; +sfr __at (CCP3CON_ADDR) CCP3CON; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON2_ADDR) ADCON2; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (CVRCON_ADDR) CVRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (PMDATA_ADDR) PMDATA; +sfr __at (PMADR_ADDR) PMADR; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + diff --git a/device/lib/pic/libdev/pic16f74.c b/device/lib/pic/libdev/pic16f74.c new file mode 100644 index 00000000..c9c46f51 --- /dev/null +++ b/device/lib/pic/libdev/pic16f74.c @@ -0,0 +1,84 @@ +/* Register definitions for pic16f74. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATA_ADDR) PMDATA; +sfr __at (PMADR_ADDR) PMADR; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f76.c b/device/lib/pic/libdev/pic16f76.c new file mode 100644 index 00000000..61b41dc6 --- /dev/null +++ b/device/lib/pic/libdev/pic16f76.c @@ -0,0 +1,79 @@ +/* Register definitions for pic16f76. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATA_ADDR) PMDATA; +sfr __at (PMADR_ADDR) PMADR; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f767.c b/device/lib/pic/libdev/pic16f767.c new file mode 100644 index 00000000..918ba927 --- /dev/null +++ b/device/lib/pic/libdev/pic16f767.c @@ -0,0 +1,103 @@ +/* Register definitions for pic16f767. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (CCPR3L_ADDR) CCPR3L; +sfr __at (CCPR3H_ADDR) CCPR3H; +sfr __at (CCP3CON_ADDR) CCP3CON; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON2_ADDR) ADCON2; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (CVRCON_ADDR) CVRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (PMDATA_ADDR) PMDATA; +sfr __at (PMADR_ADDR) PMADR; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + diff --git a/device/lib/pic/libdev/pic16f77.c b/device/lib/pic/libdev/pic16f77.c new file mode 100644 index 00000000..a22b0f30 --- /dev/null +++ b/device/lib/pic/libdev/pic16f77.c @@ -0,0 +1,84 @@ +/* Register definitions for pic16f77. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRES_ADDR) ADRES; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PMDATA_ADDR) PMDATA; +sfr __at (PMADR_ADDR) PMADR; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f777.c b/device/lib/pic/libdev/pic16f777.c new file mode 100644 index 00000000..2f7de0f2 --- /dev/null +++ b/device/lib/pic/libdev/pic16f777.c @@ -0,0 +1,105 @@ +/* Register definitions for pic16f777. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (CCPR3L_ADDR) CCPR3L; +sfr __at (CCPR3H_ADDR) CCPR3H; +sfr __at (CCP3CON_ADDR) CCP3CON; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADCON2_ADDR) ADCON2; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (CVRCON_ADDR) CVRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (PMDATA_ADDR) PMDATA; +sfr __at (PMADR_ADDR) PMADR; +sfr __at (PMDATH_ADDR) PMDATH; +sfr __at (PMADRH_ADDR) PMADRH; +sfr __at (PMCON1_ADDR) PMCON1; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + diff --git a/device/lib/pic/libdev/pic16f785.c b/device/lib/pic/libdev/pic16f785.c new file mode 100644 index 00000000..c99d805f --- /dev/null +++ b/device/lib/pic/libdev/pic16f785.c @@ -0,0 +1,83 @@ +/* Register definitions for pic16f785. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (ANSEL0_ADDR) ANSEL0; +sfr __at (PR2_ADDR) PR2; +sfr __at (ANSEL1_ADDR) ANSEL1; +sfr __at (WPU_ADDR) WPU; +sfr __at (WPUA_ADDR) WPUA; +sfr __at (IOC_ADDR) IOC; +sfr __at (IOCA_ADDR) IOCA; +sfr __at (REFCON_ADDR) REFCON; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (EEDAT_ADDR) EEDAT; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (PWMCON1_ADDR) PWMCON1; +sfr __at (PWMCON0_ADDR) PWMCON0; +sfr __at (PWMCLK_ADDR) PWMCLK; +sfr __at (PWMPH1_ADDR) PWMPH1; +sfr __at (PWMPH2_ADDR) PWMPH2; +sfr __at (CM1CON0_ADDR) CM1CON0; +sfr __at (CM2CON0_ADDR) CM2CON0; +sfr __at (CM2CON1_ADDR) CM2CON1; +sfr __at (OPA1CON_ADDR) OPA1CON; +sfr __at (OPA2CON_ADDR) OPA2CON; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + diff --git a/device/lib/pic/libdev/pic16f818.c b/device/lib/pic/libdev/pic16f818.c new file mode 100644 index 00000000..5614604c --- /dev/null +++ b/device/lib/pic/libdev/pic16f818.c @@ -0,0 +1,72 @@ +/* Register definitions for pic16f818. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + diff --git a/device/lib/pic/libdev/pic16f819.c b/device/lib/pic/libdev/pic16f819.c new file mode 100644 index 00000000..80504fac --- /dev/null +++ b/device/lib/pic/libdev/pic16f819.c @@ -0,0 +1,72 @@ +/* Register definitions for pic16f819. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + diff --git a/device/lib/pic/libdev/pic16f84.c b/device/lib/pic/libdev/pic16f84.c new file mode 100644 index 00000000..bf0bd8fc --- /dev/null +++ b/device/lib/pic/libdev/pic16f84.c @@ -0,0 +1,32 @@ +/* Register definitions for pic16f84. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16f84a.c b/device/lib/pic/libdev/pic16f84a.c new file mode 100644 index 00000000..184499c0 --- /dev/null +++ b/device/lib/pic/libdev/pic16f84a.c @@ -0,0 +1,32 @@ +/* Register definitions for pic16f84a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; + diff --git a/device/lib/pic/libdev/pic16f87.c b/device/lib/pic/libdev/pic16f87.c new file mode 100644 index 00000000..1d04e343 --- /dev/null +++ b/device/lib/pic/libdev/pic16f87.c @@ -0,0 +1,79 @@ +/* Register definitions for pic16f87. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (CVRCON_ADDR) CVRCON; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + diff --git a/device/lib/pic/libdev/pic16f870.c b/device/lib/pic/libdev/pic16f870.c new file mode 100644 index 00000000..faf7aa18 --- /dev/null +++ b/device/lib/pic/libdev/pic16f870.c @@ -0,0 +1,71 @@ +/* Register definitions for pic16f870. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f871.c b/device/lib/pic/libdev/pic16f871.c new file mode 100644 index 00000000..1338e6c0 --- /dev/null +++ b/device/lib/pic/libdev/pic16f871.c @@ -0,0 +1,76 @@ +/* Register definitions for pic16f871. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (PR2_ADDR) PR2; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f872.c b/device/lib/pic/libdev/pic16f872.c new file mode 100644 index 00000000..f17323f1 --- /dev/null +++ b/device/lib/pic/libdev/pic16f872.c @@ -0,0 +1,72 @@ +/* Register definitions for pic16f872. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; + diff --git a/device/lib/pic/libdev/pic16f873.c b/device/lib/pic/libdev/pic16f873.c new file mode 100644 index 00000000..322bc4d9 --- /dev/null +++ b/device/lib/pic/libdev/pic16f873.c @@ -0,0 +1,83 @@ +/* Register definitions for pic16f873. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f873a.c b/device/lib/pic/libdev/pic16f873a.c new file mode 100644 index 00000000..7ff3acf7 --- /dev/null +++ b/device/lib/pic/libdev/pic16f873a.c @@ -0,0 +1,87 @@ +/* Register definitions for pic16f873a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (CVRCON_ADDR) CVRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f874.c b/device/lib/pic/libdev/pic16f874.c new file mode 100644 index 00000000..88c7c4cc --- /dev/null +++ b/device/lib/pic/libdev/pic16f874.c @@ -0,0 +1,88 @@ +/* Register definitions for pic16f874. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f874a.c b/device/lib/pic/libdev/pic16f874a.c new file mode 100644 index 00000000..608536e5 --- /dev/null +++ b/device/lib/pic/libdev/pic16f874a.c @@ -0,0 +1,92 @@ +/* Register definitions for pic16f874a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (CVRCON_ADDR) CVRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f876.c b/device/lib/pic/libdev/pic16f876.c new file mode 100644 index 00000000..d972f86a --- /dev/null +++ b/device/lib/pic/libdev/pic16f876.c @@ -0,0 +1,83 @@ +/* Register definitions for pic16f876. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f876a.c b/device/lib/pic/libdev/pic16f876a.c new file mode 100644 index 00000000..1d4f1094 --- /dev/null +++ b/device/lib/pic/libdev/pic16f876a.c @@ -0,0 +1,87 @@ +/* Register definitions for pic16f876a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (CVRCON_ADDR) CVRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f877.c b/device/lib/pic/libdev/pic16f877.c new file mode 100644 index 00000000..670cce9d --- /dev/null +++ b/device/lib/pic/libdev/pic16f877.c @@ -0,0 +1,88 @@ +/* Register definitions for pic16f877. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f877a.c b/device/lib/pic/libdev/pic16f877a.c new file mode 100644 index 00000000..4f7106f9 --- /dev/null +++ b/device/lib/pic/libdev/pic16f877a.c @@ -0,0 +1,92 @@ +/* Register definitions for pic16f877a. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (SSPCON2_ADDR) SSPCON2; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (CVRCON_ADDR) CVRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; + diff --git a/device/lib/pic/libdev/pic16f88.c b/device/lib/pic/libdev/pic16f88.c new file mode 100644 index 00000000..9a907835 --- /dev/null +++ b/device/lib/pic/libdev/pic16f88.c @@ -0,0 +1,86 @@ +/* Register definitions for pic16f88. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (CMCON_ADDR) CMCON; +sfr __at (CVRCON_ADDR) CVRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (EEDATA_ADDR) EEDATA; +sfr __at (EEADR_ADDR) EEADR; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits; +volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; + diff --git a/device/lib/pic/libdev/pic16f913.c b/device/lib/pic/libdev/pic16f913.c new file mode 100644 index 00000000..54fe262d --- /dev/null +++ b/device/lib/pic/libdev/pic16f913.c @@ -0,0 +1,127 @@ +/* Register definitions for pic16f913. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (WPU_ADDR) WPU; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (IOC_ADDR) IOC; +sfr __at (CMCON1_ADDR) CMCON1; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (CMCON0_ADDR) CMCON0; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (LCDCON_ADDR) LCDCON; +sfr __at (LCDPS_ADDR) LCDPS; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (EEDATL_ADDR) EEDATL; +sfr __at (EEADRL_ADDR) EEADRL; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (LCDDATA0_ADDR) LCDDATA0; +sfr __at (LCDDATA1_ADDR) LCDDATA1; +sfr __at (LCDDATA3_ADDR) LCDDATA3; +sfr __at (LCDDATA4_ADDR) LCDDATA4; +sfr __at (LCDDATA6_ADDR) LCDDATA6; +sfr __at (LCDDATA7_ADDR) LCDDATA7; +sfr __at (LCDDATA9_ADDR) LCDDATA9; +sfr __at (LCDDATA10_ADDR) LCDDATA10; +sfr __at (LCDSE0_ADDR) LCDSE0; +sfr __at (LCDSE1_ADDR) LCDSE1; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; +volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits; +volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits; +volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; +volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits; +volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits; +volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits; +volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits; +volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits; +volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits; +volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits; +volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits; +volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; +volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits; +volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; +volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits; +volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + diff --git a/device/lib/pic/libdev/pic16f914.c b/device/lib/pic/libdev/pic16f914.c new file mode 100644 index 00000000..45dd36f1 --- /dev/null +++ b/device/lib/pic/libdev/pic16f914.c @@ -0,0 +1,143 @@ +/* Register definitions for pic16f914. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (WPU_ADDR) WPU; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (IOC_ADDR) IOC; +sfr __at (CMCON1_ADDR) CMCON1; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (CMCON0_ADDR) CMCON0; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (LCDCON_ADDR) LCDCON; +sfr __at (LCDPS_ADDR) LCDPS; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (EEDATL_ADDR) EEDATL; +sfr __at (EEADRL_ADDR) EEADRL; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (LCDDATA0_ADDR) LCDDATA0; +sfr __at (LCDDATA1_ADDR) LCDDATA1; +sfr __at (LCDDATA2_ADDR) LCDDATA2; +sfr __at (LCDDATA3_ADDR) LCDDATA3; +sfr __at (LCDDATA4_ADDR) LCDDATA4; +sfr __at (LCDDATA5_ADDR) LCDDATA5; +sfr __at (LCDDATA6_ADDR) LCDDATA6; +sfr __at (LCDDATA7_ADDR) LCDDATA7; +sfr __at (LCDDATA8_ADDR) LCDDATA8; +sfr __at (LCDDATA9_ADDR) LCDDATA9; +sfr __at (LCDDATA10_ADDR) LCDDATA10; +sfr __at (LCDDATA11_ADDR) LCDDATA11; +sfr __at (LCDSE0_ADDR) LCDSE0; +sfr __at (LCDSE1_ADDR) LCDSE1; +sfr __at (LCDSE2_ADDR) LCDSE2; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; +volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits; +volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits; +volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; +volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits; +volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits; +volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits; +volatile __LCDDATA11_bits_t __at(LCDDATA11_ADDR) LCDDATA11_bits; +volatile __LCDDATA2_bits_t __at(LCDDATA2_ADDR) LCDDATA2_bits; +volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits; +volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits; +volatile __LCDDATA5_bits_t __at(LCDDATA5_ADDR) LCDDATA5_bits; +volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits; +volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits; +volatile __LCDDATA8_bits_t __at(LCDDATA8_ADDR) LCDDATA8_bits; +volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits; +volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; +volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits; +volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits; +volatile __LCDSE2_bits_t __at(LCDSE2_ADDR) LCDSE2_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; +volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits; +volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + diff --git a/device/lib/pic/libdev/pic16f916.c b/device/lib/pic/libdev/pic16f916.c new file mode 100644 index 00000000..a684e06c --- /dev/null +++ b/device/lib/pic/libdev/pic16f916.c @@ -0,0 +1,127 @@ +/* Register definitions for pic16f916. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (WPU_ADDR) WPU; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (IOC_ADDR) IOC; +sfr __at (CMCON1_ADDR) CMCON1; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (CMCON0_ADDR) CMCON0; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (LCDCON_ADDR) LCDCON; +sfr __at (LCDPS_ADDR) LCDPS; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (EEDATL_ADDR) EEDATL; +sfr __at (EEADRL_ADDR) EEADRL; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (LCDDATA0_ADDR) LCDDATA0; +sfr __at (LCDDATA1_ADDR) LCDDATA1; +sfr __at (LCDDATA3_ADDR) LCDDATA3; +sfr __at (LCDDATA4_ADDR) LCDDATA4; +sfr __at (LCDDATA6_ADDR) LCDDATA6; +sfr __at (LCDDATA7_ADDR) LCDDATA7; +sfr __at (LCDDATA9_ADDR) LCDDATA9; +sfr __at (LCDDATA10_ADDR) LCDDATA10; +sfr __at (LCDSE0_ADDR) LCDSE0; +sfr __at (LCDSE1_ADDR) LCDSE1; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; +volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits; +volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits; +volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; +volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits; +volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits; +volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits; +volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits; +volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits; +volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits; +volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits; +volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits; +volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; +volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits; +volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; +volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits; +volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + diff --git a/device/lib/pic/libdev/pic16f917.c b/device/lib/pic/libdev/pic16f917.c new file mode 100644 index 00000000..c22be29c --- /dev/null +++ b/device/lib/pic/libdev/pic16f917.c @@ -0,0 +1,143 @@ +/* Register definitions for pic16f917. + * This file was automatically generated by: + * inc2h.pl V1.6 + * Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved + */ +#include + +data __at (INDF_ADDR) volatile char INDF; +sfr __at (TMR0_ADDR) TMR0; +data __at (PCL_ADDR) volatile char PCL; +sfr __at (STATUS_ADDR) STATUS; +sfr __at (FSR_ADDR) FSR; +sfr __at (PORTA_ADDR) PORTA; +sfr __at (PORTB_ADDR) PORTB; +sfr __at (PORTC_ADDR) PORTC; +sfr __at (PORTD_ADDR) PORTD; +sfr __at (PORTE_ADDR) PORTE; +sfr __at (PCLATH_ADDR) PCLATH; +sfr __at (INTCON_ADDR) INTCON; +sfr __at (PIR1_ADDR) PIR1; +sfr __at (PIR2_ADDR) PIR2; +sfr __at (TMR1L_ADDR) TMR1L; +sfr __at (TMR1H_ADDR) TMR1H; +sfr __at (T1CON_ADDR) T1CON; +sfr __at (TMR2_ADDR) TMR2; +sfr __at (T2CON_ADDR) T2CON; +sfr __at (SSPBUF_ADDR) SSPBUF; +sfr __at (SSPCON_ADDR) SSPCON; +sfr __at (CCPR1L_ADDR) CCPR1L; +sfr __at (CCPR1H_ADDR) CCPR1H; +sfr __at (CCP1CON_ADDR) CCP1CON; +sfr __at (RCSTA_ADDR) RCSTA; +sfr __at (TXREG_ADDR) TXREG; +sfr __at (RCREG_ADDR) RCREG; +sfr __at (CCPR2L_ADDR) CCPR2L; +sfr __at (CCPR2H_ADDR) CCPR2H; +sfr __at (CCP2CON_ADDR) CCP2CON; +sfr __at (ADRESH_ADDR) ADRESH; +sfr __at (ADCON0_ADDR) ADCON0; +sfr __at (OPTION_REG_ADDR) OPTION_REG; +sfr __at (TRISA_ADDR) TRISA; +sfr __at (TRISB_ADDR) TRISB; +sfr __at (TRISC_ADDR) TRISC; +sfr __at (TRISD_ADDR) TRISD; +sfr __at (TRISE_ADDR) TRISE; +sfr __at (PIE1_ADDR) PIE1; +sfr __at (PIE2_ADDR) PIE2; +sfr __at (PCON_ADDR) PCON; +sfr __at (OSCCON_ADDR) OSCCON; +sfr __at (OSCTUNE_ADDR) OSCTUNE; +sfr __at (ANSEL_ADDR) ANSEL; +sfr __at (PR2_ADDR) PR2; +sfr __at (SSPADD_ADDR) SSPADD; +sfr __at (SSPSTAT_ADDR) SSPSTAT; +sfr __at (WPUB_ADDR) WPUB; +sfr __at (WPU_ADDR) WPU; +sfr __at (IOCB_ADDR) IOCB; +sfr __at (IOC_ADDR) IOC; +sfr __at (CMCON1_ADDR) CMCON1; +sfr __at (TXSTA_ADDR) TXSTA; +sfr __at (SPBRG_ADDR) SPBRG; +sfr __at (CMCON0_ADDR) CMCON0; +sfr __at (VRCON_ADDR) VRCON; +sfr __at (ADRESL_ADDR) ADRESL; +sfr __at (ADCON1_ADDR) ADCON1; +sfr __at (WDTCON_ADDR) WDTCON; +sfr __at (LCDCON_ADDR) LCDCON; +sfr __at (LCDPS_ADDR) LCDPS; +sfr __at (LVDCON_ADDR) LVDCON; +sfr __at (EEDATL_ADDR) EEDATL; +sfr __at (EEADRL_ADDR) EEADRL; +sfr __at (EEDATH_ADDR) EEDATH; +sfr __at (EEADRH_ADDR) EEADRH; +sfr __at (LCDDATA0_ADDR) LCDDATA0; +sfr __at (LCDDATA1_ADDR) LCDDATA1; +sfr __at (LCDDATA2_ADDR) LCDDATA2; +sfr __at (LCDDATA3_ADDR) LCDDATA3; +sfr __at (LCDDATA4_ADDR) LCDDATA4; +sfr __at (LCDDATA5_ADDR) LCDDATA5; +sfr __at (LCDDATA6_ADDR) LCDDATA6; +sfr __at (LCDDATA7_ADDR) LCDDATA7; +sfr __at (LCDDATA8_ADDR) LCDDATA8; +sfr __at (LCDDATA9_ADDR) LCDDATA9; +sfr __at (LCDDATA10_ADDR) LCDDATA10; +sfr __at (LCDDATA11_ADDR) LCDDATA11; +sfr __at (LCDSE0_ADDR) LCDSE0; +sfr __at (LCDSE1_ADDR) LCDSE1; +sfr __at (LCDSE2_ADDR) LCDSE2; +sfr __at (EECON1_ADDR) EECON1; +sfr __at (EECON2_ADDR) EECON2; + +// +// bitfield definitions +// +volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits; +volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits; +volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits; +volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits; +volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits; +volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits; +volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits; +volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits; +volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits; +volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits; +volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits; +volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits; +volatile __LCDDATA0_bits_t __at(LCDDATA0_ADDR) LCDDATA0_bits; +volatile __LCDDATA1_bits_t __at(LCDDATA1_ADDR) LCDDATA1_bits; +volatile __LCDDATA10_bits_t __at(LCDDATA10_ADDR) LCDDATA10_bits; +volatile __LCDDATA11_bits_t __at(LCDDATA11_ADDR) LCDDATA11_bits; +volatile __LCDDATA2_bits_t __at(LCDDATA2_ADDR) LCDDATA2_bits; +volatile __LCDDATA3_bits_t __at(LCDDATA3_ADDR) LCDDATA3_bits; +volatile __LCDDATA4_bits_t __at(LCDDATA4_ADDR) LCDDATA4_bits; +volatile __LCDDATA5_bits_t __at(LCDDATA5_ADDR) LCDDATA5_bits; +volatile __LCDDATA6_bits_t __at(LCDDATA6_ADDR) LCDDATA6_bits; +volatile __LCDDATA7_bits_t __at(LCDDATA7_ADDR) LCDDATA7_bits; +volatile __LCDDATA8_bits_t __at(LCDDATA8_ADDR) LCDDATA8_bits; +volatile __LCDDATA9_bits_t __at(LCDDATA9_ADDR) LCDDATA9_bits; +volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits; +volatile __LCDSE0_bits_t __at(LCDSE0_ADDR) LCDSE0_bits; +volatile __LCDSE1_bits_t __at(LCDSE1_ADDR) LCDSE1_bits; +volatile __LCDSE2_bits_t __at(LCDSE2_ADDR) LCDSE2_bits; +volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits; +volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits; +volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits; +volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits; +volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits; +volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits; +volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits; +volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits; +volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits; +volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits; +volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits; +volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits; +volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits; +volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits; +volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits; +volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits; +volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits; +volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits; +volatile __WPU_bits_t __at(WPU_ADDR) WPU_bits; +volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits; + diff --git a/device/lib/pic/libsdcc/_gptrget1.S b/device/lib/pic/libsdcc/_gptrget1.S index 81355d21..bb0d4ed7 100644 --- a/device/lib/pic/libsdcc/_gptrget1.S +++ b/device/lib/pic/libsdcc/_gptrget1.S @@ -58,15 +58,15 @@ __gptrget1: __dataptrget1: setup_fsr - movf INDF, W + movf _INDF, W return __codeptrget1: ; call the RETLW instruction at the given address movf STK00, W - movwf PCLATH + movwf _PCLATH movf STK01, W - movwf PCL + movwf _PCL return ; should never be executed... END diff --git a/device/lib/pic/libsdcc/_gptrget2.S b/device/lib/pic/libsdcc/_gptrget2.S index 4829a62b..fcaebe68 100644 --- a/device/lib/pic/libsdcc/_gptrget2.S +++ b/device/lib/pic/libsdcc/_gptrget2.S @@ -57,19 +57,19 @@ __gptrget2: __dataptrget2: setup_fsr - movf INDF, W + movf _INDF, W movwf STK00 ; low byte in STK00 inc_fsr - movf INDF, W ; high byte in WREG + movf _INDF, W ; high byte in WREG return __codeptrget2: pagesel __codeptrget1 ; might reside in different page call __codeptrget1 movwf STK02 ; temporarily store LSB - incfsz STK01,F ; increment low address byte - decf STK00,F ; undo increment of high address byte if low byte did not overflow - incf STK00,F ; increment high address byte + incfsz STK01,F ; increment low address byte + decf STK00,F ; undo increment of high address byte if low byte did not overflow + incf STK00,F ; increment high address byte pagesel __codeptrget1 ; might reside in different page call __codeptrget1 movwf STK03 ; temporarily store MSB diff --git a/device/lib/pic/libsdcc/_gptrget3.S b/device/lib/pic/libsdcc/_gptrget3.S index 65928467..e08a17ed 100644 --- a/device/lib/pic/libsdcc/_gptrget3.S +++ b/device/lib/pic/libsdcc/_gptrget3.S @@ -58,28 +58,28 @@ __gptrget3: __dataptrget3: setup_fsr - movf INDF, W + movf _INDF, W movwf STK01 ; LSB in STK01 inc_fsr - movf INDF, W + movf _INDF, W movwf STK00 ; 2nd byte in STK00 inc_fsr - movf INDF, W ; MSB in WREG + movf _INDF, W ; MSB in WREG return __codeptrget3: pagesel __codeptrget1 ; might reside in different page call __codeptrget1 movwf STK02 ; temporarily store LSB - incfsz STK01,F ; increment low address byte - decf STK00,F ; undo increment of high address byte if low byte did not overflow - incf STK00,F ; increment high address byte + incfsz STK01,F ; increment low address byte + decf STK00,F ; undo increment of high address byte if low byte did not overflow + incf STK00,F ; increment high address byte pagesel __codeptrget1 ; might reside in different page call __codeptrget1 movwf STK03 ; temporarily store 2nd byte - incfsz STK01,F ; increment low address byte - decf STK00,F ; undo increment of high address byte if low byte did not overflow - incf STK00,F ; increment high address byte + incfsz STK01,F ; increment low address byte + decf STK00,F ; undo increment of high address byte if low byte did not overflow + incf STK00,F ; increment high address byte pagesel __codeptrget1 ; might reside in different page call __codeptrget1 movwf STK04 ; temporarily store MSB diff --git a/device/lib/pic/libsdcc/_gptrget4.S b/device/lib/pic/libsdcc/_gptrget4.S index 3648832c..3d3158d5 100644 --- a/device/lib/pic/libsdcc/_gptrget4.S +++ b/device/lib/pic/libsdcc/_gptrget4.S @@ -59,37 +59,37 @@ __gptrget4: __dataptrget4: setup_fsr - movf INDF, W + movf _INDF, W movwf STK02 ; LSB in STK02 inc_fsr - movf INDF, W + movf _INDF, W movwf STK01 ; 2nd byte in STK01 inc_fsr - movf INDF, W + movf _INDF, W movwf STK00 ; 3rd byte in STK00 inc_fsr - movf INDF, W ; MSB in WREG + movf _INDF, W ; MSB in WREG return __codeptrget4: pagesel __codeptrget1 ; might reside in different page call __codeptrget1 movwf STK02 ; temporarily store LSB - incfsz STK01,F ; increment low address byte - decf STK00,F ; undo increment of high address byte if low byte did not overflow - incf STK00,F ; increment high address byte + incfsz STK01,F ; increment low address byte + decf STK00,F ; undo increment of high address byte if low byte did not overflow + incf STK00,F ; increment high address byte pagesel __codeptrget1 ; might reside in different page call __codeptrget1 movwf STK03 ; temporarily store 2nd byte - incfsz STK01,F ; increment low address byte - decf STK00,F ; undo increment of high address byte if low byte did not overflow - incf STK00,F ; increment high address byte + incfsz STK01,F ; increment low address byte + decf STK00,F ; undo increment of high address byte if low byte did not overflow + incf STK00,F ; increment high address byte pagesel __codeptrget1 ; might reside in different page call __codeptrget1 movwf STK04 ; temporarily store 3rd byte - incfsz STK01,F ; increment low address byte - decf STK00,F ; undo increment of high address byte if low byte did not overflow - incf STK00,F ; increment high address byte + incfsz STK01,F ; increment low address byte + decf STK00,F ; undo increment of high address byte if low byte did not overflow + incf STK00,F ; increment high address byte pagesel __codeptrget1 ; might reside in different page call __codeptrget1 movwf STK05 ; temporarily store MSB diff --git a/device/lib/pic/libsdcc/_gptrput1.S b/device/lib/pic/libsdcc/_gptrput1.S index 1247be39..73c0db5f 100644 --- a/device/lib/pic/libsdcc/_gptrput1.S +++ b/device/lib/pic/libsdcc/_gptrput1.S @@ -58,7 +58,7 @@ __gptrput1: __dataptrput1: setup_fsr movf STK02, W ; get LSB(val) - movwf INDF ; store LSB + movwf _INDF ; store LSB return END diff --git a/device/lib/pic/libsdcc/_gptrput2.S b/device/lib/pic/libsdcc/_gptrput2.S index c6d5b489..f1811030 100644 --- a/device/lib/pic/libsdcc/_gptrput2.S +++ b/device/lib/pic/libsdcc/_gptrput2.S @@ -56,10 +56,10 @@ __gptrput2: __dataptrput2: setup_fsr movf STK03, W ; get LSB(val) - movwf INDF + movwf _INDF inc_fsr movf STK02, W ; get MSB(val) - movwf INDF + movwf _INDF return END diff --git a/device/lib/pic/libsdcc/_gptrput3.S b/device/lib/pic/libsdcc/_gptrput3.S index 214a93f0..0f0da791 100644 --- a/device/lib/pic/libsdcc/_gptrput3.S +++ b/device/lib/pic/libsdcc/_gptrput3.S @@ -56,13 +56,13 @@ __gptrput3: __dataptrput3: setup_fsr movf STK04, W ; get LSB(val) - movwf INDF + movwf _INDF inc_fsr movf STK03, W ; get 2nd byte of val - movwf INDF + movwf _INDF inc_fsr movf STK02, W ; get MSB(val) - movwf INDF + movwf _INDF return END diff --git a/device/lib/pic/libsdcc/_gptrput4.S b/device/lib/pic/libsdcc/_gptrput4.S index 2e108c28..50ecbaeb 100644 --- a/device/lib/pic/libsdcc/_gptrput4.S +++ b/device/lib/pic/libsdcc/_gptrput4.S @@ -56,16 +56,16 @@ __gptrput4: __dataptrput4: setup_fsr movf STK05, W ; get LSB(val) - movwf INDF + movwf _INDF inc_fsr movf STK04, W ; get 2nd byte of val - movwf INDF + movwf _INDF inc_fsr movf STK03, W ; get 3rd byte of val - movwf INDF + movwf _INDF inc_fsr movf STK02, W ; get MSB(val) - movwf INDF + movwf _INDF return END diff --git a/device/lib/pic/libsdcc/macros.inc b/device/lib/pic/libsdcc/macros.inc index 5ab3874e..79294b71 100644 --- a/device/lib/pic/libsdcc/macros.inc +++ b/device/lib/pic/libsdcc/macros.inc @@ -1,3 +1,17 @@ +; ----------------------------------------------- +; --- extern declared SFRs +; ----------------------------------------------- + extern _STATUS + extern _FSR + extern _INDF + extern _PCLATH + extern _PCL + +C EQU 0 +DC EQU 1 +Z EQU 2 +IRP EQU 7 + ; ----------------------------------------------- ; --- generic pointer access helpers ; ----------------------------------------------- @@ -8,35 +22,35 @@ GPTRTAG_CODE EQU 0x80 ; setup FSR to point to (STK00:STK01) setup_fsr macro movf STK01, W - movwf FSR + movwf _FSR ; select indirectly addressed bank - bcf STATUS, IRP + bcf _STATUS, IRP btfsc STK00, 0 - bsf STATUS, IRP + bsf _STATUS, IRP endm ; increment FSR, update IRP on bank crossings ; FIXME: update IRP if FSR is reset to 0... inc_fsr macro - incf FSR, F + incf _FSR, F endm ; dispatch according to gptr type select_routine macro dataptr, codeptr ; __data pointer tag: 0x00 xorlw GPTRTAG_DATA - btfsc STATUS, Z + btfsc _STATUS, Z goto dataptr ; __code pointer tag: 0x80 xorlw (GPTRTAG_DATA ^ GPTRTAG_CODE) - btfsc STATUS, Z + btfsc _STATUS, Z goto codeptr endm check_data macro dataptr ; __data pointer tag: 0x00 xorlw GPTRTAG_DATA - btfsc STATUS, Z + btfsc _STATUS, Z goto dataptr endm diff --git a/device/lib/pic16/Makefile.subdir b/device/lib/pic16/Makefile.subdir index c9358587..102973be 100644 --- a/device/lib/pic16/Makefile.subdir +++ b/device/lib/pic16/Makefile.subdir @@ -60,6 +60,10 @@ clean : recurse $(Q)-$(RM) .dummy $(foreach suf,asm d p lst hex cod sym,$(OBJS:.o=.$(suf))) @-echo "dummy" > .dummy $(Q)-$(RM) .dummy $(OBJS) $(LIB_LIB) + @-echo "dummy" > .dummy + $(Q)-$(RM) .dummy $(TARGETS) + @-echo "dummy" > .dummy + $(Q)-$(RM) .dummy $(addprefix $(topsrcdir)/$(installdir)/,$(notdir $(TARGETS))) $(Q)-[ ! -d "$(topsrcdir)/$(builddir)" ] || $(RMDIR) "$(topsrcdir)/$(builddir)" clean-intermediate : recurse diff --git a/src/SDCCmain.c b/src/SDCCmain.c index 3b5324f6..a7089a3f 100644 --- a/src/SDCCmain.c +++ b/src/SDCCmain.c @@ -2027,6 +2027,12 @@ preProcess (char **envp) addSet(&preArgvSet, Safe_strdup("-DSDCC_{port}")); addSet(&preArgvSet, Safe_strdup("-D__{port}")); + if (port && port->processor && TARGET_IS_PIC) { + char proc[512]; + SNPRINTF(&proc[0], 512, "-DSDCC_PROCESSOR=\"%s\"", port->processor); + addSet(&preArgvSet, Safe_strdup(proc)); + } + /* standard include path */ if (!options.nostdinc) { inclList = appendStrSet(includeDirsSet, "-I\"", "\""); diff --git a/src/pic/device.c b/src/pic/device.c index fea8565c..df172481 100644 --- a/src/pic/device.c +++ b/src/pic/device.c @@ -19,6 +19,8 @@ -------------------------------------------------------------------------*/ #include +#include +#include #include "common.h" // Include everything in the SDCC src directory #include "newalloc.h" @@ -31,97 +33,397 @@ #if defined(__BORLANDC__) || defined(_MSC_VER) #define STRCASECMP stricmp +#define STRNCASECMP strnicmp #else #define STRCASECMP strcasecmp +#define STRNCASECMP strncasecmp #endif extern int Gstack_base_addr; extern int Gstack_size; -static PIC_device Pics[] = { - { - {"p16f627", "16f627", "pic16f627", "f627"}, /* processor name */ - (memRange *)NULL, - (memRange *)NULL, - 0, /* max ram address (calculated) */ - 0x1ff, /* default max ram address */ - 0x80, /* Bank Mask */ - }, - - { - {"p16f628", "16f628", "pic16f628", "f628"}, - (memRange *)NULL, - (memRange *)NULL, - 0, - 0x1ff, - 0x80, - }, - - { - {"p16f84", "16f84", "pic16f84", "f84"}, - (memRange *)NULL, - (memRange *)NULL, - 0, - 0x4f, /* 68 register available 0x0C to 0x4F (0x8C to 0xCF mapped to bank 0) */ - 0x80, - }, - - { - {"p16f873", "16f873", "pic16f873", "f873"}, - (memRange *)NULL, - (memRange *)NULL, - 0, - 0x1ff, - 0x180, - }, - - { - {"p16f877", "16f877", "pic16f877", "f877"}, - (memRange *)NULL, - (memRange *)NULL, - 0, - 0x1ff, - 0x180, - }, - - { - {"p16f819", "16f819", "pic16f819", "f819"}, - (memRange *)NULL, - (memRange *)NULL, - 0, - 0x1ff, - 0x80, - }, - -}; - -static int num_of_supported_PICS = sizeof(Pics)/sizeof(PIC_device); +#define MAX_PICLIST 200 +static PIC_device *Pics[MAX_PICLIST]; +static int num_of_supported_PICS = 0; static PIC_device *pic=NULL; +int maxRAMaddress = 0; AssignedMemory *finalMapping=NULL; #define CONFIG_WORD_ADDRESS 0x2007 +#define CONFIG2_WORD_ADDRESS 0x2008 #define DEFAULT_CONFIG_WORD 0x3fff +#define DEFAULT_CONFIG2_WORD 0x3ffc + +#define DEVICE_FILE_NAME "pic14devices.txt" +#define PIC14_STRING_LEN 256 +#define SPLIT_WORDS_MAX 16 static unsigned int config_word = DEFAULT_CONFIG_WORD; +static unsigned int config2_word = DEFAULT_CONFIG2_WORD; extern int pic14_is_shared (regs *reg); extern void emitSymbolToFile (FILE *of, const char *name, const char *section_type, int size, int addr, int useEQU, int globalize); + +/* parse a value from the configuration file */ +static int parse_config_value(char *str) +{ + if (str[strlen(str) - 1] == 'K') + return atoi(str) * 1024; /* like "1K" */ + + else if (STRNCASECMP(str, "0x", 2) == 0) + return strtol(str+2, NULL, 16); /* like "0x400" */ + + else + return atoi(str); /* like "1024" */ +} + + +/* split a line into words */ +static int split_words(char result_word[SPLIT_WORDS_MAX][PIC14_STRING_LEN], char *str) +{ + char *pos = str; + int num_words = 0; + int ccount; + + while (*pos != '\0' && num_words < SPLIT_WORDS_MAX) { + /* remove leading spaces */ + while (isspace(*pos) || *pos == ',') + pos++; + + /* copy everything up until the first space or comma */ + for (ccount = 0; *pos != '\0' && !isspace(*pos) && *pos != ',' && ccount < PIC14_STRING_LEN-1; ccount++, pos++) + result_word[num_words][ccount] = *pos; + result_word[num_words][ccount] = '\0'; + + num_words++; + } + + return num_words; +} + + +/* remove annoying prefixes from the processor name */ +static char *sanitise_processor_name(char *name) +{ + char *proc_pos = name; + + if (name == NULL) + return NULL; + + if (STRNCASECMP(proc_pos, "pic16", 5) == 0) + proc_pos += 5; + + else if (STRNCASECMP(proc_pos, "p16", 3) == 0) + proc_pos += 3; + + else if (STRNCASECMP(proc_pos, "16", 2) == 0) + proc_pos += 2; + + return proc_pos; +} + + +/* create a structure for a pic processor */ +static PIC_device *create_pic(char *pic_name, int maxram, int bankmsk, int confsiz, int program, int data, int eeprom, int io) +{ + PIC_device *new_pic; + char *simple_pic_name = sanitise_processor_name(pic_name); + + new_pic = Safe_calloc(1, sizeof(PIC_device)); + new_pic->name[0] = Safe_calloc(strlen(simple_pic_name)+3, sizeof(char)); + sprintf(new_pic->name[0], "16%s", simple_pic_name); + new_pic->name[1] = Safe_calloc(strlen(simple_pic_name)+4, sizeof(char)); + sprintf(new_pic->name[1], "p16%s", simple_pic_name); + new_pic->name[2] = Safe_calloc(strlen(simple_pic_name)+6, sizeof(char)); + sprintf(new_pic->name[2], "pic16%s", simple_pic_name); + new_pic->name[3] = Safe_calloc(strlen(simple_pic_name)+1, sizeof(char)); + strcpy(new_pic->name[3], simple_pic_name); + + new_pic->defMaxRAMaddrs = maxram; + new_pic->bankMask = bankmsk; + new_pic->hasSecondConfigReg = confsiz > 1; + + new_pic->programMemSize = program; + new_pic->dataMemSize = data; + new_pic->eepromMemSize = eeprom; + new_pic->ioPins = io; + + Pics[num_of_supported_PICS] = new_pic; + num_of_supported_PICS++; + + return new_pic; +} + + +/* mark some registers as being duplicated across banks */ +static void register_map(int num_words, char word[SPLIT_WORDS_MAX][PIC14_STRING_LEN]) +{ + memRange r; + int pcount; + + if (num_words < 3) { + fprintf(stderr, "WARNING: not enough values in %s regmap directive\n", DEVICE_FILE_NAME); + return; + } + + r.alias = parse_config_value(word[1]); + + for (pcount = 2; pcount < num_words; pcount++) { + + r.start_address = parse_config_value(word[pcount]); + r.end_address = parse_config_value(word[pcount]); + r.bank = (r.start_address >> 7) & 3; + + addMemRange(&r, 1); + } +} + + +/* define ram areas - may be duplicated across banks */ +static void ram_map(int num_words, char word[SPLIT_WORDS_MAX][PIC14_STRING_LEN]) +{ + memRange r; + + if (num_words < 4) { + fprintf(stderr, "WARNING: not enough values in %s memmap directive\n", DEVICE_FILE_NAME); + return; + } + + r.start_address = parse_config_value(word[1]); + r.end_address = parse_config_value(word[2]); + r.alias = parse_config_value(word[3]); + r.bank = (r.start_address >> 7) & 3; + + addMemRange(&r, 0); +} + +extern set *includeDirsSet; +extern set *userIncDirsSet; +extern set *libDirsSet; +extern set *libPathsSet; + +/* read the file with all the pic14 definitions and pick out the definition for a processor + * if specified. if pic_name is NULL reads everything */ +static PIC_device *find_device(char *pic_name) +{ + FILE *pic_file; + char pic_buf[PIC14_STRING_LEN]; + char *pic_buf_pos; + int found_processor = FALSE; + int done = FALSE; + char processor_name[SPLIT_WORDS_MAX][PIC14_STRING_LEN]; + int num_processor_names = 0; + int pic_maxram = 0; + int pic_bankmsk = 0; + int pic_confsiz = 0; + int pic_program = 0; + int pic_data = 0; + int pic_eeprom = 0; + int pic_io = 0; + char *simple_pic_name; + char *dir; + char filename[512]; + int len = 512; + + simple_pic_name = sanitise_processor_name(pic_name); + + num_of_supported_PICS = 0; + + /* open the piclist file */ + /* first scan all include directories */ + pic_file = NULL; + //fprintf( stderr, "%s: searching %s\n", __FUNCTION__, DEVICE_FILE_NAME ); + for (dir = setFirstItem(includeDirsSet); + !pic_file && dir; + dir = setNextItem(includeDirsSet)) + { + fprintf( stderr, "searching1 %s\n", dir ); + SNPRINTF(&filename[0], len, "%s%s%s", dir, DIR_SEPARATOR_STRING, DEVICE_FILE_NAME); + pic_file = fopen( filename, "rt" ); + if (pic_file) break; + } // for + for (dir = setFirstItem(userIncDirsSet); + !pic_file && dir; + dir = setNextItem(userIncDirsSet)) + { + fprintf( stderr, "searching2 %s\n", dir ); + SNPRINTF(&filename[0], len, "%s%s%s", dir, DIR_SEPARATOR_STRING, DEVICE_FILE_NAME); + pic_file = fopen( filename, "rt" ); + if (pic_file) break; + } // for + for (dir = setFirstItem(libDirsSet); + !pic_file && dir; + dir = setNextItem(libDirsSet)) + { + fprintf( stderr, "searching3 %s\n", dir ); + SNPRINTF(&filename[0], len, "%s%s%s", dir, DIR_SEPARATOR_STRING, DEVICE_FILE_NAME); + pic_file = fopen( filename, "rt" ); + if (pic_file) break; + } // for + for (dir = setFirstItem(libPathsSet); + !pic_file && dir; + dir = setNextItem(libPathsSet)) + { + fprintf( stderr, "searching4 %s\n", dir ); + SNPRINTF(&filename[0], len, "%s%s%s", dir, DIR_SEPARATOR_STRING, DEVICE_FILE_NAME); + pic_file = fopen( filename, "rt" ); + if (pic_file) break; + } // for + if (!pic_file) { + pic_file = fopen(DATADIR LIB_DIR_SUFFIX DIR_SEPARATOR_STRING "pic" DIR_SEPARATOR_STRING DEVICE_FILE_NAME, "rt"); + } + if (pic_file == NULL) { + /* this second attempt is used when initially building the libraries */ + pic_file = fopen(".." DIR_SEPARATOR_STRING ".." DIR_SEPARATOR_STRING ".." DIR_SEPARATOR_STRING ".." + DIR_SEPARATOR_STRING "src" DIR_SEPARATOR_STRING "pic" DIR_SEPARATOR_STRING + DEVICE_FILE_NAME, "rt"); + if (pic_file == NULL) { + fprintf(stderr, "can't find %s\n", DATADIR LIB_DIR_SUFFIX DIR_SEPARATOR_STRING "pic" + DIR_SEPARATOR_STRING DEVICE_FILE_NAME); + return NULL; + } + } + + /* read line by line */ + pic_buf[sizeof(pic_buf)-1] = '\0'; + while (fgets(pic_buf, sizeof(pic_buf)-1, pic_file) != NULL && !done) { + + /* remove trailing spaces */ + while (isspace(pic_buf[strlen(pic_buf)-1])) + pic_buf[strlen(pic_buf)-1] = '\0'; + + /* remove leading spaces */ + for (pic_buf_pos = pic_buf; isspace(*pic_buf_pos); pic_buf_pos++) + {} + + /* ignore comment / empty lines */ + if (*pic_buf_pos != '\0' && *pic_buf_pos != '#') { + + /* split into fields */ + char pic_word[SPLIT_WORDS_MAX][PIC14_STRING_LEN]; + int num_pic_words; + int wcount; + + num_pic_words = split_words(pic_word, pic_buf_pos); + + if (STRCASECMP(pic_word[0], "processor") == 0) { + + if (pic_name == NULL) { + /* this is the mode where we read all the processors in - store the names for now */ + if (num_processor_names > 0) { + /* store away all the previous processor definitions */ + int dcount; + + for (dcount = 1; dcount < num_processor_names; dcount++) + create_pic(processor_name[dcount], pic_maxram, pic_bankmsk, + pic_confsiz, pic_program, pic_data, pic_eeprom, pic_io); + } + + num_processor_names = split_words(processor_name, pic_buf_pos); + } + else { + /* if we've just completed reading a processor definition stop now */ + if (found_processor) + done = TRUE; + else { + /* check if this processor name is a match */ + for (wcount = 1; wcount < num_pic_words; wcount++) { + + /* skip uninteresting prefixes */ + char *found_name = sanitise_processor_name(pic_word[wcount]); + + if (STRCASECMP(found_name, simple_pic_name) == 0) + found_processor = TRUE; + } + } + } + } + + else { + if (found_processor || pic_name == NULL) { + /* only parse a processor section if we've found the one we want */ + if (STRCASECMP(pic_word[0], "maxram") == 0 && num_pic_words > 1) { + pic_maxram = parse_config_value(pic_word[1]); + setMaxRAM(pic_maxram); + } + else if (STRCASECMP(pic_word[0], "bankmsk") == 0 && num_pic_words > 1) + pic_bankmsk = parse_config_value(pic_word[1]); + + else if (STRCASECMP(pic_word[0], "confsiz") == 0 && num_pic_words > 1) + pic_confsiz = parse_config_value(pic_word[1]); + + else if (STRCASECMP(pic_word[0], "program") == 0 && num_pic_words > 1) + pic_program = parse_config_value(pic_word[1]); + + else if (STRCASECMP(pic_word[0], "data") == 0 && num_pic_words > 1) + pic_data = parse_config_value(pic_word[1]); + + else if (STRCASECMP(pic_word[0], "eeprom") == 0 && num_pic_words > 1) + pic_eeprom = parse_config_value(pic_word[1]); + + else if (STRCASECMP(pic_word[0], "io") == 0 && num_pic_words > 1) + pic_io = parse_config_value(pic_word[1]); + + else if (STRCASECMP(pic_word[0], "regmap") == 0 && num_pic_words > 2) { + if (found_processor) + register_map(num_pic_words, pic_word); + } + else if (STRCASECMP(pic_word[0], "memmap") == 0 && num_pic_words > 2) { + if (found_processor) + ram_map(num_pic_words, pic_word); + } + else { + fprintf(stderr, "WARNING: %s: bad syntax `%s'\n", DEVICE_FILE_NAME, pic_word[0]); + } + } + } + } + } + + fclose(pic_file); + + /* if we're in read-the-lot mode then create the final processor definition */ + if (pic_name == NULL) { + + if (num_processor_names > 0) { + /* store away all the previous processor definitions */ + int dcount; + + for (dcount = 1; dcount < num_processor_names; dcount++) + create_pic(processor_name[dcount], pic_maxram, pic_bankmsk, + pic_confsiz, pic_program, pic_data, pic_eeprom, pic_io); + } + } + else { + /* in search mode */ + if (found_processor) { + /* create a new pic entry */ + return create_pic(pic_name, pic_maxram, pic_bankmsk, + pic_confsiz, pic_program, pic_data, pic_eeprom, pic_io); + } + } + + return NULL; +} + void addMemRange(memRange *r, int type) { int i; int alias = r->alias; - if (pic->maxRAMaddress < 0) { - fprintf(stderr, "missing \"#pragma maxram\" setting\n"); + if (maxRAMaddress < 0) { + fprintf(stderr, "missing maxram setting in %s\n", DEVICE_FILE_NAME); return; } do { for (i=r->start_address; i<= r->end_address; i++) { - if ((i|alias) <= pic->maxRAMaddress) { + if ((i|alias) <= maxRAMaddress) { + /* if we haven't seen this address before, enter it */ + if (!finalMapping[i | alias].isValid) { finalMapping[i | alias].isValid = 1; finalMapping[i | alias].alias = r->alias; finalMapping[i | alias].bank = r->bank; @@ -131,9 +433,10 @@ void addMemRange(memRange *r, int type) } else { finalMapping[i | alias].isSFR = 0; } + } } else { fprintf(stderr, "WARNING: %s:%s memory at 0x%x is beyond max ram = 0x%x\n", - __FILE__,__FUNCTION__,(i|alias), pic->maxRAMaddress); + __FILE__,__FUNCTION__,(i|alias), maxRAMaddress); } } @@ -150,20 +453,20 @@ void addMemRange(memRange *r, int type) void setMaxRAM(int size) { int i; - pic->maxRAMaddress = size; + maxRAMaddress = size; - if (pic->maxRAMaddress < 0) { - fprintf(stderr, "invalid \"#pragma maxram 0x%x\" setting\n", - pic->maxRAMaddress); + if (maxRAMaddress < 0) { + fprintf(stderr, "invalid maxram 0x%x setting in %s\n", + maxRAMaddress, DEVICE_FILE_NAME); return; } - finalMapping = Safe_calloc(1+pic->maxRAMaddress, + finalMapping = Safe_calloc(1+maxRAMaddress, sizeof(AssignedMemory)); /* Now initialize the finalMapping array */ - for(i=0; i<=pic->maxRAMaddress; i++) { + for(i=0; i<=maxRAMaddress; i++) { finalMapping[i].reg = NULL; finalMapping[i].isValid = 0; finalMapping[i].bank = (i>>7); @@ -203,7 +506,7 @@ int REGallBanks(regs *reg) int isSFR(int address) { - if( (address > pic->maxRAMaddress) || !finalMapping[address].isSFR) + if( (address > maxRAMaddress) || !finalMapping[address].isSFR) return 0; return 1; @@ -218,7 +521,7 @@ void dump_map(void) { int i; - for(i=0; i<=pic->maxRAMaddress; i++) { + for(i=0; i<=maxRAMaddress; i++) { //fprintf(stdout , "addr 0x%02x is %s\n", i, ((finalMapping[i].isValid) ? "valid":"invalid")); if(finalMapping[i].isValid) { @@ -244,12 +547,12 @@ void dump_sfr(FILE *of) //dump_map(); /* display the register map */ //fprintf(stdout,";dump_sfr \n"); - if (pic->maxRAMaddress < 0) { - fprintf(stderr, "missing \"#pragma maxram\" setting\n"); + if (maxRAMaddress < 0) { + fprintf(stderr, "missing maxram setting in %s\n", DEVICE_FILE_NAME); return; } - for (addr = 0; addr <= pic->maxRAMaddress; addr++) + for (addr = 0; addr <= maxRAMaddress; addr++) { regs *reg = finalMapping[addr].reg; @@ -258,7 +561,10 @@ void dump_sfr(FILE *of) if (pic14_options.isLibrarySource && pic14_is_shared (reg)) { /* rely on external declarations for the non-fixed stack */ - fprintf (of, "\textern\t%s\n", reg->name); + /* Update: We always emit the STACK symbols into a + * udata_shr section, so no extern declaration is + * required. */ + //fprintf (of, "\textern\t%s\n", reg->name); } else { emitSymbolToFile (of, reg->name, "udata", reg->size, reg->isFixed ? reg->address : -1, 0, pic14_is_shared (reg)); } @@ -325,7 +631,7 @@ void dump_sfr(FILE *of) addr++; - } while(addr <= pic->maxRAMaddress); + } while(addr <= maxRAMaddress); #endif @@ -343,33 +649,63 @@ void dump_sfr(FILE *of) *-----------------------------------------------------------------*/ void list_valid_pics(int ncols, int list_alias) { - int col,longest; - int i,j,k,l; + int col=0,longest; + int i,j,k; + int max_alias = 1; + + if (num_of_supported_PICS == 0) + find_device(NULL); /* load all the definitions */ if(list_alias) - list_alias = sizeof(Pics[0].name) / sizeof(Pics[0].name[0]); + max_alias = PROCESSOR_NAMES; /* decrement the column number if it's greater than zero */ ncols = (ncols > 1) ? ncols-1 : 4; /* Find the device with the longest name */ for(i=0,longest=0; iname[j]); if(k>longest) longest = k; } } +#if 0 + /* heading */ + fprintf(stderr, "\nPIC14 processors and their characteristics:\n\n"); + fprintf(stderr, " processor"); + for(k=0; kname[0]); + l = longest + 2 - strlen(Pics[i]->name[0]); + for(k=0; kprogramMemSize % 1024 == 0) + fprintf(stderr, "%4dK", Pics[i]->programMemSize / 1024); + else + fprintf(stderr, "%5d", Pics[i]->programMemSize); + + fprintf(stderr, " %5d %5d %4d\n", + Pics[i]->dataMemSize, Pics[i]->eepromMemSize, Pics[i]->ioPins); + } + col = 0; + fprintf(stderr, "\nPIC14 processors supported:\n"); for(i=0; i < num_of_supported_PICS; i++) { - j = 0; - do { - fprintf(stderr,"%s", Pics[i].name[j]); + for (j = 0; jname[j]); if(colname[j]); for(k=0; kmaxRAMaddress = -1; } /*-----------------------------------------------------------------* @@ -437,7 +747,7 @@ void init_pic(char *pic_type) *-----------------------------------------------------------------*/ int picIsInitialized(void) { - if(pic && pic->maxRAMaddress > 0) + if(pic && maxRAMaddress > 0) return 1; return 0; @@ -453,7 +763,7 @@ char *processor_base_name(void) if(!pic) return NULL; - return pic->name[0]; + return pic->name[1]; } /*-----------------------------------------------------------------* @@ -462,13 +772,13 @@ int validAddress(int address, int reg_size) { int i; - if (pic->maxRAMaddress < 0) { - fprintf(stderr, "missing \"#pragma maxram\" setting\n"); + if (maxRAMaddress < 0) { + fprintf(stderr, "missing maxram setting in %s\n", DEVICE_FILE_NAME); return 0; } // fprintf(stderr, "validAddress: Checking 0x%04x\n",address); assert (reg_size > 0); - if(address + (reg_size - 1) > pic->maxRAMaddress) + if(address + (reg_size - 1) > maxRAMaddress) return 0; for (i=0; imaxRAMaddress < 0) { - fprintf(stderr, "missing \"#pragma maxram\" setting\n"); + if (maxRAMaddress < 0) { + fprintf(stderr, "missing maxram setting in %s\n", DEVICE_FILE_NAME); return; } @@ -554,7 +864,7 @@ int assignRegister(regs *reg, int start_address) * so we'll search through all availble ram address and * assign the first one */ - for (i=start_address; i<=pic->maxRAMaddress; i++) { + for (i=start_address; i<=maxRAMaddress; i++) { if (validAddress(i,reg->size)) { reg->address = i; @@ -626,54 +936,90 @@ void assignRelocatableRegisters(set *regset, int used) /*-----------------------------------------------------------------* * void assignConfigWordValue(int address, int value) * -* All midrange PICs have one config word at address 0x2007. -* This routine will assign a value to that address. +* Most midrange PICs have one config word at address 0x2007. +* Newer PIC14s have a second config word at address 0x2008. +* This routine will assign values to those addresses. * *-----------------------------------------------------------------*/ void assignConfigWordValue(int address, int value) { - if(CONFIG_WORD_ADDRESS == address) + if (CONFIG_WORD_ADDRESS == address) config_word = value; - //fprintf(stderr,"setting config word to 0x%x\n",value); + else if (CONFIG2_WORD_ADDRESS == address) + config2_word = value; + + //fprintf(stderr,"setting config word 0x%x to 0x%x\n", address, value); } /*-----------------------------------------------------------------* * int getConfigWord(int address) * -* Get the current value of the config word. +* Get the current value of a config word. * *-----------------------------------------------------------------*/ int getConfigWord(int address) { - if(CONFIG_WORD_ADDRESS == address) + switch (address) + { + case CONFIG_WORD_ADDRESS: return config_word; - else - return 0; + case CONFIG2_WORD_ADDRESS: + return config2_word; + default: + return 0; + } } /*-----------------------------------------------------------------* * *-----------------------------------------------------------------*/ -void setDefMaxRam(void) +unsigned getMaxRam(void) { - unsigned i; - setMaxRAM(pic->defMaxRAMaddrs); /* Max RAM has not been included, so use default setting */ - /* Validate full memory range for use by general purpose RAM */ - for (i=0; i <= pic->defMaxRAMaddrs; i++) { - finalMapping[i].bank = (i>>7); - finalMapping[i].isValid = 1; - } + return pic->defMaxRAMaddrs; } + /*-----------------------------------------------------------------* -* +* int getHasSecondConfigReg(void) - check if the device has a +* second config register, rather than just one. *-----------------------------------------------------------------*/ -unsigned getMaxRam(void) +int getHasSecondConfigReg(void) { - return pic->defMaxRAMaddrs; + if(!pic) + return 0; + else + return pic->hasSecondConfigReg; +} + +/*-----------------------------------------------------------------* + * Query the size of the sharebank of the selected device. + * FIXME: Currently always returns 16. + *-----------------------------------------------------------------*/ +int pic14_getSharebankSize(void) +{ + return 16; } + +/*-----------------------------------------------------------------* + * Query the highest byte address occupied by the sharebank of the + * selected device. + * FIXME: Currently always returns 0x7f. + * THINK: Might not be needed, if we assign all shareable objects to + * a `udata_shr' section and let the linker do the rest... + * Tried it, but yields `no target memory available' for pic16f877... + *-----------------------------------------------------------------*/ +int pic14_getSharebankAddress(void) +{ + int sharebankAddress = 0x7f; + /* If total RAM is less than 0x7f as with 16f84 then reduce + * sharebankAddress to fit */ + if ((unsigned)sharebankAddress > getMaxRam()) + sharebankAddress = (int)getMaxRam(); + return sharebankAddress; +} + diff --git a/src/pic/device.h b/src/pic/device.h index 52d50cc0..5fb8a440 100644 --- a/src/pic/device.h +++ b/src/pic/device.h @@ -83,6 +83,12 @@ typedef struct PIC_device { int defMaxRAMaddrs; /* default maximum value for a data address */ int bankMask; /* Bitmask that is ANDed with address to extract banking bits */ // int hasAliasedRAM:1; /* True if there are bank independent registers */ + int hasSecondConfigReg; /* True if there is a second configuration register */ + + int programMemSize; /* program memory size in words - for device listing only */ + int dataMemSize; /* data (RAM) memory size in bytes - for device listing only */ + int eepromMemSize; /* EEPROM memory size in bytes - for device listing only */ + int ioPins; /* number of I/O pins - for device listing only */ } PIC_device; @@ -102,5 +108,8 @@ void addMemRange(memRange *r, int type); void setMaxRAM(int size); void setDefMaxRam(void); unsigned getMaxRam(void); +int getHasSecondConfigReg(void); +int pic14_getSharebankSize(void); +int pic14_getSharebankAddress(void); #endif /* __DEVICE_H__ */ diff --git a/src/pic/glue.c b/src/pic/glue.c index 6f69194a..6b6af973 100644 --- a/src/pic/glue.c +++ b/src/pic/glue.c @@ -70,6 +70,9 @@ extern void printPublics (FILE * afile); extern void printChar (FILE * ofile, char *s, int plen); void pCodeInitRegisters(void); int getConfigWord(int address); +int getHasSecondConfigReg(void); +int pic14_getSharebankSize(void); +int pic14_getSharebankAddress(void); char *udata_section_name=0; // FIXME Temporary fix to change udata section name -- VR @@ -191,11 +194,15 @@ emitSymbolToFile (FILE *of, const char *name, const char *section_type, int size if (!section_type) section_type = "udata"; if (addr != -1) { + /* absolute symbols are handled in pic14_constructAbsMap */ + /* do nothing */ +#if 0 /* workaround gpasm bug with symbols being EQUated and placed in absolute sections */ - if (is_shared_address (addr)) + if (1 || !is_shared_address (addr)) { if (globalize) fprintf (of, "\tglobal\t%s\n", name); - fprintf (of, "udata_%s_%u\t%s\t0x%04x\n", moduleName, sec_idx++, section_type, addr); + fprintf (of, "udata_%s_%u\t%s\t0x%04x\n", moduleName, + sec_idx++, "udata_ovr", addr); fprintf (of, "%s\tres\t%d\n", name, size); } else @@ -203,16 +210,119 @@ emitSymbolToFile (FILE *of, const char *name, const char *section_type, int size /* EQUs cannot be exported... */ fprintf (of, "%s\tEQU\t0x%04x\n", name, addr); } +#endif } else { if (globalize) fprintf (of, "\tglobal\t%s\n", name); - fprintf (of, "udata_%s_%u\t%s\n", moduleName, sec_idx++, section_type); + fprintf (of, "udata_%s_%u\t%s\n", moduleName, + sec_idx++, section_type); fprintf (of, "%s\tres\t%d\n", name, size); } } - + + //if (options.verbose) fprintf (stderr, "%s: emitted %s\n", __FUNCTION__, name); addSet (&symbolsEmitted, (void *) name); } +#define IS_DEFINED_HERE(sym) (!IS_EXTERN(sym->etype)) +static void +pic14_constructAbsMap (FILE *ofile) +{ + memmap *maps[] = { data, sfr, NULL }; + int i; + hTab *ht = NULL; + symbol *sym; + set *aliases; + int addr, min=-1, max=-1; + int size; + + for (i=0; maps[i] != NULL; i++) + { + for (sym = (symbol *)setFirstItem (maps[i]->syms); + sym; sym = setNextItem (maps[i]->syms)) + { + if (IS_DEFINED_HERE(sym) && SPEC_ABSA(sym->etype)) + { + addr = SPEC_ADDR(sym->etype); + if (max == -1 || addr > max) max = addr; + if (min == -1 || addr < min) min = addr; + //fprintf (stderr, "%s: sym %s @ 0x%x\n", __FUNCTION__, sym->name, addr); + aliases = hTabItemWithKey (ht, addr); + if (aliases) { + /* May not use addSetHead, as we cannot update the + * list's head in the hastable `ht'. */ + addSet (&aliases, sym); +#if 0 + fprintf( stderr, "%s: now %d aliases for %s @ 0x%x\n", + __FUNCTION__, elementsInSet(aliases), sym->name, addr); +#endif + } else { + addSet (&aliases, sym); + hTabAddItem (&ht, addr, aliases); + } // if + } // if + } // for sym + } // for i + + /* now emit definitions for all absolute symbols */ + fprintf (ofile, "%s", iComments2); + fprintf (ofile, "; absolute symbol definitions\n"); + fprintf (ofile, "%s", iComments2); + for (addr=min; addr <= max; addr++) + { + size = 1; + aliases = hTabItemWithKey (ht, addr); + if (aliases && elementsInSet(aliases)) { + fprintf (ofile, "udata_abs_%s_%x\tudata_ovr\t0x%04x", + moduleName, addr, addr); + for (sym = setFirstItem (aliases); sym; + sym = setNextItem (aliases)) + { + /* emit STATUS as well as _STATUS, required for SFRs only */ + fprintf (ofile, "\n%s", sym->name); + fprintf (ofile, "\n%s", sym->rname); + if (getSize(sym->type) > size) { + size = getSize(sym->type); + } + } // for + fprintf (ofile, "\tres\t%d\n", size); + } // if + } // for i + + /* also emit STK symbols + * XXX: This is ugly and fails as soon as devices start to get + * differently sized sharebanks, since STK12 will be + * required by larger devices but only up to STK03 might + * be defined using smaller devices. */ + fprintf (ofile, "\n"); + if (!pic14_options.isLibrarySource) + { + fprintf (ofile, "\tglobal PSAVE\n"); + fprintf (ofile, "\tglobal SSAVE\n"); + fprintf (ofile, "\tglobal WSAVE\n"); + for (i=pic14_getSharebankSize()-4; i >= 0; i--) { + fprintf (ofile, "\tglobal STK%02d\n", i); + } // for i + fprintf (ofile, "sharebank udata_ovr 0x%04x\n", + pic14_getSharebankAddress() - pic14_getSharebankSize() + 1); + fprintf (ofile, "PSAVE\tres 1\n"); + fprintf (ofile, "SSAVE\tres 1\n"); + fprintf (ofile, "WSAVE\tres 1\n"); + /* fill rest of sharebank with stack STKxx .. STK00 */ + for (i=pic14_getSharebankSize()-4; i >= 0; i--) { + fprintf (ofile, "STK%02d\tres 1\n", i); + } // for i + } else { + /* declare STKxx as extern for all files + * except the one containing main() */ + fprintf (ofile, "\textern PSAVE\n"); + fprintf (ofile, "\textern SSAVE\n"); + fprintf (ofile, "\textern WSAVE\n"); + for (i=pic14_getSharebankSize()-4; i >= 0; i--) { + fprintf (ofile, "\textern STK%02d\n", i); + } // for i + } +} + /*-----------------------------------------------------------------*/ /* emitRegularMap - emit code for maps with no special cases */ /*-----------------------------------------------------------------*/ @@ -245,13 +355,16 @@ pic14emitRegularMap (memmap * map, bool addPublics, bool arFlag) !sym->allocreq && sym->level) continue; - /* if global variable & not static or extern + /* if global variable & not static or extern and addPublics allowed then add it to the public set */ if ((sym->level == 0 || (sym->_isparm && !IS_REGPARM (sym->etype))) && addPublics && !IS_STATIC (sym->etype)) + { + //fprintf( stderr, "%s: made public %s\n", __FUNCTION__, sym->name ); addSetHead (&publics, sym); + } // PIC code allocates its own registers - so ignore parameter variable generated by processFuncArgs() if (sym->_isparm) @@ -275,10 +388,13 @@ pic14emitRegularMap (memmap * map, bool addPublics, bool arFlag) fprintf (map->oFile, "%s_%d_%d", sym->name, sym->level, sym->block); } #endif + /* absolute symbols are handled in pic14_constructAbsMap */ + if (SPEC_ABSA(sym->etype) && IS_DEFINED_HERE(sym)) + continue; /* if it has an absolute address then generate an equate for this no need to allocate space */ - if (SPEC_ABSA (sym->etype)) + if (0 && SPEC_ABSA (sym->etype)) { //if (options.debug || sym->level == 0) //fprintf (map->oFile,"; == 0x%04x\n",SPEC_ADDR (sym->etype)); @@ -300,7 +416,15 @@ pic14emitRegularMap (memmap * map, bool addPublics, bool arFlag) } else { - emitSymbolToFile (map->oFile, sym->rname, NULL, getSize (sym->type) & 0xffff, -1, 0, 0); + emitSymbolToFile (map->oFile, + sym->rname, + NULL, + getSize (sym->type) & 0xffff, + SPEC_ABSA(sym->etype) + ? SPEC_ADDR(sym->etype) + : -1, + 0, + 0); /* { int i, size; @@ -816,13 +940,14 @@ pic14emitStaticSeg (memmap * map) static void pic14emitMaps () { + pic14_constructAbsMap (sfr->oFile); /* no special considerations for the following data, idata & bit & xdata */ pic14emitRegularMap (data, TRUE, TRUE); pic14emitRegularMap (idata, TRUE, TRUE); pic14emitRegularMap (bit, TRUE, FALSE); pic14emitRegularMap (xdata, TRUE, TRUE); - pic14emitRegularMap (sfr, FALSE, FALSE); + pic14emitRegularMap (sfr, TRUE, FALSE); pic14emitRegularMap (sfrbit, FALSE, FALSE); pic14emitRegularMap (code, TRUE, FALSE); pic14emitStaticSeg (statsg); @@ -860,7 +985,13 @@ pic14createInterruptVect (FILE * vFile) fprintf (vFile, "%s", iComments2); fprintf (vFile, "; config word \n"); fprintf (vFile, "%s", iComments2); - fprintf (vFile, "\t__config 0x%x\n", getConfigWord(0x2007)); + if (getHasSecondConfigReg()) + { + fprintf (vFile, "\t__config _CONFIG1, 0x%x\n", getConfigWord(0x2007)); + fprintf (vFile, "\t__config _CONFIG2, 0x%x\n", getConfigWord(0x2008)); + } + else + fprintf (vFile, "\t__config 0x%x\n", getConfigWord(0x2007)); fprintf (vFile, "%s", iComments2); fprintf (vFile, "; reset vector \n"); @@ -920,7 +1051,8 @@ pic14printPublics (FILE * afile) fprintf (afile, "\tglobal %s\n", sym->rname); } else { /* Absolute variables are defines in the asm file as equates and thus can not be made global. */ - if (!SPEC_ABSA (sym->etype)) + /* Not any longer! */ + //if (!SPEC_ABSA (sym->etype)) fprintf (afile, "\tglobal %s\n", sym->rname); } } diff --git a/src/pic/main.c b/src/pic/main.c index e6014e0e..77fd95c7 100644 --- a/src/pic/main.c +++ b/src/pic/main.c @@ -25,7 +25,7 @@ static char _defaultRules[] = static char *_pic14_keywords[] = { "at", - "bit", + //"bit", "code", "critical", "data", @@ -36,7 +36,7 @@ static char *_pic14_keywords[] = "pdata", "reentrant", "sfr", - "sbit", + //"sbit", "using", "xdata", "_data", @@ -72,7 +72,6 @@ static void _pic14_init (void) { asm_addTree (&asm_asxxxx_mapping); - pCodeInitRegisters(); memset (&pic14_options, 0, sizeof (pic14_options)); } @@ -142,17 +141,7 @@ _process_pragma(const char *sz) return 0; } else if (startsWith (ptr, "maxram")) { - char *maxRAM = strtok((char *)NULL, WHITE); - - if (maxRAM != (char *)NULL) { - int maxRAMaddress; - value *maxRAMVal; - - maxRAMVal = constVal(maxRAM); - maxRAMaddress = (int)floatFromVal(maxRAMVal); - setMaxRAM(maxRAMaddress); - } - + // not used any more - comes from device config file pic14devices.txt instead return 0; } return 1; @@ -187,9 +176,42 @@ _pic14_parseOptions (int *pargc, char **argv, int *i) return FALSE; } +extern set *dataDirsSet; +extern set *includeDirsSet; +/* pic14 port uses include/pic and lib/pic instead of + * include/pic14 and lib/pic14 as indicated by SDCCmain.c's + * setIncludePaths routine. */ +static void +_pic14_initPaths (void) +{ + char *p; + char *p2=NULL; + set *tempSet=NULL; + + if (options.nostdinc) + return; + + tempSet = appendStrSet(dataDirsSet, NULL, INCLUDE_DIR_SUFFIX DIR_SEPARATOR_STRING "pic"); + mergeSets(&includeDirsSet, tempSet); + + if ((p = getenv(SDCC_INCLUDE_NAME)) != NULL) + { + addSetHead(&includeDirsSet, p); + p2=Safe_alloc(strlen(p)+strlen(DIR_SEPARATOR_STRING)+strlen("pic")+1); + if(p2!=NULL) + { + strcpy(p2, p); + strcat(p2, DIR_SEPARATOR_STRING); + strcat(p2, "pic"); + addSetHead(&includeDirsSet, p2); + } + } +} + static void _pic14_finaliseOptions (void) { + pCodeInitRegisters(); port->mem.default_local_map = data; port->mem.default_globl_map = data; @@ -456,6 +478,8 @@ static void _pic14_do_link (void) /* LIBRARIES */ addSet(&libFilesSet, "libsdcc.lib"); + SNPRINTF(&temp[0], 128, "pic%s.lib", port->processor); + addSet(&libFilesSet, temp); shash_add(&linkValues, "libs", joinStrSet(libFilesSet)); lcmd = msprintf(linkValues, lfrm); @@ -556,7 +580,7 @@ PORT pic_port = _pic14_init, _pic14_parseOptions, _pic14_poptions, - NULL, + _pic14_initPaths, _pic14_finaliseOptions, _pic14_setDefaultOptions, pic14_assignRegisters, diff --git a/src/pic/pcode.c b/src/pic/pcode.c index b5539144..58a6b85a 100644 --- a/src/pic/pcode.c +++ b/src/pic/pcode.c @@ -1350,11 +1350,18 @@ void pCodeInitRegisters(void) initialized = 1; init_pic(port->processor); - shareBankAddress = 0x7f; /* FIXME - some PIC ICs like 16C7X which do not have a shared bank need a different approach. */ - if ((unsigned)shareBankAddress > getMaxRam()) /* If total RAM is less than 0x7f as with 16f84 then reduce shareBankAddress to fit */ - shareBankAddress = (int)getMaxRam(); - stkSize = 15; /* Set pseudo stack size to 15, on multi memory bank ICs this leaves room for WSAVE (used for interrupts) to fit into the shared portion of the memory bank */ - initStack(shareBankAddress, stkSize); /* Putting the pseudo stack in shared memory so all modules use the same register when passing fn parameters */ + /* FIXME - some PIC ICs like 16C7X which do not have a shared bank + * need a different approach. + * The fixed address might not be needed anyway, possibly the + * linker will assign udata_shr sections correctly... */ + shareBankAddress = pic14_getSharebankAddress(); + /* Set pseudo stack size to SHAREBANKSIZE - 3. + * On multi memory bank ICs this leaves room for WSAVE/SSAVE/PSAVE + * (used for interrupts) to fit into the shared portion of the + * memory bank */ + stkSize = pic14_getSharebankSize()-3; + /* Putting the pseudo stack in shared memory so all modules use the same register when passing fn parameters */ + initStack(shareBankAddress, stkSize); pc_status.r = allocProcessorRegister(IDX_STATUS,"STATUS", PO_STATUS, 0x180); pc_pcl.r = allocProcessorRegister(IDX_PCL,"PCL", PO_PCL, 0x80); @@ -5606,7 +5613,8 @@ void AnalyzeBanking(void) pBlock *pb; if(!picIsInitialized()) { - setDefMaxRam(); // Max RAM has not been included, so use default setting + werror(E_FILE_OPEN_ERR, "no memory size is known for this processor"); + exit(1); } if (!the_pFile) return; diff --git a/src/pic/ralloc.c b/src/pic/ralloc.c index 7d58ccbd..c6f7f3cf 100644 --- a/src/pic/ralloc.c +++ b/src/pic/ralloc.c @@ -134,6 +134,7 @@ static void vsprintf (buffer, fmt, ap); fprintf (debugF, "%s", buffer); + //if (options.verbose) fprintf (stderr, "%s: %s", __FUNCTION__, buffer); /* while (isspace((unsigned char)*bufferP)) bufferP++; @@ -369,7 +370,7 @@ static regs* newReg(short type, short pc_type, int rIdx, char *name, int size, i dReg->name = Safe_strdup(buffer); } dReg->isFree = 0; - dReg->wasUsed = 1; + dReg->wasUsed = 0; if (type == REG_SFR) dReg->isFixed = 1; else @@ -386,7 +387,9 @@ static regs* newReg(short type, short pc_type, int rIdx, char *name, int size, i dReg->reglives.usedpFlows = newSet(); dReg->reglives.assignedpFlows = newSet(); - hTabAddItem(&dynDirectRegNames, regname2key(name), dReg); + hTabAddItem(&dynDirectRegNames, regname2key(dReg->name), dReg); + debugLog( "%s: Created register %s (%p).\n", + __FUNCTION__, dReg->name, __builtin_return_address(0) ); return dReg; } @@ -486,7 +489,7 @@ regFindFree (set *dRegs) return NULL; } /*-----------------------------------------------------------------*/ -/* initStack - allocate registers for a psuedo stack */ +/* initStack - allocate registers for a pseudo stack */ /*-----------------------------------------------------------------*/ void initStack(int base_address, int size) { @@ -596,7 +599,7 @@ dirregWithName (char *name) int IS_CONFIG_ADDRESS(int address) { - return address == 0x2007; + return address == 0x2007 || address == 0x2008; } /*-----------------------------------------------------------------*/ @@ -2740,7 +2743,7 @@ regTypeNum () debugLog (" %d - \n", __LINE__); - /* create a psuedo symbol & force a spil */ + /* create a pseudo symbol & force a spil */ //X symbol *psym = newSymbol (rematStr (OP_SYMBOL (IC_LEFT (ic))), 1); psym = rematStr (OP_SYMBOL (IC_LEFT (ic))); psym->type = sym->type; diff --git a/support/scripts/inc2h.pl b/support/scripts/inc2h.pl index 4283688e..589f38ce 100755 --- a/support/scripts/inc2h.pl +++ b/support/scripts/inc2h.pl @@ -129,28 +129,44 @@ while () { # } # } +# Create header for pic${processor}.c file +$lcproc = "pic" . lc($processor); +$c_head = < + +EOT + # # Convert the file. # $defaultType = 'other'; $includeFile = $path.$path_delim.'header'.$path_delim.'p'.lc($processor).'.inc'; +$defsFile = "pic" . lc($processor) . ".c"; open(HEADER, "<$includeFile") || die "$programName: Error: Cannot open include file $includeFile ($!)\n"; while (
) { - if (/^;-* (\S+) Bits/i) { - if (defined($alias{$1})) { - $defaultType = "bits $alias{$1}"; - } else { - $defaultType = "bits $1"; + if (/^;-+ (\S+) Bits/i) { + # also accept "UIE/UIR Bits" + foreach $name (split(/\//, $1)) { + if (defined($alias{$name})) { + $defaultType = "bits $alias{$name}"; + } else { + $defaultType = "bits $name"; + } } s/;/\/\//; $body .= "$_"; - } elsif (/^;-* Register Files/i) { + } elsif (/^;-+ Register Files/i) { $defaultType = 'sfr'; s/;/\/\//; $body .= "$_"; - } elsif (/^;=*/i) { + } elsif (/^;=+/i) { $defaultType = ''; s/;/\/\//; $body .= "$_"; @@ -203,7 +219,8 @@ while (
) { } else { $addresses .= sprintf("#define %s_ADDR\t0x%s\n", $name, $value); } - $body .= sprintf("sfr at %-30s %s;$rest\n", "${name}_ADDR", $name); + $body .= sprintf("extern sfr __at %-30s $name;$rest\n", "(${name}_ADDR)" ); + $c_head .= sprintf("sfr __at %-30s $name;\n", "(${name}_ADDR)"); $addr{"p$processor", "$name"} = "0x$value"; } elsif ($type eq 'volatile') { # @@ -213,7 +230,8 @@ while (
) { $pragmas .= sprintf("#pragma memmap %s_ADDR %s_ADDR " . "SFR %s\t// %s\n", $name, $name, $bitmask, $name); - $body .= sprintf("data at %-30s %s;$rest\n", "${name}_ADDR volatile char", $name); + $body .= sprintf("extern data __at %-30s $name;$rest\n", "(${name}_ADDR) volatile char"); + $c_head .= sprintf("data __at %-30s $name;\n", "(${name}_ADDR) volatile char"); if (defined $addr{"p$processor", "$name"}) { $addresses .= sprintf("#define %s_ADDR\t0x%s\n", $name, $addr{"p$processor", "$name"}); } else { @@ -223,7 +241,13 @@ while (
) { ($junk, $register) = split(/\s/, $type); $bit = hex($value); $addr = $addr{"$register"}; - $body .= "BIT_AT(${register}_ADDR,$bit)\t$name;$rest\n"; + # prepare struct declaration + for ($k=0; $k < scalar @{$bits{"$register"}->{oct($bit)}}; $k++) { + $name = "" if ($bits{"$register"}->{oct($bit)} eq $name) + } + if ($name ne "") { + push @{$bits{"$register"}->{oct($bit)}}, $name; + } } else { # # Other registers, bits and/or configurations. @@ -249,8 +273,7 @@ while (
) { # $body .= "\n"; } elsif (/__MAXRAM\s+H'([0-9a-fA-F]+)'/) { - $maxram .= "//\n// Memory organization.\n//\n" - . sprintf("#pragma maxram 0x%s\n\n", $1); + $maxram .= "//\n// Memory organization.\n//\n"; $pragmas = $maxram . $ram{"p$processor"} . "\n" . $pragmas; @@ -287,21 +310,72 @@ $header .= <{oct($i)}}; + if ($max < scalar @names) { $max = scalar @names; } + if ($idx >= scalar @names) { + $structs .= " unsigned char :1;\n"; + } else { # (1 == scalar @names) { + $structs .= " unsigned char " . $names[$idx] . ":1;\n"; +# } else { +# $structs .= " union {\n"; +# foreach $name (@names) { +# $structs .= " unsigned char " . $name . ":1;\n"; +# } # foreach +# $structs .= " };\n"; + } + } # for + $structs .= " };\n"; + $idx++; + } while ($idx < $max); + $structs .= "} __${reg}_bits_t;\n"; + $structs .= "extern volatile __${reg}_bits_t __at(${reg}_ADDR) ${reg}_bits;\n\n"; + $c_head .= "volatile __${reg}_bits_t __at(${reg}_ADDR) ${reg}_bits;\n"; + + # emit defines for individual bits + for ($i=0; $i < 8; $i++) + { + @names = @{$bits{$reg}->{oct($i)}}; + foreach $field (@names) { + $structs .= sprintf("#define %-20s ${reg}_bits.$field\n", $field); + } # foreach + } + $structs .= "\n"; +} # foreach + print $header . $addresses . "\n" . $pragmas . "\n\n" - . $body + . $body . "\n" + . $structs . "#endif\n"; +open(DEFS, ">$defsFile") or die "Could not open $defsFile for writing."; +print DEFS $c_head . "\n"; +close DEFS; + sub Usage { print STDERR <