From 4e872a797f81595d5de790138bdec62f2bf175f0 Mon Sep 17 00:00:00 2001
From: Olivier DANET <odanet@caramail.com>
Date: Mon, 17 May 2021 14:47:14 +0200
Subject: [PATCH] target/zynqmp : Add AXI AP access port

The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs.

Change-Id: I6303331c217795657575de4759444938e775dee1
Signed-off-by: Olivier DANET <odanet@caramail.com>
Reviewed-on: http://openocd.zylin.com/6263
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---
 tcl/target/xilinx_zynqmp.cfg | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg
index b21603f62..e66289a70 100644
--- a/tcl/target/xilinx_zynqmp.cfg
+++ b/tcl/target/xilinx_zynqmp.cfg
@@ -92,6 +92,8 @@ for { set _core 0 } { $_core < $_cores } { incr _core } {
     eval $_command
 }
 
+target create uscale.axi mem_ap -dap uscale.dap -ap-num 0
+
 eval $_smp_command
 targets $_TARGETNAME.0
 
-- 
2.30.2