From 43cbf733800129fde1fc741e0bf5e11f3edfc86e Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 20 May 2016 23:29:11 +0200 Subject: [PATCH] Further Refactor stlink.h into correct places and files, create backend.h --- include/stlink.h | 67 +++++-------------------------------- include/stlink/backend.h | 33 ++++++++++++++++++ include/stlink/chipid.h | 2 +- include/stlink/reg.h | 7 ++++ src/chipid.c | 72 ++++++++++++++++++++-------------------- src/common.c | 68 ++++++++++++++++++------------------- src/flash_loader.c | 6 ++-- src/usb.c | 8 ++--- 8 files changed, 126 insertions(+), 137 deletions(-) create mode 100644 include/stlink/backend.h diff --git a/include/stlink.h b/include/stlink.h index 3b86005..72eebb7 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -51,30 +51,20 @@ extern "C" { /* cortex core ids */ // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 -#define CORE_M3_R1 0x1BA00477 -#define CORE_M3_R2 0x4BA00477 -#define CORE_M4_R0 0x2BA01477 // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 #define STM32_SRAM_BASE 0x20000000 - /* Cortex™-M3 Technical Reference Manual */ - /* Debug Halting Control and Status Register */ -#define DHCSR 0xe000edf0 -#define DCRSR 0xe000edf4 -#define DCRDR 0xe000edf8 -#define DBGKEY 0xa05f0000 - /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 - enum flash_type { - FLASH_TYPE_UNKNOWN = 0, - FLASH_TYPE_F0, - FLASH_TYPE_L0, - FLASH_TYPE_F4, - FLASH_TYPE_L4, + enum stlink_flash_type { + STLINK_FLASH_TYPE_UNKNOWN = 0, + STLINK_FLASH_TYPE_F0, + STLINK_FLASH_TYPE_L0, + STLINK_FLASH_TYPE_F4, + STLINK_FLASH_TYPE_L4 }; typedef struct { @@ -123,34 +113,7 @@ typedef struct flash_loader { typedef struct _stlink stlink_t; - typedef struct _stlink_backend { - void (*close) (stlink_t * sl); - int (*exit_debug_mode) (stlink_t * sl); - int (*enter_swd_mode) (stlink_t * sl); - int (*enter_jtag_mode) (stlink_t * stl); - int (*exit_dfu_mode) (stlink_t * stl); - int (*core_id) (stlink_t * stl); - int (*reset) (stlink_t * stl); - int (*jtag_reset) (stlink_t * stl, int value); - int (*run) (stlink_t * stl); - int (*status) (stlink_t * stl); - int (*version) (stlink_t *sl); - int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*read_all_regs) (stlink_t *sl, reg * regp); - int (*read_reg) (stlink_t *sl, int r_idx, reg * regp); - int (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); - int (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); - int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp); - int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - int (*step) (stlink_t * stl); - int (*current_mode) (stlink_t * stl); - int (*force_debug) (stlink_t *sl); - int32_t (*target_voltage) (stlink_t *sl); - } stlink_backend_t; +#include "stlink/backend.h" struct _stlink { struct _stlink_backend *backend; @@ -171,20 +134,12 @@ typedef struct flash_loader { char serial[16]; int serial_size; -#define STM32_FLASH_PGSZ 1024 -#define STM32L_FLASH_PGSZ 256 - -#define STM32F4_FLASH_PGSZ 16384 -#define STM32F4_FLASH_SIZE (128 * 1024 * 8) - - enum flash_type flash_type; + enum stlink_flash_type flash_type; stm32_addr_t flash_base; size_t flash_size; size_t flash_pgsz; /* sram settings */ -#define STM32_SRAM_SIZE (8 * 1024) -#define STM32L_SRAM_SIZE (16 * 1024) stm32_addr_t sram_base; size_t sram_size; @@ -195,9 +150,6 @@ typedef struct flash_loader { struct stlink_version_ version; }; - //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose); - - // delegated functions... int stlink_enter_swd_mode(stlink_t *sl); int stlink_enter_jtag_mode(stlink_t *sl); int stlink_exit_debug_mode(stlink_t *sl); @@ -225,8 +177,6 @@ typedef struct flash_loader { int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); - - // unprocessed int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); @@ -249,7 +199,6 @@ typedef struct flash_loader { int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size); - int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); int stlink_load_device_params(stlink_t *sl); #include "stlink/sg.h" diff --git a/include/stlink/backend.h b/include/stlink/backend.h new file mode 100644 index 0000000..20b1c71 --- /dev/null +++ b/include/stlink/backend.h @@ -0,0 +1,33 @@ +#ifndef STLINK_BACKEND_H_ +#define STLINK_BACKEND_H_ + + typedef struct _stlink_backend { + void (*close) (stlink_t * sl); + int (*exit_debug_mode) (stlink_t * sl); + int (*enter_swd_mode) (stlink_t * sl); + int (*enter_jtag_mode) (stlink_t * stl); + int (*exit_dfu_mode) (stlink_t * stl); + int (*core_id) (stlink_t * stl); + int (*reset) (stlink_t * stl); + int (*jtag_reset) (stlink_t * stl, int value); + int (*run) (stlink_t * stl); + int (*status) (stlink_t * stl); + int (*version) (stlink_t *sl); + int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); + int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); + int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*read_all_regs) (stlink_t *sl, reg * regp); + int (*read_reg) (stlink_t *sl, int r_idx, reg * regp); + int (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); + int (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); + int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp); + int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); + int (*step) (stlink_t * stl); + int (*current_mode) (stlink_t * stl); + int (*force_debug) (stlink_t *sl); + int32_t (*target_voltage) (stlink_t *sl); + } stlink_backend_t; + +#endif /* STLINK_BACKEND_H_ */ diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 351bb55..a5012e3 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -61,7 +61,7 @@ enum stlink_stm32_chipids { struct stlink_chipid_params { uint32_t chip_id; char *description; - enum flash_type flash_type; + enum stlink_flash_type flash_type; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; diff --git a/include/stlink/reg.h b/include/stlink/reg.h index c6af166..917325f 100644 --- a/include/stlink/reg.h +++ b/include/stlink/reg.h @@ -5,4 +5,11 @@ #define STLINK_REG_CM3_FP_CTRL 0xE0002000 #define STLINK_REG_CM3_FP_COMP0 0xE0002008 +/* Cortex™-M3 Technical Reference Manual */ +/* Debug Halting Control and Status Register */ +#define STLINK_REG_DHCSR 0xe000edf0 +#define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 +#define STLINK_REG_DCRSR 0xe000edf4 +#define STLINK_REG_DCRDR 0xe000edf8 + #endif /* STLINK_REG_H_ */ diff --git a/src/chipid.c b/src/chipid.c index 423fbcb..c3f1a92 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -6,7 +6,7 @@ static const struct stlink_chipid_params devices[] = { //RM0385 and DS10916 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F7, .description = "F7 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff0f442, // section 41.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 @@ -16,7 +16,7 @@ static const struct stlink_chipid_params devices[] = { { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, .description = "F1 Medium-density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x5000, @@ -26,7 +26,7 @@ static const struct stlink_chipid_params devices[] = { { // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, .description = "F2 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ .flash_pagesize = 0x20000, .sram_size = 0x20000, @@ -36,7 +36,7 @@ static const struct stlink_chipid_params devices[] = { { // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, .description = "F1 Low-density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x2800, @@ -46,7 +46,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4, .description = "F4 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x30000, @@ -56,7 +56,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4_DSI, .description = "F46x and F47x device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x40000, @@ -66,7 +66,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4_HD, .description = "F42x and F43x device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x40000, @@ -76,7 +76,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4_LP, .description = "F4 device (low power)", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x10000, @@ -86,7 +86,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F411RE, .description = "F4 device (low power) - stm32f411re", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x20000, @@ -96,7 +96,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4_DE, .description = "F4 device (Dynamic Efficency)", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x18000, @@ -106,7 +106,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F1_HIGH, .description = "F1 High-density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x10000, @@ -118,7 +118,7 @@ static const struct stlink_chipid_params devices[] = { // not the sector write protection...) .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, .description = "L1 Med-density device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, .sram_size = 0x4000, @@ -128,7 +128,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_L1_CAT2, .description = "L1 Cat.2 device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, .sram_size = 0x8000, @@ -138,7 +138,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, .description = "L1 Medium-Plus-density device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ @@ -148,7 +148,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_L1_HIGH, .description = "L1 High-density device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ @@ -158,7 +158,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_L152_RE, .description = "L152RE", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ @@ -168,7 +168,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F1_CONN, .description = "F1 Connectivity line device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x10000, @@ -178,7 +178,7 @@ static const struct stlink_chipid_params devices[] = { {//Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, .description = "F1 Medium/Low-density Value Line device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x2000,//0x1000 for low density devices @@ -189,7 +189,7 @@ static const struct stlink_chipid_params devices[] = { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. .chip_id = STLINK_CHIPID_STM32_F446, .description = "F446 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x20000, .sram_size = 0x20000, @@ -200,7 +200,7 @@ static const struct stlink_chipid_params devices[] = { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. .chip_id = STLINK_CHIPID_STM32_F410, .description = "F410 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x4000, .sram_size = 0x8000, @@ -212,7 +212,7 @@ static const struct stlink_chipid_params devices[] = { // Support based on DM00043574.pdf (RM0316) document. .chip_id = STLINK_CHIPID_STM32_F3, .description = "F3 device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -224,7 +224,7 @@ static const struct stlink_chipid_params devices[] = { // Support based on 303 above (37x and 30x have same memory map) .chip_id = STLINK_CHIPID_STM32_F37x, .description = "F3 device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -234,7 +234,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, .description = "F1 High-density value line device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x8000, @@ -244,7 +244,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F1_XL, .description = "F1 XL-density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x18000, @@ -256,7 +256,7 @@ static const struct stlink_chipid_params devices[] = { //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0_CAN, .description = "F07x device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 @@ -268,7 +268,7 @@ static const struct stlink_chipid_params devices[] = { //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0, .description = "F0 device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 @@ -278,7 +278,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F09X, .description = "F09X device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) @@ -290,7 +290,7 @@ static const struct stlink_chipid_params devices[] = { //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F04, .description = "F04x device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 @@ -302,7 +302,7 @@ static const struct stlink_chipid_params devices[] = { //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0_SMALL, .description = "F0 small device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 @@ -313,7 +313,7 @@ static const struct stlink_chipid_params devices[] = { // STM32F30x .chip_id = STLINK_CHIPID_STM32_F3_SMALL, .description = "F3 small device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -325,7 +325,7 @@ static const struct stlink_chipid_params devices[] = { // RM0367,RM0377 documents was used to find these parameters .chip_id = STLINK_CHIPID_STM32_L0, .description = "L0x3 device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, .sram_size = 0x2000, @@ -337,7 +337,7 @@ static const struct stlink_chipid_params devices[] = { // RM0367,RM0377 documents was used to find these parameters .chip_id = STLINK_CHIPID_STM32_L0_CAT5, .description = "L0x Category 5 device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, .sram_size = 0x5000, @@ -349,7 +349,7 @@ static const struct stlink_chipid_params devices[] = { // RM0367,RM0377 documents was used to find these parameters .chip_id = STLINK_CHIPID_STM32_L0_CAT2, .description = "L0x Category 2 device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, .sram_size = 0x2000, @@ -361,7 +361,7 @@ static const struct stlink_chipid_params devices[] = { // RM0364 document was used to find these parameters .chip_id = STLINK_CHIPID_STM32_F334, .description = "F334 device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0x3000, @@ -373,7 +373,7 @@ static const struct stlink_chipid_params devices[] = { // Support based on DM00043574.pdf (RM0316) document rev 5. .chip_id = STLINK_CHIPID_STM32_F303_HIGH, .description = "F303 high density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register .flash_pagesize = 0x800, // 4.2.1 Flash memory organization .sram_size = 0x10000, // 3.3 Embedded SRAM @@ -385,7 +385,7 @@ static const struct stlink_chipid_params devices[] = { // From RM0351. .chip_id = STLINK_CHIPID_STM32_L4, .description = "L4 device", - .flash_type = FLASH_TYPE_L4, + .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671) .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) // SRAM1 is "up to" 96k in the standard Cortex-M memory map; diff --git a/src/common.c b/src/common.c index 493f1b9..2899f29 100644 --- a/src/common.c +++ b/src/common.c @@ -185,9 +185,9 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t reg, res; - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) reg = FLASH_F4_CR; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) reg = STM32L4_FLASH_CR; else reg = FLASH_CR; @@ -204,9 +204,9 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ uint32_t cr_lock_shift, cr = read_flash_cr(sl); - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) cr_lock_shift = FLASH_F4_CR_LOCK; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_lock_shift = STM32L4_FLASH_CR_LOCK; else cr_lock_shift = FLASH_CR_LOCK; @@ -221,9 +221,9 @@ static void unlock_flash(stlink_t *sl) { an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) key_reg = FLASH_F4_KEYR; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) key_reg = STM32L4_FLASH_KEYR; else key_reg = FLASH_KEYR; @@ -249,10 +249,10 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n; - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; } else { @@ -270,10 +270,10 @@ static void set_flash_cr_pg(stlink_t *sl) { x = read_flash_cr(sl); - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= 1 << STM32L4_FLASH_CR_PG; @@ -288,9 +288,9 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { uint32_t cr_reg, n; - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) cr_reg = FLASH_F4_CR; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_reg = STM32L4_FLASH_CR; else cr_reg = FLASH_CR; @@ -312,10 +312,10 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { static void set_flash_cr_mer(stlink_t *sl) { uint32_t val, cr_reg, cr_mer; - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { @@ -331,10 +331,10 @@ static void set_flash_cr_mer(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { uint32_t val, cr_reg, cr_mer; - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { @@ -350,10 +350,10 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { static void set_flash_cr_strt(stlink_t *sl) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = 1 << STM32L4_FLASH_CR_STRT; } else { @@ -375,9 +375,9 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res, sr_reg; - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) sr_reg = FLASH_F4_SR; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_reg = STM32L4_FLASH_SR; else sr_reg = FLASH_SR; @@ -390,9 +390,9 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) sr_busy_shift = FLASH_F4_SR_BSY; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_busy_shift = STM32L4_FLASH_SR_BSY; else sr_busy_shift = FLASH_SR_BSY; @@ -491,7 +491,7 @@ int stlink_exit_debug_mode(stlink_t *sl) { int ret; DLOG("*** stlink_exit_debug_mode ***\n"); - ret = stlink_write_debug32(sl, DHCSR, DBGKEY); + ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); if (ret == -1) return ret; @@ -588,7 +588,7 @@ int stlink_load_device_params(stlink_t *sl) { return -1; } - if (params->flash_type == FLASH_TYPE_UNKNOWN) { + if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { WLOG("Invalid flash type, please check device declaration\n"); return -1; } @@ -800,7 +800,7 @@ int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { DLOG("*** stlink_read_unsupported_reg\n"); DLOG(" (%d) ***\n", r_idx); - /* Convert to values used by DCRSR */ + /* Convert to values used by STLINK_REG_DCRSR */ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ r_convert = 0x14; } else if (r_idx == 0x40) { /* FPSCR */ @@ -821,7 +821,7 @@ int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *reg DLOG("*** stlink_write_unsupported_reg\n"); DLOG(" (%d) ***\n", r_idx); - /* Convert to values used by DCRSR */ + /* Convert to values used by STLINK_REG_DCRSR */ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ r_convert = r_idx; /* The backend function handles this */ } else if (r_idx == 0x40) { /* FPSCR */ @@ -1237,7 +1237,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L4) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1283,7 +1283,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } else if (sl->flash_type == FLASH_TYPE_L0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; uint32_t flash_regs_base; @@ -1351,7 +1351,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == FLASH_TYPE_F0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1383,7 +1383,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->flash_type == FLASH_TYPE_L0) { + if (sl->flash_type == STLINK_FLASH_TYPE_L0) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1581,7 +1581,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (eraseonly) return 0; - if ((sl->flash_type == FLASH_TYPE_F4) || (sl->flash_type == FLASH_TYPE_L4)) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4/L4\n"); @@ -1641,7 +1641,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END - else if (sl->flash_type == FLASH_TYPE_L0) { + else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { /* use fast word write. todo: half page. */ uint32_t val; uint32_t flash_regs_base; @@ -1716,7 +1716,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == FLASH_TYPE_F0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0) { ILOG("Starting Flash write for VL/F0/F3 core id\n"); /* flash loader initialization */ if (stlink_flash_loader_init(sl, &fl) == -1) { @@ -1774,7 +1774,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { return -1; } - if (sl->flash_type == FLASH_TYPE_L0) + if (sl->flash_type == STLINK_FLASH_TYPE_L0) erased_pattern = 0x00; else erased_pattern = 0xff; diff --git a/src/flash_loader.c b/src/flash_loader.c index 23f235b..eaba6d3 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -265,15 +265,15 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return -1; } - if (sl->flash_type == FLASH_TYPE_F0) { + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; - } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L0) { count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { count = size / sizeof(uint64_t); if (size % sizeof(uint64_t)) ++count; diff --git a/src/usb.c b/src/usb.c index b303998..3a72035 100644 --- a/src/usb.c +++ b/src/usb.c @@ -567,11 +567,11 @@ int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { sl->q_buf[i] = 0; } - ret = _stlink_usb_write_mem32(sl, DCRSR, 4); + ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); if (ret == -1) return ret; - _stlink_usb_read_mem32(sl, DCRDR, 4); + _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); if (ret == -1) return ret; @@ -648,7 +648,7 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg write_uint32(sl->q_buf, val); - ret = _stlink_usb_write_mem32(sl, DCRDR, 4); + ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); if (ret == -1) return ret; @@ -657,7 +657,7 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg sl->q_buf[2] = 0x01; sl->q_buf[3] = 0; - return _stlink_usb_write_mem32(sl, DCRSR, 4); + return _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); } int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { -- 2.47.2