From 43974f34adadb0b8af908e364681fb3025df3e7e Mon Sep 17 00:00:00 2001
From: jnosky <Jerry@CGS_Office.(none)>
Date: Thu, 10 Nov 2011 20:09:20 -0500
Subject: [PATCH] Added the IO_Toggle and discovery demo samples including a
 working make

Can now build and flash these these samples
---
 exampleF4/Projects/IO_Toggle/Makefile         |   31 +
 exampleF4/Projects/IO_Toggle/main.c           |  143 ++
 exampleF4/Projects/IO_Toggle/readme.txt       |   91 +
 .../Projects/IO_Toggle/startup_stm32f4xx.s    |  509 ++++
 exampleF4/Projects/IO_Toggle/stm32_flash.ld   |  170 ++
 .../Projects/IO_Toggle/stm32f4_discovery.h    |  158 ++
 exampleF4/Projects/IO_Toggle/stm32f4xx_conf.h |   94 +
 exampleF4/Projects/IO_Toggle/stm32f4xx_it.c   |  167 ++
 exampleF4/Projects/IO_Toggle/stm32f4xx_it.h   |   54 +
 .../Projects/IO_Toggle/system_stm32f4xx.c     |  545 ++++
 exampleF4/Projects/discovery_demo/Makefile    |   61 +
 .../discovery_demo/Release_Notes.html         |  151 ++
 .../discovery_demo/STM32F4-Discovery_Demo.bin |  Bin 0 -> 31620 bytes
 .../discovery_demo/STM32F4-Discovery_Demo.elf |  Bin 0 -> 243586 bytes
 exampleF4/Projects/discovery_demo/main.c      |  509 ++++
 exampleF4/Projects/discovery_demo/main.h      |   62 +
 exampleF4/Projects/discovery_demo/selftest.c  |  808 ++++++
 exampleF4/Projects/discovery_demo/selftest.h  |   41 +
 .../discovery_demo/startup_stm32f4xx.s        |  509 ++++
 .../Projects/discovery_demo/stm32_flash.ld    |  170 ++
 .../Projects/discovery_demo/stm32f4xx_conf.h  |   94 +
 .../Projects/discovery_demo/stm32f4xx_it.c    |  320 +++
 .../Projects/discovery_demo/stm32f4xx_it.h    |   54 +
 .../discovery_demo/system_stm32f4xx.c         |  566 +++++
 exampleF4/Projects/discovery_demo/usb_bsp.c   |  382 +++
 exampleF4/Projects/discovery_demo/usb_conf.h  |  252 ++
 exampleF4/Projects/discovery_demo/usb_core.c  | 2187 +++++++++++++++++
 exampleF4/Projects/discovery_demo/usb_core.h  |  408 +++
 exampleF4/Projects/discovery_demo/usbd_conf.h |   93 +
 exampleF4/Projects/discovery_demo/usbd_desc.c |  313 +++
 exampleF4/Projects/discovery_demo/usbd_desc.h |  114 +
 exampleF4/Projects/discovery_demo/usbd_usr.c  |  238 ++
 32 files changed, 9294 insertions(+)
 create mode 100644 exampleF4/Projects/IO_Toggle/Makefile
 create mode 100644 exampleF4/Projects/IO_Toggle/main.c
 create mode 100644 exampleF4/Projects/IO_Toggle/readme.txt
 create mode 100644 exampleF4/Projects/IO_Toggle/startup_stm32f4xx.s
 create mode 100644 exampleF4/Projects/IO_Toggle/stm32_flash.ld
 create mode 100644 exampleF4/Projects/IO_Toggle/stm32f4_discovery.h
 create mode 100644 exampleF4/Projects/IO_Toggle/stm32f4xx_conf.h
 create mode 100644 exampleF4/Projects/IO_Toggle/stm32f4xx_it.c
 create mode 100644 exampleF4/Projects/IO_Toggle/stm32f4xx_it.h
 create mode 100644 exampleF4/Projects/IO_Toggle/system_stm32f4xx.c
 create mode 100644 exampleF4/Projects/discovery_demo/Makefile
 create mode 100644 exampleF4/Projects/discovery_demo/Release_Notes.html
 create mode 100644 exampleF4/Projects/discovery_demo/STM32F4-Discovery_Demo.bin
 create mode 100644 exampleF4/Projects/discovery_demo/STM32F4-Discovery_Demo.elf
 create mode 100644 exampleF4/Projects/discovery_demo/main.c
 create mode 100644 exampleF4/Projects/discovery_demo/main.h
 create mode 100644 exampleF4/Projects/discovery_demo/selftest.c
 create mode 100644 exampleF4/Projects/discovery_demo/selftest.h
 create mode 100644 exampleF4/Projects/discovery_demo/startup_stm32f4xx.s
 create mode 100644 exampleF4/Projects/discovery_demo/stm32_flash.ld
 create mode 100644 exampleF4/Projects/discovery_demo/stm32f4xx_conf.h
 create mode 100644 exampleF4/Projects/discovery_demo/stm32f4xx_it.c
 create mode 100644 exampleF4/Projects/discovery_demo/stm32f4xx_it.h
 create mode 100644 exampleF4/Projects/discovery_demo/system_stm32f4xx.c
 create mode 100644 exampleF4/Projects/discovery_demo/usb_bsp.c
 create mode 100644 exampleF4/Projects/discovery_demo/usb_conf.h
 create mode 100644 exampleF4/Projects/discovery_demo/usb_core.c
 create mode 100644 exampleF4/Projects/discovery_demo/usb_core.h
 create mode 100644 exampleF4/Projects/discovery_demo/usbd_conf.h
 create mode 100644 exampleF4/Projects/discovery_demo/usbd_desc.c
 create mode 100644 exampleF4/Projects/discovery_demo/usbd_desc.h
 create mode 100644 exampleF4/Projects/discovery_demo/usbd_usr.c

diff --git a/exampleF4/Projects/IO_Toggle/Makefile b/exampleF4/Projects/IO_Toggle/Makefile
new file mode 100644
index 0000000..ef8860a
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/Makefile
@@ -0,0 +1,31 @@
+EXECUTABLE=IO_Toggle.elf
+BIN_IMAGE=IO_Toggle.bin
+
+CC=arm-none-eabi-gcc
+OBJCOPY=arm-none-eabi-objcopy
+
+CFLAGS=-g -O2 -mlittle-endian -mthumb
+CFLAGS+=-mcpu=cortex-m4	
+CFLAGS+=-ffreestanding -nostdlib
+
+# to run from FLASH
+CFLAGS+=-Wl,-T,stm32_flash.ld
+
+# stm32f4_discovery lib
+CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc
+CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/device_support
+CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/core_support
+
+all: $(BIN_IMAGE)
+
+$(BIN_IMAGE): $(EXECUTABLE)
+	$(OBJCOPY) -O binary $^ $@
+
+$(EXECUTABLE): main.c system_stm32f4xx.c startup_stm32f4xx.s stm32f4xx_it.c 
+	$(CC) $(CFLAGS) $^ -o $@  -L../../STM32F4xx_StdPeriph_Driver/build -lSTM32F4xx_StdPeriph_Driver
+
+clean:
+	rm -rf $(EXECUTABLE)
+	rm -rf $(BIN_IMAGE)
+
+.PHONY: all clean
diff --git a/exampleF4/Projects/IO_Toggle/main.c b/exampleF4/Projects/IO_Toggle/main.c
new file mode 100644
index 0000000..5da875f
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/main.c
@@ -0,0 +1,143 @@
+/**
+  ******************************************************************************
+  * @file    IO_Toggle/main.c 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4_discovery.h"
+#include "stm32f4xx_conf.h"
+
+/** @addtogroup STM32F4_Discovery_Peripheral_Examples
+  * @{
+  */
+
+/** @addtogroup IO_Toggle
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+GPIO_InitTypeDef  GPIO_InitStructure;
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+void Delay(__IO uint32_t nCount);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Main program
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  /*!< At this stage the microcontroller clock setting is already configured, 
+       this is done through SystemInit() function which is called from startup
+       file (startup_stm32f4xx.s) before to branch to application main.
+       To reconfigure the default setting of SystemInit() function, refer to
+        system_stm32f4xx.c file
+     */
+
+  /* GPIOD Periph clock enable */
+  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
+
+  /* Configure PD12, PD13, PD14 and PD15 in output pushpull mode */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  while (1)
+  {
+    /* PD12 to be toggled */
+    GPIO_SetBits(GPIOD, GPIO_Pin_12);
+    
+    /* Insert delay */
+    Delay(0x3FFFFF);
+    
+    /* PD13 to be toggled */
+    GPIO_SetBits(GPIOD, GPIO_Pin_13);
+    
+    /* Insert delay */
+    Delay(0x3FFFFF);
+  
+    /* PD14 to be toggled */
+    GPIO_SetBits(GPIOD, GPIO_Pin_14);
+    
+    /* Insert delay */
+    Delay(0x3FFFFF);
+    
+    /* PD15 to be toggled */
+    GPIO_SetBits(GPIOD, GPIO_Pin_15);
+    
+    /* Insert delay */
+    Delay(0x7FFFFF);
+    
+    GPIO_ResetBits(GPIOD, GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15);
+    
+    /* Insert delay */
+    Delay(0xFFFFFF);
+  }
+}
+
+/**
+  * @brief  Delay Function.
+  * @param  nCount:specifies the Delay time length.
+  * @retval None
+  */
+void Delay(__IO uint32_t nCount)
+{
+  while(nCount--)
+  {
+  }
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+#endif
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/IO_Toggle/readme.txt b/exampleF4/Projects/IO_Toggle/readme.txt
new file mode 100644
index 0000000..fda5b2e
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/readme.txt
@@ -0,0 +1,91 @@
+/**
+  @page GPIO_IOToggle GPIO IO Toggle example
+  
+  @verbatim
+  ******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
+  * @file    IO_Toggle/readme.txt 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Description of the GPIO IO Toggle example.
+  ******************************************************************************
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  ******************************************************************************
+   @endverbatim
+
+@par Example Description 
+
+This example describes how to toggle the GPIO pins connected on AHB bus.
+
+PD12, PD13, PD14 and PD15 (configured in output pushpull mode) toggles in a forever loop.
+ - Set PD12, PD13, PD14 and PD15 by setting corresponding bits in BSRRL register
+ - Reset PD12, PD13, PD14 and PD15  by setting corresponding bits in BSRRH register
+
+In this example, HCLK is configured at 168 MHz.
+
+@par Directory contents 
+
+  - IO_Toggle/stm32f4xx_conf.h    Library Configuration file
+  - IO_Toggle/stm32f4xx_it.c      Interrupt handlers
+  - IO_Toggle/stm32f4xx_it.h      Interrupt handlers header file
+  - IO_Toggle/main.c              Main program
+  - IO_Toggle/system_stm32f4xx.c  STM32F4xx system source file
+
+@par Hardware and Software environment
+
+  - This example runs on STM32F4xx Devices Revision A.
+
+  - This example has been tested with STM32F4-Discovery (MB997) RevA and can be
+    easily tailored to any other development board
+
+  - STM32F4-Discovery
+    - LED4, LED3, LED5 and LED6 are connected respectively to PD.12, PD.13, PD.14 and PD.15.
+      
+
+@par How to use it ? 
+
+In order to make the program work, you must do the following :
+
+ + EWARM
+    - Open the IO_Toggle.eww workspace 
+    - Rebuild all files: Project->Rebuild all
+    - Load project image: Project->Debug
+    - Run program: Debug->Go(F5)
+
+ + MDK-ARM
+    - Open the IO_Toggle.uvproj project
+    - Rebuild all files: Project->Rebuild all target files
+    - Load project image: Debug->Start/Stop Debug Session
+    - Run program: Debug->Run (F5)    
+
+ + TASKING
+    - Open TASKING toolchain.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to  TASKING workspace directory and select the project "IO_Toggle"   
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+ + TrueSTUDIO
+    - Open the TrueSTUDIO toolchain.
+    - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace 
+      directory.
+    - Click on File->Import, select General->'Existing Projects into Workspace' 
+      and then click "Next". 
+    - Browse to the TrueSTUDIO workspace directory and select the project "IO_Toggle" 
+    - Rebuild all project files: Select the project in the "Project explorer" 
+      window then click on Project->build project menu.
+    - Run program: Select the project in the "Project explorer" window then click 
+      Run->Debug (F11)
+
+
+    
+ * <h3><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h3>
+ */
diff --git a/exampleF4/Projects/IO_Toggle/startup_stm32f4xx.s b/exampleF4/Projects/IO_Toggle/startup_stm32f4xx.s
new file mode 100644
index 0000000..ce5360f
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/startup_stm32f4xx.s
@@ -0,0 +1,509 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f4xx.s
+  * @author    MCD Application Team
+  * @version   V1.0.0
+  * @date      30-September-2011
+  * @brief     STM32F4xx Devices vector table for RIDE7 toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM mounted on 
+  *                  STM324xG-EVAL board to be used as data memory (optional, 
+  *                  to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      
+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          
+  .word     RCC_IRQHandler                    /* RCC                          */                                            
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          
+  .word     TIM2_IRQHandler                   /* TIM2                         */                   
+  .word     TIM3_IRQHandler                   /* TIM3                         */                   
+  .word     TIM4_IRQHandler                   /* TIM4                         */                   
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            
+  .word     SPI1_IRQHandler                   /* SPI1                         */                   
+  .word     SPI2_IRQHandler                   /* SPI2                         */                   
+  .word     USART1_IRQHandler                 /* USART1                       */                   
+  .word     USART2_IRQHandler                 /* USART2                       */                   
+  .word     USART3_IRQHandler                 /* USART3                       */                   
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
+  .word     FSMC_IRQHandler                   /* FSMC                         */                   
+  .word     SDIO_IRQHandler                   /* SDIO                         */                   
+  .word     TIM5_IRQHandler                   /* TIM5                         */                   
+  .word     SPI3_IRQHandler                   /* SPI3                         */                   
+  .word     UART4_IRQHandler                  /* UART4                        */                   
+  .word     UART5_IRQHandler                  /* UART5                        */                   
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .word     ETH_IRQHandler                    /* Ethernet                     */                   
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .word     USART6_IRQHandler                 /* USART6                       */                    
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .word     DCMI_IRQHandler                   /* DCMI                         */                   
+  .word     CRYP_IRQHandler                   /* CRYP crypto                  */                   
+  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .word     FPU_IRQHandler                    /* FPU                          */                         
+                         
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+      
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FSMC_IRQHandler            
+   .thumb_set FSMC_IRQHandler,Default_Handler
+                     
+   .weak      SDIO_IRQHandler            
+   .thumb_set SDIO_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+            
+   .weak      ETH_IRQHandler      
+   .thumb_set ETH_IRQHandler,Default_Handler
+                  
+   .weak      ETH_WKUP_IRQHandler                  
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+            
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                  
+   .weak      DCMI_IRQHandler            
+   .thumb_set DCMI_IRQHandler,Default_Handler
+                     
+   .weak      CRYP_IRQHandler            
+   .thumb_set CRYP_IRQHandler,Default_Handler
+               
+   .weak      HASH_RNG_IRQHandler                  
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler  
+   
+/*******************   (C)   COPYRIGHT   2011   STMicroelectronics   *****END   OF   FILE****/
diff --git a/exampleF4/Projects/IO_Toggle/stm32_flash.ld b/exampleF4/Projects/IO_Toggle/stm32_flash.ld
new file mode 100644
index 0000000..1a0b4b8
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F407VG Device with
+**                1024KByte FLASH, 192KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000;    /* end of 128K RAM on AHB bus*/
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/exampleF4/Projects/IO_Toggle/stm32f4_discovery.h b/exampleF4/Projects/IO_Toggle/stm32f4_discovery.h
new file mode 100644
index 0000000..c6fec42
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/stm32f4_discovery.h
@@ -0,0 +1,158 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4_discovery.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   This file contains definitions for STM32F4-Discovery Kit's Leds and 
+  *          push-button hardware resources.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************  
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4_DISCOVERY_H
+#define __STM32F4_DISCOVERY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+                                              
+/* Includes ------------------------------------------------------------------*/
+ #include "stm32f4xx.h"
+   
+/** @addtogroup Utilities
+  * @{
+  */
+  
+/** @addtogroup STM32F4_DISCOVERY
+  * @{
+  */
+      
+/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL
+  * @{
+  */ 
+
+/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types
+  * @{
+  */
+typedef enum 
+{
+  LED4 = 0,
+  LED3 = 1,
+  LED5 = 2,
+  LED6 = 3
+} Led_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_USER = 0,
+} Button_TypeDef;
+
+typedef enum 
+{  
+  BUTTON_MODE_GPIO = 0,
+  BUTTON_MODE_EXTI = 1
+} ButtonMode_TypeDef;     
+/**
+  * @}
+  */ 
+
+/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants
+  * @{
+  */ 
+
+/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_LED
+  * @{
+  */
+#define LEDn                             4
+
+#define LED4_PIN                         GPIO_Pin_12
+#define LED4_GPIO_PORT                   GPIOD
+#define LED4_GPIO_CLK                    RCC_AHB1Periph_GPIOD  
+  
+#define LED3_PIN                         GPIO_Pin_13
+#define LED3_GPIO_PORT                   GPIOD
+#define LED3_GPIO_CLK                    RCC_AHB1Periph_GPIOD  
+  
+#define LED5_PIN                         GPIO_Pin_14
+#define LED5_GPIO_PORT                   GPIOD
+#define LED5_GPIO_CLK                    RCC_AHB1Periph_GPIOD  
+  
+#define LED6_PIN                         GPIO_Pin_15
+#define LED6_GPIO_PORT                   GPIOD
+#define LED6_GPIO_CLK                    RCC_AHB1Periph_GPIOD
+/**
+  * @}
+  */ 
+  
+/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_BUTTON
+  * @{
+  */  
+#define BUTTONn                          1  
+
+/**
+ * @brief Wakeup push-button
+ */
+#define USER_BUTTON_PIN                GPIO_Pin_0
+#define USER_BUTTON_GPIO_PORT          GPIOA
+#define USER_BUTTON_GPIO_CLK           RCC_AHB1Periph_GPIOA
+#define USER_BUTTON_EXTI_LINE          EXTI_Line0
+#define USER_BUTTON_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOA
+#define USER_BUTTON_EXTI_PIN_SOURCE    EXTI_PinSource0
+#define USER_BUTTON_EXTI_IRQn          EXTI0_IRQn 
+/**
+  * @}
+  */ 
+  
+/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros
+  * @{
+  */  
+/**
+  * @}
+  */ 
+
+
+/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions
+  * @{
+  */
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4_DISCOVERY_H */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/IO_Toggle/stm32f4xx_conf.h b/exampleF4/Projects/IO_Toggle/stm32f4xx_conf.h
new file mode 100644
index 0000000..abd159f
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/stm32f4xx_conf.h
@@ -0,0 +1,94 @@
+/**
+  ******************************************************************************
+  * @file    IO_Toggle/stm32f4xx_conf.h  
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_CONF_H
+#define __STM32F4xx_CONF_H
+
+#if defined  (HSE_VALUE)
+/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
+ #undef HSE_VALUE
+ #define HSE_VALUE    ((uint32_t)8000000) 
+#endif /* HSE_VALUE */
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f4xx_adc.h"
+#include "stm32f4xx_can.h"
+#include "stm32f4xx_crc.h"
+#include "stm32f4xx_cryp.h"
+#include "stm32f4xx_dac.h"
+#include "stm32f4xx_dbgmcu.h"
+#include "stm32f4xx_dcmi.h"
+#include "stm32f4xx_dma.h"
+#include "stm32f4xx_exti.h"
+#include "stm32f4xx_flash.h"
+#include "stm32f4xx_fsmc.h"
+#include "stm32f4xx_hash.h"
+#include "stm32f4xx_gpio.h"
+#include "stm32f4xx_i2c.h"
+#include "stm32f4xx_iwdg.h"
+#include "stm32f4xx_pwr.h"
+#include "stm32f4xx_rcc.h"
+#include "stm32f4xx_rng.h"
+#include "stm32f4xx_rtc.h"
+#include "stm32f4xx_sdio.h"
+#include "stm32f4xx_spi.h"
+#include "stm32f4xx_syscfg.h"
+#include "stm32f4xx_tim.h"
+#include "stm32f4xx_usart.h"
+#include "stm32f4xx_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* If an external clock source is used, then the value of the following define 
+   should be set to the value of the external clock source, else, if no external 
+   clock is used, keep this define commented */
+/*#define I2S_EXTERNAL_CLOCK_VAL   12288000 */ /* Value of the external clock in Hz */
+
+
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F4xx_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/IO_Toggle/stm32f4xx_it.c b/exampleF4/Projects/IO_Toggle/stm32f4xx_it.c
new file mode 100644
index 0000000..ceac51a
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/stm32f4xx_it.c
@@ -0,0 +1,167 @@
+/**
+  ******************************************************************************
+  * @file    IO_Toggle/stm32f4xx_it.c 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_it.h"
+
+/** @addtogroup STM32F4_Discovery_Peripheral_Examples
+  * @{
+  */
+
+/** @addtogroup IO_Toggle
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M4 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief   This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSVC exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*                 STM32F4xx Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f4xx.s).                                               */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/IO_Toggle/stm32f4xx_it.h b/exampleF4/Projects/IO_Toggle/stm32f4xx_it.h
new file mode 100644
index 0000000..74f17c9
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/stm32f4xx_it.h
@@ -0,0 +1,54 @@
+/**
+  ******************************************************************************
+  * @file    GPIO/IOToggle/stm32f4xx_it.h 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/IO_Toggle/system_stm32f4xx.c b/exampleF4/Projects/IO_Toggle/system_stm32f4xx.c
new file mode 100644
index 0000000..b058084
--- /dev/null
+++ b/exampleF4/Projects/IO_Toggle/system_stm32f4xx.c
@@ -0,0 +1,545 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F4xx devices,
+  *          and is generated by the clock configuration tool
+  *          stm32f4xx_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define
+  *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F4xx device revision    | Rev A
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 168000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 168000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 336
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        High Performance mode                  | Enabled
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 5
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | OFF
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f4xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM324xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      8
+#define PLL_N      336
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      7
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 168000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable high performance mode, System frequency up to 168 MHz */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_PMODE;  
+
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM324xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 | 
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 | 
+ | PD4  <-> FSMC_NOE | PE3  <-> FSMC_A19  | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 | 
+ | PD5  <-> FSMC_NWE | PE4  <-> FSMC_A20  | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 | 
+ | PD8  <-> FSMC_D13 | PE7  <-> FSMC_D4   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 | 
+ | PD9  <-> FSMC_D14 | PE8  <-> FSMC_D5   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 | 
+ | PD10 <-> FSMC_D15 | PE9  <-> FSMC_D6   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | 
+ | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8   | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9   | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE13 <-> FSMC_D10  |------------------+
+ | PD15 <-> FSMC_D1  | PE14 <-> FSMC_D11  |
+ |                   | PE15 <-> FSMC_D12  |
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xaaaa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xffff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00cc0cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa828a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc3cf;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010603;//0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 3;//0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 6;//4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
diff --git a/exampleF4/Projects/discovery_demo/Makefile b/exampleF4/Projects/discovery_demo/Makefile
new file mode 100644
index 0000000..782f982
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/Makefile
@@ -0,0 +1,61 @@
+EXECUTABLE=STM32F4-Discovery_Demo.elf
+BIN_IMAGE=STM32F4-Discovery_Demo.bin
+
+CC=arm-none-eabi-gcc
+OBJCOPY=arm-none-eabi-objcopy
+
+CFLAGS=-g -O2 -mlittle-endian -mthumb
+CFLAGS+=-mcpu=cortex-m4
+CFLAGS+=-ffreestanding -nostdlib
+
+#usb_conf.h
+CFLAGS+=-DUSE_USB_OTG_FS=1
+
+# to run from FLASH
+CFLAGS+=-Wl,-T,stm32_flash.ld
+
+CFLAGS+=-I./
+
+# stm32f4_discovery lib
+CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc
+CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/device_support
+CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/core_support
+
+#STM32_USB_Device_Library
+CFLAGS+=-I../../STM32_USB_Device_Library/Class/hid/inc
+CFLAGS+=-I../../STM32_USB_Device_Library/Core/inc
+
+#STM32_USB_OTG_Driver
+CFLAGS+=-I../../STM32_USB_OTG_Driver/inc
+
+#STM32F4xx_StdPeriph_Driver\inc
+CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc
+
+#Utilities
+CFLAGS+=-I../../Utilities/STM32F4-Discovery
+
+all: $(BIN_IMAGE)
+
+$(BIN_IMAGE): $(EXECUTABLE)
+	$(OBJCOPY) -O binary $^ $@
+
+$(EXECUTABLE): main.c selftest.c system_stm32f4xx.c startup_stm32f4xx.s stm32f4xx_it.c \
+	usb_bsp.c usbd_desc.c usbd_usr.c usb_core.c \
+	../../Utilities/STM32F4-Discovery/stm32f4_discovery.c \
+	../../Utilities/STM32F4-Discovery/stm32f4_discovery_audio_codec.c \
+	../../Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.c \
+	../../STM32_USB_OTG_Driver/src/usb_dcd_int.c \
+	../../STM32_USB_OTG_Driver/src/usb_dcd.c \
+	../../STM32_USB_Device_Library/core/src/usbd_core.c \
+	../../STM32_USB_Device_Library/core/src/usbd_req.c \
+	../../STM32_USB_Device_Library/core/src/usbd_ioreq.c \
+	../../STM32_USB_Device_Library/class/hid/src/usbd_hid_core.c \
+
+		
+	$(CC) $(CFLAGS) $^ -o $@  -L../../STM32F4xx_StdPeriph_Driver/build -lSTM32F4xx_StdPeriph_Driver -L../../STM32F_USB_OTG_Driver/build
+
+clean:
+	rm -rf $(EXECUTABLE)
+	rm -rf $(BIN_IMAGE)
+
+.PHONY: all clean
diff --git a/exampleF4/Projects/discovery_demo/Release_Notes.html b/exampleF4/Projects/discovery_demo/Release_Notes.html
new file mode 100644
index 0000000..304ad5d
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/Release_Notes.html
@@ -0,0 +1,151 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+
+
+
+
+
+
+  
+  <meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
+
+  
+  <link rel="File-List" href="Library_files/filelist.xml">
+
+  
+  <link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32F4-Discovery Board Demonstration firmware</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
+
+
+  
+
+  
+
+  
+  <style>
+<!--
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+  <meta content="MCD Application Team" name="author"></head>
+<body link="blue" vlink="blue">
+<div class="Section1">
+<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
+</o:p></span></p>
+<div align="center">
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+  <tbody>
+    <tr>
+      <td style="padding: 0cm;" valign="top">
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
+        <tbody>
+          <tr>
+            <td style="vertical-align: top;">
+            <p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
+            </td>
+          </tr>
+          <tr style="">
+            <td style="padding: 1.5pt;">
+            <h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
+Notes for STM32F4-Discovery Board Demonstration firmware</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
+2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
+            <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
+      <table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+        <tbody>
+          <tr style="">
+            <td style="padding: 0cm;" valign="top">
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
+            <ol style="margin-top: 0cm;" start="1" type="1">
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F4-Discovery Board Demonstration firmware update History</a><o:p></o:p></span></li>
+              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
+            </ol>
+            <span style="font-family: &quot;Times New Roman&quot;;">
+            </span>
+            <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F4-Discovery Board Demonstration firmware&nbsp;update History</span></h2><div style="margin-left: 40px;"><span style="font-size: 10pt; font-family: Verdana;">For more information on the STM32F4-Discovery board&nbsp;visit <a href="http://www.st.com/stm32f4-discovery" target="_blank">www.st.com/stm32f4-discovery</a>.</span></div><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 186px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 19-September-2011</span></h3>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes<o:p></o:p></span></u></b></p>
+
+            <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">First official version of the<span style="font-weight: bold; font-style: italic;"> STM32F4-Discovery Board Demonstration firmware</span></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span><br><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
+enclosed firmware and all the related documentation are not covered by
+a License Agreement, if you need such License you can contact your
+local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
+
+            <b><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
+PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
+SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
+ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
+CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
+CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
+THEIR PRODUCTS.</span></b>
+            
+            <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
+            <hr align="center" size="2" width="100%"></span></div>
+            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STMicroelectronics<span style="color: black;"> Microcontrollers visit </span><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;">www.st.com</span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"><a href="http://www.st.com/stm32l" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
+            </td>
+          </tr>
+        </tbody>
+      </table>
+      <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
+      </td>
+    </tr>
+  </tbody>
+</table>
+</div>
+<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
+</div>
+
+</body></html>
\ No newline at end of file
diff --git a/exampleF4/Projects/discovery_demo/STM32F4-Discovery_Demo.bin b/exampleF4/Projects/discovery_demo/STM32F4-Discovery_Demo.bin
new file mode 100644
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diff --git a/exampleF4/Projects/discovery_demo/STM32F4-Discovery_Demo.elf b/exampleF4/Projects/discovery_demo/STM32F4-Discovery_Demo.elf
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HcmV?d00001

diff --git a/exampleF4/Projects/discovery_demo/main.c b/exampleF4/Projects/discovery_demo/main.c
new file mode 100644
index 0000000..b7d92ed
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/main.c
@@ -0,0 +1,509 @@
+/**
+  ******************************************************************************
+  * @file    main.c 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "usbd_hid_core.h"
+#include "usbd_usr.h"
+#include "usbd_desc.h"
+
+//Library config for this project!!!!!!!!!!!
+#include "stm32f4xx_conf.h"
+
+/** @addtogroup STM32F4-Discovery_Demo
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define TESTRESULT_ADDRESS         0x080FFFFC
+#define ALLTEST_PASS               0x00000000
+#define ALLTEST_FAIL               0x55555555
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
+  #if defined ( __ICCARM__ ) /*!< IAR Compiler */
+    #pragma data_alignment = 4   
+  #endif
+#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
+__ALIGN_BEGIN USB_OTG_CORE_HANDLE  USB_OTG_dev __ALIGN_END;
+  
+uint16_t PrescalerValue = 0;
+
+__IO uint32_t TimingDelay;
+__IO uint8_t DemoEnterCondition = 0x00;
+__IO uint8_t UserButtonPressed = 0x00;
+LIS302DL_InitTypeDef  LIS302DL_InitStruct;
+LIS302DL_FilterConfigTypeDef LIS302DL_FilterStruct;  
+__IO int8_t X_Offset, Y_Offset, Z_Offset  = 0x00;
+uint8_t Buffer[6];
+
+/* Private function prototypes -----------------------------------------------*/
+static uint32_t Demo_USBConfig(void);
+static void TIM4_Config(void);
+static void Demo_Exec(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @brief  Main program.
+  * @param  None
+  * @retval None
+  */
+int main(void)
+{
+  RCC_ClocksTypeDef RCC_Clocks;
+  
+  /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/
+  STM_EVAL_PBInit(BUTTON_USER, BUTTON_MODE_EXTI); 
+  
+  STM_EVAL_LEDInit(LED4);
+  STM_EVAL_LEDInit(LED3);
+  STM_EVAL_LEDInit(LED5);
+  STM_EVAL_LEDInit(LED6);
+  
+  /* SysTick end of count event each 10ms */
+  RCC_GetClocksFreq(&RCC_Clocks);
+  SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);
+  
+  if (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
+  {
+    /* Turn on LEDs available on STM32F4-Discovery ---------------------------*/
+    STM_EVAL_LEDOn(LED4);
+    STM_EVAL_LEDOn(LED3);
+    STM_EVAL_LEDOn(LED5);
+    STM_EVAL_LEDOn(LED6); 
+
+    if ((*(__IO uint32_t*) TESTRESULT_ADDRESS) == ALLTEST_PASS)
+    {
+      TimingDelay = 300;
+      /* Waiting User Button is pressed or Test Program condition verified */
+      while ((STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)&&(TimingDelay != 0x00))
+      {}
+    }
+    else
+    {
+      /* Waiting User Button is Released  or TimeOut*/
+      TimingDelay = 300;
+      while ((STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)&&(TimingDelay != 0x00))
+      {}
+      if (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET)
+      {
+        TimingDelay = 0x00;
+      }
+    }
+    if (TimingDelay == 0x00)
+    {
+      /* Turn off LEDs available on STM32F4-Discovery ------------------------*/
+      STM_EVAL_LEDOff(LED4);
+      STM_EVAL_LEDOff(LED3);
+      STM_EVAL_LEDOff(LED5);
+      STM_EVAL_LEDOff(LED6); 
+      
+      /* Waiting User Button is released */
+      while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
+      {}
+      
+      /* Unlocks the FLASH control register access */
+      FLASH_Unlock();
+      
+      /* Move discovery kit to detect negative and positive acceleration values 
+      on X, Y and Z axis */
+      Accelerometer_MEMS_Test();
+      
+      /* USB Hardware connection */
+      USB_Test();
+      
+      /* Audio Hardware connection */
+      Audio_Test();
+      
+      /* Microphone MEMS Hardware connection */
+      Microphone_MEMS_Test();
+      
+      /* Write PASS code at last word in the flash memory */
+      FLASH_ProgramWord(TESTRESULT_ADDRESS, ALLTEST_PASS);
+      
+      while(1)
+      {
+        /* Toggle Green LED: signaling the End of the Test program */
+        STM_EVAL_LEDToggle(LED4);
+        Delay(10);
+      }
+    }
+    else
+    {
+      Demo_Exec();
+    }
+  }
+  else
+  {    
+    Demo_Exec();
+  }
+}
+
+/**
+  * @brief  Execute the demo application.
+  * @param  None
+  * @retval None
+  */
+static void Demo_Exec(void)
+{
+  RCC_ClocksTypeDef RCC_Clocks;
+  uint8_t togglecounter = 0x00;
+  
+  while(1)
+  {
+    DemoEnterCondition = 0x00;
+    
+    /* Reset UserButton_Pressed variable */
+    UserButtonPressed = 0x00;
+    
+    /* Initialize LEDs to be managed by GPIO */
+    STM_EVAL_LEDInit(LED4);
+    STM_EVAL_LEDInit(LED3);
+    STM_EVAL_LEDInit(LED5);
+    STM_EVAL_LEDInit(LED6);
+    
+    /* SysTick end of count event each 10ms */
+    RCC_GetClocksFreq(&RCC_Clocks);
+    SysTick_Config(RCC_Clocks.HCLK_Frequency / 100);  
+    
+    /* Turn OFF all LEDs */
+    STM_EVAL_LEDOff(LED4);
+    STM_EVAL_LEDOff(LED3);
+    STM_EVAL_LEDOff(LED5);
+    STM_EVAL_LEDOff(LED6);
+    
+    /* Waiting User Button is pressed */
+    while (UserButtonPressed == 0x00)
+    {
+      /* Toggle LED4 */
+      STM_EVAL_LEDToggle(LED4);
+      Delay(10);
+      /* Toggle LED4 */
+      STM_EVAL_LEDToggle(LED3);
+      Delay(10);
+      /* Toggle LED4 */
+      STM_EVAL_LEDToggle(LED5);
+      Delay(10);
+      /* Toggle LED4 */
+      STM_EVAL_LEDToggle(LED6);
+      Delay(10);
+      togglecounter ++;
+      if (togglecounter == 0x10)
+      {
+        togglecounter = 0x00;
+        while (togglecounter < 0x10)
+        {
+          STM_EVAL_LEDToggle(LED4);
+          STM_EVAL_LEDToggle(LED3);
+          STM_EVAL_LEDToggle(LED5);
+          STM_EVAL_LEDToggle(LED6);
+          Delay(10);
+          togglecounter ++;
+        }
+       togglecounter = 0x00;
+      }
+    }
+    
+    /* Waiting User Button is Released */
+    while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
+    {}
+    UserButtonPressed = 0x00;
+    
+    /* TIM4 channels configuration */
+    TIM4_Config();
+    
+    /* Disable all Timer4 channels */
+    TIM_CCxCmd(TIM4, TIM_Channel_1, DISABLE);
+    TIM_CCxCmd(TIM4, TIM_Channel_2, DISABLE);
+    TIM_CCxCmd(TIM4, TIM_Channel_3, DISABLE);
+    TIM_CCxCmd(TIM4, TIM_Channel_4, DISABLE);
+
+    /* MEMS configuration */
+    LIS302DL_InitStruct.Power_Mode = LIS302DL_LOWPOWERMODE_ACTIVE;
+    LIS302DL_InitStruct.Output_DataRate = LIS302DL_DATARATE_100;
+    LIS302DL_InitStruct.Axes_Enable = LIS302DL_XYZ_ENABLE;
+    LIS302DL_InitStruct.Full_Scale = LIS302DL_FULLSCALE_2_3;
+    LIS302DL_InitStruct.Self_Test = LIS302DL_SELFTEST_NORMAL;
+    LIS302DL_Init(&LIS302DL_InitStruct);
+    
+    /* Required delay for the MEMS Accelerometre: Turn-on time = 3/Output data Rate 
+    = 3/100 = 30ms */
+    Delay(30);
+    
+    DemoEnterCondition = 0x01;
+    /* MEMS High Pass Filter configuration */
+    LIS302DL_FilterStruct.HighPassFilter_Data_Selection = LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER;
+    LIS302DL_FilterStruct.HighPassFilter_CutOff_Frequency = LIS302DL_HIGHPASSFILTER_LEVEL_1;
+    LIS302DL_FilterStruct.HighPassFilter_Interrupt = LIS302DL_HIGHPASSFILTERINTERRUPT_1_2;
+    LIS302DL_FilterConfig(&LIS302DL_FilterStruct);
+    
+    LIS302DL_Read(Buffer, LIS302DL_OUT_X_ADDR, 6);
+    X_Offset = Buffer[0];
+    Y_Offset = Buffer[2];
+    Z_Offset = Buffer[4];
+    
+    /* USB configuration */
+    Demo_USBConfig();
+    
+    /* Waiting User Button is pressed */
+    while (UserButtonPressed == 0x00)
+    {}
+    
+    /* Waiting User Button is Released */
+    while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
+    {}
+    
+    /* Disable SPI1 used to drive the MEMS accelerometre */
+    SPI_Cmd(LIS302DL_SPI, DISABLE);
+    
+    /* Disconnect the USB device */
+    DCD_DevDisconnect(&USB_OTG_dev);
+    USB_OTG_StopDevice(&USB_OTG_dev);
+  }
+}
+
+/**
+  * @brief  Initializes the USB for the demonstration application.
+  * @param  None
+  * @retval None
+  */
+static uint32_t Demo_USBConfig(void)
+{
+  USBD_Init(&USB_OTG_dev,
+            USB_OTG_FS_CORE_ID,
+            &USR_desc, 
+            &USBD_HID_cb, 
+            &USR_cb);
+  
+  return 0;
+}
+
+/**
+  * @brief  Configures the TIM Peripheral.
+  * @param  None
+  * @retval None
+  */
+static void TIM4_Config(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  TIM_OCInitTypeDef  TIM_OCInitStructure;
+  TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
+  
+  /* --------------------------- System Clocks Configuration -----------------*/
+  /* TIM4 clock enable */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
+  
+  /* GPIOD clock enable */
+  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
+
+  /*-------------------------- GPIO Configuration ----------------------------*/
+  /* GPIOD Configuration: Pins 12, 13, 14 and 15 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+  /* Connect TIM4 pins to AF2 */  
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_TIM4);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_TIM4); 
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_TIM4);
+  GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_TIM4); 
+  
+    /* -----------------------------------------------------------------------
+    TIM4 Configuration: Output Compare Timing Mode:
+    
+    In this example TIM4 input clock (TIM4CLK) is set to 2 * APB1 clock (PCLK1), 
+    since APB1 prescaler is different from 1 (APB1 Prescaler = 4, see system_stm32f4xx.c file).
+      TIM4CLK = 2 * PCLK1  
+      PCLK1 = HCLK / 4 
+      => TIM4CLK = 2*(HCLK / 4) = HCLK/2 = SystemCoreClock/2
+         
+    To get TIM4 counter clock at 2 KHz, the prescaler is computed as follows:
+       Prescaler = (TIM4CLK / TIM1 counter clock) - 1
+       Prescaler = (168 MHz/(2 * 2 KHz)) - 1 = 41999
+                                        
+    To get TIM4 output clock at 1 Hz, the period (ARR)) is computed as follows:
+       ARR = (TIM4 counter clock / TIM4 output clock) - 1
+           = 1999
+                    
+    TIM4 Channel1 duty cycle = (TIM4_CCR1/ TIM4_ARR)* 100 = 50%
+    TIM4 Channel2 duty cycle = (TIM4_CCR2/ TIM4_ARR)* 100 = 50%
+    TIM4 Channel3 duty cycle = (TIM4_CCR3/ TIM4_ARR)* 100 = 50%
+    TIM4 Channel4 duty cycle = (TIM4_CCR4/ TIM4_ARR)* 100 = 50%
+    
+    ==> TIM4_CCRx = TIM4_ARR/2 = 1000  (where x = 1, 2, 3 and 4).
+  
+    Note: 
+     SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file.
+     Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
+     function to update SystemCoreClock variable value. Otherwise, any configuration
+     based on this variable will be incorrect.    
+  ----------------------------------------------------------------------- */ 
+  
+  
+  /* Compute the prescaler value */
+  PrescalerValue = (uint16_t) ((SystemCoreClock /2) / 2000) - 1;
+  
+  /* Time base configuration */
+  TIM_TimeBaseStructure.TIM_Period = TIM_ARR;
+  TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue;
+  TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
+  
+  /* Enable TIM4 Preload register on ARR */
+  TIM_ARRPreloadConfig(TIM4, ENABLE);
+  
+  /* TIM PWM1 Mode configuration: Channel */
+  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
+  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
+  TIM_OCInitStructure.TIM_Pulse = TIM_CCR;
+  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
+  
+  /* Output Compare PWM1 Mode configuration: Channel1 */
+  TIM_OC1Init(TIM4, &TIM_OCInitStructure);
+  TIM_CCxCmd(TIM4, TIM_Channel_1, DISABLE);
+  
+  TIM_OC1PreloadConfig(TIM4, TIM_OCPreload_Enable);
+  
+  /* Output Compare PWM1 Mode configuration: Channel2 */
+  TIM_OC2Init(TIM4, &TIM_OCInitStructure);
+  TIM_CCxCmd(TIM4, TIM_Channel_2, DISABLE);
+  
+  TIM_OC2PreloadConfig(TIM4, TIM_OCPreload_Enable);
+    
+  /* Output Compare PWM1 Mode configuration: Channel3 */
+  TIM_OC3Init(TIM4, &TIM_OCInitStructure);
+  TIM_CCxCmd(TIM4, TIM_Channel_3, DISABLE);
+  
+  TIM_OC3PreloadConfig(TIM4, TIM_OCPreload_Enable);
+  
+  /* Output Compare PWM1 Mode configuration: Channel4 */
+  TIM_OC4Init(TIM4, &TIM_OCInitStructure);
+  TIM_CCxCmd(TIM4, TIM_Channel_4, DISABLE);
+  
+  TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Enable);
+  
+  /* TIM4 enable counter */
+  TIM_Cmd(TIM4, ENABLE);
+}
+
+/**
+  * @brief  Inserts a delay time.
+  * @param  nTime: specifies the delay time length, in 10 ms.
+  * @retval None
+  */
+void Delay(__IO uint32_t nTime)
+{
+  TimingDelay = nTime;
+
+  while(TimingDelay != 0);
+}
+
+/**
+  * @brief  Decrements the TimingDelay variable.
+  * @param  None
+  * @retval None
+  */
+void TimingDelay_Decrement(void)
+{
+  if (TimingDelay != 0x00)
+  { 
+    TimingDelay--;
+  }
+}
+
+/**
+  * @brief  This function handles the test program fail.
+  * @param  None
+  * @retval None
+  */
+void Fail_Handler(void)
+{
+  /* Erase last sector */ 
+  FLASH_EraseSector(FLASH_Sector_11, VoltageRange_3);
+  /* Write FAIL code at last word in the flash memory */
+  FLASH_ProgramWord(TESTRESULT_ADDRESS, ALLTEST_FAIL);
+  
+  while(1)
+  {
+    /* Toggle Red LED */
+    STM_EVAL_LEDToggle(LED5);
+    Delay(5);
+  }
+}
+
+/**
+  * @brief  MEMS accelerometre management of the timeout situation.
+  * @param  None.
+  * @retval None.
+  */
+uint32_t LIS302DL_TIMEOUT_UserCallback(void)
+{
+  /* MEMS Accelerometer Timeout error occured during Test program execution */
+  if (DemoEnterCondition == 0x00)
+  {
+    /* Timeout error occured for SPI TXE/RXNE flags waiting loops.*/
+    Fail_Handler();    
+  }
+  /* MEMS Accelerometer Timeout error occured during Demo execution */
+  else
+  {
+    while (1)
+    {   
+    }
+  }
+  return 0;  
+}
+
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *   where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{ 
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+  /* Infinite loop */
+  while (1)
+  {
+  }
+}
+#endif
+
+/**
+  * @}
+  */
+
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/main.h b/exampleF4/Projects/discovery_demo/main.h
new file mode 100644
index 0000000..cc19bb4
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/main.h
@@ -0,0 +1,62 @@
+/**
+  ******************************************************************************
+  * @file    main.h 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Header for main.c module
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4_DISCOVERY_DEMO_H
+#define __STM32F4_DISCOVERY_DEMO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4_discovery.h"
+#include "stm32f4_discovery_audio_codec.h"
+#include "stm32f4_discovery_lis302dl.h"
+#include "selftest.h"
+#include <stdio.h>
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* TIM2 Autoreload and Capture Compare register values */
+#define TIM_ARR                          (uint16_t)1999
+#define TIM_CCR                          (uint16_t)1000
+
+/* MEMS Microphone SPI Interface */
+#define SPI_SCK_PIN                   GPIO_Pin_10
+#define SPI_SCK_GPIO_PORT             GPIOB
+#define SPI_SCK_GPIO_CLK              RCC_AHB1Periph_GPIOB
+#define SPI_SCK_SOURCE                GPIO_PinSource10
+#define SPI_SCK_AF                    GPIO_AF_SPI2
+
+#define SPI_MOSI_PIN                  GPIO_Pin_3
+#define SPI_MOSI_GPIO_PORT            GPIOC
+#define SPI_MOSI_GPIO_CLK             RCC_AHB1Periph_GPIOC
+#define SPI_MOSI_SOURCE               GPIO_PinSource3
+#define SPI_MOSI_AF                   GPIO_AF_SPI2
+
+/* Exported macro ------------------------------------------------------------*/
+#define ABS(x)         (x < 0) ? (-x) : x
+#define MAX(a,b)       (a < b) ? (b) : a
+/* Exported functions ------------------------------------------------------- */
+void TimingDelay_Decrement(void);
+void Delay(__IO uint32_t nTime);
+void Fail_Handler(void);
+#endif /* __STM32F4_DISCOVERY_DEMO_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/selftest.c b/exampleF4/Projects/discovery_demo/selftest.c
new file mode 100644
index 0000000..7183ffa
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/selftest.c
@@ -0,0 +1,808 @@
+/**
+  ******************************************************************************
+  * @file    selftest.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   This file provides the hardware tests
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "selftest.h"
+
+//Library config for this project!!!!!!!!!!!
+#include "stm32f4xx_conf.h"
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define MEMS_PASSCONDITION              15
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Init Structure definition */
+RCC_ClocksTypeDef      RCC_Clocks;
+ADC_InitTypeDef        ADC_InitStructure;
+ADC_CommonInitTypeDef  ADC_CommonInitStructure;
+
+__IO uint16_t ConvData1, ConvData2;
+__IO uint16_t counter0 = 0, counter1 = 0, Idx = 0;
+uint8_t ADC_Channel[2] = {ADC_Channel_2, ADC_Channel_3};
+uint8_t DACTest = 0;
+uint8_t GPIO_Pin [2] = {GPIO_Pin_2, GPIO_Pin_3};
+
+uint16_t count = 0, count1 = 24, Left_Right = 0;
+const int16_t sinebuf[48] = {0, 4276, 8480, 12539, 16383, 19947, 23169, 25995,
+                             28377, 30272, 31650, 32486, 32767, 32486, 31650, 30272,
+                             28377, 25995, 23169, 19947, 16383, 12539, 8480, 4276,
+                             0, -4276, -8480, -12539, -16383, -19947, -23169, -25995,
+                             -28377, -30272, -31650, -32486, -32767, -32486, -31650, -30272,
+                             -28377, -25995, -23169, -19947, -16383, -12539, -8480, -4276
+                             };
+extern __IO uint32_t TimingDelay;
+
+extern LIS302DL_InitTypeDef  LIS302DL_InitStruct;
+extern LIS302DL_FilterConfigTypeDef LIS302DL_FilterStruct;  
+
+extern __IO int8_t X_Offset, Y_Offset, Z_Offset;
+extern uint8_t Buffer[6];
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @brief Test MEMS Hardware.
+  *   The main objectif of this test is to check the hardware connection of the 
+  *   MEMS peripheral.
+  * @param None
+  * @retval None
+  */
+void Accelerometer_MEMS_Test(void)
+{
+  uint8_t temp, memsteststatus = 0x00;
+  uint8_t xdata, ydata = 0;
+  
+  /* MEMS configuration ------------------------------------------------------*/
+  /* Set configuration of LIS302DL*/
+  LIS302DL_InitStruct.Power_Mode = LIS302DL_LOWPOWERMODE_ACTIVE;
+  LIS302DL_InitStruct.Output_DataRate = LIS302DL_DATARATE_100;
+  LIS302DL_InitStruct.Axes_Enable = LIS302DL_X_ENABLE | LIS302DL_Y_ENABLE;
+  LIS302DL_InitStruct.Full_Scale = LIS302DL_FULLSCALE_2_3;
+  LIS302DL_InitStruct.Self_Test = LIS302DL_SELFTEST_NORMAL;
+  LIS302DL_Init(&LIS302DL_InitStruct);
+  
+  /* Set configuration of Internal High Pass Filter of LIS302DL*/
+  LIS302DL_FilterStruct.HighPassFilter_Data_Selection = LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER;
+  LIS302DL_FilterStruct.HighPassFilter_CutOff_Frequency = LIS302DL_HIGHPASSFILTER_LEVEL_1;
+  LIS302DL_FilterStruct.HighPassFilter_Interrupt = LIS302DL_HIGHPASSFILTERINTERRUPT_1_2;
+  LIS302DL_FilterConfig(&LIS302DL_FilterStruct);
+  
+  /* Required delay for the MEMS Accelerometre: Turn-on time = 3/Output data Rate 
+                                                             = 3/100 = 30ms */
+  Delay(30);
+  
+  /* Read WHO_AM_I register */
+  LIS302DL_Read(&temp, LIS302DL_WHO_AM_I_ADDR, 1);
+  
+  /* Check device identification register, this register should contains 
+  the device identifier that for LIS302DL is set to 0x3B */
+  if (temp != 0x3B)
+  {
+    Fail_Handler();
+  }
+
+  TimingDelay = 500;
+  /* Wait until detecting all MEMS direction or timeout */
+  while((memsteststatus == 0x00)&&(TimingDelay != 0x00))
+  {
+    LIS302DL_Read(Buffer, LIS302DL_OUT_X_ADDR, 4);
+    xdata = ABS((int8_t)(Buffer[0]));
+    ydata = ABS((int8_t)(Buffer[2]));
+    /* Check test PASS condition */   
+    if ((xdata > MEMS_PASSCONDITION) || (ydata > MEMS_PASSCONDITION)) 
+    {
+      /* MEMS Test PASS */
+      memsteststatus = 0x01;
+    }
+  }
+  
+  /* MEMS test status: PASS */ 
+  if(memsteststatus != 0x00)
+  {
+    /* Turn Green LED ON: signaling MEMS Test PASS */
+    STM_EVAL_LEDOn(LED4);
+    
+    /* Waiting User Button is pressed */
+    while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET)
+    {}
+    
+    /* Waiting User Button is Released */
+    while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)
+    {}
+    
+    /* Turn Green LED OFF: signaling the end of MEMS Test and switching to 
+       the next Sub Test */
+    STM_EVAL_LEDOff(LED4);
+  }
+  /* MEMS test status: Timeout occurs */
+  else
+  {
+    Fail_Handler();
+  }
+}
+
+/**
+  * @brief Test USB Hardware.
+  *   The main objectif of this test is to check the hardware connection of the 
+  *   Audio and USB peripheral.
+  * @param None
+  * @retval None
+  */
+void USB_Test(void)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /******************************** USB Test **********************************/
+  
+  /*----------------- Part1: without cables connected ------------------------*/ 
+  
+  /* GPIOA, GPIOC and GPIOD clock enable */
+  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | \
+                         RCC_AHB1Periph_GPIOD, ENABLE);
+  
+  /* GPIOD Configuration: Pins 5 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOD, &GPIO_InitStructure);
+  
+  /* Turn LED8 ON using PD5 */
+  GPIO_ResetBits(GPIOD, GPIO_Pin_5);
+  
+  /* GPIOC Configuration: Pin 0 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+  
+  /* GPIOA Configuration: Pin 9 in input pull-up */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* Turn LED7 ON using PC0 (5v) */
+  GPIO_ResetBits(GPIOC, GPIO_Pin_0); 
+  
+  /* Waiting delay 10ms */
+  Delay(1);
+  
+  if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET)
+  {
+    Fail_Handler();
+  }
+  
+  /* GPIOA Configuration: Pins 10 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* Waiting delay 10ms */
+  Delay(1);
+  
+  /* Check the ID level without cable connected */
+  if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_10) == Bit_RESET)
+  {
+    Fail_Handler();
+  }
+  
+  /* Turn LED7 OFF using PC0 */
+  GPIO_SetBits(GPIOC, GPIO_Pin_0);  
+  
+  /* GPIOA Configuration: Pins 11, 12 in input pull-up */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* GPIOA Configuration: Pin 9 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  GPIO_ResetBits(GPIOA, GPIO_Pin_9);
+  
+  /* Waiting delay 10ms */
+  Delay(1);
+  
+  /* Check PA11 and PA12 level without cable connected */
+  if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET) || \
+      (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET))
+  {
+    Fail_Handler();
+  }
+  
+  /* GPIOA Configuration: Pins 12 in input pull-up */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* GPIOA Configuration: Pin 11 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  GPIO_ResetBits(GPIOA, GPIO_Pin_11);
+  
+  /* Waiting delay 10ms */
+  Delay(1);
+  
+  /* Check PA12 level without cable connected */
+  if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET)
+  {
+    Fail_Handler();
+  }
+  
+  /* GPIOA Configuration: Pins 11 in input pull-up */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* GPIOA Configuration: Pin 12 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  GPIO_ResetBits(GPIOA, GPIO_Pin_12);
+  
+  /* Waiting delay 10ms */
+  Delay(1);
+  
+  /* Check PA12 level without cable connected */
+  if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET)
+  {
+    Fail_Handler();
+  }
+  
+  /* GPIOA Configuration: Pins 9 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* Turn LED7 ON using PA9 */
+  GPIO_SetBits(GPIOA, GPIO_Pin_9);
+  
+  /* Turn Green LED ON: signaling Audio USB Test part1 PASS */
+  STM_EVAL_LEDOn(LED4);
+  
+  /* Waiting User Button is pressed */
+  while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET)
+  {}
+  
+  /* Waiting User Button is Released */
+  while (STM_EVAL_PBGetState(BUTTON_USER) != Bit_RESET)
+  {}
+  
+  /* Turn Green LED OFF: signaling the end of Audio USB Test part1 and switching to 
+  the part2 */
+  STM_EVAL_LEDOff(LED4);
+  
+  /* Turn LED7 OFF using PA9 */
+  GPIO_ResetBits(GPIOA, GPIO_Pin_9);
+  
+  /* Turn LED8 OFF using PD5 */
+  GPIO_SetBits(GPIOD, GPIO_Pin_5);
+  
+  /*--------------- Part2: with Audio USB cables connected  ------------------*/ 
+  
+  /*********************************** USB Test *******************************/
+  /* Check the ID level with cable connected */
+  if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_10) != Bit_RESET)
+  {
+    Fail_Handler();
+  }
+  
+  /* GPIOA Configuration: Pins 11, 12 in input pull-down */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* GPIOA Configuration: Pin 9 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  GPIO_SetBits(GPIOA, GPIO_Pin_9);
+  
+  /* Waiting delay 10ms */
+  Delay(1);
+  
+  /* Check PA11 and PA12 level with cable connected */
+  if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET) || \
+      (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET))
+  {
+    Fail_Handler();
+  }
+  
+  /* GPIOA Configuration: Pins 9, 12 in input pull-down */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* GPIOA Configuration: Pin 11 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  GPIO_SetBits(GPIOA, GPIO_Pin_11);
+  
+  /* Waiting delay 10ms */
+  Delay(1);
+  
+  /* Check PA9 and PA12 level with cable connected */
+  if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET)|| \
+      (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET))
+  {
+    Fail_Handler();
+  }
+  
+  /* GPIOA Configuration: Pins 9, 11 in input pull-down */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_11;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* GPIOA Configuration: Pin 12 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  GPIO_SetBits(GPIOA, GPIO_Pin_12);
+  
+  /* Waiting delay 10ms */
+  Delay(1);
+  
+  /* Check PA9 and PA12 level with cable connected */
+  if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET)|| \
+      (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET))
+  {
+    Fail_Handler();
+  }
+
+  /* GPIOA Configuration: Pins 11, 12 in input pull-down */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* GPIOA Configuration: Pin 9 in output push-pull */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  /* Turn LED7 OFF using PA9 */
+  GPIO_ResetBits(GPIOA, GPIO_Pin_9);
+}
+
+/**
+  * @brief Test Audio Hardware.
+  *   The main objectif of this test is to check the hardware connection of the 
+  *   Audio peripheral.
+  * @param  None
+  * @retval None
+  */
+void Audio_Test(void)
+{ 
+  GPIO_InitTypeDef  GPIO_InitStructure;  
+  uint8_t audioteststatus = 0x00;
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE);
+  
+  /* Set the current audio interface: I2S or DAC */
+  EVAL_AUDIO_SetAudioInterface(AUDIO_INTERFACE_I2S);
+  
+  /* Initialize the Audio codec and all related peripherals (I2S, I2C, IOs...) */  
+  if (EVAL_AUDIO_Init(OUTPUT_DEVICE_HEADPHONE, 87, I2S_AudioFreq_48k) !=0)
+  {
+    Fail_Handler();
+  }
+  /* I2S code to be exectued under the I2S interrupt */
+  DACTest = 0;
+  
+  /* ADC Common Init */
+  ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
+  ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div8;
+  ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
+  ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_20Cycles; 
+  ADC_CommonInit(&ADC_CommonInitStructure);
+  
+  /* ADC peripherals Init */
+  ADC_StructInit(&ADC_InitStructure);
+  ADC_InitStructure.ADC_Resolution = ADC_Resolution_8b;
+  ADC_InitStructure.ADC_ScanConvMode = DISABLE;
+  ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
+  ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
+  ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
+  ADC_InitStructure.ADC_NbrOfConversion = 1;
+  ADC_Init(ADC1, &ADC_InitStructure);
+
+  ADC_Init(ADC2, &ADC_InitStructure);
+  
+  /* Configure ADC Channels pin as analog input */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 ;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  
+  counter1 = 0;
+  counter0 = 0;
+  audioteststatus = 0;
+  /* ADCperipheral[PerIdx] Regular Channel Config */  
+  ADC_RegularChannelConfig(ADC1, ADC_Channel_2, 1, ADC_SampleTime_56Cycles);
+  /* ADCperipheral[PerIdx] Regular Channel Config */  
+  ADC_RegularChannelConfig(ADC2, ADC_Channel_3, 1, ADC_SampleTime_56Cycles);
+  /* Enable ADC1 */
+  ADC_Cmd(ADC1, ENABLE);
+  ADC_Cmd(ADC2, ENABLE);
+ 
+  TimingDelay = 500;
+  /* Wait until detecting 500 data*/
+  while((audioteststatus == 0)&&(TimingDelay != 0))
+  {
+    ADC_SoftwareStartConv(ADC1);
+    while(ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == RESET);
+    ConvData1 = ADC_GetConversionValue(ADC1); 
+
+    ADC_SoftwareStartConv(ADC2);
+    while(ADC_GetFlagStatus(ADC2, ADC_FLAG_EOC) == RESET);
+    ConvData2 = ADC_GetConversionValue(ADC2);
+    
+    /* 1.75V equals to 150 */
+    if ((ConvData1 > 150) && (ConvData2 < 10) && (counter1 != 500))
+    {
+      counter1 ++;
+    }
+    if ((ConvData1 < 10) && (ConvData2 > 150) && (counter0 != 500))
+    {
+      counter0 ++;
+    }
+    if((counter1 == 500) && (counter0 == 500))
+    {
+      audioteststatus = 1; 
+    }
+  }
+  
+  /* Disable ADC Peripherals */ 
+  ADC_Cmd(ADC1, DISABLE);
+  ADC_Cmd(ADC2, DISABLE);
+  
+  /* Audio test status: FAIL */ 
+  if(audioteststatus == 0)
+  {
+    Fail_Handler();
+  }
+  
+  EVAL_AUDIO_DeInit();
+  EVAL_AUDIO_SetAudioInterface(AUDIO_INTERFACE_DAC);
+  /* Initialize the Audio codec and all related peripherals (I2S, I2C, IOs...) */  
+  if (EVAL_AUDIO_Init(OUTPUT_DEVICE_HEADPHONE, 100, I2S_AudioFreq_48k) !=0)
+  {
+    Fail_Handler();
+  }
+  
+  /* DAC code to be exectued under the I2S interrupt */
+  DACTest = 1;
+  counter1 = 0;
+  counter0 = 0;
+  audioteststatus = 0;
+  
+  /* Enable ADC1 */
+  ADC_Cmd(ADC1, ENABLE);
+  ADC_Cmd(ADC2, ENABLE);
+  
+  TimingDelay = 500;
+  /* Wait until detecting 50 data*/
+  while((audioteststatus == 0)&&(TimingDelay != 0))
+  {
+    
+    ADC_SoftwareStartConv(ADC1);
+    while(ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == RESET);
+    
+    ConvData1 = ADC_GetConversionValue(ADC1); 
+    
+    ADC_SoftwareStartConv(ADC2);
+    while(ADC_GetFlagStatus(ADC2, ADC_FLAG_EOC) == RESET);
+    
+    ConvData2 = ADC_GetConversionValue(ADC2);
+    
+    /* 2.0V equals to 170 */
+    if ((ConvData1 > 170) && (ConvData2 > 170) &&(counter1 != 500))
+    {
+      counter1 ++;
+    }
+    if ((ConvData1 < 10) && (ConvData2 < 10) && (counter0 != 500))
+    {
+      counter0 ++;
+    }
+    if((counter1 == 500) && (counter0 == 500))
+    {
+      audioteststatus = 1; 
+    }
+  }
+  
+  /* Audio test status: FAIL */ 
+  if(audioteststatus == 0x00)
+  {
+    Fail_Handler();
+  }
+  
+  /* Turn Green LED ON: signaling Audio USB Test part2 PASS */
+  STM_EVAL_LEDOn(LED4);
+  
+  /* Waiting User_Button pressed */
+  while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET)
+  {}
+  
+  /* Turn Green LED OFF: signaling the end of Audio USB Test part2 */
+  STM_EVAL_LEDOff(LED4);
+}
+
+/**
+  * @brief Test Micophone MEMS Hardware.
+  *   The main objectif of this test is to check the hardware connection of the 
+  *   Microphone MEMS peripheral.
+  * @param None
+  * @retval None
+  */
+void Microphone_MEMS_Test(void)
+{
+  uint16_t data = 0x00;
+  uint8_t index = 0x00;
+  I2S_InitTypeDef  I2S_InitStructure;
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+  /* Enable the SPI clock */
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
+
+  /* Enable GPIO clocks */
+  RCC_AHB1PeriphClockCmd(SPI_SCK_GPIO_CLK | SPI_MOSI_GPIO_CLK, ENABLE);
+
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;
+
+  /* SPI SCK pin configuration */
+  GPIO_InitStructure.GPIO_Pin = SPI_SCK_PIN;
+  GPIO_Init(SPI_SCK_GPIO_PORT, &GPIO_InitStructure);
+  
+  /* Connect SPI pins to AF5 */  
+  GPIO_PinAFConfig(SPI_SCK_GPIO_PORT, SPI_SCK_SOURCE, SPI_SCK_AF);
+  
+  /* SPI MOSI pin configuration */
+  GPIO_InitStructure.GPIO_Pin =  SPI_MOSI_PIN;
+  GPIO_Init(SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);
+  
+  GPIO_PinAFConfig(SPI_MOSI_GPIO_PORT, SPI_MOSI_SOURCE, SPI_MOSI_AF);
+  
+  /* I2S configuration -------------------------------------------------------*/
+  SPI_I2S_DeInit(SPI2);
+  I2S_InitStructure.I2S_AudioFreq = 64000;
+  I2S_InitStructure.I2S_Standard = I2S_Standard_MSB;
+  I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
+  I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
+  I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx;
+  I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+  /* Initialize the I2S peripheral with the structure above */
+  I2S_Init(SPI2, &I2S_InitStructure);
+  
+  /* Enable the I2S peripheral */
+  I2S_Cmd(SPI2, ENABLE);
+  
+  /* Waiting until MEMS microphone ready : Wake-up Time */
+  Delay(10);
+  
+  TimingDelay = 500;
+  /* Wait until detect the click on the MEMS microphone or TimeOut delay*/
+  while((index < 30) && (TimingDelay != 0x00))
+  { 
+    /* Waiting RXNE Flag or TimeOut delay */
+    while((SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_RXNE) == RESET)&& (TimingDelay != 0x00))
+    {}
+    data = SPI_I2S_ReceiveData(SPI2);
+    if (data == 0xFFFF)
+    {
+      index++;  
+    }
+  }
+  
+  /* MEMS microphone test status: Timeout occurs */
+  if(index != 30)
+  {
+    Fail_Handler();
+  }
+}
+
+/*--------------------------------
+       Callbacks implementation:
+           the callbacks prototypes are defined in the stm324xg_eval_audio_codec.h file
+           and their implementation should be done in the user code if they are needed.
+           Below some examples of callback implementations.
+                                     --------------------------------------------------------*/
+/**
+  * @brief  Calculates the remaining file size and new position of the pointer.
+  * @param  None
+  * @retval None
+  */
+void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size)
+{
+  /* Calculate the remaining audio data in the file and the new size 
+     for the DMA transfer. If the Audio files size is less than the DMA max 
+     data transfer size, so there is no calculation to be done, just restart 
+     from the beginning of the file ... */
+  /* Check if the end of file has been reached */
+
+}
+
+/**
+  * @brief  Manages the DMA Half Transfer complete interrupt.
+  * @param  None
+  * @retval None
+  */
+void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size)
+{  
+#ifdef AUDIO_MAL_MODE_CIRCULAR
+  
+  /* Display message on the LCD screen */
+  LCD_DisplayStringLine(Line8, " 1/2 Buffer Reached "); 
+  
+#endif /* AUDIO_MAL_MODE_CIRCULAR */
+  
+  /* Generally this interrupt routine is used to load the buffer when 
+  a streaming scheme is used: When first Half buffer is already transferred load 
+  the new data to the first half of buffer while DMA is transferring data from 
+  the second half. And when Transfer complete occurs, load the second half of 
+  the buffer while the DMA is transferring from the first half ... */
+  /* 
+    ...........
+                   */
+}
+/**
+  * @brief  Get next data sample callback
+  * @param  None
+  * @retval Next data sample to be sent
+  */
+uint16_t EVAL_AUDIO_GetSampleCallBack(void)
+{
+  uint16_t data = 0;
+  
+  if (DACTest == 0)
+  {
+    if (Left_Right==0)
+    {
+      /* Get the next sample to be sent */
+      data = sinebuf[count++];
+      
+      if (count == 48)
+      {
+        count = 0x00;
+      }
+      Left_Right = 1;
+    }
+    else
+    {
+      /* Get the next sample to be sent */
+      data = sinebuf[count1++];
+      
+      if (count1 == 48)
+      {
+        count1 = 0x00;
+      }
+      Left_Right = 0;
+    }
+  }
+  else
+  {
+    /* Get the next sample to be sent */
+    data = 32768 + sinebuf[count++];
+
+    if (count == 48)
+    {
+      count = 0x00;
+    }
+  }
+  return data;
+}
+
+
+/**
+  * @brief  Manages the DMA FIFO error interrupt.
+  * @param  None
+  * @retval None
+  */
+void EVAL_AUDIO_Error_CallBack(void* pData)
+{
+  /* Stop the program with an infinite loop */
+  while (1)
+  {}
+  
+  /* could also generate a system reset to recover from the error */
+  /* .... */
+}
+
+#ifndef USE_DEFAULT_TIMEOUT_CALLBACK
+/**
+  * @brief  Basic management of the timeout situation.
+  * @param  None.
+  * @retval None.
+  */
+uint32_t Codec_TIMEOUT_UserCallback(void)
+{   
+  /* Block communication and all processes */
+  while (1)
+  {   
+  }
+}
+#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */
+/*----------------------------------------------------------------------------*/
+
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/selftest.h b/exampleF4/Projects/discovery_demo/selftest.h
new file mode 100644
index 0000000..feef3de
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/selftest.h
@@ -0,0 +1,41 @@
+/**
+  ******************************************************************************
+  * @file    selftest.h 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Header for selftest.c module
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SELFTEST_H
+#define __SELFTEST_H
+
+/* Includes ------------------------------------------------------------------*/
+#include <stdio.h>
+#include "main.h"
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void Audio_Test(void);
+void Accelerometer_MEMS_Test(void);
+void USB_Test(void);
+void Microphone_MEMS_Test(void);
+
+#endif /* __SELFTEST_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/startup_stm32f4xx.s b/exampleF4/Projects/discovery_demo/startup_stm32f4xx.s
new file mode 100644
index 0000000..ce5360f
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/startup_stm32f4xx.s
@@ -0,0 +1,509 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f4xx.s
+  * @author    MCD Application Team
+  * @version   V1.0.0
+  * @date      30-September-2011
+  * @brief     STM32F4xx Devices vector table for RIDE7 toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM mounted on 
+  *                  STM324xG-EVAL board to be used as data memory (optional, 
+  *                  to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      
+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          
+  .word     RCC_IRQHandler                    /* RCC                          */                                            
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          
+  .word     TIM2_IRQHandler                   /* TIM2                         */                   
+  .word     TIM3_IRQHandler                   /* TIM3                         */                   
+  .word     TIM4_IRQHandler                   /* TIM4                         */                   
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            
+  .word     SPI1_IRQHandler                   /* SPI1                         */                   
+  .word     SPI2_IRQHandler                   /* SPI2                         */                   
+  .word     USART1_IRQHandler                 /* USART1                       */                   
+  .word     USART2_IRQHandler                 /* USART2                       */                   
+  .word     USART3_IRQHandler                 /* USART3                       */                   
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
+  .word     FSMC_IRQHandler                   /* FSMC                         */                   
+  .word     SDIO_IRQHandler                   /* SDIO                         */                   
+  .word     TIM5_IRQHandler                   /* TIM5                         */                   
+  .word     SPI3_IRQHandler                   /* SPI3                         */                   
+  .word     UART4_IRQHandler                  /* UART4                        */                   
+  .word     UART5_IRQHandler                  /* UART5                        */                   
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .word     ETH_IRQHandler                    /* Ethernet                     */                   
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .word     USART6_IRQHandler                 /* USART6                       */                    
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .word     DCMI_IRQHandler                   /* DCMI                         */                   
+  .word     CRYP_IRQHandler                   /* CRYP crypto                  */                   
+  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .word     FPU_IRQHandler                    /* FPU                          */                         
+                         
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+      
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FSMC_IRQHandler            
+   .thumb_set FSMC_IRQHandler,Default_Handler
+                     
+   .weak      SDIO_IRQHandler            
+   .thumb_set SDIO_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+            
+   .weak      ETH_IRQHandler      
+   .thumb_set ETH_IRQHandler,Default_Handler
+                  
+   .weak      ETH_WKUP_IRQHandler                  
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+            
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                  
+   .weak      DCMI_IRQHandler            
+   .thumb_set DCMI_IRQHandler,Default_Handler
+                     
+   .weak      CRYP_IRQHandler            
+   .thumb_set CRYP_IRQHandler,Default_Handler
+               
+   .weak      HASH_RNG_IRQHandler                  
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler  
+   
+/*******************   (C)   COPYRIGHT   2011   STMicroelectronics   *****END   OF   FILE****/
diff --git a/exampleF4/Projects/discovery_demo/stm32_flash.ld b/exampleF4/Projects/discovery_demo/stm32_flash.ld
new file mode 100644
index 0000000..ee842a7
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/stm32_flash.ld
@@ -0,0 +1,170 @@
+/*
+*****************************************************************************
+**
+**  File        : stm32_flash.ld
+**
+**  Abstract    : Linker script for STM32F207IG Device with
+**                1024KByte FLASH, 112KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2001c000;    /* end of 112K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
+  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 112K
+  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+	*(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+
+   .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+    .ARM : {
+    __exidx_start = .;
+      *(.ARM.exidx*)
+      __exidx_end = .;
+    } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array*))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = .;
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : AT ( _sidata )
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  /* MEMORY_bank1 section, code must be located here explicitly            */
+  /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+  .memory_b1_text :
+  {
+    *(.mb1text)        /* .mb1text sections (code) */
+    *(.mb1text*)       /* .mb1text* sections (code)  */
+    *(.mb1rodata)      /* read-only data (constants) */
+    *(.mb1rodata*)
+  } >MEMORY_B1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/exampleF4/Projects/discovery_demo/stm32f4xx_conf.h b/exampleF4/Projects/discovery_demo/stm32f4xx_conf.h
new file mode 100644
index 0000000..74447a8
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/stm32f4xx_conf.h
@@ -0,0 +1,94 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_conf.h  
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_CONF_H
+#define __STM32F4xx_CONF_H
+
+#if defined  (HSE_VALUE)
+/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
+ #undef HSE_VALUE
+ #define HSE_VALUE    ((uint32_t)8000000) 
+#endif /* HSE_VALUE */
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f4xx_adc.h"
+#include "stm32f4xx_can.h"
+#include "stm32f4xx_crc.h"
+#include "stm32f4xx_cryp.h"
+#include "stm32f4xx_dac.h"
+#include "stm32f4xx_dbgmcu.h"
+#include "stm32f4xx_dcmi.h"
+#include "stm32f4xx_dma.h"
+#include "stm32f4xx_exti.h"
+#include "stm32f4xx_flash.h"
+#include "stm32f4xx_fsmc.h"
+#include "stm32f4xx_hash.h"
+#include "stm32f4xx_gpio.h"
+#include "stm32f4xx_i2c.h"
+#include "stm32f4xx_iwdg.h"
+#include "stm32f4xx_pwr.h"
+#include "stm32f4xx_rcc.h"
+#include "stm32f4xx_rng.h"
+#include "stm32f4xx_rtc.h"
+#include "stm32f4xx_sdio.h"
+#include "stm32f4xx_spi.h"
+#include "stm32f4xx_syscfg.h"
+#include "stm32f4xx_tim.h"
+#include "stm32f4xx_usart.h"
+#include "stm32f4xx_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* If an external clock source is used, then the value of the following define 
+   should be set to the value of the external clock source, else, if no external 
+   clock is used, keep this define commented */
+/*#define I2S_EXTERNAL_CLOCK_VAL   12288000 */ /* Value of the external clock in Hz */
+
+
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F4xx_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/stm32f4xx_it.c b/exampleF4/Projects/discovery_demo/stm32f4xx_it.c
new file mode 100644
index 0000000..cee2c24
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/stm32f4xx_it.c
@@ -0,0 +1,320 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides all exceptions handler and peripherals interrupt
+  *          service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_it.h"
+#include "main.h"
+#include "usb_core.h"
+#include "usbd_core.h"
+#include "stm32f4_discovery.h"
+#include "usbd_hid_core.h"
+
+//Library config for this project!!!!!!!!!!!
+#include "stm32f4xx_conf.h"
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CURSOR_STEP     7
+
+extern uint8_t Buffer[6];
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+extern __IO uint8_t DemoEnterCondition;
+uint8_t Counter  = 0x00;
+extern int8_t X_Offset;
+extern int8_t Y_Offset;
+extern __IO uint8_t UserButtonPressed;
+__IO uint8_t TempAcceleration = 0;
+/* Private function prototypes -----------------------------------------------*/
+extern USB_OTG_CORE_HANDLE           USB_OTG_dev;
+static uint8_t *USBD_HID_GetPos (void);
+extern uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
+
+/******************************************************************************/
+/*            Cortex-M3 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief   This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Hard Fault exception.
+  * @param  None
+  * @retval None
+  */
+void HardFault_Handler(void)
+{
+  /* Go to infinite loop when Hard Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles PendSVC exception.
+  * @param  None
+  * @retval None
+  */
+void PendSV_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles SysTick Handler.
+  * @param  None
+  * @retval None
+  */
+void SysTick_Handler(void)
+{
+  uint8_t *buf;
+  uint8_t temp1, temp2 = 0x00;
+  
+  if (DemoEnterCondition == 0x00)
+  {
+    TimingDelay_Decrement();
+  }
+  else
+  {
+    buf = USBD_HID_GetPos();
+    if((buf[1] != 0) ||(buf[2] != 0))
+    {
+      USBD_HID_SendReport (&USB_OTG_dev, 
+                           buf,
+                           4);
+    } 
+    Counter ++;
+    if (Counter == 10)
+    {
+      Buffer[0] = 0;
+      Buffer[2] = 0;
+      /* Disable All TIM4 Capture Compare Channels */
+      TIM_CCxCmd(TIM4, TIM_Channel_1, DISABLE);
+      TIM_CCxCmd(TIM4, TIM_Channel_2, DISABLE);
+      TIM_CCxCmd(TIM4, TIM_Channel_3, DISABLE);
+      TIM_CCxCmd(TIM4, TIM_Channel_4, DISABLE);
+      
+      LIS302DL_Read(Buffer, LIS302DL_OUT_X_ADDR, 6);
+      /* Remove the offsets values from data */
+      Buffer[0] -= X_Offset;
+      Buffer[2] -= Y_Offset;
+      /* Update autoreload and capture compare registers value*/
+      temp1 = ABS((int8_t)(Buffer[0]));
+      temp2 = ABS((int8_t)(Buffer[2]));       
+      TempAcceleration = MAX(temp1, temp2);
+
+      if(TempAcceleration != 0)
+      { 
+        if ((int8_t)Buffer[0] < -2)
+        {
+          /* Enable TIM4 Capture Compare Channel 4 */
+          TIM_CCxCmd(TIM4, TIM_Channel_4, ENABLE);
+          /* Sets the TIM4 Capture Compare4 Register value */
+          TIM_SetCompare4(TIM4, TIM_CCR/TempAcceleration);
+        }
+        if ((int8_t)Buffer[0] > 2)
+        {
+          /* Enable TIM4 Capture Compare Channel 2 */
+          TIM_CCxCmd(TIM4, TIM_Channel_2, ENABLE);
+          /* Sets the TIM4 Capture Compare2 Register value */
+          TIM_SetCompare2(TIM4, TIM_CCR/TempAcceleration);
+        }
+        if ((int8_t)Buffer[2] > 2)
+        { 
+          /* Enable TIM4 Capture Compare Channel 1 */
+          TIM_CCxCmd(TIM4, TIM_Channel_1, ENABLE);
+          /* Sets the TIM4 Capture Compare1 Register value */
+          TIM_SetCompare1(TIM4, TIM_CCR/TempAcceleration);
+        }      
+        if ((int8_t)Buffer[2] < -2)
+        { 
+          /* Enable TIM4 Capture Compare Channel 3 */
+          TIM_CCxCmd(TIM4, TIM_Channel_3, ENABLE);
+          /* Sets the TIM4 Capture Compare3 Register value */
+          TIM_SetCompare3(TIM4, TIM_CCR/TempAcceleration);
+        }
+        /* Time base configuration */
+        TIM_SetAutoreload(TIM4,  TIM_ARR/TempAcceleration);
+      }
+      Counter = 0x00;
+    }  
+  }
+  
+}
+
+/******************************************************************************/
+/*                 STM32Fxxx Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32fxxx.s).                                               */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @brief  This function handles EXTI0_IRQ Handler.
+  * @param  None
+  * @retval None
+  */
+void EXTI0_IRQHandler(void)
+{
+  UserButtonPressed = 0x01;
+  
+  /* Clear the EXTI line pending bit */
+  EXTI_ClearITPendingBit(USER_BUTTON_EXTI_LINE);
+}
+
+/**
+  * @brief  This function handles EXTI15_10_IRQ Handler.
+  * @param  None
+  * @retval None
+  */
+void OTG_FS_WKUP_IRQHandler(void)
+{
+  if(USB_OTG_dev.cfg.low_power)
+  {
+	/* Reset SLEEPDEEP and SLEEPONEXIT bits */
+	SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));
+
+	/* After wake-up from sleep mode, reconfigure the system clock */
+	SystemInit();
+    USB_OTG_UngateClock(&USB_OTG_dev);
+  }
+  EXTI_ClearITPendingBit(EXTI_Line18);
+}
+
+/**
+  * @brief  This function handles OTG_HS Handler.
+  * @param  None
+  * @retval None
+  */
+void OTG_FS_IRQHandler(void)
+{
+  USBD_OTG_ISR_Handler (&USB_OTG_dev);
+}
+
+/**
+* @brief  USBD_HID_GetPos
+* @param  None
+* @retval Pointer to report
+*/
+static uint8_t *USBD_HID_GetPos (void)
+{
+  static uint8_t HID_Buffer[4] = {0};
+  
+  HID_Buffer[1] = 0;
+  HID_Buffer[2] = 0;
+  /* LEFT Direction */
+  if(((int8_t)Buffer[2]) < -2)
+  {
+    HID_Buffer[1] += CURSOR_STEP;
+  }
+  /* RIGHT Direction */ 
+  if(((int8_t)Buffer[2]) > 2)
+  {
+   HID_Buffer[1] -= CURSOR_STEP;
+  } 
+  /* UP Direction */
+  if(((int8_t)Buffer[0]) < -2)
+  {
+    HID_Buffer[2] += CURSOR_STEP;
+  }
+  /* DOWN Direction */ 
+  if(((int8_t)Buffer[0]) > 2)
+  {
+    HID_Buffer[2] -= CURSOR_STEP;
+  } 
+  
+  return HID_Buffer;
+}
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/stm32f4xx_it.h b/exampleF4/Projects/discovery_demo/stm32f4xx_it.h
new file mode 100644
index 0000000..4ae766c
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/stm32f4xx_it.h
@@ -0,0 +1,54 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.h 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_conf.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/system_stm32f4xx.c b/exampleF4/Projects/discovery_demo/system_stm32f4xx.c
new file mode 100644
index 0000000..fbb195c
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/system_stm32f4xx.c
@@ -0,0 +1,566 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F4xx devices,
+  *          and is generated by the clock configuration tool
+  *          stm32f4xx_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define
+  *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F4xx device revision    | Rev A
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 168000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 168000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 8000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 8
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 336
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | 192
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | 5
+  *-----------------------------------------------------------------------------
+  *        I2S input clock(Hz)                    | 38400000
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        High Performance mode                  | Enabled
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 5
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | OFF
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f4xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM324xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      8
+#define PLL_N      336
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      7
+
+/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N
+   I2SCLK = PLLI2S_VCO / PLLI2S_R */
+#define PLLI2S_N   192
+#define PLLI2S_R   5
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 168000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable high performance mode, System frequency up to 168 MHz */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_PMODE;  
+
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+/******************************************************************************/
+/*                        I2S clock configuration                             */
+/******************************************************************************/
+  /* PLLI2S clock used as I2S clock source */
+  RCC->CFGR &= ~RCC_CFGR_I2SSRC;
+
+  /* Configure PLLI2S */
+  RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);
+
+  /* Enable PLLI2S */
+  RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);
+
+  /* Wait till PLLI2S is ready */
+  while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)
+  {
+  }
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM324xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 | 
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 | 
+ | PD4  <-> FSMC_NOE | PE3  <-> FSMC_A19  | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 | 
+ | PD5  <-> FSMC_NWE | PE4  <-> FSMC_A20  | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 | 
+ | PD8  <-> FSMC_D13 | PE7  <-> FSMC_D4   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 | 
+ | PD9  <-> FSMC_D14 | PE8  <-> FSMC_D5   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 | 
+ | PD10 <-> FSMC_D15 | PE9  <-> FSMC_D6   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | 
+ | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8   | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9   | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE13 <-> FSMC_D10  |------------------+
+ | PD15 <-> FSMC_D1  | PE14 <-> FSMC_D11  |
+ |                   | PE15 <-> FSMC_D12  |
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xaaaa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xffff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00cc0cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa828a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc3cf;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010603;//0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 3;//0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 6;//4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
diff --git a/exampleF4/Projects/discovery_demo/usb_bsp.c b/exampleF4/Projects/discovery_demo/usb_bsp.c
new file mode 100644
index 0000000..6861d65
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/usb_bsp.c
@@ -0,0 +1,382 @@
+/**
+  ******************************************************************************
+  * @file    usb_bsp.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   This file is responsible to offer board support package and is 
+  *          configurable by user.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_bsp.h"
+#include "usbd_conf.h"
+#include "stm32f4_discovery.h"
+
+//Library config for this project!!!!!!!!!!!
+#include "stm32f4xx_conf.h"
+
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+* @{
+*/
+
+/** @defgroup USB_BSP
+* @brief This file is responsible to offer board support package
+* @{
+*/ 
+
+/** @defgroup USB_BSP_Private_Defines
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup USB_BSP_Private_TypesDefinitions
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+
+
+
+/** @defgroup USB_BSP_Private_Macros
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+/** @defgroup USBH_BSP_Private_Variables
+* @{
+*/ 
+
+/**
+* @}
+*/ 
+
+/** @defgroup USBH_BSP_Private_FunctionPrototypes
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+/** @defgroup USB_BSP_Private_Functions
+* @{
+*/ 
+
+
+/**
+* @brief  USB_OTG_BSP_Init
+*         Initilizes BSP configurations
+* @param  None
+* @retval None
+*/
+
+void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+
+#ifndef USE_ULPI_PHY 
+#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
+  EXTI_InitTypeDef EXTI_InitStructure;
+  NVIC_InitTypeDef NVIC_InitStructure; 
+#endif  
+#endif
+  
+ 
+ #ifdef USE_USB_OTG_FS 
+
+  RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA , ENABLE);  
+  
+  /* Configure SOF VBUS ID DM DP Pins */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8  | 
+    GPIO_Pin_9  | 
+      GPIO_Pin_11 | 
+        GPIO_Pin_12;
+  
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);  
+  
+  GPIO_PinAFConfig(GPIOA,GPIO_PinSource8,GPIO_AF_OTG1_FS) ;
+  GPIO_PinAFConfig(GPIOA,GPIO_PinSource9,GPIO_AF_OTG1_FS) ; 
+  GPIO_PinAFConfig(GPIOA,GPIO_PinSource11,GPIO_AF_OTG1_FS) ; 
+  GPIO_PinAFConfig(GPIOA,GPIO_PinSource12,GPIO_AF_OTG1_FS) ;
+  
+  /* this for ID line debug */
+  
+  
+  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_10;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ;  
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);  
+  GPIO_PinAFConfig(GPIOA,GPIO_PinSource10,GPIO_AF_OTG1_FS) ;   
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE) ; 
+ #else // USE_USB_OTG_HS 
+
+  #ifdef USE_ULPI_PHY // ULPI
+  RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | 
+                         RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOH | 
+                           RCC_AHB1Periph_GPIOI, ENABLE);    
+  
+  
+  GPIO_PinAFConfig(GPIOA,GPIO_PinSource3, GPIO_AF_OTG2_HS) ; // D0
+  GPIO_PinAFConfig(GPIOA,GPIO_PinSource5, GPIO_AF_OTG2_HS) ; // CLK
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource0, GPIO_AF_OTG2_HS) ; // D1
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource1, GPIO_AF_OTG2_HS) ; // D2
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource5, GPIO_AF_OTG2_HS) ; // D7
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource10,GPIO_AF_OTG2_HS) ; // D3
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource11,GPIO_AF_OTG2_HS) ; // D4
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource12,GPIO_AF_OTG2_HS) ; // D5
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource13,GPIO_AF_OTG2_HS) ; // D6
+  GPIO_PinAFConfig(GPIOH,GPIO_PinSource4, GPIO_AF_OTG2_HS) ; // NXT
+  GPIO_PinAFConfig(GPIOI,GPIO_PinSource11,GPIO_AF_OTG2_HS) ; // DIR
+  GPIO_PinAFConfig(GPIOC,GPIO_PinSource0, GPIO_AF_OTG2_HS) ; // STP
+  
+  // CLK
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 ; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);  
+  
+  // D0
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3  ; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);  
+  
+  
+  
+  // D1 D2 D3 D4 D5 D6 D7
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1  |
+    GPIO_Pin_5 | GPIO_Pin_10 | 
+      GPIO_Pin_11| GPIO_Pin_12 | 
+        GPIO_Pin_13 ;
+  
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);  
+  
+  
+  // STP
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0  ;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);  
+  
+  //NXT  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_Init(GPIOH, &GPIO_InitStructure);  
+  
+  
+  //DIR
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 ; 
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_Init(GPIOI, &GPIO_InitStructure);  
+  
+  
+  RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_OTG_HS | 
+                         RCC_AHB1Periph_OTG_HS_ULPI, ENABLE) ;    
+   
+  #else
+   #ifdef USE_I2C_PHY    
+  RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOB , ENABLE);  
+  /* Configure RESET INTN SCL SDA (Phy/I2C) Pins */
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | 
+    GPIO_Pin_1 | 
+      GPIO_Pin_10 | 
+        GPIO_Pin_11;
+  
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);  
+  
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource0,GPIO_AF_OTG2_FS) ; 
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource1,GPIO_AF_OTG2_FS) ; 
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource10,GPIO_AF_OTG2_FS) ; 
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource11,GPIO_AF_OTG2_FS);
+  RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_OTG_HS, ENABLE) ;  
+  
+   #else
+
+  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB , ENABLE);
+  
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12  | 
+    GPIO_Pin_13 |
+      GPIO_Pin_14 | 
+        GPIO_Pin_15;
+  
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);  
+  
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource12, GPIO_AF_OTG2_FS) ; 
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource13,GPIO_AF_OTG2_FS) ; 
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource14,GPIO_AF_OTG2_FS) ; 
+  GPIO_PinAFConfig(GPIOB,GPIO_PinSource15,GPIO_AF_OTG2_FS) ;
+  RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_OTG_HS, ENABLE) ;  
+   #endif  
+  #endif // USE_ULPI_PHY
+  
+ #endif //USB_OTG_HS
+
+  
+  /* enable the PWR clock */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);   
+  
+  /* Configure the Key button in EXTI mode */
+  STM_EVAL_PBInit(BUTTON_USER, BUTTON_MODE_EXTI);
+  
+#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
+  EXTI_ClearITPendingBit(EXTI_Line18);
+  
+  EXTI_InitStructure.EXTI_Line = EXTI_Line18; 
+  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+
+  EXTI_ClearITPendingBit(EXTI_Line18);   
+
+  NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_WKUP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  EXTI_ClearITPendingBit(EXTI_Line18);    
+#endif 
+  
+#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
+  EXTI_ClearITPendingBit(EXTI_Line20);
+  
+  EXTI_InitStructure.EXTI_Line = EXTI_Line20; 
+  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+  EXTI_Init(&EXTI_InitStructure);
+
+  EXTI_ClearITPendingBit(EXTI_Line20);   
+
+  NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_WKUP_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+
+  EXTI_ClearITPendingBit(EXTI_Line20);    
+#endif   
+
+  EXTI_ClearITPendingBit(USER_BUTTON_EXTI_LINE);  
+}
+/**
+* @brief  USB_OTG_BSP_EnableInterrupt
+*         Enabele USB Global interrupt
+* @param  None
+* @retval None
+*/
+void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev)
+{
+  NVIC_InitTypeDef NVIC_InitStructure; 
+  
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
+#ifdef USE_USB_OTG_HS   
+  NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_IRQn;
+#else
+  NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_IRQn;  
+#endif
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);  
+#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
+  NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_EP1_OUT_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);  
+  
+  NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
+  NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_EP1_IN_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);   
+#endif
+}
+/**
+* @brief  USB_OTG_BSP_uDelay
+*         This function provides delay time in micro sec
+* @param  usec : Value of delay required in micro sec
+* @retval None
+*/
+void USB_OTG_BSP_uDelay (const uint32_t usec)
+{
+  uint32_t count = 0;
+  const uint32_t utime = (120 * usec / 7);
+  do
+  {
+    if ( ++count > utime )
+    {
+      return ;
+    }
+  }
+  while (1);
+}
+
+
+/**
+* @brief  USB_OTG_BSP_mDelay
+*          This function provides delay time in milli sec
+* @param  msec : Value of delay required in milli sec
+* @retval None
+*/
+void USB_OTG_BSP_mDelay (const uint32_t msec)
+{
+  USB_OTG_BSP_uDelay(msec * 1000);   
+}
+/**
+* @}
+*/ 
+
+/**
+* @}
+*/ 
+
+/**
+* @}
+*/
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/usb_conf.h b/exampleF4/Projects/discovery_demo/usb_conf.h
new file mode 100644
index 0000000..eeb2f79
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/usb_conf.h
@@ -0,0 +1,252 @@
+/**
+  ******************************************************************************
+  * @file    usb_conf.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   General low level driver configuration
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_CONF__H__
+#define __USB_CONF__H__
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+
+/** @addtogroup USB_OTG_DRIVER
+  * @{
+  */
+  
+/** @defgroup USB_CONF
+  * @brief USB low level driver configuration file
+  * @{
+  */ 
+
+/** @defgroup USB_CONF_Exported_Defines
+  * @{
+  */ 
+
+/* USB Core and PHY interface configuration.
+   Tip: To avoid modifying these defines each time you need to change the USB
+        configuration, you can declare the needed define in your toolchain
+        compiler preprocessor.
+   */
+#ifndef USE_USB_OTG_FS
+ //#define USE_USB_OTG_FS
+#endif /* USE_USB_OTG_FS */
+
+#ifdef USE_USB_OTG_FS 
+ #define USB_OTG_FS_CORE
+#endif
+
+/*******************************************************************************
+*                      FIFO Size Configuration in Device mode
+*  
+*  (i) Receive data FIFO size = RAM for setup packets + 
+*                   OUT endpoint control information +
+*                   data OUT packets + miscellaneous
+*      Space = ONE 32-bits words
+*     --> RAM for setup packets = 10 spaces
+*        (n is the nbr of CTRL EPs the device core supports) 
+*     --> OUT EP CTRL info      = 1 space
+*        (one space for status information written to the FIFO along with each 
+*        received packet)
+*     --> data OUT packets      = (Largest Packet Size / 4) + 1 spaces 
+*        (MINIMUM to receive packets)
+*     --> OR data OUT packets  = at least 2*(Largest Packet Size / 4) + 1 spaces 
+*        (if high-bandwidth EP is enabled or multiple isochronous EPs)
+*     --> miscellaneous = 1 space per OUT EP
+*        (one space for transfer complete status information also pushed to the 
+*        FIFO with each endpoint's last packet)
+*
+*  (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for 
+*       that particular IN EP. More space allocated in the IN EP Tx FIFO results
+*       in a better performance on the USB and can hide latencies on the AHB.
+*
+*  (iii) TXn min size = 16 words. (n  : Transmit FIFO index)
+*   (iv) When a TxFIFO is not used, the Configuration should be as follows: 
+*       case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+*       --> Txm can use the space allocated for Txn.
+*       case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+*       --> Txn should be configured with the minimum space of 16 words
+*  (v) The FIFO is used optimally when used TxFIFOs are allocated in the top 
+*       of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+*******************************************************************************/
+ 
+
+
+/****************** USB OTG FS CONFIGURATION **********************************/
+#ifdef USB_OTG_FS_CORE
+ #define RX_FIFO_FS_SIZE                          128
+ #define TX0_FIFO_FS_SIZE                          64
+ #define TX1_FIFO_FS_SIZE                         128
+ #define TX2_FIFO_FS_SIZE                          0
+ #define TX3_FIFO_FS_SIZE                          0
+
+ //#define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
+ //#define USB_OTG_FS_SOF_OUTPUT_ENABLED
+#endif
+
+/****************** USB OTG MODE CONFIGURATION ********************************/
+
+//#define USE_HOST_MODE
+#define USE_DEVICE_MODE
+//#define USE_OTG_MODE
+
+
+#ifndef USB_OTG_FS_CORE
+ #ifndef USB_OTG_HS_CORE
+    #error  "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined"
+ #endif
+#endif
+
+
+#ifndef USE_DEVICE_MODE
+ #ifndef USE_HOST_MODE
+    #error  "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
+ #endif
+#endif
+
+#ifndef USE_USB_OTG_HS
+ #ifndef USE_USB_OTG_FS
+    #error  "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined"
+ #endif
+#else //USE_USB_OTG_HS
+ #ifndef USE_ULPI_PHY
+  #ifndef USE_EMBEDDED_PHY
+   #ifndef USE_I2C_PHY
+     #error  "USE_ULPI_PHY or USE_EMBEDDED_PHY or USE_I2C_PHY should be defined"
+   #endif
+  #endif
+ #endif
+#endif
+
+/****************** C Compilers dependant keywords ****************************/
+/* In HS mode and when the DMA is used, all variables and data structures dealing
+   with the DMA during the transaction process should be 4-bytes aligned */    
+#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
+  #if defined   (__GNUC__)        /* GNU Compiler */
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+    #define __ALIGN_BEGIN         
+  #else                           
+    #define __ALIGN_END
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)  
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN 
+    #elif defined  (__TASKING__)  /* TASKING Compiler */
+      #define __ALIGN_BEGIN    __align(4) 
+    #endif /* __CC_ARM */  
+  #endif /* __GNUC__ */ 
+#else
+  #define __ALIGN_BEGIN
+  #define __ALIGN_END   
+#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
+
+/* __packed keyword used to decrease the data type alignment to 1-byte */
+#if defined (__CC_ARM)         /* ARM Compiler */
+  #define __packed    __packed
+#elif defined (__ICCARM__)     /* IAR Compiler */
+  #define __packed    __packed
+#elif defined   ( __GNUC__ )   /* GNU Compiler */                        
+  #define __packed    __attribute__ ((__packed__))
+#elif defined   (__TASKING__)  /* TASKING Compiler */
+  #define __packed    __unaligned
+#endif /* __CC_ARM */
+
+/****************** C Compilers dependant keywords ****************************/
+/* In HS mode and when the DMA is used, all variables and data structures dealing
+   with the DMA during the transaction process should be 4-bytes aligned */    
+#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
+  #if defined   (__GNUC__)        /* GNU Compiler */
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+    #define __ALIGN_BEGIN         
+  #else                           
+    #define __ALIGN_END
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)  
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN 
+    #elif defined  (__TASKING__)  /* TASKING Compiler */
+      #define __ALIGN_BEGIN    __align(4) 
+    #endif /* __CC_ARM */  
+  #endif /* __GNUC__ */ 
+#else
+  #define __ALIGN_BEGIN
+  #define __ALIGN_END   
+#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
+
+/* __packed keyword used to decrease the data type alignment to 1-byte */
+#if defined (__CC_ARM)         /* ARM Compiler */
+  #define __packed    __packed
+#elif defined (__ICCARM__)     /* IAR Compiler */
+  #define __packed    __packed
+#elif defined   ( __GNUC__ )   /* GNU Compiler */                        
+  #define __packed    __attribute__ ((__packed__))
+#elif defined   (__TASKING__)  /* TASKING Compiler */
+  #define __packed    __unaligned
+#endif /* __CC_ARM */
+
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USB_CONF_Exported_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USB_CONF_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup USB_CONF_Exported_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup USB_CONF_Exported_FunctionsPrototype
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+#endif //__USB_CONF__H__
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
diff --git a/exampleF4/Projects/discovery_demo/usb_core.c b/exampleF4/Projects/discovery_demo/usb_core.c
new file mode 100644
index 0000000..74e432a
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/usb_core.c
@@ -0,0 +1,2187 @@
+/**
+  ******************************************************************************
+  * @file    usb_core.c
+  * @author  MCD Application Team
+  * @version V2.0.0
+  * @date    22-July-2011
+  * @brief   USB-OTG Core Layer
+  ******************************************************************************
+  * @attention 
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_core.h"
+#include "usb_bsp.h"
+
+
+/** @addtogroup USB_OTG_DRIVER
+* @{
+*/
+
+/** @defgroup USB_CORE 
+* @brief This file includes the USB-OTG Core Layer
+* @{
+*/
+
+
+/** @defgroup USB_CORE_Private_Defines
+* @{
+*/ 
+
+/**
+* @}
+*/ 
+
+
+/** @defgroup USB_CORE_Private_TypesDefinitions
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+
+/** @defgroup USB_CORE_Private_Macros
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup USB_CORE_Private_Variables
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup USB_CORE_Private_FunctionPrototypes
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup USB_CORE_Private_Functions
+* @{
+*/ 
+
+/**
+* @brief  USB_OTG_EnableCommonInt
+*         Initializes the commmon interrupts, used in both device and modes
+* @param  pdev : Selected device
+* @retval None
+*/
+static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_GINTMSK_TypeDef  int_mask;
+  
+  int_mask.d32 = 0;
+  /* Clear any pending USB_OTG Interrupts */
+#ifndef USE_OTG_MODE
+  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF);
+#endif
+  /* Clear any pending interrupts */
+  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
+  /* Enable the interrupts in the INTMSK */
+  int_mask.b.wkupintr = 1;
+  int_mask.b.usbsuspend = 1; 
+  
+#ifdef USE_OTG_MODE
+  int_mask.b.otgintr = 1;
+  int_mask.b.sessreqintr = 1;
+  int_mask.b.conidstschng = 1;
+#endif
+  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32);
+}
+
+/**
+* @brief  USB_OTG_CoreReset : Soft reset of the core
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  __IO USB_OTG_GRSTCTL_TypeDef  greset;
+  uint32_t count = 0;
+  
+  greset.d32 = 0;
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    USB_OTG_BSP_uDelay(3);
+    greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
+    if (++count > 200000)
+    {
+      return USB_OTG_OK;
+    }
+  }
+  while (greset.b.ahbidle == 0);
+  /* Core Soft Reset */
+  count = 0;
+  greset.b.csftrst = 1;
+  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 );
+  do
+  {
+    greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL);
+    if (++count > 200000)
+    {
+      break;
+    }
+  }
+  while (greset.b.csftrst == 1);
+  /* Wait for 3 PHY Clocks*/
+  USB_OTG_BSP_uDelay(3);
+  return status;
+}
+
+/**
+* @brief  USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated 
+*         with the EP
+* @param  pdev : Selected device
+* @param  src : source pointer
+* @param  ch_ep_num : end point number
+* @param  bytes : No. of bytes
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, 
+                                uint8_t             *src, 
+                                uint8_t             ch_ep_num, 
+                                uint16_t            len)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  if (pdev->cfg.dma_enable == 0)
+  {
+    uint32_t count32b= 0 , i= 0;
+    __IO uint32_t *fifo;
+    
+    count32b =  (len + 3) / 4;
+    fifo = pdev->regs.DFIFO[ch_ep_num];
+    for (i = 0; i < count32b; i++, src+=4)
+    {
+      USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) );
+    }
+  }
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_ReadPacket : Reads a packet from the Rx FIFO
+* @param  pdev : Selected device
+* @param  dest : Destination Pointer
+* @param  bytes : No. of bytes
+* @retval None
+*/
+void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, 
+                         uint8_t *dest, 
+                         uint16_t len)
+{
+  uint32_t i=0;
+  uint32_t count32b = (len + 3) / 4;
+  
+  __IO uint32_t *fifo = pdev->regs.DFIFO[0];
+  
+  for ( i = 0; i < count32b; i++, dest += 4 )
+  {
+    *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo);
+    
+  }
+  return ((void *)dest);
+}
+
+/**
+* @brief  USB_OTG_SelectCore 
+*         Initialize core registers address.
+* @param  pdev : Selected device
+* @param  coreID : USB OTG Core ID
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, 
+                               USB_OTG_CORE_ID_TypeDef coreID)
+{
+  uint32_t i , baseAddress = 0;
+  USB_OTG_STS status = USB_OTG_OK;
+  
+  pdev->cfg.dma_enable       = 0;
+  
+  /* at startup the core is in FS mode */
+  pdev->cfg.speed            = USB_OTG_SPEED_FULL;
+  pdev->cfg.mps              = USB_OTG_FS_MAX_PACKET_SIZE ;    
+    
+  /* initialize device cfg following its address */
+  if (coreID == USB_OTG_FS_CORE_ID)
+  {
+    baseAddress                = USB_OTG_FS_BASE_ADDR;
+    pdev->cfg.coreID           = USB_OTG_FS_CORE_ID;
+    pdev->cfg.host_channels    = 8 ;
+    pdev->cfg.dev_endpoints    = 4 ;
+    pdev->cfg.TotalFifoSize    = 320; /* in 32-bits */
+    pdev->cfg.phy_itface       = USB_OTG_EMBEDDED_PHY;     
+    
+#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED    
+    pdev->cfg.Sof_output       = 1;    
+#endif 
+    
+#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT    
+    pdev->cfg.low_power        = 1;    
+#endif     
+  }
+  else if (coreID == USB_OTG_HS_CORE_ID)
+  {
+    baseAddress                = USB_OTG_HS_BASE_ADDR;
+    pdev->cfg.coreID           = USB_OTG_HS_CORE_ID;    
+    pdev->cfg.host_channels    = 12 ;
+    pdev->cfg.dev_endpoints    = 6 ;
+    pdev->cfg.TotalFifoSize    = 1280;/* in 32-bits */
+    
+#ifdef USB_OTG_ULPI_PHY_ENABLED
+    pdev->cfg.phy_itface       = USB_OTG_ULPI_PHY;
+#else    
+ #ifdef USB_OTG_EMBEDDED_PHY_ENABLED
+    pdev->cfg.phy_itface       = USB_OTG_EMBEDDED_PHY;
+ #else   
+   #ifdef USB_OTG_I2C_PHY_ENABLED    
+    pdev->cfg.phy_itface       = USB_OTG_I2C_PHY; 
+   #endif
+ #endif  
+#endif      
+    
+#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED    
+    pdev->cfg.dma_enable       = 1;    
+#endif
+    
+#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED    
+    pdev->cfg.Sof_output       = 1;    
+#endif 
+    
+#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT    
+    pdev->cfg.low_power        = 1;    
+#endif 
+    
+  }
+  
+  pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \
+    USB_OTG_CORE_GLOBAL_REGS_OFFSET);
+  pdev->regs.DREGS =  (USB_OTG_DREGS  *)  (baseAddress + \
+    USB_OTG_DEV_GLOBAL_REG_OFFSET);
+  
+  for (i = 0; i < pdev->cfg.dev_endpoints; i++)
+  {
+    pdev->regs.INEP_REGS[i]  = (USB_OTG_INEPREGS *)  \
+      (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \
+        (i * USB_OTG_EP_REG_OFFSET));
+    pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \
+      (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \
+        (i * USB_OTG_EP_REG_OFFSET));
+  }
+  pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \
+    USB_OTG_HOST_GLOBAL_REG_OFFSET);
+  pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET);
+  
+  for (i = 0; i < pdev->cfg.host_channels; i++)
+  {
+    pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \
+      USB_OTG_HOST_CHAN_REGS_OFFSET + \
+        (i * USB_OTG_CHAN_REGS_OFFSET));
+  }
+  for (i = 0; i < pdev->cfg.host_channels; i++)
+  {
+    pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\
+      (i * USB_OTG_DATA_FIFO_SIZE));
+  }
+  pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET);
+  
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_CoreInit
+*         Initializes the USB_OTG controller registers and prepares the core
+*         device mode or host mode operation.
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_GUSBCFG_TypeDef  usbcfg;
+  USB_OTG_GCCFG_TypeDef    gccfg;
+  USB_OTG_GI2CCTL_TypeDef  i2cctl;
+  USB_OTG_GAHBCFG_TypeDef  ahbcfg;
+  
+  usbcfg.d32 = 0;
+  gccfg.d32 = 0;
+  ahbcfg.d32 = 0;
+  
+
+  
+  if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
+  {
+    gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG);
+    gccfg.b.pwdn = 0;
+    
+    if (pdev->cfg.Sof_output)
+    {
+      gccfg.b.sofouten = 1;   
+    }
+    USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
+    
+    /* Init The ULPI Interface */
+    usbcfg.d32 = 0;
+    usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
+    
+    usbcfg.b.physel            = 0; /* HS Interface */
+#ifdef USB_OTG_INTERNAL_VBUS_ENABLED
+    usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */
+#else
+ #ifdef USB_OTG_EXTERNAL_VBUS_ENABLED    
+    usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */
+ #endif
+#endif 
+    usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */    
+    usbcfg.b.ulpi_utmi_sel     = 1; /* ULPI seleInterfacect */
+    
+    usbcfg.b.phyif             = 0; /* 8 bits */
+    usbcfg.b.ddrsel            = 0; /* single data rate */
+    
+    usbcfg.b.ulpi_fsls = 0;
+    usbcfg.b.ulpi_clk_sus_m = 0;
+    USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
+    
+    /* Reset after a PHY select  */
+    USB_OTG_CoreReset(pdev);
+    
+    if(pdev->cfg.dma_enable == 1)
+    {
+      
+      ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
+      ahbcfg.b.dmaenable = 1;
+      USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
+      
+    }    
+  }
+  else /* FS interface (embedded Phy or I2C Phy) */
+  {
+    
+    usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);;
+    usbcfg.b.physel  = 1; /* FS Interface */
+    USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
+    /* Reset after a PHY select and set Host mode */
+    USB_OTG_CoreReset(pdev);
+    /* Enable the I2C interface and deactivate the power down*/
+    gccfg.d32 = 0;
+    gccfg.b.pwdn = 1;
+    
+    if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
+    {
+      gccfg.b.i2cifen = 1;
+    }   
+    gccfg.b.vbussensingA = 1 ;
+    gccfg.b.vbussensingB = 1 ;     
+#ifndef VBUS_SENSING_ENABLED
+    gccfg.b.disablevbussensing = 1; 
+#endif    
+    
+    if(pdev->cfg.Sof_output)
+    {
+      gccfg.b.sofouten = 1;  
+    }
+    
+    USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32);
+    USB_OTG_BSP_mDelay(20);
+    /* Program GUSBCFG.OtgUtmifsSel to I2C*/
+    usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
+    
+    if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
+    {
+      usbcfg.b.otgutmifssel = 1;
+    }
+    
+    USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
+    
+    if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY)
+    {
+      /*Program GI2CCTL.I2CEn*/
+      i2cctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GI2CCTL);
+      i2cctl.b.i2cdevaddr = 1;
+      i2cctl.b.i2cen = 0;
+      i2cctl.b.dat_se0 = 1;
+      i2cctl.b.addr = 0x2D;
+      USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
+      
+      USB_OTG_BSP_mDelay(200);
+      
+      i2cctl.b.i2cen = 1;
+      USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32);
+      USB_OTG_BSP_mDelay(200);
+    }
+  }
+  /* case the HS core is working in FS mode */
+  if(pdev->cfg.dma_enable == 1)
+  {
+    
+    ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG);
+    ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/
+    ahbcfg.b.dmaenable = 1;
+    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32);
+    
+  }
+  /* initialize OTG features */
+#ifdef  USE_OTG_MODE
+  usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
+  usbcfg.b.hnpcap = 1;
+  usbcfg.b.srpcap = 1;
+  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
+  USB_OTG_EnableCommonInt(pdev);
+#endif
+  return status;
+}
+/**
+* @brief  USB_OTG_EnableGlobalInt
+*         Enables the controller's Global Int in the AHB Config reg
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_GAHBCFG_TypeDef  ahbcfg;
+  
+  ahbcfg.d32 = 0;
+  ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
+  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_DisableGlobalInt
+*         Enables the controller's Global Int in the AHB Config reg
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_GAHBCFG_TypeDef  ahbcfg;
+  ahbcfg.d32 = 0;
+  ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
+  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
+* @param  pdev : Selected device
+* @param  num : FO num
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num )
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  __IO USB_OTG_GRSTCTL_TypeDef  greset;
+  
+  uint32_t count = 0;
+  greset.d32 = 0;
+  greset.b.txfflsh = 1;
+  greset.b.txfnum  = num;
+  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
+  do
+  {
+    greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
+    if (++count > 200000)
+    {
+      break;
+    }
+  }
+  while (greset.b.txfflsh == 1);
+  /* Wait for 3 PHY Clocks*/
+  USB_OTG_BSP_uDelay(3);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_FlushRxFifo : Flush a Rx FIFO
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev )
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  __IO USB_OTG_GRSTCTL_TypeDef  greset;
+  uint32_t count = 0;
+  
+  greset.d32 = 0;
+  greset.b.rxfflsh = 1;
+  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 );
+  do
+  {
+    greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL);
+    if (++count > 200000)
+    {
+      break;
+    }
+  }
+  while (greset.b.rxfflsh == 1);
+  /* Wait for 3 PHY Clocks*/
+  USB_OTG_BSP_uDelay(3);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_SetCurrentMode : Set ID line
+* @param  pdev : Selected device
+* @param  mode :  (Host/device)
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_GUSBCFG_TypeDef  usbcfg;
+  
+  usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
+  
+  usbcfg.b.force_host = 0;
+  usbcfg.b.force_dev = 0;
+  
+  if ( mode == HOST_MODE)
+  {
+    usbcfg.b.force_host = 1;
+  }
+  else if ( mode == DEVICE_MODE)
+  {
+    usbcfg.b.force_dev = 1;
+  }
+  
+  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32);
+  USB_OTG_BSP_mDelay(50);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_GetMode : Get current mode
+* @param  pdev : Selected device
+* @retval current mode
+*/
+uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev)
+{
+  return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1);
+}
+
+
+/**
+* @brief  USB_OTG_IsDeviceMode : Check if it is device mode
+* @param  pdev : Selected device
+* @retval num_in_ep
+*/
+uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev)
+{
+  return (USB_OTG_GetMode(pdev) != HOST_MODE);
+}
+
+
+/**
+* @brief  USB_OTG_IsHostMode : Check if it is host mode
+* @param  pdev : Selected device
+* @retval num_in_ep
+*/
+uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev)
+{
+  return (USB_OTG_GetMode(pdev) == HOST_MODE);
+}
+
+
+/**
+* @brief  USB_OTG_ReadCoreItr : returns the Core Interrupt register
+* @param  pdev : Selected device
+* @retval Status
+*/
+uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev)
+{
+  uint32_t v = 0;
+  v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS);
+  v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK);
+  return v;
+}
+
+
+/**
+* @brief  USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register
+* @param  pdev : Selected device
+* @retval Status
+*/
+uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev)
+{
+  return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT));
+}
+
+#ifdef USE_HOST_MODE
+/**
+* @brief  USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode
+* @param  pdev : Selected device
+* @retval status
+*/
+USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_STS                     status = USB_OTG_OK;
+  USB_OTG_FSIZ_TypeDef            nptxfifosize;
+  USB_OTG_FSIZ_TypeDef            ptxfifosize;  
+  USB_OTG_HCFG_TypeDef            hcfg;
+  
+#ifdef USE_OTG_MODE
+  USB_OTG_OTGCTL_TypeDef          gotgctl;
+#endif
+  
+  uint32_t                        i = 0;
+  
+  nptxfifosize.d32 = 0;  
+  ptxfifosize.d32 = 0;
+#ifdef USE_OTG_MODE
+  gotgctl.d32 = 0;
+#endif
+  hcfg.d32 = 0;
+  
+  
+  /* configure charge pump IO */
+  USB_OTG_BSP_ConfigVBUS(pdev);
+  
+  /* Restart the Phy Clock */
+  USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
+  
+  /* Initialize Host Configuration Register */
+  USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); /* in init phase */
+  
+  hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
+  hcfg.b.fslssupp = 0;
+  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
+  
+  /* Configure data FIFO sizes */
+  /* Rx FIFO */
+#ifdef USB_OTG_FS_CORE
+  if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID)
+  {
+    /* set Rx FIFO size */
+    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
+    nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;   
+    nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ;  
+    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
+    
+    ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ;
+    ptxfifosize.b.depth     = TXH_P_FS_FIFOSIZ;
+    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);      
+  }
+#endif
+#ifdef USB_OTG_HS_CORE  
+   if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID)
+  {
+   /* set Rx FIFO size */
+    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
+    nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;   
+    nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ;  
+    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
+    
+    ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ;
+    ptxfifosize.b.depth     = TXH_P_HS_FIFOSIZ;
+    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);      
+  }
+#endif  
+  
+#ifdef USE_OTG_MODE
+  /* Clear Host Set HNP Enable in the USB_OTG Control Register */
+  gotgctl.b.hstsethnpen = 1;
+  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0);
+#endif
+  
+  /* Make sure the FIFOs are flushed. */
+  USB_OTG_FlushTxFifo(pdev, 0x10 );         /* all Tx FIFOs */
+  USB_OTG_FlushRxFifo(pdev);
+  
+  
+  /* Clear all pending HC Interrupts */
+  for (i = 0; i < pdev->cfg.host_channels; i++)
+  {
+    USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF );
+    USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCGINTMSK, 0 );
+  }
+#ifndef USE_OTG_MODE
+  USB_OTG_DriveVbus(pdev, 1);
+#endif
+  
+  USB_OTG_EnableHostInt(pdev);
+  return status;
+}
+
+/**
+* @brief  USB_OTG_IsEvenFrame 
+*         This function returns the frame number for sof packet
+* @param  pdev : Selected device
+* @retval Frame number
+*/
+uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) 
+{
+  return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1);
+}
+
+/**
+* @brief  USB_OTG_DriveVbus : set/reset vbus
+* @param  pdev : Selected device
+* @param  state : VBUS state
+* @retval None
+*/
+void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state)
+{
+  USB_OTG_HPRT0_TypeDef     hprt0;
+  
+  hprt0.d32 = 0;
+  
+  /* enable disable the external charge pump */
+  USB_OTG_BSP_DriveVBUS(pdev, state);
+  
+  /* Turn on the Host port power. */
+  hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
+  if ((hprt0.b.prtpwr == 0 ) && (state == 1 ))
+  {
+    hprt0.b.prtpwr = 1;
+    USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
+  }
+  if ((hprt0.b.prtpwr == 1 ) && (state == 0 ))
+  {
+    hprt0.b.prtpwr = 0;
+    USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
+  }
+  
+  USB_OTG_BSP_mDelay(200);
+}
+/**
+* @brief  USB_OTG_EnableHostInt: Enables the Host mode interrupts
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_STS       status = USB_OTG_OK;
+  USB_OTG_GINTMSK_TypeDef  intmsk;
+  intmsk.d32 = 0;
+  /* Disable all interrupts. */
+  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0);
+  
+  /* Clear any pending interrupts. */
+  USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
+  
+  /* Enable the common interrupts */
+  USB_OTG_EnableCommonInt(pdev);
+  
+  if (pdev->cfg.dma_enable == 0)
+  {  
+    intmsk.b.rxstsqlvl  = 1;
+  }  
+  intmsk.b.portintr   = 1;
+  intmsk.b.hcintr     = 1;
+  intmsk.b.disconnect = 1;  
+  intmsk.b.sofintr    = 1;  
+  intmsk.b.incomplisoout  = 1; 
+  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
+  return status;
+}
+
+/**
+* @brief  USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the 
+*         HCFG register on the PHY type
+* @param  pdev : Selected device
+* @param  freq : clock frequency
+* @retval None
+*/
+void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq)
+{
+  USB_OTG_HCFG_TypeDef   hcfg;
+  
+  hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
+  hcfg.b.fslspclksel = freq;
+  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
+}
+
+
+/**
+* @brief  USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later
+* @param  pdev : Selected device
+* @retval HPRT0 value
+*/
+uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_HPRT0_TypeDef  hprt0;
+  
+  hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
+  hprt0.b.prtena = 0;
+  hprt0.b.prtconndet = 0;
+  hprt0.b.prtenchng = 0;
+  hprt0.b.prtovrcurrchng = 0;
+  return hprt0.d32;
+}
+
+
+/**
+* @brief  USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks
+* @param  pdev : Selected device
+* @retval Status
+*/
+uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev)
+{
+  return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT));
+}
+
+
+/**
+* @brief  USB_OTG_ResetPort : Reset Host Port
+* @param  pdev : Selected device
+* @retval status
+* @note : (1)The application must wait at least 10 ms (+ 10 ms security)
+*   before clearing the reset bit.
+*/
+uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_HPRT0_TypeDef  hprt0;
+  
+  hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
+  hprt0.b.prtrst = 1;
+  USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
+  USB_OTG_BSP_mDelay (10);                                /* See Note #1 */
+  hprt0.b.prtrst = 0;
+  USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
+  USB_OTG_BSP_mDelay (20);   
+  return 1;
+}
+
+
+/**
+* @brief  USB_OTG_HC_Init : Prepares a host channel for transferring packets
+* @param  pdev : Selected device
+* @param  hc_num : channel number
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  uint32_t intr_enable = 0;
+  USB_OTG_HCGINTMSK_TypeDef  hcintmsk;
+  USB_OTG_GINTMSK_TypeDef    gintmsk;
+  USB_OTG_HCCHAR_TypeDef     hcchar;
+  USB_OTG_HCINTn_TypeDef     hcint;
+  
+  
+  gintmsk.d32 = 0;
+  hcintmsk.d32 = 0;
+  hcchar.d32 = 0;
+  
+  /* Clear old interrupt conditions for this host channel. */
+  hcint.d32 = 0xFFFFFFFF;
+  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32);
+  
+  /* Enable channel interrupts required for this transfer. */
+  hcintmsk.d32 = 0;
+  
+  if (pdev->cfg.dma_enable == 1)
+  {
+    hcintmsk.b.ahberr = 1;
+  }
+  
+  switch (pdev->host.hc[hc_num].ep_type) 
+  {
+  case EP_TYPE_CTRL:
+  case EP_TYPE_BULK:
+    hcintmsk.b.xfercompl = 1;
+    hcintmsk.b.stall = 1;
+    hcintmsk.b.xacterr = 1;
+    hcintmsk.b.datatglerr = 1;
+    hcintmsk.b.nak = 1;  
+    if (pdev->host.hc[hc_num].ep_is_in) 
+    {
+      hcintmsk.b.bblerr = 1;
+    } 
+    else 
+    {
+      hcintmsk.b.nyet = 1;
+      if (pdev->host.hc[hc_num].do_ping) 
+      {
+        hcintmsk.b.ack = 1;
+      }
+    }
+    break;
+  case EP_TYPE_INTR:
+    hcintmsk.b.xfercompl = 1;
+    hcintmsk.b.nak = 1;
+    hcintmsk.b.stall = 1;
+    hcintmsk.b.xacterr = 1;
+    hcintmsk.b.datatglerr = 1;
+    hcintmsk.b.frmovrun = 1;
+    
+    if (pdev->host.hc[hc_num].ep_is_in) 
+    {
+      hcintmsk.b.bblerr = 1;
+    }
+    
+    break;
+  case EP_TYPE_ISOC:
+    hcintmsk.b.xfercompl = 1;
+    hcintmsk.b.frmovrun = 1;
+    hcintmsk.b.ack = 1;
+    
+    if (pdev->host.hc[hc_num].ep_is_in) 
+    {
+      hcintmsk.b.xacterr = 1;
+      hcintmsk.b.bblerr = 1;
+    }
+    break;
+  }
+  
+  
+  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, hcintmsk.d32);
+  
+  
+  /* Enable the top level host channel interrupt. */
+  intr_enable = (1 << hc_num);
+  USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable);
+  
+  /* Make sure host channel interrupts are enabled. */
+  gintmsk.b.hcintr = 1;
+  USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32);
+  
+  /* Program the HCCHAR register */
+  hcchar.d32 = 0;
+  hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr;
+  hcchar.b.epnum   = pdev->host.hc[hc_num].ep_num;
+  hcchar.b.epdir   = pdev->host.hc[hc_num].ep_is_in;
+  hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED);
+  hcchar.b.eptype  = pdev->host.hc[hc_num].ep_type;
+  hcchar.b.mps     = pdev->host.hc[hc_num].max_packet;
+  if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR)
+  {
+    hcchar.b.oddfrm  = 1;
+  }
+  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_HC_StartXfer : Start transfer
+* @param  pdev : Selected device
+* @param  hc_num : channel number
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_HCCHAR_TypeDef   hcchar;
+  USB_OTG_HCTSIZn_TypeDef  hctsiz;
+  USB_OTG_HNPTXSTS_TypeDef hnptxsts; 
+  USB_OTG_HPTXSTS_TypeDef  hptxsts; 
+  USB_OTG_GINTMSK_TypeDef  intmsk;
+  uint16_t                 len_words = 0;   
+  
+  uint16_t num_packets;
+  uint16_t max_hc_pkt_count;
+  
+  max_hc_pkt_count = 256;
+  hctsiz.d32 = 0;
+  hcchar.d32 = 0;
+  intmsk.d32 = 0;
+  
+  /* Compute the expected number of packets associated to the transfer */
+  if (pdev->host.hc[hc_num].xfer_len > 0)
+  {
+    num_packets = (pdev->host.hc[hc_num].xfer_len + \
+      pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet;
+    
+    if (num_packets > max_hc_pkt_count)
+    {
+      num_packets = max_hc_pkt_count;
+      pdev->host.hc[hc_num].xfer_len = num_packets * \
+        pdev->host.hc[hc_num].max_packet;
+    }
+  }
+  else
+  {
+    num_packets = 1;
+  }
+  if (pdev->host.hc[hc_num].ep_is_in)
+  {
+    pdev->host.hc[hc_num].xfer_len = num_packets * \
+      pdev->host.hc[hc_num].max_packet;
+  }
+  /* Initialize the HCTSIZn register */
+  hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len;
+  hctsiz.b.pktcnt = num_packets;
+  hctsiz.b.pid = pdev->host.hc[hc_num].data_pid;
+  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
+  
+  if (pdev->cfg.dma_enable == 1)
+  {
+    USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff);
+  }
+  
+  
+  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
+  hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev);
+  
+  /* Set host channel enable */
+  hcchar.b.chen = 1;
+  hcchar.b.chdis = 0;
+  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
+
+  if (pdev->cfg.dma_enable == 0) /* Slave mode */
+  {  
+    if((pdev->host.hc[hc_num].ep_is_in == 0) && 
+        (pdev->host.hc[hc_num].xfer_len > 0))
+    {
+      switch(pdev->host.hc[hc_num].ep_type) 
+      {
+        /* Non periodic transfer */
+      case EP_TYPE_CTRL:
+      case EP_TYPE_BULK:
+        
+        hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
+        len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
+        
+        /* check if there is enough space in FIFO space */
+        if(len_words > hnptxsts.b.nptxfspcavail)
+        {
+          /* need to process data in nptxfempty interrupt */
+          intmsk.b.nptxfempty = 1;
+          USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);  
+        }
+        
+        break;
+        /* Periodic transfer */
+      case EP_TYPE_INTR:
+      case EP_TYPE_ISOC:
+        hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
+        len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4;
+        /* check if there is enough space in FIFO space */
+        if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */
+        {
+          /* need to process data in ptxfempty interrupt */
+          intmsk.b.ptxfempty = 1;
+          USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);  
+        }
+        break;
+        
+      default:
+        break;
+      }
+      
+      /* Write packet into the Tx FIFO. */
+      USB_OTG_WritePacket(pdev, 
+                          pdev->host.hc[hc_num].xfer_buff , 
+                          hc_num, pdev->host.hc[hc_num].xfer_len);
+    }
+  }
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_HC_Halt : Halt channel
+* @param  pdev : Selected device
+* @param  hc_num : channel number
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_HNPTXSTS_TypeDef            nptxsts;
+  USB_OTG_HPTXSTS_TypeDef             hptxsts;
+  USB_OTG_HCCHAR_TypeDef              hcchar;
+  
+  nptxsts.d32 = 0;
+  hptxsts.d32 = 0;
+  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
+  hcchar.b.chen = 1;
+  hcchar.b.chdis = 1;
+  
+  /* Check for space in the request queue to issue the halt. */
+  if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK)
+  {
+    nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
+    if (nptxsts.b.nptxqspcavail == 0)
+    {
+      hcchar.b.chen = 0;
+    }
+  }
+  else
+  {
+    hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
+    if (hptxsts.b.ptxqspcavail == 0)
+    {
+      hcchar.b.chen = 0;
+    }
+  }
+  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
+  return status;
+}
+
+/**
+* @brief  Issue a ping token
+* @param  None
+* @retval : None
+*/
+USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
+{
+  USB_OTG_STS               status = USB_OTG_OK;
+  USB_OTG_HCCHAR_TypeDef    hcchar;
+  USB_OTG_HCTSIZn_TypeDef   hctsiz;  
+ 
+  hctsiz.d32 = 0;
+  hctsiz.b.dopng = 1;
+  hctsiz.b.pktcnt = 1;
+  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32);
+  
+  hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR);
+  hcchar.b.chen = 1;
+  hcchar.b.chdis = 0;
+  USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32);
+  return status;  
+}
+
+/**
+* @brief  Stop the device and clean up fifo's
+* @param  None
+* @retval : None
+*/
+void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_HCCHAR_TypeDef  hcchar;
+  uint32_t                i;
+  
+  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0);
+  USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT,      0xFFFFFFFF);
+  /* Flush out any leftover queued requests. */
+  
+  for (i = 0; i < pdev->cfg.host_channels; i++)
+  {
+    hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
+    hcchar.b.chen = 0;
+    hcchar.b.chdis = 1;
+    hcchar.b.epdir = 0;
+    USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32);
+  }
+  
+  /* Flush the FIFO */
+  USB_OTG_FlushRxFifo(pdev);
+  USB_OTG_FlushTxFifo(pdev ,  0x10 );  
+}
+#endif
+#ifdef USE_DEVICE_MODE
+/*         PCD Core Layer       */
+
+/**
+* @brief  USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register 
+*         depending the PHY type and the enumeration speed of the device.
+* @param  pdev : Selected device
+* @retval : None
+*/
+void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed)
+{
+  USB_OTG_DCFG_TypeDef   dcfg;
+  
+  dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG);
+  dcfg.b.devspd = speed;
+  USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32);
+}
+
+
+/**
+* @brief  USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers 
+*         for device mode
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_STS             status       = USB_OTG_OK;
+  USB_OTG_DEPCTL_TypeDef  depctl;
+  uint32_t i;
+  USB_OTG_DCFG_TypeDef    dcfg;
+  USB_OTG_FSIZ_TypeDef    nptxfifosize;
+  USB_OTG_FSIZ_TypeDef    txfifosize;
+  USB_OTG_DIEPMSK_TypeDef msk;
+  USB_OTG_DTHRCTL_TypeDef dthrctl;  
+  
+  depctl.d32 = 0;
+  dcfg.d32 = 0;
+  nptxfifosize.d32 = 0;
+  txfifosize.d32 = 0;
+  msk.d32 = 0;
+  
+  /* Restart the Phy Clock */
+  USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
+  /* Device configuration register */
+  dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
+  dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80;
+  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 );
+  
+#ifdef USB_OTG_FS_CORE
+  if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID  )
+  {  
+    
+    /* Set Full speed phy */
+    USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL);
+    
+    /* set Rx FIFO size */
+    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
+    
+    /* EP0 TX*/
+    nptxfifosize.b.depth     = TX0_FIFO_FS_SIZE;
+    nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
+    
+    
+    /* EP1 TX*/
+    txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+    txfifosize.b.depth = TX1_FIFO_FS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
+    
+    
+    /* EP2 TX*/
+    txfifosize.b.startaddr += txfifosize.b.depth;
+    txfifosize.b.depth = TX2_FIFO_FS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
+    
+    
+    /* EP3 TX*/  
+    txfifosize.b.startaddr += txfifosize.b.depth;
+    txfifosize.b.depth = TX3_FIFO_FS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
+  }
+#endif
+#ifdef USB_OTG_HS_CORE
+  if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID  )
+  {
+    
+    /* Set High speed phy */
+    
+    if(pdev->cfg.phy_itface  == USB_OTG_ULPI_PHY)
+    {
+       USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH);
+    }
+    else /* set High speed phy in Full speed mode */
+    {
+      USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL);
+    }
+    
+    /* set Rx FIFO size */
+    USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
+    
+    /* EP0 TX*/
+    nptxfifosize.b.depth     = TX0_FIFO_HS_SIZE;
+    nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 );
+    
+    
+    /* EP1 TX*/
+    txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+    txfifosize.b.depth = TX1_FIFO_HS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 );
+    
+    
+    /* EP2 TX*/
+    txfifosize.b.startaddr += txfifosize.b.depth;
+    txfifosize.b.depth = TX2_FIFO_HS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 );
+    
+    
+    /* EP3 TX*/  
+    txfifosize.b.startaddr += txfifosize.b.depth;
+    txfifosize.b.depth = TX3_FIFO_HS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 );
+    
+    /* EP4 TX*/
+    txfifosize.b.startaddr += txfifosize.b.depth;
+    txfifosize.b.depth = TX4_FIFO_HS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 );
+    
+    
+    /* EP5 TX*/  
+    txfifosize.b.startaddr += txfifosize.b.depth;
+    txfifosize.b.depth = TX5_FIFO_HS_SIZE;
+    USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 );
+  }
+#endif  
+  /* Flush the FIFOs */
+  USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */
+  USB_OTG_FlushRxFifo(pdev);
+  /* Clear all pending Device Interrupts */
+  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
+  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
+  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
+  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
+  
+  for (i = 0; i < pdev->cfg.dev_endpoints; i++)
+  {
+    depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL);
+    if (depctl.b.epena)
+    {
+      depctl.d32 = 0;
+      depctl.b.epdis = 1;
+      depctl.b.snak = 1;
+    }
+    else
+    {
+      depctl.d32 = 0;
+    }
+    USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32);
+    USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0);
+    USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
+  }
+  for (i = 0; i <  pdev->cfg.dev_endpoints; i++)
+  {
+    USB_OTG_DEPCTL_TypeDef  depctl;
+    depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL);
+    if (depctl.b.epena)
+    {
+      depctl.d32 = 0;
+      depctl.b.epdis = 1;
+      depctl.b.snak = 1;
+    }
+    else
+    {
+      depctl.d32 = 0;
+    }
+    USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32);
+    USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0);
+    USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
+  }
+  msk.d32 = 0;
+  msk.b.txfifoundrn = 1;
+  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32);
+  
+  if (pdev->cfg.dma_enable == 1)
+  {
+    dthrctl.d32 = 0;
+    dthrctl.b.non_iso_thr_en = 1;
+    dthrctl.b.iso_thr_en = 1;
+    dthrctl.b.tx_thr_len = 64;
+    dthrctl.b.rx_thr_en = 1;
+    dthrctl.b.rx_thr_len = 64;
+    USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32);  
+  }
+  USB_OTG_EnableDevInt(pdev);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_EnableDevInt : Enables the Device mode interrupts
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_GINTMSK_TypeDef  intmsk;
+  
+  intmsk.d32 = 0;
+  
+  /* Disable all interrupts. */
+  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0);
+  /* Clear any pending interrupts */
+  USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF);
+  /* Enable the common interrupts */
+  USB_OTG_EnableCommonInt(pdev);
+  
+  if (pdev->cfg.dma_enable == 0)
+  {
+    intmsk.b.rxstsqlvl = 1;
+  }
+  
+  /* Enable interrupts matching to the Device mode ONLY */
+  intmsk.b.usbsuspend = 1;
+  intmsk.b.usbreset   = 1;
+  intmsk.b.enumdone   = 1;
+  intmsk.b.inepintr   = 1;
+  intmsk.b.outepintr  = 1;
+  intmsk.b.sofintr    = 1; 
+
+  intmsk.b.incomplisoin    = 1; 
+  intmsk.b.incomplisoout    = 1;   
+#ifdef VBUS_SENSING_ENABLED
+  intmsk.b.sessreqintr    = 1; 
+  intmsk.b.otgintr    = 1;    
+#endif  
+  USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_GetDeviceSpeed
+*         Get the device speed from the device status register
+* @param  None
+* @retval status
+*/
+enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_DSTS_TypeDef  dsts;
+  enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN;
+  
+  
+  dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
+  
+  switch (dsts.b.enumspd)
+  {
+  case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
+    speed = USB_SPEED_HIGH;
+    break;
+  case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
+  case DSTS_ENUMSPD_FS_PHY_48MHZ:
+    speed = USB_SPEED_FULL;
+    break;
+    
+  case DSTS_ENUMSPD_LS_PHY_6MHZ:
+    speed = USB_SPEED_LOW;
+    break;
+  }
+  
+  return speed;
+}
+/**
+* @brief  enables EP0 OUT to receive SETUP packets and configures EP0
+*   for transmitting packets
+* @param  None
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS  USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_STS             status = USB_OTG_OK;
+  USB_OTG_DSTS_TypeDef    dsts;
+  USB_OTG_DEPCTL_TypeDef  diepctl;
+  USB_OTG_DCTL_TypeDef    dctl;
+  
+  dctl.d32 = 0;
+  /* Read the Device Status and Endpoint 0 Control registers */
+  dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
+  diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL);
+  /* Set the MPS of the IN EP based on the enumeration speed */
+  switch (dsts.b.enumspd)
+  {
+  case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
+  case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
+  case DSTS_ENUMSPD_FS_PHY_48MHZ:
+    diepctl.b.mps = DEP0CTL_MPS_64;
+    break;
+  case DSTS_ENUMSPD_LS_PHY_6MHZ:
+    diepctl.b.mps = DEP0CTL_MPS_8;
+    break;
+  }
+  USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32);
+  dctl.b.cgnpinnak = 1;
+  USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_EPActivate : Activates an EP
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_DEPCTL_TypeDef  depctl;
+  USB_OTG_DAINT_TypeDef  daintmsk;
+  __IO uint32_t *addr;
+  
+  
+  depctl.d32 = 0;
+  daintmsk.d32 = 0;
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1)
+  {
+    addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
+    daintmsk.ep.in = 1 << ep->num;
+  }
+  else
+  {
+    addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
+    daintmsk.ep.out = 1 << ep->num;
+  }
+  /* If the EP is already active don't change the EP Control
+  * register. */
+  depctl.d32 = USB_OTG_READ_REG32(addr);
+  if (!depctl.b.usbactep)
+  {
+    depctl.b.mps    = ep->maxpacket;
+    depctl.b.eptype = ep->type;
+    depctl.b.txfnum = ep->tx_fifo_num;
+    depctl.b.setd0pid = 1;
+    depctl.b.usbactep = 1;
+    USB_OTG_WRITE_REG32(addr, depctl.d32);
+  }
+  /* Enable the Interrupt for this EP */
+#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
+  if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
+  {
+    USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32);
+  }
+  else
+#endif   
+    USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_EPDeactivate : Deactivates an EP
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_DEPCTL_TypeDef  depctl;
+  USB_OTG_DAINT_TypeDef  daintmsk;
+  __IO uint32_t *addr;
+  
+  depctl.d32 = 0;
+  daintmsk.d32 = 0;  
+  /* Read DEPCTLn register */
+  if (ep->is_in == 1)
+  {
+    addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL;
+    daintmsk.ep.in = 1 << ep->num;
+  }
+  else
+  {
+    addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL;
+    daintmsk.ep.out = 1 << ep->num;
+  }
+  depctl.b.usbactep = 0;
+  USB_OTG_WRITE_REG32(addr, depctl.d32);
+  /* Disable the Interrupt for this EP */
+  
+#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
+  if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID))
+  {
+    USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0);
+  }
+  else
+#endif    
+    USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and 
+*         starts the xfer
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_DEPCTL_TypeDef     depctl;
+  USB_OTG_DEPXFRSIZ_TypeDef  deptsiz;
+  USB_OTG_DSTS_TypeDef       dsts;    
+  uint32_t fifoemptymsk = 0;  
+  
+  depctl.d32 = 0;
+  deptsiz.d32 = 0;
+  /* IN endpoint */
+  if (ep->is_in == 1)
+  {
+    depctl.d32  = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL));
+    deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ));
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0)
+    {
+      deptsiz.b.xfersize = 0;
+      deptsiz.b.pktcnt = 1;
+    }
+    else
+    {
+      /* Program the transfer size and packet count
+      * as follows: xfersize = N * maxpacket +
+      * short_packet pktcnt = N + (short_packet
+      * exist ? 1 : 0)
+      */
+      deptsiz.b.xfersize = ep->xfer_len;
+      deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+
+      if (ep->type == EP_TYPE_ISOC)
+      {
+        deptsiz.b.mc = 1;
+      }       
+    }
+    USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32);
+    
+    if (pdev->cfg.dma_enable == 1)
+    {
+      USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr);
+    }
+    else
+    {
+      if (ep->type != EP_TYPE_ISOC)
+      {
+        /* Enable the Tx FIFO Empty Interrupt for this EP */
+        if (ep->xfer_len > 0)
+        {
+          fifoemptymsk = 1 << ep->num;
+          USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
+        }
+      }
+    }
+    
+    
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
+      
+      if (((dsts.b.soffn)&0x1) == 0)
+      {
+        depctl.b.setd1pid = 1;
+      }
+      else
+      {
+        depctl.b.setd0pid = 1;
+      }
+    } 
+    
+    /* EP enable, IN data in FIFO */
+    depctl.b.cnak = 1;
+    depctl.b.epena = 1;
+    USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32);
+
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len);   
+    }    
+  }
+  else
+  {
+    /* OUT endpoint */
+    depctl.d32  = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL));
+    deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ));
+    /* Program the transfer size and packet count as follows:
+    * pktcnt = N
+    * xfersize = N * maxpacket
+    */
+    if (ep->xfer_len == 0)
+    {
+      deptsiz.b.xfersize = ep->maxpacket;
+      deptsiz.b.pktcnt = 1;
+    }
+    else
+    {
+      deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
+      deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
+    }
+    USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
+    
+    if (pdev->cfg.dma_enable == 1)
+    {
+      USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr);
+    }
+    
+    if (ep->type == EP_TYPE_ISOC)
+    {
+      if (ep->even_odd_frame)
+      {
+        depctl.b.setd1pid = 1;
+      }
+      else
+      {
+        depctl.b.setd0pid = 1;
+      }
+    }
+    /* EP enable */
+    depctl.b.cnak = 1;
+    depctl.b.epena = 1;
+    USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32);
+  }
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and 
+*         starts the xfer
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
+{
+  USB_OTG_STS                 status = USB_OTG_OK;
+  USB_OTG_DEPCTL_TypeDef      depctl;
+  USB_OTG_DEP0XFRSIZ_TypeDef  deptsiz;
+  USB_OTG_INEPREGS          *in_regs;
+  uint32_t fifoemptymsk = 0;
+  
+  depctl.d32   = 0;
+  deptsiz.d32  = 0;
+  /* IN endpoint */
+  if (ep->is_in == 1)
+  {
+    in_regs = pdev->regs.INEP_REGS[0];
+    depctl.d32  = USB_OTG_READ_REG32(&in_regs->DIEPCTL);
+    deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ);
+    /* Zero Length Packet? */
+    if (ep->xfer_len == 0)
+    {
+      deptsiz.b.xfersize = 0;
+      deptsiz.b.pktcnt = 1;
+      
+    }
+    else
+    {
+      if (ep->xfer_len > ep->maxpacket)
+      {
+        ep->xfer_len = ep->maxpacket;
+        deptsiz.b.xfersize = ep->maxpacket;
+      }
+      else
+      {
+        deptsiz.b.xfersize = ep->xfer_len;
+      }
+      deptsiz.b.pktcnt = 1;
+    }
+    USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32);
+    
+    if (pdev->cfg.dma_enable == 1)
+    {
+      USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr);  
+    }
+    
+    /* EP enable, IN data in FIFO */
+    depctl.b.cnak = 1;
+    depctl.b.epena = 1;
+    USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32);
+    
+    
+    
+    if (pdev->cfg.dma_enable == 0)
+    {
+      /* Enable the Tx FIFO Empty Interrupt for this EP */
+      if (ep->xfer_len > 0)
+      {
+        {
+          fifoemptymsk |= 1 << ep->num;
+          USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk);
+        }
+      }
+    }
+  }
+  else
+  {
+    /* OUT endpoint */
+    depctl.d32  = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
+    deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ);
+    /* Program the transfer size and packet count as follows:
+    * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
+    * pktcnt = N           */
+    if (ep->xfer_len == 0)
+    {
+      deptsiz.b.xfersize = ep->maxpacket;
+      deptsiz.b.pktcnt = 1;
+    }
+    else
+    {
+      ep->xfer_len = ep->maxpacket;
+      deptsiz.b.xfersize = ep->maxpacket;
+      deptsiz.b.pktcnt = 1;
+    }
+    USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32);
+    if (pdev->cfg.dma_enable == 1)
+    {
+      USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr);
+    }
+    /* EP enable */
+    depctl.b.cnak = 1;
+    depctl.b.epena = 1;
+    USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32);
+    
+  }
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_EPSetStall : Set the EP STALL
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_DEPCTL_TypeDef  depctl;
+  __IO uint32_t *depctl_addr;
+  
+  depctl.d32 = 0;
+  if (ep->is_in == 1)
+  {
+    depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
+    depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
+    /* set the disable and stall bits */
+    if (depctl.b.epena)
+    {
+      depctl.b.epdis = 1;
+    }
+    depctl.b.stall = 1;
+    USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
+  }
+  else
+  {
+    depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
+    depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
+    /* set the stall bit */
+    depctl.b.stall = 1;
+    USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
+  }
+  return status;
+}
+
+
+/**
+* @brief  Clear the EP STALL
+* @param  pdev : Selected device
+* @retval USB_OTG_STS : status
+*/
+USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep)
+{
+  USB_OTG_STS status = USB_OTG_OK;
+  USB_OTG_DEPCTL_TypeDef  depctl;
+  __IO uint32_t *depctl_addr;
+  
+  depctl.d32 = 0;
+  
+  if (ep->is_in == 1)
+  {
+    depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
+  }
+  else
+  {
+    depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
+  }
+  depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
+  /* clear the stall bits */
+  depctl.b.stall = 0;
+  if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
+  {
+    depctl.b.setd0pid = 1; /* DATA0 */
+  }
+  USB_OTG_WRITE_REG32(depctl_addr, depctl.d32);
+  return status;
+}
+
+
+/**
+* @brief  USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits
+* @param  pdev : Selected device
+* @retval OUT endpoint interrupt bits
+*/
+uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev)
+{
+  uint32_t v;
+  v  = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
+  v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
+  return ((v & 0xffff0000) >> 16);
+}
+
+
+/**
+* @brief  USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register
+* @param  pdev : Selected device
+* @param  ep : end point number
+* @retval Device OUT EP Interrupt register
+*/
+uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
+{
+  uint32_t v;
+  v  = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT);
+  v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK);
+  return v;
+}
+
+
+/**
+* @brief  USB_OTG_ReadDevAllInEPItr : Get int status register
+* @param  pdev : Selected device
+* @retval int status register
+*/
+uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev)
+{
+  uint32_t v;
+  v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT);
+  v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK);
+  return (v & 0xffff);
+}
+
+/**
+* @brief  configures EPO to receive SETUP packets
+* @param  None
+* @retval : None
+*/
+void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev)
+{
+  USB_OTG_DEP0XFRSIZ_TypeDef  doeptsize0;
+  doeptsize0.d32 = 0;
+  doeptsize0.b.supcnt = 3;
+  doeptsize0.b.pktcnt = 1;
+  doeptsize0.b.xfersize = 8 * 3;
+  USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 );
+  
+  if (pdev->cfg.dma_enable == 1)
+  {
+    USB_OTG_DEPCTL_TypeDef  doepctl;
+    doepctl.d32 = 0;
+    USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, 
+                        (uint32_t)&pdev->dev.setup_packet);
+    
+    /* EP enable */
+    doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL);
+    doepctl.b.epena = 1;
+    doepctl.d32 = 0x80008000;
+    USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32);
+  }
+}
+
+/**
+* @brief  USB_OTG_RemoteWakeup : active remote wakeup signalling
+* @param  None
+* @retval : None
+*/
+void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev)
+{
+  
+  USB_OTG_DCTL_TypeDef     dctl;
+  USB_OTG_DSTS_TypeDef     dsts;
+  USB_OTG_PCGCCTL_TypeDef  power;  
+  
+  if (pdev->dev.DevRemoteWakeup) 
+  {
+    dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
+    if(dsts.b.suspsts == 1)
+    {
+      if(pdev->cfg.low_power)
+      {
+        /* un-gate USB Core clock */
+        power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
+        power.b.gatehclk = 0;
+        power.b.stoppclk = 0;
+        USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
+      }   
+      /* active Remote wakeup signaling */
+      dctl.d32 = 0;
+      dctl.b.rmtwkupsig = 1;
+      USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32);
+      USB_OTG_BSP_mDelay(5);
+      USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
+    }
+  }
+}
+
+
+/**
+* @brief  USB_OTG_UngateClock : active USB Core clock
+* @param  None
+* @retval : None
+*/
+void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev)
+{
+  if(pdev->cfg.low_power)
+  {
+    
+    USB_OTG_DSTS_TypeDef     dsts;
+    USB_OTG_PCGCCTL_TypeDef  power; 
+    
+    dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
+    
+    if(dsts.b.suspsts == 1)
+    {
+      /* un-gate USB Core clock */
+      power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
+      power.b.gatehclk = 0;
+      power.b.stoppclk = 0;
+      USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
+      
+    }
+  }
+}
+
+/**
+* @brief  Stop the device and clean up fifo's
+* @param  None
+* @retval : None
+*/
+void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev)
+{
+  uint32_t i;
+  
+  pdev->dev.device_status = 1;
+    
+  for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
+  {
+    USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
+    USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
+  }
+
+  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 );
+  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 );
+  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 );
+  USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );  
+  
+  /* Flush the FIFO */
+  USB_OTG_FlushRxFifo(pdev);
+  USB_OTG_FlushTxFifo(pdev ,  0x10 );  
+}
+
+/**
+* @brief  returns the EP Status
+* @param  pdev : Selected device
+*         ep : endpoint structure
+* @retval : EP status
+*/
+
+uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep)
+{
+  USB_OTG_DEPCTL_TypeDef  depctl;
+  __IO uint32_t *depctl_addr;
+  uint32_t Status = 0;  
+  
+  depctl.d32 = 0;
+  if (ep->is_in == 1)
+  {
+    depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
+    depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
+    
+    if (depctl.b.stall == 1)  
+      Status = USB_OTG_EP_TX_STALL;
+    else if (depctl.b.naksts == 1)
+      Status = USB_OTG_EP_TX_NAK;
+    else 
+      Status = USB_OTG_EP_TX_VALID;     
+
+  }
+  else
+  {
+    depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
+    depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
+    if (depctl.b.stall == 1)  
+      Status = USB_OTG_EP_RX_STALL;
+    else if (depctl.b.naksts == 1)
+      Status = USB_OTG_EP_RX_NAK;
+    else 
+      Status = USB_OTG_EP_RX_VALID; 
+  } 
+  
+  /* Return the current status */
+  return Status;
+}
+
+/**
+* @brief  Set the EP Status
+* @param  pdev : Selected device
+*         Status : new Status
+*         ep : EP structure
+* @retval : None
+*/
+void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status)
+{
+  USB_OTG_DEPCTL_TypeDef  depctl;
+  __IO uint32_t *depctl_addr;
+  
+  depctl.d32 = 0;
+
+  /* Process for IN endpoint */
+  if (ep->is_in == 1)
+  {
+    depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL);
+    depctl.d32 = USB_OTG_READ_REG32(depctl_addr);
+    
+    if (Status == USB_OTG_EP_TX_STALL)  
+    {
+      USB_OTG_EPSetStall(pdev, ep); return;
+    }
+    else if (Status == USB_OTG_EP_TX_NAK)
+      depctl.b.snak = 1;
+    else if (Status == USB_OTG_EP_TX_VALID)
+    {
+      if (depctl.b.stall == 1)
+      {  
+        ep->even_odd_frame = 0;
+        USB_OTG_EPClearStall(pdev, ep);
+        return;
+      }      
+      depctl.b.cnak = 1;
+      depctl.b.usbactep = 1; 
+      depctl.b.epena = 1;
+    }
+    else if (Status == USB_OTG_EP_TX_DIS)
+      depctl.b.usbactep = 0;
+  } 
+  else /* Process for OUT endpoint */
+  {
+    depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL);
+    depctl.d32 = USB_OTG_READ_REG32(depctl_addr);    
+    
+    if (Status == USB_OTG_EP_RX_STALL)  {
+      depctl.b.stall = 1;
+    }
+    else if (Status == USB_OTG_EP_RX_NAK)
+      depctl.b.snak = 1;
+    else if (Status == USB_OTG_EP_RX_VALID)
+    {
+      if (depctl.b.stall == 1)
+      {  
+        ep->even_odd_frame = 0;
+        USB_OTG_EPClearStall(pdev, ep);
+        return;
+      }  
+      depctl.b.cnak = 1;
+      depctl.b.usbactep = 1;    
+      depctl.b.epena = 1;
+    }
+    else if (Status == USB_OTG_EP_RX_DIS)
+    {
+      depctl.b.usbactep = 0;    
+    }
+  }
+
+  USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); 
+}
+
+#endif
+/**
+* @}
+*/ 
+
+/**
+* @}
+*/ 
+
+/**
+* @}
+*/
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/usb_core.h b/exampleF4/Projects/discovery_demo/usb_core.h
new file mode 100644
index 0000000..82a09e1
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/usb_core.h
@@ -0,0 +1,408 @@
+/**
+  ******************************************************************************
+  * @file    usb_core.h
+  * @author  MCD Application Team
+  * @version V2.0.0
+  * @date    22-July-2011
+  * @brief   Header of the Core Layer
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_CORE_H__
+#define __USB_CORE_H__
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_conf.h"
+#include "usb_regs.h"
+#include "usb_defines.h"
+
+
+/** @addtogroup USB_OTG_DRIVER
+  * @{
+  */
+  
+/** @defgroup USB_CORE
+  * @brief usb otg driver core layer
+  * @{
+  */ 
+
+
+/** @defgroup USB_CORE_Exported_Defines
+  * @{
+  */ 
+
+#define USB_OTG_EP0_IDLE                          0
+#define USB_OTG_EP0_SETUP                         1
+#define USB_OTG_EP0_DATA_IN                       2
+#define USB_OTG_EP0_DATA_OUT                      3
+#define USB_OTG_EP0_STATUS_IN                     4
+#define USB_OTG_EP0_STATUS_OUT                    5
+#define USB_OTG_EP0_STALL                         6
+
+#define USB_OTG_EP_TX_DIS       0x0000
+#define USB_OTG_EP_TX_STALL     0x0010
+#define USB_OTG_EP_TX_NAK       0x0020
+#define USB_OTG_EP_TX_VALID     0x0030
+ 
+#define USB_OTG_EP_RX_DIS       0x0000
+#define USB_OTG_EP_RX_STALL     0x1000
+#define USB_OTG_EP_RX_NAK       0x2000
+#define USB_OTG_EP_RX_VALID     0x3000
+/**
+  * @}
+  */ 
+#define   MAX_DATA_LENGTH                        0xFF
+
+/** @defgroup USB_CORE_Exported_Types
+  * @{
+  */ 
+
+
+typedef enum {
+  USB_OTG_OK = 0,
+  USB_OTG_FAIL
+}USB_OTG_STS;
+
+typedef enum {
+  HC_IDLE = 0,
+  HC_XFRC,
+  HC_HALTED,
+  HC_NAK,
+  HC_NYET,
+  HC_STALL,
+  HC_XACTERR,  
+  HC_BBLERR,   
+  HC_DATATGLERR,  
+}HC_STATUS;
+
+typedef enum {
+  URB_IDLE = 0,
+  URB_DONE,
+  URB_NOTREADY,
+  URB_ERROR,
+  URB_STALL
+}URB_STATE;
+
+typedef enum {
+  CTRL_START = 0,
+  CTRL_XFRC,
+  CTRL_HALTED,
+  CTRL_NAK,
+  CTRL_STALL,
+  CTRL_XACTERR,  
+  CTRL_BBLERR,   
+  CTRL_DATATGLERR,  
+  CTRL_FAIL
+}CTRL_STATUS;
+
+
+typedef struct USB_OTG_hc
+{
+  uint8_t       dev_addr ;
+  uint8_t       ep_num;
+  uint8_t       ep_is_in;
+  uint8_t       speed;
+  uint8_t       do_ping;  
+  uint8_t       ep_type;
+  uint16_t      max_packet;
+  uint8_t       data_pid;
+  uint8_t       *xfer_buff;
+  uint32_t      xfer_len;
+  uint32_t      xfer_count;  
+  uint8_t       toggle_in;
+  uint8_t       toggle_out;
+  uint32_t       dma_addr;  
+}
+USB_OTG_HC , *PUSB_OTG_HC;
+
+typedef struct USB_OTG_ep
+{
+  uint8_t        num;
+  uint8_t        is_in;
+  uint8_t        is_stall;  
+  uint8_t        type;
+  uint8_t        data_pid_start;
+  uint8_t        even_odd_frame;
+  uint16_t       tx_fifo_num;
+  uint32_t       maxpacket;
+  /* transaction level variables*/
+  uint8_t        *xfer_buff;
+  uint32_t       dma_addr;  
+  uint32_t       xfer_len;
+  uint32_t       xfer_count;
+  /* Transfer level variables*/  
+  uint32_t       rem_data_len;
+  uint32_t       total_data_len;
+  uint32_t       ctl_data_len;  
+
+}
+
+USB_OTG_EP , *PUSB_OTG_EP;
+
+
+
+typedef struct USB_OTG_core_cfg
+{
+  uint8_t       host_channels;
+  uint8_t       dev_endpoints;
+  uint8_t       speed;
+  uint8_t       dma_enable;
+  uint16_t      mps;
+  uint16_t      TotalFifoSize;
+  uint8_t       phy_itface;
+  uint8_t       Sof_output;
+  uint8_t       low_power;
+  uint8_t       coreID;
+ 
+}
+USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS;
+
+
+
+typedef  struct  usb_setup_req {
+    
+    uint8_t   bmRequest;                      
+    uint8_t   bRequest;                           
+    uint16_t  wValue;                             
+    uint16_t  wIndex;                             
+    uint16_t  wLength;                            
+} USB_SETUP_REQ;
+
+typedef struct _Device_TypeDef
+{
+  uint8_t  *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length);  
+  uint8_t  *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length); 
+  uint8_t  *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length);  
+  uint8_t  *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length);  
+  uint8_t  *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length);  
+  uint8_t  *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length);  
+  uint8_t  *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length);   
+} USBD_DEVICE, *pUSBD_DEVICE;
+
+typedef struct USB_OTG_hPort
+{
+  void (*Disconnect) (void *phost);
+  void (*Connect) (void *phost); 
+  uint8_t ConnStatus;
+  uint8_t DisconnStatus;
+  uint8_t ConnHandled;
+  uint8_t DisconnHandled;
+} USB_OTG_hPort_TypeDef;
+
+typedef struct _Device_cb
+{
+  uint8_t  (*Init)         (void *pdev , uint8_t cfgidx);
+  uint8_t  (*DeInit)       (void *pdev , uint8_t cfgidx);
+ /* Control Endpoints*/
+  uint8_t  (*Setup)        (void *pdev , USB_SETUP_REQ  *req);  
+  uint8_t  (*EP0_TxSent)   (void *pdev );    
+  uint8_t  (*EP0_RxReady)  (void *pdev );  
+  /* Class Specific Endpoints*/
+  uint8_t  (*DataIn)       (void *pdev , uint8_t epnum);   
+  uint8_t  (*DataOut)      (void *pdev , uint8_t epnum); 
+  uint8_t  (*SOF)          (void *pdev); 
+  uint8_t  (*IsoINIncomplete)  (void *pdev); 
+  uint8_t  (*IsoOUTIncomplete)  (void *pdev);   
+
+  uint8_t  *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length); 
+#ifdef USB_OTG_HS_CORE 
+  uint8_t  *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length);   
+#endif
+
+#ifdef USB_SUPPORT_USER_STRING_DESC 
+  uint8_t  *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index,  uint16_t *length);   
+#endif  
+  
+} USBD_Class_cb_TypeDef;
+
+
+
+typedef struct _USBD_USR_PROP
+{
+  void (*Init)(void);   
+  void (*DeviceReset)(uint8_t speed); 
+  void (*DeviceConfigured)(void);
+  void (*DeviceSuspended)(void);
+  void (*DeviceResumed)(void);  
+  
+  void (*DeviceConnected)(void);  
+  void (*DeviceDisconnected)(void);    
+  
+}
+USBD_Usr_cb_TypeDef;
+
+typedef struct _DCD
+{
+  uint8_t        device_config;
+  uint8_t        device_state;
+  uint8_t        device_status;
+  uint8_t        device_address;
+  uint32_t       DevRemoteWakeup;
+  USB_OTG_EP     in_ep   [USB_OTG_MAX_TX_FIFOS];
+  USB_OTG_EP     out_ep  [USB_OTG_MAX_TX_FIFOS];
+  uint8_t        setup_packet [8*3];
+  USBD_Class_cb_TypeDef         *class_cb;
+  USBD_Usr_cb_TypeDef           *usr_cb;
+  USBD_DEVICE                   *usr_device;  
+  uint8_t        *pConfig_descriptor;
+ }
+DCD_DEV , *DCD_PDEV;
+
+
+typedef struct _HCD
+{
+  uint8_t                  Rx_Buffer [MAX_DATA_LENGTH];  
+  __IO uint32_t            ConnSts;
+  __IO uint32_t            ErrCnt[USB_OTG_MAX_TX_FIFOS];
+  __IO uint32_t            XferCnt[USB_OTG_MAX_TX_FIFOS];
+  __IO HC_STATUS           HC_Status[USB_OTG_MAX_TX_FIFOS];  
+  __IO URB_STATE           URB_State[USB_OTG_MAX_TX_FIFOS];
+  USB_OTG_HC               hc [USB_OTG_MAX_TX_FIFOS];
+  uint16_t                 channel [USB_OTG_MAX_TX_FIFOS];
+  USB_OTG_hPort_TypeDef    *port_cb;  
+}
+HCD_DEV , *USB_OTG_USBH_PDEV;
+
+
+typedef struct _OTG
+{
+  uint8_t    OTG_State;
+  uint8_t    OTG_PrevState;  
+  uint8_t    OTG_Mode;    
+}
+OTG_DEV , *USB_OTG_USBO_PDEV;
+
+typedef struct USB_OTG_handle
+{
+  USB_OTG_CORE_CFGS    cfg;
+  USB_OTG_CORE_REGS    regs;
+#ifdef USE_DEVICE_MODE
+  DCD_DEV     dev;
+#endif
+#ifdef USE_HOST_MODE
+  HCD_DEV     host;
+#endif
+#ifdef USE_OTG_MODE
+  OTG_DEV     otg;
+#endif
+}
+USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE;
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USB_CORE_Exported_Macros
+  * @{
+  */ 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USB_CORE_Exported_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup USB_CORE_Exported_FunctionsPrototype
+  * @{
+  */ 
+
+
+USB_OTG_STS  USB_OTG_CoreInit        (USB_OTG_CORE_HANDLE *pdev);
+USB_OTG_STS  USB_OTG_SelectCore      (USB_OTG_CORE_HANDLE *pdev, 
+                                      USB_OTG_CORE_ID_TypeDef coreID);
+USB_OTG_STS  USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev);
+USB_OTG_STS  USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev);
+void*           USB_OTG_ReadPacket   (USB_OTG_CORE_HANDLE *pdev ,
+    uint8_t *dest,
+    uint16_t len);
+USB_OTG_STS  USB_OTG_WritePacket     (USB_OTG_CORE_HANDLE *pdev ,
+    uint8_t *src,
+    uint8_t ch_ep_num,
+    uint16_t len);
+USB_OTG_STS  USB_OTG_FlushTxFifo     (USB_OTG_CORE_HANDLE *pdev , uint32_t num);
+USB_OTG_STS  USB_OTG_FlushRxFifo     (USB_OTG_CORE_HANDLE *pdev);
+
+uint32_t     USB_OTG_ReadCoreItr     (USB_OTG_CORE_HANDLE *pdev);
+uint32_t     USB_OTG_ReadOtgItr      (USB_OTG_CORE_HANDLE *pdev);
+uint8_t      USB_OTG_IsHostMode      (USB_OTG_CORE_HANDLE *pdev);
+uint8_t      USB_OTG_IsDeviceMode    (USB_OTG_CORE_HANDLE *pdev);
+uint32_t     USB_OTG_GetMode         (USB_OTG_CORE_HANDLE *pdev);
+USB_OTG_STS  USB_OTG_PhyInit         (USB_OTG_CORE_HANDLE *pdev);
+USB_OTG_STS  USB_OTG_SetCurrentMode  (USB_OTG_CORE_HANDLE *pdev,
+    uint8_t mode);
+
+/*********************** HOST APIs ********************************************/
+#ifdef USE_HOST_MODE
+USB_OTG_STS  USB_OTG_CoreInitHost    (USB_OTG_CORE_HANDLE *pdev);
+USB_OTG_STS  USB_OTG_EnableHostInt   (USB_OTG_CORE_HANDLE *pdev);
+USB_OTG_STS  USB_OTG_HC_Init         (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
+USB_OTG_STS  USB_OTG_HC_Halt         (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
+USB_OTG_STS  USB_OTG_HC_StartXfer    (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
+USB_OTG_STS  USB_OTG_HC_DoPing       (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num);
+uint32_t     USB_OTG_ReadHostAllChannels_intr    (USB_OTG_CORE_HANDLE *pdev);
+uint32_t     USB_OTG_ResetPort       (USB_OTG_CORE_HANDLE *pdev);
+uint32_t     USB_OTG_ReadHPRT0       (USB_OTG_CORE_HANDLE *pdev);
+void         USB_OTG_DriveVbus       (USB_OTG_CORE_HANDLE *pdev, uint8_t state);
+void         USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq);
+uint8_t      USB_OTG_IsEvenFrame     (USB_OTG_CORE_HANDLE *pdev) ;
+void         USB_OTG_StopHost        (USB_OTG_CORE_HANDLE *pdev);
+#endif
+/********************* DEVICE APIs ********************************************/
+#ifdef USE_DEVICE_MODE
+USB_OTG_STS  USB_OTG_CoreInitDev         (USB_OTG_CORE_HANDLE *pdev);
+USB_OTG_STS  USB_OTG_EnableDevInt        (USB_OTG_CORE_HANDLE *pdev);
+uint32_t     USB_OTG_ReadDevAllInEPItr           (USB_OTG_CORE_HANDLE *pdev);
+enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev);
+USB_OTG_STS  USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev);
+USB_OTG_STS  USB_OTG_EPActivate  (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+USB_OTG_STS  USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+USB_OTG_STS  USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+USB_OTG_STS  USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+USB_OTG_STS  USB_OTG_EPSetStall          (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+USB_OTG_STS  USB_OTG_EPClearStall        (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
+uint32_t     USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev);
+uint32_t     USB_OTG_ReadDevOutEP_itr    (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
+uint32_t     USB_OTG_ReadDevAllInEPItr   (USB_OTG_CORE_HANDLE *pdev);
+void         USB_OTG_InitDevSpeed        (USB_OTG_CORE_HANDLE *pdev , uint8_t speed);
+uint8_t      USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev);
+void         USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev);
+void         USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev);
+void         USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev);
+void         USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev);
+void         USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status);
+uint32_t     USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep);
+#endif
+/**
+  * @}
+  */ 
+
+#endif  /* __USB_CORE_H__ */
+
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
diff --git a/exampleF4/Projects/discovery_demo/usbd_conf.h b/exampleF4/Projects/discovery_demo/usbd_conf.h
new file mode 100644
index 0000000..3ff02b6
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/usbd_conf.h
@@ -0,0 +1,93 @@
+/**
+  ******************************************************************************
+  * @file    usbd_conf.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   USB Device configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USBD_CONF__H__
+#define __USBD_CONF__H__
+
+/* Includes ------------------------------------------------------------------*/
+#include   "stm32f4_discovery.h"
+
+/** @defgroup USB_CONF_Exported_Defines
+  * @{
+  */ 
+
+
+#define USBD_CFG_MAX_NUM           1
+#define USBD_ITF_MAX_NUM           1
+
+#define USB_MAX_STR_DESC_SIZ       64 
+
+
+
+#define USBD_DYNAMIC_DESCRIPTOR_CHANGE_ENABLED 
+
+/** @defgroup USB_String_Descriptors
+  * @{
+  */ 
+
+
+/** @defgroup USB_HID_Class_Layer_Parameter
+  * @{
+  */ 
+#define HID_IN_EP                    0x81
+#define HID_OUT_EP                   0x01
+
+#define HID_IN_PACKET                4
+#define HID_OUT_PACKET               4
+
+/**
+  * @}
+  */ 
+/** @defgroup USB_CONF_Exported_Types
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USB_CONF_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup USB_CONF_Exported_Variables
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup USB_CONF_Exported_FunctionsPrototype
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+#endif //__USBD_CONF__H__
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
diff --git a/exampleF4/Projects/discovery_demo/usbd_desc.c b/exampleF4/Projects/discovery_demo/usbd_desc.c
new file mode 100644
index 0000000..ff9b670
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/usbd_desc.c
@@ -0,0 +1,313 @@
+/**
+  ******************************************************************************
+  * @file    usbd_desc.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   This file provides the USBD descriptors and string formating method.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_core.h"
+#include "usbd_desc.h"
+#include "usbd_req.h"
+#include "usbd_conf.h"
+#include "usb_regs.h"
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+
+
+/** @defgroup USBD_DESC 
+  * @brief USBD descriptors module
+  * @{
+  */ 
+
+/** @defgroup USBD_DESC_Private_TypesDefinitions
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_DESC_Private_Defines
+  * @{
+  */ 
+
+#define USBD_VID                     0x0483
+#define USBD_PID                     0x5710
+
+#define USBD_LANGID_STRING            0x409
+#define USBD_MANUFACTURER_STRING      "STMicroelectronics"
+
+#define USBD_PRODUCT_HS_STRING        "Joystick in HS mode"
+#define USBD_SERIALNUMBER_HS_STRING   "00000000011B"
+
+#define USBD_PRODUCT_FS_STRING        "Joystick in FS Mode"
+#define USBD_SERIALNUMBER_FS_STRING   "00000000011C"
+
+#define USBD_CONFIGURATION_HS_STRING  "HID Config"
+#define USBD_INTERFACE_HS_STRING      "HID Interface"
+
+#define USBD_CONFIGURATION_FS_STRING  "HID Config"
+#define USBD_INTERFACE_FS_STRING      "HID Interface"
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_DESC_Private_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_DESC_Private_Variables
+  * @{
+  */ 
+
+USBD_DEVICE USR_desc =
+{
+  USBD_USR_DeviceDescriptor,
+  USBD_USR_LangIDStrDescriptor, 
+  USBD_USR_ManufacturerStrDescriptor,
+  USBD_USR_ProductStrDescriptor,
+  USBD_USR_SerialStrDescriptor,
+  USBD_USR_ConfigStrDescriptor,
+  USBD_USR_InterfaceStrDescriptor,
+  
+};
+
+#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
+  #if defined ( __ICCARM__ ) /*!< IAR Compiler */
+    #pragma data_alignment=4   
+  #endif
+#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
+/* USB Standard Device Descriptor */
+__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] __ALIGN_END =
+  {
+    0x12,                       /*bLength */
+    USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/
+    0x00,                       /*bcdUSB */
+    0x02,
+    0x00,                       /*bDeviceClass*/
+    0x00,                       /*bDeviceSubClass*/
+    0x00,                       /*bDeviceProtocol*/
+    USB_OTG_MAX_EP0_SIZE,      /*bMaxPacketSize*/
+    LOBYTE(USBD_VID),           /*idVendor*/
+    HIBYTE(USBD_VID),           /*idVendor*/
+    LOBYTE(USBD_PID),           /*idVendor*/
+    HIBYTE(USBD_PID),           /*idVendor*/
+    0x00,                       /*bcdDevice rel. 2.00*/
+    0x02,
+    USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/
+    USBD_IDX_PRODUCT_STR,       /*Index of product string*/
+    USBD_IDX_SERIAL_STR,        /*Index of serial number string*/
+    USBD_CFG_MAX_NUM            /*bNumConfigurations*/
+  } ; /* USB_DeviceDescriptor */
+
+#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
+  #if defined ( __ICCARM__ ) /*!< IAR Compiler */
+    #pragma data_alignment=4   
+  #endif
+#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
+/* USB Standard Device Descriptor */
+__ALIGN_BEGIN uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
+{
+  USB_LEN_DEV_QUALIFIER_DESC,
+  USB_DESC_TYPE_DEVICE_QUALIFIER,
+  0x00,
+  0x02,
+  0x00,
+  0x00,
+  0x00,
+  0x40,
+  0x01,
+  0x00,
+};
+
+#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
+  #if defined ( __ICCARM__ ) /*!< IAR Compiler */
+    #pragma data_alignment=4   
+  #endif
+#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
+/* USB Standard Device Descriptor */
+__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] __ALIGN_END =
+{
+     USB_SIZ_STRING_LANGID,         
+     USB_DESC_TYPE_STRING,       
+     LOBYTE(USBD_LANGID_STRING),
+     HIBYTE(USBD_LANGID_STRING), 
+};
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_DESC_Private_FunctionPrototypes
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_DESC_Private_Functions
+  * @{
+  */ 
+
+/**
+* @brief  USBD_USR_DeviceDescriptor 
+*         return the device descriptor
+* @param  speed : current device speed
+* @param  length : pointer to data length variable
+* @retval pointer to descriptor buffer
+*/
+uint8_t *  USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length)
+{
+  *length = sizeof(USBD_DeviceDesc);
+  return USBD_DeviceDesc;
+}
+
+/**
+* @brief  USBD_USR_LangIDStrDescriptor 
+*         return the LangID string descriptor
+* @param  speed : current device speed
+* @param  length : pointer to data length variable
+* @retval pointer to descriptor buffer
+*/
+uint8_t *  USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length)
+{
+  *length =  sizeof(USBD_LangIDDesc);  
+  return USBD_LangIDDesc;
+}
+
+
+/**
+* @brief  USBD_USR_ProductStrDescriptor 
+*         return the product string descriptor
+* @param  speed : current device speed
+* @param  length : pointer to data length variable
+* @retval pointer to descriptor buffer
+*/
+uint8_t *  USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length)
+{
+ 
+  
+  if(speed == 0)
+  {   
+    USBD_GetString (USBD_PRODUCT_HS_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString (USBD_PRODUCT_FS_STRING, USBD_StrDesc, length);    
+  }
+  return USBD_StrDesc;
+}
+
+/**
+* @brief  USBD_USR_ManufacturerStrDescriptor 
+*         return the manufacturer string descriptor
+* @param  speed : current device speed
+* @param  length : pointer to data length variable
+* @retval pointer to descriptor buffer
+*/
+uint8_t *  USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length)
+{
+  USBD_GetString (USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
+  return USBD_StrDesc;
+}
+
+/**
+* @brief  USBD_USR_SerialStrDescriptor 
+*         return the serial number string descriptor
+* @param  speed : current device speed
+* @param  length : pointer to data length variable
+* @retval pointer to descriptor buffer
+*/
+uint8_t *  USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length)
+{
+  if(speed  == USB_OTG_SPEED_HIGH)
+  {    
+    USBD_GetString (USBD_SERIALNUMBER_HS_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString (USBD_SERIALNUMBER_FS_STRING, USBD_StrDesc, length);    
+  }
+  return USBD_StrDesc;
+}
+
+/**
+* @brief  USBD_USR_ConfigStrDescriptor 
+*         return the configuration string descriptor
+* @param  speed : current device speed
+* @param  length : pointer to data length variable
+* @retval pointer to descriptor buffer
+*/
+uint8_t *  USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length)
+{
+  if(speed  == USB_OTG_SPEED_HIGH)
+  {  
+    USBD_GetString (USBD_CONFIGURATION_HS_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString (USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length); 
+  }
+  return USBD_StrDesc;  
+}
+
+
+/**
+* @brief  USBD_USR_InterfaceStrDescriptor 
+*         return the interface string descriptor
+* @param  speed : current device speed
+* @param  length : pointer to data length variable
+* @retval pointer to descriptor buffer
+*/
+uint8_t *  USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length)
+{
+  if(speed == 0)
+  {
+    USBD_GetString (USBD_INTERFACE_HS_STRING, USBD_StrDesc, length);
+  }
+  else
+  {
+    USBD_GetString (USBD_INTERFACE_FS_STRING, USBD_StrDesc, length);
+  }
+  return USBD_StrDesc;  
+}
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
diff --git a/exampleF4/Projects/discovery_demo/usbd_desc.h b/exampleF4/Projects/discovery_demo/usbd_desc.h
new file mode 100644
index 0000000..ed999dc
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/usbd_desc.h
@@ -0,0 +1,114 @@
+/**
+  ******************************************************************************
+  * @file    usbd_desc.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   header file for the usbd_desc.c file
+  ******************************************************************************
+  * @attention 
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+
+#ifndef __USB_DESC_H
+#define __USB_DESC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_def.h"
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+  * @{
+  */
+  
+/** @defgroup USB_DESC
+  * @brief general defines for the usb device library file
+  * @{
+  */ 
+
+/** @defgroup USB_DESC_Exported_Defines
+  * @{
+  */
+#define USB_DEVICE_DESCRIPTOR_TYPE              0x01
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE       0x02
+#define USB_STRING_DESCRIPTOR_TYPE              0x03
+#define USB_INTERFACE_DESCRIPTOR_TYPE           0x04
+#define USB_ENDPOINT_DESCRIPTOR_TYPE            0x05
+#define USB_SIZ_DEVICE_DESC                     18
+#define USB_SIZ_STRING_LANGID                   4
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup USBD_DESC_Exported_TypesDefinitions
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+
+
+/** @defgroup USBD_DESC_Exported_Macros
+  * @{
+  */ 
+/**
+  * @}
+  */ 
+
+/** @defgroup USBD_DESC_Exported_Variables
+  * @{
+  */ 
+extern  uint8_t USBD_DeviceDesc  [USB_SIZ_DEVICE_DESC];
+extern  uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ];
+extern  uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC]; 
+extern  uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC];
+extern  uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID];
+extern  USBD_DEVICE USR_desc; 
+/**
+  * @}
+  */ 
+
+/** @defgroup USBD_DESC_Exported_FunctionsPrototype
+  * @{
+  */ 
+
+
+uint8_t *     USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length);
+uint8_t *     USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length);
+uint8_t *     USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length);
+uint8_t *     USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length);
+uint8_t *     USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length);
+uint8_t *     USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length);
+uint8_t *     USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length);
+
+#ifdef USB_SUPPORT_USER_STRING_DESC
+uint8_t *     USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length);  
+#endif /* USB_SUPPORT_USER_STRING_DESC */  
+  
+/**
+  * @}
+  */ 
+
+#endif /* __USBD_DESC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+* @}
+*/ 
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/exampleF4/Projects/discovery_demo/usbd_usr.c b/exampleF4/Projects/discovery_demo/usbd_usr.c
new file mode 100644
index 0000000..6ebd157
--- /dev/null
+++ b/exampleF4/Projects/discovery_demo/usbd_usr.c
@@ -0,0 +1,238 @@
+/**
+  ******************************************************************************
+  * @file    usbd_usr.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   This file includes the user application layer
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "usbd_usr.h"
+#include "usbd_ioreq.h"
+
+
+/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
+* @{
+*/
+
+/** @defgroup USBD_USR 
+* @brief    This file includes the user application layer
+* @{
+*/ 
+
+/** @defgroup USBD_USR_Private_TypesDefinitions
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup USBD_USR_Private_Defines
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup USBD_USR_Private_Macros
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup USBD_USR_Private_Variables
+* @{
+*/ 
+
+USBD_Usr_cb_TypeDef USR_cb =
+{
+  USBD_USR_Init,
+  USBD_USR_DeviceReset,
+  USBD_USR_DeviceConfigured,
+  USBD_USR_DeviceSuspended,
+  USBD_USR_DeviceResumed,
+  
+  USBD_USR_DeviceConnected,
+  USBD_USR_DeviceDisconnected,  
+  
+  
+};
+
+
+
+/**
+* @}
+*/
+
+/** @defgroup USBD_USR_Private_Constants
+* @{
+*/ 
+
+/**
+* @}
+*/
+
+
+
+/** @defgroup USBD_USR_Private_FunctionPrototypes
+* @{
+*/ 
+/**
+* @}
+*/ 
+
+
+/** @defgroup USBD_USR_Private_Functions
+* @{
+*/ 
+
+/**
+* @brief  USBD_USR_Init 
+*         Displays the message on LCD for host lib initialization
+* @param  None
+* @retval None
+*/
+void USBD_USR_Init(void)
+{   
+  /* Setup SysTick Timer for 40 msec interrupts 
+  This interrupt is used to probe the joystick */
+  if (SysTick_Config(SystemCoreClock / 24))
+  { 
+    /* Capture error */ 
+    while (1);
+  }
+}
+
+/**
+* @brief  USBD_USR_DeviceReset 
+*         Displays the message on LCD on device Reset Event
+* @param  speed : device speed
+* @retval None
+*/
+void USBD_USR_DeviceReset(uint8_t speed )
+{
+ switch (speed)
+ {
+   case USB_OTG_SPEED_HIGH: 
+     break;
+
+  case USB_OTG_SPEED_FULL: 
+     break;
+ default:
+     break;
+     
+ }
+}
+
+
+/**
+* @brief  USBD_USR_DeviceConfigured
+*         Displays the message on LCD on device configuration Event
+* @param  None
+* @retval Staus
+*/
+void USBD_USR_DeviceConfigured (void)
+{
+}
+
+
+/**
+* @brief  USBD_USR_DeviceConnected
+*         Displays the message on LCD on device connection Event
+* @param  None
+* @retval Staus
+*/
+void USBD_USR_DeviceConnected (void)
+{
+}
+
+
+/**
+* @brief  USBD_USR_DeviceDisonnected
+*         Displays the message on LCD on device disconnection Event
+* @param  None
+* @retval Staus
+*/
+void USBD_USR_DeviceDisconnected (void)
+{
+}
+
+/**
+* @brief  USBD_USR_DeviceSuspended 
+*         Displays the message on LCD on device suspend Event
+* @param  None
+* @retval None
+*/
+void USBD_USR_DeviceSuspended(void)
+{
+  /* Users can do their application actions here for the USB-Reset */
+}
+
+
+/**
+* @brief  USBD_USR_DeviceResumed 
+*         Displays the message on LCD on device resume Event
+* @param  None
+* @retval None
+*/
+void USBD_USR_DeviceResumed(void)
+{
+  /* Users can do their application actions here for the USB-Reset */
+}
+
+/**
+* @}
+*/ 
+
+/**
+* @}
+*/ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-- 
2.47.2