From 2ebb9d0c0255a7428511e28b770aba5b49d7dbd1 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 2 Aug 2012 20:04:56 -0700 Subject: [PATCH] Add pull-ups on the rotary switches Signed-off-by: Keith Packard --- packages/74x.fp | 24 ++++++ symbols/74x.sym | 58 ++++++++++++++ telefire.pcb | 126 +++++++++++++++++++++++------- telefire.sch | 202 ++++++++++++++++++++++++++++++++++++------------ 4 files changed, 333 insertions(+), 77 deletions(-) create mode 100644 packages/74x.fp create mode 100644 symbols/74x.sym diff --git a/packages/74x.fp b/packages/74x.fp new file mode 100644 index 0000000..1bfe4f1 --- /dev/null +++ b/packages/74x.fp @@ -0,0 +1,24 @@ +# author: Keith Packard +# email: keithp@keithp.com +# dist-license: GPL 2 +# use-license: unlimited +Element[0x0 "74x" "" "" 0 0 -10000 -10000 0 100 0x0] +( +# + Pad[ -5000 -2250 -5000 -4400 1400 900 2000 "1" "1" 0x100] + Pad[ -2500 -2250 -2500 -4400 1400 900 2000 "2" "2" 0x100] + Pad[ 0 -2250 0 -4400 1400 900 2000 "3" "3" 0x100] + Pad[ 2500 -2250 2500 -4400 1400 900 2000 "4" "4" 0x100] + Pad[ 5000 -2250 5000 -4400 1400 900 2000 "C" "C" 0x100] + + Pad[ -5000 2250 -5000 4400 1400 900 2000 "C" "C" 0x100] + Pad[ -2500 2250 -2500 4400 1400 900 2000 "9" "9" 0x100] + Pad[ 0 2250 0 4400 1400 900 2000 "8" "8" 0x100] + Pad[ 2500 2250 2500 4400 1400 900 2000 "7" "7" 0x100] + Pad[ 5000 2250 5000 4400 1400 900 2000 "6" "6" 0x100] + + ElementLine [ -6700 6050 6700 6050 1000 ] + ElementLine [ 6700 -6050 -6700 -6050 1000 ] + ElementLine [ 6700 6050 6700 -6050 1000 ] + ElementLine [ -6700 -6050 -6700 6050 1000 ] +) diff --git a/symbols/74x.sym b/symbols/74x.sym new file mode 100644 index 0000000..4cd10bf --- /dev/null +++ b/symbols/74x.sym @@ -0,0 +1,58 @@ +v 20110115 2 +L 600 200 500 0 3 0 0 0 -1 -1 +L 500 0 400 200 3 0 0 0 -1 -1 +L 400 200 300 0 3 0 0 0 -1 -1 +L 300 0 200 200 3 0 0 0 -1 -1 +T 300 400 5 10 0 0 0 0 1 +device=Bussed x8 Resistor Array +T 500 1300 5 10 0 0 0 0 1 +numslots=8 +T 500 1500 5 10 0 0 0 0 1 +slotdef=1:1,C +T 500 1700 5 10 0 0 0 0 1 +slotdef=2:2,C +T 500 1900 5 10 0 0 0 0 1 +slotdef=3:3,C +T 500 2100 5 10 0 0 0 0 1 +slotdef=4:4,C +T 500 2300 5 10 0 0 0 0 1 +slotdef=5:6,C +T 500 2500 5 10 0 0 0 0 1 +slotdef=6:7,C +T 500 2700 5 10 0 0 0 0 1 +slotdef=7:8,C +T 500 2900 5 10 0 0 0 0 1 +slotdef=8:9,C +L 600 200 700 0 3 0 0 0 -1 -1 +L 700 0 750 100 3 0 0 0 -1 -1 +P 0 100 152 100 1 0 0 +{ +T 50 150 5 8 1 1 0 0 1 +pinnumber=1 +T 50 150 5 8 0 0 0 0 1 +pinseq=1 +T 50 150 5 8 0 1 0 0 1 +pinlabel=1 +T 50 150 5 8 0 1 0 0 1 +pintype=pas +} +P 900 100 750 100 1 0 0 +{ +T 750 150 5 8 1 1 0 0 1 +pinnumber=C +T 750 150 5 8 0 0 0 0 1 +pinseq=2 +T 750 150 5 8 0 1 0 0 1 +pinlabel=C +T 750 150 5 8 0 1 0 0 1 +pintype=pas +} +L 201 200 150 100 3 0 0 0 -1 -1 +T 200 250 8 10 1 1 0 0 1 +refdes=R? +T 600 250 8 10 1 1 0 0 1 +value=? +T 0 0 8 10 0 1 0 0 1 +pins=2 +T 0 0 8 10 0 1 0 0 1 +class=DISCRETE diff --git a/telefire.pcb b/telefire.pcb index cbd4249..f90e169 100644 --- a/telefire.pcb +++ b/telefire.pcb @@ -6,11 +6,11 @@ FileVersion[20070407] PCB["TeleFire" 400000 450000] Grid[100.0 0 0 0] -Cursor[0 0 0.000000] +Cursor[313000 52600 0.000000] PolyArea[200000000.000000] Thermal[0.500000] DRC[500 1000 500 500 1500 700] -Flags("showdrc,nameonpcb,alldirection,clearnew") +Flags("showdrc,nameonpcb,clearnew,snappin") Groups("1,c:2,s:3") Styles["Signal,1000,2900,1500,1000:Power,2500,6000,3500,1000:Fat,2500,6000,3500,1000:Skinny,600,2402,1181,600"] @@ -882,6 +882,11 @@ Via[312300 149400 2900 2000 0 1500 "" ""] Via[322300 194400 2900 2000 0 1500 "" ""] Via[309000 145000 6000 2000 0 3500 "" ""] Via[305700 422300 6000 2000 0 3500 "" "thermal(1S)"] +Via[340800 79400 2900 2000 0 1500 "" ""] +Via[344500 73600 2900 2000 0 1500 "" ""] +Via[349500 76100 2900 2000 0 1500 "" ""] +Via[329500 79500 2900 2000 0 1500 "" ""] +Via[334600 83400 2900 2000 0 1500 "" ""] Element["" "sma-edge" "J8" "SMA" 383700 176700 0 0 1 10 ""] ( @@ -1970,6 +1975,25 @@ Element["" "CB1" "U31" "CB1AH-P-12V" 147750 275500 40300 33400 0 100 ""] ElementLine [-52150 -43300 52150 -43300 1000] ElementLine [52150 -43300 52150 43300 1000] + ) + +Element["" "74x" "R101" "10k" 334600 70200 -10000 -11100 3 100 ""] +( + Pad[2250 -5000 4400 -5000 1400 900 2000 "1" "1" "square,edge2"] + Pad[2250 -2500 4400 -2500 1400 900 2000 "2" "2" "square,edge2"] + Pad[2250 0 4400 0 1400 900 2000 "3" "3" "square,edge2"] + Pad[2250 2500 4400 2500 1400 900 2000 "4" "4" "square,edge2"] + Pad[2250 5000 4400 5000 1400 900 2000 "C" "C" "square,edge2"] + Pad[-4400 -5000 -2250 -5000 1400 900 2000 "C" "C" "square"] + Pad[-4400 -2500 -2250 -2500 1400 900 2000 "9" "9" "square"] + Pad[-4400 0 -2250 0 1400 900 2000 "8" "8" "square"] + Pad[-4400 2500 -2250 2500 1400 900 2000 "7" "7" "square"] + Pad[-4400 5000 -2250 5000 1400 900 2000 "6" "6" "square"] + ElementLine [-6050 -6700 -6050 6700 1000] + ElementLine [6050 -6700 6050 6700 1000] + ElementLine [-6050 6700 6050 6700 1000] + ElementLine [-6050 -6700 6050 -6700 1000] + ) Layer(1 "top") ( @@ -2121,35 +2145,11 @@ Layer(1 "top") Line[351100 192900 353300 190700 1000 2000 "clearline"] Line[356200 190700 356200 193500 1000 2000 "clearline"] Line[356200 193500 354200 195500 1000 2000 "clearline"] - Line[291000 32200 300500 22700 1000 2000 "clearline"] - Line[300500 22700 321000 22700 1000 2000 "clearline"] - Line[321000 32200 311000 42200 1000 2000 "clearline"] - Line[311000 42200 311000 57200 1000 2000 "clearline"] - Line[311000 57200 319500 65700 1000 2000 "clearline"] - Line[319500 65700 319500 86700 1000 2000 "clearline"] Line[291000 52200 291000 76200 1000 2000 "clearline"] Line[291000 76200 312500 97700 1000 2000 "clearline"] Line[312500 97700 320500 97700 1000 2000 "clearline"] Line[320500 97700 324500 93700 1000 2000 "clearline"] Line[314500 79700 314500 87200 1000 2000 "clearline"] - Line[321000 22700 328000 29700 1000 2000 "clearline"] - Line[328000 29700 328000 80200 1000 2000 "clearline"] - Line[328000 80200 334500 86700 1000 2000 "clearline"] - Line[321000 52200 321000 59200 1000 2000 "clearline"] - Line[321000 59200 324000 62200 1000 2000 "clearline"] - Line[324000 62200 324000 81200 1000 2000 "clearline"] - Line[324000 81200 329500 86700 1000 2000 "clearline"] - Line[338500 32200 331000 39700 1000 2000 "clearline"] - Line[331000 39700 331000 77700 1000 2000 "clearline"] - Line[331000 77700 337000 83700 1000 2000 "clearline"] - Line[368500 32200 347000 53700 1000 2000 "clearline"] - Line[347000 53700 347000 95700 1000 2000 "clearline"] - Line[347000 95700 344500 98200 1000 2000 "clearline"] - Line[344500 98200 339500 93200 1000 2000 "clearline"] - Line[338500 52200 338500 80700 1000 2000 "clearline"] - Line[338500 80700 344500 86700 1000 2000 "clearline"] - Line[349500 86700 349500 71200 1000 2000 "clearline"] - Line[349500 71200 368500 52200 1000 2000 "clearline"] Line[334500 107200 334500 102700 1000 2000 "clearline"] Line[334500 102700 332000 100200 1000 2000 "clearline"] Line[324500 107700 328500 103700 1000 2000 "clearline"] @@ -2158,9 +2158,6 @@ Layer(1 "top") Line[337000 100200 333500 96700 1000 2000 "clearline"] Line[333500 96700 325000 96700 1000 2000 "clearline"] Line[325000 96700 314500 107200 1000 2000 "clearline"] - Line[337000 83700 337000 95200 1000 2000 "clearline"] - Line[337000 95200 344500 102700 1000 2000 "clearline"] - Line[344500 102700 344500 107200 1000 2000 "clearline"] Line[319500 113700 319500 119700 1000 2000 "clearline"] Line[349500 113200 349500 116700 2500 2000 "clearline"] Line[349500 116700 346500 119700 2500 2000 "clearline"] @@ -2593,6 +2590,52 @@ Layer(1 "top") Line[82400 85200 106700 90600 20000 4000 "clearline"] Line[106700 90600 106700 59800 20000 4000 "clearline"] Line[106700 75200 82400 75200 20000 4000 "clearline"] + Line[334500 89950 334500 78425 1000 2000 "clearline"] + Line[334500 78425 331275 75200 1000 2000 "clearline"] + Line[329500 89950 329500 78100 1000 2000 "clearline"] + Line[329500 78100 328400 77000 1000 2000 "clearline"] + Line[328400 77000 328400 73300 1000 2000 "clearline"] + Line[328400 73300 329000 72700 1000 2000 "clearline"] + Line[329000 72700 331275 72700 1000 2000 "clearline"] + Line[324500 89950 324500 73600 1000 2000 "clearline"] + Line[324500 73600 327900 70200 1000 2000 "clearline"] + Line[327900 70200 331275 70200 1000 2000 "clearline"] + Line[319500 89950 319500 76100 1000 2000 "clearline"] + Line[319500 76100 327900 67700 1000 2000 "clearline"] + Line[327900 67700 331275 67700 1000 2000 "clearline"] + Line[337100 79400 337100 76025 1000 2000 "clearline"] + Line[337100 76025 337925 75200 1000 2000 "clearline"] + Line[337925 75200 335700 75200 1000 2000 "clearline"] + Line[335700 75200 334600 74100 1000 2000 "clearline"] + Line[334600 74100 334600 65900 1000 2000 "clearline"] + Line[334600 65900 333900 65200 1000 2000 "clearline"] + Line[333900 65200 331275 65200 1000 2000 "clearline"] + Line[337100 79300 337100 97200 1000 2000 "clearline"] + Line[337100 97200 342100 102200 1000 2000 "clearline"] + Line[342100 102200 342100 119100 1000 2000 "clearline"] + Line[342100 119100 341500 119700 1000 2000 "clearline"] + Line[339500 89950 339500 80700 1000 2000 "clearline"] + Line[339500 80700 340800 79400 1000 2000 "clearline"] + Line[340800 79400 340800 73100 1000 2000 "clearline"] + Line[340800 73100 340400 72700 1000 2000 "clearline"] + Line[340400 72700 337925 72700 1000 2000 "clearline"] + Line[344500 89950 344500 73600 1000 2000 "clearline"] + Line[344500 73600 341100 70200 1000 2000 "clearline"] + Line[341100 70200 337925 70200 1000 2000 "clearline"] + Line[349500 89950 349500 74500 1000 2000 "clearline"] + Line[349500 74500 342700 67700 1000 2000 "clearline"] + Line[342700 67700 337925 67700 1000 2000 "clearline"] + Line[344500 110450 344500 105600 1000 2000 "clearline"] + Line[344500 105600 354100 96000 1000 2000 "clearline"] + Line[354100 96000 354100 76400 1000 2000 "clearline"] + Line[354100 76400 342900 65200 1000 2000 "clearline"] + Line[342900 65200 337925 65200 1000 2000 "clearline"] + Line[327900 67700 327900 39100 1000 2000 "clearline"] + Line[327900 39100 321000 32200 1000 2000 "clearline"] + Line[338100 65200 338100 63700 1000 2000 "clearline"] + Line[338100 63700 331700 57300 1000 2000 "clearline"] + Line[331700 57300 331700 39000 1000 2000 "clearline"] + Line[331700 39000 338500 32200 1000 2000 "clearline"] Polygon("") ( [399700 149200] [380700 149200] [380700 166700] [399700 166700] @@ -2663,6 +2706,22 @@ Layer(2 "bottom") Line[82400 85200 106700 90600 20000 4000 "clearline"] Line[106700 90600 106700 59800 20000 4000 "clearline"] Line[106700 75200 82400 75200 20000 4000 "clearline"] + Line[344500 73600 341200 73600 1000 2000 "clearline"] + Line[341200 73600 338400 70800 1000 2000 "clearline"] + Line[338400 70800 338400 52300 1000 2000 "clearline"] + Line[338400 52300 338500 52200 1000 2000 "clearline"] + Line[340800 79400 342300 79400 1000 2000 "clearline"] + Line[342300 79400 347200 74500 1000 2000 "clearline"] + Line[347200 74500 347200 53500 1000 2000 "clearline"] + Line[347200 53500 368500 32200 1000 2000 "clearline"] + Line[349500 76100 349500 71200 1000 2000 "clearline"] + Line[349500 71200 368500 52200 1000 2000 "clearline"] + Line[329500 79500 329500 60700 1000 2000 "clearline"] + Line[329500 60700 321000 52200 1000 2000 "clearline"] + Line[334600 83400 328700 83400 1000 2000 "clearline"] + Line[328700 83400 297400 52100 1000 2000 "clearline"] + Line[297400 52100 297400 38600 1000 2000 "clearline"] + Line[297400 38600 291000 32200 1000 2000 "clearline"] Polygon("clearpoly") ( [397500 447500] [2500 447500] [2500 2500] [397500 2500] @@ -2712,6 +2771,7 @@ NetList() Connect("D8-1") Connect("R2-2") Connect("R18-2") + Connect("R101-C") Connect("U1-5") Connect("U2-10") Connect("U2-16") @@ -3031,41 +3091,49 @@ NetList() ) Net("unnamed_net24" "(unknown)") ( + Connect("R101-2") Connect("S1-4") Connect("U2-1") ) Net("unnamed_net25" "(unknown)") ( + Connect("R101-3") Connect("S1-3") Connect("U2-2") ) Net("unnamed_net26" "(unknown)") ( + Connect("R101-4") Connect("S1-6") Connect("U2-3") ) Net("unnamed_net27" "(unknown)") ( + Connect("R101-6") Connect("S2-1") Connect("U2-4") ) Net("unnamed_net28" "(unknown)") ( + Connect("R101-7") Connect("S2-4") Connect("U2-5") ) Net("unnamed_net29" "(unknown)") ( + Connect("R101-8") Connect("S2-3") Connect("U2-6") ) Net("unnamed_net30" "(unknown)") ( + Connect("R101-9") Connect("S2-6") Connect("U2-7") ) Net("unnamed_net31" "(unknown)") ( + Connect("R101-1") Connect("S1-1") Connect("U2-15") ) diff --git a/telefire.sch b/telefire.sch index 16a8975..a11a406 100644 --- a/telefire.sch +++ b/telefire.sch @@ -1,26 +1,26 @@ v 20110115 2 C 40000 40000 0 0 0 EMBEDDEDtitle-C-keithp.sym [ -T 43200 41100 5 10 0 0 0 0 1 +T 31100 40800 5 10 0 0 0 0 1 graphical=1 -T 54500 40400 15 8 1 0 0 0 1 -FILE: -T 59500 40400 15 8 1 0 0 0 1 -REVISION: -T 57400 40400 15 8 1 0 0 0 1 -PAGE -T 58200 40400 15 8 1 0 0 0 1 -OF -B 54400 40000 7600 2700 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 -L 54400 40600 62000 40600 15 0 0 0 -1 -1 -T 54500 40100 15 10 1 0 0 0 1 -Project URL: +B 30000 40000 32000 27000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 54400 41400 62000 41400 15 0 0 0 -1 -1 T 54900 40800 9 10 1 0 0 0 2 Copyright 2012 by Keith Packard Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL -L 54400 41400 62000 41400 15 0 0 0 -1 -1 -B 30000 40000 32000 27000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 -T 31100 40800 5 10 0 0 0 0 1 +T 54500 40100 15 10 1 0 0 0 1 +Project URL: +L 54400 40600 62000 40600 15 0 0 0 -1 -1 +B 54400 40000 7600 2700 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 58200 40400 15 8 1 0 0 0 1 +OF +T 57400 40400 15 8 1 0 0 0 1 +PAGE +T 59500 40400 15 8 1 0 0 0 1 +REVISION: +T 54500 40400 15 8 1 0 0 0 1 +FILE: +T 43200 41100 5 10 0 0 0 0 1 graphical=1 ] C 45600 54500 1 0 0 gnd.sym @@ -1055,48 +1055,28 @@ footprint=SO16 T 42620 60095 5 10 0 1 0 0 1 device=IC } -C 41725 62250 1 0 1 A6R-102R.sym +C 41200 62300 1 0 1 A6R-102R.sym { -T 40930 63775 5 10 1 1 0 6 1 +T 40405 63825 5 10 1 1 0 6 1 refdes=S1 -T 41255 62348 5 10 1 1 0 6 1 +T 40730 62398 5 10 1 1 0 6 1 value=A6R-102R -T 37225 82850 5 10 0 1 0 6 1 +T 36700 82900 5 10 0 1 0 6 1 footprint=DIP6 } -C 41725 60050 1 0 1 A6R-102R.sym +C 41200 60100 1 0 1 A6R-102R.sym { -T 40930 61575 5 10 1 1 0 6 1 +T 40405 61625 5 10 1 1 0 6 1 refdes=S2 -T 41255 60148 5 10 1 1 0 6 1 +T 40730 60198 5 10 1 1 0 6 1 value=A6R-102R -T 37225 80650 5 10 0 1 0 6 1 +T 36700 80700 5 10 0 1 0 6 1 footprint=DIP6 } -N 41725 63850 42625 63850 4 -N 42625 63850 42625 63550 4 -N 42625 62350 41725 62350 4 -N 41725 62350 41725 62650 4 -N 42625 62750 42025 62750 4 -N 42025 62750 42025 63050 4 -N 42025 63050 41725 63050 4 -N 42625 63150 42325 63150 4 -N 42325 63150 42325 63450 4 -N 42325 63450 41725 63450 4 -N 42625 61950 41725 61950 4 -N 41725 61950 41725 61650 4 -N 41725 60450 42625 60450 4 -N 42625 60450 42625 60750 4 -N 41725 60850 42325 60850 4 -N 42325 60850 42325 61150 4 -N 42325 61150 42625 61150 4 -N 42625 61550 42025 61550 4 -N 42025 61550 42025 61250 4 -N 42025 61250 41725 61250 4 -N 39925 63450 39925 63050 4 -N 39925 61250 39925 60850 4 -C 39825 62750 1 0 0 gnd.sym -C 39825 60550 1 0 0 gnd.sym +N 39400 63500 39400 63100 4 +N 39400 60900 39400 61300 4 +C 39300 62800 1 0 0 gnd.sym +C 39300 60625 1 0 0 gnd.sym C 43975 59800 1 0 0 gnd.sym C 43825 64650 1 0 0 3.3V-plus.sym N 45525 63150 46425 63150 4 @@ -2090,3 +2070,129 @@ refdes=J3 T 45695 45705 5 10 0 1 180 0 1 footprint=ZX62-B-5PA } +N 42100 60500 42100 64200 4 +C 41900 64200 1 0 0 3.3V-plus.sym +N 41200 63900 41200 63675 4 +N 41200 63675 42625 63675 4 +N 42625 63675 42625 63550 4 +N 41200 63500 41200 63250 4 +N 41200 63250 42625 63250 4 +N 42625 63250 42625 63150 4 +N 41200 63100 41200 62900 4 +N 41200 62900 42625 62900 4 +N 42625 62900 42625 62750 4 +N 41200 62700 41200 62500 4 +N 41200 62500 42625 62500 4 +N 42625 62500 42625 62350 4 +N 42625 61950 41200 61950 4 +N 41200 61950 41200 61700 4 +N 42625 61550 41200 61550 4 +N 41200 61550 41200 61300 4 +N 42625 61150 41200 61150 4 +N 41200 61150 41200 60900 4 +N 42625 60750 41200 60750 4 +N 41200 60750 41200 60500 4 +C 41200 63800 1 0 0 74x.sym +{ +T 41500 64200 5 10 0 0 0 0 1 +device=Bussed x8 Resistor Array +T 41300 64050 5 10 1 1 0 0 1 +refdes=R101 +T 41800 64050 5 10 1 1 0 0 1 +value=10k +T 41200 63800 5 10 0 0 0 0 1 +slot=1 +T 41200 63800 5 10 0 0 0 0 1 +footprint=74x +} +C 41200 63400 1 0 0 74x.sym +{ +T 41500 63800 5 10 0 0 0 0 1 +device=Bussed x8 Resistor Array +T 41300 63650 5 10 1 1 0 0 1 +refdes=R101 +T 41800 63650 5 10 1 1 0 0 1 +value=10k +T 41200 63400 5 10 0 0 0 0 1 +slot=2 +T 41200 63400 5 10 0 0 0 0 1 +footprint=74x +} +C 41200 63000 1 0 0 74x.sym +{ +T 41500 63400 5 10 0 0 0 0 1 +device=Bussed x8 Resistor Array +T 41300 63250 5 10 1 1 0 0 1 +refdes=R101 +T 41800 63250 5 10 1 1 0 0 1 +value=10k +T 41200 63000 5 10 0 0 0 0 1 +slot=3 +T 41200 63000 5 10 0 0 0 0 1 +footprint=74x +} +C 41200 62600 1 0 0 74x.sym +{ +T 41500 63000 5 10 0 0 0 0 1 +device=Bussed x8 Resistor Array +T 41300 62850 5 10 1 1 0 0 1 +refdes=R101 +T 41800 62850 5 10 1 1 0 0 1 +value=10k +T 41200 62600 5 10 0 0 0 0 1 +slot=4 +T 41200 62600 5 10 0 0 0 0 1 +footprint=74x +} +C 41200 61600 1 0 0 74x.sym +{ +T 41500 62000 5 10 0 0 0 0 1 +device=Bussed x8 Resistor Array +T 41300 61850 5 10 1 1 0 0 1 +refdes=R101 +T 41800 61850 5 10 1 1 0 0 1 +value=10k +T 41200 61600 5 10 0 0 0 0 1 +slot=5 +T 41200 61600 5 10 0 0 0 0 1 +footprint=74x +} +C 41200 61200 1 0 0 74x.sym +{ +T 41500 61600 5 10 0 0 0 0 1 +device=Bussed x8 Resistor Array +T 41300 61450 5 10 1 1 0 0 1 +refdes=R101 +T 41800 61450 5 10 1 1 0 0 1 +value=10k +T 41200 61200 5 10 0 0 0 0 1 +slot=6 +T 41200 61200 5 10 0 0 0 0 1 +footprint=74x +} +C 41200 60800 1 0 0 74x.sym +{ +T 41500 61200 5 10 0 0 0 0 1 +device=Bussed x8 Resistor Array +T 41300 61050 5 10 1 1 0 0 1 +refdes=R101 +T 41800 61050 5 10 1 1 0 0 1 +value=10k +T 41200 60800 5 10 0 0 0 0 1 +slot=7 +T 41200 60800 5 10 0 0 0 0 1 +footprint=74x +} +C 41200 60400 1 0 0 74x.sym +{ +T 41500 60800 5 10 0 0 0 0 1 +device=Bussed x8 Resistor Array +T 41300 60650 5 10 1 1 0 0 1 +refdes=R101 +T 41800 60650 5 10 1 1 0 0 1 +value=10k +T 41200 60400 5 10 0 0 0 0 1 +slot=8 +T 41200 60400 5 10 0 0 0 0 1 +footprint=74x +} -- 2.47.2