From 0ac34444ce2ccdcaa5fe722e2420f96c46224039 Mon Sep 17 00:00:00 2001 From: drdani Date: Mon, 7 Feb 2000 08:24:57 +0000 Subject: [PATCH] ucsim-0.2.37-pre3 into cvs git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@81 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- sim/ucsim/gui.src/portmon.src/(c).1 | 25 + sim/ucsim/gui.src/portmon.src/Makefile.in | 130 ++ sim/ucsim/gui.src/portmon.src/clean.mk | 28 + sim/ucsim/gui.src/portmon.src/conf.mk | 12 + sim/ucsim/gui.src/portmon.src/pmapp.cc | 113 ++ sim/ucsim/gui.src/portmon.src/pmappcl.h | 48 + sim/ucsim/gui.src/portmon.src/port.cc | 143 ++ sim/ucsim/gui.src/portmon.src/portcl.h | 64 + sim/ucsim/gui.src/portmon.src/portmon.cc | 68 + sim/ucsim/gui.src/serio.src/Makefile.in | 102 ++ sim/ucsim/gui.src/serio.src/USAGE | 9 + sim/ucsim/gui.src/serio.src/clean.mk | 28 + sim/ucsim/gui.src/serio.src/conf.mk | 12 + sim/ucsim/gui.src/serio.src/config.h | 16 + sim/ucsim/gui.src/serio.src/fileio.cc | 143 ++ sim/ucsim/gui.src/serio.src/fileio.hh | 22 + sim/ucsim/gui.src/serio.src/frontend.cc | 162 ++ sim/ucsim/gui.src/serio.src/frontend.hh | 43 + sim/ucsim/gui.src/serio.src/main.cc | 102 ++ sim/ucsim/gui.src/serio.src/posix_signal.cc | 106 ++ sim/ucsim/gui.src/serio.src/posix_signal.hh | 19 + sim/ucsim/s51.src/(c).1 | 25 + sim/ucsim/s51.src/(null).cdb | 1 + sim/ucsim/s51.src/Makefile.in | 129 ++ sim/ucsim/s51.src/arith.cc | 535 +++++++ sim/ucsim/s51.src/bit.cc | 235 +++ sim/ucsim/s51.src/clean.mk | 29 + sim/ucsim/s51.src/cmd.cc | 244 +++ sim/ucsim/s51.src/cmd.h | 55 + sim/ucsim/s51.src/cmd51.cc | 157 ++ sim/ucsim/s51.src/cmd51cl.h | 67 + sim/ucsim/s51.src/cmd_brk.cc | 264 ++++ sim/ucsim/s51.src/cmd_brk.h | 44 + sim/ucsim/s51.src/conf.mk | 11 + sim/ucsim/s51.src/debugger | 1 + sim/ucsim/s51.src/dump.cc | 282 ++++ sim/ucsim/s51.src/dump.h | 51 + sim/ucsim/s51.src/glob.cc | 501 ++++++ sim/ucsim/s51.src/glob.h | 40 + sim/ucsim/s51.src/go.cc | 219 +++ sim/ucsim/s51.src/go.h | 43 + sim/ucsim/s51.src/inc.cc | 184 +++ sim/ucsim/s51.src/inst.list | 256 +++ sim/ucsim/s51.src/interrupt.cc | 85 + sim/ucsim/s51.src/interruptcl.h | 54 + sim/ucsim/s51.src/jmp.cc | 531 +++++++ sim/ucsim/s51.src/logic.cc | 377 +++++ sim/ucsim/s51.src/lst2ls | 23 + sim/ucsim/s51.src/monitor1-2 | 5 + sim/ucsim/s51.src/monitor2-1 | 5 + sim/ucsim/s51.src/mov.cc | 565 +++++++ sim/ucsim/s51.src/port.cc | 78 + sim/ucsim/s51.src/portcl.h | 57 + sim/ucsim/s51.src/regs51.h | 320 ++++ sim/ucsim/s51.src/s51.cc | 55 + sim/ucsim/s51.src/serial.cc | 72 + sim/ucsim/s51.src/serialcl.h | 54 + sim/ucsim/s51.src/set.cc | 384 +++++ sim/ucsim/s51.src/set.h | 48 + sim/ucsim/s51.src/show.cc | 346 ++++ sim/ucsim/s51.src/show.h | 37 + sim/ucsim/s51.src/sim51.cc | 274 ++++ sim/ucsim/s51.src/sim51cl.h | 47 + sim/ucsim/s51.src/start1 | 5 + sim/ucsim/s51.src/start2 | 5 + sim/ucsim/s51.src/temp.lnk | 15 + sim/ucsim/s51.src/test_extit.c | 15 + sim/ucsim/s51.src/test_idlepd.c | 35 + sim/ucsim/s51.src/test_ser.c | 114 ++ sim/ucsim/s51.src/test_stack.c | 9 + sim/ucsim/s51.src/timer0.cc | 69 + sim/ucsim/s51.src/timer0cl.h | 54 + sim/ucsim/s51.src/timer1.cc | 69 + sim/ucsim/s51.src/timer1cl.h | 54 + sim/ucsim/s51.src/timer2.cc | 70 + sim/ucsim/s51.src/timer2cl.h | 54 + sim/ucsim/s51.src/uc251.cc | 45 + sim/ucsim/s51.src/uc251cl.h | 45 + sim/ucsim/s51.src/uc51.cc | 1566 +++++++++++++++++++ sim/ucsim/s51.src/uc51cl.h | 256 +++ sim/ucsim/s51.src/uc51r.cc | 466 ++++++ sim/ucsim/s51.src/uc51rcl.h | 73 + sim/ucsim/s51.src/uc52.cc | 310 ++++ sim/ucsim/s51.src/uc52cl.h | 61 + sim/ucsim/s51.src/uc89c51r.cc | 307 ++++ sim/ucsim/s51.src/uc89c51rcl.h | 63 + sim/ucsim/s51.src/where.cc | 142 ++ sim/ucsim/s51.src/where.h | 46 + sim/ucsim/sim.src/(c).1 | 25 + sim/ucsim/sim.src/Makefile.in | 116 ++ sim/ucsim/sim.src/arg.cc | 209 +++ sim/ucsim/sim.src/argcl.h | 134 ++ sim/ucsim/sim.src/brk.cc | 326 ++++ sim/ucsim/sim.src/brkcl.h | 211 +++ sim/ucsim/sim.src/clean.mk | 22 + sim/ucsim/sim.src/conf.mk | 10 + sim/ucsim/sim.src/hw.cc | 92 ++ sim/ucsim/sim.src/hwcl.h | 63 + sim/ucsim/sim.src/itsrc.cc | 110 ++ sim/ucsim/sim.src/itsrccl.h | 84 + sim/ucsim/sim.src/mem.cc | 403 +++++ sim/ucsim/sim.src/memcl.h | 125 ++ sim/ucsim/sim.src/option.cc | 173 ++ sim/ucsim/sim.src/optioncl.h | 89 ++ sim/ucsim/sim.src/sim.cc | 652 ++++++++ sim/ucsim/sim.src/simcl.h | 99 ++ sim/ucsim/sim.src/stack.cc | 49 + sim/ucsim/sim.src/stackcl.h | 61 + sim/ucsim/sim.src/uc.cc | 970 ++++++++++++ sim/ucsim/sim.src/uccl.h | 191 +++ sim/ucsim/z80.src/(c).1 | 25 + sim/ucsim/z80.src/Makefile.in | 120 ++ sim/ucsim/z80.src/clean.mk | 26 + sim/ucsim/z80.src/conf.mk | 10 + sim/ucsim/z80.src/glob.cc | 155 ++ sim/ucsim/z80.src/glob.h | 39 + sim/ucsim/z80.src/inst.cc | 49 + sim/ucsim/z80.src/instcl.h | 5 + sim/ucsim/z80.src/regsz80.h | 72 + sim/ucsim/z80.src/simz80.cc | 44 + sim/ucsim/z80.src/simz80cl.h | 45 + sim/ucsim/z80.src/sz80.cc | 46 + sim/ucsim/z80.src/z80.cc | 356 +++++ sim/ucsim/z80.src/z80cl.h | 69 + 124 files changed, 17408 insertions(+) create mode 100644 sim/ucsim/gui.src/portmon.src/(c).1 create mode 100644 sim/ucsim/gui.src/portmon.src/Makefile.in create mode 100644 sim/ucsim/gui.src/portmon.src/clean.mk create mode 100644 sim/ucsim/gui.src/portmon.src/conf.mk create mode 100644 sim/ucsim/gui.src/portmon.src/pmapp.cc create mode 100644 sim/ucsim/gui.src/portmon.src/pmappcl.h create mode 100644 sim/ucsim/gui.src/portmon.src/port.cc create mode 100644 sim/ucsim/gui.src/portmon.src/portcl.h create mode 100644 sim/ucsim/gui.src/portmon.src/portmon.cc create mode 100644 sim/ucsim/gui.src/serio.src/Makefile.in create mode 100644 sim/ucsim/gui.src/serio.src/USAGE create mode 100644 sim/ucsim/gui.src/serio.src/clean.mk create mode 100644 sim/ucsim/gui.src/serio.src/conf.mk create mode 100644 sim/ucsim/gui.src/serio.src/config.h create mode 100644 sim/ucsim/gui.src/serio.src/fileio.cc create mode 100644 sim/ucsim/gui.src/serio.src/fileio.hh create mode 100644 sim/ucsim/gui.src/serio.src/frontend.cc create mode 100644 sim/ucsim/gui.src/serio.src/frontend.hh create mode 100644 sim/ucsim/gui.src/serio.src/main.cc create mode 100644 sim/ucsim/gui.src/serio.src/posix_signal.cc create mode 100644 sim/ucsim/gui.src/serio.src/posix_signal.hh create mode 100644 sim/ucsim/s51.src/(c).1 create mode 100644 sim/ucsim/s51.src/(null).cdb create mode 100644 sim/ucsim/s51.src/Makefile.in create mode 100644 sim/ucsim/s51.src/arith.cc create mode 100644 sim/ucsim/s51.src/bit.cc create mode 100644 sim/ucsim/s51.src/clean.mk create mode 100644 sim/ucsim/s51.src/cmd.cc create mode 100644 sim/ucsim/s51.src/cmd.h create mode 100644 sim/ucsim/s51.src/cmd51.cc create mode 100644 sim/ucsim/s51.src/cmd51cl.h create mode 100644 sim/ucsim/s51.src/cmd_brk.cc create mode 100644 sim/ucsim/s51.src/cmd_brk.h create mode 100644 sim/ucsim/s51.src/conf.mk create mode 100755 sim/ucsim/s51.src/debugger create mode 100644 sim/ucsim/s51.src/dump.cc create mode 100644 sim/ucsim/s51.src/dump.h create mode 100644 sim/ucsim/s51.src/glob.cc create mode 100644 sim/ucsim/s51.src/glob.h create mode 100644 sim/ucsim/s51.src/go.cc create mode 100644 sim/ucsim/s51.src/go.h create mode 100644 sim/ucsim/s51.src/inc.cc create mode 100644 sim/ucsim/s51.src/inst.list create mode 100644 sim/ucsim/s51.src/interrupt.cc create mode 100644 sim/ucsim/s51.src/interruptcl.h create mode 100644 sim/ucsim/s51.src/jmp.cc create mode 100644 sim/ucsim/s51.src/logic.cc create mode 100755 sim/ucsim/s51.src/lst2ls create mode 100755 sim/ucsim/s51.src/monitor1-2 create mode 100755 sim/ucsim/s51.src/monitor2-1 create mode 100644 sim/ucsim/s51.src/mov.cc create mode 100644 sim/ucsim/s51.src/port.cc create mode 100644 sim/ucsim/s51.src/portcl.h create mode 100644 sim/ucsim/s51.src/regs51.h create mode 100644 sim/ucsim/s51.src/s51.cc create mode 100644 sim/ucsim/s51.src/serial.cc create mode 100644 sim/ucsim/s51.src/serialcl.h create mode 100644 sim/ucsim/s51.src/set.cc create mode 100644 sim/ucsim/s51.src/set.h create mode 100644 sim/ucsim/s51.src/show.cc create mode 100644 sim/ucsim/s51.src/show.h create mode 100644 sim/ucsim/s51.src/sim51.cc create mode 100644 sim/ucsim/s51.src/sim51cl.h create mode 100755 sim/ucsim/s51.src/start1 create mode 100755 sim/ucsim/s51.src/start2 create mode 100644 sim/ucsim/s51.src/temp.lnk create mode 100644 sim/ucsim/s51.src/test_extit.c create mode 100644 sim/ucsim/s51.src/test_idlepd.c create mode 100644 sim/ucsim/s51.src/test_ser.c create mode 100644 sim/ucsim/s51.src/test_stack.c create mode 100644 sim/ucsim/s51.src/timer0.cc create mode 100644 sim/ucsim/s51.src/timer0cl.h create mode 100644 sim/ucsim/s51.src/timer1.cc create mode 100644 sim/ucsim/s51.src/timer1cl.h create mode 100644 sim/ucsim/s51.src/timer2.cc create mode 100644 sim/ucsim/s51.src/timer2cl.h create mode 100644 sim/ucsim/s51.src/uc251.cc create mode 100644 sim/ucsim/s51.src/uc251cl.h create mode 100644 sim/ucsim/s51.src/uc51.cc create mode 100644 sim/ucsim/s51.src/uc51cl.h create mode 100644 sim/ucsim/s51.src/uc51r.cc create mode 100644 sim/ucsim/s51.src/uc51rcl.h create mode 100644 sim/ucsim/s51.src/uc52.cc create mode 100644 sim/ucsim/s51.src/uc52cl.h create mode 100644 sim/ucsim/s51.src/uc89c51r.cc create mode 100644 sim/ucsim/s51.src/uc89c51rcl.h create mode 100644 sim/ucsim/s51.src/where.cc create mode 100644 sim/ucsim/s51.src/where.h create mode 100644 sim/ucsim/sim.src/(c).1 create mode 100644 sim/ucsim/sim.src/Makefile.in create mode 100644 sim/ucsim/sim.src/arg.cc create mode 100644 sim/ucsim/sim.src/argcl.h create mode 100644 sim/ucsim/sim.src/brk.cc create mode 100644 sim/ucsim/sim.src/brkcl.h create mode 100644 sim/ucsim/sim.src/clean.mk create mode 100644 sim/ucsim/sim.src/conf.mk create mode 100644 sim/ucsim/sim.src/hw.cc create mode 100644 sim/ucsim/sim.src/hwcl.h create mode 100644 sim/ucsim/sim.src/itsrc.cc create mode 100644 sim/ucsim/sim.src/itsrccl.h create mode 100644 sim/ucsim/sim.src/mem.cc create mode 100644 sim/ucsim/sim.src/memcl.h create mode 100644 sim/ucsim/sim.src/option.cc create mode 100644 sim/ucsim/sim.src/optioncl.h create mode 100644 sim/ucsim/sim.src/sim.cc create mode 100644 sim/ucsim/sim.src/simcl.h create mode 100644 sim/ucsim/sim.src/stack.cc create mode 100644 sim/ucsim/sim.src/stackcl.h create mode 100644 sim/ucsim/sim.src/uc.cc create mode 100644 sim/ucsim/sim.src/uccl.h create mode 100644 sim/ucsim/z80.src/(c).1 create mode 100644 sim/ucsim/z80.src/Makefile.in create mode 100644 sim/ucsim/z80.src/clean.mk create mode 100644 sim/ucsim/z80.src/conf.mk create mode 100644 sim/ucsim/z80.src/glob.cc create mode 100644 sim/ucsim/z80.src/glob.h create mode 100644 sim/ucsim/z80.src/inst.cc create mode 100644 sim/ucsim/z80.src/instcl.h create mode 100644 sim/ucsim/z80.src/regsz80.h create mode 100644 sim/ucsim/z80.src/simz80.cc create mode 100644 sim/ucsim/z80.src/simz80cl.h create mode 100644 sim/ucsim/z80.src/sz80.cc create mode 100644 sim/ucsim/z80.src/z80.cc create mode 100644 sim/ucsim/z80.src/z80cl.h diff --git a/sim/ucsim/gui.src/portmon.src/(c).1 b/sim/ucsim/gui.src/portmon.src/(c).1 new file mode 100644 index 00000000..d673f9fd --- /dev/null +++ b/sim/ucsim/gui.src/portmon.src/(c).1 @@ -0,0 +1,25 @@ +/* + * Simulator of microcontrollers (@@F@@) + * + * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ diff --git a/sim/ucsim/gui.src/portmon.src/Makefile.in b/sim/ucsim/gui.src/portmon.src/Makefile.in new file mode 100644 index 00000000..5f3e2907 --- /dev/null +++ b/sim/ucsim/gui.src/portmon.src/Makefile.in @@ -0,0 +1,130 @@ +# +# uCsim gui.src/portmon.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1999 +# + +SHELL = /bin/sh +CXX = @CXX@ +CPP = @CPP@ +CXXCPP = @CXXCPP@ +RANLIB = @RANLIB@ +INSTALL = @INSTALL@ + +PRJDIR = ../.. +PKGDIR = ../ + +DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +CPPFLAGS = @CPPFLAGS@ -I. -I$(PRJDIR) -I$(PKGDIR) +CFLAGS = @CFLAGS@ -Wall +CXXFLAGS = @CXXFLAGS@ -Wall +M_OR_MM = @M_OR_MM@ + +LIBS = -L$(PRJDIR) -L$(PKGDIR) -lgui -lutil @LIBS@ + +curses_ok = @curses_ok@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +includedir = @includedir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +srcdir = @srcdir@ + +OBJECTS = portmon.o \ + pmapp.o port.o + + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs portmon.src + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) -s portmon $(bindir) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(bindir)/portmon + + +# Performing self-test +# -------------------- +check: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(bindir) || $(INSTALL) -d $(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: *.cc *.h $(PRJDIR)/*.h $(PKGDIR)/*.h + $(CXXCPP) $(CPPFLAGS) $(M_OR_MM) *.cc >Makefile.dep + +include Makefile.dep +include clean.mk + +#parser.cc: parser.y + +#plex.cc: plex.l + +# My rules +# -------- +ifeq ($(curses_ok),yes) +portmon.src: portmon +else +portmon.src: +endif + +portmon: $(OBJECTS) $(PRJDIR)/*.a $(PKGDIR)/*.a + $(CXX) $(CXXFLAGS) -o portmon $(OBJECTS) $(LIBS) + +ifeq ($(curses_ok),yes) +otherlibs: + cd $(PRJDIR) && $(MAKE) libs + cd $(PKGDIR) && $(MAKE) libs +else +otherlibs: +endif + +.cc.o: + $(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $< -o $@ + +.y.cc: + rm -f $*.cc $*.h + $(YACC) -d $< + mv y.tab.c $*.cc + mv y.tab.h $*.h + +.l.cc: + rm -f $*.cc + $(LEX) -t $< >$*.cc + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(PRJDIR)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" PRJDIR="$(PRJDIR)" freshconf;\ + fi + +# End of gui.src/portmon.src/Makefile.in diff --git a/sim/ucsim/gui.src/portmon.src/clean.mk b/sim/ucsim/gui.src/portmon.src/clean.mk new file mode 100644 index 00000000..02760e9b --- /dev/null +++ b/sim/ucsim/gui.src/portmon.src/clean.mk @@ -0,0 +1,28 @@ +# uCsim gui.src/portmon.src/clean.mk + +# Deleting all files created by building the program +# -------------------------------------------------- +clean: + rm -f *core *[%~] *.[oa] + rm -f .[a-z]*~ + rm -f portmon + + +# Deleting all files created by configuring or building the program +# ----------------------------------------------------------------- +distclean: clean + rm -f config.cache config.log config.status + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean + +# End of gui.src/portmon.src/clean.mk diff --git a/sim/ucsim/gui.src/portmon.src/conf.mk b/sim/ucsim/gui.src/portmon.src/conf.mk new file mode 100644 index 00000000..b3ad7360 --- /dev/null +++ b/sim/ucsim/gui.src/portmon.src/conf.mk @@ -0,0 +1,12 @@ +# uCsim gui.src/portmon.src/conf.mk + +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(PRJDIR)/configure.in + cd $(PRJDIR) && $(SHELL) ./config.status + +# End of gui.src/portmon.src/conf.mk diff --git a/sim/ucsim/gui.src/portmon.src/pmapp.cc b/sim/ucsim/gui.src/portmon.src/pmapp.cc new file mode 100644 index 00000000..2605a22c --- /dev/null +++ b/sim/ucsim/gui.src/portmon.src/pmapp.cc @@ -0,0 +1,113 @@ +/* + * Simulator of microcontrollers (pmapp.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "wincl.h" +#include "labelcl.h" + +#include "pmappcl.h" +#include "portcl.h" + + +int +cl_pmapp::mk_views(class cl_group *ins_to) +{ + class cl_view *v; + //class cl_win *w; + class cl_box *b; + + b= new cl_box(0,0,0,0); + + if (!ins_to) + return(0); + + b->set(43,2,14,13); + v= new cl_portw(b, 3, "Port #3", this); + v->init(); + ins_to->insert(v); + + b->set(29,2,14,13); + v= new cl_portw(b, 2, "Port #2", this); + v->init(); + ins_to->insert(v); + /* + b->set(15,2,14,13); + ins_to->insert(v= new cl_portw(b, 1, "Port #1", this)); + v->init(); + + b->set(1,2,14,13); + ins_to->insert(v= new cl_portw(b, 0, "Port #0", this)); + v->init(); + + b->set(59,3,19,11); + v= new cl_label(b, this, +"Next win: n,TAB\nPrev win: p\nCursor : u,d,l,r,\n arrows\nToggle : space,CR\nQuit : q"); + v->init(); + b->move_rel(-1,-1); + b->grow(2,2); + + b->set(58,2,21,13); + w= new cl_win(b, "Help", this); + w->options&= ~OF_SELECTABLE; + w->init(); + w->insert(v); + ins_to->insert(w); + w->draw(); + */ + delete b; + + return(0); +} + +int * +cl_pmapp::mk_palette(void) +{ + return(cl_app::mk_palette()); +} + +int +cl_pmapp::handle_event(struct t_event *event) +{ + if (event->what == EV_KEY) + switch (event->event.key) + { + case 'q': + event->what= EV_COMMAND; + event->event.msg.cmd= CMD_QUIT; + return(0); + case 'p': + desk->select_prev(); + return(1); + case 'n': case '\t': + desk->select_next(); + return(1); + + } + return(cl_app::handle_event(event)); +} + + +/* End of gui.src/portmon.src/pmapp.cc */ diff --git a/sim/ucsim/gui.src/portmon.src/pmappcl.h b/sim/ucsim/gui.src/portmon.src/pmappcl.h new file mode 100644 index 00000000..d9f30110 --- /dev/null +++ b/sim/ucsim/gui.src/portmon.src/pmappcl.h @@ -0,0 +1,48 @@ +/* + * Simulator of microcontrollers (pmappcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef PMAPPCL_HEADER +#define PMAPPCL_HEADER + +#include "appcl.h" + + +class cl_pmapp: public cl_app +{ +public: + cl_pmapp(char *iname): cl_app(iname) {} + + virtual int mk_views(class cl_group *ins_to); + virtual int *mk_palette(void); + + virtual int handle_event(struct t_event *event); +}; + + +#endif + +/* End of gui.src/portmon.src/pmappcl.h */ diff --git a/sim/ucsim/gui.src/portmon.src/port.cc b/sim/ucsim/gui.src/portmon.src/port.cc new file mode 100644 index 00000000..010ec3e8 --- /dev/null +++ b/sim/ucsim/gui.src/portmon.src/port.cc @@ -0,0 +1,143 @@ +/*@1@*/ + +#include "portcl.h" + + +/* + * Viewer of the port + */ + +cl_port::cl_port(class cl_box *ipos, int iid, char *iname, class cl_app *iapp): + cl_view(ipos, iname, iapp) +{ + id= iid; + sfr= 0; + pin= 0; + curs_x= curs_y= 0; +} + +int +cl_port::draw(void) +{ + int x, y, mask, hc, nc; + + cl_view::draw(); + + nc= hc= get_color(C_WIN_NORMAL); + if (state & SF_SELECTED) + hc= get_color(C_WIN_SELECTED); + mvwprintw(window, 0,0, "SFR PORT PIN"); + for (x= 0, mask= 0x80, y= 1; mask; mask>>= 1,y++) + { + wattrset(window, (curs_x)?nc:(curs_y==y-1?hc:nc)); + mvwprintw(window, y,x, " %c", (sfr&mask)?'1':'0'); + } + wattrset(window, nc); + for (x= 5, mask= 0x80, y= 1; mask; mask>>= 1,y++) + mvwprintw(window, y,x, "%c", (sfr&pin&mask)?'1':'0'); + for (x=9, mask= 0x80, y= 1; mask; mask>>= 1,y++) + { + wattrset(window, curs_x?(curs_y==y-1?hc:nc):nc); + mvwprintw(window, y,x, "%c ", (pin&mask)?'1':'0'); + } + wattrset(window, nc); + mvwprintw(window, 9,0, "0x%02x 0x%02x", sfr, pin); + mvwprintw(window, 10,4, "0x%02x", sfr&pin); + app->drawn++; + return(0); +} + +int +cl_port::handle_event(struct t_event *event) +{ + if (event->what == EV_KEY) + switch (event->event.key) + { + case KEY_HOME: + curs_y= 0; draw(); return(1); + case KEY_A1: + curs_x= curs_y= 0; draw(); return(1); + case KEY_A3: + curs_y= 0; curs_x= 1; draw(); return(1); + case KEY_C1: + curs_x= 0; curs_y= 7; draw(); return(1); + case KEY_C3: + curs_x= 1; curs_y= 7; draw(); return(1); + case KEY_LEFT: case KEY_RIGHT: case 'j': case 'k': case 'l': case 'r': + if (curs_x) + curs_x= 0; + else + curs_x= 1; + draw(); + return(1); + case KEY_UP: case 'u': + curs_y--; + if (curs_y < 0) + curs_y= 7; + draw(); + return(1); + case KEY_DOWN: case 'd': + curs_y++; + if (curs_y > 7) + curs_y= 0; + draw(); + return(1); + case ' ': case '\n': case '\r': + if (curs_x) + toggle_pin(7-curs_y); + else + toggle_sfr(7-curs_y); + return(1); + } + return(cl_view::handle_event(event)); +} + +int +cl_port::toggle_sfr(int bitnr) +{ + int mask= 1<init(); + return(v); +} + +int +cl_portw::handle_event(struct t_event *event) +{ + return(cl_win::handle_event(event)); +} + + +/* End of gui.src/portmap.src/port.cc */ diff --git a/sim/ucsim/gui.src/portmon.src/portcl.h b/sim/ucsim/gui.src/portmon.src/portcl.h new file mode 100644 index 00000000..760f0ad6 --- /dev/null +++ b/sim/ucsim/gui.src/portmon.src/portcl.h @@ -0,0 +1,64 @@ +/* + * Simulator of microcontrollers (portcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef PORTCL_HEADER +#define PORTCL_HEADER + +#include "viewcl.h" +#include "wincl.h" + + +class cl_port: public cl_view +{ +public: + int id; + int sfr, pin; + int curs_x, curs_y; +public: + cl_port(class cl_box *ipos, int iid, char *iname, class cl_app *iapp); + + virtual int draw(void); + virtual int handle_event(struct t_event *event); + int toggle_sfr(int bitnr); + int toggle_pin(int bitnr); +}; + +class cl_portw: public cl_win +{ +public: + int id; +public: + cl_portw(class cl_box *ipos, int iid, char *ititle, class cl_app *iapp); + virtual class cl_view *mk_intern(class cl_box *ipos); + + virtual int handle_event(struct t_event *event); +}; + + +#endif + +/* End of gui.src/portmon.src/portcl.h */ diff --git a/sim/ucsim/gui.src/portmon.src/portmon.cc b/sim/ucsim/gui.src/portmon.src/portmon.cc new file mode 100644 index 00000000..50d3b3a8 --- /dev/null +++ b/sim/ucsim/gui.src/portmon.src/portmon.cc @@ -0,0 +1,68 @@ +/* + * Simulator of microcontrollers (portmon.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include + +#include "pmappcl.h" + + +class cl_pmapp *app; + +void xx(class cl_view *v) +{ + fprintf(stderr,"%s 0x%x ", v->name, v->state); +} + +int +main(int argc, char *argv) +{ + app= new cl_pmapp("portmon"); + app->init(); + { + class cl_view *v= app; + while (v) + { + if (v->is_group()) + { + class cl_group *g= (class cl_group *)v; + fprintf(stderr, "%s->%s\n", g->name,(g->current)?(g->current->name):"none"); + g->for_each(xx); + fprintf(stderr, "\n"); + v= g->current; + } + else + v= 0; + } + } + app->run(); + //getch(); + delete app; + return(0); +} + + +/* End of gui.src/portmon.src/portmon.cc */ diff --git a/sim/ucsim/gui.src/serio.src/Makefile.in b/sim/ucsim/gui.src/serio.src/Makefile.in new file mode 100644 index 00000000..024a0d2e --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/Makefile.in @@ -0,0 +1,102 @@ +# Makefile for kano-networks talker + +SHELL = /bin/sh +CXX = @CXX@ +CXXCPP = @CXXCPP@ +INSTALL = @INSTALL@ +CP = /bin/cp + +PRJDIR = ../.. + +DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +CPPFLAGS = @CPPFLAGS@ -I. -I$(PRJDIR) \ + -I$(PRJDIR)/cmd.src -I$(PRJDIR)/sim.src +CFLAGS = @CFLAGS@ -Wall +CXXFLAGS = @CXXFLAGS@ -Wall +M_OR_MM = @M_OR_MM@ + +LIBS = @LIBS@ + +curses_ok = @curses_ok@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +includedir = @includedir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +srcdir = @srcdir@ + +OBJECTS = main.o fileio.o frontend.o posix_signal.o + + +# Compiling entire program or any subproject +# ------------------------------------------ +all: serio.src + +ifeq ($(curses_ok),yes) +serio.src: checkconf serialview +else +serio.src: checkconf +endif + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) -s serialview $(bindir) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(bindir)/serialview + + +# Performing self-test +# -------------------- +check: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(bindir) || $(INSTALL) -d $(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: *.cc *.h *.hh + $(CXXCPP) $(CPPFLAGS) $(M_OR_MM) *.cc >Makefile.dep + +include Makefile.dep +include clean.mk + + +# My rules +# -------- +serialview: $(OBJECTS) + $(CXX) -o $@ $(OBJECTS) $(LIBS) + +.cc.o: + $(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $< -o $@ + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(PRJDIR)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" PRJDIR="$(PRJDIR)" freshconf;\ + fi + +# End of gui.src/serio.src/Makefile.in diff --git a/sim/ucsim/gui.src/serio.src/USAGE b/sim/ucsim/gui.src/serio.src/USAGE new file mode 100644 index 00000000..a76e65e5 --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/USAGE @@ -0,0 +1,9 @@ +*note: tested on: +Solaris 7 using gcc version 2.95.1 19990816 (release) +with ncurses +should work with curses although not guranteed + +Start serialview +Start the s51 simulator with the following command line options: +-S out=/tmp/out,in=/tmp/in +or whatever pipes you wish to use diff --git a/sim/ucsim/gui.src/serio.src/clean.mk b/sim/ucsim/gui.src/serio.src/clean.mk new file mode 100644 index 00000000..15d74cd6 --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/clean.mk @@ -0,0 +1,28 @@ +# uCsim gui.src/serio.src/clean.mk + +# Deleting all files created by building the program +# -------------------------------------------------- +clean: + rm -f *core *[%~] *.[oa] + rm -f .[a-z]*~ + rm -f serialview + + +# Deleting all files created by configuring or building the program +# ----------------------------------------------------------------- +distclean: clean + rm -f config.cache config.log config.status + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean + +# End of gui.src/serio.src/clean.mk diff --git a/sim/ucsim/gui.src/serio.src/conf.mk b/sim/ucsim/gui.src/serio.src/conf.mk new file mode 100644 index 00000000..a4bc1a28 --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/conf.mk @@ -0,0 +1,12 @@ +# uCsim gui.src/serio.src/conf.mk + +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(PRJDIR)/configure.in + cd $(PRJDIR) && $(SHELL) ./config.status + +# End of gui.src/serio.src/conf.mk diff --git a/sim/ucsim/gui.src/serio.src/config.h b/sim/ucsim/gui.src/serio.src/config.h new file mode 100644 index 00000000..2ee36881 --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/config.h @@ -0,0 +1,16 @@ +/****************************************************************************** + * to emulate the serial input and output of an 8051 controller * + * config.h - general defintions * + ******************************************************************************/ + +#ifndef DEF_INFILE +// the processors serial output +#define DEF_INFILE "/tmp/out" +#endif + +#ifndef DEF_OUTFILE +// the processors serial input +#define DEF_OUTFILE "/tmp/in" +#endif + +#define MAX_SIZ 1024 diff --git a/sim/ucsim/gui.src/serio.src/fileio.cc b/sim/ucsim/gui.src/serio.src/fileio.cc new file mode 100644 index 00000000..8c653cfd --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/fileio.cc @@ -0,0 +1,143 @@ +/****************************************************************************** + * to emulate the serial input and output of an 8051 controller * + * fileio.cc - file input and output * + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include "fileio.hh" + +FileIO::FileIO() +{ + + // make the input fifo + if(mkfifo(DEF_INFILE, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH) == -1) { + if(errno != EEXIST) { + cerr << "mkfifo(): Error number " << errno << " occourred: " << strerror(errno) << "\n"; + exit(-1); + } + } + + // the input fifo - non blocking + if ((fdin = open(DEF_INFILE, O_RDONLY|O_NONBLOCK)) == -1) { + cerr << "open(): Error number " << errno << " occourred: " << strerror(errno) << "\n"; + exit(-1); + } + + // make the output fifo + if(mkfifo(DEF_OUTFILE, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH) == -1) { + if(errno != EEXIST) { + cerr << "mkfifo(): Error number " << errno << " occourred: " << strerror(errno) << "\n"; + exit(-1); + } + } + + // the output fifo + if ((fdout = open(DEF_OUTFILE, O_RDWR|O_NONBLOCK)) == -1) { + cerr << "open(): Error number " << errno << " occourred: " << strerror(errno) << "\n"; + exit(-1); + } +} + +FileIO::FileIO(char *infile, char *outfile) +{ + // make the input fifo + if(mkfifo(infile, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH) == -1) { + if(errno != EEXIST) { + cerr << "mkfifo(): Error number " << errno << " occourred: " << strerror(errno); + exit(-1); + } + } + + // the input fifo - non blocking + if ((fdin = open(infile, O_RDONLY|O_NONBLOCK)) == -1) { + cerr << "open(): Error number " << errno << " occourred: " << strerror(errno); + exit(-1); + } + + // make the output fifo + if(mkfifo(outfile, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH) == -1) { + if(errno != EEXIST) { + cerr << "mkfifo(): Error number " << errno << " occourred: " << strerror(errno); + exit(-1); + } + } + + // the output fifo + if ((fdout = open(outfile, O_RDWR|O_NONBLOCK)) == -1) { + cerr << "open(): Error number " << errno << " occourred: " << strerror(errno); + exit(-1); + } +} + + +FileIO::~FileIO() +{ + close(fdin); + close(fdout); +} + +int FileIO::SendByte(char b) +{ + int ret; + + if((ret = write(fdout, &b, 1)) != 1) + { + cerr << "write(): Error number " << errno << " occourred: " << strerror(errno); + exit(-1); + } + + return(ret); +} + + +int FileIO::RecvByte(char *b) +{ + int ret; + + ret = read(fdin, b, 1); + + if((ret == -1) && (errno != EAGAIN)) + { + cerr << "read(): Error number " << errno << " occourred: " << strerror(errno); + exit(-1); + } + + return(ret); +} + +// send a string +int FileIO::SendStr(char *str) +{ + int ret; + + if((ret = write(fdout, str, strlen(str))) != (int)strlen(str)) + { + cerr << "write(): Error number " << errno << " occourred: " << strerror(errno); + exit(-1); + } + + return(ret); +} + + +int FileIO::RecvStr(char *str) +{ + int ret; + + ret = read(fdin, str, MAX_SIZ-1); + str[MAX_SIZ] = 0; + + if((ret == -1) && (errno != EAGAIN)) + { + cerr << "read(): Error number " << errno << " occourred: " << strerror(errno); + exit(-1); + } + + return(ret); +} diff --git a/sim/ucsim/gui.src/serio.src/fileio.hh b/sim/ucsim/gui.src/serio.src/fileio.hh new file mode 100644 index 00000000..fa7ac411 --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/fileio.hh @@ -0,0 +1,22 @@ +/****************************************************************************** + * to emulate the serial input and output of an 8051 controller * + * fileio.hh - file input and output * + ******************************************************************************/ +#include "config.h" + +class FileIO +{ + public: + FileIO(); + FileIO(char *infile, char *outfile); + ~FileIO(); + + int SendByte(char b); + int RecvByte(char *b); + int SendStr(char *str); + int RecvStr(char *str); + + private: + int fdin; + int fdout; +}; diff --git a/sim/ucsim/gui.src/serio.src/frontend.cc b/sim/ucsim/gui.src/serio.src/frontend.cc new file mode 100644 index 00000000..e0cf78d9 --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/frontend.cc @@ -0,0 +1,162 @@ +/****************************************************************************** + * to emulate the serial input and output of an 8051 controller * + * frontend.cc - the ncurses frontend * + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "frontend.hh" + +Viewer::Viewer() +{ + /* initalise the output screen */ + initscr(); + cbreak(); + noecho(); + nl(); + intrflush(stdscr,FALSE); + keypad(stdscr, TRUE); + + /* clear the screen and off you go */ + refresh(); + + // get the coordinates for the box + /* create the subwindow */ + win_c.min_x = win_c.min_y = 0; + getmaxyx(stdscr, win_c.max_y, win_c.max_x); + + /* define the boxed size */ + topleft.x = win_c.min_x + 1; + bottomright.x = win_c.max_x - 2; + topleft.y = win_c.min_y + 1; + bottomright.y = win_c.max_y - 2; + middle_y = (int)((bottomright.y-topleft.y)/2)+1; + middle_x = (int)((bottomright.x-topleft.x)/2)+1; + + // draw the two subwindows + inp_c.min_x = outp_c.min_x = topleft.x; + inp_c.max_x = outp_c.max_x = bottomright.x; + inp_c.min_y = topleft.y; + inp_c.max_y = middle_y-topleft.y; + outp_c.min_y = middle_y+1; + outp_c.max_y = bottomright.y-middle_y; + inp = subwin(stdscr, inp_c.max_y, inp_c.max_x, inp_c.min_y, inp_c.min_x); + outp = subwin(stdscr, outp_c.max_y, outp_c.max_x, outp_c.min_y,outp_c.min_x); + + // initalise the windows + touchwin(inp); + werase(inp); + wrefresh(inp); + scrollok(inp, TRUE); + + touchwin(outp); + werase(outp); + wrefresh(outp); + scrollok(outp, TRUE); + refresh(); + + nodelay(inp, TRUE); + + // flush the input buffers + flushinp(); + + move(topleft.x,topleft.y); + DrawBox(); +} + +Viewer::~Viewer() +{ + delwin(inp); + delwin(outp); + erase(); + refresh(); + endwin(); +} + +void Viewer::DrawBox(void) +{ + int height, width; + COORDINATES current; + + // save the current position + getyx(stdscr, current.y, current.x); + + height = (bottomright.y - topleft.y)+1; + width = (bottomright.x - topleft.y)+1; + + mvaddch(topleft.y-1, topleft.x-1, ACS_ULCORNER); + mvaddch(topleft.y-1, bottomright.x+1, ACS_URCORNER); + mvaddch(bottomright.y+1, bottomright.x+1, ACS_LRCORNER); + mvaddch(bottomright.y+1, topleft.x-1, ACS_LLCORNER); + + /* wmove (screen, y, x) */ + /* top */ + move(topleft.y-1, topleft.x); + hline(ACS_HLINE, width); + /* bottom */ + move(bottomright.y+1, topleft.x); + hline(ACS_HLINE, width); + move(bottomright.y+1, topleft.x); + hline(ACS_HLINE, width); + + /* left */ + move(topleft.y, topleft.x-1); + vline(ACS_VLINE, height); + + /* right */ + move(topleft.y, bottomright.x+1); + vline(ACS_VLINE, height); + + /* the divider */ + mvaddch(middle_y, bottomright.x+1, ACS_RTEE); + mvaddch(middle_y, topleft.x-1, ACS_LTEE); + hline(ACS_HLINE, width); + + // the window titles + mvaddstr(inp_c.min_y-1, middle_x-(strlen("Input")/2), "Input"); + mvaddstr(middle_y, middle_x-(strlen("Output")/2), "Output"); + move(current.y, current.x); + refresh(); +} + +void Viewer::AddStrOutWin(char *string) +{ + waddstr(outp, string); + wrefresh(outp); +} + +void Viewer::GetStrInWin(char *string) +{ + if(wgetstr(inp, string) == ERR) { + string[0] = 0; + } else { + waddstr(inp, string); + wrefresh(inp); + } +} + +void Viewer::AddChOutWin(char b) +{ + waddch(outp, b); + wrefresh(outp); +} + +char Viewer::GetChInWin(void) +{ + int b = wgetch(inp); + + if(b==ERR) { + b=0; + } else { + waddch(inp, (chtype)b); + wrefresh(inp); + } + + return((char)b); +} diff --git a/sim/ucsim/gui.src/serio.src/frontend.hh b/sim/ucsim/gui.src/serio.src/frontend.hh new file mode 100644 index 00000000..d780ac40 --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/frontend.hh @@ -0,0 +1,43 @@ +/****************************************************************************** + * to emulate the serial input and output of an 8051 controller * + * frontend.hh - ncurses frontend * + ******************************************************************************/ +#include +#include +#include +#include "config.h" + +struct COORDS_S +{ + int min_x; + int max_x; + int min_y; + int max_y; +}; +typedef struct COORDS_S COORDS; + +struct COORDINATES_S +{ + int x; + int y; +}; +typedef struct COORDINATES_S COORDINATES; + + +class Viewer +{ + public: + Viewer(); + ~Viewer(); + void DrawBox(void); + void AddStrOutWin(char *string); + void GetStrInWin(char *string); + void AddChOutWin(char b); + char GetChInWin(void); + + private: + WINDOW *inp, *outp; + COORDS win_c, inp_c, outp_c; + COORDINATES topleft, bottomright, current; + int middle_y, middle_x; +}; diff --git a/sim/ucsim/gui.src/serio.src/main.cc b/sim/ucsim/gui.src/serio.src/main.cc new file mode 100644 index 00000000..9589f5d6 --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/main.cc @@ -0,0 +1,102 @@ +/****************************************************************************** + * to emulate the serial input and output of an 8051 controller * + * main.cc - the main stuff * + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fileio.hh" +#include "frontend.hh" +#include "posix_signal.hh" + + +// globals +int doloop = 1; + +// the signal handler +void HandleSig(int info) +{ + doloop = 0; +} + + +// usage +void PrintUsage(char *progname) +{ +cout << "Usage: " << progname << " [-i ] [-o ] [-h]\n"; +cout << "-i \t is the pipe to the controllers' serial input\n"; +cout << "-o \t is the pipe to the controllers' serial output\n"; +cout << "-h\t\tshow the help\n"; +cout << "\nTim Hurman - t.hurman@virgin.net\n"; +exit(0); +} + + +// the main function +int main(int argc, char **argv) +{ + char *string = new char[MAX_SIZ]; + extern char *optarg; + int errflg=0; + char c; + char *infile = DEF_INFILE; + char *outfile = DEF_OUTFILE; + + // sort out any command line params + while ((c = getopt(argc, argv, "i:o:h")) != EOF) + switch(c) { + case 'i': + infile = optarg; + break; + case 'o': + outfile = optarg; + break; + case 'h': + errflg++; + break; + default: + cerr << "Invalid or unknown switch\n"; + errflg++; + break; + } + + // was there a problem + if(errflg) + PrintUsage(argv[0]); + + // the main objects needed + FileIO *fobj = new FileIO(infile, outfile); + Viewer *view = new Viewer(); + SigHandler *sig = new SigHandler(); + + // add a signal handler for ^C + sig->SetSignal(SIGINT, HandleSig); + + // set the timeout for waiting for a char + while(doloop) + { + string[0] = view->GetChInWin(); + if(string[0] == 4) + break; + + if(string[0] != 0) + fobj->SendByte(string[0]); + + if(fobj->RecvStr(string) > 0) + view->AddStrOutWin(string); + + usleep(5000); + } + + delete fobj; + delete view; + delete sig; + delete string; + return(0); +} diff --git a/sim/ucsim/gui.src/serio.src/posix_signal.cc b/sim/ucsim/gui.src/serio.src/posix_signal.cc new file mode 100644 index 00000000..f9baf936 --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/posix_signal.cc @@ -0,0 +1,106 @@ +/****************************************************************************** + * posix_signal.cc - A signal handleing class for linux + solaris * + * to convert posix into somthing easier to use * + * Tim Hurman - t.hurman@virgin.net * + * Last edited on 01th Oct 19999 * + ******************************************************************************/ +/* + * A quick note, fscking linux, none of this would be neccessary if + * linux contained support for sighold, sigrelse, sigignore and sigpause. + * + */ + +#include +#include +#include /* header for waitpid() and various macros */ +#include /* header for signal functions */ +#include +#include +#include +#include +#include + +#include "posix_signal.hh" + +// constructor +SigHandler::SigHandler() +{ +} + +// destructor +SigHandler::~SigHandler() +{ +} + +/* set a signal */ +int SigHandler::SetSignal(int SIGNAL, SIG_PF ACTION) +{ + struct sigaction act; + + /* declare what is going to be called when */ + act.sa_handler = ACTION; + + /* clear the structure's mask */ + sigemptyset(&act.sa_mask); + + /* set up some flags */ + if(SIGNAL == SIGCHLD) { + act.sa_flags = SA_NOCLDSTOP; + } + + /* set the signal handler */ + if(sigaction(SIGNAL, &act, NULL) < 0) + { + cerr << "sigaction(): " << strerror(errno) << "\n"; + exit(-1); + } + + /* all ok */ + return(0); +} + + +/* block a signal */ +int SigHandler::BlockSignal(int SIGNAL) +{ + sigset_t set; + + /* initalise */ + sigemptyset(&set); + + /* add the SIGNAL to the set */ + sigaddset(&set, SIGNAL); + + /* block it */ + if(sigprocmask(SIG_BLOCK, &set, NULL) < 0) + { + cerr << "sigprocmask(): " << strerror(errno) << "\n"; + exit(-1); + } + + /* done */ + return(0); +} + + +/* unblock a signal */ +int SigHandler::UnBlockSignal(int SIGNAL) +{ + sigset_t set; + + /* initalise */ + sigemptyset(&set); + + /* add the SIGNAL to the set */ + sigaddset(&set, SIGNAL); + + /* block it */ + if(sigprocmask(SIG_UNBLOCK, &set, NULL) < 0) + { + cerr << "sigprocmask(): " << strerror(errno) << "\n"; + exit(-1); + } + + /* done */ + return(0); +} diff --git a/sim/ucsim/gui.src/serio.src/posix_signal.hh b/sim/ucsim/gui.src/serio.src/posix_signal.hh new file mode 100644 index 00000000..18c0caec --- /dev/null +++ b/sim/ucsim/gui.src/serio.src/posix_signal.hh @@ -0,0 +1,19 @@ +/****************************************************************************** + * posix_signal.hh - A signal handleing class for linux + solaris * + * to convert posix into somthing easier to use * + * Tim Hurman - t.hurman@virgin.net * + * Last edited on 01th Oct 1999 * + ******************************************************************************/ +typedef void(*SIG_PF)(int); +class SigHandler +{ + public: + SigHandler(); + ~SigHandler(); + int SetSignal(int SIGNAL, SIG_PF ACTION); + int BlockSignal(int SIGNAL); + int UnBlockSignal(int SIGNAL); + + private: + +}; diff --git a/sim/ucsim/s51.src/(c).1 b/sim/ucsim/s51.src/(c).1 new file mode 100644 index 00000000..d673f9fd --- /dev/null +++ b/sim/ucsim/s51.src/(c).1 @@ -0,0 +1,25 @@ +/* + * Simulator of microcontrollers (@@F@@) + * + * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ diff --git a/sim/ucsim/s51.src/(null).cdb b/sim/ucsim/s51.src/(null).cdb new file mode 100644 index 00000000..492cf6b5 --- /dev/null +++ b/sim/ucsim/s51.src/(null).cdb @@ -0,0 +1 @@ +M:(null) diff --git a/sim/ucsim/s51.src/Makefile.in b/sim/ucsim/s51.src/Makefile.in new file mode 100644 index 00000000..f0e52e09 --- /dev/null +++ b/sim/ucsim/s51.src/Makefile.in @@ -0,0 +1,129 @@ +# +# uCsim s51.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = @CXX@ +CPP = @CPP@ +CXXCPP = @CXXCPP@ +RANLIB = @RANLIB@ +INSTALL = @INSTALL@ + +PRJDIR = .. + +DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +CPPFLAGS = @CPPFLAGS@ -I. -I$(PRJDIR) \ + -I$(PRJDIR)/cmd.src -I$(PRJDIR)/sim.src +CFLAGS = @CFLAGS@ -Wall +CXXFLAGS = @CXXFLAGS@ -Wall +M_OR_MM = @M_OR_MM@ + +SDCC = sdcc +SDCFLAGS = --debug --stack-after-data --model-small +SDCPPFLAGS = + +LIBS = @LIBS@ -L$(PRJDIR) -lutil -lsim -lcmd + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +includedir = @includedir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +srcdir = @srcdir@ + +OBJECTS = s51.o glob.o sim51.o cmd51.o \ + inc.o jmp.o mov.o logic.o arith.o bit.o \ + timer0.o timer1.o timer2.o serial.o port.o interrupt.o \ + uc51.o uc52.o uc51r.o uc89c51r.o uc251.o \ + cmd.o dump.o go.o cmd_brk.o set.o where.o show.o + + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs s51.src tests + +tests: test_ser.ihx + +test_ser.ihx: test_ser.rel + $(SDCC) $(SDCFLAGS) $< + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) -s s51 $(bindir) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(bindir)/s51 + + +# Performing self-test +# -------------------- +check: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(bindir) || $(INSTALL) -d $(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: *.cc *.h + $(CXXCPP) $(CPPFLAGS) $(M_OR_MM) *.cc >Makefile.dep + +include Makefile.dep +include clean.mk + +#parser.cc: parser.y + +#plex.cc: plex.l + +# My rules +# -------- +.SUFFIXES: .rel + +s51.src: s51 + +s51: $(OBJECTS) $(PRJDIR)/*.a + $(CXX) $(CXXFLAGS) -o s51 $(OBJECTS) $(LIBS) + +otherlibs: + cd $(PRJDIR)/cmd.src && $(MAKE) all + cd $(PRJDIR)/sim.src && $(MAKE) all + +.cc.o: + $(CXX) $(CXXFLAGS) $(CPPFLAGS) -c $< -o $@ + +.c.rel: + $(SDCC) $(SDCFLAGS) $(SDCPPFLAGS) -c $< + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(PRJDIR)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" PRJDIR="$(PRJDIR)" freshconf;\ + fi + +# End of s51.src/Makefile.in diff --git a/sim/ucsim/s51.src/arith.cc b/sim/ucsim/s51.src/arith.cc new file mode 100644 index 00000000..6df4c8f8 --- /dev/null +++ b/sim/ucsim/s51.src/arith.cc @@ -0,0 +1,535 @@ +/* + * Simulator of microcontrollers (arith.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include + +// local +#include "uc51cl.h" +#include "regs51.h" + + +/* + * 0x03 1 12 RR A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_rr(uchar code) +{ + uchar acc; + + acc= sfr->read(event_at.ws= event_at.rs= ACC); + if (acc & 0x01) + sfr->set(ACC, (acc >> 1) | 0x80); + else + sfr->set(ACC, acc >> 1); + return(resGO); +} + + +/* + * 0x13 1 12 RRC A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_rrc(uchar code) +{ + bool cy; + uchar acc; + + cy= GET_C; + SET_C((acc= sfr->read(ACC)) & 0x01); + event_at.ws= event_at.rs= ACC; + acc>>= 1; + if (cy) + acc|= 0x80; + sfr->set(ACC, acc); + return(resGO); +} + + +/* + * 0x23 1 12 RL A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_rl(uchar code) +{ + uchar acc; + + acc= sfr->read(event_at.ws= event_at.rs= ACC); + if (acc & 0x80) + sfr->set(ACC, (acc << 1 ) | 0x01); + else + sfr->set(ACC, acc << 1); + return(resGO); +} + + +/* + * 0x24 2 12 ADD A,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_add_a_$data(uchar code) +{ + uchar data, acc; + bool newC, newA, c6; + + data= fetch(); + acc = sfr->get(ACC); + newC= (((uint)acc+(uint)(data)) > 255)?0x80:0; + newA= ((acc&0x0f)+(data&0x0f)) & 0xf0; + c6 = ((acc&0x7f)+(data&0x7f)) & 0x80; + event_at.ws= ACC; + sfr->set(ACC, acc+data); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(resGO); +} + + +/* + * 0x25 2 12 ADD A,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_add_a_addr(uchar code) +{ + uchar data, acc; + bool newC, newA, c6; + + data= read(get_direct(fetch(), &event_at.ri, &event_at.rs)); + acc = sfr->get(ACC); + newC= (((uint)acc+(uint)(data)) > 255)?0x80:0; + newA= ((acc&0x0f)+(data&0x0f)) & 0xf0; + c6 = ((acc&0x7f)+(data&0x7f)) & 0x80; + event_at.ws= ACC; + sfr->set(ACC, acc+data); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(resGO); +} + + +/* + * 0x26-0x27 1 12 ADD A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_add_a_$ri(uchar code) +{ + uchar data, *addr, acc; + bool newC, newA, c6; + int res; + + addr= get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + acc = sfr->get(ACC); + data= *addr; + newC= (((uint)acc+(uint)data) > 255)?0x80:0; + newA= ((acc&0x0f)+(data&0x0f)) & 0xf0; + c6 = ((acc&0x7f)+(data&0x7f)) & 0x80; + event_at.ws= ACC; + sfr->set(ACC, acc+data); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(res); +} + + +/* + * 0x28-0x2f 1 12 ADD A,Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_add_a_rn(uchar code) +{ + uchar data, acc; + bool newC, newA, c6; + + data= *(get_reg(code & 0x07, &event_at.ri)); + acc = sfr->get(ACC); + newC= (((uint)acc+(uint)data) > 255)?0x80:0; + newA= ((acc&0x0f)+(data&0x0f)) & 0xf0; + c6 = ((acc&0x7f)+(data&0x7f)) & 0x80; + event_at.ws= ACC; + sfr->set(ACC, acc+data); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(resGO); +} + + +/* + * 0x33 1 12 RLC A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_rlc(uchar code) +{ + bool cy; + uchar acc; + + cy= GET_C; + SET_C((acc= sfr->get(event_at.rs= ACC)) & 0x80); + acc<<= 1; + if (cy) + acc|= 0x01; + sfr->set(event_at.ws= ACC, acc); + return(resGO); +} + + +/* + * 0x34 2 12 ADDC A,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_addc_a_$data(uchar code) +{ + uchar data, acc; + bool orgC, newC, newA, c6; + + data= fetch(); + acc = sfr->get(ACC); + newC= (((uint)acc+(uint)data+((orgC= GET_C)?1:0)) > 255)?0x80:0; + newA= ((acc&0x0f)+(data&0x0f)+(orgC?1:0)) & 0xf0; + c6 = ((acc&0x7f)+(data&0x7f)+(orgC?1:0)) & 0x80; + sfr->set(event_at.ws= ACC, acc + data + (orgC?1:0)); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(resGO); +} + + +/* + * 0x35 2 12 ADDC A,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_addc_a_addr(uchar code) +{ + uchar data, acc; + bool orgC, newC, newA, c6; + + data= read(get_direct(fetch(), &event_at.ri, &event_at.rs)); + acc = sfr->get(ACC); + newC= (((uint)acc+(uint)data+((orgC= GET_C)?1:0)) > 255)?0x80:0; + newA= ((acc&0x0f)+(data&0x0f)+(orgC?1:0)) & 0xf0; + c6 = ((acc&0x7f)+(data&0x7f)+(orgC?1:0)) & 0x80; + sfr->set(event_at.ws= ACC, acc + data + (orgC?1:0)); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(resGO); +} + + +/* + * 0x36-0x37 1 12 ADDC A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_addc_a_$ri(uchar code) +{ + uchar data, *addr, acc; + bool orgC, newC, newA, c6; + int res; + + addr= get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + acc = sfr->get(ACC); + data= *addr; + newC= (((uint)acc+(uint)data+((orgC= GET_C)?1:0)) > 255)?0x80:0; + newA= ((acc&0x0f)+(data&0x0f)+(orgC?1:0)) & 0xf0; + c6 = ((acc&0x7f)+(data&0x7f)+(orgC?1:0)) & 0x80; + sfr->set(event_at.ws= ACC, acc + data + (orgC?1:0)); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(res); +} + + +/* + * 0x38-0x3f 1 12 ADDC A,Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_addc_a_rn(uchar code) +{ + uchar data, acc; + bool orgC, newC, newA, c6; + + data= *(get_reg(code & 0x07, &event_at.ri)); + acc = sfr->get(ACC); + newC= (((uint)acc+(uint)data+((orgC= GET_C)?1:0)) > 255)?0x80:0; + newA= ((acc&0x0f)+(data&0x0f)+(orgC?1:0)) & 0xf0; + c6 = ((acc&0x7f)+(data&0x7f)+(orgC?1:0)) & 0x80; + sfr->set(event_at.ws= ACC, acc + data + (orgC?1:0)); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(resGO); +} + + +/* + * 0x84 1 48 DIV AB + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_div_ab(uchar code) +{ + uchar temp, psw, b, acc; + + psw= sfr->get(PSW); + psw&= ~bmCY; + if (!(b= sfr->get(event_at.rs= B))) + psw|= bmOV; + else + { + psw&= ~bmOV; + temp= (acc= sfr->get(ACC)) / b; + sfr->set(B, acc % b); + sfr->set(event_at.ws= ACC, temp); + } + sfr->set(PSW, psw); + tick(3); + return(resGO); +} + + +/* + * 0x94 2 12 SUBB A,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_subb_a_$data(uchar code) +{ + uchar data, d, acc; + bool newC, newA, c6; + + data= fetch(); + acc = sfr->get(ACC); + d= ~data + (GET_C?0:1); + newC= (acc < data+(GET_C?1:0))?0x80:0; + newA= !(((acc&0x0f)+(d&0x0f)) & 0xf0); + c6 = (((acc&0x7f)+(d&0x7f)) & 0x80)?0:0x80; + acc-= data; + if (GET_C) + acc--; + sfr->set(event_at.ws= ACC, acc); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(resGO); +} + + +/* + * 0x95 2 12 SUBB A,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_subb_a_addr(uchar code) +{ + uchar *addr, data, d, acc; + bool newC, newA, c6; + + addr= get_direct(fetch(), &event_at.ri, &event_at.rs); + acc = sfr->get(ACC); + data= read(addr); + d= ~data + (GET_C?0:1); + newC= (acc < data+(GET_C?1:0))?0x80:0; + newA= !(((acc&0x0f)+(d&0x0f)) & 0xf0); + c6 = (((acc&0x7f)+(d&0x7f)) & 0x80)?0:0x80; + acc-= data; + event_at.ws= ACC; + if (GET_C) + acc--; + sfr->set(ACC, acc); + SET_C(newC); + SET_BIT(newC ^ c6, PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(resGO); +} + + +/* + * 0x96-0x97 1 12 SUBB A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_subb_a_$ri(uchar code) +{ + uchar data, d, acc; + bool newC, newA, c6; + int res; + + data= *(get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res)); + acc = sfr->get(ACC); + d= ~data + (GET_C?0:1); + newC= (acc < data+(GET_C?1:0))?0x80:0; + newA= !(((acc&0x0f)+(d&0x0f)) & 0xf0); + c6 = (((acc&0x7f)+(d&0x7f)) & 0x80)?0:0x80; + acc-= data; + event_at.ws= ACC; + if (GET_C) + acc--; + sfr->set(ACC, acc); + SET_C(newC); + SET_BIT(newC ^ (acc & 0x80), PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(res); +} + + +/* + * 0x98-0x9f 1 12 SUBB A,Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_subb_a_rn(uchar code) +{ + uchar data, d, acc; + bool newC, newA, c6; + + data= *(get_reg(code & 0x07, &event_at.ri)); + acc = sfr->get(ACC); + d= ~data + (GET_C?0:1); + newC= (acc < data+(GET_C?1:0))?0x80:0; + newA= !(((acc&0x0f)+(d&0x0f)) & 0xf0); + c6 = (((acc&0x7f)+(d&0x7f)) & 0x80)?0:0x80; + acc-= data; + event_at.ws= ACC; + if (GET_C) + acc--; + sfr->set(ACC, acc); + SET_C(newC); + SET_BIT(newC ^ (acc & 0x80), PSW, bmOV); + SET_BIT(newA, PSW, bmAC); + return(resGO); +} + + +/* + * 0xa4 1 48 MUL AB + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mul_ab(uchar code) +{ + uint temp, psw, acc, b; + + psw= sfr->get(PSW); + psw&= ~bmCY; + temp= (acc= sfr->get(ACC)) * (b= sfr->get(B)); + sfr->set(event_at.ws= ACC, temp & 0xff); + sfr->set(event_at.rs= B, (temp >> 8) & 0xff); + SET_BIT(sfr->get(B), PSW, bmOV); + tick(3); + return(resGO); +} + + +/* + * 0xd4 1 12 DA A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_da_a(uchar code) +{ + uchar acc, psw; + + acc= sfr->get(ACC); + psw= sfr->get(PSW); + event_at.ws= ACC; + if ((acc & 0x0f) > 9 || + (psw & bmAC)) + { + if (((uint)acc+(uint)0x06) > 255) + psw|= bmCY; + acc+= 0x06; + } + if ((acc & 0xf0) > 0x90 || + (psw & bmCY)) + { + if (((uint)acc+(uint)0x60) > 255) + psw|= bmCY; + acc+= 0x60; + } + sfr->set(ACC, acc); + sfr->set(PSW, psw); + return(resGO); +} + + +/* End of s51.src/arith.cc */ diff --git a/sim/ucsim/s51.src/bit.cc b/sim/ucsim/s51.src/bit.cc new file mode 100644 index 00000000..4d7e44cb --- /dev/null +++ b/sim/ucsim/s51.src/bit.cc @@ -0,0 +1,235 @@ +/* + * Simulator of microcontrollers (bit.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "uc51cl.h" +#include "regs51.h" + + +/* + * 0x72 2 24 ORL C,bit + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_orl_c_bit(uchar code) +{ + uchar *addr, bitaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.ri, &event_at.rs); + SET_C(GET_C || + (read(addr) & BIT_MASK(bitaddr))); + event_at.ws= PSW; + tick(1); + return(resGO); +} + + +/* + * 0x82 2 24 ANL C,bit + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_anl_c_bit(uchar code) +{ + uchar *addr, bitaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.ri, &event_at.rs); + SET_C(GET_C && + (read(addr) & BIT_MASK(bitaddr))); + event_at.ws= PSW; + tick(1); + return(resGO); +} + + +/* + * 0x92 2 24 MOV bit,C + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_bit_c(uchar code) +{ + uchar *addr, bitaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.wi, &event_at.ws); + if (GET_C) + (*addr)|= BIT_MASK(bitaddr); + else + (*addr)&= ~BIT_MASK(bitaddr); + event_at.rs= PSW; + proc_write(addr); + tick(1); + return(resGO); +} + + +/* + * 0xa2 2 12 MOV C,bit + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_c_bit(uchar code) +{ + uchar *addr, bitaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.ri, &event_at.rs); + SET_C(read(addr) & BIT_MASK(bitaddr)); + event_at.ws= PSW; + return(resGO); +} + + +/* + * 0xb0 2 24 ANL C,/bit + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_anl_c_$bit(uchar code) +{ + uchar *addr, bitaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.ri, &event_at.rs); + SET_C(GET_C && + !(read(addr) & BIT_MASK(bitaddr))); + event_at.ws= PSW; + tick(1); + return(resGO); +} + + +/* + * 0xb2 2 12 CPL bit + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_cpl_bit(uchar code) +{ + uchar *addr, bitaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.wi, &event_at.ws); + (*addr)^= BIT_MASK(bitaddr); + proc_write(addr); + return(resGO); +} + + +/* + * 0xb3 1 12 CPL C + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_cpl_c(uchar code) +{ + sfr->set(PSW, sfr->get(PSW) ^ bmCY); + event_at.ws= PSW; + return(resGO); +} + + +/* + * 0xc2 2 12 CLR bit + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_clr_bit(uchar code) +{ + uchar *addr, bitaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.wi, &event_at.ws); + (*addr)&= ~BIT_MASK(bitaddr); + proc_write(addr); + return(resGO); +} + + +/* + * 0xc3 1 12 CLR C + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_clr_c(uchar code) +{ + sfr->set(PSW, sfr->get(PSW) & ~bmCY); + event_at.ws= PSW; + return(resGO); +} + + +/* + * 0xd2 2 12 SETB bit + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_setb_bit(uchar code) +{ + uchar *addr, bitaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.wi, &event_at.ws); + (*addr)|= BIT_MASK(bitaddr); + proc_write(addr); + return(resGO); +} + + +/* + * 0xd3 1 12 SETB C + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_setb_c(uchar code) +{ + sfr->set(PSW, sfr->get(PSW) | bmCY); + event_at.ws= PSW; + return(resGO); +} + + +/* End of s51.src/bit.cc */ diff --git a/sim/ucsim/s51.src/clean.mk b/sim/ucsim/s51.src/clean.mk new file mode 100644 index 00000000..31cf1bff --- /dev/null +++ b/sim/ucsim/s51.src/clean.mk @@ -0,0 +1,29 @@ +# uCsim s51.src/clean.mk + +# Deleting all files created by building the program +# -------------------------------------------------- +clean: + rm -f *core *[%~] *.[oa] + rm -f test_*.??* + rm -f .[a-z]*~ + rm -f s51 + + +# Deleting all files created by configuring or building the program +# ----------------------------------------------------------------- +distclean: clean + rm -f config.cache config.log config.status + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean + +# End of s51.src/clean.mk diff --git a/sim/ucsim/s51.src/cmd.cc b/sim/ucsim/s51.src/cmd.cc new file mode 100644 index 00000000..9e224981 --- /dev/null +++ b/sim/ucsim/s51.src/cmd.cc @@ -0,0 +1,244 @@ +/* + * Simulator of microcontrollers (cmd.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include +#include "i_string.h" + +#include "uccl.h" +#include "globals.h" + +#include "dump.h" +#include "go.h" +#include "cmd_brk.h" +#include "set.h" +#include "where.h" +#include "optioncl.h" +#include "show.h" + +#include "cmd.h" + + +/* Table is defined at the end of this file */ + + +/* + * HELP + */ + +static bool +cmd_help(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + int i; + + i= 0; + while (cmd_table[i].name != NULL) + { + if (cmd_table[i].help != NULL) + sim->cmd->printf("%s\n", cmd_table[i].help); + i++; + } + sim->cmd->printf("----\nSet of new commands:\n"); + for (i= 0; i < sim->cmdset->count; i++) + { + class cl_cmd *cmd= (class cl_cmd *)(sim->cmdset->at(i)); + sim->cmd->printf("%s\n", cmd->short_help); + } + return(FALSE); +} + + +/* + * GET OPTION [opt] + */ + +static bool +cmd_get_option(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + char *s; + int i; + class cl_option *o; + + s= strtok(NULL, delimiters); + for (i= 0; i < uc->options->count; i++) + { + o= (class cl_option *)(uc->options->at(i)); + if (!s || + !strcmp(s, o->id)) + { + fprintf(sim->cmd_out(), "%s ", o->id); + o->print(sim->cmd_out()); + fprintf(sim->cmd_out(), " %s\n", o->help); + } + } + return(FALSE); +} + + +/* + * SET OPTION opt value + */ + +static bool +cmd_set_option(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + char *s, *id; + int i; + class cl_option *o; + + if ((id= strtok(NULL, delimiters)) == NULL) + { + fprintf(sim->cmd_out(), "Name of option has not given.\n"); + return(FALSE); + } + if ((s= strtok(NULL, delimiters)) == NULL) + { + fprintf(sim->cmd_out(), "Value has not given.\n"); + return(FALSE); + } + for (i= 0; i < uc->options->count; i++) + { + o= (class cl_option *)(uc->options->at(i)); + if (!strcmp(id, o->id)) + { + o->set_value(s); + break; + } + } + return(FALSE); +} + + +/* + * Table of commands and their names + */ + +struct cmd_entry cmd_table[]= +{ + {"g" , cmd_go, FALSE, + "g [start [stop]] Go"}, + + {"stop", cmd_stop, FALSE, + "stop Stop"}, + + {"pc", cmd_pc, FALSE, + "pc [address] Get/set content of PC"}, + + {"s" , cmd_step, TRUE, + "s [step] Step"}, + + {"n" , cmd_next, TRUE, + "n [step] Next"}, + + {"bse", cmd_brk_sete, FALSE, + "bse wi|ri|wx|rx|ws|rs|rc f|d addr [hit]\n" + " Set EVENT Breakpoint"}, + + {"bde", cmd_brk_dele, FALSE, + "bde wi|ri|wx|rx|ws|rs|rc addr\n" + " Delete EVENT Breakpoint"}, + + {"ba", cmd_brk_delall, FALSE, + "ba Delete all breakpoints"}, + + {"dis", cmd_disass, TRUE, + "dis [start [offset [lines]]]\n" + " Disassemble code"}, + + {"dp", cmd_dump_port, FALSE, + "dp Dump ports"}, + + {"ds", cmd_dump_sfr, FALSE, + "ds [addr...] Dump SFR"}, + + {"db", cmd_dump_bit, TRUE, + "db addr... Dump bit"}, + + {"si", cmd_set_iram, FALSE, + "si addr data... Set Internal RAM"}, + + {"sx", cmd_set_xram, FALSE, + "sx addr data... Set External RAM"}, + + {"sc", cmd_set_code, FALSE, + "sc addr data... Set code (ROM)"}, + + {"ss", cmd_set_sfr, FALSE, + "ss addr data... Set SFR area"}, + + {"sb", cmd_set_bit, FALSE, + "sb addr data... Set bit"}, + + {"sp", cmd_set_port, FALSE, + "sp port data Set port pins"}, + + {"fi", cmd_fill_iram, FALSE, + "fi start stop data Fill IRAM area with `data'"}, + + {"fx", cmd_fill_xram, FALSE, + "fx start stop data Fill XRAM area with `data'"}, + + {"fs", cmd_fill_sfr, FALSE, + "fs start stop data Fill SFR area with `data'"}, + + {"fc", cmd_fill_code, FALSE, + "fc start stop data Fill ROM area with `data'"}, + + {"wi", cmd_where_iram, FALSE, + "wi,Wi string Search for `string' in IRAM (Wi case sensitive)"}, + {"Wi", cmd_Where_iram, FALSE, NULL}, + + {"wx", cmd_where_xram, FALSE, + "wx,Wx string Search for `string' in XRAM (Wx case sensitive)"}, + {"Wx", cmd_Where_xram, FALSE, NULL}, + + {"wc", cmd_where_code, FALSE, + "wc,Wc string Search for `string' in ROM (Wc case sensitive)"}, + {"Wc", cmd_Where_code, FALSE, NULL}, + + {"sopt", cmd_set_option, FALSE, + "sopt opt value Set value of option"}, + + {"gopt", cmd_get_option, FALSE, + "gopt [opt] Get value of option(s)"}, + + {"show", cmd_show, FALSE, + "show c|w Show licensing information"}, + + {"h" , cmd_help, FALSE, + "h,? Help about commands"}, + {"?" , cmd_help, FALSE, NULL}, + + {NULL, NULL} +}; + + +/* End of s51.src/cmd.cc */ diff --git a/sim/ucsim/s51.src/cmd.h b/sim/ucsim/s51.src/cmd.h new file mode 100644 index 00000000..2833eb0c --- /dev/null +++ b/sim/ucsim/s51.src/cmd.h @@ -0,0 +1,55 @@ +/* + * Simulator of microcontrollers (cmd.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef CMD_HEADER +#define CMD_HEADER + +#include "ddconfig.h" + +#include + + +/* Type of entries in command table */ + +struct cmd_entry +{ + // Name of the command + char *name; + // Function to execute + bool (*func)(char *cmd, /*class t_uc51*/void *uc, class cl_sim *sim); + // Command can be repeated by empty command + bool can_repeat; + // Help about the command + char *help; +}; + +extern struct cmd_entry cmd_table[]; + + +#endif + +/* End of s51.src/cmd.h */ diff --git a/sim/ucsim/s51.src/cmd51.cc b/sim/ucsim/s51.src/cmd51.cc new file mode 100644 index 00000000..b79d9983 --- /dev/null +++ b/sim/ucsim/s51.src/cmd51.cc @@ -0,0 +1,157 @@ +/* + * Simulator of microcontrollers (cmd51.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include "i_string.h" + +#include "globals.h" + +#include "cmd51cl.h" + + +/* + * Special console for s51 it uses old version of the command interpreter + */ + +cl_51cons::cl_51cons(char *fin, char *fout, class cl_sim *asim): + cl_console(fin, fout, asim) +{} + +cl_51cons::cl_51cons(FILE *fin, FILE *fout, class cl_sim *asim): + cl_console(fin, fout, asim) +{} + +#ifdef SOCKET_AVAIL +cl_51cons::cl_51cons(int portnumber, class cl_sim *asim): + cl_console(portnumber, asim) +{} +#endif + +int +cl_51cons::proc_input(void) +{ + return(cl_console::proc_input()); + /*char *cmd= read_line(); + if (!cmd) + return(1); + int retval= interpret(cmd); + prompt(); + free(cmd); + return(retval);*/ +} + +bool +cl_51cons::interpret(char *cmd) +{ + int i; + char *c, *s; + bool repeat= FALSE, retval= FALSE; + + if (*cmd) + { + c= strdup(cmd); + if (last_command) + free(last_command); + last_command= strdup(cmd); + } + else + if (last_command == NULL) + return(FALSE); + else + { + c= strdup(last_command); + repeat= TRUE; + } + i= 0; + s= strtok(c, delimiters); + while ((cmd_table[i].name != NULL) && + /*(strstr(c, cmd_table[i].name) != c)*/ + (strcmp(s, cmd_table[i].name) != 0)) + i++; + if (cmd_table[i].name == NULL) + { + fprintf(sim->cmd_out(), "Unknown command.\n"); + if (last_command) + { + free(last_command); + last_command= NULL; + } + } + else + { + if (!repeat) + retval= cmd_table[i].func(c, sim->uc, sim); + else + if (cmd_table[i].can_repeat) + retval= cmd_table[i].func(c, sim->uc, sim); + } + free(c); + return(retval); +} + +bool +cl_51cons::old_command(class cl_cmdline *cmdline) +{ + int i= 0; + + if (cmdline->name == 0 || + *(cmdline->name) == '\0' || + *(cmdline->name) == '\n') + return(TRUE); + while ((cmd_table[i].name != NULL) && + /*(strstr(c, cmd_table[i].name) != c)*/ + (strcmp(cmdline->name, cmd_table[i].name) != 0)) + i++; + return(cmd_table[i].name != NULL); +} + + +/* + * Special commander for s51 it uses special console + */ + +cl_51cmd::cl_51cmd(class cl_sim *asim): + cl_commander(asim) +{} + +class cl_console * +cl_51cmd::mk_console(char *fin, char *fout, class cl_sim *asim) +{ + return(new cl_51cons(fin, fout, asim)); +} + +class cl_console * +cl_51cmd::mk_console(FILE *fin, FILE *fout, class cl_sim *asim) +{ + return(new cl_51cons(fin, fout, asim)); +} + + +/* End of s51.src/cmd51.cc */ diff --git a/sim/ucsim/s51.src/cmd51cl.h b/sim/ucsim/s51.src/cmd51cl.h new file mode 100644 index 00000000..21cdd351 --- /dev/null +++ b/sim/ucsim/s51.src/cmd51cl.h @@ -0,0 +1,67 @@ +/* + * Simulator of microcontrollers (cmd51cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef CMD51CL_HEADER +#define CMD51CL_HEADER + +#include "ddconfig.h" + +// cmd +#include "newcmdcl.h" + +// local +#include "cmd.h" +#include "simcl.h" + + +class cl_51cons: public cl_console +{ +public: + cl_51cons(char *fin, char *fout, class cl_sim *asim); + cl_51cons(FILE *fin, FILE *fout, class cl_sim *asim); +#ifdef SOCKET_AVAIL + cl_51cons(int portnumber, class cl_sim *asim); +#endif + virtual int proc_input(void); + virtual bool interpret(char *cmd); + virtual bool old_command(class cl_cmdline *cmdline); +}; + +class cl_51cmd: public cl_commander +{ +public: + cl_51cmd(class cl_sim *asim); + virtual class cl_console *mk_console(char *fin, char *fout, + class cl_sim *asim); + virtual class cl_console *mk_console(FILE *fin, FILE *fout, + class cl_sim *asim); +}; + + +#endif + +/* End of s51.src/cmd51cl.h */ diff --git a/sim/ucsim/s51.src/cmd_brk.cc b/sim/ucsim/s51.src/cmd_brk.cc new file mode 100644 index 00000000..1c7e49cc --- /dev/null +++ b/sim/ucsim/s51.src/cmd_brk.cc @@ -0,0 +1,264 @@ +/* + * Simulator of microcontrollers (cmd_brk.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include "i_string.h" + +#include "simcl.h" + +#include "uc51cl.h" //FIXME +#include "globals.h" + + +/* + * BREAKPOINT SET f|d addr [hit] + */ +//FIXME +/*bool +cmd_brk_setf(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + char *s; + uint addr; + int hit= 1; + enum brk_perm perm; + class cl_brk *b; + + if ((s= strtok(NULL, delimiters)) == NULL) + { + sim->cmd->printf("Permanency has not given\n"); + return(FALSE); + } + switch (*s) + { + case 'f': case 'F': + perm= brkFIX; + break; + case 'd': case 'D': + perm= brkDYNAMIC; + break; + default: + sim->cmd->printf("Unknow permanency\n"); + return(FALSE); + } + if ((s= strtok(NULL, delimiters)) == NULL) + { + sim->cmd->printf("Address has not given\n"); + return(FALSE); + } + addr= (uint)strtol(s, NULL, 0); + if ((s= strtok(NULL, delimiters)) != NULL) + hit= strtol(s, NULL, 0); + if (uc->fbrk_at(addr)) + sim->cmd->printf("Breakpoint at %06x is already set.\n", addr); + else + { + b= new cl_fetch_brk(addr, perm, hit); + uc->fbrk->add_bp(b); + } + return(FALSE); +} +*/ + +/* + * BREAKPOINT SET EVENT wi|ri|wx|rx|ws|rs|rc f|d addr [hit] + */ +//FIXME +bool +cmd_brk_sete(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + char *s; + char *id; + uint addr; + int hit= 1; + enum brk_perm perm; + class cl_ev_brk *b= NULL; + + if ((id= strtok(NULL, delimiters)) == NULL) + { + sim->cmd->printf("Event has not given.\n"); + return(FALSE); + } + if ((s= strtok(NULL, delimiters)) == NULL) + { + sim->cmd->printf("Permanency has not given\n"); + return(FALSE); + } + switch (*s) + { + case 'f': case 'F': + perm= brkFIX; + break; + case 'd': case 'D': + perm= brkDYNAMIC; + break; + default: + sim->cmd->printf("Unknow permanency\n"); + return(FALSE); + } + if ((s= strtok(NULL, delimiters)) == NULL) + { + sim->cmd->printf("Address has not given\n"); + return(FALSE); + } + addr= (uint)strtol(s, NULL, 0); + if ((s= strtok(NULL, delimiters)) != NULL) + hit= strtol(s, NULL, 0); + else + { + if (!strcmp(id, "wi")) + b= new cl_wi_brk(uc->ebrk->make_new_nr(), addr, perm, hit); + else if (!strcmp(id, "ri")) + b= new cl_ri_brk(uc->ebrk->make_new_nr(), addr, perm, hit); + else if (!strcmp(id, "wx")) + b= new cl_wx_brk(uc->ebrk->make_new_nr(), addr, perm, hit); + else if (!strcmp(id, "rx")) + b= new cl_rx_brk(uc->ebrk->make_new_nr(), addr, perm, hit); + else if (!strcmp(id, "ws")) + b= new cl_ws_brk(uc->ebrk->make_new_nr(), addr, perm, hit); + else if (!strcmp(id, "rs")) + b= new cl_rs_brk(uc->ebrk->make_new_nr(), addr, perm, hit); + else if (!strcmp(id, "rc")) + b= new cl_rc_brk(uc->ebrk->make_new_nr(), addr, perm, hit); + else + sim->cmd->printf("Event %s is unknown.\n", id); + if (b) + uc->ebrk->add_bp(b); + } + return(FALSE); +} + + +/* + * BREAKPOINT DELETE addr + */ +//FIXME +/*bool +cmd_brk_delf(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + uint addr; + char *s; + + if ((s= strtok(NULL, delimiters)) == NULL) + sim->cmd->printf("Address has not given.\n"); + else + { + addr= (uint)strtol(s, NULL, 0); + if (uc->fbrk_at(addr) == NULL) + sim->cmd->printf("No breakpoint at %06x\n", addr); + else + uc->fbrk->del_bp(addr); + } + return(FALSE); +}*/ + + +/* + * BREAKPOINT DELETE EVENT wi|ri|wx|rx|ws|rs|rc addr + */ +//FIXME +bool +cmd_brk_dele(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + uint addr; + char *s, *id; + + if ((id= strtok(NULL, delimiters)) == NULL) + { + fprintf(sim->cmd_out(), "Event has not given.\n"); + return(FALSE); + } + if ((s= strtok(NULL, delimiters)) == NULL) + fprintf(sim->cmd_out(), "Address has not given.\n"); + else + { + addr= (uint)strtol(s, NULL, 0); + if (uc->ebrk_at(addr, id) == NULL) + fprintf(sim->cmd_out(), "No %s breakpoint at %06x\n", id, addr); + else + uc->rm_ebrk(addr, id); + } + return(FALSE); +} + + +/* + * BREAKPOINT DELETE ALL + */ +//FIXME +bool +cmd_brk_delall(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + while (uc->fbrk->count) + { + class cl_brk *brk= (class cl_brk *)(uc->fbrk->at(0)); + uc->fbrk->del_bp(brk->addr); + } + while (uc->ebrk->count) + uc->ebrk->free_at(0); + return(FALSE); +} + + +/* + * BREAKPOINT LIST + */ +//FIXME +/*bool +cmd_brk_lst(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + class cl_fetch_brk *fb; + class cl_ev_brk *eb; + int i; + char *s; + + for (i= 0; i < uc->fbrk->count; i++) + { + fb= (class cl_fetch_brk *)(uc->fbrk->at(i)); + s = uc->disass(fb->addr, NULL); + fprintf(sim->cmd_out(), "%c %d(%d) %06x %02x %s\n", + (fb->perm==brkFIX)?'F':'D', + fb->hit, fb->cnt, + fb->addr, uc->get_mem(MEM_ROM, fb->addr), s); + free(s); + } + for (i= 0; i < uc->ebrk->count; i++) + { + eb= (class cl_ev_brk *)(uc->ebrk->at(i)); + fprintf(sim->cmd_out(), "%c %d(%d) %06x %s\n", + (eb->perm==brkFIX)?'F':'D', + eb->hit, eb->cnt, + eb->addr, eb->id); + } + return(FALSE); +}*/ + + +/* End of s51.src/cmd_brk.cc */ diff --git a/sim/ucsim/s51.src/cmd_brk.h b/sim/ucsim/s51.src/cmd_brk.h new file mode 100644 index 00000000..d737b2db --- /dev/null +++ b/sim/ucsim/s51.src/cmd_brk.h @@ -0,0 +1,44 @@ +/* + * Simulator of microcontrollers (cmd_brk.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef CMD_BRK_HEADER +#define CMD_BRK_HEADER + +#include "ddconfig.h" + + +//extern bool cmd_brk_setf(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_brk_sete(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_brk_delf(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_brk_dele(char *cmd, class t_uc51 *uc, class cl_sim *sim); +//extern bool cmd_brk_lst(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_brk_delall(char *cmd, class t_uc51 *uc, class cl_sim *sim); + + +#endif + +/* End of s51.src/cmd_brk.h */ diff --git a/sim/ucsim/s51.src/conf.mk b/sim/ucsim/s51.src/conf.mk new file mode 100644 index 00000000..3f6e75a5 --- /dev/null +++ b/sim/ucsim/s51.src/conf.mk @@ -0,0 +1,11 @@ +# uCsim s51.src/conf.mk +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(PRJDIR)/configure.in + cd $(PRJDIR) && $(SHELL) ./config.status + +# End of s51.src/conf.mk diff --git a/sim/ucsim/s51.src/debugger b/sim/ucsim/s51.src/debugger new file mode 100755 index 00000000..4a30ac90 --- /dev/null +++ b/sim/ucsim/s51.src/debugger @@ -0,0 +1 @@ +sdcdb -s /dev/ttyp1 "$@" diff --git a/sim/ucsim/s51.src/dump.cc b/sim/ucsim/s51.src/dump.cc new file mode 100644 index 00000000..1a1af360 --- /dev/null +++ b/sim/ucsim/s51.src/dump.cc @@ -0,0 +1,282 @@ +/* + * Simulator of microcontrollers (dump.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include "i_string.h" + +#include "simcl.h" + +#include "uc51cl.h" //FIXME +#include "regs51.h" //FIXME +#include "globals.h" +#include "cmdutil.h" + + +/* + * Dump memory + */ + +void +dump_memory(cl_mem *mem, + t_addr *start, t_addr stop, int bpl, FILE *f, + class cl_sim *sim) +{ + int i; + + while ((*start <= stop) && + (*start < mem->size)) + { + sim->cmd->printf("%06x ", *start); + for (i= 0; (i < bpl) && + (*start+i < mem->size) && + (*start+i <= stop); + i++) + { + char format[10]; + sprintf(format, "%%0%dx ", mem->width/4); + fprintf(f, format/*"%02x "*/, mem->get(*start+i)); + } + while (i < bpl) + { + fprintf(f, " "); + i++; + } + for (i= 0; (i < bpl) && + (*start+i < mem->size) && + (*start+i <= stop); + i++) + fprintf(f, "%c", + isprint(mem->get(*start+i))?(char)mem->get(*start+i):'.'); + fprintf(f, "\n"); + (*start)+= bpl; + } +} + + +/* + * DISASSEMBLE [start [offset [lines]]] + */ +//FIXME +static int disass_last_stop= 0; + +bool +cmd_disass(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + char *s; + int start, offset= -1, dir; + int lines= 20; + uint realstart; + + if (!uc->there_is_inst()) + return(FALSE); + if ((s= strtok(NULL, delimiters)) != NULL) + start= strtol(s, NULL, 0); + else + start= disass_last_stop; + if ((s= strtok(NULL, delimiters)) != NULL) + offset= strtol(s, NULL, 0); + if ((s= strtok(NULL, delimiters)) != NULL) + lines= strtol(s, NULL, 0); + + realstart= start; + while (!uc->inst_at(realstart)) + realstart= (realstart+1) & (EROM_SIZE-1); + if (offset) + { + dir= (offset < 0)?-1:+1; + while (offset) + { + realstart= (realstart+dir) & (EROM_SIZE-1); + while (!uc->inst_at(realstart)) + realstart= (realstart+dir) & (EROM_SIZE-1); + offset+= -dir; + } + } + + while (lines) + { + uc->print_disass(realstart, sim->cmd->actual_console); + realstart= (realstart+1) & (EROM_SIZE-1); + while (!uc->inst_at(realstart)) + realstart= (realstart+1) & (EROM_SIZE-1); + lines--; + } + + disass_last_stop= realstart; + return(FALSE); +} + + +/* + * DUMP PORTS + */ +//FIXME +bool +cmd_dump_port(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + uchar data; + + data= uc->get_mem(MEM_SFR, P0); + sim->cmd->printf("P0 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c", data, data, isprint(data)?data:'.'); + + data= uc->get_mem(MEM_SFR, P1); + sim->cmd->printf(" P1 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c\n", data, data, isprint(data)?data:'.'); + + data= uc->port_pins[0]; + sim->cmd->printf("Pin0 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c", data, data, isprint(data)?data:'.'); + + data= uc->port_pins[1]; + sim->cmd->printf(" Pin1 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c\n", data, data, isprint(data)?data:'.'); + + data= uc->port_pins[0] & uc->get_mem(MEM_SFR, P0); + sim->cmd->printf("Port0 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c", data, data, isprint(data)?data:'.'); + + data= uc->port_pins[1] & uc->get_mem(MEM_SFR, P1); + sim->cmd->printf(" Port1 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c\n", data, data, isprint(data)?data:'.'); + + sim->cmd->printf("\n"); + + data= uc->get_mem(MEM_SFR, P2); + sim->cmd->printf("P2 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c", data, data, isprint(data)?data:'.'); + + data= uc->get_mem(MEM_SFR, P3); + sim->cmd->printf(" P3 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c\n", data, data, isprint(data)?data:'.'); + + data= uc->port_pins[2]; + sim->cmd->printf("Pin2 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c", data, data, isprint(data)?data:'.'); + + data= uc->port_pins[3]; + sim->cmd->printf(" Pin3 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c\n", data, data, isprint(data)?data:'.'); + + data= uc->port_pins[2] & uc->get_mem(MEM_SFR, P2); + sim->cmd->printf("Port2 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c", data, data, isprint(data)?data:'.'); + + data= uc->port_pins[3] & uc->get_mem(MEM_SFR, P3); + sim->cmd->printf(" Port3 "); + print_bin(data, 8, sim->cmd_out()); + sim->cmd->printf(" 0x%02x %3d %c\n", data, data, isprint(data)?data:'.'); + + return(FALSE); +} + + +/* + * DUMP SFR [addr...] + */ +//FIXME +bool +cmd_dump_sfr(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + char *s; + t_addr start= 0x80; + uchar data; + struct name_entry *ne; + + if ((s= strtok(NULL, delimiters)) != NULL) + while (s != NULL) + { + if ((ne= get_name_entry(uc->sfr_tbl(), s, uc)) != NULL) + { + data= uc->get_mem(MEM_SFR, ne->addr); + sim->cmd->printf("%6s %02x %3d %c\n", ne->name, data, data, + isprint(data)?data:'.'); + } + else + { + start= strtol(s, NULL, 0); + data = uc->get_mem(MEM_SFR, start); + if (start >= SFR_START) + sim->cmd->printf("%06x %02x %3d %c\n", start, data, data, + isprint(data)?data:'.'); + } + s= strtok(NULL, delimiters); + } + else + // dump all + dump_memory(uc->mem(MEM_SFR), &start, 255, 16, sim->cmd_out(), sim); + return(FALSE); +} + + +/* + * DUMP BIT addr... + */ +//FIXME +bool +cmd_dump_bit(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + char *s, *sym; + uchar *cell, addr; + uchar bitaddr, bitmask; + + if ((s= strtok(NULL, delimiters)) == NULL) + { + sim->cmd->printf("Address has not given.\n"); + return(FALSE); + } + while (s) + { + if (!interpret_bitname(s, uc, &cell, &addr, &bitaddr, &bitmask, &sym)) + { + sim->cmd->printf("Bad address %s\n", s); + return(FALSE); + } + sim->cmd->printf("%06x %6s %c\n", addr, sym, (*cell & bitmask)?'1':'0'); + free(sym); + s= strtok(NULL, delimiters); + } + return(FALSE); +} + + +/* End of s51.src/dump.cc */ diff --git a/sim/ucsim/s51.src/dump.h b/sim/ucsim/s51.src/dump.h new file mode 100644 index 00000000..6350782e --- /dev/null +++ b/sim/ucsim/s51.src/dump.h @@ -0,0 +1,51 @@ +/* + * Simulator of microcontrollers (dump.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef DUMP_HEADER +#define DUMP_HEADER + +#include "ddconfig.h" + +#include "memcl.h" +#include "brkcl.h" +#include "newcmdcl.h" + +#include "uc51cl.h" //FIXME + + +extern void dump_memory(cl_mem *mem, t_addr *start, t_addr stop, + int bpl, FILE *f, class cl_sim *sim); + +extern bool cmd_disass(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_dump_port(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_dump_sfr(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_dump_bit(char *cmd, class t_uc51 *uc, class cl_sim *sim); + + +#endif + +/* End of s51.src/dump.h */ diff --git a/sim/ucsim/s51.src/glob.cc b/sim/ucsim/s51.src/glob.cc new file mode 100644 index 00000000..00cd82ff --- /dev/null +++ b/sim/ucsim/s51.src/glob.cc @@ -0,0 +1,501 @@ +/* + * Simulator of microcontrollers (glob.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + + +#include + +#include "stypes.h" + + +/* + * Names of instructions + */ + +struct dis_entry disass_51[]= { + { 0x00, 0xff, ' ', 1, "NOP"}, + { 0x01, 0xff, 'A', 2, "AJMP %A"}, + { 0x02, 0xff, 'L', 3, "LJMP %l"}, + { 0x03, 0xff, ' ', 1, "RR A"}, + { 0x04, 0xff, ' ', 1, "INC A"}, + { 0x05, 0xff, ' ', 2, "INC %a"}, + { 0x06, 0xff, ' ', 1, "INC @R0"}, + { 0x07, 0xff, ' ', 1, "INC @R1"}, + { 0x08, 0xff, ' ', 1, "INC R0"}, + { 0x09, 0xff, ' ', 1, "INC R1"}, + { 0x0a, 0xff, ' ', 1, "INC R2"}, + { 0x0b, 0xff, ' ', 1, "INC R3"}, + { 0x0c, 0xff, ' ', 1, "INC R4"}, + { 0x0d, 0xff, ' ', 1, "INC R5"}, + { 0x0e, 0xff, ' ', 1, "INC R6"}, + { 0x0f, 0xff, ' ', 1, "INC R7"}, + { 0x10, 0xff, 'R', 3, "JBC %b,%R"}, + { 0x11, 0xff, 'a', 2, "ACALL %A"}, + { 0x12, 0xff, 'l', 3, "LCALL %l"}, + { 0x13, 0xff, ' ', 1, "RRC A"}, + { 0x14, 0xff, ' ', 1, "DEC A"}, + { 0x15, 0xff, ' ', 2, "DEC %a"}, + { 0x16, 0xff, ' ', 1, "DEC @R0"}, + { 0x17, 0xff, ' ', 1, "DEC @R1"}, + { 0x18, 0xff, ' ', 1, "DEC R0"}, + { 0x19, 0xff, ' ', 1, "DEC R1"}, + { 0x1a, 0xff, ' ', 1, "DEC R2"}, + { 0x1b, 0xff, ' ', 1, "DEC R3"}, + { 0x1c, 0xff, ' ', 1, "DEC R4"}, + { 0x1d, 0xff, ' ', 1, "DEC R5"}, + { 0x1e, 0xff, ' ', 1, "DEC R6"}, + { 0x1f, 0xff, ' ', 1, "DEC R7"}, + { 0x20, 0xff, 'R', 3, "JB %b,%R"}, + { 0x21, 0xff, 'A', 2, "AJMP %A"}, + { 0x22, 0xff, '_', 1, "RET"}, + { 0x23, 0xff, ' ', 1, "RL A"}, + { 0x24, 0xff, ' ', 2, "ADD A,#%d"}, + { 0x25, 0xff, ' ', 2, "ADD A,%a"}, + { 0x26, 0xff, ' ', 1, "ADD A,@R0"}, + { 0x27, 0xff, ' ', 1, "ADD A,@R1"}, + { 0x28, 0xff, ' ', 1, "ADD A,R0"}, + { 0x29, 0xff, ' ', 1, "ADD A,R1"}, + { 0x2a, 0xff, ' ', 1, "ADD A,R2"}, + { 0x2b, 0xff, ' ', 1, "ADD A,R3"}, + { 0x2c, 0xff, ' ', 1, "ADD A,R4"}, + { 0x2d, 0xff, ' ', 1, "ADD A,R5"}, + { 0x2e, 0xff, ' ', 1, "ADD A,R6"}, + { 0x2f, 0xff, ' ', 1, "ADD A,R7"}, + { 0x30, 0xff, 'R', 3, "JNB %b,%R"}, + { 0x31, 0xff, 'a', 2, "ACALL %A"}, + { 0x32, 0xff, '_', 1, "RETI"}, + { 0x33, 0xff, ' ', 1, "RLC A"}, + { 0x34, 0xff, ' ', 2, "ADDC A,#%d"}, + { 0x35, 0xff, ' ', 2, "ADDC A,%a"}, + { 0x36, 0xff, ' ', 1, "ADDC A,@R0"}, + { 0x37, 0xff, ' ', 1, "ADDC A,@R1"}, + { 0x38, 0xff, ' ', 1, "ADDC A,R0"}, + { 0x39, 0xff, ' ', 1, "ADDC A,R1"}, + { 0x3a, 0xff, ' ', 1, "ADDC A,R2"}, + { 0x3b, 0xff, ' ', 1, "ADDC A,R3"}, + { 0x3c, 0xff, ' ', 1, "ADDC A,R4"}, + { 0x3d, 0xff, ' ', 1, "ADDC A,R5"}, + { 0x3e, 0xff, ' ', 1, "ADDC A,R6"}, + { 0x3f, 0xff, ' ', 1, "ADDC A,R7"}, + { 0x40, 0xff, 'r', 2, "JC %r"}, + { 0x41, 0xff, 'A', 2, "AJMP %A"}, + { 0x42, 0xff, ' ', 2, "ORL %a,A"}, + { 0x43, 0xff, ' ', 3, "ORL %a,#%D"}, + { 0x44, 0xff, ' ', 2, "ORL A,#%d"}, + { 0x45, 0xff, ' ', 2, "ORL A,%a"}, + { 0x46, 0xff, ' ', 1, "ORL A,@R0"}, + { 0x47, 0xff, ' ', 1, "ORL A,@R1"}, + { 0x48, 0xff, ' ', 1, "ORL A,R0"}, + { 0x49, 0xff, ' ', 1, "ORL A,R1"}, + { 0x4a, 0xff, ' ', 1, "ORL A,R2"}, + { 0x4b, 0xff, ' ', 1, "ORL A,R3"}, + { 0x4c, 0xff, ' ', 1, "ORL A,R4"}, + { 0x4d, 0xff, ' ', 1, "ORL A,R5"}, + { 0x4e, 0xff, ' ', 1, "ORL A,R6"}, + { 0x4f, 0xff, ' ', 1, "ORL A,R7"}, + { 0x50, 0xff, 'r', 2, "JNC %r"}, + { 0x51, 0xff, 'a', 2, "ACALL %A"}, + { 0x52, 0xff, ' ', 2, "ANL %a,A"}, + { 0x53, 0xff, ' ', 3, "ANL %a,#%D"}, + { 0x54, 0xff, ' ', 2, "ANL A,#%d"}, + { 0x55, 0xff, ' ', 2, "ANL A,%a"}, + { 0x56, 0xff, ' ', 1, "ANL A,@R0"}, + { 0x57, 0xff, ' ', 1, "ANL A,@R1"}, + { 0x58, 0xff, ' ', 1, "ANL A,R0"}, + { 0x59, 0xff, ' ', 1, "ANL A,R1"}, + { 0x5a, 0xff, ' ', 1, "ANL A,R2"}, + { 0x5b, 0xff, ' ', 1, "ANL A,R3"}, + { 0x5c, 0xff, ' ', 1, "ANL A,R4"}, + { 0x5d, 0xff, ' ', 1, "ANL A,R5"}, + { 0x5e, 0xff, ' ', 1, "ANL A,R6"}, + { 0x5f, 0xff, ' ', 1, "ANL A,R7"}, + { 0x60, 0xff, 'r', 2, "JZ %r"}, + { 0x61, 0xff, 'A', 2, "AJMP %A"}, + { 0x62, 0xff, ' ', 2, "XRL %a,A"}, + { 0x63, 0xff, ' ', 3, "XRL %a,#%D"}, + { 0x64, 0xff, ' ', 2, "XRL A,#%d"}, + { 0x65, 0xff, ' ', 2, "XRL A,%a"}, + { 0x66, 0xff, ' ', 1, "XRL A,@R0"}, + { 0x67, 0xff, ' ', 1, "XRL A,@R1"}, + { 0x68, 0xff, ' ', 1, "XRL A,R0"}, + { 0x69, 0xff, ' ', 1, "XRL A,R1"}, + { 0x6a, 0xff, ' ', 1, "XRL A,R2"}, + { 0x6b, 0xff, ' ', 1, "XRL A,R3"}, + { 0x6c, 0xff, ' ', 1, "XRL A,R4"}, + { 0x6d, 0xff, ' ', 1, "XRL A,R5"}, + { 0x6e, 0xff, ' ', 1, "XRL A,R6"}, + { 0x6f, 0xff, ' ', 1, "XRL A,R7"}, + { 0x70, 0xff, 'r', 2, "JNZ %r"}, + { 0x71, 0xff, 'a', 2, "ACALL %A"}, + { 0x72, 0xff, ' ', 2, "ORL C,%b"}, + { 0x73, 0xff, '_', 1, "JMP @A+DPTR"}, + { 0x74, 0xff, ' ', 2, "MOV A,#%d"}, + { 0x75, 0xff, ' ', 3, "MOV %a,#%D"}, + { 0x76, 0xff, ' ', 2, "MOV @R0,#%d"}, + { 0x77, 0xff, ' ', 2, "MOV @R1,#%d"}, + { 0x78, 0xff, ' ', 2, "MOV R0,#%d"}, + { 0x79, 0xff, ' ', 2, "MOV R1,#%d"}, + { 0x7a, 0xff, ' ', 2, "MOV R2,#%d"}, + { 0x7b, 0xff, ' ', 2, "MOV R3,#%d"}, + { 0x7c, 0xff, ' ', 2, "MOV R4,#%d"}, + { 0x7d, 0xff, ' ', 2, "MOV R5,#%d"}, + { 0x7e, 0xff, ' ', 2, "MOV R6,#%d"}, + { 0x7f, 0xff, ' ', 2, "MOV R7,#%d"}, + { 0x80, 0xff, 's', 2, "SJMP %r"}, + { 0x81, 0xff, 'A', 2, "AJMP %A"}, + { 0x82, 0xff, ' ', 2, "ANL C,%b"}, + { 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"}, + { 0x84, 0xff, ' ', 1, "DIV AB"}, + { 0x85, 0xff, ' ', 3, "MOV %8,%a"}, + { 0x86, 0xff, ' ', 2, "MOV %a,@R0"}, + { 0x87, 0xff, ' ', 2, "MOV %a,@R1"}, + { 0x88, 0xff, ' ', 2, "MOV %a,R0"}, + { 0x89, 0xff, ' ', 2, "MOV %a,R1"}, + { 0x8a, 0xff, ' ', 2, "MOV %a,R2"}, + { 0x8b, 0xff, ' ', 2, "MOV %a,R3"}, + { 0x8c, 0xff, ' ', 2, "MOV %a,R4"}, + { 0x8d, 0xff, ' ', 2, "MOV %a,R5"}, + { 0x8e, 0xff, ' ', 2, "MOV %a,R6"}, + { 0x8f, 0xff, ' ', 2, "MOV %a,R7"}, + { 0x90, 0xff, ' ', 3, "MOV DPTR,#%6"}, + { 0x91, 0xff, 'a', 2, "ACALL %A"}, + { 0x92, 0xff, ' ', 2, "MOV %b,C"}, + { 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"}, + { 0x94, 0xff, ' ', 2, "SUBB A,#%d"}, + { 0x95, 0xff, ' ', 2, "SUBB A,%a"}, + { 0x96, 0xff, ' ', 1, "SUBB A,@R0"}, + { 0x97, 0xff, ' ', 1, "SUBB A,@R1"}, + { 0x98, 0xff, ' ', 1, "SUBB A,R0"}, + { 0x99, 0xff, ' ', 1, "SUBB A,R1"}, + { 0x9a, 0xff, ' ', 1, "SUBB A,R2"}, + { 0x9b, 0xff, ' ', 1, "SUBB A,R3"}, + { 0x9c, 0xff, ' ', 1, "SUBB A,R4"}, + { 0x9d, 0xff, ' ', 1, "SUBB A,R5"}, + { 0x9e, 0xff, ' ', 1, "SUBB A,R6"}, + { 0x9f, 0xff, ' ', 1, "SUBB A,R7"}, + { 0xa0, 0xff, ' ', 2, "ORL C,/%b"}, + { 0xa1, 0xff, 'A', 2, "AJMP %A"}, + { 0xa2, 0xff, ' ', 2, "MOV C,%b"}, + { 0xa3, 0xff, ' ', 1, "INC DPTR"}, + { 0xa4, 0xff, ' ', 1, "MUL AB"}, + { 0xa5, 0xff, '_', 1, "-"}, + { 0xa6, 0xff, ' ', 2, "MOV @R0,%a"}, + { 0xa7, 0xff, ' ', 2, "MOV @R1,%a"}, + { 0xa8, 0xff, ' ', 2, "MOV R0,%a"}, + { 0xa9, 0xff, ' ', 2, "MOV R1,%a"}, + { 0xaa, 0xff, ' ', 2, "MOV R2,%a"}, + { 0xab, 0xff, ' ', 2, "MOV R3,%a"}, + { 0xac, 0xff, ' ', 2, "MOV R4,%a"}, + { 0xad, 0xff, ' ', 2, "MOV R5,%a"}, + { 0xae, 0xff, ' ', 2, "MOV R6,%a"}, + { 0xaf, 0xff, ' ', 2, "MOV R7,%a"}, + { 0xb0, 0xff, ' ', 2, "ANL C,/%b"}, + { 0xb1, 0xff, 'a', 2, "ACALL %A"}, + { 0xb2, 0xff, ' ', 2, "CPL %b"}, + { 0xb3, 0xff, ' ', 1, "CPL C"}, + { 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"}, + { 0xb5, 0xff, 'R', 3, "CJNE A,%a,%R"}, + { 0xb6, 0xff, 'R', 3, "CJNE @R0,#%d,%R"}, + { 0xb7, 0xff, 'R', 3, "CJNE @R1,#%d,%R"}, + { 0xb8, 0xff, 'R', 3, "CJNE R0,#%d,%R"}, + { 0xb9, 0xff, 'R', 3, "CJNE R1,#%d,%R"}, + { 0xba, 0xff, 'R', 3, "CJNE R2,#%d,%R"}, + { 0xbb, 0xff, 'R', 3, "CJNE R3,#%d,%R"}, + { 0xbc, 0xff, 'R', 3, "CJNE R4,#%d,%R"}, + { 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"}, + { 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"}, + { 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"}, + { 0xc0, 0xff, ' ', 2, "PUSH %a"}, + { 0xc1, 0xff, 'A', 2, "AJMP %A"}, + { 0xc2, 0xff, ' ', 2, "CLR %b"}, + { 0xc3, 0xff, ' ', 1, "CLR C"}, + { 0xc4, 0xff, ' ', 1, "SWAP A"}, + { 0xc5, 0xff, ' ', 2, "XCH A,%a"}, + { 0xc6, 0xff, ' ', 1, "XCH A,@R0"}, + { 0xc7, 0xff, ' ', 1, "XCH A,@R1"}, + { 0xc8, 0xff, ' ', 1, "XCH A,R0"}, + { 0xc9, 0xff, ' ', 1, "XCH A,R1"}, + { 0xca, 0xff, ' ', 1, "XCH A,R2"}, + { 0xcb, 0xff, ' ', 1, "XCH A,R3"}, + { 0xcc, 0xff, ' ', 1, "XCH A,R4"}, + { 0xcd, 0xff, ' ', 1, "XCH A,R5"}, + { 0xce, 0xff, ' ', 1, "XCH A,R6"}, + { 0xcf, 0xff, ' ', 1, "XCH A,R7"}, + { 0xd0, 0xff, ' ', 2, "POP %a"}, + { 0xd1, 0xff, 'a', 2, "ACALL %A"}, + { 0xd2, 0xff, ' ', 2, "SETB %b"}, + { 0xd3, 0xff, ' ', 1, "SETB C"}, + { 0xd4, 0xff, ' ', 1, "DA A"}, + { 0xd5, 0xff, 'R', 3, "DJNZ %a,%R"}, + { 0xd6, 0xff, ' ', 1, "XCHD A,@R0"}, + { 0xd7, 0xff, ' ', 1, "XCHD A,@R1"}, + { 0xd8, 0xff, 'r', 2, "DJNZ R0,%r"}, + { 0xd9, 0xff, 'r', 2, "DJNZ R1,%r"}, + { 0xda, 0xff, 'r', 2, "DJNZ R2,%r"}, + { 0xdb, 0xff, 'r', 2, "DJNZ R3,%r"}, + { 0xdc, 0xff, 'r', 2, "DJNZ R4,%r"}, + { 0xdd, 0xff, 'r', 2, "DJNZ R5,%r"}, + { 0xde, 0xff, 'r', 2, "DJNZ R6,%r"}, + { 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"}, + { 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"}, + { 0xe1, 0xff, 'A', 2, "AJMP %A"}, + { 0xe2, 0xff, ' ', 1, "MOVX A,@R0"}, + { 0xe3, 0xff, ' ', 1, "MOVX A,@R1"}, + { 0xe4, 0xff, ' ', 1, "CLR A"}, + { 0xe5, 0xff, ' ', 2, "MOV A,%a"}, + { 0xe6, 0xff, ' ', 1, "MOV A,@R0"}, + { 0xe7, 0xff, ' ', 1, "MOV A,@R1"}, + { 0xe8, 0xff, ' ', 1, "MOV A,R0"}, + { 0xe9, 0xff, ' ', 1, "MOV A,R1"}, + { 0xea, 0xff, ' ', 1, "MOV A,R2"}, + { 0xeb, 0xff, ' ', 1, "MOV A,R3"}, + { 0xec, 0xff, ' ', 1, "MOV A,R4"}, + { 0xed, 0xff, ' ', 1, "MOV A,R5"}, + { 0xee, 0xff, ' ', 1, "MOV A,R6"}, + { 0xef, 0xff, ' ', 1, "MOV A,R7"}, + { 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"}, + { 0xf1, 0xff, 'a', 2, "ACALL %A"}, + { 0xf2, 0xff, ' ', 1, "MOVX @R0,A"}, + { 0xf3, 0xff, ' ', 1, "MOVX @R1,A"}, + { 0xf4, 0xff, ' ', 1, "CPL A"}, + { 0xf5, 0xff, ' ', 2, "MOV %a,A"}, + { 0xf6, 0xff, ' ', 1, "MOV @R0,A"}, + { 0xf7, 0xff, ' ', 1, "MOV @R1,A"}, + { 0xf8, 0xff, ' ', 1, "MOV R0,A"}, + { 0xf9, 0xff, ' ', 1, "MOV R1,A"}, + { 0xfa, 0xff, ' ', 1, "MOV R2,A"}, + { 0xfb, 0xff, ' ', 1, "MOV R3,A"}, + { 0xfc, 0xff, ' ', 1, "MOV R4,A"}, + { 0xfd, 0xff, ' ', 1, "MOV R5,A"}, + { 0xfe, 0xff, ' ', 1, "MOV R6,A"}, + { 0xff, 0xff, ' ', 1, "MOV R7,A"}, + { 0, 0, 0, 0, NULL } +}; + + +/* + * Names of SFR cells + */ + +struct name_entry sfr_tab51[]= +{ + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xe0, "ACC"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xf0, "B"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd0, "PSW"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x81, "SP"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x82, "DPL"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x83, "DPH"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x80, "P0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x90, "P1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa0, "P2"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xb0, "P3"}, + {CPU_ALL_51|CPU_ALL_52, 0xb8, "IP"}, + {CPU_ALL_51|CPU_ALL_52, 0xa8, "IE"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x89, "TMOD"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x88, "TCON"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8c, "TH0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8a, "TL0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8d, "TH1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8b, "TL1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x98, "SCON"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x99, "SBUF"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x87, "PCON"}, + {CPU_ALL_52|CPU_251, 0xc8, "T2CON"}, + {CPU_ALL_52|CPU_251, 0xcd, "TH2"}, + {CPU_ALL_52|CPU_251, 0xcc, "TL2"}, + {CPU_ALL_52|CPU_251, 0xcb, "RCAP2H"}, + {CPU_ALL_52|CPU_251, 0xca, "RCAP2L"}, + {CPU_251, 0x84, "DPXL"}, + {CPU_89C51R|CPU_51R, 0x8e, "AUXR"}, + {CPU_51R|CPU_89C51R|CPU_251, 0xa6, "WDTRST"}, + {CPU_51R|CPU_89C51R|CPU_251, 0xa9, "SADDR"}, + {CPU_89C51R|CPU_51R, 0xb7, "IPH"}, + {CPU_251, 0xb7, "IPH0"}, + {CPU_251, 0xa8, "IE0"}, + {CPU_251, 0xb8, "IPL0"}, + {CPU_51R|CPU_89C51R|CPU_251, 0xb9, "SADEN"}, + {CPU_251, 0xbd, "SPH"}, + {CPU_51R|CPU_89C51R|CPU_251, 0xc9, "T2MOD"}, + {CPU_251, 0xd1, "PSW1"}, + {CPU_89C51R|CPU_251, 0xd8, "CCON"}, + {CPU_89C51R|CPU_251, 0xd9, "CMOD"}, + {CPU_89C51R|CPU_251, 0xda, "CCAPM0"}, + {CPU_89C51R|CPU_251, 0xdb, "CCAPM1"}, + {CPU_89C51R|CPU_251, 0xdc, "CCAPM2"}, + {CPU_89C51R|CPU_251, 0xdd, "CCAPM3"}, + {CPU_89C51R|CPU_251, 0xde, "CCAPM4"}, + {CPU_89C51R|CPU_251, 0xe9, "CL"}, + {CPU_89C51R|CPU_251, 0xea, "CCAP0L"}, + {CPU_89C51R|CPU_251, 0xeb, "CCAP1L"}, + {CPU_89C51R|CPU_251, 0xec, "CCAP2L"}, + {CPU_89C51R|CPU_251, 0xed, "CCAP3L"}, + {CPU_89C51R|CPU_251, 0xee, "CCAP4L"}, + {CPU_89C51R|CPU_251, 0xf9, "CH"}, + {CPU_89C51R|CPU_251, 0xfa, "CCAP0H"}, + {CPU_89C51R|CPU_251, 0xfb, "CCAP1H"}, + {CPU_89C51R|CPU_251, 0xfc, "CCAP2H"}, + {CPU_89C51R|CPU_251, 0xfd, "CCAP3H"}, + {CPU_89C51R|CPU_251, 0xfe, "CCAP4H"}, + {CPU_89C51R, 0xa2, "AUXR1"}, + {0, 0, NULL} +}; + + +/* + * Names of bits + */ + +struct name_entry bit_tab51[]= +{ + /* PSW */ + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd7, "CY"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd6, "AC"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd5, "F0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd4, "RS1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd3, "RS0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd2, "OV"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd0, "P"}, + /* TCON */ + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8f, "TF1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8e, "TR1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8d, "TF0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8c, "TR0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8b, "IE1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8a, "IT1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x89, "IE0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x88, "IT0"}, + /* IE */ + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xaf, "EA"}, + {CPU_89C51R|CPU_251, 0xae, "EC"}, + {CPU_ALL_52|CPU_251, 0xad, "ET2"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xac, "ES"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xab, "ET1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xaa, "EX1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa9, "ET0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa8, "EX0"}, + /* IP */ + {CPU_89C51R|CPU_251, 0xbe, "PPC"}, + {CPU_ALL_52, 0xbd, "PT2"}, + {CPU_ALL_51|CPU_ALL_52, 0xbc, "PS"}, + {CPU_ALL_51|CPU_ALL_52, 0xbb, "PT1"}, + {CPU_ALL_51|CPU_ALL_52, 0xba, "PX1"}, + {CPU_ALL_51|CPU_ALL_52, 0xb9, "PT0"}, + {CPU_ALL_51|CPU_ALL_52, 0xb8, "PX0"}, + /* IPL0 */ + {CPU_251, 0xbe, "IPL0.6"}, + {CPU_251, 0xbd, "IPL0.5"}, + {CPU_251, 0xbc, "IPL0.4"}, + {CPU_251, 0xbb, "IPL0.3"}, + {CPU_251, 0xba, "IPL0.2"}, + {CPU_251, 0xb9, "IPL0.1"}, + {CPU_251, 0xb8, "IPL0.0"}, + /* SCON */ + {CPU_51R|CPU_89C51R|CPU_251, 0x9f, "FE/SM0"}, + {CPU_ALL_51|CPU_ALL_52, 0x9f, "SM0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9e, "SM1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9d, "SM2"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9c, "REN"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9b, "TB8"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9a, "RB8"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x99, "TI"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x98, "RI"}, + /* T2CON */ + {CPU_ALL_52|CPU_251, 0xcf, "TF2"}, + {CPU_ALL_52|CPU_251, 0xce, "EXF2"}, + {CPU_ALL_52|CPU_251, 0xcd, "RCLK"}, + {CPU_ALL_52|CPU_251, 0xcc, "TCLK"}, + {CPU_ALL_52|CPU_251, 0xcb, "EXEN2"}, + {CPU_ALL_52|CPU_251, 0xca, "TR2"}, + {CPU_ALL_52|CPU_251, 0xc9, "C/T2"}, + {CPU_ALL_52|CPU_251, 0xc8, "CP/RL2"}, + /* CCON */ + {CPU_89C51R|CPU_251, 0xdf, "CF"}, + {CPU_89C51R|CPU_251, 0xde, "CR"}, + {CPU_89C51R|CPU_251, 0xdc, "CCF4"}, + {CPU_89C51R|CPU_251, 0xdb, "CCF3"}, + {CPU_89C51R|CPU_251, 0xda, "CCF2"}, + {CPU_89C51R|CPU_251, 0xd9, "CCF1"}, + {CPU_89C51R|CPU_251, 0xd8, "CCF0"}, + /* P1 */ + {CPU_89C51R|CPU_251, 0x97, "CEX4"}, + {CPU_89C51R|CPU_251, 0x96, "CEX3"}, + {CPU_89C51R|CPU_251, 0x95, "CEX2"}, + {CPU_89C51R|CPU_251, 0x94, "CEX1"}, + {CPU_89C51R|CPU_251, 0x93, "CEX0"}, + {CPU_89C51R|CPU_251, 0x92, "EXI"}, + {CPU_89C51R|CPU_251, 0x91, "T2EX"}, + {CPU_89C51R|CPU_251, 0x90, "T2"}, + + {0, 0, NULL} +}; + + +/* + * Information about different type of CPUs + */ + +struct cpu_entry cpus_51[]= +{ + {"51" , CPU_51, CPU_HMOS}, + {"8051" , CPU_51, CPU_HMOS}, + {"8751" , CPU_51, CPU_HMOS}, + {"C51" , CPU_51, CPU_CMOS}, + {"80C51" , CPU_51, CPU_CMOS}, + {"87C51" , CPU_51, CPU_CMOS}, + {"31" , CPU_31, CPU_HMOS}, + {"8031" , CPU_31, CPU_HMOS}, + {"C31" , CPU_31, CPU_CMOS}, + {"80C31" , CPU_31, CPU_CMOS}, + + {"52" , CPU_52, CPU_HMOS}, + {"8052" , CPU_52, CPU_HMOS}, + {"8752" , CPU_52, CPU_HMOS}, + {"C52" , CPU_52, CPU_CMOS}, + {"80C52" , CPU_52, CPU_CMOS}, + {"87C52" , CPU_52, CPU_CMOS}, + {"32" , CPU_32, CPU_HMOS}, + {"8032" , CPU_32, CPU_HMOS}, + {"C32" , CPU_32, CPU_CMOS}, + {"80C32" , CPU_32, CPU_CMOS}, + + {"51R" , CPU_51R, CPU_CMOS}, + {"51RA" , CPU_51R, CPU_CMOS}, + {"51RB" , CPU_51R, CPU_CMOS}, + {"51RC" , CPU_51R, CPU_CMOS}, + {"C51R" , CPU_51R, CPU_CMOS}, + {"C51RA" , CPU_51R, CPU_CMOS}, + {"C51RB" , CPU_51R, CPU_CMOS}, + {"C51RC" , CPU_51R, CPU_CMOS}, + + {"89C51R", CPU_89C51R, CPU_CMOS}, + + {"251" , CPU_251, CPU_CMOS}, + {"C251" , CPU_251, CPU_CMOS}, + {NULL, 0, 0} +}; + + +/* End of s51.src/glob.cc */ diff --git a/sim/ucsim/s51.src/glob.h b/sim/ucsim/s51.src/glob.h new file mode 100644 index 00000000..76e5f9ba --- /dev/null +++ b/sim/ucsim/s51.src/glob.h @@ -0,0 +1,40 @@ +/* + * Simulator of microcontrollers (glob.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef GLOB_HEADER +#define GLOB_HEADER + + +extern struct dis_entry disass_51[]; +extern struct name_entry sfr_tab51[]; +extern struct name_entry bit_tab51[]; +extern struct cpu_entry cpus_51[]; + + +#endif + +/* End of s51.src/glob.h */ diff --git a/sim/ucsim/s51.src/go.cc b/sim/ucsim/s51.src/go.cc new file mode 100644 index 00000000..cbc52ba7 --- /dev/null +++ b/sim/ucsim/s51.src/go.cc @@ -0,0 +1,219 @@ +/* + * Simulator of microcontrollers (go.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include "i_string.h" + +#include "simcl.h" + +#include "uc51cl.h" //FIXME +#include "globals.h" +#include "dump.h" + + +/* + * GO [start [stop]] + */ +//FIXME +bool +cmd_go(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + char *start_str, *stop_str; + t_addr start= uc->PC; + long stop= -1; + class cl_brk *b; + bool brk_at_stop= FALSE; + + if (sim->state & SIM_GO) + { + fprintf(sim->cmd_out(), + "Execution is already running.\n"); + return(0); + } + if ((start_str= strtok(NULL, delimiters)) != NULL) + { + start= strtol(start_str, NULL, 0); + if ((stop_str= strtok(NULL, delimiters)) != NULL) + stop= strtol(stop_str, NULL, 0); + } + if (uc->PC != start) + { + if (!uc->inst_at(start) && + uc->debug) + fprintf(sim->cmd_out(), + "Warning: maybe not instruction at 0x%06lx\n", start); + uc->PC= start; + } + if (stop >= 0) + { + if (start == (t_addr)stop) + { + fprintf(sim->cmd_out(), "Addresses must be different.\n"); + return(FALSE); + } + if ((b= uc->fbrk_at(stop))) + { + brk_at_stop= TRUE; + b->cnt= 1; + } + else + { + b= new cl_fetch_brk(uc->fbrk->make_new_nr(), stop, brkDYNAMIC, 1); + uc->fbrk->add_bp(b); + } + } + if (uc->fbrk_at(start)) + uc->do_inst(1); + //fprintf(sim->cmd_out(), "Simulation started, PC=0x%06x\n", uc->PC); + sim->cmd->printf("Simulation started, PC=0x%06x\n", uc->PC); + sim->start(sim->cmd->actual_console); + //uc->do_inst(-1); + /*if ((stop >= 0) && + !brk_at_stop) + uc->fbrk->del_bp(stop);*/ + /*fprintf(sim->cmd_out(), "%d\n", uc->result); + uc->print_disass(uc->PC);*/ + return(FALSE); +} + + +bool +cmd_stop(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + sim->stop(resUSER); + uc->print_disass(uc->PC, sim->cmd->actual_console); + return(FALSE); +} + + +static void +dump_step(class t_uc51 *uc, class cl_sim *sim) +{ + //cmd_dump_regs(NULL, uc, sim); + uc->print_regs(sim->cmd->actual_console); +} + + +/* + * STEP [step] + */ +//FIXME +bool +cmd_step(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + int step= 1; + char *s; + + if ((s= strtok(NULL, delimiters)) != NULL) + step= strtol(s, NULL, 0); + while (step--) + { + uc->do_inst(1); + dump_step(uc, sim); + } + return(FALSE); +} + + +/* + * NEXT [step] + */ +//FIXME +bool +cmd_next(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + int step= 1; + char *s; + class cl_brk *b; + uint next; + + if ((s= strtok(NULL, delimiters)) != NULL) + step= strtol(s, NULL, 0); + while (step--) + { + if ((uc->dis_tbl()[uc->get_mem(MEM_ROM, uc->PC)].branch == 'a') || + (uc->dis_tbl()[uc->get_mem(MEM_ROM, uc->PC)].branch == 'l')) + { + next= uc->PC+2; + if (uc->dis_tbl()[uc->get_mem(MEM_ROM, uc->PC)].branch == 'l') + next++; + if (!uc->fbrk_at(next)) + { + b= new cl_fetch_brk(uc->fbrk->make_new_nr(), + next, brkDYNAMIC, 1); + uc->fbrk->add(b); + } + uc->do_inst(-1); + } + else + uc->do_inst(1); + dump_step(uc, sim); + } + return(FALSE); +} + + +/* + * PC [address] + */ +//FIXME +bool +cmd_pc(char *cmd, class t_uc51 *uc, class cl_sim *sim) +{ + char *s, *p= NULL; + long pc; + + if ((s= strtok(NULL, delimiters)) == NULL) + { + uc->print_disass(uc->PC, sim->cmd->actual_console); + return(FALSE); + } + pc= strtol(s, &p, 0); + if (p && + ((p == s) || + *p)) + fprintf(sim->cmd_out(), "Wrong parameter, PC unchanged.\n"); + else + { + if (pc >= EROM_SIZE) + pc= 0; + if (!uc->inst_at(pc) && + uc->debug) + fprintf(sim->cmd_out(), + "Warning: maybe not instruction at %06lx\n", pc); + uc->PC= pc; + uc->print_disass(uc->PC, sim->cmd->actual_console); + } + return(FALSE); +} + + +/* End of s51.src/go.cc */ diff --git a/sim/ucsim/s51.src/go.h b/sim/ucsim/s51.src/go.h new file mode 100644 index 00000000..8dbc6563 --- /dev/null +++ b/sim/ucsim/s51.src/go.h @@ -0,0 +1,43 @@ +/* + * Simulator of microcontrollers (go.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef GO_HEADER +#define GO_HEADER + +#include "ddconfig.h" + + +extern bool cmd_go(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_stop(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_step(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_next(char *cmd, class t_uc51 *uc, class cl_sim *sim); +extern bool cmd_pc(char *cmd, class t_uc51 *uc, class cl_sim *sim); + + +#endif + +/* End of s51.src/go.h */ diff --git a/sim/ucsim/s51.src/inc.cc b/sim/ucsim/s51.src/inc.cc new file mode 100644 index 00000000..f3d67750 --- /dev/null +++ b/sim/ucsim/s51.src/inc.cc @@ -0,0 +1,184 @@ +/* + * Simulator of microcontrollers (inc.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "uc51cl.h" +#include "regs51.h" + + +/* + * 0x04 1 12 INC A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_inc_a(uchar code) +{ + sfr->set(event_at.ws= ACC, sfr->get(ACC)+1); + return(resGO); +} + + +/* + * 0x05 2 12 INC addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_inc_addr(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)++; + proc_write(addr); + return(resGO); +} + + +/* + * 0x06-0x07 1 12 INC @Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_inc_$ri(uchar code) +{ + uchar *addr; + int res; + + addr= get_indirect(event_at.wi= *(get_reg(code & 0x01)), &res); + (*addr)++; + proc_write(addr); + return(res); +} + + +/* + * 0x08-0x0f 1 12 INC Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_inc_rn(uchar code) +{ + (*(get_reg(code & 0x07, &event_at.wi)))++; + return(resGO); +} + + +/* + * 0x14 1 12 DEC A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_dec_a(uchar code) +{ + sfr->set(event_at.ws= ACC, sfr->get(ACC)-1); + return(resGO); +} + + +/* + * 0x15 2 12 DEC addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_dec_addr(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)--; + proc_write(addr); + return(resGO); +} + + +/* + * 0x16-0x17 1 12 DEC @Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_dec_$ri(uchar code) +{ + uchar *addr; + int res; + + addr= get_indirect(event_at.wi= *(get_reg(code & 0x01)), &res); + (*addr)--; + proc_write(addr); + return(res); +} + + +/* + * 0x18-0x1f 1 12 DEC Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_dec_rn(uchar code) +{ + (*(get_reg(code & 0x07, &event_at.wi)))--; + return(resGO); +} + + +/* + * 0xa3 1 24 INC DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_inc_dptr(uchar code) +{ + uint dptr; + + dptr= sfr->get(DPH)*256 + sfr->get(DPL) + 1; + sfr->set(event_at.ws= DPH, (dptr >> 8) & 0xff); + sfr->set(DPL, dptr & 0xff); + tick(1); + return(resGO); +} + + +/* End of s51.src/inc.cc */ diff --git a/sim/ucsim/s51.src/inst.list b/sim/ucsim/s51.src/inst.list new file mode 100644 index 00000000..99286e45 --- /dev/null +++ b/sim/ucsim/s51.src/inst.list @@ -0,0 +1,256 @@ +0x00 NOP 1 12 +0x01 AJMP addr 2 24 +0x02 LJMP addr 3 24 +0x03 RR A 1 12 +0x04 INC A 1 12 +0x05 INC addr 2 12 +0x06 INC @R0 1 12 +0x07 INC @R1 1 12 +0x08 INC R0 1 12 +0x09 INC R1 1 12 +0x0a INC R2 1 12 +0x0b INC R3 1 12 +0x0c INC R4 1 12 +0x0d INC R5 1 12 +0x0e INC R6 1 12 +0x0f INC R7 1 12 +0x10 JBC bit,addr 3 12 +0x11 ACALL addr 2 24 +0x12 LCALL addr 3 24 +0x13 RRC A 1 12 +0x14 DEC A 1 12 +0x15 DEC addr 2 12 +0x16 DEC @R0 1 12 +0x17 DEC @R1 1 12 +0x18 DEC R0 1 12 +0x19 DEC R1 1 12 +0x1a DEC R2 1 12 +0x1b DEC R3 1 12 +0x1c DEC R4 1 12 +0x1d DEC R5 1 12 +0x1e DEC R6 1 12 +0x1f DEC R7 1 12 +0x20 JB bit,addr 3 24 +0x21 AJMP addr 2 24 +0x22 RET 1 24 +0x23 RL A 1 12 +0x24 ADD A,#data 2 12 +0x25 ADD A,addr 2 12 +0x26 ADD A,@R0 1 12 +0x27 ADD A,@R1 1 12 +0x28 ADD A,R0 1 12 +0x29 ADD A,R1 1 12 +0x2a ADD A,R2 1 12 +0x2b ADD A,R3 1 12 +0x2c ADD A,R4 1 12 +0x2d ADD A,R5 1 12 +0x2e ADD A,R6 1 12 +0x2f ADD A,R7 1 12 +0x30 JNB bit,addr 3 12(?) +0x31 ACALL addr 2 24 +0x32 RETI 1 24 +0x33 RLC A 1 12 +0x34 ADDC A,#data 2 12 +0x35 ADDC A,addr 2 12 +0x36 ADDC A,@R0 1 12 +0x37 ADDC A,@R1 1 12 +0x38 ADDC A,R0 1 12 +0x39 ADDC A,R1 1 12 +0x3a ADDC A,R2 1 12 +0x3b ADDC A,R3 1 12 +0x3c ADDC A,R4 1 12 +0x3d ADDC A,R5 1 12 +0x3e ADDC A,R6 1 12 +0x3f ADDC A,R7 1 12 +0x40 JC addr 2 24 +0x41 AJMP addr 2 24 +0x42 ORL addr,A 2 12 +0x43 ORL addr,#data 3 24 +0x44 ORL A,#data 2 12 +0x45 ORL A,addr 2 12 +0x46 ORL A,@R0 1 12 +0x47 ORL A,@R1 1 12 +0x48 ORL A,R0 1 12 +0x49 ORL A,R1 1 12 +0x4a ORL A,R2 1 12 +0x4b ORL A,R3 1 12 +0x4c ORL A,R4 1 12 +0x4d ORL A,R5 1 12 +0x4e ORL A,R6 1 12 +0x4f ORL A,R7 1 12 +0x50 JNC addr 2 24 +0x51 ACALL addr 2 24 +0x52 ANL addr,A 2 12 +0x53 ANL addr,#data 3 24 +0x54 ANL A,#data 2 12 +0x55 ANL A,addr 2 12 +0x56 ANL A,@R0 1 12 +0x57 ANL A,@R1 1 12 +0x58 ANL A,R0 1 12 +0x59 ANL A,R1 1 12 +0x5a ANL A,R2 1 12 +0x5b ANL A,R3 1 12 +0x5c ANL A,R4 1 12 +0x5d ANL A,R5 1 12 +0x5e ANL A,R6 1 12 +0x5f ANL A,R7 1 12 +0x60 JZ addr 2 24 +0x61 AJMP addr 2 24 +0x62 XRL addr,A 2 12 +0x63 XRL addr,#data 3 24 +0x64 XRL A,#data 2 12 +0x65 XRL A,addr 2 12 +0x66 XRL A,@R0 1 12 +0x67 XRL A,@R1 1 12 +0x68 XRL A,R0 1 12 +0x69 XRL A,R1 1 12 +0x6a XRL A,R2 1 12 +0x6b XRL A,R3 1 12 +0x6c XRL A,R4 1 12 +0x6d XRL A,R5 1 12 +0x6e XRL A,R6 1 12 +0x6f XRL A,R7 1 12 +0x70 JNZ addr 2 24 +0x71 ACALL addr 2 24 +0x72 ORL C,addr 2 24 +0x73 JMP @A+DPTR 1 24 +0x74 MOV A,#data 2 12 +0x75 MOV addr,#data 3 24 +0x76 MOV @R0,#data 2 12 +0x77 MOV @R1,#data 2 12 +0x78 MOV R0,#data 2 12 +0x79 MOV R1,#data 2 12 +0x7a MOV R2,#data 2 12 +0x7b MOV R3,#data 2 12 +0x7c MOV R4,#data 2 12 +0x7d MOV R5,#data 2 12 +0x7e MOV R6,#data 2 12 +0x7f MOV R7,#data 2 12 +0x80 SJMP addr 2 24 +0x81 AJMP addr 2 24 +0x82 ANL C,addr 2 24 +0x83 MOVC A,@A+PC 1 24 +0x84 DIV AB 1 48 +0x85 MOV addr,addr 3 24 +0x86 MOV addr,@R0 2 24 +0x87 MOV addr,@R1 2 24 +0x88 MOV addr,R0 2 24 +0x89 MOV addr,R1 2 24 +0x8a MOV addr,R2 2 24 +0x8b MOV addr,R3 2 24 +0x8c MOV addr,R4 2 24 +0x8d MOV addr,R5 2 24 +0x8e MOV addr,R6 2 24 +0x8f MOV addr,R7 2 24 +0x90 MOV DPTR,#data 3 24 +0x91 ACALL addr 2 24 +0x92 MOV addr,C 2 24 +0x93 MOVC A,@A+DPTR 1 24 +0x94 SUBB A,#data 2 12 +0x95 SUBB A,addr 2 12 +0x96 SUBB A,@R0 1 12 +0x97 SUBB A,@R1 1 12 +0x98 SUBB A,R0 1 12 +0x99 SUBB A,R1 1 12 +0x9a SUBB A,R2 1 12 +0x9b SUBB A,R3 1 12 +0x9c SUBB A,R4 1 12 +0x9d SUBB A,R5 1 12 +0x9e SUBB A,R6 1 12 +0x9f SUBB A,R7 1 12 +0xa0 ORL C,/addr 2 24 +0xa1 AJMP addr 2 24 +0xa2 MOV C,addr 2 12 +0xa3 INC DPTR 1 24 +0xa4 MUL AB 1 48 +0xa5 ****************Breakpoint +0xa6 MOV @R0,addr 2 24 +0xa7 MOV @R1,addr 2 24 +0xa8 MOV R0,addr 2 24 +0xa9 MOV R1,addr 2 24 +0xaa MOV R2,addr 2 24 +0xab MOV R3,addr 2 24 +0xac MOV R4,addr 2 24 +0xad MOV R5,addr 2 24 +0xae MOV R6,addr 2 24 +0xaf MOV R7,addr 2 24 +0xb0 ANL C,/addr 2 24 +0xb1 ACALL addr 2 24 +0xb2 CPL bitaddr 2 12 +0xb3 CPL C 1 12 +0xb4 CJNE A,#data,addr 3 24 +0xb5 CJNE A,addr,addr 3 24 +0xb6 CJNE @R0,#data,addr 3 24 +0xb7 CJNE @R1,#data,addr 3 24 +0xb8 CJNE R0,#data,addr 3 24 +0xb9 CJNE R1,#data,addr 3 24 +0xba CJNE R2,#data,addr 3 24 +0xbb CJNE R3,#data,addr 3 24 +0xbc CJNE R4,#data,addr 3 24 +0xbd CJNE R5,#data,addr 3 24 +0xbe CJNE R6,#data,addr 3 24 +0xbf CJNE R7,#data,addr 3 24 +0xc0 PUSH addr 2 24 +0xc1 AJMP addr 2 24 +0xc2 CLR bitaddr 2 12 +0xc3 CLR C 1 12 +0xc4 SWAP A 1 12 +0xc5 XCH A,addr 2 12 +0xc6 XCH A,@R0 1 12 +0xc7 XCH A,@R1 1 12 +0xc8 XCH A,R0 1 12 +0xc9 XCH A,R1 1 12 +0xca XCH A,R2 1 12 +0xcb XCH A,R3 1 12 +0xcc XCH A,R4 1 12 +0xcd XCH A,R5 1 12 +0xce XCH A,R6 1 12 +0xcf XCH A,R7 1 12 +0xd0 POP addr 2 24 +0xd1 ACALL addr 2 24 +0xd2 SETB addr 2 12 +0xd3 SETB C 1 12 +0xd4 DA A 1 12 +0xd5 DJNZ addr,addr 3 24 +0xd6 XCHD A,@R0 1 12 +0xd7 XCHD A,@R1 1 12 +0xd8 DJNZ R0,addr 2 24 +0xd9 DJNZ R1,addr 2 24 +0xda DJNZ R2,addr 2 24 +0xdb DJNZ R3,addr 2 24 +0xdc DJNZ R4,addr 2 24 +0xdd DJNZ R5,addr 2 24 +0xde DJNZ R6,addr 2 24 +0xdf DJNZ R7,addr 2 24 +0xe0 MOVX A,@DPTR 1 24 +0xe1 AJMP addr 2 24 +0xe2 MOVX A,@R0 1 24 +0xe3 MOVX A,@R1 1 24 +0xe4 CLR A 1 12 +0xe5 MOV A,addr 2 12 +0xe6 MOV A,@R0 1 12 +0xe7 MOV A,@R1 1 12 +0xe8 MOV A,R0 1 12 +0xe9 MOV A,R1 1 12 +0xea MOV A,R2 1 12 +0xeb MOV A,R3 1 12 +0xec MOV A,R4 1 12 +0xed MOV A,R5 1 12 +0xee MOV A,R6 1 12 +0xef MOV A,R7 1 12 +0xf0 MOVX @DPTR,A 1 24 +0xf1 ACALL addr 2 24 +0xf2 MOVX @R0,A 1 24 +0xf3 MOVX @R1,A 1 24 +0xf4 CPL A 1 12 +0xf5 MOV addr,A 2 12 +0xf6 MOV @R0,A 1 12 +0xf7 MOV @R1,A 1 12 +0xf8 MOV R0,A 1 12 +0xf9 MOV R1,A 1 12 +0xfa MOV R2,A 1 12 +0xfb MOV R3,A 1 12 +0xfc MOV R4,A 1 12 +0xfd MOV R5,A 1 12 +0xfe MOV R6,A 1 12 +0xff MOV R7,A 1 12 diff --git a/sim/ucsim/s51.src/interrupt.cc b/sim/ucsim/s51.src/interrupt.cc new file mode 100644 index 00000000..cbbcb66d --- /dev/null +++ b/sim/ucsim/s51.src/interrupt.cc @@ -0,0 +1,85 @@ +/* + * Simulator of microcontrollers (interrupt.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +// sim +#include "itsrccl.h" + +// local +#include "interruptcl.h" +#include "regs51.h" + + +cl_interrupt::cl_interrupt(class cl_uc *auc): + cl_hw(auc, HW_INTERRUPT, 0, "irq") +{} + +/*int +cl_interrupt::init(void) +{ + return(0); +}*/ + +void +cl_interrupt::print_info(class cl_console *con) +{ + int ie= uc->get_mem(MEM_SFR, IE); + int i; + + con->printf("Interrupts are %s. Interrupt sources:\n", + (ie&bmEA)?"enabled":"disabled"); + con->printf(" Handler En Pr Req Act Name\n"); + for (i= 0; i < uc->it_sources->count; i++) + { + class cl_it_src *is= (class cl_it_src *)(uc->it_sources->at(i)); + con->printf(" 0x%06x", is->addr); + con->printf(" %-3s", (ie&(is->ie_mask))?"en":"dis"); + con->printf(" %2d", uc->it_priority(is->ie_mask)); + con->printf(" %-3s", + (uc->get_mem(MEM_SFR, is->src_reg)&(is->src_mask))? + "YES":"no"); + con->printf(" %-3s", (is->active)?"act":"no"); + con->printf(" %s", is->name); + con->printf("\n"); + } + con->printf("Active interrupt service(s):\n"); + con->printf(" Pr Handler PC Source\n"); + for (i= 0; i < uc->it_levels->count; i++) + { + class it_level *il= (class it_level *)(uc->it_levels->at(i)); + if (il->level >= 0) + { + con->printf(" %2d", il->level); + con->printf(" 0x%06x", il->addr); + con->printf(" 0x%06x", il->PC); + con->printf(" %s", (il->source)?(il->source->name):"nothing"); + con->printf("\n"); + } + } +} + + +/* End of s51.src/interrupt.cc */ diff --git a/sim/ucsim/s51.src/interruptcl.h b/sim/ucsim/s51.src/interruptcl.h new file mode 100644 index 00000000..04001797 --- /dev/null +++ b/sim/ucsim/s51.src/interruptcl.h @@ -0,0 +1,54 @@ +/* + * Simulator of microcontrollers (interruptcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef INTERRUPTCL_HEADER +#define INTERRUPTCL_HEADER + +#include "stypes.h" +#include "pobjcl.h" +#include "uccl.h" + +#include "newcmdcl.h" + + +class cl_interrupt: public cl_hw +{ +public: + cl_interrupt(class cl_uc *auc); + //virtual int init(void); + + //virtual ulong read(class cl_mem *mem, long addr); + //virtual void write(class cl_mem *mem, long addr, ulong *val); + + //virtual int tick(int cycles); + virtual void print_info(class cl_console *con); +}; + + +#endif + +/* End of s51.src/interruptcl.h */ diff --git a/sim/ucsim/s51.src/jmp.cc b/sim/ucsim/s51.src/jmp.cc new file mode 100644 index 00000000..d66b05a0 --- /dev/null +++ b/sim/ucsim/s51.src/jmp.cc @@ -0,0 +1,531 @@ +/* + * Simulator of microcontrollers (jmp.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +/* Bugs fixed by Sandeep Dutta: + * relative<->absolute jump in "jmp @a+dptr" + */ + +#include "ddconfig.h" + +#include +#include + +// local +#include "uc51cl.h" +#include "regs51.h" + + +/* + * 0x[02468ace]1 2 24 AJMP addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_ajmp_addr(uchar code) +{ + uchar h, l; + + h= (code >> 5) & 0x07; + l= fetch(); + tick(1); + PC= (PC & 0xf800) | (h*256 + l); + return(resGO); +} + + +/* + * 0x10 3 12 JBC bit,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_jbc_bit_addr(uchar code) +{ + uchar bitaddr, *addr, jaddr; + + bitaddr= fetch(); + jaddr = fetch(); + addr = get_bit(bitaddr, &event_at.ri, &event_at.rs); + if (*addr & BIT_MASK(bitaddr)) + { + (*addr)&= ~BIT_MASK(bitaddr); + PC= (PC + (signed char)jaddr) & (EROM_SIZE - 1); + } + return(resGO); +} + + +/* + * 0x02 3 24 LJMP addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_ljmp(uchar code) +{ + PC= fetch()*256 + fetch(); + tick(1); + return(resGO); +} + + +/* + * 0x[13579bdf]1 2 24 ACALL addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_acall_addr(uchar code) +{ + uchar h, l, *sp, *aof_SP; + int res; + + h= (code >> 5) & 0x07; + l= fetch(); + aof_SP= &((sfr->umem8)[SP]); + //MEM(MEM_SFR)[SP]++; + (*aof_SP)++; + proc_write_sp(*aof_SP); + sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res); + if (res != resGO) + res= resSTACK_OV; + (*sp)= PC & 0xff; // push low byte + tick(1); + + //MEM(MEM_SFR)[SP]++; + (*aof_SP)++; + proc_write_sp(*aof_SP); + sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res); + if (res != resGO) + res= resSTACK_OV; + (*sp)= (PC >> 8) & 0xff; // push high byte + PC= (PC & 0xf800) | (h*256 + l); + return(res); +} + + +/* + * 0x12 3 24 LCALL addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_lcall(uchar code, uint addr) +{ + uchar h= 0, l= 0, *sp, *aof_SP; + int res; + + if (!addr) + { + h= fetch(); + l= fetch(); + } + aof_SP= &((sfr->umem8)[SP]); + //MEM(MEM_SFR)[SP]++; + (*aof_SP)++; + proc_write_sp(*aof_SP); + sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res); + if (res != resGO) + res= resSTACK_OV; + (*sp)= PC & 0xff; // push low byte + if (!addr) + tick(1); + + //MEM(MEM_SFR)[SP]++; + (*aof_SP)++; + proc_write_sp(*aof_SP); + sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res); + if (res != resGO) + res= resSTACK_OV; + (*sp)= (PC >> 8) & 0xff; // push high byte + if (addr) + PC= addr; + else + PC= h*256 + l; + return(res); +} + + +/* + * 0x20 3 24 JB bit,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_jb_bit_addr(uchar code) +{ + uchar *addr, bitaddr, jaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.ri, &event_at.rs); + tick(1); + jaddr= fetch(); + if (read(addr) & BIT_MASK(bitaddr)) + PC= (PC + (signed char)jaddr) & (EROM_SIZE-1); + return(resGO); +} + + +/* + * 0x22 1 24 RET + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_ret(uchar code) +{ + uchar h, l, *sp, *aof_SP; + int res; + + aof_SP= &((sfr->umem8)[SP]); + sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res); + if (res != resGO) + res= resSTACK_OV; + h= *sp; + //MEM(MEM_SFR)[SP]--; + (*aof_SP)--; + proc_write_sp(*aof_SP); + tick(1); + + sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res); + if (res != resGO) + res= resSTACK_OV; + l= *sp; + //MEM(MEM_SFR)[SP]--; + (*aof_SP)--; + proc_write_sp(*aof_SP); + PC= h*256 + l; + return(res); +} + + +/* + * 0x30 3 24 JNB bit,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_jnb_bit_addr(uchar code) +{ + uchar *addr, bitaddr, jaddr; + + addr= get_bit(bitaddr= fetch(), &event_at.ri, &event_at.rs); + tick(1); + jaddr= fetch(); + if (!(read(addr) & BIT_MASK(bitaddr))) + PC= (PC + (signed char)jaddr) & (get_mem_size(MEM_ROM)-1); + return(resGO); +} + + +/* + * 0x32 1 24 RETI + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_reti(uchar code) +{ + uchar h, l, *sp, *aof_SP; + int res; + + aof_SP= &((sfr->umem8)[SP]); + sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res); + if (res != resGO) + res= resSTACK_OV; + h= *sp; + //MEM(MEM_SFR)[SP]--; + (*aof_SP)--; + proc_write_sp(*aof_SP); + tick(1); + + sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res); + if (res != resGO) + res= resSTACK_OV; + l= *sp; + //MEM(MEM_SFR)[SP]--; + (*aof_SP)--; + proc_write_sp(*aof_SP); + PC= h*256 + l; + + was_reti= TRUE; + class it_level *il= (class it_level *)(it_levels->top()); + if (il && + il->level >= 0) + { + il= (class it_level *)(it_levels->pop()); + delete il; + } + return(res); +} + + +/* + * 0x40 2 24 JC addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_jc_addr(uchar code) +{ + uchar jaddr; + + jaddr= fetch(); + tick(1); + if (GET_C) + PC= (PC + (signed char)jaddr) & (EROM_SIZE-1); + event_at.rs= PSW; + return(resGO); +} + + +/* + * 0x50 2 24 JNC addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_jnc_addr(uchar code) +{ + uchar jaddr; + + jaddr= fetch(); + tick(1); + if (!GET_C) + PC= (PC + (signed char)jaddr) & (EROM_SIZE-1); + event_at.rs= ACC; + return(resGO); +} + + +/* + * 0x60 2 24 JZ addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_jz_addr(uchar code) +{ + uchar jaddr; + + jaddr= fetch(); + tick(1); + if (!sfr->get(ACC)) + PC= (PC + (signed char)jaddr) & (EROM_SIZE-1); + return(resGO); +} + + +/* + * 0x70 2 24 JNZ addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_jnz_addr(uchar code) +{ + uchar jaddr; + + jaddr= fetch(); + tick(1); + if (sfr->get(ACC)) + PC= (PC + (signed char)jaddr) & (EROM_SIZE-1); + return(resGO); +} + + +/* + * 0x73 1 24 JMP @A+DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_jmp_$a_dptr(uchar code) +{ + PC= (sfr->get(DPH)*256 + sfr->get(DPL) + + read_mem(MEM_SFR, ACC)) & + (EROM_SIZE - 1); + return(resGO); +} + + +/* + * 0x80 2 24 SJMP addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_sjmp(uchar code) +{ + signed char target= fetch(); + PC= (PC + target) & (EROM_SIZE -1); + tick(1); + return(resGO); +} + + +/* + * 0xb4 3 24 CJNE A,#data,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_cjne_a_$data_addr(uchar code) +{ + uchar data, jaddr; + + data = fetch(); + jaddr= fetch(); + tick(1); + SET_C(sfr->get(ACC) < data); + if (read_mem(MEM_SFR, event_at.rs= ACC) != data) + PC= (PC + (signed char)jaddr) & (EROM_SIZE - 1); + return(resGO); +} + + +/* + * 0xb5 3 24 CJNE A,addr,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_cjne_a_addr_addr(uchar code) +{ + uchar data, *addr, jaddr; + + addr = get_direct(fetch(), &event_at.ri, &event_at.rs); + jaddr= fetch(); + tick(1); + data= read(addr); + SET_C(sfr->get(ACC) < data); + if (sfr->get(event_at.rs= ACC) != data) + PC= (PC + (signed char)jaddr) & (EROM_SIZE - 1); + return(resGO); +} + + +/* + * 0xb6-0xb7 3 24 CJNE @Ri,#data,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_cjne_$ri_$data_addr(uchar code) +{ + uchar *addr, data, jaddr; + int res; + + addr = get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + data = fetch(); + jaddr= fetch(); + tick(1); + SET_C(*addr < data); + if (*addr != data) + PC= (PC + (signed char)jaddr) & (EROM_SIZE - 1); + return(res); +} + + +/* + * 0xb8-0xbf 3 24 CJNE Rn,#data,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_cjne_rn_$data_addr(uchar code) +{ + uchar *reg, data, jaddr; + + reg = get_reg(code & 0x07, &event_at.ri); + data = fetch(); + jaddr= fetch(); + tick(1); + SET_C(*reg < data); + if (*reg != data) + PC= (PC + (signed char)jaddr) & (EROM_SIZE - 1); + return(resGO); +} + + +/* + * 0xd5 3 24 DJNZ addr,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_djnz_addr_addr(uchar code) +{ + uchar *addr, jaddr; + + addr = get_direct(fetch(), &event_at.wi, &event_at.ws); + jaddr= fetch(); + if (--(*addr)) + PC= (PC + (signed char)jaddr) & (EROM_SIZE-1); + return(resGO); +} + + +/* + * 0xd8-0xdf 2 24 DJNZ Rn,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_djnz_rn_addr(uchar code) +{ + uchar *reg, jaddr; + + reg = get_reg(code & 0x07, &event_at.wi); + jaddr= fetch(); + if (--(*reg)) + PC= (PC + (signed char)jaddr) & (EROM_SIZE-1); + return(resGO); +} + + +/* End of s51.src/jmp.cc */ diff --git a/sim/ucsim/s51.src/logic.cc b/sim/ucsim/s51.src/logic.cc new file mode 100644 index 00000000..32e936b9 --- /dev/null +++ b/sim/ucsim/s51.src/logic.cc @@ -0,0 +1,377 @@ +/* + * Simulator of microcontrollers (logic.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// prj +#include "stypes.h" + +// local +#include "uc51cl.h" +#include "regs51.h" + + +/* + * 0x42 2 12 ORL addr,A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_orl_addr_a(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)|= sfr->get(event_at.rs= ACC); + proc_write(addr); + return(resGO); +} + + +/* + * 0x43 3 24 ORL addr,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_orl_addr_$data(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)|= fetch(); + proc_write(addr); + tick(1); + return(resGO); +} + + +/* + * 0x44 2 12 ORL A,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_orl_a_$data(uchar code) +{ + uchar d; + + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d|= fetch()); + return(resGO); +} + + +/* + * 0x45 2 12 ORL A,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_orl_a_addr(uchar code) +{ + uchar *addr, d; + + addr= get_direct(fetch(), &event_at.ri, &event_at.rs); + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d|= read(addr)); + return(resGO); +} + + +/* + * 0x46-0x47 1 12 ORL A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_orl_a_$ri(uchar code) +{ + uchar *addr, d; + int res; + + addr= get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d|= *addr); + return(res); +} + + +/* + * 0x48-0x4f 1 12 ORL A,Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_orl_a_rn(uchar code) +{ + uchar d; + + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d|= *(get_reg(code & 0x07, &event_at.ri))); + return(resGO); +} + + +/* + * 0x52 2 12 ANL addr,A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_anl_addr_a(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)&= sfr->get(event_at.rs= ACC); + proc_write(addr); + return(resGO); +} + + +/* + * 0x53 3 24 ANL addr,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_anl_addr_$data(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)&= fetch(); + proc_write(addr); + tick(1); + return(resGO); +} + + +/* + * 0x54 2 12 ANL A,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_anl_a_$data(uchar code) +{ + uchar d; + + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d&= fetch()); + return(resGO); +} + + +/* + * 0x55 2 12 ANL A,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_anl_a_addr(uchar code) +{ + uchar *addr, d; + + addr= get_direct(fetch(), &event_at.ri, &event_at.rs); + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d&= read(addr)); + return(resGO); +} + + +/* + * 0x56-0x57 1 12 ANL A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_anl_a_$ri(uchar code) +{ + uchar *addr, d; + int res; + + addr= get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d&= *addr); + return(res); +} + + +/* + * 0x58-0x5f 1 12 ANL A,Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_anl_a_rn(uchar code) +{ + uchar d; + + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d&= *(get_reg(code & 0x07, &event_at.ri))); + return(resGO); +} + + +/* + * 0x62 2 12 XRL addr,A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xrl_addr_a(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)^= sfr->get(event_at.rs= ACC); + proc_write(addr); + return(resGO); +} + + +/* + * 0x63 3 24 XRL addr,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xrl_addr_$data(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)^= fetch(); + proc_write(addr); + tick(1); + return(resGO); +} + + +/* + * 0x64 2 12 XRL A,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xrl_a_$data(uchar code) +{ + uchar d; + + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d^= fetch()); + return(resGO); +} + + +/* + * 0x65 2 12 XRL A,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xrl_a_addr(uchar code) +{ + uchar d; + + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d^= read(get_direct(fetch(), + &event_at.ri, + &event_at.ri))); + return(resGO); +} + + +/* + * 0x66-0x67 1 12 XRL A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xrl_a_$ri(uchar code) +{ + uchar *addr, d; + int res; + + addr= get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d^= *addr); + return(res); +} + + +/* + * 0x68-0x6f 1 12 XRL A,Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xrl_a_rn(uchar code) +{ + uchar d; + + d= sfr->get(event_at.ws= ACC); + sfr->set(ACC, d^= *(get_reg(code & 0x07, &event_at.ri))); + return(resGO); +} + + +/* + * 0xf4 1 12 CPL A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_cpl_a(uchar code) +{ + sfr->set(event_at.ws= ACC, ~(sfr->get(ACC))); + return(resGO); +} + + +/* End of s51.src/logic.cc */ diff --git a/sim/ucsim/s51.src/lst2ls b/sim/ucsim/s51.src/lst2ls new file mode 100755 index 00000000..2bd27524 --- /dev/null +++ b/sim/ucsim/s51.src/lst2ls @@ -0,0 +1,23 @@ +FNAME=$1 + +awk -v FNAME=$FNAME 'BEGIN { + cfname= FNAME ".c"; + i= 1; + while (getline csrc[i] ${FNAME}.ls + +# End of lst2ls + diff --git a/sim/ucsim/s51.src/monitor1-2 b/sim/ucsim/s51.src/monitor1-2 new file mode 100755 index 00000000..1c3685d3 --- /dev/null +++ b/sim/ucsim/s51.src/monitor1-2 @@ -0,0 +1,5 @@ +#!/bin/sh + +cat 1_tee|tee /dev/tty >tee_2 + +# End of monitor1-2 diff --git a/sim/ucsim/s51.src/monitor2-1 b/sim/ucsim/s51.src/monitor2-1 new file mode 100755 index 00000000..07def21f --- /dev/null +++ b/sim/ucsim/s51.src/monitor2-1 @@ -0,0 +1,5 @@ +#!/bin/sh + +cat 2_tee|tee /dev/tty >tee_1 + +# End of monitor2-1 diff --git a/sim/ucsim/s51.src/mov.cc b/sim/ucsim/s51.src/mov.cc new file mode 100644 index 00000000..c324ff59 --- /dev/null +++ b/sim/ucsim/s51.src/mov.cc @@ -0,0 +1,565 @@ +/* + * Simulator of microcontrollers (mov.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +/* Bugs fixed by Sandeep Dutta: + * source<->dest bug in "mov direct,direct" + * get register in "mov @ri,address" + */ + +#include "ddconfig.h" + +#include + +// sim +#include "memcl.h" + +// local +#include "uc51cl.h" +#include "regs51.h" + + +/* + * 0x74 2 12 MOV A,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_a_$data(uchar code) +{ + sfr->set(event_at.ws= ACC, fetch()); + return(resGO); +} + + +/* + * 0x75 3 24 MOV addr,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_addr_$data(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)= fetch(); + proc_write(addr); + tick(1); + return(resGO); +} + + +/* + * 0x76-0x77 2 12 MOV @Ri,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_$ri_$data(uchar code) +{ + uchar *addr; + int res; + + addr= get_indirect(event_at.wi= *(get_reg(code & 0x01)), &res); + (*addr)= fetch(); + proc_write(addr); + return(res); +} + + +/* + * 0x78-0x7f 2 12 MOV Rn,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_rn_$data(uchar code) +{ + uchar *reg; + + reg= get_reg(code & 0x07, &event_at.wi); + (*reg)= fetch(); + return(resGO); +} + + +/* + * 0x93 1 24 MOVC A,@A+DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_movc_a_$a_pc(uchar code) +{ + //SFR[ACC]= EROM[event_at.rc= (PC + SFR[ACC]) & (EROM_SIZE - 1)]; + sfr->set(ACC, + mem(MEM_ROM)->get(event_at.rc= + (PC + sfr->get(ACC)))&(EROM_SIZE - 1)); + tick(1); + return(resGO); +} + + +/* + * 0x85 3 24 MOV addr,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_addr_addr(uchar code) +{ + uchar *d, *s; + + /* SD reversed s & d here */ + s= get_direct(fetch(), &event_at.ri, &event_at.rs); + d= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*d)= read(s); + proc_write(d); + tick(1); + return(resGO); +} + + +/* + * 0x86-0x87 2 24 MOV addr,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_addr_$ri(uchar code) +{ + uchar *d, *s; + int res; + + d= get_direct(fetch(), &event_at.wi, &event_at.ws); + s= get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + *d= *s; + proc_write(d); + tick(1); + return(res); +} + + +/* + * 0x88-0x8f 2 24 MOV addr,Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_addr_rn(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)= *(get_reg(code & 0x07, &event_at.ri)); + proc_write(addr); + tick(1); + return(resGO); +} + + +/* + * 0x90 3 24 MOV DPTR,#data + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_dptr_$data(uchar code) +{ + sfr->set(event_at.ws= DPH, fetch()); + sfr->set(DPL, fetch()); + tick(1); + return(resGO); +} + + +/* + * 0x93 1 24 MOVC A,@A+DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_movc_a_$a_dptr(uchar code) +{ + //SFR[ACC]= EROM[event_at.rc= (SFR[DPH]*256+SFR[DPL]+SFR[ACC])&(EROM_SIZE-1)]; + sfr->set(ACC, get_mem(MEM_ROM, event_at.rc= + (sfr->get(DPH)*256+sfr->get(DPL) + + sfr->get(ACC)) & (EROM_SIZE-1))); + tick(1); + return(resGO); +} + + +/* + * 0xa6-0xa7 2 24 MOV @Ri,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_$ri_addr(uchar code) +{ + uchar *d, *s; + int res; + + d= get_indirect(event_at.wi= *(get_reg(code & 0x01)), &res); + s= get_direct(fetch(), &event_at.ri, &event_at.rs); + (*d)= read(s); + tick(1); + return(res); +} + + +/* + * 0xa8-0xaf 2 24 MOV Rn,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_rn_addr(uchar code) +{ + uchar *reg, *addr; + + reg = get_reg(code & 0x07, &event_at.wi); + addr= get_direct(fetch(), &event_at.ri, &event_at.rs); + (*reg)= read(addr); + tick(1); + return(resGO); +} + + +/* + * 0xc0 2 24 PUSH addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_push(uchar code) +{ + uchar *addr, *sp; + int res; + + addr= get_direct(fetch(), &event_at.ri, &event_at.rs); + MEM(MEM_SFR)[SP]++; + sp= get_indirect(sfr->get(SP), &res); + if (res != resGO) + res= resSTACK_OV; + (*sp)= read(addr); + tick(1); + return(res); +} + + +/* + * 0xc5 2 12 XCH A,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xch_a_addr(uchar code) +{ + uchar temp, *addr; + + addr= get_direct(fetch(), &event_at.ri, &event_at.rs); + temp= sfr->get(ACC); + sfr->set(event_at.ws= ACC, read(addr)); + (*addr)= temp; + proc_write(addr); + return(resGO); +} + + +/* + * 0xc6-0xc7 1 12 XCH A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xch_a_$ri(uchar code) +{ + uchar temp, *addr; + int res; + + addr= get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + temp= sfr->get(ACC); + sfr->set(event_at.ws= ACC, *addr); + (*addr)= temp; + return(res); +} + + +/* + * 0xc8-0xcf 1 12 XCH A,Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xch_a_rn(uchar code) +{ + uchar temp, *reg; + + reg = get_reg(code & 0x07, &event_at.ri); + temp= sfr->get(ACC); + sfr->set(event_at.wi= ACC, *reg); + (*reg)= temp; + return(resGO); +} + + +/* + * 0xd0 2 24 POP addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_pop(uchar code) +{ + uchar *addr, *sp; + int res; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + sp= get_indirect(get_mem(MEM_SFR, SP), &res); + if (res != resGO) + res= resSTACK_OV; + MEM(MEM_SFR)[SP]--; + (*addr)= *sp; + proc_write(addr); + tick(1); + return(res); +} + + +/* + * 0xd6-0xd7 1 12 XCHD A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_xchd_a_$ri(uchar code) +{ + uchar *addr, temp; + int res; + + addr= get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + temp= *addr & 0x0f; + (*addr) = (*addr & 0xf0) | (sfr->get(ACC) & 0x0f); + sfr->set(event_at.ws= ACC, (sfr->get(ACC) & 0xf0) | temp); + return(res); +} + + +/* + * 0xe0 1 24 MOVX A,@DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_movx_a_$dptr(uchar code) +{ + sfr->set(event_at.ws= ACC, + get_mem(MEM_XRAM, event_at.rx=sfr->get(DPH)*256+sfr->get(DPL))); + tick(1); + return(resGO); +} + + +/* + * 0xe2-0xe3 1 24 MOVX A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_movx_a_$ri(uchar code) +{ + uchar *addr; + + addr= get_reg(code & 0x01); + sfr->set(event_at.ws= ACC, + read_mem(MEM_XRAM, + event_at.rx= (sfr->get(P2)&port_pins[2])*256+*addr)); + tick(1); + return(resGO); +} + + +/* + * 0xe5 2 12 MOV A,addr + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_a_addr(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.ri, &event_at.rs); + sfr->set(event_at.ws= ACC, read(addr)); + return(resGO); +} + + +/* + * 0xe6-0xe7 1 12 MOV A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_a_$ri(uchar code) +{ + uchar *addr; + int res; + + addr= get_indirect(event_at.ri= *(get_reg(code & 0x01)), &res); + sfr->set(event_at.ws= ACC, *addr); + return(res); +} + + +/* + * 0xe8-0xef 1 12 MOV A,Rn + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_a_rn(uchar code) +{ + sfr->set(event_at.ws= ACC, *(get_reg(code & 0x07, &event_at.ri))); + return(resGO); +} + + +/* + * 0xf0 1 24 MOVX @DPTR,A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_movx_$dptr_a(uchar code) +{ + set_mem(MEM_XRAM, event_at.wx= sfr->get(DPH)*256+sfr->get(DPL), + sfr->get(event_at.rs= ACC)); + return(resGO); +} + + +/* + * 0xf2-0xf3 1 24 MOVX @Ri,A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_movx_$ri_a(uchar code) +{ + uchar *addr; + + addr= get_reg(code & 0x01); + set_mem(MEM_XRAM, + event_at.wx= (sfr->get(P2) & port_pins[2])*256 + *addr, + sfr->get(ACC)); + tick(1); + return(resGO); +} + + +/* + * 0xf5 2 12 MOV addr,A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_addr_a(uchar code) +{ + uchar *addr; + + addr= get_direct(fetch(), &event_at.wi, &event_at.ws); + (*addr)= sfr->get(event_at.rs= ACC); + proc_write(addr); + return(resGO); +} + + +/* + * 0xf6-0xf7 1 12 MOV @Ri,A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_$ri_a(uchar code) +{ + uchar *addr; + int res; + + addr= get_indirect(event_at.wi= *(get_reg(code & 0x01)), &res); + (*addr)= sfr->get(event_at.rs= ACC); + return(res); +} + + +/* + * 0xf8-0xff 1 12 MOV Rn,A + *____________________________________________________________________________ + * + */ + +int +t_uc51::inst_mov_rn_a(uchar code) +{ + uchar *reg; + + reg= get_reg(code &0x07, &event_at.wi); + (*reg)= sfr->get(event_at.rs= ACC); + return(resGO); +} + + +/* End of s51.src/mov.cc */ diff --git a/sim/ucsim/s51.src/port.cc b/sim/ucsim/s51.src/port.cc new file mode 100644 index 00000000..3367c724 --- /dev/null +++ b/sim/ucsim/s51.src/port.cc @@ -0,0 +1,78 @@ +/* + * Simulator of microcontrollers (port.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include + +#include "portcl.h" +#include "regs51.h" + + +cl_port::cl_port(class cl_uc *auc, int aid): + cl_hw(auc, HW_PORT, aid, "port") +{} + +int +cl_port::init(void) +{ + switch (id) + { + case 0: sfr= P0; break; + case 1: sfr= P1; break; + case 2: sfr= P2; break; + case 3: sfr= P3; break; + default: sfr= P0; return(1); + } + return(0); +} + +void +cl_port::print_info(class cl_console *con) +{ + uchar data; + + con->printf("%s[%d]\n", id_string, id); + data= uc->get_mem(MEM_SFR, sfr); + con->printf("P%d ", id); + con->print_bin(data, 8); + con->printf(" 0x%02x %3d %c (Value in SFR register)\n", + data, data, isprint(data)?data:'.'); + + data= uc->port_pins[id]; + con->printf("Pin%d ", id); + con->print_bin(data, 8); + con->printf(" 0x%02x %3d %c (Output of outside circuits)\n", + data, data, isprint(data)?data:'.'); + + data= uc->port_pins[id] & uc->get_mem(MEM_SFR, sfr); + con->printf("Port%d ", id); + con->print_bin(data, 8); + con->printf(" 0x%02x %3d %c (Value on the port pins)\n", + data, data, isprint(data)?data:'.'); +} + + +/* End of s51.src/port.cc */ diff --git a/sim/ucsim/s51.src/portcl.h b/sim/ucsim/s51.src/portcl.h new file mode 100644 index 00000000..87a6f7d5 --- /dev/null +++ b/sim/ucsim/s51.src/portcl.h @@ -0,0 +1,57 @@ +/* + * Simulator of microcontrollers (portcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef PORTCL_HEADER +#define PORTCL_HEADER + +#include "stypes.h" +#include "pobjcl.h" +#include "uccl.h" + +#include "newcmdcl.h" + + +class cl_port: public cl_hw +{ +public: + int sfr; + +public: + cl_port(class cl_uc *auc, int aid); + virtual int init(void); + + //virtual ulong read(class cl_mem *mem, long addr); + //virtual void write(class cl_mem *mem, long addr, ulong *val); + + //virtual int tick(int cycles); + virtual void print_info(class cl_console *con); +}; + + +#endif + +/* End of s51.src/portcl.h */ diff --git a/sim/ucsim/s51.src/regs51.h b/sim/ucsim/s51.src/regs51.h new file mode 100644 index 00000000..fbea3a95 --- /dev/null +++ b/sim/ucsim/s51.src/regs51.h @@ -0,0 +1,320 @@ +/* + * Simulator of microcontrollers (regs51.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef REGS51_HEADER +#define REGS51_HEADER + + +/* Address of SFR registers */ + +#define ACC 0xe0 /* Accumulator */ +#define B 0xf0 /* B register (scondary accumulator) */ +#define PSW 0xd0 /* Program Status Word */ +#define SP 0x81 /* Stack Pointer */ +#define DPL 0x82 /* Data Pointer Low byte */ +#define DPH 0x83 /* Data Pointer High byte */ +#define P0 0x80 /* Port #0 */ +#define P1 0x90 /* Port #1 */ +#define P2 0xa0 /* Port #2 */ +#define P3 0xb0 /* Port #3 */ +#define IP 0xb8 /* Intrrupt Priority */ +#define IE 0xa8 /* Interrupt Enable */ +#define TMOD 0x89 /* Timer MODe */ +#define TCON 0x88 /* Timer CONtrol */ +#define T2CON 0xc8 /* Timer #2 CONtrol */ +#define TH0 0x8c /* Timer #0 High byte */ +#define TL0 0x8a /* Timer #0 Low byte */ +#define TH1 0x8d /* Timer #1 High byte */ +#define TL1 0x8b /* Timer #1 Low byte */ +#define SCON 0x98 /* Serial line CONtrol */ +#define TH2 0xcd /* Timer #2 High byte */ +#define TL2 0xcc /* Timer #2 Low byte */ +#define RCAP2H 0xcb /* Capture Register of Timer #2 High byte */ +#define RCAP2L 0xca /* Capture Register of Timer #2 Low byte */ +#define SBUF 0x99 /* Serial line BUFfer */ +#define PCON 0x87 /* Power CONtrol */ + +#define AUXR 0x8e /* Auxiliary Register */ +#define AUXR1 0xa2 /* Secondary Aux Register */ + +#define DPXL 0x84 /* */ +#define WDTRST 0xa6 /* */ +#define IE0 0xa8 /* */ +#define SADDR 0xa9 /* */ +#define IPH0 0xb7 /* */ +#define IPH 0xb7 +#define IPL0 0xb8 /* */ +#define SADEN 0xb9 /* */ +#define SPH 0xbd /* */ +#define T2MOD 0xc9 /* */ +#define PSW1 0xd1 /* */ +#define CCON 0xd8 /* */ +#define CMOD 0xd9 /* */ +#define CCAPM0 0xda /* */ +#define CCAPM1 0xdb /* */ +#define CCAPM2 0xdc /* */ +#define CCAPM3 0xdd /* */ +#define CCAPM4 0xde /* */ +#define CL 0xe9 /* */ +#define CCAP0L 0xea /* */ +#define CCAP1L 0xeb /* */ +#define CCAP2L 0xec /* */ +#define CCAP3L 0xed /* */ +#define CCAP4L 0xee /* */ +#define CH 0xf9 /* */ +#define CCAP0H 0xfa /* */ +#define CCAP1H 0xfb /* */ +#define CCAP2H 0xfc /* */ +#define CCAP3H 0xfd /* */ +#define CCAP4H 0xfe /* */ + +/* Bit masks of flag bits in PSW (0xd0)*/ + +#define bmCY 0x80 /* carry */ +#define bmAC 0x40 /* acarry */ +#define bmF0 0x20 /* flag 0 */ +#define bmRS1 0x10 /* register select 1 */ +#define bmRS0 0x08 /* register select 0 */ +#define bmOV 0x04 /* arithmetic overflow */ +#define bmP 0x01 /* parity, set by hardware */ + +/* Bit masks in PCON (0x87) */ + +#define bmSMOD1 0x80 +#define bmSMOD 0x80 +#define bmSMOD0 0x40 +#define bmPOF 0x10 +#define bmGF1 0x08 +#define bmGF0 0x04 +#define bmPD 0x02 +#define bmIDL 0x01 + +/* Bit masks in IE (0xa8) */ + +#define bmEA 0x80 +#define bmEC 0x40 +#define bmET2 0x20 +#define bmES 0x10 +#define bmET1 0x08 +#define bmEX1 0x04 +#define bmET0 0x02 +#define bmEX0 0x01 + +/* Bit masks in IP (0xb8) */ + +#define bmPPC 0x40 +#define bmPT2 0x20 +#define bmPS 0x10 +#define bmPT1 0x08 +#define bmPX1 0x04 +#define bmPT0 0x02 +#define bmPX0 0x01 + +/* Bit masks in IPL0 (0xb8) */ + +#define bmIPL0_6 0x40 +#define bmIPL0_5 0x20 +#define bmIPL0_4 0x10 +#define bmIPL0_3 0x08 +#define bmIPL0_2 0x04 +#define bmIPL0_1 0x02 +#define bmIPL0_0 0x01 + +/* Bit masks in IPH0 (0xb7) */ + +#define bmIPH0_6 0x40 +#define bmIPH0_5 0x20 +#define bmIPH0_4 0x10 +#define bmIPH0_3 0x08 +#define bmIPH0_2 0x04 +#define bmIPH0_1 0x02 +#define bmIPH0_0 0x01 + +/* Bit masks in P1 (0x90) */ + +#define bmCEX4 0x80 +#define bmCEX3 0x40 +#define bmCEX2 0x20 +#define bmCEX1 0x10 +#define bmCEX0 0x08 +#define bmECI 0x04 +#define bmT2EX 0x02 +#define bmT2 0x01 + +/* Bit masks in P3 (0xb0) */ + +#define bmRXD 0x01 +#define bmTXD 0x02 +#define bm_INT0 0x04 +#define bm_INT1 0x08 +#define bmT0 0x10 +#define bmT1 0x20 +#define bm_WR 0x40 +#define bm_RD 0x80 + +/* Bit masks in TMOD (0x89) */ + +#define bmGATE1 0x80 +#define bmC_T1 0x40 +#define bmM11 0x20 +#define bmM01 0x10 +#define bmGATE0 0x08 +#define bmC_T0 0x04 +#define bmM10 0x02 +#define bmM00 0x01 + +/* Bit masks in TCON (0x88) */ + +#define bmTF1 0x80 +#define bmTR1 0x40 +#define bmTF0 0x20 +#define bmTR0 0x10 +#define bmIE1 0x08 +#define bmIT1 0x04 +#define bmIE0 0x02 +#define bmIT0 0x01 + +/* Bit masks in AUXR (0x8e) */ + +#define bmEXTRAM 0x02 +#define bmDISABLE 0x01 + +/* Bit masks in AUXR1 (0xa2) */ + +#define bmENBOOT 0x20 +#define bmGF2 0x08 +#define bmDPS 0x01 + +/* Bit masks in T2CON (0xc8) */ + +#define bmTF2 0x80 +#define bmEXF2 0x40 +#define bmRCLK 0x20 +#define bmTCLK 0x10 +#define bmEXEN2 0x08 +#define bmTR2 0x04 +#define bmC_T2 0x02 +#define bmCP_RL2 0x01 + +/* Bit masks in SCON (0x98) */ + +#define bmFE_SM0 0x80 +#define bmFE 0x80 +#define bmSM0 0x80 +#define bmSM1 0x40 +#define bmSM2 0x20 +#define bmREN 0x10 +#define bmTB8 0x08 +#define bmRB8 0x04 +#define bmTI 0x02 +#define bmRI 0x01 + +/* Bit masks in T2MOD (0xc9) */ + +#define bmT2OE 0x02 +#define bmDCEN 0x01 + +/* Bit masks in CMOD (0xd9) */ + +#define bmCIDL 0x80 +#define bmWDTE 0x40 +#define bmCPS1 0x04 +#define bmCPS0 0x02 +#define bmECF 0x01 + +/* Bit masks in CCON (0xd8) */ + +#define bmCF 0x80 +#define bmCR 0x40 +#define bmCCF4 0x10 +#define bmCCF3 0x08 +#define bmCCF2 0x04 +#define bmCCF1 0x02 +#define bmCCF0 0x01 + +/* Bit masks in CCAPM0 (0xda) */ + +#define bmECOM0 0x40 +#define bmCAPP0 0x20 +#define bmCAPN0 0x10 +#define bmMAT0 0x08 +#define bmTOG0 0x04 +#define bmPWM0 0x02 +#define bmECCF0 0x01 + +/* Bit masks in CCAPM1 (0xdb) */ + +#define bmECOM1 0x40 +#define bmCAPP1 0x20 +#define bmCAPN1 0x10 +#define bmMAT1 0x08 +#define bmTOG1 0x04 +#define bmPWM1 0x02 +#define bmECCF1 0x01 + +/* Bit masks in CCAPM2 (0xdc) */ + +#define bmECOM2 0x40 +#define bmCAPP2 0x20 +#define bmCAPN2 0x10 +#define bmMAT2 0x08 +#define bmTOG2 0x04 +#define bmPWM2 0x02 +#define bmECCF2 0x01 + +/* Bit masks in CCAPM3 (0xdd) */ + +#define bmECOM3 0x40 +#define bmCAPP3 0x20 +#define bmCAPN3 0x10 +#define bmMAT3 0x08 +#define bmTOG3 0x04 +#define bmPWM3 0x02 +#define bmECCF3 0x01 + +/* Bit masks in CCAPM4 (0xde) */ + +#define bmECOM4 0x40 +#define bmCAPP4 0x20 +#define bmCAPN4 0x10 +#define bmMAT4 0x08 +#define bmTOG4 0x04 +#define bmPWM4 0x02 +#define bmECCF4 0x01 + +#define bmECOM 0x40 +#define bmCAPP 0x20 +#define bmCAPN 0x10 +#define bmMAT 0x08 +#define bmTOG 0x04 +#define bmPWM 0x02 +#define bmEDDF 0x01 + + +#endif + +/* End of s51.src/regs51.h */ diff --git a/sim/ucsim/s51.src/s51.cc b/sim/ucsim/s51.src/s51.cc new file mode 100644 index 00000000..da2c65c0 --- /dev/null +++ b/sim/ucsim/s51.src/s51.cc @@ -0,0 +1,55 @@ +/* + * Simulator of microcontrollers (s51.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include + +#include "globals.h" + +#include "sim51cl.h" + + +/* + * Main function of the Simulator of MCS51. Everything starts here. + */ + +int +main(int argc, char *argv[]) +{ + int retval; + + simulator= new cl_sim51(argc, argv); + if (simulator->init()) + return(1); + retval= simulator->main(); + delete simulator; + + return(retval); +} + +/* End of s51.src/s51.cc */ diff --git a/sim/ucsim/s51.src/serial.cc b/sim/ucsim/s51.src/serial.cc new file mode 100644 index 00000000..5389c3df --- /dev/null +++ b/sim/ucsim/s51.src/serial.cc @@ -0,0 +1,72 @@ +/* + * Simulator of microcontrollers (serial.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "serialcl.h" +#include "regs51.h" + + +cl_serial::cl_serial(class cl_uc *auc): + cl_hw(auc, HW_UART, 0, "uart") +{} + +/*int +cl_serial::init(void) +{ + return(0); +}*/ + +void +cl_serial::print_info(class cl_console *con) +{ + char *modes[]= { "Shift, fixed clock", + "8 bit UART timer clocked", + "9 bit UART fixed clock", + "9 bit UART timer clocked" }; + int scon= uc->get_mem(MEM_SFR, SCON); + + con->printf("%s[%d]", id_string, id); + int mode= (scon&(bmSM0|bmSM1))>>6; + con->printf(" %s MultiProc=%s", modes[mode], + (mode&2)?((scon&bmSM2)?"ON":"OFF"):"none"); + con->printf(" irq=%s", (uc->get_mem(MEM_SFR, IE)&bmES)?"en":"dis"); + con->printf(" prio=%d", uc->it_priority(bmPS)); + con->printf("\n"); + + con->printf("Receiver"); + con->printf(" %s", (scon&bmREN)?"ON":"OFF"); + con->printf(" RB8=%c", (scon&bmRB8)?'1':'0'); + con->printf(" irq=%c", (scon&bmRI)?'1':'0'); + con->printf("\n"); + + con->printf("Transmitter"); + con->printf(" TB8=%c", (scon&bmTB8)?'1':'0'); + con->printf(" irq=%c", (scon&bmTI)?'1':'0'); + con->printf("\n"); +} + + +/* End of s51.src/serial.cc */ diff --git a/sim/ucsim/s51.src/serialcl.h b/sim/ucsim/s51.src/serialcl.h new file mode 100644 index 00000000..a3db04cf --- /dev/null +++ b/sim/ucsim/s51.src/serialcl.h @@ -0,0 +1,54 @@ +/* + * Simulator of microcontrollers (serialcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SERIALCL_HEADER +#define SERIALCL_HEADER + +#include "stypes.h" +#include "pobjcl.h" +#include "uccl.h" + +#include "newcmdcl.h" + + +class cl_serial: public cl_hw +{ +public: + cl_serial(class cl_uc *auc); + //virtual int init(void); + + //virtual ulong read(class cl_mem *mem, long addr); + //virtual void write(class cl_mem *mem, long addr, ulong *val); + + //virtual int tick(int cycles); + virtual void print_info(class cl_console *con); +}; + + +#endif + +/* End of s51.src/serialcl.h */ diff --git a/sim/ucsim/s51.src/set.cc b/sim/ucsim/s51.src/set.cc new file mode 100644 index 00000000..47b81b7b --- /dev/null +++ b/sim/ucsim/s51.src/set.cc @@ -0,0 +1,384 @@ +/* + * Simulator of microcontrollers (set.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include "i_string.h" + +#include "stypes.h" +#include "simcl.h" +#include "memcl.h" +#include "uccl.h" +#include "globals.h" + +#include "cmdutil.h" +#include "dump.h" + +#include "regs51.h" //FIXME + + +/* + * Parsing command and write data into specified buffer + */ + +static void +set_memory(cl_mem *mem, t_addr first, + class cl_uc *uc, struct name_entry tabl[], class cl_sim *sim) +{ + t_addr start, addr; + char *s, *p; + uchar data, *what= 0; + struct name_entry *ne= NULL; + + if ((s= strtok(NULL, delimiters)) == NULL) + { + fprintf(sim->cmd_out(), "Address has not given.\n"); + return; + } + if (tabl) + ne= get_name_entry(tabl, s, uc); + if (ne) + addr= ne->addr; + else + { + addr= strtol(s, &p, 0); + if (p && + *p) + { + fprintf(sim->cmd_out(), "Bad address.\n"); + return; + } + } + start= addr; + if (start >= mem->size) + { + fprintf(sim->cmd_out(), + "Address %ld(0x%lx) is bigger than %ld(0x%lx).\n", + start, start, mem->size-1, mem->size-1); + return; + } + if (!(start >= first)) + { + fprintf(sim->cmd_out(), + "Address %ld(0x%lx) is less than %ld(0x%lx).\n", + start, start, first, first); + return; + } + if ((s= strtok(NULL, " \t\v")) == NULL) + { + fprintf(sim->cmd_out(), "Data has not given.\n"); + return; + } + while (s && + addr < mem->size) + { + if (isdigit(*s)) + { + data= strtol(s, &p, 0); + if (p && + *p) + { + fprintf(sim->cmd_out(), "Bad data %s\n", s); + break; + } + mem->set(addr, data); + if (what == uc->MEM(MEM_SFR)) + { + uc->proc_write/*FIXME*/(&what[addr]); + if (addr == ACC) + uc->set_p_flag/*FIXME*/(); + } + if (what == uc->MEM(MEM_ROM)) + uc->del_inst_at/*FIXME*/(addr); + addr++; + } + else + { + int i, len; + p= proc_escape(s, &len); + i= 0; + while ((i < len) && + addr < mem->size) + { + what[addr]= p[i++]; + if (what == uc->MEM(MEM_SFR)) + { + uc->proc_write/*FIXME*/(&what[addr]); + if (addr == ACC) + uc->set_p_flag/*FIXME*/(); + } + if (what == uc->MEM(MEM_ROM)) + uc->del_inst_at/*FIXME*/(addr); + addr++; + } + free(p); + } + s= strtok(NULL, " \t\v"); + } + dump_memory(mem, &start, addr-1, 16, sim->cmd_out(), sim); +} + + +/* + * SET IRAM addr data... + */ + +bool +cmd_set_iram(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + set_memory(uc->mem(MEM_IRAM), 0, uc, NULL, sim); + return(FALSE); +} + + +/* + * SET XRAM addr data... + */ + +bool +cmd_set_xram(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + uc->eram2xram(); + set_memory(uc->mem(MEM_XRAM), 0, uc, NULL, sim); + uc->xram2eram(); + return(FALSE); +} + + +/* + * SET CODE addr data... + */ + +bool +cmd_set_code(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + set_memory(uc->mem(MEM_ROM), 0, uc, NULL, sim); + return(FALSE); +} + + +/* + * SET SFR addr data... + */ + +bool +cmd_set_sfr(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + set_memory(uc->mem(MEM_SFR), SFR_START, uc, uc->sfr_tbl(), sim); + return(FALSE); +} + + +/* + * SET BIT addr data... + */ + +bool +cmd_set_bit(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + char *s; + uchar *cell, addr; + uchar bitaddr, bitmask; + + if ((s= strtok(NULL, delimiters)) == NULL) + { + fprintf(sim->cmd_out(), "Address has not given.\n"); + return(FALSE); + } + if (!interpret_bitname(s, uc, &cell, &addr, &bitaddr, &bitmask, NULL)) + { + fprintf(sim->cmd_out(), "Bad address %s\n", s); + return(FALSE); + } + + if ((s= strtok(NULL, delimiters)) == NULL) + { + fprintf(sim->cmd_out(), "Data has not given.\n"); + return(FALSE); + } + while (s) + { + if (!isdigit(*s)) + { + fprintf(sim->cmd_out(), "Bad data %s\n", s); + return(FALSE); + } + if (*s == '0') + *cell&= ~bitmask; + else + *cell|= bitmask; + bitmask<<= 1; + bitmask&= 0xff; + s= strtok(NULL, delimiters); + } + return(FALSE); +} + + +/* + * SET PORT port data + */ + +bool +cmd_set_port(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + char *s, *p; + uchar port, data; + + if ((s= strtok(NULL, delimiters)) == NULL) + { + fprintf(sim->cmd_out(), "Port number has not given.\n"); + return(FALSE); + } + port= strtol(s, &p, 0); + if ((p && *p) || + (port > 3)) + { + fprintf(sim->cmd_out(), "Port number %s is wrong.\n", s); + return(FALSE); + } + + if ((s= strtok(NULL, delimiters)) == NULL) + { + fprintf(sim->cmd_out(), "Date has not given.\n"); + return(FALSE); + } + data= strtol(s, &p, 0); + if (p && *p) + { + fprintf(sim->cmd_out(), "Data %s is wrong.\n", s); + return(FALSE); + } + uc->port_pins[port]= data; + return(FALSE); +} + + +/* + * Fill memory commands + */ + +static void +fill_memory(uchar *what, int size, int first, class cl_uc *uc, + class cl_sim *sim) +{ + char *s, *p; + int start, stop; + uchar data; + + if ((s= strtok(NULL, delimiters)) == NULL) + return; + start= strtol(s, &p, 0); + if ((p && *p) || + (start < 0) || + (start < first) || + (start >= size)) + fprintf(sim->cmd_out(), "Start address %s is wrong.\n", s); + + if ((s= strtok(NULL, delimiters)) == NULL) + return; + stop= strtol(s, &p, 0); + if ((p && *p) || + (stop < start) || + (stop >= size)) + fprintf(sim->cmd_out(), "Stop address %s is wrong.\n", s); + + if ((s= strtok(NULL, delimiters)) == NULL) + return; + data= strtol(s, &p, 0); + if (p && *p) + fprintf(sim->cmd_out(), "Data %s is wrong.\n", s); + + while (start <= stop) + { + what[start]= data; + if (what == uc->MEM(MEM_SFR)) + { + uc->proc_write/*FIXME*/(&what[start]); + if (start == ACC) + uc->set_p_flag/*FIXME*/(); + } + if (what == uc->MEM(MEM_ROM)) + uc->del_inst_at/*FIXME*/(start); + start++; + } +} + + +/* + * FILL IRAM from to data + */ + +bool +cmd_fill_iram(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + fill_memory(uc->MEM(MEM_IRAM), uc->get_mem_size(MEM_IRAM), 0, uc, sim); + return(FALSE); +} + + +/* + * FILL XRAM from to data + */ + +bool +cmd_fill_xram(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + fill_memory(uc->MEM(MEM_XRAM), uc->get_mem_size(MEM_XRAM), 0, uc, sim); + uc->xram2eram/*FIXME*/(); + return(FALSE); +} + + +/* + * FILL SFR from to data + */ + +bool +cmd_fill_sfr(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + fill_memory(uc->MEM(MEM_SFR), uc->get_mem_size(MEM_SFR), SFR_START, uc, sim); + return(FALSE); +} + + +/* + * FILL CODE from to data + */ + +bool +cmd_fill_code(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + fill_memory(uc->MEM(MEM_ROM), EROM_SIZE, 0, uc, sim); + return(FALSE); +} + + +/* End of s51.src/set.cc */ diff --git a/sim/ucsim/s51.src/set.h b/sim/ucsim/s51.src/set.h new file mode 100644 index 00000000..b06f7963 --- /dev/null +++ b/sim/ucsim/s51.src/set.h @@ -0,0 +1,48 @@ +/* + * Simulator of microcontrollers (set.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SET_HEADER +#define SET_HEADER + +#include "ddconfig.h" + + +extern bool cmd_set_iram(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_set_xram(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_set_code(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_set_sfr(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_set_bit(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_set_port(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_fill_iram(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_fill_xram(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_fill_sfr(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_fill_code(char *cmd, class cl_uc *uc, class cl_sim *sim); + + +#endif + +/* End of s51.src/set.h */ diff --git a/sim/ucsim/s51.src/show.cc b/sim/ucsim/s51.src/show.cc new file mode 100644 index 00000000..b7bd584c --- /dev/null +++ b/sim/ucsim/s51.src/show.cc @@ -0,0 +1,346 @@ +/* + * Simulator of microcontrollers (show.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include "i_string.h" + +#include "simcl.h" + +#include "uccl.h" +#include "globals.h" + + +static char *warranty= +" NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. +"; + + +static char *copying= +" GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + + We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + + Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + + Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + + The precise terms and conditions for copying, distribution and +modification follow. + + GNU GENERAL PUBLIC LICENSE + TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION + + 0. This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The \"Program\", below, +refers to any such program or work, and a \"work based on the Program\" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term \"modification\".) Each licensee is addressed as \"you\". + +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + + 1. You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. + +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. + + 2. You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: + + a) You must cause the modified files to carry prominent notices + stating that you changed the files and the date of any change. + + b) You must cause any work that you distribute or publish, that in + whole or in part contains or is derived from the Program or any + part thereof, to be licensed as a whole at no charge to all third + parties under the terms of this License. + + c) If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) + +These requirements apply to the modified work as a whole. If +identifiable sections of that work are not derived from the Program, +and can be reasonably considered independent and separate works in +themselves, then this License, and its terms, do not apply to those +sections when you distribute them as separate works. But when you +distribute the same sections as part of a whole which is a work based +on the Program, the distribution of the whole must be on the terms of +this License, whose permissions for other licensees extend to the +entire whole, and thus to each and every part regardless of who wrote it. + +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. + +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + + 3. You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + a) Accompany it with the complete corresponding machine-readable + source code, which must be distributed under the terms of Sections + 1 and 2 above on a medium customarily used for software interchange; or, + + b) Accompany it with a written offer, valid for at least three + years, to give any third party, for a charge no more than your + cost of physically performing source distribution, a complete + machine-readable copy of the corresponding source code, to be + distributed under the terms of Sections 1 and 2 above on a medium + customarily used for software interchange; or, + + c) Accompany it with the information you received as to the offer + to distribute corresponding source code. (This alternative is + allowed only for noncommercial distribution and only if you + received the program in object code or executable form with such + an offer, in accord with Subsection b above.) + +The source code for a work means the preferred form of the work for +making modifications to it. For an executable work, complete source +code means all the source code for all modules it contains, plus any +associated interface definition files, plus the scripts used to +control compilation and installation of the executable. However, as a +special exception, the source code distributed need not include +anything that is normally distributed (in either source or binary +form) with the major components (compiler, kernel, and so on) of the +operating system on which the executable runs, unless that component +itself accompanies the executable. + +If distribution of executable or object code is made by offering +access to copy from a designated place, then offering equivalent +access to copy the source code from the same place counts as +distribution of the source code, even though third parties are not +compelled to copy the source along with the object code. + + 4. You may not copy, modify, sublicense, or distribute the Program +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + + 5. You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + + 6. Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + + 7. If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. + +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. + +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. + +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + + 8. If the distribution and/or use of the Program is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Program under this License +may add an explicit geographical distribution limitation excluding +those countries, so that distribution is permitted only in or among +countries not thus excluded. In such case, this License incorporates +the limitation as if written in the body of this License. + + 9. The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and \"any +later version\", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. +"; + + +bool +cmd_show(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + char *s; + + if ((s= strtok(NULL, delimiters)) == NULL) + { + fprintf(sim->cmd_out(), "Parameter is not given.\n"); + return(FALSE); + } + if (*s == 'c') + { + fprintf(sim->cmd_out(), "%s\n", copying); + } + else if (*s == 'w') + fprintf(sim->cmd_out(), "%s\n", warranty); + else + fprintf(sim->cmd_out(), "Unknown parameter.\n"); + return(FALSE); +} + + +/* End of s51.src/show.cc */ diff --git a/sim/ucsim/s51.src/show.h b/sim/ucsim/s51.src/show.h new file mode 100644 index 00000000..fa0076f0 --- /dev/null +++ b/sim/ucsim/s51.src/show.h @@ -0,0 +1,37 @@ +/* + * Simulator of microcontrollers (show.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SHOW_HEADER +#define SHOW_HEADER + + +extern bool cmd_show(char *cmd, class cl_uc *uc, class cl_sim *sim); + + +#endif + +/* End of s51.src/show.h */ diff --git a/sim/ucsim/s51.src/sim51.cc b/sim/ucsim/s51.src/sim51.cc new file mode 100644 index 00000000..9979fe71 --- /dev/null +++ b/sim/ucsim/s51.src/sim51.cc @@ -0,0 +1,274 @@ +/* + * Simulator of microcontrollers (sim51.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include +#include "i_string.h" + +#include "globals.h" +#include "utils.h" + +#include "sim51cl.h" +#include "cmd51cl.h" +#include "uc51cl.h" +#include "uc52cl.h" +#include "uc51rcl.h" +#include "uc89c51rcl.h" +#include "uc251cl.h" +#include "glob.h" + + +cl_sim51::cl_sim51(int iargc, char *iargv[]): + cl_sim("t:s:S:hH", iargc, iargv) +{} + +static void +print_help(char *name) +{ + printf("%s: %s\n", name, VERSIONSTR); + printf("Usage: %s [-hHVvP] [-p prompt] [-t CPU] [-X freq[k|M]]\n" + " [-c file] [-s file] [-S optionlist]" +#ifdef SOCKET_AVAIL + " [-Z portnum]" +#endif + "\n" + " [files...]\n", name); + printf + ( + "Options:\n" + " -t CPU Type of CPU: 51, C52, 251, etc.\n" + " -X freq[k|M] XTAL frequency\n" + " -c file Open command console on `file'\n" +#ifdef SOCKET_AVAIL + " -Z portnum Use localhost:portnumber for command console\n" +#endif + " -s file Connect serial interface to `file'\n" + " -S options `options' is a comma separated list of options\n" + " according to serial interface. Know options are:\n" + " in=file serial input will be read from file named `file'\n" + " out=file serial output will be written to `file'\n" + " -p prompt Specify string for prompt\n" + " -P Prompt is a null ('\\0') character\n" + " -V Verbose mode\n" + " -v Print out version number\n" + " -H Print out types of known CPUs\n" + " -h Print out this help\n" + ); +} + +enum { + SOPT_IN= 0, + SOPT_OUT +}; + +static const char *S_opts[]= { + /*[SOPT_IN]=*/ "in", + /*[SOPT_OUT]=*/ "out", + NULL +}; + +int +cl_sim51::proc_arg(char optopt, char *optarg) +{ + char *cpu_type= NULL, *cp; + int i; + char *subopts, *value; + + switch (optopt) + { + + case 't': + + if (cpu_type) + free(cpu_type); + cpu_type= strdup(optarg); + for (cp= cpu_type; *cp; *cp= toupper(*cp), cp++); + arguments->add(new cl_prg_arg('t', 0, cpu_type)); + break; + + case 's': + { + FILE *Ser_in, *Ser_out; + if (arg_avail('s')) + { + fprintf(stderr, "-s option can not be used more than once.\n"); + break; + } + arguments->add(new cl_prg_arg('s', 0, (long long)1)); + if ((Ser_in= fopen(optarg, "r")) == NULL) + { + fprintf(stderr, + "Can't open `%s': %s\n", optarg, strerror(errno)); + return(4); + } + arguments->add(new cl_prg_arg(0, "Ser_in", Ser_in)); + if ((Ser_out= fopen(optarg, "w")) == NULL) + { + fprintf(stderr, + "Can't open `%s': %s\n", optarg, strerror(errno)); + return(4); + } + arguments->add(new cl_prg_arg(0, "Ser_out", Ser_out)); + break; + } + + case 'S': + + subopts= optarg; + while (*subopts != '\0') + switch (get_sub_opt(&subopts, S_opts, &value)) + { + FILE *Ser_in, *Ser_out; + case SOPT_IN: + if (value == NULL) { + fprintf(stderr, "No value for -S in\n"); + exit(1); + } + if (arg_avail("Ser_in")) + { + fprintf(stderr, "Serial input specified more than once.\n"); + break; + } + if ((Ser_in= fopen(value, "r")) == NULL) + { + fprintf(stderr, + "Can't open `%s': %s\n", value, strerror(errno)); + exit(4); + } + arguments->add(new cl_prg_arg(0, "Ser_in", Ser_in)); + break; + case SOPT_OUT: + if (value == NULL) { + fprintf(stderr, "No value for -S out\n"); + exit(1); + } + if (arg_avail("Ser_out")) + { + fprintf(stderr, "Serial output specified more than once.\n"); + break; + } + if ((Ser_out= fopen(value, "w")) == NULL) + { + fprintf(stderr, + "Can't open `%s': %s\n", value, strerror(errno)); + exit(4); + } + arguments->add(new cl_prg_arg(0, "Ser_out", Ser_out)); + break; + default: + /* Unknown suboption. */ + fprintf(stderr, "Unknown suboption `%s' for -S\n", value); + exit(1); + break; + } + break; + + case 'h': + + print_help("s51"); + exit(0); + break; + + case 'H': + i= 0; + while (cpus_51[i].type_str != NULL) + { + printf("%s\n", cpus_51[i].type_str); + i++; + } + exit(0); + break; + + case '?': + + if (isprint(optopt)) + fprintf(stderr, "Unknown option `-%c'.\n", optopt); + else + fprintf(stderr, "Unknown option character `\\x%x'.\n", optopt); + return(1); + break; + + default: + // should never happen... + abort(); + } + return(0); +} + +class cl_commander * +cl_sim51::mk_commander(void) +{ + class cl_commander *cmd= new cl_51cmd(this); + return(cmd); +} + +class cl_uc * +cl_sim51::mk_controller(void) +{ + int i; + + i= 0; + if (get_sarg('t', 0) == NULL) + simulator->arguments->add(new cl_prg_arg('t', 0, "C51")); + while ((cpus_51[i].type_str != NULL) && + (strcmp(get_sarg('t', 0), cpus_51[i].type_str) != 0)) + i++; + if (cpus_51[i].type_str == NULL) + { + fprintf(stderr, "Unknown processor type. " + "Use -H option to see known types.\n"); + return(NULL); + } + switch (cpus_51[i].type) + { + case CPU_51: case CPU_31: + return(new t_uc51(cpus_51[i].type, cpus_51[i].technology, this)); + case CPU_52: case CPU_32: + return(new t_uc52(cpus_51[i].type, cpus_51[i].technology, this)); + case CPU_51R: + return(new t_uc51r(cpus_51[i].type, cpus_51[i].technology, this)); + case CPU_89C51R: + return(new t_uc89c51r(cpus_51[i].type, cpus_51[i].technology, this)); + case CPU_251: + return(new t_uc251(cpus_51[i].type, cpus_51[i].technology, this)); + } + return(NULL); +} + +void +cl_sim51::build_cmd_set(void) +{ + cl_sim::build_cmd_set(); + cmdset->del("ds"); +} + + +/* End of s51.src/sim51.cc */ diff --git a/sim/ucsim/s51.src/sim51cl.h b/sim/ucsim/s51.src/sim51cl.h new file mode 100644 index 00000000..55cc28e4 --- /dev/null +++ b/sim/ucsim/s51.src/sim51cl.h @@ -0,0 +1,47 @@ +/* + * Simulator of microcontrollers (sim51cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SIM51CL_HEADER +#define SIM51CL_HEADER + +#include "simcl.h" + + +class cl_sim51: public cl_sim +{ +public: + cl_sim51(int iargc, char *iargv[]); + virtual int proc_arg(char optopt, char *optarg); + virtual class cl_commander *mk_commander(void); + virtual class cl_uc *mk_controller(void); + virtual void build_cmd_set(void); +}; + + +#endif + +/* End of s51.src/sim51cl.h */ diff --git a/sim/ucsim/s51.src/start1 b/sim/ucsim/s51.src/start1 new file mode 100755 index 00000000..8bdf6aa1 --- /dev/null +++ b/sim/ucsim/s51.src/start1 @@ -0,0 +1,5 @@ +#!/bin/sh + +s51 -Sin=tee_1,out=1_tee "$@" + +# End of start1 diff --git a/sim/ucsim/s51.src/start2 b/sim/ucsim/s51.src/start2 new file mode 100755 index 00000000..15a08116 --- /dev/null +++ b/sim/ucsim/s51.src/start2 @@ -0,0 +1,5 @@ +#!/bin/sh + +s51 -Sin=tee_2,out=2_tee "$@" + +# End of start2 diff --git a/sim/ucsim/s51.src/temp.lnk b/sim/ucsim/s51.src/temp.lnk new file mode 100644 index 00000000..567863a8 --- /dev/null +++ b/sim/ucsim/s51.src/temp.lnk @@ -0,0 +1,15 @@ +-muxi +-z +-b CODE = 0x0000 +-b DSEG = 0x0030 +-b XSEG = 0x0000 +-b ISEG = 0x0080 +-b BSEG = 0x0000 +-k /stuff/sdcc/share/sdcc51lib/small +-l libsdcc +-l libint +-l liblong +-l libfloat +test_ser.rel + +-e diff --git a/sim/ucsim/s51.src/test_extit.c b/sim/ucsim/s51.src/test_extit.c new file mode 100644 index 00000000..f61fd41f --- /dev/null +++ b/sim/ucsim/s51.src/test_extit.c @@ -0,0 +1,15 @@ +#include + +sfr at 0xa6 WDTRST; + +void jaj() interrupt 0 { P2= P0; P0++; } + +void main() +{ + IT0=0; /* low level triggered */ + IT0=1; /* falling edge triggered */ + EX0=1; /* enable ex #0 */ + EA=1; + P0=0; + for(;;); +} diff --git a/sim/ucsim/s51.src/test_idlepd.c b/sim/ucsim/s51.src/test_idlepd.c new file mode 100644 index 00000000..56b6aaaa --- /dev/null +++ b/sim/ucsim/s51.src/test_idlepd.c @@ -0,0 +1,35 @@ +#include + +sfr at 0xa6 WDTRST; + +void jaj_ex0() interrupt 0 { P2= P0; } + +void jaj_t0() interrupt 1 { P2= P0; } + +void main() +{ + TH0= 0x80; + TL0= 0x80; + TMOD= 0x02; + + IT0=0; /* low level triggered */ + IT0=1; /* falling edge triggered */ + EX0=1; /* enable ex #0 */ + ET0=1; /* en t0 */ + + TR0= 1; + + EA=1; + P0=0; + while (1) + { + P0= 0; + PCON|= 1;/*idle*/ + P0++; + P0++; + P0++; + } + WDTRST= 0x1e; + WDTRST= 0xe1; + PCON|= 2;/*pd*/ +} diff --git a/sim/ucsim/s51.src/test_ser.c b/sim/ucsim/s51.src/test_ser.c new file mode 100644 index 00000000..1af12abc --- /dev/null +++ b/sim/ucsim/s51.src/test_ser.c @@ -0,0 +1,114 @@ +#include + +#define BUFSIZE 16 +#define T0H 0xfc +#define T0L 0x67 + +unsigned char buf[BUFSIZE]; +unsigned char first_free= 0, last_occupied= 0; +bit transmitting, overflow; +volatile int t0cnt; + +void ser_it(void) interrupt 4 +{ + unsigned char temp; + if (RI) { + buf[first_free]= SBUF; + first_free= ((temp= first_free)+1) % BUFSIZE; + if (first_free == last_occupied) { + first_free= temp; + overflow= 1; + } + RI= 0; + } + if (TI) { + transmitting= 0; + TI= 0; + } +} + +void t0_it(void) interrupt 1 +{ + TL0= T0L; + TH0= T0H; + if (t0cnt) + t0cnt--; +} + +char empty(void) +{ + return(first_free == last_occupied); +} + +unsigned char get_ch(void) +{ + unsigned char c; + c= buf[last_occupied]; + last_occupied= (last_occupied+1) % BUFSIZE; + overflow= 0; + return(c); +} + +void send_ch(unsigned char c) +{ + while (transmitting) ; + transmitting= 1; + SBUF= c; +} + +void send_str(char *str) +{ + while (*str) { + send_ch(*str); + str++; + } +} + +void process(void) +{ + unsigned char c; + c= get_ch(); + if ((c >= 'a' && c <= 'z') || + (c >= 'A' && c <= 'Z')) + c^= 0x20; + send_ch(c); +} + +void wait(int delay) +{ + t0cnt= delay; + while (t0cnt) + PCON|= 1; +} + +char test(char c) +{ + return(c+1); +} + +void main(void) +{ + t0cnt= 0; + transmitting= overflow= 0; + SCON= 0x7c; + TL1= TH1= 250; /* 9600 baud */ + TH0= T0H; + TL0= T0L; + TMOD= 0x21; + TR0= TR1= 1; + ES= ET0= 1; + EA= 1; + send_str("\nOK\n"); + test(0); + wait(1000); + test(1); + send_str("delay off\n"); + for (;;) { + if (!empty()) { + if (overflow) { + send_str("Overflow!\n"); + } + process(); + } + } +} diff --git a/sim/ucsim/s51.src/test_stack.c b/sim/ucsim/s51.src/test_stack.c new file mode 100644 index 00000000..25ba88d7 --- /dev/null +++ b/sim/ucsim/s51.src/test_stack.c @@ -0,0 +1,9 @@ +void jaj(void) +{ + jaj(); +} + +void main(void) +{ + jaj(); +} diff --git a/sim/ucsim/s51.src/timer0.cc b/sim/ucsim/s51.src/timer0.cc new file mode 100644 index 00000000..d1b7dd6b --- /dev/null +++ b/sim/ucsim/s51.src/timer0.cc @@ -0,0 +1,69 @@ +/* + * Simulator of microcontrollers (timer0.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "timer0cl.h" +#include "regs51.h" + + +cl_timer0::cl_timer0(class cl_uc *auc): + cl_hw(auc, HW_TIMER, 0, "timer0") +{} + +/*int +cl_timer0::init(void) +{ + return(0); +}*/ + +void +cl_timer0::print_info(class cl_console *con) +{ + char *modes[]= { "13 bit", "16 bit", "8 bit autoreload", "2x8 bit" }; + int tmod= uc->get_mem(MEM_SFR, TMOD); + int on; + + con->printf("%s[%d] 0x%04x", id_string, id, + 256*uc->get_mem(MEM_SFR, TH0)+uc->get_mem(MEM_SFR, TL0)); + int mode= tmod & (bmM00|bmM10); + con->printf(" %s", modes[mode]); + con->printf(" %s", (tmod&bmC_T0)?"counter":"timer"); + if (tmod&bmGATE0) + { + con->printf(" gated"); + on= uc->get_mem(MEM_SFR, P3) & uc->port_pins[3] & bm_INT0; + } + else + on= uc->get_mem(MEM_SFR, TCON) & bmTR0; + con->printf(" %s", on?"ON":"OFF"); + con->printf(" irq=%c", (uc->get_mem(MEM_SFR, TCON)&bmTF0)?'1':'0'); + con->printf(" %s", (uc->get_mem(MEM_SFR, IE)&bmET0)?"en":"dis"); + con->printf(" prio=%d", uc->it_priority(bmPT0)); + con->printf("\n"); +} + + +/* End of s51.src/timer0.cc */ diff --git a/sim/ucsim/s51.src/timer0cl.h b/sim/ucsim/s51.src/timer0cl.h new file mode 100644 index 00000000..648f9239 --- /dev/null +++ b/sim/ucsim/s51.src/timer0cl.h @@ -0,0 +1,54 @@ +/* + * Simulator of microcontrollers (timer0cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef TIMER0CL_HEADER +#define TIMER0CL_HEADER + +#include "stypes.h" +#include "pobjcl.h" +#include "uccl.h" + +#include "newcmdcl.h" + + +class cl_timer0: public cl_hw +{ +public: + cl_timer0(class cl_uc *auc); + //virtual int init(void); + + //virtual ulong read(class cl_mem *mem, long addr); + //virtual void write(class cl_mem *mem, long addr, ulong *val); + + //virtual int tick(int cycles); + virtual void print_info(class cl_console *con); +}; + + +#endif + +/* End of s51.src/timer0cl.h */ diff --git a/sim/ucsim/s51.src/timer1.cc b/sim/ucsim/s51.src/timer1.cc new file mode 100644 index 00000000..30a924eb --- /dev/null +++ b/sim/ucsim/s51.src/timer1.cc @@ -0,0 +1,69 @@ +/* + * Simulator of microcontrollers (timer1.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "timer1cl.h" +#include "regs51.h" + + +cl_timer1::cl_timer1(class cl_uc *auc): + cl_hw(auc, HW_TIMER, 1, "timer1") +{} + +/*int +cl_timer1::init(void) +{ + return(0); +}*/ + +void +cl_timer1::print_info(class cl_console *con) +{ + char *modes[]= { "13 bit", "16 bit", "8 bit autoreload", "stop" }; + int tmod= uc->get_mem(MEM_SFR, TMOD); + int on; + + con->printf("%s[%d] 0x%04x", id_string, id, + 256*uc->get_mem(MEM_SFR, TH1)+uc->get_mem(MEM_SFR, TL1)); + int mode= (tmod & (bmM11|bmM01)) >> 4; + con->printf(" %s", modes[mode]); + con->printf(" %s", (tmod&bmC_T1)?"counter":"timer"); + if (tmod&bmGATE1) + { + con->printf(" gated"); + on= uc->get_mem(MEM_SFR, P3) & uc->port_pins[3] & bm_INT0; + } + else + on= uc->get_mem(MEM_SFR, TCON) & bmTR1; + con->printf(" %s", on?"ON":"OFF"); + con->printf(" irq=%c", (uc->get_mem(MEM_SFR, TCON)&bmTF1)?'1':'0'); + con->printf(" %s", (uc->get_mem(MEM_SFR, IE)&bmET1)?"en":"dis"); + con->printf(" prio=%d", uc->it_priority(bmPT1)); + con->printf("\n"); +} + + +/* End of timer1.cc */ diff --git a/sim/ucsim/s51.src/timer1cl.h b/sim/ucsim/s51.src/timer1cl.h new file mode 100644 index 00000000..cd24a3b2 --- /dev/null +++ b/sim/ucsim/s51.src/timer1cl.h @@ -0,0 +1,54 @@ +/* + * Simulator of microcontrollers (timer1cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef TIMER1CL_HEADER +#define TIMER1CL_HEADER + +#include "stypes.h" +#include "pobjcl.h" +#include "uccl.h" + +#include "newcmdcl.h" + + +class cl_timer1: public cl_hw +{ +public: + cl_timer1(class cl_uc *auc); + //virtual int init(void); + + //virtual ulong read(class cl_mem *mem, long addr); + //virtual void write(class cl_mem *mem, long addr, ulong *val); + + //virtual int tick(int cycles); + virtual void print_info(class cl_console *con); +}; + + +#endif + +/* End of s51.src/timer1cl.h */ diff --git a/sim/ucsim/s51.src/timer2.cc b/sim/ucsim/s51.src/timer2.cc new file mode 100644 index 00000000..2918eebb --- /dev/null +++ b/sim/ucsim/s51.src/timer2.cc @@ -0,0 +1,70 @@ +/* + * Simulator of microcontrollers (timer2.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "timer2cl.h" +#include "regs51.h" + + +cl_timer2::cl_timer2(class cl_uc *auc): + cl_hw(auc, HW_TIMER, 2, "timer2") +{} + +/*int +cl_timer2::init(void) +{ + return(0); +}*/ + +void +cl_timer2::print_info(class cl_console *con) +{ + int t2con= uc->get_mem(MEM_SFR, T2CON); + + con->printf("%s[%d] 0x%04x", id_string, id, + 256*uc->get_mem(MEM_SFR, TH2)+uc->get_mem(MEM_SFR, TL2)); + if (t2con & (bmRCLK|bmTCLK)) + { + con->printf(" baud"); + if (t2con & bmRCLK) + con->printf(" RCLK"); + if (t2con & bmTCLK) + con->printf(" TCLK"); + } + else + con->printf(" %s", (t2con&bmCP_RL2)?"capture":"reload"); + con->printf(" 0x%04x", + 256*uc->get_mem(MEM_SFR, RCAP2H)+uc->get_mem(MEM_SFR, RCAP2L)); + con->printf(" %s", (t2con&bmC_T2)?"counter":"timer"); + con->printf(" %s", (t2con&bmTR2)?"ON":"OFF"); + con->printf(" irq=%c", (t2con&bmTF2)?'1':'0'); + con->printf(" %s", (uc->get_mem(MEM_SFR, IE)&bmET2)?"en":"dis"); + con->printf(" prio=%d", uc->it_priority(bmPT2)); + con->printf("\n"); +} + + +/* End of s51.src/timer2.cc */ diff --git a/sim/ucsim/s51.src/timer2cl.h b/sim/ucsim/s51.src/timer2cl.h new file mode 100644 index 00000000..cf3f3b01 --- /dev/null +++ b/sim/ucsim/s51.src/timer2cl.h @@ -0,0 +1,54 @@ +/* + * Simulator of microcontrollers (timer2cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef TIMER2CL_HEADER +#define TIMER2CL_HEADER + +#include "stypes.h" +#include "pobjcl.h" +#include "uccl.h" + +#include "newcmdcl.h" + + +class cl_timer2: public cl_hw +{ +public: + cl_timer2(class cl_uc *auc); + //virtual int init(void); + + //virtual ulong read(class cl_mem *mem, long addr); + //virtual void write(class cl_mem *mem, long addr, ulong *val); + + //virtual int tick(int cycles); + virtual void print_info(class cl_console *con); +}; + + +#endif + +/* End of s51.src/timer2cl.h */ diff --git a/sim/ucsim/s51.src/uc251.cc b/sim/ucsim/s51.src/uc251.cc new file mode 100644 index 00000000..74d21ff7 --- /dev/null +++ b/sim/ucsim/s51.src/uc251.cc @@ -0,0 +1,45 @@ +/* + * Simulator of microcontrollers (uc251.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include + +#include "uc251cl.h" + + +/* + * Making an 251 CPU object + */ + +t_uc251::t_uc251(int Itype, int Itech, class cl_sim *asim): + t_uc89c51r(Itype, Itech, asim) +{ +} + + +/* End of s51.src/uc251.cc */ diff --git a/sim/ucsim/s51.src/uc251cl.h b/sim/ucsim/s51.src/uc251cl.h new file mode 100644 index 00000000..0f710601 --- /dev/null +++ b/sim/ucsim/s51.src/uc251cl.h @@ -0,0 +1,45 @@ +/* + * Simulator of microcontrollers (uc251cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef UC251CL_HEADER +#define UC251CL_HEADER + +#include "ddconfig.h" + +#include "uc89c51rcl.h" + + +class t_uc251: public t_uc89c51r +{ +public: + t_uc251(int Itype, int Itech, class cl_sim *asim); +}; + + +#endif + +/* End of s51.src/uc251cl.h */ diff --git a/sim/ucsim/s51.src/uc51.cc b/sim/ucsim/s51.src/uc51.cc new file mode 100644 index 00000000..77e8c4d3 --- /dev/null +++ b/sim/ucsim/s51.src/uc51.cc @@ -0,0 +1,1566 @@ +/* + * Simulator of microcontrollers (uc51.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if FD_HEADER_OK +# include HEADER_FD +#endif +#include "i_string.h" + +// sim +#include "optioncl.h" + +// local +#include "uc51cl.h" +#include "glob.h" +#include "regs51.h" +#include "dump.h" +#include "timer0cl.h" +#include "timer1cl.h" +#include "serialcl.h" +#include "portcl.h" +#include "interruptcl.h" + + +/* + * Making a new micro-controller and reset it + */ + +t_uc51::t_uc51(int Itype, int Itech, class cl_sim *asim): + cl_uc(asim) +{ + int i; + struct termios tattr; + + type= Itype; + technology= Itech; + + debug= asim->get_iarg('V', 0); + stop_at_it= FALSE; + options->add(new cl_bool_opt(&debug, "verbose", "Verbose flag.")); + options->add(new cl_bool_opt(&stop_at_it, "stopit", + "Stop if interrupt accepted.")); + options->add(new cl_cons_debug_opt(asim, "debug", + "Debug messages appears on this console.")); + + serial_in = (FILE*)asim->get_parg(0, "Ser_in"); + serial_out= (FILE*)asim->get_parg(0, "Ser_out"); + if (serial_in) + { + // making `serial' unbuffered + if (setvbuf(serial_in, NULL, _IONBF, 0)) + perror("Unbuffer serial input channel"); + // setting O_NONBLOCK + if ((i= fcntl(fileno(serial_in), F_GETFL, 0)) < 0) + perror("Get flags of serial input"); + i|= O_NONBLOCK; + if (fcntl(fileno(serial_in), F_SETFL, i) < 0) + perror("Set flags of serial input"); + // switching terminal to noncanonical mode + if (isatty(fileno(serial_in))) + { + tcgetattr(fileno(serial_in), &saved_attributes_in); + tcgetattr(fileno(serial_in), &tattr); + tattr.c_lflag&= ~(ICANON|ECHO); + tattr.c_cc[VMIN] = 1; + tattr.c_cc[VTIME]= 0; + tcsetattr(fileno(serial_in), TCSAFLUSH, &tattr); + } + else + fprintf(stderr, "Warning: serial input interface connected to a " + "non-terminal file.\n"); + } + if (serial_out) + { + // making `serial' unbuffered + if (setvbuf(serial_out, NULL, _IONBF, 0)) + perror("Unbuffer serial output channel"); + // setting O_NONBLOCK + if ((i= fcntl(fileno(serial_out), F_GETFL, 0)) < 0) + perror("Get flags of serial output"); + i|= O_NONBLOCK; + if (fcntl(fileno(serial_out), F_SETFL, i) < 0) + perror("Set flags of serial output"); + // switching terminal to noncanonical mode + if (isatty(fileno(serial_out))) + { + tcgetattr(fileno(serial_out), &saved_attributes_out); + tcgetattr(fileno(serial_out), &tattr); + tattr.c_lflag&= ~(ICANON|ECHO); + tattr.c_cc[VMIN] = 1; + tattr.c_cc[VTIME]= 0; + tcsetattr(fileno(serial_out), TCSAFLUSH, &tattr); + } + else + fprintf(stderr, "Warning: serial output interface connected to a " + "non-terminal file.\n"); + } + + for (i= 0; i < 4; i++) + port_pins[i]= 0xff; + it_sources->add(new cl_it_src(bmEX0, TCON, bmIE0, 0x0003, true, + "external #0")); + it_sources->add(new cl_it_src(bmET0, TCON, bmTF0, 0x000b, true, + "timer #0")); + it_sources->add(new cl_it_src(bmEX1, TCON, bmIE1, 0x0013, true, + "external #1")); + it_sources->add(new cl_it_src(bmET1, TCON, bmTF1, 0x001b, true, + "timer #1")); + it_sources->add(new cl_it_src(bmES , SCON, bmTI , 0x0023, false, + "serial transmit")); + it_sources->add(new cl_it_src(bmES , SCON, bmRI , 0x0023, false, + "serial receive")); +} + + +/* + * Initializing. Virtual calls go here + * This method must be called first after object creation. + */ + +int +t_uc51::init(void) +{ + cl_uc::init(); + reset(); + return(0); +} + +static char id_string_51[100]; + +char * +t_uc51::id_string(void) +{ + int i; + + for (i= 0; cpus_51[i].type_str != NULL && cpus_51[i].type != type; i++) ; + sprintf(id_string_51, "%s %s", + cpus_51[i].type_str?cpus_51[i].type_str:"51", + (technology==CPU_HMOS)?"HMOS":"CMOS"); + return(id_string_51); +} + +void +t_uc51::mk_hw_elements(void) +{ + class cl_hw *h; + + hws->add(h= new cl_timer0(this)); + h->init(); + hws->add(h= new cl_timer1(this)); + h->init(); + hws->add(h= new cl_serial(this)); + h->init(); + hws->add(h= new cl_port(this, 0)); + h->init(); + hws->add(h= new cl_port(this, 1)); + h->init(); + hws->add(h= new cl_port(this, 2)); + h->init(); + hws->add(h= new cl_port(this, 3)); + h->init(); + hws->add(h= new cl_interrupt(this)); + h->init(); +} + +class cl_mem * +t_uc51::mk_mem(enum mem_class type) +{ + class cl_mem *m= cl_uc::mk_mem(type); + if (type == MEM_SFR) + sfr= m; + if (type == MEM_IRAM) + iram= m; + return(m); +} + + +/* + * Destroying the micro-controller object + */ + +t_uc51::~t_uc51(void) +{ + if (serial_out) + { + if (isatty(fileno(serial_out))) + tcsetattr(fileno(serial_out), TCSANOW, &saved_attributes_out); + fclose(serial_out); + } + if (serial_in) + { + if (isatty(fileno(serial_in))) + tcsetattr(fileno(serial_in), TCSANOW, &saved_attributes_in); + fclose(serial_in); + } +} + + +/* + * Writing data to EROM + */ + +void +t_uc51::write_rom(uint addr, ulong data) +{ + if (addr < EROM_SIZE) + set_mem(MEM_ROM, addr, data); +} + + +/* + * Disassembling an instruction + */ + +struct dis_entry * +t_uc51::dis_tbl(void) +{ + return(disass_51); +} + +struct name_entry * +t_uc51::sfr_tbl(void) +{ + return(sfr_tab51); +} + +struct name_entry * +t_uc51::bit_tbl(void) +{ + return(bit_tab51); +} + +char * +t_uc51::disass(uint addr, char *sep) +{ + char work[256], temp[20], c[2]; + char *buf, *p, *b, *t; + uint code= get_mem(MEM_ROM, addr); + + p= work; + b= dis_tbl()[code].mnemonic; + while (*b) + { + if (*b == '%') + { + b++; + switch (*(b++)) + { + case 'A': // absolute address + sprintf(temp, "%04lx", + (addr&0xf800)| + (((code>>5)&0x07)*256 + + get_mem(MEM_ROM, addr+1))); + break; + case 'l': // long address + sprintf(temp, "%04lx", + get_mem(MEM_ROM, addr+1)*256 + get_mem(MEM_ROM, addr+2)); + break; + case 'a': // addr8 (direct address) at 2nd byte + if (!get_name(get_mem(MEM_ROM, addr+1), sfr_tbl(), temp)) + sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+1)); + break; + case '8': // addr8 (direct address) at 3rd byte + if (!get_name(get_mem(MEM_ROM, addr+2), sfr_tbl(), temp)) + sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+1)); + sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+2)); + break; + case 'b': // bitaddr at 2nd byte + if (get_name(get_mem(MEM_ROM, addr+1), bit_tbl(), temp)) + break; + if (get_name(get_bitidx(get_mem(MEM_ROM, addr+1)), + sfr_tbl(), temp)) + { + strcat(temp, "."); + sprintf(c, "%1ld", get_mem(MEM_ROM, addr+1)&0x07); + strcat(temp, c); + break; + } + sprintf(temp, "%02x.%ld", + get_bitidx(get_mem(MEM_ROM, addr+1)), + get_mem(MEM_ROM, addr+1)&0x07); + break; + case 'r': // rel8 address at 2nd byte + sprintf(temp, "%04x", + addr+2+(signed char)(get_mem(MEM_ROM, addr+1))); + break; + case 'R': // rel8 address at 3rd byte + sprintf(temp, "%04x", + addr+3+(signed char)(get_mem(MEM_ROM, addr+2))); + break; + case 'd': // data8 at 2nd byte + sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+1)); + break; + case 'D': // data8 at 3rd byte + sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+2)); + break; + case '6': // data16 at 2nd(H)-3rd(L) byte + sprintf(temp, "%04lx", + get_mem(MEM_ROM, addr+1)*256 + get_mem(MEM_ROM, addr+2)); + break; + default: + strcpy(temp, "?"); + break; + } + t= temp; + while (*t) + *(p++)= *(t++); + } + else + *(p++)= *(b++); + } + *p= '\0'; + + p= strchr(work, ' '); + if (!p) + { + buf= strdup(work); + return(buf); + } + if (sep == NULL) + buf= (char *)malloc(6+strlen(p)+1); + else + buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1); + for (p= work, b= buf; *p != ' '; p++, b++) + *b= *p; + p++; + *b= '\0'; + if (sep == NULL) + { + while (strlen(buf) < 6) + strcat(buf, " "); + } + else + strcat(buf, sep); + strcat(buf, p); + return(buf); +} + +void +t_uc51::print_disass(uint addr, class cl_console *con) +{ + char *dis; + class cl_brk *b; + int i; + uint code= get_mem(MEM_ROM, addr); + + b = fbrk_at(addr); + dis= disass(addr, NULL); + if (b) + con->printf("%c", (b->perm == brkFIX)?'F':'D'); + else + con->printf(" "); + con->printf("%c %06x %02x", + inst_at(addr)?' ':'*', + addr, code); + for (i= 1; i < inst_length(code); i++) + con->printf(" %02x", get_mem(MEM_ROM, addr+i)); + while (i < 3) + { + con->printf(" "); + i++; + } + con->printf(" %s\n", dis); + free(dis); +} + +void +t_uc51::print_regs(class cl_console *con) +{ + t_addr start; + uchar data; + + start= sfr->get(PSW) & 0x18; + dump_memory(iram, &start, start+7, 8, sim->cmd_out(), sim); + start= sfr->get(PSW) & 0x18; + data= iram->get(iram->get(start)); + con->printf("%06x %02x %c", + iram->get(start), data, isprint(data)?data:'.'); + + con->printf(" ACC= 0x%02x %3d %c B= 0x%02x", sfr->get(ACC), sfr->get(ACC), + isprint(sfr->get(ACC))?(sfr->get(ACC)):'.', sfr->get(B)); + eram2xram(); + data= get_mem(MEM_XRAM, sfr->get(DPH)*256+sfr->get(DPL)); + con->printf(" DPTR= 0x%02x%02x @DPTR= 0x%02x %3d %c\n", sfr->get(DPH), + sfr->get(DPL), data, data, isprint(data)?data:'.'); + + data= iram->get(iram->get(start+1)); + con->printf("%06x %02x %c", iram->get(start+1), data, + isprint(data)?data:'.'); + data= sfr->get(PSW); + con->printf(" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c\n", data, + (data&bmCY)?'1':'0', (data&bmAC)?'1':'0', + (data&bmOV)?'1':'0', (data&bmP)?'1':'0'); + + print_disass(PC, con); +} + + +/* + * Resetting the micro-controller + */ + +void +t_uc51::reset(void) +{ + cl_uc::reset(); + + clear_sfr(); + + result= resGO; + + was_reti= FALSE; + + s_tr_t1 = 0; + s_rec_t1 = 0; + s_tr_tick = 0; + s_rec_tick = 0; + s_in = 0; + s_out = 0; + s_sending = FALSE; + s_receiving= FALSE; + s_rec_bit = 0; + s_tr_bit = 0; +} + + +/* + * Setting up SFR area to reset value + */ + +void +t_uc51::clear_sfr(void) +{ + int i; + + for (i= 0; i < SFR_SIZE; i++) + sfr->set(i, 0); + sfr->set(P0, 0xff); + sfr->set(P1, 0xff); + sfr->set(P2, 0xff); + sfr->set(P3, 0xff); + sfr->set(SP, 7); + prev_p1= port_pins[1] & sfr->get(P1); + prev_p3= port_pins[3] & sfr->get(P3); +} + + +/* + * Analyzing code and settig up instruction map + */ + +void +t_uc51::analyze(uint addr) +{ + uint code; + struct dis_entry *tabl; + + code= get_mem(MEM_ROM, addr); + tabl= &(dis_tbl()[code]); + while (!inst_at(addr) && + code != 0xa5 /* break point */) + { + set_inst_at(addr); + switch (tabl->branch) + { + case 'a': // acall + analyze((addr & 0xf800)| + ((get_mem(MEM_ROM, addr+1)&0x07)*256+ + get_mem(MEM_ROM, addr+2))); + analyze(addr+tabl->length); + break; + case 'A': // ajmp + addr= (addr & 0xf800)| + ((get_mem(MEM_ROM, addr+1) & 0x07)*256 + get_mem(MEM_ROM, addr+2)); + break; + case 'l': // lcall + analyze(get_mem(MEM_ROM, addr+1)*256 + get_mem(MEM_ROM, addr+2)); + analyze(addr+tabl->length); + break; + case 'L': // ljmp + addr= get_mem(MEM_ROM, addr+1)*256 + get_mem(MEM_ROM, addr+2); + break; + case 'r': // reljmp (2nd byte) + analyze((addr + (signed char)(get_mem(MEM_ROM, addr+1))) & + (EROM_SIZE - 1)); + analyze(addr+tabl->length); + break; + case 'R': // reljmp (3rd byte) + analyze((addr+ + (signed char)(get_mem(MEM_ROM, addr+2)))&(EROM_SIZE-1)); + analyze(addr+tabl->length); + break; + case 's': // sjmp + { + signed char target; + target= get_mem(MEM_ROM, addr+1); + addr+= 2; + addr= (addr+target)&(EROM_SIZE-1); + break; + } + case '_': + return; + default: + addr= (addr+tabl->length) & (EROM_SIZE - 1); + break; + } + code= get_mem(MEM_ROM, addr); + tabl= &(dis_tbl()[code]); + } +} + + +/* + * Inform hardware elements that `cycles' machine cycles have elapsed + */ + +int +t_uc51::tick(int cycles) +{ + int l; + + cl_uc::tick(cycles); + do_hardware(cycles); + s_tr_tick+= (l= cycles * clock_per_cycle()); + s_rec_tick+= l; + return(0); +} + + +/* + * Correcting direct address + * + * This function returns address of addressed element which can be an IRAM + * or an SFR. + */ + +uchar * +t_uc51::get_direct(t_mem addr, t_addr *ev_i, t_addr *ev_s) +{ + if (addr < SFR_START) + return(&(MEM(MEM_IRAM)[*ev_i= addr])); + else + return(&(MEM(MEM_SFR)[*ev_s= addr])); +} + +/* + * Calculating address of indirectly addressed IRAM cell + * If CPU is 8051 and addr is over 127, it must be illegal! + */ + +uchar * +t_uc51::get_indirect(uchar addr, int *res) +{ + if (addr >= SFR_START) + *res= resINV_ADDR; + else + *res= resGO; + return(&(MEM(MEM_IRAM)[addr])); +} + + +/* + * Calculating address of specified register cell in IRAM + */ + +uchar * +t_uc51::get_reg(uchar regnum) +{ + return(&(MEM(MEM_IRAM)[(sfr->get(PSW) & (bmRS0|bmRS1)) | + (regnum & 0x07)])); +} + +uchar * +t_uc51::get_reg(uchar regnum, t_addr *event) +{ + return(&(MEM(MEM_IRAM)[*event= (sfr->get(PSW) & (bmRS0|bmRS1)) | + (regnum & 0x07)])); +} + + +/* + * Calculating address of IRAM or SFR cell which contains addressed bit + * Next function returns index of cell which contains addressed bit. + */ + +uchar * +t_uc51::get_bit(uchar bitaddr) +{ + if (bitaddr < 128) + return(&(MEM(MEM_IRAM)[(bitaddr/8)+32])); + return(&(MEM(MEM_SFR)[bitaddr & 0xf8])); +} + +uchar * +t_uc51::get_bit(uchar bitaddr, t_addr *ev_i, t_addr *ev_s) +{ + if (bitaddr < 128) + return(&(MEM(MEM_IRAM)[*ev_i= (bitaddr/8)+32])); + return(&(MEM(MEM_SFR)[*ev_s= bitaddr & 0xf8])); +} + +uchar +t_uc51::get_bitidx(uchar bitaddr) +{ + if (bitaddr < 128) + return((bitaddr/8)+32); + return(bitaddr & 0xf8); +} + + +/* + * Processing write operation to IRAM + * + * It starts serial transmition if address is in SFR and it is + * SBUF. Effect on IE is also checked. + */ + +void +t_uc51::proc_write(uchar *addr) +{ + if (addr == &((sfr->umem8)[SBUF])) + { + s_out= sfr->get(SBUF); + s_sending= TRUE; + s_tr_bit = 0; + s_tr_tick= 0; + s_tr_t1 = 0; + } + if (addr == &((sfr->umem8)[IE])) + was_reti= TRUE; +} + +void +t_uc51::proc_write_sp(uchar val) +{ + if (val > sp_max) + sp_max= val; + sp_avg= (sp_avg+val)/2; +} + + +/* + * Reading IRAM or SFR, but if address points to a port, it reads + * port pins instead of port latches + */ + +uchar +t_uc51::read(uchar *addr) +{ + if (addr == &(MEM(MEM_SFR)[P0])) + return(get_mem(MEM_SFR, P0) & port_pins[0]); + if (addr == &(MEM(MEM_SFR)[P1])) + return(get_mem(MEM_SFR, P1) & port_pins[1]); + if (addr == &(MEM(MEM_SFR)[P2])) + return(get_mem(MEM_SFR, P2) & port_pins[2]); + if (addr == &(MEM(MEM_SFR)[P3])) + return(get_mem(MEM_SFR, P3) & port_pins[3]); + return(*addr); +} + + +/* + * Fetching one instruction and executing it + */ + +void +t_uc51::pre_inst(void) +{ + event_at.wi= (t_addr)-1; + event_at.ri= (t_addr)-1; + event_at.wx= (t_addr)-1; + event_at.rx= (t_addr)-1; + event_at.ws= (t_addr)-1; + event_at.rs= (t_addr)-1; + event_at.rc= (t_addr)-1; +} + +int +t_uc51::exec_inst(void) +{ + ulong code; + int res; + + //pr_inst(); + if (fetch(&code)) + return(resBREAKPOINT); + tick(1); + switch (code) + { + case 0x00: res= inst_nop(code); break; + case 0x01: case 0x21: case 0x41: case 0x61: + case 0x81: case 0xa1: case 0xc1: case 0xe1:res=inst_ajmp_addr(code);break; + case 0x02: res= inst_ljmp(code); break; + case 0x03: res= inst_rr(code); break; + case 0x04: res= inst_inc_a(code); break; + case 0x05: res= inst_inc_addr(code); break; + case 0x06: case 0x07: res= inst_inc_$ri(code); break; + case 0x08: case 0x09: case 0x0a: case 0x0b: + case 0x0c: case 0x0d: case 0x0e: case 0x0f: res= inst_inc_rn(code); break; + case 0x10: res= inst_jbc_bit_addr(code); break; + case 0x11: case 0x31: case 0x51: case 0x71: + case 0x91: case 0xb1: case 0xd1: case 0xf1:res=inst_acall_addr(code);break; + case 0x12: res= inst_lcall(code, 0); break; + case 0x13: res= inst_rrc(code); break; + case 0x14: res= inst_dec_a(code); break; + case 0x15: res= inst_dec_addr(code); break; + case 0x16: case 0x17: res= inst_dec_$ri(code); break; + case 0x18: case 0x19: case 0x1a: case 0x1b: + case 0x1c: case 0x1d: case 0x1e: case 0x1f: res= inst_dec_rn(code); break; + case 0x20: res= inst_jb_bit_addr(code); break; + case 0x22: res= inst_ret(code); break; + case 0x23: res= inst_rl(code); break; + case 0x24: res= inst_add_a_$data(code); break; + case 0x25: res= inst_add_a_addr(code); break; + case 0x26: case 0x27: res= inst_add_a_$ri(code); break; + case 0x28: case 0x29: case 0x2a: case 0x2b: + case 0x2c: case 0x2d: case 0x2e: case 0x2f:res= inst_add_a_rn(code);break; + case 0x30: res= inst_jnb_bit_addr(code); break; + case 0x32: res= inst_reti(code); break; + case 0x33: res= inst_rlc(code); break; + case 0x34: res= inst_addc_a_$data(code); break; + case 0x35: res= inst_addc_a_addr(code); break; + case 0x36: case 0x37: res= inst_addc_a_$ri(code); break; + case 0x38: case 0x39: case 0x3a: case 0x3b: + case 0x3c: case 0x3d: case 0x3e: case 0x3f:res= inst_addc_a_rn(code);break; + case 0x40: res= inst_jc_addr(code); break; + case 0x42: res= inst_orl_addr_a(code); break; + case 0x43: res= inst_orl_addr_$data(code); break; + case 0x44: res= inst_orl_a_$data(code); break; + case 0x45: res= inst_orl_a_addr(code); break; + case 0x46: case 0x47: res= inst_orl_a_$ri(code); break; + case 0x48: case 0x49: case 0x4a: case 0x4b: + case 0x4c: case 0x4d: case 0x4e: case 0x4f: res= inst_orl_a_rn(code);break; + case 0x50: res= inst_jnc_addr(code); break; + case 0x52: res= inst_anl_addr_a(code); break; + case 0x53: res= inst_anl_addr_$data(code); break; + case 0x54: res= inst_anl_a_$data(code); break; + case 0x55: res= inst_anl_a_addr(code); break; + case 0x56: case 0x57: res= inst_anl_a_$ri(code); break; + case 0x58: case 0x59: case 0x5a: case 0x5b: + case 0x5c: case 0x5d: case 0x5e: case 0x5f: res= inst_anl_a_rn(code);break; + case 0x60: res= inst_jz_addr(code); break; + case 0x62: res= inst_xrl_addr_a(code); break; + case 0x63: res= inst_xrl_addr_$data(code); break; + case 0x64: res= inst_xrl_a_$data(code); break; + case 0x65: res= inst_xrl_a_addr(code); break; + case 0x66: case 0x67: res= inst_xrl_a_$ri(code); break; + case 0x68: case 0x69: case 0x6a: case 0x6b: + case 0x6c: case 0x6d: case 0x6e: case 0x6f: res= inst_xrl_a_rn(code);break; + case 0x70: res= inst_jnz_addr(code); break; + case 0x72: res= inst_orl_c_bit(code); break; + case 0x73: res= inst_jmp_$a_dptr(code); break; + case 0x74: res= inst_mov_a_$data(code); break; + case 0x75: res= inst_mov_addr_$data(code); break; + case 0x76: case 0x77: res= inst_mov_$ri_$data(code); break; + case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: + case 0x7d: case 0x7e: case 0x7f: res=inst_mov_rn_$data(code); break; + case 0x80: res= inst_sjmp(code); break; + case 0x82: res= inst_anl_c_bit(code); break; + case 0x83: res= inst_movc_a_$a_pc(code); break; + case 0x84: res= inst_div_ab(code); break; + case 0x85: res= inst_mov_addr_addr(code); break; + case 0x86: case 0x87: res= inst_mov_addr_$ri(code); break; + case 0x88: case 0x89: case 0x8a: case 0x8b: + case 0x8c: case 0x8d: case 0x8e: case 0x8f:res=inst_mov_addr_rn(code);break; + case 0x90: res= inst_mov_dptr_$data(code); break; + case 0x92: res= inst_mov_bit_c(code); break; + case 0x93: res= inst_movc_a_$a_dptr(code); break; + case 0x94: res= inst_subb_a_$data(code); break; + case 0x95: res= inst_subb_a_addr(code); break; + case 0x96: case 0x97: res= inst_subb_a_$ri(code); break; + case 0x98: case 0x99: case 0x9a: case 0x9b: + case 0x9c: case 0x9d: case 0x9e: case 0x9f:res= inst_subb_a_rn(code);break; + case 0xa2: res= inst_mov_c_bit(code); break; + case 0xa3: res= inst_inc_dptr(code); break; + case 0xa4: res= inst_mul_ab(code); break; + case 0xa5: res= inst_unknown(code); break; + case 0xa6: case 0xa7: res= inst_mov_$ri_addr(code); break; + case 0xa8: case 0xa9: case 0xaa: case 0xab: + case 0xac: case 0xad: case 0xae: case 0xaf:res=inst_mov_rn_addr(code);break; + case 0xb0: res= inst_anl_c_$bit(code); break; + case 0xb2: res= inst_cpl_bit(code); break; + case 0xb3: res= inst_cpl_c(code); break; + case 0xb4: res= inst_cjne_a_$data_addr(code); break; + case 0xb5: res= inst_cjne_a_addr_addr(code); break; + case 0xb6: case 0xb7: res= inst_cjne_$ri_$data_addr(code); break; + case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: + case 0xbd: case 0xbe: case 0xbf: res=inst_cjne_rn_$data_addr(code); break; + case 0xc0: res= inst_push(code); break; + case 0xc2: res= inst_clr_bit(code); break; + case 0xc3: res= inst_clr_c(code); break; + case 0xc4: res= inst_swap(code); break; + case 0xc5: res= inst_xch_a_addr(code); break; + case 0xc6: case 0xc7: res= inst_xch_a_$ri(code); break; + case 0xc8: case 0xc9: case 0xca: case 0xcb: + case 0xcc: case 0xcd: case 0xce: case 0xcf: res= inst_xch_a_rn(code);break; + case 0xd0: res= inst_pop(code); break; + case 0xd2: res= inst_setb_bit(code); break; + case 0xd3: res= inst_setb_c(code); break; + case 0xd4: res= inst_da_a(code); break; + case 0xd5: res= inst_djnz_addr_addr(code); break; + case 0xd6: case 0xd7: res= inst_xchd_a_$ri(code); break; + case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc: + case 0xdd: case 0xde: case 0xdf: res=inst_djnz_rn_addr(code); break; + case 0xe0: res= inst_movx_a_$dptr(code); break; + case 0xe2: case 0xe3: res= inst_movx_a_$ri(code); break; + case 0xe4: res= inst_clr_a(code); break; + case 0xe5: res= inst_mov_a_addr(code); break; + case 0xe6: case 0xe7: res= inst_mov_a_$ri(code); break; + case 0xe8: case 0xe9: case 0xea: case 0xeb: + case 0xec: case 0xed: case 0xee: case 0xef: res= inst_mov_a_rn(code);break; + case 0xf0: res= inst_movx_$dptr_a(code); break; + case 0xf2: case 0xf3: res= inst_movx_$ri_a(code); break; + case 0xf4: res= inst_cpl_a(code); break; + case 0xf5: res= inst_mov_addr_a(code); break; + case 0xf6: case 0xf7: res= inst_mov_$ri_a(code); break; + case 0xf8: case 0xf9: case 0xfa: case 0xfb: + case 0xfc: case 0xfd: case 0xfe: case 0xff: res= inst_mov_rn_a(code);break; + default: + res= inst_unknown(code); + break; + } + //post_inst(); + return(res); +} + + +/* + * Simulating execution of next instruction + * + * This is an endless loop if requested number of steps is negative. + * In this case execution is stopped if an instruction results other + * status than GO. Execution can be stopped if `cmd_in' is not NULL + * and there is input available on that file. It is usefull if the + * command console is on a terminal. If input is available then a + * complete line is read and dropped out because input is buffered + * (inp_avail will be TRUE if ENTER is pressed) and it can confuse + * command interepter. + */ + +int +t_uc51::do_inst(int step) +{ + result= resGO; + while ((result == resGO) && + (state != stPD) && + (step != 0)) + { + if (step > 0) + step--; + if (state == stGO) + { + was_reti= FALSE; + pre_inst(); + result= exec_inst(); + post_inst(); + if (result == resGO) + result= check_events(); + } + else + { + // tick hw in idle state + post_inst(); + tick(1); + } + if (result == resGO) + { + int res; + if ((res= do_interrupt()) != resGO) + result= res; + else + result= idle_pd(); + } + if ((step < 0) && + ((ticks->ticks % 100000) < 50)) + { + if (sim->cmd->input_avail_on_frozen()) + { + result= resUSER; + } + else + if (sim->cmd->input_avail()) + break; + } + if (((result == resINTERRUPT) && + stop_at_it) || + result >= resSTOP) + { + sim->stop(result); + break; + } + } + if (state == stPD) + { + //FIXME: tick outsiders eg. watchdog + if (sim->cmd->input_avail_on_frozen()) + { + //fprintf(stderr,"uc: inp avail in PD mode, user stop\n"); + result= resUSER; + sim->stop(result); + } + } + return(result); +} + +void +t_uc51::post_inst(void) +{ + uint tcon= sfr->get(TCON); + uint p3= sfr->get(P3); + + set_p_flag(); + + // Read of SBUF must be serial input data + sfr->set(SBUF, s_in); + + // Setting up external interrupt request bits (IEx) + if ((tcon & bmIT0)) + { + // IE0 edge triggered + if ((prev_p3 & bm_INT0) && + !(p3 & port_pins[3] & bm_INT0)) + // falling edge on INT0 + { + sim->cmd->debug("%g sec (%d clks): " + "Falling edge detected on INT0 (P3.2)\n", + get_rtime(), ticks->ticks); + sfr->set_bit1(TCON, bmIE0); + } + } + else + { + // IE0 level triggered + if (p3 & port_pins[3] & bm_INT0) + sfr->set_bit0(TCON, bmIE0); + else + sfr->set_bit1(TCON, bmIE0); + } + if ((tcon & bmIT1)) + { + // IE1 edge triggered + if ((prev_p3 & bm_INT1) && + !(p3 & port_pins[3] & bm_INT1)) + // falling edge on INT1 + sfr->set_bit1(TCON, bmIE1); + } + else + { + // IE1 level triggered + if (p3 & port_pins[3] & bm_INT1) + sfr->set_bit0(TCON, bmIE1); + else + sfr->set_bit1(TCON, bmIE1); + } + prev_p3= p3 & port_pins[3]; + prev_p1= p3 & port_pins[1]; +} + + +/* + * Setting up parity flag + */ + +void +t_uc51::set_p_flag(void) +{ + bool p; + int i; + uchar uc; + + p = FALSE; + uc= sfr->get(ACC); + for (i= 0; i < 8; i++) + { + if (uc & 1) + p= !p; + uc>>= 1; + } + SET_BIT(p, PSW, bmP); +} + +/* + * Simulating hardware elements + */ + +int +t_uc51::do_hardware(int cycles) +{ + int res; + + if ((res= do_timers(cycles)) != resGO) + return(res); + if ((res= do_serial(cycles)) != resGO) + return(res); + return(do_wdt(cycles)); +} + + +/* + * + */ + +int +t_uc51::serial_bit_cnt(int mode) +{ + int /*mode,*/ divby= 12; + int *tr_src= 0, *rec_src= 0; + + //mode= sfr->get(SCON) >> 6; + switch (mode) + { + case 0: + divby = 12; + tr_src = &s_tr_tick; + rec_src= &s_rec_tick; + break; + case 1: + case 3: + divby = (sfr->get(PCON)&bmSMOD)?16:32; + tr_src = &s_tr_t1; + rec_src= &s_rec_t1; + break; + case 2: + divby = (sfr->get(PCON)&bmSMOD)?16:32; + tr_src = &s_tr_tick; + rec_src= &s_rec_tick; + break; + } + if (s_sending) + { + while (*tr_src >= divby) + { + (*tr_src)-= divby; + s_tr_bit++; + } + } + if (s_receiving) + { + while (*rec_src >= divby) + { + (*rec_src)-= divby; + s_rec_bit++; + } + } + return(0); +} + + +/* + * Simulating serial line + */ + +int +t_uc51::do_serial(int cycles) +{ + int mode, bits= 8; + char c; + uint scon= sfr->get(SCON); + + mode= scon >> 6; + switch (mode) + { + case 0: + bits= 8; + break; + case 1: + bits= 10; + break; + case 2: + case 3: + bits= 11; + break; + } + serial_bit_cnt(mode); + if (s_sending && + (s_tr_bit >= bits)) + { + s_sending= FALSE; + sfr->set_bit1(SCON, bmTI); + if (serial_out) + { + putc(s_out, serial_out); + fflush(serial_out); + } + s_tr_bit-= bits; + } + if ((scon & bmREN) && + serial_in && + !s_receiving) + { + fd_set set; static struct timeval timeout= {0,0}; + FD_ZERO(&set); + FD_SET(fileno(serial_in), &set); + int i= select(fileno(serial_in)+1, &set, NULL, NULL, &timeout); + if (i > 0 && + FD_ISSET(fileno(serial_in), &set)) + { + s_receiving= TRUE; + s_rec_bit= 0; + s_rec_tick= s_rec_t1= 0; + } + } + if (s_receiving && + (s_rec_bit >= bits)) + { + if (::read(fileno(serial_in), &c, 1) == 1) + { + s_in= c; + sfr->set(SBUF, s_in); + received(c); + } + s_receiving= FALSE; + s_rec_bit-= bits; + } + return(resGO); +} + +void +t_uc51::received(int c) +{ + sfr->set_bit1(SCON, bmRI); +} + + +/* + * Simulating timers + */ + +int +t_uc51::do_timers(int cycles) +{ + int res; + + if ((res= do_timer0(cycles)) != resGO) + return(res); + return(do_timer1(cycles)); +} + + +/* + * Simulating timer 0 + */ + +int +t_uc51::do_timer0(int cycles) +{ + uint tmod= sfr->get(TMOD); + uint tcon= sfr->get(TCON); + uint p3= sfr->get(P3); + + if (((tmod & bmGATE0) && + (p3 & port_pins[3] & bm_INT0)) || + (tcon & bmTR0)) + { + if (!(tmod & bmC_T0) || + ((prev_p3 & bmT0) && + !(p3 & port_pins[3] & bmT0))) + { + if (!(tmod & bmM00) && + !(tmod & bmM10)) + { + if (tmod & bmC_T0) + cycles= 1; + while (cycles--) + { + // mod 0, TH= 8 bit t/c, TL= 5 bit precounter + (MEM(MEM_SFR)[TL0])++; + if (sfr->get(TL0) > 0x1f) + { + sfr->set_bit0(TL0, ~0x1f); + if (!++(MEM(MEM_SFR)[TH0])) + { + sfr->set_bit1(TCON, bmTF0); + t0_overflow(); + } + } + } + } + else if ((tmod & bmM00) && + !(tmod & bmM10)) + { + if (tmod & bmC_T0) + cycles= 1; + while (cycles--) + { + // mod 1 TH+TL= 16 bit t/c + if (!++(MEM(MEM_SFR)[TL0])) + { + if (!++(MEM(MEM_SFR)[TH0])) + { + sfr->set_bit1(TCON, bmTF0); + t0_overflow(); + } + } + } + } + else if (!(tmod & bmM00) && + (tmod & bmM10)) + { + if (tmod & bmC_T0) + cycles= 1; + while (cycles--) + { + // mod 2 TL= 8 bit t/c auto reload from TH + if (!++(MEM(MEM_SFR)[TL0])) + { + sfr->set(TL0, sfr->get(TH0)); + sfr->set_bit1(TCON, bmTF0); + t0_overflow(); + } + } + } + else + { + // mod 3 TL= 8 bit t/c + // TH= 8 bit timer controlled with T1's bits + if (!++(MEM(MEM_SFR)[TL0])) + { + sfr->set_bit1(TCON, bmTF0); + t0_overflow(); + } + } + } + } + if ((tmod & bmM00) && + (tmod & bmM10)) + { + if (((tmod & bmGATE1) && + (p3 & port_pins[3] & bm_INT1)) || + (tcon & bmTR1)) + { + if (!++(MEM(MEM_SFR)[TH0])) + { + sfr->set_bit1(TCON, bmTF1); + s_tr_t1++; + s_rec_t1++; + t0_overflow(); + } + } + } + return(resGO); +} + +/* + * Called every time when T0 overflows + */ + +int +t_uc51::t0_overflow(void) +{ + return(0); +} + + +/* + * Simulating timer 1 + */ + +int +t_uc51::do_timer1(int cycles) +{ + uint tmod= sfr->get(TMOD); + uint tcon= sfr->get(TCON); + uint p3= sfr->get(P3); + + if (((tmod & bmGATE1) && + (p3 & port_pins[3] & bm_INT1)) || + (tcon & bmTR1)) + { + if (!(tmod & bmC_T1) || + ((prev_p3 & bmT1) && + !(p3 & port_pins[3] & bmT1))) + { + if (!(tmod & bmM01) && + !(tmod & bmM11)) + { + if (tmod & bmC_T0) + cycles= 1; + while (cycles--) + { + // mod 0, TH= 8 bit t/c, TL= 5 bit precounter + if (++(MEM(MEM_SFR)[TL1]) > 0x1f) + { + sfr->set_bit0(TL1, ~0x1f); + if (!++(MEM(MEM_SFR)[TH1])) + { + sfr->set_bit1(TCON, bmTF1); + s_tr_t1++; + s_rec_t1++; + } + } + } + } + else if ((tmod & bmM01) && + !(tmod & bmM11)) + { + if (tmod & bmC_T0) + cycles= 1; + while (cycles--) + { + // mod 1 TH+TL= 16 bit t/c + if (!++(MEM(MEM_SFR)[TL1])) + if (!++(MEM(MEM_SFR)[TH1])) + { + sfr->set_bit1(TCON, bmTF1); + s_tr_t1++; + s_rec_t1++; + } + } + } + else if (!(tmod & bmM01) && + (tmod & bmM11)) + { + if (tmod & bmC_T1) + cycles= 1; + while (cycles--) + { + // mod 2 TL= 8 bit t/c auto reload from TH + if (!++(MEM(MEM_SFR)[TL1])) + { + sfr->set(TL1, sfr->get(TH1)); + sfr->set_bit1(TCON, bmTF1); + s_tr_t1++; + s_rec_t1++; + } + } + } + else + // mod 3 stop + ; + } + } + return(resGO); +} + + +/* + * Abstract method to handle WDT + */ + +int +t_uc51::do_wdt(int cycles) +{ + return(resGO); +} + + +/* + * Checking for interrupt requests and accept one if needed + */ + +int +t_uc51::do_interrupt(void) +{ + int i, ie= 0; + + if (was_reti) + { + was_reti= FALSE; + return(resGO); + } + if (!((ie= sfr->get(IE)) & bmEA)) + return(resGO); + class it_level *il= (class it_level *)(it_levels->top()), *IL= 0; + for (i= 0; i < it_sources->count; i++) + { + class cl_it_src *is= (class cl_it_src *)(it_sources->at(i)); + if (is->is_active() && + (ie & is->ie_mask) && + (sfr->get(is->src_reg) & is->src_mask)) + { + int pr= it_priority(is->ie_mask); + if (il->level >= 0 && + pr <= il->level) + continue; + if (state == stIDLE) + { + state= stGO; + sfr->set_bit0(PCON, bmIDL); + was_reti= 1; + return(resGO); + } + if (is->clr_bit) + sfr->set_bit0(is->src_reg, is->src_mask); + sim->cmd->debug("%g sec (%d clks): " + "Accepting interrupt `%s' PC= 0x%06x\n", + get_rtime(), ticks->ticks, is->name, PC); + IL= new it_level(pr, is->addr, PC, is); + return(accept_it(IL)); + } + } + return(resGO); +} + +int +t_uc51::it_priority(uchar ie_mask) +{ + if (sfr->get(IP) & ie_mask) + return(1); + return(0); +} + + +/* + * Accept an interrupt + */ + +int +t_uc51::accept_it(class it_level *il) +{ + state= stGO; + sfr->set_bit0(PCON, bmIDL); + it_levels->push(il); + tick(1); + int res= inst_lcall(0, il->addr); + if (res != resGO) + return(res); + else + return(resINTERRUPT); +} + + +/* + * Checking if Idle or PowerDown mode should be activated + */ + +int +t_uc51::idle_pd(void) +{ + uint pcon= sfr->get(PCON); + + if (technology != CPU_CMOS) + return(resGO); + if (pcon & bmIDL) + { + if (state != stIDLE) + sim->cmd->debug("%g sec (%d clks): CPU in Idle mode\n", + get_rtime(), ticks->ticks); + state= stIDLE; + //was_reti= 1; + } + if (pcon & bmPD) + { + if (state != stPD) + sim->cmd->debug("%g sec (%d clks): CPU in PowerDown mode\n", + get_rtime(), ticks->ticks); + state= stPD; + } + return(resGO); +} + + +/* + * Checking if EVENT break happened + */ + +int +t_uc51::check_events(void) +{ + int i; + class cl_ev_brk *eb; + + if (!ebrk->count) + return(resGO); + for (i= 0; i < ebrk->count; i++) + { + eb= (class cl_ev_brk *)(ebrk->at(i)); + if (eb->match(&event_at)) + return(resBREAKPOINT); + } + return(resGO); +} + + +/* + * Simulating an unknown instruction + * + * Normally this function is called for unimplemented instructions, because + * every instruction must be known! + */ + +int +t_uc51::inst_unknown(uchar code) +{ + PC--; + if (1)//debug)// && sim->cmd_out()) + sim->cmd->debug("Unknown instruction %02x at %06x\n", code, PC); + return(resHALT); +} + + +/* + * 0x00 1 12 NOP + */ + +int +t_uc51::inst_nop(uchar code) +{ + return(resGO); +} + + +/* + * 0xe4 1 12 CLR A + */ + +int +t_uc51::inst_clr_a(uchar code) +{ + ulong d= 0; + + sfr->write(ACC, &d); + return(resGO); +} + + +/* + * 0xc4 1 1 SWAP A + */ + +int +t_uc51::inst_swap(uchar code) +{ + uchar temp; + + temp= (sfr->read(ACC) >> 4) & 0x0f; + sfr->set(ACC, (sfr->get(ACC) << 4) | temp); + return(resGO); +} + + +/* End of s51.src/uc51.cc */ diff --git a/sim/ucsim/s51.src/uc51cl.h b/sim/ucsim/s51.src/uc51cl.h new file mode 100644 index 00000000..9ce1294e --- /dev/null +++ b/sim/ucsim/s51.src/uc51cl.h @@ -0,0 +1,256 @@ +/* + * Simulator of microcontrollers (uc51cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef UC51CL_HEADER +#define UC51CL_HEADER + +#include +#include + +#include "pobjcl.h" + +#include "simcl.h" +#include "memcl.h" +#include "uccl.h" +#include "itsrccl.h" +#include "brkcl.h" +#include "stypes.h" + + +class t_uc51: public cl_uc +{ +public: + // Options + bool debug; + bool stop_at_it; +int jaj; + // Data for breakpoint handling + struct event_rec event_at; + + FILE *serial_in; // Serial line input + FILE *serial_out; // Serial line output + + class cl_mem *sfr, *iram; + +protected: + struct termios saved_attributes_in; // Attributes of serial interface + struct termios saved_attributes_out; + + // Help to detect external it requests (falling edge) + uchar prev_p1; // Prev state of P1 + uchar prev_p3; // Prev state of P3 + + // Seral line simulation + uchar s_in; // Serial channel input reg + uchar s_out; // Serial channel output reg + bool s_sending; // Transmitter is working + bool s_receiving; // Receiver is working + int s_rec_bit; // Bit counter of receiver + int s_tr_bit; // Bit counter of transmitter + int s_rec_t1; // T1 overflows for receiving + int s_tr_t1; // T1 overflows for sending + int s_rec_tick; // Machine cycles for receiving + int s_tr_tick; // Machine cycles for sending + + // Simulation of interrupt system + bool was_reti; // Instruction had an effect on IE + +public: + int result; // result of instruction execution + + t_uc51(int Itype, int Itech, + class cl_sim *asim); + ~t_uc51(void); + virtual int init(void); + virtual char *id_string(void); + virtual void mk_hw_elements(void); + virtual class cl_mem *mk_mem(enum mem_class type); + + void write_rom(uint addr, ulong data); + virtual int clock_per_cycle(void) { return(12); } + virtual struct dis_entry *dis_tbl(void); + virtual struct name_entry *sfr_tbl(void); + virtual struct name_entry *bit_tbl(void); + //virtual char *disass(uint addr, char *sep); + virtual char *disass(uint addr, char *sep); + virtual void print_disass(uint addr, class cl_console *con); + virtual void print_regs(class cl_console *con); + virtual void reset(void); + virtual void clear_sfr(void); + virtual void analyze(uint addr); + virtual void set_p_flag(void); + virtual void proc_write(uchar *addr); + virtual void proc_write_sp(uchar val); + virtual uchar *get_bit(uchar bitaddr); + virtual uchar *get_bit(uchar bitaddr, t_addr *ev_i, t_addr *ev_s); + virtual int it_priority(uchar ie_mask); + + virtual int do_inst(int step); + +protected: + virtual int do_hardware(int cycles); + virtual int do_interrupt(void); + virtual int accept_it(class it_level *il); + virtual int serial_bit_cnt(int mode); + virtual int do_serial(int cycles); + virtual void received(int c); + virtual int do_timers(int cycles); + virtual int do_timer0(int cycles); + virtual int t0_overflow(void); + virtual int do_timer1(int cycles); + virtual int do_wdt(int cycles); + virtual int idle_pd(void); + virtual int tick(int cycles); + virtual int check_events(void); + + virtual uchar *get_direct(t_mem addr, t_addr *ev_i, t_addr *ev_s); + virtual uchar *get_indirect(uchar addr, int *res); + virtual uchar *get_reg(uchar regnum); + virtual uchar *get_reg(uchar regnum, t_addr *event); + virtual uchar get_bitidx(uchar bitaddr); + virtual uchar read(uchar *addr); + virtual void pre_inst(void); + virtual int exec_inst(void); + virtual void post_inst(void); + + virtual int inst_unknown(uchar code); + virtual int inst_nop(uchar code); /* 00 */ + virtual int inst_ajmp_addr(uchar code); /* [02468ace]1 */ + virtual int inst_ljmp(uchar code); /* 02 */ + virtual int inst_rr(uchar code); /* 03 */ + virtual int inst_inc_a(uchar code); /* 04 */ + virtual int inst_inc_addr(uchar code); /* 05 */ + virtual int inst_inc_$ri(uchar code); /* 06,07 */ + virtual int inst_inc_rn(uchar code); /* 08-0f */ + virtual int inst_jbc_bit_addr(uchar code); /* 10 */ + virtual int inst_acall_addr(uchar code); /* [13579bdf]1 */ + virtual int inst_lcall(uchar code, uint addr); /* 12 */ + virtual int inst_rrc(uchar code); /* 13 */ + virtual int inst_dec_a(uchar code); /* 14 */ + virtual int inst_dec_addr(uchar code); /* 15 */ + virtual int inst_dec_$ri(uchar code); /* 16,17 */ + virtual int inst_dec_rn(uchar code); /* 18-1f */ + virtual int inst_jb_bit_addr(uchar code); /* 20 */ + virtual int inst_ret(uchar code); /* 22 */ + virtual int inst_rl(uchar code); /* 23 */ + virtual int inst_add_a_$data(uchar code); /* 24 */ + virtual int inst_add_a_addr(uchar code); /* 25 */ + virtual int inst_add_a_$ri(uchar code); /* 26,27 */ + virtual int inst_add_a_rn(uchar code); /* 28-2f */ + virtual int inst_jnb_bit_addr(uchar code); /* 30 */ + virtual int inst_reti(uchar code); /* 32 */ + virtual int inst_rlc(uchar code); /* 33 */ + virtual int inst_addc_a_$data(uchar code); /* 34 */ + virtual int inst_addc_a_addr(uchar code); /* 35 */ + virtual int inst_addc_a_$ri(uchar code); /* 36,37 */ + virtual int inst_addc_a_rn(uchar code); /* 38-3f */ + virtual int inst_jc_addr(uchar code); /* 40 */ + virtual int inst_orl_addr_a(uchar code); /* 42 */ + virtual int inst_orl_addr_$data(uchar code); /* 43 */ + virtual int inst_orl_a_$data(uchar code); /* 44 */ + virtual int inst_orl_a_addr(uchar code); /* 45 */ + virtual int inst_orl_a_$ri(uchar code); /* 46,47 */ + virtual int inst_orl_a_rn(uchar code); /* 48-4f */ + virtual int inst_jnc_addr(uchar code); /* 50 */ + virtual int inst_anl_addr_a(uchar code); /* 52 */ + virtual int inst_anl_addr_$data(uchar code); /* 53 */ + virtual int inst_anl_a_$data(uchar code); /* 54 */ + virtual int inst_anl_a_addr(uchar code); /* 55 */ + virtual int inst_anl_a_$ri(uchar code); /* 56,57 */ + virtual int inst_anl_a_rn(uchar code); /* 58-5f */ + virtual int inst_jz_addr(uchar code); /* 60 */ + virtual int inst_xrl_addr_a(uchar code); /* 62 */ + virtual int inst_xrl_addr_$data(uchar code); /* 63 */ + virtual int inst_xrl_a_$data(uchar code); /* 64 */ + virtual int inst_xrl_a_addr(uchar code); /* 65 */ + virtual int inst_xrl_a_$ri(uchar code); /* 66,67 */ + virtual int inst_xrl_a_rn(uchar code); /* 68-6f */ + virtual int inst_jnz_addr(uchar code); /* 70 */ + virtual int inst_orl_c_bit(uchar code); /* 72 */ + virtual int inst_jmp_$a_dptr(uchar code); /* 73 */ + virtual int inst_mov_a_$data(uchar code); /* 74 */ + virtual int inst_mov_addr_$data(uchar code); /* 75 */ + virtual int inst_mov_$ri_$data(uchar code); /* 76,77 */ + virtual int inst_mov_rn_$data(uchar code); /* 78-7f */ + virtual int inst_sjmp(uchar code); /* 80 */ + virtual int inst_anl_c_bit(uchar code); /* 82 */ + virtual int inst_movc_a_$a_pc(uchar code); /* 83 */ + virtual int inst_div_ab(uchar code); /* 84 */ + virtual int inst_mov_addr_addr(uchar code); /* 85 */ + virtual int inst_mov_addr_$ri(uchar code); /* 86,87 */ + virtual int inst_mov_addr_rn(uchar code); /* 88-8f */ + virtual int inst_mov_dptr_$data(uchar code); /* 90 */ + virtual int inst_mov_bit_c(uchar code); /* 92 */ + virtual int inst_movc_a_$a_dptr(uchar code); /* 93 */ + virtual int inst_subb_a_$data(uchar code); /* 94 */ + virtual int inst_subb_a_addr(uchar code); /* 95 */ + virtual int inst_subb_a_$ri(uchar code); /* 96,97 */ + virtual int inst_subb_a_rn(uchar code); /* 98-9f */ + virtual int inst_mov_c_bit(uchar code); /* a2 */ + virtual int inst_inc_dptr(uchar code); /* a3 */ + virtual int inst_mul_ab(uchar code); /* a4 */ + virtual int inst_mov_$ri_addr(uchar code); /* a6,a7 */ + virtual int inst_mov_rn_addr(uchar code); /* a8-af */ + virtual int inst_anl_c_$bit(uchar code); /* b0 */ + virtual int inst_cpl_bit(uchar code); /* b2 */ + virtual int inst_cpl_c(uchar code); /* b3 */ + virtual int inst_cjne_a_$data_addr(uchar code); /* b4 */ + virtual int inst_cjne_a_addr_addr(uchar code); /* b5 */ + virtual int inst_cjne_$ri_$data_addr(uchar code); /* b6,b7 */ + virtual int inst_cjne_rn_$data_addr(uchar code); /* b8-bf */ + virtual int inst_push(uchar code); /* c0 */ + virtual int inst_clr_bit(uchar code); /* c2 */ + virtual int inst_clr_c(uchar code); /* c3*/ + virtual int inst_swap(uchar code); /* c4 */ + virtual int inst_xch_a_addr(uchar code); /* c5 */ + virtual int inst_xch_a_$ri(uchar code); /* c6,c7 */ + virtual int inst_xch_a_rn(uchar code); /* c8-cf */ + virtual int inst_pop(uchar code); /* d0 */ + virtual int inst_setb_bit(uchar code); /* d2 */ + virtual int inst_setb_c(uchar code); /* d3 */ + virtual int inst_da_a(uchar code); /* d4 */ + virtual int inst_djnz_addr_addr(uchar code); /* d5 */ + virtual int inst_xchd_a_$ri(uchar code); /* d6,d7 */ + virtual int inst_djnz_rn_addr(uchar code); /* d8-df */ + virtual int inst_movx_a_$dptr(uchar code); /* e0 */ + virtual int inst_movx_a_$ri(uchar code); /* e2,e3 */ + virtual int inst_clr_a(uchar code); /* e4 */ + virtual int inst_mov_a_addr(uchar code); /* e5 */ + virtual int inst_mov_a_$ri(uchar code); /* e6,e7 */ + virtual int inst_mov_a_rn(uchar code); /* e8-ef */ + virtual int inst_movx_$dptr_a(uchar code); /* f0 */ + virtual int inst_movx_$ri_a(uchar code); /* f2,f3 */ + virtual int inst_cpl_a(uchar code); /* f4 */ + virtual int inst_mov_addr_a(uchar code); /* f5 */ + virtual int inst_mov_$ri_a(uchar code); /* f6,f7 */ + virtual int inst_mov_rn_a(uchar code); /* f8-ff */ +}; + + +#endif + +/* End of s51.src/uc51cl.h */ diff --git a/sim/ucsim/s51.src/uc51r.cc b/sim/ucsim/s51.src/uc51r.cc new file mode 100644 index 00000000..5af287f1 --- /dev/null +++ b/sim/ucsim/s51.src/uc51r.cc @@ -0,0 +1,466 @@ +/* + * Simulator of microcontrollers (uc51r.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include + +// local +#include "uc51rcl.h" +#include "regs51.h" + + +/* + * Making an 8051r CPU object + */ + +t_uc51r::t_uc51r(int Itype, int Itech, class cl_sim *asim): + t_uc52(Itype, Itech, asim) +{ + int i; + + for (i= 0; i < ERAM_SIZE; i++) + ERAM[i]= 0; + clock_out= 0; +} + + +/* + * Resetting of the microcontroller + * + * Original method is extended with handling of WDT. + */ + +void +t_uc51r::reset(void) +{ + t_uc52::reset(); + WDT= -1; // Disable WDT + wdtrst= 0; + MEM(MEM_SFR)[SADDR]= MEM(MEM_SFR)[SADEN]= 0; +} + + +/* + * Copying ERAM to XRAM and vice versa + * + * This two methods are used by command interpreter to make ERAM and + * beginning of XRAM to be equivalent. + */ + +void +t_uc51r::eram2xram(void) +{ + int i; + + for (i= 0; i < ERAM_SIZE; i++) + set_mem(MEM_XRAM, i, ERAM[i]); +} + +void +t_uc51r::xram2eram(void) +{ + int i; + + for (i= 0; i < ERAM_SIZE; i++) + ERAM[i]= get_mem(MEM_XRAM, i); +} + + +/* + * Processing write operation of SFR + * + * Inherited method is extended with WDT handling. + */ + +void +t_uc51r::proc_write(uchar *addr) +{ + t_uc52::proc_write(addr); + // Handling WDT + if (addr == &(MEM(MEM_SFR)[WDTRST])) + { + if ((wdtrst == 0x1e) && + (*addr == 0xe1)) + { + WDT= 0; + sim->cmd->debug("%g sec (%d tick): Watchdog timer enabled/reset" + " PC= 0x%06x\n", + get_rtime(), ticks->ticks, PC); + } + wdtrst= *addr; + } +} + + +/* + * Simulating timers + * + * Calling inherited method to simulate timer #0 and #1 and then + * simulating timer #2. + */ + +int +t_uc51r::do_timers(int cycles) +{ + int res; + + if ((res= t_uc51::do_timers(cycles)) != resGO) + return(res); + return(do_timer2(cycles)); +} + + +/* + * Simulating timer 2 + * + * It is something wrong: T2MOD is not implemented in 52?! + */ + +int +t_uc51r::do_timer2(int cycles) +{ + bool nocount= FALSE; + uint t2mod= get_mem(MEM_SFR, T2MOD); + uint t2con= get_mem(MEM_SFR, T2CON); + uint p1= get_mem(MEM_SFR, P1); + + exf2it->activate(); + if (!(t2con & bmTR2)) + /* Timer OFF */ + return(resGO); + + if (t2mod & bmT2OE) + return(do_t2_clockout(cycles)); + + if (t2con & (bmRCLK | bmTCLK)) + return(do_t2_baud(cycles)); + + /* Determining nr of input clocks */ + if (!(t2con & bmTR2)) + nocount= TRUE; // Timer OFF + else + if (t2con & bmC_T2) + { + // Counter mode, falling edge on P1.0 (T2) + if ((prev_p1 & bmT2) && + !(p1 & port_pins[1] & bmT2)) + cycles= 1; + else + nocount= TRUE; + } + /* Counting */ + while (cycles--) + { + if (t2con & bmCP_RL2) + do_t2_capture(&cycles, nocount); + else + { + int overflow; + overflow= 0; + /* Auto-Relode mode */ + if (t2mod & bmDCEN) + { + /* DCEN= 1 */ + exf2it->deactivate(); + if (nocount) + cycles= 0; + else + { + if (p1 & port_pins[1] & bmT2EX) + { + // UP + if (!++(MEM(MEM_SFR)[TL2])) + if (!++(MEM(MEM_SFR)[TH2])) + { + overflow++; + MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[RCAP2H]; + MEM(MEM_SFR)[TL2]= MEM(MEM_SFR)[RCAP2L]; + mem(MEM_SFR)->set_bit1(T2CON, bmTF2); + } + } + else + { + // DOWN + MEM(MEM_SFR)[TL2]--; + if (MEM(MEM_SFR)[TL2] == 0xff) + MEM(MEM_SFR)[TH2]--; + if (MEM(MEM_SFR)[TH2] == MEM(MEM_SFR)[RCAP2H] && + MEM(MEM_SFR)[TL2] == MEM(MEM_SFR)[RCAP2L]) + { + overflow++; + MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[TL2]= 0xff; + mem(MEM_SFR)->set_bit1(T2CON, bmTF2); + } + } + while (overflow--) + MEM(MEM_SFR)[P1]^= bmEXF2; + } + } + else + /* DCEN= 0 */ + do_t2_reload(&cycles, nocount); + } + }// while cycles + + return(resGO); +} + + +/* + * Clock out mode of Timer #2 + */ + +int +t_uc51r::do_t2_clockout(int cycles) +{ + uint t2con= get_mem(MEM_SFR, T2CON); + uint p1= get_mem(MEM_SFR, P1); + + /* Programmable Clock Out Mode */ + if ((prev_p1 & bmT2EX) && + !(p1 & port_pins[1] & bmT2EX) && + (t2con & bmEXEN2)) + mem(MEM_SFR)->set_bit1(T2CON, bmEXF2); + if (t2con & bmCP_RL2) + return(resGO); + if (t2con & bmC_T2) + { + if ((prev_p1 & bmT2) && + !(p1 & port_pins[1] & bmT2)) + cycles= 1; + else + cycles= 0; + } + else + cycles*= 6; + if (t2con & bmTR2) + while (cycles--) + { + if (!++(MEM(MEM_SFR)[TL2])) + if (!++(MEM(MEM_SFR)[TH2])) + { + MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[RCAP2H]; + MEM(MEM_SFR)[TL2]= MEM(MEM_SFR)[RCAP2L]; + clock_out++; + if (!(t2con & bmC_T2)) + { + SET_BIT((clock_out&1), P1, bmT2); + } + } + } + return(resGO); +} + + +/* + * Handling serial line + */ + +int +t_uc51r::serial_bit_cnt(int mode) +{ + int divby= 12; + int *tr_src= 0, *rec_src= 0; + + switch (mode) + { + case 0: + divby = 12; + tr_src = &s_tr_tick; + rec_src= &s_rec_tick; + break; + case 1: + case 3: + divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32; + tr_src = (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_tr_t2):(&s_tr_t1); + rec_src= (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_rec_t2):(&s_rec_t1); + break; + case 2: + divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32; + tr_src = &s_tr_tick; + rec_src= &s_rec_tick; + break; + } + if (s_sending) + { + while (*tr_src >= divby) + { + (*tr_src)-= divby; + s_tr_bit++; + } + } + if (s_receiving) + { + while (*rec_src >= divby) + { + (*rec_src)-= divby; + s_rec_bit++; + } + } + return(0); +} + +void +t_uc51r::received(int c) +{ + uint br= get_mem(MEM_SFR, SADDR) | get_mem(MEM_SFR, SADEN); + int scon= get_mem(MEM_SFR, SCON); + + if ((0 < scon >> 6) && + (scon & bmSM2)) + { + if ( + /* Check for individual address */ + ((get_mem(MEM_SFR, SADDR) & get_mem(MEM_SFR, SADEN)) == + (c & get_mem(MEM_SFR, SADEN))) + || + /* Check for broadcast address */ + (br == (br & c)) + ) + mem(MEM_SFR)->set_bit1(SCON, bmRI); + return; + } + mem(MEM_SFR)->set_bit1(SCON, bmRI); +} + + +/* + * Handling WDT + */ + +int +t_uc51r::do_wdt(int cycles) +{ + if (WDT >= 0) + { + WDT+= cycles; +fprintf(stderr,"WDT=%d\n",WDT); + if (WDT & ~(0x3fff)) + { + sim->cmd->debug("%g sec (%d ticks): " + "Watchdog timer resets the CPU, PC= 0x%06x\n", + get_rtime(), ticks->ticks, PC); + reset(); + return(resWDTRESET); + } + } + return(resGO); +} + + +/* + * 0xe0 1 24 MOVX A,@DPTR + *____________________________________________________________________________ + * + */ + +int +t_uc51r::inst_movx_a_$dptr(uchar code) +{ + if ((get_mem(MEM_SFR, AUXR) & bmEXTRAM) || + MEM(MEM_SFR)[DPH]) + MEM(MEM_SFR)[event_at.ws= ACC]= read_mem(MEM_XRAM, + event_at.rx= + MEM(MEM_SFR)[DPH]*256+ + MEM(MEM_SFR)[DPL]); + else + MEM(MEM_SFR)[event_at.ws= ACC]= ERAM[event_at.rx= MEM(MEM_SFR)[DPL]]; + tick(1); + return(resGO); +} + + +/* + * 0xe2-0xe3 1 24 MOVX A,@Ri + *____________________________________________________________________________ + * + */ + +int +t_uc51r::inst_movx_a_$ri(uchar code) +{ + uchar *addr; + int res; + + addr= get_indirect(*(get_reg(code & 0x01)), &res); + if (get_mem(MEM_SFR, AUXR) & bmEXTRAM) + MEM(MEM_SFR)[event_at.ws= ACC]= + read_mem(MEM_XRAM, + event_at.rx= (MEM(MEM_SFR)[P2]&port_pins[2])*256+*addr); + else + MEM(MEM_SFR)[event_at.ws= ACC]= ERAM[event_at.rx= *addr]; + tick(1); + return(res); +} + + +/* + * 0xf0 1 24 MOVX @DPTR,A + *____________________________________________________________________________ + * + */ + +int +t_uc51r::inst_movx_$dptr_a(uchar code) +{ + if ((get_mem(MEM_SFR, AUXR) & bmEXTRAM) || + MEM(MEM_SFR)[DPH]) + write_mem(MEM_XRAM, + event_at.wx= MEM(MEM_SFR)[DPH]*256+MEM(MEM_SFR)[DPL], + MEM(MEM_SFR)[event_at.rs= ACC]); + else + ERAM[event_at.wx= MEM(MEM_SFR)[DPL]]= MEM(MEM_SFR)[event_at.rs= ACC]; + return(resGO); +} + + +/* + * 0xf2-0xf3 1 24 MOVX @Ri,A + *____________________________________________________________________________ + * + */ + +int +t_uc51r::inst_movx_$ri_a(uchar code) +{ + uchar *addr; + int res; + + addr= get_indirect(event_at.wi= *(get_reg(code & 0x01)), &res); + if (get_mem(MEM_SFR, AUXR) & bmEXTRAM) + write_mem(MEM_XRAM, + event_at.wx= (MEM(MEM_SFR)[P2] & port_pins[2])*256 + *addr, + MEM(MEM_SFR)[ACC]); + else + ERAM[event_at.wx= *addr]= MEM(MEM_SFR)[ACC]; + tick(1); + return(res); +} + + +/* End of s51.src/uc51r.cc */ diff --git a/sim/ucsim/s51.src/uc51rcl.h b/sim/ucsim/s51.src/uc51rcl.h new file mode 100644 index 00000000..535ceb9f --- /dev/null +++ b/sim/ucsim/s51.src/uc51rcl.h @@ -0,0 +1,73 @@ +/* + * Simulator of microcontrollers (uc51rcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef UC51RCL_HEADER +#define UC51RCL_HEADER + +#include "ddconfig.h" + +#include "uc52cl.h" +#include "itsrccl.h" + + +class t_uc51r: public t_uc52 +{ +protected: + int clock_out; + int WDT; // If negative then WDT is disabled + uchar wdtrst; + +public: + uchar ERAM[ERAM_SIZE]; + +public: + t_uc51r(int Itype, int Itech, class cl_sim *asim); + + virtual void reset(void); + + virtual void eram2xram(void); + virtual void xram2eram(void); + + virtual void proc_write(uchar *addr); + + virtual int do_timers(int cycles); + virtual int do_timer2(int cycles); + virtual int do_t2_clockout(int cycles); + virtual int serial_bit_cnt(int mode); + virtual void received(int c); + virtual int do_wdt(int cycles); + + virtual int inst_movx_a_$dptr(uchar code); /* e0 */ + virtual int inst_movx_a_$ri(uchar code); /* e2,e3 */ + virtual int inst_movx_$dptr_a(uchar code); /* f0 */ + virtual int inst_movx_$ri_a(uchar code); /* f2,f3 */ +}; + + +#endif + +/* End of s51.src/uc52cl.h */ diff --git a/sim/ucsim/s51.src/uc52.cc b/sim/ucsim/s51.src/uc52.cc new file mode 100644 index 00000000..8f181ffe --- /dev/null +++ b/sim/ucsim/s51.src/uc52.cc @@ -0,0 +1,310 @@ +/* + * Simulator of microcontrollers (uc52.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include + +// local +#include "uc52cl.h" +#include "regs51.h" +#include "timer2cl.h" + + +/* + * Making an 8052 CPU object + */ + +t_uc52::t_uc52(int Itype, int Itech, class cl_sim *asim): + t_uc51(Itype, Itech, asim) +{ + it_sources->add(new cl_it_src(bmET2, T2CON, bmTF2, 0x002b, false, + "timer #2 TF2")); + exf2it= new cl_it_src(bmET2, T2CON, bmEXF2, 0x002b, false, + "timer #2 EXF2"); + it_sources->add(exf2it); +} + + +void +t_uc52::mk_hw_elements(void) +{ + class cl_hw *h; + + t_uc51::mk_hw_elements(); + hws->add(h= new cl_timer2(this)); + h->init(); +} + + +/* + * Calculating address of indirectly addressed IRAM cell + * + * If CPU is 8051 and addr is over 127, it must be illegal! But in 52 + * it is legal. + * + */ + +uchar * +t_uc52::get_indirect(uchar addr, int *res) +{ + *res= resGO; + return(&(MEM(MEM_IRAM)[addr])); +} + + +/* + * Simulating timers + * + * Calling inherited method to simulate timer #0 and #1 and then + * simulating timer #2. + * + */ + +int +t_uc52::do_timers(int cycles) +{ + int res; + + if ((res= t_uc51::do_timers(cycles)) != resGO) + return(res); + return(do_timer2(cycles)); +} + + +/* + * Simulating timer 2 + */ + +int +t_uc52::do_timer2(int cycles) +{ + bool nocount= FALSE; + uint t2con= get_mem(MEM_SFR, T2CON); + + exf2it->activate(); + if (!(t2con & bmTR2)) + /* Timer OFF */ + return(resGO); + + if (t2con & (bmRCLK | bmTCLK)) + return(do_t2_baud(cycles)); + + /* Determining nr of input clocks */ + if (!(t2con & bmTR2)) + nocount= TRUE; // Timer OFF + else + if (t2con & bmC_T2) + { + // Counter mode, falling edge on P1.0 (T2) + if ((prev_p1 & bmT2) && + !(get_mem(MEM_SFR, P1) & port_pins[1] & bmT2)) + cycles= 1; + else + nocount= TRUE; + } + /* Counting */ + while (cycles--) + { + if (t2con & bmCP_RL2) + do_t2_capture(&cycles, nocount); + else + do_t2_reload(&cycles, nocount); + }// while cycles + + return(resGO); +} + + +/* + * Baud rate generator mode of Timer #2 + */ + +int +t_uc52::do_t2_baud(int cycles) +{ + uint t2con= get_mem(MEM_SFR, T2CON); + uint p1= get_mem(MEM_SFR, P1); + + /* Baud Rate Generator */ + if ((prev_p1 & bmT2EX) && + !(p1 & port_pins[1] & bmT2EX) && + (t2con & bmEXEN2)) + mem(MEM_SFR)->set_bit1(T2CON, bmEXF2); + if (t2con & bmC_T2) + { + if ((prev_p1 & bmT2) && + !(p1 & port_pins[1] & bmT2)) + cycles= 1; + else + cycles= 0; + } + else + cycles*= 6; + if (t2con & bmTR2) + while (cycles--) + { + if (!++(MEM(MEM_SFR)[TL2])) + if (!++(MEM(MEM_SFR)[TH2])) + { + MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[RCAP2H]; + MEM(MEM_SFR)[TL2]= MEM(MEM_SFR)[RCAP2L]; + s_rec_t2++; + s_tr_t2++; + } + } + return(resGO); +} + + +/* + * Capture function of Timer #2 + */ + +void +t_uc52::do_t2_capture(int *cycles, bool nocount) +{ + uint p1= get_mem(MEM_SFR, P1); + uint t2con= get_mem(MEM_SFR, T2CON); + + /* Capture mode */ + if (nocount) + *cycles= 0; + else + { + if (!++(MEM(MEM_SFR)[TL2])) + { + if (!++(MEM(MEM_SFR)[TH2])) + mem(MEM_SFR)->set_bit1(T2CON, bmTF2); + } + } + // capture + if ((prev_p1 & bmT2EX) && + !(p1 & port_pins[1] & bmT2EX) && + (t2con & bmEXEN2)) + { + MEM(MEM_SFR)[RCAP2H]= MEM(MEM_SFR)[TH2]; + MEM(MEM_SFR)[RCAP2L]= MEM(MEM_SFR)[TL2]; + mem(MEM_SFR)->set_bit1(T2CON, bmEXF2); + prev_p1&= ~bmT2EX; // Falling edge has been handled + } +} + + +/* + * Auto Reload mode of Timer #2, counting UP + */ + +void +t_uc52::do_t2_reload(int *cycles, bool nocount) +{ + int overflow; + bool ext2= 0; + + /* Auto-Relode mode */ + overflow= 0; + if (nocount) + *cycles= 0; + else + { + if (!++(MEM(MEM_SFR)[TL2])) + { + if (!++(MEM(MEM_SFR)[TH2])) + { + mem(MEM_SFR)->set_bit1(T2CON, bmTF2); + overflow++; + } + } + } + // reload + if ((prev_p1 & bmT2EX) && + !(get_mem(MEM_SFR, P1) & port_pins[1] & bmT2EX) && + (get_mem(MEM_SFR, T2CON) & bmEXEN2)) + { + ext2= TRUE; + mem(MEM_SFR)->set_bit1(T2CON, bmEXF2); + prev_p1&= ~bmT2EX; // Falling edge has been handled + } + if (overflow || + ext2) + { + MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[RCAP2H]; + MEM(MEM_SFR)[TL2]= MEM(MEM_SFR)[RCAP2L]; + } +} + + +/* + * + */ + +int +t_uc52::serial_bit_cnt(int mode) +{ + int divby= 12; + int *tr_src= 0, *rec_src= 0; + + switch (mode) + { + case 0: + divby = 12; + tr_src = &s_tr_tick; + rec_src= &s_rec_tick; + break; + case 1: + case 3: + divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32; + tr_src = (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_tr_t2):(&s_tr_t1); + rec_src= (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_rec_t2):(&s_rec_t1); + break; + case 2: + divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32; + tr_src = &s_tr_tick; + rec_src= &s_rec_tick; + break; + } + if (s_sending) + { + while (*tr_src >= divby) + { + (*tr_src)-= divby; + s_tr_bit++; + } + } + if (s_receiving) + { + while (*rec_src >= divby) + { + (*rec_src)-= divby; + s_rec_bit++; + } + } + return(0); +} + + +/* End of s51.src/uc52.cc */ diff --git a/sim/ucsim/s51.src/uc52cl.h b/sim/ucsim/s51.src/uc52cl.h new file mode 100644 index 00000000..e0d6e61a --- /dev/null +++ b/sim/ucsim/s51.src/uc52cl.h @@ -0,0 +1,61 @@ +/* + * Simulator of microcontrollers (uc52cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef UC52CL_HEADER +#define UC52CL_HEADER + +#include "ddconfig.h" + +#include "uc51cl.h" +#include "itsrccl.h" + + +class t_uc52: public t_uc51 +{ +protected: + class cl_it_src *exf2it; + int s_rec_t2; // T2 overflows for receiving + int s_tr_t2; // T2 overflows for sending + +public: + t_uc52(int Itype, int Itech, class cl_sim *asim); + virtual void mk_hw_elements(void); + + virtual uchar *get_indirect(uchar addr, int *res); + + virtual int do_timers(int cycles); + virtual int do_timer2(int cycles); + virtual int do_t2_baud(int cycles); + virtual void do_t2_capture(int *cycles, bool nocount); + virtual void do_t2_reload(int *cycles, bool nocount); + virtual int serial_bit_cnt(int mode); +}; + + +#endif + +/* End of s51.src/uc52cl.h */ diff --git a/sim/ucsim/s51.src/uc89c51r.cc b/sim/ucsim/s51.src/uc89c51r.cc new file mode 100644 index 00000000..4d038386 --- /dev/null +++ b/sim/ucsim/s51.src/uc89c51r.cc @@ -0,0 +1,307 @@ +/* + * Simulator of microcontrollers (uc89c51r.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include + +// local +#include "uc89c51rcl.h" +#include "regs51.h" + + +t_uc89c51r::t_uc89c51r(int Itype, int Itech, class cl_sim *asim): + t_uc51r(Itype, Itech, asim) +{ + it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF4, 0x0033, false, + "PCA module #4")); + it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF3, 0x0033, false, + "PCA module #3")); + it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF2, 0x0033, false, + "PCA module #2")); + it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF1, 0x0033, false, + "PCA module #1")); + it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF0, 0x0033, false, + "PCA module #0")); + it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCF, 0x0033, false, + "PCA counter")); +} + + +void +t_uc89c51r::reset(void) +{ + t_uc51r::reset(); + mem(MEM_SFR)->set_bit1(CCAPM0, bmECOM); + mem(MEM_SFR)->set_bit1(CCAPM1, bmECOM); + mem(MEM_SFR)->set_bit1(CCAPM2, bmECOM); + mem(MEM_SFR)->set_bit1(CCAPM3, bmECOM); + mem(MEM_SFR)->set_bit1(CCAPM4, bmECOM); + t0_overflows= 0; + dpl0= dph0= dpl1= dph1= 0; + set_mem(MEM_SFR, IPH, 0); +} + +void +t_uc89c51r::proc_write(uchar *addr) +{ + t_uc51r::proc_write(addr); + + if (addr == &(MEM(MEM_SFR)[CCAP0L])) + mem(MEM_SFR)->set_bit0(CCAPM0, bmECOM); + if (addr == &(MEM(MEM_SFR)[CCAP0H])) + mem(MEM_SFR)->set_bit1(CCAPM0, bmECOM); + + if (addr == &(MEM(MEM_SFR)[CCAP1L])) + mem(MEM_SFR)->set_bit0(CCAPM1, bmECOM); + if (addr == &(MEM(MEM_SFR)[CCAP1H])) + mem(MEM_SFR)->set_bit1(CCAPM1, bmECOM); + + if (addr == &(MEM(MEM_SFR)[CCAP2L])) + mem(MEM_SFR)->set_bit0(CCAPM2, bmECOM); + if (addr == &(MEM(MEM_SFR)[CCAP2H])) + mem(MEM_SFR)->set_bit1(CCAPM2, bmECOM); + + if (addr == &(MEM(MEM_SFR)[CCAP3L])) + mem(MEM_SFR)->set_bit0(CCAPM3, bmECOM); + if (addr == &(MEM(MEM_SFR)[CCAP3H])) + mem(MEM_SFR)->set_bit1(CCAPM3, bmECOM); + + if (addr == &(MEM(MEM_SFR)[CCAP4L])) + mem(MEM_SFR)->set_bit0(CCAPM4, bmECOM); + if (addr == &(MEM(MEM_SFR)[CCAP4H])) + mem(MEM_SFR)->set_bit1(CCAPM4, bmECOM); + + if (addr == &(MEM(MEM_SFR)[AUXR])) + mem(MEM_SFR)->set_bit0(AUXR, 0x04); +} + +uchar +t_uc89c51r::read(uchar *addr) +{ + return(t_uc51r::read(addr)); +} + +int +t_uc89c51r::it_priority(uchar ie_mask) +{ + uchar l, h; + + l= get_mem(MEM_SFR, IP) & ie_mask; + h= get_mem(MEM_SFR, IPH) & ie_mask; + if (!h && !l) + return(0); + if (!h && l) + return(1); + if (h && !l) + return(2); + if (h && l) + return(3); + return(0); +} + +void +t_uc89c51r::pre_inst(void) +{ + if (get_mem(MEM_SFR, AUXR1) & bmDPS) + { + set_mem(MEM_SFR, DPL, dpl1); + set_mem(MEM_SFR, DPH, dph1); + } + else + { + set_mem(MEM_SFR, DPL, dpl0); + set_mem(MEM_SFR, DPH, dph0); + } +} + +void +t_uc89c51r::post_inst(void) +{ + if (get_mem(MEM_SFR, AUXR1) & bmDPS) + { + dpl1= get_mem(MEM_SFR, DPL); + dph1= get_mem(MEM_SFR, DPH); + } + else + { + dpl0= get_mem(MEM_SFR, DPL); + dph0= get_mem(MEM_SFR, DPH); + } +} + + +/* + * Simulating timers + * + * Calling inherited method to simulate timer #0, #1, #2 and then + * simulating Programmable Counter Array + */ + +int +t_uc89c51r::do_timers(int cycles) +{ + int res; + + if ((res= t_uc51r::do_timers(cycles)) != resGO) + return(res); + return(do_pca(cycles)); +} + +int +t_uc89c51r::t0_overflow(void) +{ + uchar cmod= get_mem(MEM_SFR, CMOD) & (bmCPS0|bmCPS1); + + if (cmod == bmCPS1) + t0_overflows++; + return(0); +} + + +/* + * Simulating Programmable Counter Array + */ + +int +t_uc89c51r::do_pca(int cycles) +{ + int ret= resGO; + uint ccon= get_mem(MEM_SFR, CCON); + + if (!(ccon & bmCR)) + return(resGO); + if (state == stIDLE && + (ccon & bmCIDL)) + return(resGO); + + switch (get_mem(MEM_SFR, CMOD) & (bmCPS1|bmCPS0)) + { + case 0: + ret= do_pca_counter(cycles); + break; + case bmCPS0: + ret= do_pca_counter(cycles*3); + break; + case bmCPS1: + ret= do_pca_counter(t0_overflows); + t0_overflows= 0; + break; + case (bmCPS0|bmCPS1): + if ((prev_p1 & bmECI) != 0 & + (get_mem(MEM_SFR, P1) & bmECI) == 0) + do_pca_counter(1); + break; + } + return(ret); +} + +int +t_uc89c51r::do_pca_counter(int cycles) +{ + while (cycles--) + { + if (++(MEM(MEM_SFR)[CL]) == 0) + { + if (++(MEM(MEM_SFR)[CH]) == 0) + { + /* CH,CL overflow */ + mem(MEM_SFR)->set_bit1(CCON, bmCF); + do_pca_module(0); + do_pca_module(1); + do_pca_module(2); + do_pca_module(3); + do_pca_module(4); + } + } + } + return(resGO); +} + +int +t_uc89c51r::do_pca_module(int nr) +{ + uchar CCAPM[5]= {0xda, 0xdb, 0xdc, 0xdd, 0xde}; + uchar CCAPL[5]= {0xea, 0xeb, 0xec, 0xed, 0xee}; + uchar CCAPH[5]= {0xfa, 0xfb, 0xfc, 0xfd, 0xfe}; + uchar bmCEX[5]= {bmCEX0, bmCEX1, bmCEX2, bmCEX3, bmCEX4}; + uchar bmCCF[5]= {bmCCF0, bmCCF1, bmCCF2, bmCCF3, bmCCF4}; + uchar ccapm= get_mem(MEM_SFR, CCAPM[nr]); + uint p1= get_mem(MEM_SFR, P1); + + if ( + ((ccapm & bmCAPP) && + (prev_p1 & bmCEX[nr]) == 0 && + (p1 & bmCEX[nr]) != 0) + || + ((ccapm & bmCAPN) && + (prev_p1 & bmCEX[nr]) != 0 && + (p1 & bmCEX[nr]) == 0) + ) + { + /* Capture */ + MEM(MEM_SFR)[CCAPL[nr]]= MEM(MEM_SFR)[CL]; + MEM(MEM_SFR)[CCAPH[nr]]= MEM(MEM_SFR)[CH]; + mem(MEM_SFR)->set_bit1(CCON, bmCCF[nr]); + } + + if (ccapm & bmECOM) + { + /* Comparator enabled */ + if (MEM(MEM_SFR)[CL] == MEM(MEM_SFR)[CCAPL[nr]] && + MEM(MEM_SFR)[CH] == MEM(MEM_SFR)[CCAPH[nr]]) + { + /* Match */ + if (nr == 4 && + (MEM(MEM_SFR)[CMOD] & bmWDTE)) + { + reset(); + } + mem(MEM_SFR)->set_bit1(CCON, bmCCF[nr]); + if (ccapm & bmTOG) + { + /* Toggle */ + MEM(MEM_SFR)[P1]^= bmCEX[nr]; + } + } + if (ccapm & bmPWM) + { + /* PWM */ + if (MEM(MEM_SFR)[CL] == 0) + MEM(MEM_SFR)[CCAPL[nr]]= MEM(MEM_SFR)[CCAPH[nr]]; + if (MEM(MEM_SFR)[CL] < MEM(MEM_SFR)[CCAPL[nr]]) + MEM(MEM_SFR)[P1]&= ~(bmCEX[nr]); + else + mem(MEM_SFR)->set_bit1(P1, bmCEX[nr]); + } + } + + return(resGO); +} + + +/* End of s51.src/uc89c51r.cc */ diff --git a/sim/ucsim/s51.src/uc89c51rcl.h b/sim/ucsim/s51.src/uc89c51rcl.h new file mode 100644 index 00000000..d0df66b1 --- /dev/null +++ b/sim/ucsim/s51.src/uc89c51rcl.h @@ -0,0 +1,63 @@ +/* + * Simulator of microcontrollers (uc89c51rcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef UC89C51RCL_HEADER +#define UC89C51RCL_HEADER + +#include "ddconfig.h" + +#include "uc51rcl.h" + + +class t_uc89c51r: public t_uc51r +{ +public: + int t0_overflows; + uchar dpl0, dph0; + uchar dpl1, dph1; + +public: + t_uc89c51r(int Itype, int Itech, class cl_sim *asim); + + virtual void reset(void); + virtual void proc_write(uchar *addr); + virtual uchar read(uchar *addr); + virtual void pre_inst(void); + virtual void post_inst(void); + virtual int it_priority(uchar ie_mask); + + virtual int do_timers(int cycles); + virtual int t0_overflow(void); + virtual int do_pca(int cycles); + virtual int do_pca_counter(int cycles); + virtual int do_pca_module(int nr); +}; + + +#endif + +/* End of s51.src/uc89c51rcl.h */ diff --git a/sim/ucsim/s51.src/where.cc b/sim/ucsim/s51.src/where.cc new file mode 100644 index 00000000..7905cc32 --- /dev/null +++ b/sim/ucsim/s51.src/where.cc @@ -0,0 +1,142 @@ +/* + * Simulator of microcontrollers (where.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include "i_string.h" + +#include "stypes.h" +#include "simcl.h" +#include "memcl.h" +#include "uccl.h" +#include "globals.h" + +#include "cmdutil.h" +#include "dump.h" + + +/* + * Searching for a string in memory + */ + +static void +where_memory(cl_mem *mem, bool cs, class cl_sim *sim) +{ + char *s; + uchar *str; + int len, i, found; + t_addr start; + + if ((s= strtok(NULL, "\0")) == NULL) + return; + str= (uchar *)proc_escape(s, &len); + // assume len < size! + if (!cs) + for (i= 0; i < len; i++) + str[i]= toupper(str[i]); + start= 0; + while (start < mem->size-len) + { + t_addr tmp= start; + found= TRUE; + for (i= 0; found && (iget(start+i):toupper(mem->get(start+i))); + if (found) + { + dump_memory(mem, &tmp, start+len-1, 8, sim->cmd_out(), sim); + start+= len; + } + else + start++; + } + free(str); +} + + +/* + * WHERE IRAM string + */ + +bool +cmd_where_iram(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + where_memory(uc->mem(MEM_IRAM), FALSE, sim); + return(FALSE); +} + +bool +cmd_Where_iram(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + where_memory(uc->mem(MEM_IRAM), TRUE, sim); + return(FALSE); +} + + +/* + * WHERE XRAM string + */ + +bool +cmd_where_xram(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + uc->eram2xram/*FIXME*/(); + where_memory(uc->mem(MEM_XRAM), FALSE, sim); + return(FALSE); +} + +bool +cmd_Where_xram(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + uc->eram2xram/*FIXME*/(); + where_memory(uc->mem(MEM_XRAM), TRUE, sim); + return(FALSE); +} + + +/* + * WHERE CODE string + */ + +bool +cmd_where_code(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + where_memory(uc->mem(MEM_ROM), FALSE, sim); + return(FALSE); +} + +bool +cmd_Where_code(char *cmd, class cl_uc *uc, class cl_sim *sim) +{ + where_memory(uc->mem(MEM_ROM), TRUE, sim); + return(FALSE); +} + + +/* End of s51.src/where.cc */ diff --git a/sim/ucsim/s51.src/where.h b/sim/ucsim/s51.src/where.h new file mode 100644 index 00000000..aa67f2e4 --- /dev/null +++ b/sim/ucsim/s51.src/where.h @@ -0,0 +1,46 @@ +/* + * Simulator of microcontrollers (where.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef WHERE_HEADER +#define WHERE_HEADER + +#include "ddconfig.h" + +#include "uccl.h" + + +extern bool cmd_where_iram(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_Where_iram(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_where_xram(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_Where_xram(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_where_code(char *cmd, class cl_uc *uc, class cl_sim *sim); +extern bool cmd_Where_code(char *cmd, class cl_uc *uc, class cl_sim *sim); + + +#endif + +/* End of s51.src/where.h */ diff --git a/sim/ucsim/sim.src/(c).1 b/sim/ucsim/sim.src/(c).1 new file mode 100644 index 00000000..d673f9fd --- /dev/null +++ b/sim/ucsim/sim.src/(c).1 @@ -0,0 +1,25 @@ +/* + * Simulator of microcontrollers (@@F@@) + * + * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ diff --git a/sim/ucsim/sim.src/Makefile.in b/sim/ucsim/sim.src/Makefile.in new file mode 100644 index 00000000..9f05ae5f --- /dev/null +++ b/sim/ucsim/sim.src/Makefile.in @@ -0,0 +1,116 @@ +# +# S51 sim.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997,99 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = @CXX@ +CPP = @CPP@ +CXXCPP = @CXXCPP@ +RANLIB = @RANLIB@ +INSTALL = @INSTALL@ + +PRJDIR = .. + +DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +CPPFLAGS = @CPPFLAGS@ -I. -I$(PRJDIR) -I$(PRJDIR)/cmd.src +CFLAGS = @CFLAGS@ -Wall +CXXFLAGS = @CXXFLAGS@ -Wall +M_OR_MM = @M_OR_MM@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +includedir = @includedir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +srcdir = @srcdir@ + +OBJECTS = sim.o itsrc.o brk.o option.o arg.o stack.o \ + uc.o hw.o mem.o + + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf sim_lib + +sim.src: all + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + + +# Deleting all the installed files +# -------------------------------- +uninstall: + + +# Performing self-test +# -------------------- +check: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + + +# Creating dependencies +# --------------------- +dep: main.dep + +Makefile.dep: *.cc *.h + $(CXXCPP) $(CPPFLAGS) $(M_OR_MM) *.cc >Makefile.dep + +include Makefile.dep +include clean.mk + +#parser.cc: parser.y + +#plex.cc: plex.l + +# My rules +# -------- + +sim_lib: $(PRJDIR)/libsim.a + +$(PRJDIR)/libsim.a: $(OBJECTS) + ar -rcu $*.a $(OBJECTS) + $(RANLIB) $*.a + +.cc.o: + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@ + +.y.cc: + rm -f $*.cc $*.h + $(YACC) -d $< + mv y.tab.c $*.cc + mv y.tab.h $*.h + +.l.cc: + rm -f $*.cc + $(LEX) -t $< >$*.cc + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(PRJDIR)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" PRJDIR="$(PRJDIR)" freshconf;\ + fi + +# End of sim.src/Makefile diff --git a/sim/ucsim/sim.src/arg.cc b/sim/ucsim/sim.src/arg.cc new file mode 100644 index 00000000..e326ca6d --- /dev/null +++ b/sim/ucsim/sim.src/arg.cc @@ -0,0 +1,209 @@ +/* + * Simulator of microcontrollers (arg.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include "i_string.h" + +// prj +#include "globals.h" + +// sim +#include "simcl.h" + +// cmd +#include "cmdutil.h" + +// local +#include "argcl.h" + + +/* + * Making the argument + */ + +cl_arg::cl_arg(long long lv): + cl_base() +{ + i_value= lv; + s_value= 0; +} + +cl_arg::cl_arg(char *sv): + cl_base() +{ + s_value= sv?strdup(sv):0; +} + +cl_arg::cl_arg(double fv): + cl_base() +{ + f_value= fv; + s_value= 0; +} + +cl_arg::cl_arg(void *pv): + cl_base() +{ + p_value= pv; + s_value= 0; +} + +cl_arg::~cl_arg(void) +{ + if (s_value) + free(s_value); +} + + +/* + * Getting value of the argument + */ + +long long +cl_arg::get_ivalue(void) +{ + return(i_value); +} + +char * +cl_arg::get_svalue(void) +{ + return(s_value); +} + +double +cl_arg::get_fvalue(void) +{ + return(f_value); +} + +void * +cl_arg::get_pvalue(void) +{ + return(p_value); +} + + +/* + * Command parameters + *---------------------------------------------------------------------------- + */ + +cl_cmd_int_arg::cl_cmd_int_arg(long long addr): + cl_cmd_arg(addr) +{} + +cl_cmd_sym_arg::cl_cmd_sym_arg(char *sym): + cl_cmd_arg(sym) +{} + +long +cl_cmd_sym_arg::get_address(void) +{ + struct name_entry *ne; + + if ((ne= get_name_entry(simulator->uc->sfr_tbl(), + get_svalue(), + simulator->uc)) != NULL) + { + return(ne->addr); + } + return(-1); +} + +cl_cmd_str_arg::cl_cmd_str_arg(char *str): + cl_cmd_arg(str) +{} + +cl_cmd_bit_arg::cl_cmd_bit_arg(class cl_cmd_arg *asfr, class cl_cmd_arg *abit): + cl_cmd_arg((long long)0) +{ + sfr= asfr; + bit= abit; +} + +cl_cmd_bit_arg::~cl_cmd_bit_arg(void) +{ + if (sfr) + delete sfr; + if (bit) + delete bit; +} + +long +cl_cmd_bit_arg::get_address(void) +{ + if (sfr) + return(sfr->get_address()); + return(-1); +} + + +/* + * Program arguments + *---------------------------------------------------------------------------- + */ + +cl_prg_arg::cl_prg_arg(char sn, char *ln, long long lv): + cl_arg(lv) +{ + short_name= sn; + long_name = ln?strdup(ln):0; +} + +cl_prg_arg::cl_prg_arg(char sn, char *ln, char *sv): + cl_arg(sv) +{ + short_name= sn; + long_name = ln?strdup(ln):0; +} + +cl_prg_arg::cl_prg_arg(char sn, char *ln, double fv): + cl_arg(fv) +{ + short_name= sn; + long_name = ln?strdup(ln):0; +} + +cl_prg_arg::cl_prg_arg(char sn, char *ln, void *pv): + cl_arg(pv) +{ + short_name= sn; + long_name = ln?strdup(ln):0; +} + +cl_prg_arg::~cl_prg_arg(void) +{ + if (long_name) + free(long_name); +} + + +/* End of arg.cc */ diff --git a/sim/ucsim/sim.src/argcl.h b/sim/ucsim/sim.src/argcl.h new file mode 100644 index 00000000..ff65fa12 --- /dev/null +++ b/sim/ucsim/sim.src/argcl.h @@ -0,0 +1,134 @@ +/* + * Simulator of microcontrollers (argcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef ARGCL_HEADER +#define ARGCL_HEADER + +#include "pobjcl.h" + + +/* + * Base type of arguments/parameters + */ + +class cl_arg: public cl_base +{ +public: + union { + long long i_value; + double f_value; + void *p_value; + }; + char *s_value; + +public: + cl_arg(long long lv); + cl_arg(char *lv); + cl_arg(double fv); + cl_arg(void *pv); + ~cl_arg(void); + + virtual long long get_ivalue(void); + virtual char *get_svalue(void); + virtual double get_fvalue(void); + virtual void *get_pvalue(void); +}; + + +/* + * Command parameters + */ + +class cl_cmd_arg: public cl_arg +{ +public: + cl_cmd_arg(long long i): cl_arg(i) {} + cl_cmd_arg(char *s): cl_arg(s) {} + + virtual int is_string(void) { return(0); } + virtual long get_address(void) { return(-1); } +}; + +class cl_cmd_int_arg: public cl_cmd_arg +{ +public: + cl_cmd_int_arg(long long addr); + + virtual long get_address(void) { return(get_ivalue()); } +}; + +class cl_cmd_sym_arg: public cl_cmd_arg +{ +public: + cl_cmd_sym_arg(char *sym); + + virtual long get_address(void); +}; + +class cl_cmd_str_arg: public cl_cmd_arg +{ +public: + cl_cmd_str_arg(char *str); + + virtual int is_string(void) { return(1); } +}; + +class cl_cmd_bit_arg: public cl_cmd_arg +{ +public: + class cl_cmd_arg *sfr, *bit; + +public: + cl_cmd_bit_arg(class cl_cmd_arg *asfr, class cl_cmd_arg *abit); + ~cl_cmd_bit_arg(void); + + virtual long get_address(void); +}; + + +/* + * Program arguments + */ + +class cl_prg_arg: public cl_arg +{ +public: + char short_name; + char *long_name; + +public: + cl_prg_arg(char sn, char *ln, long long lv); + cl_prg_arg(char sn, char *ln, char *lv); + cl_prg_arg(char sn, char *ln, double fv); + cl_prg_arg(char sn, char *ln, void *pv); + ~cl_prg_arg(void); +}; + + +#endif + +/* End of argcl.h */ diff --git a/sim/ucsim/sim.src/brk.cc b/sim/ucsim/sim.src/brk.cc new file mode 100644 index 00000000..ab50bc15 --- /dev/null +++ b/sim/ucsim/sim.src/brk.cc @@ -0,0 +1,326 @@ +/* + * Simulator of microcontrollers (brk.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include + +#include "pobjcl.h" +#include "brkcl.h" + + +/* + * Base object of breakpoints + */ + +cl_brk::cl_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit): + cl_base() +{ + nr = inr; + addr = iaddr; + perm = iperm; + hit = ihit; + cnt = ihit; +} + +cl_brk::~cl_brk(void) +{} + +bool +cl_brk::do_hit(void) +{ + cnt--; + if (cnt <= 0) + { + cnt= hit; + return(1); + } + return(0); +} + + +/* + * FETCH type of breakpoint + */ + +cl_fetch_brk::cl_fetch_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit): + cl_brk(inr, iaddr, iperm, ihit) +{ + code = 0; +} + +enum brk_type +cl_fetch_brk::type(void) +{ + return(brkFETCH); +} + + +/* + * Base of EVENT type of breakpoints + */ + +cl_ev_brk::cl_ev_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit, + enum brk_event ievent, const char *iid): + cl_brk(inr, iaddr, iperm, ihit) +{ + event= ievent; + id = iid; +} + +enum brk_type +cl_ev_brk::type(void) +{ + return(brkEVENT); +} + +bool +cl_ev_brk::match(struct event_rec *ev) +{ + return(FALSE); +} + + +/* + * WRITE IRAM type of EVENT breakpoints + */ + +cl_wi_brk::cl_wi_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit): + cl_ev_brk(inr, iaddr, iperm, ihit, brkWIRAM, "wi") +{} + +bool +cl_wi_brk::match(struct event_rec *ev) +{ + return(ev->wi == addr); +} + + +/* + * READ IRAM type of EVENT breakpoints + */ + +cl_ri_brk::cl_ri_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit): + cl_ev_brk(inr, iaddr, iperm, ihit, brkRIRAM, "ri") +{} + +bool +cl_ri_brk::match(struct event_rec *ev) +{ + return(ev->ri == addr); +} + + +/* + * WRITE XRAM type of EVENT breakpoints + */ + +cl_wx_brk::cl_wx_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit): + cl_ev_brk(inr, iaddr, iperm, ihit, brkWXRAM, "wx") +{} + +bool +cl_wx_brk::match(struct event_rec *ev) +{ + return(ev->wx == addr); +} + + +/* + * READ XRAM type of EVENT breakpoints + */ + +cl_rx_brk::cl_rx_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit): + cl_ev_brk(inr, iaddr, iperm, ihit, brkRXRAM, "rx") +{} + +bool +cl_rx_brk::match(struct event_rec *ev) +{ + return(ev->rx == addr); +} + + +/* + * WRITE SFR type of EVENT breakpoints + */ + +cl_ws_brk::cl_ws_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit): + cl_ev_brk(inr, iaddr, iperm, ihit, brkWSFR, "ws") +{} + +bool +cl_ws_brk::match(struct event_rec *ev) +{ + return(ev->ws == addr); +} + + +/* + * READ SFR type of EVENT breakpoints + */ + +cl_rs_brk::cl_rs_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit): + cl_ev_brk(inr, iaddr, iperm, ihit, brkRSFR, "rs") +{} + +bool +cl_rs_brk::match(struct event_rec *ev) +{ + return(ev->rs == addr); +} + + +/* + * READ CODE type of EVENT breakpoints + */ + +cl_rc_brk::cl_rc_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit): + cl_ev_brk(inr, iaddr, iperm, ihit, brkRCODE, "rc") +{} + +bool +cl_rc_brk::match(struct event_rec *ev) +{ + return(ev->rc == addr); +} + + +/* + * Collection of break-points + * + * This is a sorted collection, sorted by nr field of brk items. + */ + +brk_coll::brk_coll(t_index alimit, t_index adelta, class cl_rom *arom): + cl_sorted_list(alimit, adelta) +{ + rom= arom; +} + +void * +brk_coll::key_of(void *item) +{ + return((void *)&(((class cl_brk *)(item))->nr)); +} + + +int +brk_coll::compare(void *key1, void *key2) +{ + int k1, k2; + + k1= *(int *)key1; + k2= *(int *)key2; + + if (k1 == k2) + return(0); + else + if (k1 < k2) + return(-1); + else + return(+1); +} + + +/* + * Checking if there is an event breakpoint for the specified event + */ + +bool +brk_coll::there_is_event(enum brk_event ev) +{ + class cl_brk *b; + int i; + + for (i= 0; i < count; i++) + { + b= (class cl_brk *)at(i); + if (b->type() == brkEVENT && + ((class cl_ev_brk *)b)->event == ev) + return(TRUE); + } + return(FALSE); +} + +int +brk_coll::make_new_nr(void) +{ + if (count == 0) + return(1); + class cl_brk *b= (class cl_brk *)(at(count-1)); + return(b->nr+1); +} + +void +brk_coll::add_bp(class cl_brk *bp) +{ + add(bp); + if (rom && + bp->addr < rom->size) + rom->bp_map->set(bp->addr); +} + +void +brk_coll::del_bp(t_addr addr) +{ + int idx; + + if (get_bp(addr, &idx)) + free_at(idx); + if (rom && + addr < rom->size) + rom->bp_map->clear(addr); +} + +class cl_brk * +brk_coll::get_bp(t_addr addr, int *idx) +{ + if (rom && + addr < rom->size && + rom->bp_map->get(addr)) + { + for (*idx= 0; *idx < count; (*idx)++) + { + class cl_brk *b= (class cl_brk *)(at(*idx)); + if (b->addr == addr) + return(b); + } + } + return(0); +} + +bool +brk_coll::bp_at(t_addr addr) +{ + return(rom && + addr < rom->size && + rom->bp_map->get(addr)); +} + + +/* End of brk.cc */ diff --git a/sim/ucsim/sim.src/brkcl.h b/sim/ucsim/sim.src/brkcl.h new file mode 100644 index 00000000..9f864307 --- /dev/null +++ b/sim/ucsim/sim.src/brkcl.h @@ -0,0 +1,211 @@ +/* + * Simulator of microcontrollers (brkcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef BRKCL_HEADER +#define BRKCL_HEADER + +#include "ddconfig.h" + +// prj +#include "pobjcl.h" +#include "stypes.h" + +// sim +#include "memcl.h" + + +/* + * Base object of breakpoints + */ + +class cl_brk: public cl_base +{ +public: + int nr; + t_addr addr; + enum brk_perm perm; // permanency (FIX,DYNAMIC) + int hit; + int cnt; + + cl_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit); + ~cl_brk(void); + + virtual enum brk_type type(void)= 0; + virtual bool do_hit(void); +}; + + +/* + * FETCH type of breakpoints + */ + +class cl_fetch_brk: public cl_brk +{ +public: + uchar code; + + cl_fetch_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit); + + virtual enum brk_type type(void); +}; + + +/* + * Base of EVENT type of breakpoints + */ + +class cl_ev_brk: public cl_brk +{ +public: + cl_ev_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit, + enum brk_event ievent, const char *iid); + + enum brk_event event; + const char *id; + + virtual enum brk_type type(void); + virtual bool match(struct event_rec *ev); +}; + + +/* + * WRITE IRAM + */ + +class cl_wi_brk: public cl_ev_brk +{ +public: + cl_wi_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit); + + virtual bool match(struct event_rec *ev); +}; + + +/* + * READ IRAM + */ + +class cl_ri_brk: public cl_ev_brk +{ +public: + cl_ri_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit); + + virtual bool match(struct event_rec *ev); +}; + + +/* + * WRITE XRAM + */ + +class cl_wx_brk: public cl_ev_brk +{ +public: + cl_wx_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit); + + virtual bool match(struct event_rec *ev); +}; + + +/* + * READ XRAM + */ + +class cl_rx_brk: public cl_ev_brk +{ +public: + cl_rx_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit); + + virtual bool match(struct event_rec *ev); +}; + + +/* + * WRITE SFR + */ + +class cl_ws_brk: public cl_ev_brk +{ +public: + cl_ws_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit); + + virtual bool match(struct event_rec *ev); +}; + + +/* + * READ SFR + */ + +class cl_rs_brk: public cl_ev_brk +{ +public: + cl_rs_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit); + + virtual bool match(struct event_rec *ev); +}; + + +/* + * READ CODE + */ + +class cl_rc_brk: public cl_ev_brk +{ +public: + cl_rc_brk(int inr, t_addr iaddr, enum brk_perm iperm, int ihit); + + virtual bool match(struct event_rec *ev); +}; + + +/* + * Collection of breakpoint sorted by address + */ + +class brk_coll: public cl_sorted_list +{ +public: + class cl_rom *rom; +public: + brk_coll(t_index alimit, t_index adelta, class cl_rom *arom); + virtual void *key_of(void *item); + virtual int compare(void *key1, void *key2); + + virtual bool there_is_event(enum brk_event ev); + virtual int make_new_nr(void); + + virtual void add_bp(class cl_brk *bp); + virtual void del_bp(t_addr addr); + virtual class cl_brk *get_bp(t_addr addr, int *idx); + virtual bool bp_at(t_addr addr); +}; + + +#endif + +/* End of brkcl.h */ diff --git a/sim/ucsim/sim.src/clean.mk b/sim/ucsim/sim.src/clean.mk new file mode 100644 index 00000000..74b12cbe --- /dev/null +++ b/sim/ucsim/sim.src/clean.mk @@ -0,0 +1,22 @@ +# Deleting all files created by building the program +# -------------------------------------------------- +clean: + rm -f *core *[%~] *.[oa] + rm -f .[a-z]*~ + + +# Deleting all files created by configuring or building the program +# ----------------------------------------------------------------- +distclean: clean + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean diff --git a/sim/ucsim/sim.src/conf.mk b/sim/ucsim/sim.src/conf.mk new file mode 100644 index 00000000..879e9bc8 --- /dev/null +++ b/sim/ucsim/sim.src/conf.mk @@ -0,0 +1,10 @@ +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(PRJDIR)/configure.in + cd $(PRJDIR) && $(SHELL) ./config.status + +# End of conf.mk diff --git a/sim/ucsim/sim.src/hw.cc b/sim/ucsim/sim.src/hw.cc new file mode 100644 index 00000000..ed7f8162 --- /dev/null +++ b/sim/ucsim/sim.src/hw.cc @@ -0,0 +1,92 @@ +/* + * Simulator of microcontrollers (hw.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include "i_string.h" + +#include "stypes.h" +#include "hwcl.h" + + +cl_hw::cl_hw(class cl_uc *auc, enum hw_cath cath, int aid, char *aid_string): + cl_base() +{ + flags= HWF_INSIDE; + uc= auc; + cathegory= cath; + id= aid; + if (aid_string && + *aid_string) + id_string= strdup(aid_string); + else + id_string= strdup("unknown hw element"); +} + +cl_hw::~cl_hw(void) +{ + free(id_string); +} + + +/* + * Callback functions for changing memory locations + */ + +ulong +cl_hw::read(class cl_mem *mem, long addr) +{ + // Simply return the value + return(mem->get(addr)); +} + +void +cl_hw::write(class cl_mem *mem, long addr, ulong *val) +{ + // Do not change *val by default +} + + +/* + * Simulating `cycles' number of machine cycle + */ + +int +cl_hw::tick(int cycles) +{ + return(0); +} + +void +cl_hw::print_info(class cl_console *con) +{ + con->printf("%s[%d]\n", id_string, id); +} + + +/* End of hw.cc */ diff --git a/sim/ucsim/sim.src/hwcl.h b/sim/ucsim/sim.src/hwcl.h new file mode 100644 index 00000000..0efce2e6 --- /dev/null +++ b/sim/ucsim/sim.src/hwcl.h @@ -0,0 +1,63 @@ +/* + * Simulator of microcontrollers (hwcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +/* Abstract hw element. It can be a timer, serial line or whatever */ + +#ifndef HWCL_HEADER +#define HWCL_HEADER + +#include "stypes.h" +#include "pobjcl.h" +#include "uccl.h" + +#include "newcmdcl.h" + + +class cl_hw: public cl_base +{ +public: + int flags; + class cl_uc *uc; + enum hw_cath cathegory; + int id; + char *id_string; + +public: + cl_hw(class cl_uc *auc, enum hw_cath cath, int aid, char *aid_string); + ~cl_hw(void); + + virtual ulong read(class cl_mem *mem, long addr); + virtual void write(class cl_mem *mem, long addr, ulong *val); + + virtual int tick(int cycles); + virtual void print_info(class cl_console *con); +}; + + +#endif + +/* End of hwcl.h */ diff --git a/sim/ucsim/sim.src/itsrc.cc b/sim/ucsim/sim.src/itsrc.cc new file mode 100644 index 00000000..d865a976 --- /dev/null +++ b/sim/ucsim/sim.src/itsrc.cc @@ -0,0 +1,110 @@ +/* + * Simulator of microcontrollers (itsrc.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include "i_string.h" + +#include "itsrccl.h" +#include "pobjcl.h" +#include "stypes.h" + + +/* + * Interrupt source + ****************************************************************************** + */ + +cl_it_src::cl_it_src(uchar Iie_mask, + uchar Isrc_reg, + uchar Isrc_mask, + uint Iaddr, + bool Iclr_bit, + char *Iname): + cl_base() +{ + ie_mask = Iie_mask; + src_reg = Isrc_reg; + src_mask= Isrc_mask; + addr = Iaddr; + clr_bit = Iclr_bit; + if (Iname != NULL) + name= strdup(Iname); + else + name= strdup("unknown"); + active= TRUE; +} + +cl_it_src::~cl_it_src(void) +{ + free(name); +} + +bool +cl_it_src::is_active(void) +{ + return(active); +} + +void +cl_it_src::set_active_status(bool Aactive) +{ + active= Aactive; +} + +void +cl_it_src::activate(void) +{ + set_active_status(TRUE); +} + +void +cl_it_src::deactivate(void) +{ + set_active_status(FALSE); +} + + +/* + * Interrupt level + ****************************************************************************** + */ + +it_level::it_level(int alevel, uint aaddr, uint aPC, class cl_it_src *is): + cl_base() +{ + level = alevel; + addr = aaddr; + PC = aPC; + source= is; +} + + + +/* End of itsrc.cc */ diff --git a/sim/ucsim/sim.src/itsrccl.h b/sim/ucsim/sim.src/itsrccl.h new file mode 100644 index 00000000..2e96279d --- /dev/null +++ b/sim/ucsim/sim.src/itsrccl.h @@ -0,0 +1,84 @@ +/* + * Simulator of microcontrollers (itsrccl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef ITSRCCL_HEADER +#define ITSRCCL_HEADER + +#include "pobjcl.h" +#include "stypes.h" + + +/* + * Represents source of interrupt + */ + +class cl_it_src: public cl_base +{ +public: + uchar ie_mask; // Mask in IE register + uchar src_reg; // Register in SFR of source + uchar src_mask; // Mask of source bit in src_reg + uint addr; // Address of service routine + bool clr_bit; // Request bit must be cleared when IT accepted + char *name; // For debug + bool active; // Acceptance can be disabled + + cl_it_src(uchar Iie_mask, + uchar Isrc_reg, + uchar Isrc_mask, + uint Iaddr, + bool Iclr_bit, + char *Iname); + ~cl_it_src(void); + + bool is_active(void); + virtual void set_active_status(bool Aactive); + virtual void activate(void); + virtual void deactivate(void); +}; + + +/* + * This class is used to follow levels of accepted interrupts + * It used on a stack of active interrupt services (it_levels of cl_uc) + */ + +class it_level: public cl_base +{ +public: + int level; + uint addr; + uint PC; + class cl_it_src *source; +public: + it_level(int alevel, uint aaddr, uint aPC, class cl_it_src *is); +}; + + +#endif + +/* End of itsrccl.h */ diff --git a/sim/ucsim/sim.src/mem.cc b/sim/ucsim/sim.src/mem.cc new file mode 100644 index 00000000..e780f4e0 --- /dev/null +++ b/sim/ucsim/sim.src/mem.cc @@ -0,0 +1,403 @@ +/* + * Simulator of microcontrollers (mem.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include +#include +#include +#include "i_string.h" + +// prj +#include "utils.h" +#include "globals.h" + +// cmd +#include "newcmdcl.h" + +// local +#include "memcl.h" +#include "hwcl.h" + + +/* + * Memory location handled specially by a hw element + */ + +cl_memloc::cl_memloc(long addr): + cl_base() +{ + address= addr; + hws= new cl_list(2, 2); + hws->init(); +} + +cl_memloc::~cl_memloc(void) +{ + hws->disconn_all(); + delete hws; +} + +ulong +cl_memloc::read(class cl_mem *mem) +{ + uchar ret= 0; + class cl_hw *hw; + + if (!hws || + hws->count == 0) + return(ret); + if ((hw= (class cl_hw *)(hws->at(0)))) + ret= hw->read(mem, address); + return(ret); +} + +void +cl_memloc::write(class cl_mem *mem, long addr, ulong *val) +{ + class cl_hw *hw; + int i; + + if (!hws) + return; + for (i= 0; i < hws->count; i++) + { + hw= (class cl_hw *)hws->at(0); + hw->write(mem, addr, val); + } +} + + +/* Sorted collection of memory locations */ + +cl_memloc_coll::cl_memloc_coll(void): + cl_sorted_list(2, 2) +{ + Duplicates= FALSE; +} + +void * +cl_memloc_coll::key_of(void *item) +{ + return(&(((class cl_memloc *)item)->address)); +} + +int +cl_memloc_coll::compare(void *key1, void *key2) +{ + if (*(long*)key1 > *(long*)key2) + return(1); + else + if (*(long*)key1 < *(long*)key2) + return(-1); + else + return(0); +} + +class cl_memloc * +cl_memloc_coll::get_loc(long address) +{ + t_index i; + + if (search(&address, i)) + return((class cl_memloc*)(at(i))); + return(0); +} + + +/* + * Memory + ****************************************************************************** + */ + +cl_mem::cl_mem(enum mem_class atype, t_addr asize, int awidth): + cl_base() +{ + int i; + + type= atype; + width= awidth; + size= asize; + mem= 0; + for (i= width, mask= 0; i; i--) + mask= (mask<<1) | 1; + if (width <= 8) + mem= (TYPE_UBYTE *)malloc(size); + else if (width <= 16) + mem= (TYPE_UWORD *)malloc(size*sizeof(TYPE_WORD)); + else + mem= (TYPE_UDWORD *)malloc(size*sizeof(TYPE_DWORD)); + read_locs= new cl_memloc_coll(); + write_locs= new cl_memloc_coll(); + dump_finished= 0; +} + +cl_mem::~cl_mem(void) +{ + if (mem) + free(mem); + delete read_locs; + delete write_locs; +} + +int +cl_mem::init(void) +{ + t_addr i; + + for (i= 0; i < size; i++) + set(i, (type==MEM_ROM)?(-1):0); + return(0); +} + +char * +cl_mem::id_string(void) +{ + char *s= get_id_string(mem_ids, type); + + return(s?s:(char*)"NONE"); +} + +ulong +cl_mem::read(t_addr addr) +{ + class cl_memloc *loc; + + if (addr >= size) + { + //FIXME + fprintf(stderr, "Address 0x%06lx is over 0x%06lx\n", addr, size); + return(0); + } + if ((loc= read_locs->get_loc(addr))) + return(loc->read(this)); + if (width <= 8) + return((((TYPE_UBYTE*)mem)[addr])&mask); + else if (width <= 16) + return((((TYPE_UWORD*)mem)[addr])&mask); + else + return((((TYPE_UDWORD*)mem)[addr])&mask); +} + +ulong +cl_mem::get(t_addr addr) +{ + if (addr >= size) + return(0); + if (width <= 8) + return((((TYPE_UBYTE*)mem)[addr])&mask); + else if (width <= 16) + return((((TYPE_UWORD*)mem)[addr])&mask); + else + return((((TYPE_UDWORD*)mem)[addr])&mask); +} + + +/* + * Modify memory location + */ + +/* Write calls callbacks of HW elements */ + +void +cl_mem::write(t_addr addr, t_mem *val) +{ + class cl_memloc *loc; + + if (addr >= size) + return; + if ((loc= write_locs->get_loc(addr))) + loc->write(this, addr, val); + if (width <= 8) + ((TYPE_UBYTE*)mem)[addr]= (*val)&mask; + else if (width <= 16) + ((TYPE_UWORD*)mem)[addr]= (*val)&mask; + else + ((TYPE_UDWORD*)mem)[addr]= (*val)&mask; +} + +/* Set doesn't call callbacks */ + +void +cl_mem::set(t_addr addr, t_mem val) +{ + if (addr >= size) + return; + if (width <= 8) + ((TYPE_UBYTE*)mem)[addr]= val&mask; + else if (width <= 16) + ((TYPE_UWORD*)mem)[addr]= val&mask; + else + ((TYPE_UDWORD*)mem)[addr]= val&mask; +} + +/* Set or clear bits, without callbacks */ + +void +cl_mem::set_bit1(t_addr addr, t_mem bits) +{ + if (addr >= size) + return; + bits&= mask; + if (width <= 8) + ((TYPE_UBYTE*)mem)[addr]|= bits; + else if (width <= 16) + ((TYPE_UWORD*)mem)[addr]|= bits; + else + ((TYPE_UDWORD*)mem)[addr]|= bits; +} + +void +cl_mem::set_bit0(t_addr addr, t_mem bits) +{ + if (addr >= size) + return; + bits&= mask; + if (width <= 8) + ((TYPE_UBYTE*)mem)[addr]&= ~bits; + else if (width <= 16) + ((TYPE_UWORD*)mem)[addr]&= ~bits; + else + ((TYPE_UDWORD*)mem)[addr]&= ~bits; +} + +void +cl_mem::dump(t_addr start, t_addr stop, int bpl, class cl_console *con) +{ + int i; + + if (start < 0) + { + start= dump_finished; + stop= start+stop; + } + while ((start <= stop) && + (start < size)) + { + con->printf("%06x ", start); + for (i= 0; (i < bpl) && + (start+i < size) && + (start+i <= stop); + i++) + { + char format[10]; + sprintf(format, "%%0%dx ", width/4); + con->printf(format/*"%02x "*/, get(start+i)); + } + while (i < bpl) + { + //FIXME + con->printf(" "); + i++; + } + for (i= 0; (i < bpl) && + (start+i < size) && + (start+i <= stop); + i++) + { + long c= get(start+i); + con->printf("%c", isprint(255&c)?(255&c):'.'); + if (width > 8) + con->printf("%c", isprint(255&(c>>8))?(255&(c>>8)):'.'); + if (width > 16) + con->printf("%c", isprint(255&(c>>16))?(255&(c>>16)):'.'); + if (width > 24) + con->printf("%c", isprint(255&(c>>24))?(255&(c>>24)):'.'); + } + con->printf("\n"); + dump_finished= start+i; + start+= bpl; + } +} + + +/* + * Bitmap + */ + +cl_bitmap::cl_bitmap(long asize): + cl_base() +{ + map= (uchar*)malloc(size= asize/(8*SIZEOF_CHAR)); + memset(map, 0, size); +} + +cl_bitmap::~cl_bitmap(void) +{ + free(map); +} + +void +cl_bitmap::set(long pos) +{ + int i; + + if ((i= pos/(8*SIZEOF_CHAR)) < size) + map[i]|= (1 << (pos & ((8*SIZEOF_CHAR)-1))); +} + +void +cl_bitmap::clear(long pos) +{ + int i; + + if ((i= pos/(8*SIZEOF_CHAR)) < size) + map[i]&= ~(1 << (pos & ((8*SIZEOF_CHAR)-1))); +} + +bool +cl_bitmap::get(long pos) +{ + return(map[pos/(8*SIZEOF_CHAR)] & (1 << (pos & ((8*SIZEOF_CHAR)-1)))); +} + +bool +cl_bitmap::empty(void) +{ + int i; + + for (i= 0; i < size && map[i] == 0; i++) ; + return(i == size); +} + +/* + * Special memory for code (ROM) + */ + +cl_rom::cl_rom(long asize, int awidth): + cl_mem(MEM_ROM, asize, awidth) +{ + bp_map= new cl_bitmap(asize); + inst_map= new cl_bitmap(asize); +} + +cl_rom::~cl_rom(void) +{ + delete bp_map; + delete inst_map; +} + + +/* End of mem.cc */ diff --git a/sim/ucsim/sim.src/memcl.h b/sim/ucsim/sim.src/memcl.h new file mode 100644 index 00000000..4f3e84b5 --- /dev/null +++ b/sim/ucsim/sim.src/memcl.h @@ -0,0 +1,125 @@ +/* + * Simulator of microcontrollers (memcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef MEMCL_HEADER +#define MEMCL_HEADER + +#include "stypes.h" +#include "pobjcl.h" + + +class cl_mem; + +/* Memory location handled specially by a hw element */ + +class cl_memloc: public cl_base +{ +public: + long address; + class cl_list *hws; + +public: + cl_memloc(long addr); + ~cl_memloc(void); + + virtual ulong read(class cl_mem *mem); + virtual void write(class cl_mem *mem, long addr, ulong *val); +}; + +class cl_memloc_coll: public cl_sorted_list +{ +public: + cl_memloc_coll(void); + + virtual void *key_of(void *item); + virtual int compare(void *key1, void *key2); + + class cl_memloc *get_loc(long address); +}; + + +/* Memory */ + +class cl_mem: public cl_base +{ +public: + enum mem_class type; + t_addr size; + ulong mask; + int width; // in bits + union { + void *mem; + uchar *umem8; + }; + class cl_memloc_coll *read_locs, *write_locs; + int dump_finished; + +public: + cl_mem(enum mem_class atype, t_addr asize, int awidth); + ~cl_mem(void); + virtual int init(void); + virtual char *id_string(void); + + virtual ulong read(t_addr addr); + virtual ulong get(t_addr addr); + virtual void write(t_addr addr, t_mem *val); + virtual void set(t_addr addr, t_mem val); + virtual void set_bit1(t_addr addr, t_mem bits); + virtual void set_bit0(t_addr addr, t_mem bits); + virtual void dump(t_addr start, t_addr stop, int bpl, class cl_console *con); +}; + +/* Spec for CODE */ + +class cl_bitmap: public cl_base +{ +public: + uchar *map; + int size; +public: + cl_bitmap(long asize); + ~cl_bitmap(void); + virtual void set(long pos); + virtual void clear(long pos); + virtual bool get(long pos); + virtual bool empty(void); +}; + +class cl_rom: public cl_mem +{ +public: + class cl_bitmap *bp_map; + class cl_bitmap *inst_map; +public: + cl_rom(long asize, int awidth); + ~cl_rom(void); +}; + + +#endif + +/* End of memcl.h */ diff --git a/sim/ucsim/sim.src/option.cc b/sim/ucsim/sim.src/option.cc new file mode 100644 index 00000000..282952ce --- /dev/null +++ b/sim/ucsim/sim.src/option.cc @@ -0,0 +1,173 @@ +/* + * Simulator of microcontrollers (option.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include "i_string.h" + +#include "stypes.h" + +#include "optioncl.h" +#include "simcl.h" + + +/* + * Base class for option's objects + *____________________________________________________________________________ + * + */ + +cl_option::cl_option(void *opt, char *Iid, char *Ihelp): + cl_base() +{ + option= opt; + id = strdup(Iid); + help = strdup(Ihelp); +} + +cl_option::~cl_option(void) +{ + free(id); + free(help); +} + + +/* + * BOOL type of option + *____________________________________________________________________________ + * + */ + +cl_bool_opt::cl_bool_opt(bool *opt, char *Iid, char *Ihelp): + cl_option(opt, Iid, Ihelp) +{} + +void +cl_bool_opt::print(FILE *f) +{ + if (*(bool *)option) + fprintf(f, "TRUE"); + else + fprintf(f, "FALSE"); +} + +bool +cl_bool_opt::get_value(void) +{ + return(*((bool *)option)); +} + +void +cl_bool_opt::set_value(bool opt) +{ + *((bool *)option)= opt; +} + +void +cl_bool_opt::set_value(char *s) +{ + char c; + + if (s) + { + c= toupper(*s); + if (c == '1' || + c == 'T' || + c == 'Y') + *(bool *)option= TRUE; + else + *(bool *)option= FALSE; + } +}; + + +/* + * Debug on console + */ + +cl_cons_debug_opt::cl_cons_debug_opt(class cl_sim *Asim, + char *Iid, + char *Ihelp): + cl_option(0, Iid, Ihelp) +{ + sim= Asim; +} + +void +cl_cons_debug_opt::print(FILE *f) +{ + if (sim->cmd->actual_console && + sim->cmd->actual_console->flags & CONS_DEBUG) + fprintf(f, "TRUE"); + else + fprintf(f, "FALSE"); +} + +bool +cl_cons_debug_opt::get_value(void) +{ + return(sim->cmd->actual_console? + (sim->cmd->actual_console->flags & CONS_DEBUG): + 0); +} + +void +cl_cons_debug_opt::set_value(bool opt) +{ + if (sim->cmd->actual_console) + { + if (opt) + sim->cmd->actual_console->flags|= CONS_DEBUG; + else + sim->cmd->actual_console->flags&= ~CONS_DEBUG; + } + +} + +void +cl_cons_debug_opt::set_value(char *s) +{ + char c; + + if (s && + sim->cmd->actual_console) + { + c= toupper(*s); + if (c == '1' || + c == 'T' || + c == 'Y') + sim->cmd->actual_console->flags|= CONS_DEBUG; + else + sim->cmd->actual_console->flags&= ~CONS_DEBUG; + } +} + + +/* End of option.cc */ diff --git a/sim/ucsim/sim.src/optioncl.h b/sim/ucsim/sim.src/optioncl.h new file mode 100644 index 00000000..ded278d7 --- /dev/null +++ b/sim/ucsim/sim.src/optioncl.h @@ -0,0 +1,89 @@ +/* + * Simulator of microcontrollers (optioncl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef OPTIONCL_HEADER +#define OPTIONCL_HEADER + +#include "ddconfig.h" + +#include + +#include "pobjcl.h" +#include "stypes.h" + + +class cl_option: public cl_base +{ +protected: + void *option; +public: + char *id; + char *help; + +public: + cl_option(void *opt, char *Iid, char *Ihelp); + ~cl_option(void); + + virtual void print(FILE *f)= 0; + + virtual bool get_value(void)= 0; + + virtual void set_value(bool)= 0; + virtual void set_value(char *s)= 0; +}; + + +class cl_bool_opt: public cl_option +{ +public: + cl_bool_opt(bool *opt, char *Iid, char *Ihelp); + + virtual void print(FILE *f); + virtual bool get_value(void); + virtual void set_value(bool); + virtual void set_value(char *s); +}; + +class cl_cons_debug_opt: public cl_option +{ +public: + class cl_sim *sim; +public: + cl_cons_debug_opt(class cl_sim *Asim, char *Iid, char *Ihelp); + + virtual void print(FILE *f); + + virtual bool get_value(void); + + virtual void set_value(bool); + virtual void set_value(char *s); +}; + + +#endif + +/* End of optioncl.h */ diff --git a/sim/ucsim/sim.src/sim.cc b/sim/ucsim/sim.src/sim.cc new file mode 100644 index 00000000..dd19b44c --- /dev/null +++ b/sim/ucsim/sim.src/sim.cc @@ -0,0 +1,652 @@ +/* + * Simulator of microcontrollers (sim.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include +#include +#ifdef HAVE_GETOPT_H +# include +#endif +#include "i_string.h" + +// prj +#include "globals.h" + +// cmd +#include "cmdsetcl.h" +#include "infocl.h" + +// local +#include "simcl.h" + + +/* + * Simulator + */ + +cl_sim::cl_sim(char *more_args, int iargc, char *iargv[]): + cl_base() +{ + argc= iargc; argv= iargv; + uc= 0; + cmd= 0; + arguments= new cl_list(2, 2); + accept_args= more_args?strdup(more_args):0; + in_files= new cl_ustrings(2, 2); +} + +int +cl_sim::init(void) +{ + int i; + + cl_base::init(); + proc_arguments(argc, argv); + cmdset= mk_cmdset(); + cmdset->init(); + build_cmd_set(); + if (!(uc= mk_controller())) + return(1); + uc->init(); + cmd= mk_commander(); + cmd->init(); + if (cmd->cons->get_count() == 0) + { + fprintf(stderr, "No command console available.\n"); + exit(1); + } + for (i= 0; i < in_files->count; i++) + { + char *fname= (char *)(in_files->at(i)); + long l; + if ((l= uc->read_hex_file(fname)) >= 0) + { + cmd->all_printf("%ld words read from %s\n", l, fname); + fprintf(stderr, "%ld words read from %s\n", l, fname); + } + char *prompt; + if (arg_avail('P')) + /*FIXME: putc('\0', f)*/; + else + cmd->all_printf("%s", arg_avail('P')?"\0": + ((prompt= get_sarg(0, "prompt"))?prompt:"> ")); + } + return(0); +} + +cl_sim::~cl_sim(void) +{ + if (uc) + delete uc; +} + +int +cl_sim::proc_arguments(int argc, char *argv[]) +{ + int i, c; + char *opts, *cp; + + opts= (char*)malloc((accept_args?strlen(accept_args):0)+100); + strcpy(opts, "c:p:PX:vV"); +#ifdef SOCKET_AVAIL + strcat(opts, "Z:r:"); +#endif + if (accept_args) + strcat(opts, accept_args); + opterr= 0; + while((c= getopt(argc, argv, opts)) != -1) + switch (c) + { + + case 'c': + arguments->add(new cl_prg_arg('c', 0, optarg)); + break; + +#ifdef SOCKET_AVAIL + case 'Z': + // By Sandeep + arguments->add(new cl_prg_arg('Z', 0, (long long)1)); + if (!optarg || !isdigit(*optarg)) + fprintf(stderr, "expected portnumber to follow -Z\n"); + else { + char *p; + long long l= strtol(optarg, &p, 0); + arguments->add(new cl_prg_arg(0, "Zport", l)); + } + break; +#endif + + case 'p': + arguments->add(new cl_prg_arg(0, "prompt", optarg)); + break; + + case 'P': + arguments->add(new cl_prg_arg('P', 0, (long long)1)); + break; + +#ifdef SOCKET_AVAIL + case 'r': + arguments->add(new cl_prg_arg('r', 0, + (long long)strtol(optarg, NULL, 0))); + break; +#endif + + case 'X': + { + double XTAL; + for (cp= optarg; *cp; *cp= toupper(*cp), cp++); + XTAL= strtod(optarg, &cp); + if (*cp == 'K') + XTAL*= 1e3; + if (*cp == 'M') + XTAL*= 1e6; + if (XTAL == 0) + { + fprintf(stderr, "Xtal frequency must be greather than 0\n"); + exit(1); + } + arguments->add(new cl_prg_arg('X', 0, XTAL)); + break; + } + + case 'v': + printf("%s: %s\n", argv[0], VERSIONSTR); + exit(0); + break; + + case 'V': + arguments->add(new cl_prg_arg('V', 0, (long long)1)); + break; + + case '?': + if ((c= proc_arg(c, optarg))) + exit(c); + break; + + default: + if ((c= proc_arg(c, optarg))) + exit(c); + } + if (!arg_avail("prompt")) + arguments->add(new cl_prg_arg(0, "prompt", "> ")); + + for (i= optind; i < argc; i++) + in_files->add(argv[i]); + + free(opts); + return(0); +} + +int +cl_sim::proc_arg(char arg, char *optarg) +{ + return(0); +} + +int +cl_sim::arg_avail(char name) +{ + class cl_prg_arg *a; + int i; + + for (i= 0; i < arguments->count; i++) + { + a= (class cl_prg_arg *)(arguments->at(i)); + if (a->short_name == name) + return(1); + } + return(0); +} + +int +cl_sim::arg_avail(char *name) +{ + class cl_prg_arg *a; + int i; + + for (i= 0; i < arguments->count; i++) + { + a= (class cl_prg_arg *)(arguments->at(i)); + if (a->long_name && + strcmp(a->long_name, name) == 0) + return(1); + } + return(0); +} + +long long +cl_sim::get_iarg(char sname, char *lname) +{ + class cl_prg_arg *a; + int i; + + for (i= 0; i < arguments->count; i++) + { + a= (class cl_prg_arg *)(arguments->at(i)); + if ((sname && a->short_name == sname) || + (lname && a->long_name && strcmp(a->long_name, lname) == 0)) + return(a->get_ivalue()); + } + return(0); +} + +char * +cl_sim::get_sarg(char sname, char *lname) +{ + class cl_prg_arg *a; + int i; + + for (i= 0; i < arguments->count; i++) + { + a= (class cl_prg_arg *)(arguments->at(i)); + if ((sname && a->short_name == sname) || + (lname && a->long_name && strcmp(a->long_name, lname) == 0)) + return(a->get_svalue()); + } + return(0); +} + + +double +cl_sim::get_farg(char sname, char *lname) +{ + class cl_prg_arg *a; + int i; + + for (i= 0; i < arguments->count; i++) + { + a= (class cl_prg_arg *)(arguments->at(i)); + if ((sname && a->short_name == sname) || + (lname && a->long_name && strcmp(a->long_name, lname) == 0)) + return(a->get_fvalue()); + } + return(0); +} + +void * +cl_sim::get_parg(char sname, char *lname) +{ + class cl_prg_arg *a; + int i; + + for (i= 0; i < arguments->count; i++) + { + a= (class cl_prg_arg *)(arguments->at(i)); + if ((sname && a->short_name == sname) || + (lname && a->long_name && strcmp(a->long_name, lname) == 0)) + return(a->get_pvalue()); + } + return(0); +} + +class cl_commander * +cl_sim::mk_commander() +{ + class cl_commander *cmd= new cl_commander(this); + return(cmd); +} + +class cl_uc * +cl_sim::mk_controller(void) +{ + return(new cl_uc(this)); +} + +class cl_cmdset * +cl_sim::mk_cmdset(void) +{ + return(new cl_cmdset(this)); +} + +class cl_cmd_arg * +cl_sim::mk_cmd_int_arg(long long i) +{ + class cl_cmd_arg *arg= new cl_cmd_int_arg(i); + arg->init(); + return(arg); +} + +class cl_cmd_arg * +cl_sim::mk_cmd_sym_arg(char *s) +{ + class cl_cmd_arg *arg= new cl_cmd_sym_arg(s); + arg->init(); + return(arg); +} + +class cl_cmd_arg * +cl_sim::mk_cmd_str_arg(char *s) +{ + class cl_cmd_arg *arg= new cl_cmd_str_arg(s); + arg->init(); + return(arg); +} + +class cl_cmd_arg * +cl_sim::mk_cmd_bit_arg(class cl_cmd_arg *sfr, class cl_cmd_arg *bit) +{ + class cl_cmd_arg *arg= new cl_cmd_bit_arg(sfr, bit); + arg->init(); + return(arg); +} + + +/* + * Main cycle of the simulator + */ + +int +cl_sim::main(void) +{ + int done= 0; + + while (!done && + (state & SIM_QUIT) == 0) + { + if (state & SIM_GO) + { + uc->do_inst(-1); + if (cmd->input_avail()) + done= cmd->proc_input(); + } + else + { + cmd->wait_input(); + done= cmd->proc_input(); + } + } + return(0); +} + +int +cl_sim::do_cmd(char *cmdstr, class cl_console *console) +{ + class cl_cmdline *cmdline; + class cl_cmd *cmd; + int retval= 0; + + cmdline= new cl_cmdline(cmdstr); + cmdline->init(); + if (console->old_command(cmdline)) + return(console->interpret(cmdstr)); + cmd= cmdset->get_cmd(cmdline); + if (cmd) + retval= cmd->work(cmdline, console); + delete cmdline; + if (cmd) + return(retval); + return(console->interpret(cmdstr)); +} + +void +cl_sim::start(class cl_console *con) +{ + state|= SIM_GO; + con->flags|= CONS_FROZEN; + cmd->frozen_console= con; +} + +void +cl_sim::stop(int reason) +{ + state&= ~SIM_GO; + if (cmd->frozen_console) + { + if (reason == resUSER && + cmd->frozen_console->input_avail()) + cmd->frozen_console->read_line(); + cmd->frozen_console->printf("Stop at 0x%06x: (%d) ", uc->PC, reason); + switch (reason) + { + case resHALT: + cmd->frozen_console->printf("Halted\n"); + break; + case resINV_ADDR: + cmd->frozen_console->printf("Invalid address\n"); + break; + case resSTACK_OV: + cmd->frozen_console->printf("Stack overflow\n"); + break; + case resBREAKPOINT: + cmd->frozen_console->printf("Breakpoint\n"); + break; + case resINTERRUPT: + cmd->frozen_console->printf("Interrupt\n"); + break; + case resWDTRESET: + cmd->frozen_console->printf("Watchdog reset\n"); + break; + case resUSER: + cmd->frozen_console->printf("User stopped\n"); + break; + case resINV_INST: + cmd->frozen_console->printf("Invalid instruction 0x%04x\n", + uc->get_mem(MEM_ROM, uc->PC)); + break; + default: + cmd->frozen_console->printf("Unknown reason\n"); + break; + } + cmd->frozen_console->printf("F 0x%06x\n", uc->PC); // for sdcdb + //if (cmd->actual_console != cmd->frozen_console) + cmd->frozen_console->flags&= ~CONS_FROZEN; + cmd->frozen_console->print_prompt(); + cmd->frozen_console= 0; + } +} + + +/* + * Obsolete methods for old commander + */ + +FILE * +cl_sim::cmd_in(void) +{ + if (!cmd || + cmd->cons->get_count() == 0) + return(stdin); + if (cmd->actual_console) + return(cmd->actual_console->in?cmd->actual_console->in:stdin); + class cl_console *con= (class cl_console *)(cmd->cons->at(0)); + return(con->in?con->in:stdin); +} + +FILE * +cl_sim::cmd_out(void) +{ + if (!cmd || + cmd->cons->get_count() == 0) + return(stdout); + if (cmd->actual_console) + return(cmd->actual_console->out?cmd->actual_console->out:stdout); + class cl_console *con= (class cl_console *)(cmd->cons->at(0)); + return(con->out?con->out:stdout); +} + + +/* + */ + +void +cl_sim::build_cmd_set(void) +{ + class cl_cmd *cmd; + class cl_cmdset *cset; + + cmdset->add(cmd= new cl_conf_cmd(this, "conf", 0, +"conf Configuration", +"long help of conf")); + cmd->init(); + + cmdset->add(cmd= new cl_state_cmd(this, "state", 0, +"state State of simulator", +"long help of state")); + cmd->init(); + + cmdset->add(cmd= new cl_file_cmd(this, "file", 0, +"file \"FILE\" Load FILE into ROM", +"long help of file")); + cmd->init(); + cmd->add_name("load"); + + cmdset->add(cmd= new cl_dl_cmd(this, "download", 0, +"download,dl Load (intel.hex) data", +"long help of download")); + cmd->init(); + cmd->add_name("dl"); + + cset= new cl_cmdset(this); + cset->init(); + cset->add(cmd= new cl_info_bp_cmd(this, "breakpoints", 0, +"info breakpoints Status of user-settable breakpoints", +"long help of info breakpoints")); + cmd->add_name("bp"); + cmd->init(); + cset->add(cmd= new cl_info_reg_cmd(this, "registers", 0, +"info registers List of integer registers and their contents", +"long help of info registers")); + cmd->init(); + cset->add(cmd= new cl_info_hw_cmd(this, "hardware", 0, +"info hardware cathegory\n" +" Status of hardware elements of the CPU", +"long help of info hardware")); + cmd->add_name("hw"); + cmd->init(); + + cmdset->add(cmd= new cl_super_cmd(this, "info", 0, +"info subcommand Information, see `info' command for more help", +"long help of info", cset)); + cmd->init(); + + cmdset->add(cmd= new cl_get_cmd(this, "get", 0, +"get Get", +"long help of get")); + cmd->init(); + + cmdset->add(cmd= new cl_set_cmd(this, "set", 0, +"set Set", +"long help of set")); + cmd->init(); + + cmdset->add(cmd= new cl_timer_cmd(this, "timer", 0, +"timer a|d|g|r|s|v id [direction|value]\n" +" Timer add|del|get|run|stop|value", +"timer add|create|make id [direction] -- create a new timer\n" +"timer del id -- delete a timer\n" +"timer get id -- list timers\n" +"timer run id -- turn a timer ON\n" +"timer stop id -- turn a timer OFF\n" +"timer value id val -- set value of a timer to `val'")); + cmd->init(); + + cmdset->add(cmd= new cl_run_cmd(this, "run", 0, +"run Go", +"long help of run")); + cmd->init(); + //cmd->add_name("g"); + + cmdset->add(cmd= new cl_step_cmd(this, "step", 0, +"step Step", +"long help of step")); + cmd->init(); + cmd->add_name("s"); + + cmdset->add(cmd= new cl_reset_cmd(this, "reset", 0, +"reset Reset", +"long help of reset")); + cmd->init(); + + cmdset->add(cmd= new cl_dump_cmd(this, "dump", 0, +"dump i|x|r|s [start [stop]]\n" +" Dump memory", +"long help of dump")); + cmd->init(); + + cmdset->add(cmd= new cl_di_cmd(this, "di", 0, +"di [start [stop]] Dump Internal RAM", +"long help of di")); + cmd->init(); + + cmdset->add(cmd= new cl_dx_cmd(this, "dx", 0, +"dx [start [stop]] Dump External RAM", +"long help of dx")); + cmd->init(); + + cmdset->add(cmd= new cl_ds_cmd(this, "ds", 0, +"ds [start [stop]] Dump SFR", +"long help of ds")); + cmd->init(); + + cmdset->add(cmd= new cl_dch_cmd(this, "dch", 0, +"dch [start [stop]] Dump code in hex form", +"long help of dch")); + cmd->init(); + + cmdset->add(cmd= new cl_dc_cmd(this, "dc", 0, +"dc [start [stop]] Dump code in disass form", +"long help of dc")); + cmd->init(); + + cmdset->add(cmd= new cl_break_cmd(this, "break", 0, +"break addr [hit] Set fix breakpoint", +"long help of break")); + cmd->init(); + + cmdset->add(cmd= new cl_tbreak_cmd(this, "tbreak", 0, +"tbreak addr [hit] Set temporary breakpoint", +"long help of tbreak")); + cmd->init(); + + cmdset->add(cmd= new cl_clear_cmd(this, "clear", 0, +"clear [addr...] Clear fix breakpoint", +"long help of clear")); + cmd->init(); + + cmdset->add(cmd= new cl_help_cmd(this, "help", 0, +"help Help", +"long help of help")); + cmd->init(); + cmd->add_name("?"); + + cmdset->add(cmd= new cl_quit_cmd(this, "quit", 0, +"quit Quit", +"long help of quit")); + cmd->init(); + + cmdset->add(cmd= new cl_kill_cmd(this, "kill", 0, +"kill Shutdown simulator", +"long help of kill")); + cmd->init(); +} + + +/* End of sim.src/sim.cc */ diff --git a/sim/ucsim/sim.src/simcl.h b/sim/ucsim/sim.src/simcl.h new file mode 100644 index 00000000..042b080b --- /dev/null +++ b/sim/ucsim/sim.src/simcl.h @@ -0,0 +1,99 @@ +/* + * Simulator of microcontrollers (simcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SIMCL_HEADER +#define SIMCL_HEADER + +#include + +// prj +#include "pobjcl.h" + +// cmd +#include "newcmdcl.h" + +// local +#include "uccl.h" +#include "argcl.h" + + +class cl_sim: public cl_base +{ +public: + int state; // See SIM_XXXX + int argc; char **argv; + + class cl_commander *cmd; + class cl_uc *uc; + class cl_cmdset *cmdset; + //class cl_console *frozen_console; + + char *accept_args; + class cl_ustrings *in_files; + class cl_list *arguments; + +public: + cl_sim(char *more_args, int iargc, char *iargv[]); + //cl_sim(class cl_uc *auc); + ~cl_sim(void); + virtual int init(void); + + virtual int proc_arguments(int argc, char *argv[]); + virtual int proc_arg(char arg, char *optarg); + + virtual class cl_commander *mk_commander(void); + virtual class cl_uc *mk_controller(void); + virtual class cl_cmdset *mk_cmdset(void); + virtual void build_cmd_set(void); + virtual class cl_cmd_arg *mk_cmd_int_arg(long long i); + virtual class cl_cmd_arg *mk_cmd_sym_arg(char *s); + virtual class cl_cmd_arg *mk_cmd_str_arg(char *s); + virtual class cl_cmd_arg *mk_cmd_bit_arg(class cl_cmd_arg *sfr, + class cl_cmd_arg *bit); + + int arg_avail(char name); + int arg_avail(char *name); + virtual long long get_iarg(char sname, char *lname); + virtual char *get_sarg(char sname, char *lname); + virtual double get_farg(char sname, char *lname); + virtual void *get_parg(char sname, char *lname); + + virtual int main(void); + virtual int do_cmd(char *cmd, class cl_console *console); + virtual void start(class cl_console *con); + virtual void stop(int reason); + + // Obsolete, for old commander +public: + FILE *cmd_out(void); + FILE *cmd_in(void); +}; + + +#endif + +/* End of simcl.h */ diff --git a/sim/ucsim/sim.src/stack.cc b/sim/ucsim/sim.src/stack.cc new file mode 100644 index 00000000..c8941d67 --- /dev/null +++ b/sim/ucsim/sim.src/stack.cc @@ -0,0 +1,49 @@ +/* + * Simulator of microcontrollers (stack.cc) + * + * Copyright (C) 2000,00 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "stackcl.h" + + +cl_stack_op::cl_stack_op(enum stack_op itype, + t_addr iPC, t_addr iaddr, t_mem idata, + t_addr iSP_before, t_addr iSP_after): + cl_base() +{ + type= itype; + PC= iPC; + addr= iaddr; + data= idata; + SP_before= iSP_before; + SP_after= iSP_after; +} + +cl_stack_op::~cl_stack_op(void) +{ +} + + +/* End of sim.src/stack.cc */ diff --git a/sim/ucsim/sim.src/stackcl.h b/sim/ucsim/sim.src/stackcl.h new file mode 100644 index 00000000..e8f46582 --- /dev/null +++ b/sim/ucsim/sim.src/stackcl.h @@ -0,0 +1,61 @@ +/* + * Simulator of microcontrollers (stackcl.h) + * + * Copyright (C) 2000,00 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef STACKCL_HEADER +#define STACKCL_HEADER + +#include "stypes.h" +#include "pobjcl.h" + + +enum stack_op { + stack_call, + stack_push, + stack_ret, + stack_pop +}; + +class cl_stack_op: public cl_base +{ +public: + enum stack_op type; + t_addr PC; // of instruction + t_addr addr; // called routine + t_mem data; // pushed data + t_addr SP_before; + t_addr SP_after; +public: + cl_stack_op(enum stack_op itype, + t_addr iPC, t_addr iaddr, t_mem idata, + t_addr iSP_before, t_addr iSP_after); + ~cl_stack_op(void); +}; + + +#endif + +/* End of sim.src/stackcl.h */ diff --git a/sim/ucsim/sim.src/uc.cc b/sim/ucsim/sim.src/uc.cc new file mode 100644 index 00000000..d0577919 --- /dev/null +++ b/sim/ucsim/sim.src/uc.cc @@ -0,0 +1,970 @@ +/* + * Simulator of microcontrollers (uc.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include "i_string.h" + +#include "uccl.h" +#include "hwcl.h" +#include "memcl.h" +#include "simcl.h" +#include "itsrccl.h" + + +/* + * Clock counter + */ + +cl_ticker::cl_ticker(int adir, int in_isr, char *aname) +{ + options= TICK_RUN; + if (in_isr) + options|= TICK_INISR; + dir= adir; + ticks= 0; + name= aname?strdup(aname):0; +} + +cl_ticker::~cl_ticker(void) +{ + if (name) + free(name); +} + +int +cl_ticker::tick(int nr) +{ + if (options&TICK_RUN) + ticks+= dir*nr; + return(ticks); +} + +double +cl_ticker::get_rtime(double xtal) +{ + double d; + + d= (double)ticks/xtal; + return(d); +} + +void +cl_ticker::dump(int nr, double xtal, class cl_console *con) +{ + con->printf("timer #%d(\"%s\") %s%s: %g sec (%lu clks)\n", + nr, name?name:"unnamed", + (options&TICK_RUN)?"ON":"OFF", + (options&TICK_INISR)?",ISR":"", + get_rtime(xtal), ticks); +} + + +/* + * Abstract microcontroller + ****************************************************************************** + */ + +cl_uc::cl_uc(class cl_sim *asim): + cl_base() +{ + int i; + sim = asim; + mems= new cl_list(MEM_TYPES, 1); + hws = new cl_list(2, 1); + options= new cl_list(2, 2); + for (i= MEM_ROM; i < MEM_TYPES; i++) + mems->add(0); + ticks= new cl_ticker(+1, 0, "time"); + isr_ticks= new cl_ticker(+1, TICK_INISR, "isr"); + idle_ticks= new cl_ticker(+1, TICK_IDLE, "idle"); + counters= new cl_list(2, 2); + it_levels= new cl_list(2, 2); + it_sources= new cl_list(2, 2); + class it_level *il= new it_level(-1, 0, 0, 0); + it_levels->push(il); + st_ops= new cl_list(2, 2); + sp_max= 0; + sp_avg= 0; +} + + +cl_uc::~cl_uc(void) +{ + delete mems; + delete hws; + delete options; + delete ticks; + delete isr_ticks; + delete idle_ticks; + delete counters; + delete fbrk; + delete ebrk; + delete it_levels; + delete it_sources; + delete st_ops; +} + + +int +cl_uc::init(void) +{ + int mc; + + cl_base::init(); + if (!(sim->arg_avail('X')) || + sim->get_farg('X', 0) == 0) + xtal= 11059200; + else + xtal= sim->get_farg('X', 0); + for (mc= MEM_ROM; mc < MEM_TYPES; mc++) + { + class cl_mem *m= mk_mem((enum mem_class)mc); + mems->put_at(mc, m); + } + ebrk= new brk_coll(2, 2, (class cl_rom *)mem(MEM_ROM)); + fbrk= new brk_coll(2, 2, (class cl_rom *)mem(MEM_ROM)); + fbrk->Duplicates= FALSE; + mk_hw_elements(); + reset(); + return(0); +} + +char * +cl_uc::id_string(void) +{ + return("unknown microcontroller"); +} + +void +cl_uc::reset(void) +{ + class it_level *il; + + PC= 0; + state = stGO; + ticks->ticks= 0; + isr_ticks->ticks= 0; + idle_ticks->ticks= 0; + /*FIXME should we clear user counters?*/ + il= (class it_level *)(it_levels->top()); + while (il && + il->level >= 0) + { + il= (class it_level *)(it_levels->pop()); + delete il; + il= (class it_level *)(it_levels->top()); + } + sp_max= 0; + sp_avg= 0; +} + +/* + * Making elements + */ + +class cl_mem * +cl_uc::mk_mem(enum mem_class type) +{ + class cl_mem *m; + + if (get_mem_size(type) <= 0) + return(0); + if (type == MEM_ROM) + m= new cl_rom(get_mem_size(type), get_mem_width(type)); + else + m= new cl_mem(type, get_mem_size(type), get_mem_width(type)); + m->init(); + return(m); +} + +t_addr +cl_uc::get_mem_size(enum mem_class type) +{ + switch (type) + { + case MEM_ROM: return(0x10000); + case MEM_XRAM: return(0x10000); + case MEM_IRAM: return(0x100); + case MEM_SFR: return(0x100); + case MEM_TYPES: + default: return(0); + } + return(0); +} + +int +cl_uc::get_mem_width(enum mem_class type) +{ + return(8); +} + +void +cl_uc::mk_hw_elements(void) +{ +} + + +/* + * Read/write simulated memory + */ + +ulong +cl_uc::read_mem(enum mem_class type, long addr) +{ + class cl_mem *m; + + if ((m= (class cl_mem*)mems->at(type))) + return(m->read(addr)); + //FIXME +fprintf(stderr, "cl_uc::read_mem(type= %d, 0x%06lx) TROUBLE\n", type, addr); + return(0); +} + +ulong +cl_uc::get_mem(enum mem_class type, long addr) +{ + class cl_mem *m; + + if ((m= (class cl_mem*)mems->at(type))) + return(m->get(addr)); + //FIXME +printf("cl_uc::get_mem(type= %d, 0x%06lx) TROUBLE\n", type, addr); + return(0); +} + +void +cl_uc::write_mem(enum mem_class type, long addr, ulong val) +{ + class cl_mem *m; + + if ((m= (class cl_mem*)mems->at(type))) + { + m->write(addr, &val); + //m->mem[addr]= val; + } + //FIXME +else printf("cl_uc::write_mem(type= %d, 0x%06lx, 0x%lx) TROUBLE\n", type, addr, val); +} + +void +cl_uc::set_mem(enum mem_class type, long addr, ulong val) +{ + class cl_mem *m; + + if ((m= (class cl_mem*)mems->at(type))) + m->set(addr, val); + //FIXME +else printf("cl_uc::set_mem(type= %d, 0x%06lx, 0x%lx) TROUBLE\n", type, addr, val); +} + +class cl_mem * +cl_uc::mem(enum mem_class type) +{ + if (mems->count < type) + //FIXME +{printf("TROUBLE\n"); return(0); +} + return((class cl_mem *)(mems->at(type))); +} + +uchar * +cl_uc::MEM(enum mem_class type) +{ + class cl_mem *m; + + if ((m= mem(type)) == 0) + //FIXME +{printf("TROUBLE\n"); return(0); +} + return((TYPE_UBYTE *)(m->mem)); +} + + +/* Local function for `read_hex_file' method to read some bytes */ + +static long +ReadInt(FILE *f, bool *ok, int bytes) +{ + char s2[3]; + long l= 0; + + *ok= FALSE; + while (bytes) + { + if (fscanf(f, "%2c", &s2[0]) == EOF) + return(0); + s2[2]= '\0'; + l= l*256 + strtol(s2, NULL, 16); + bytes--; + } + *ok= TRUE; + return(l); +} + + +/* + * Reading intel hexa file into EROM + *____________________________________________________________________________ + * + * If parameter is a NULL pointer, this function reads data from `cmd_in' + * + */ + +long +cl_uc::read_hex_file(const char *name) +{ + FILE *f; + char c; + long written= 0, recnum= 0; + + uchar dnum; // data number + uchar rtyp=0; // record type + uint addr= 0; // address + uchar rec[300]; // data record + uchar sum ; // checksum + uchar chk ; // check + int i; + bool ok, get_low= 1; + uchar low= 0, high; + + if (!name) + f= sim->/*FIXME*/cmd_in(); + else + if ((f= fopen(name, "r")) == NULL) + { + fprintf(stderr, "Can't open `%s': %s\n", name, strerror(errno)); + return(-1); + } + + //memset(inst_map, '\0', sizeof(inst_map)); + ok= TRUE; + while (ok && + rtyp != 1) + { + while (((c= getc(f)) != ':') && + (c != EOF)) ; + if (c != ':') + {fprintf(stderr, ": not found\n");break;} + recnum++; + dnum= ReadInt(f, &ok, 1);//printf("dnum=%02x",dnum); + chk = dnum; + addr= ReadInt(f, &ok, 2);//printf("addr=%04x",addr); + chk+= (addr & 0xff); + chk+= ((addr >> 8) & 0xff); + rtyp= ReadInt(f, &ok, 1);//printf("rtyp=%02x ",rtyp); + chk+= rtyp; + for (i= 0; ok && (i < dnum); i++) + { + rec[i]= ReadInt(f, &ok, 1);//printf("%02x",rec[i]); + chk+= rec[i]; + } + if (ok) + { + sum= ReadInt(f, &ok, 1);//printf(" sum=%02x\n",sum); + if (ok) + { + if (((sum + chk) & 0xff) == 0) + { + if (rtyp == 0) + { + if (get_mem_width(MEM_ROM) > 8) + addr/= 2; + for (i= 0; i < dnum; i++) + { + if (get_mem_width(MEM_ROM) <= 8) + { + set_mem(MEM_ROM, addr, rec[i]); + addr++; + written++; + } + else if (get_mem_width(MEM_ROM) <= 16) + { + if (get_low) + { + low= rec[i]; + get_low= 0; + } + else + { + high= rec[i]; + set_mem(MEM_ROM, addr, (high*256)+low); + addr++; + written++; + get_low= 1; + } + } + } + } + else + if (sim->get_iarg('V', 0) && + rtyp != 1) + fprintf(sim->cmd_out(), + "Unknown record type %d(0x%x)\n", rtyp, rtyp); + } + else + if (sim->get_iarg('V', 0)) + fprintf(sim->cmd_out(), + "Checksum error (%x instead of %x) in record %ld.\n", + chk, sum, recnum); + } + else + if (sim->get_iarg('V', 0)) + fprintf(sim->cmd_out(), "Read error in record %ld.\n", recnum); + } + } + if (get_mem_width(MEM_ROM) > 8 && + !get_low) + set_mem(MEM_ROM, addr, low); + + if (name) + fclose(f); + if (sim->get_iarg('V', 0)) + fprintf(sim->cmd_out(), "%ld records have been read\n", recnum); + analyze(0); + return(written); +} + + +/* + * Handling instruction map + * + * `inst_at' is checking if the specified address is in instruction + * map and `set_inst_at' marks the address in the map and + * `del_inst_at' deletes the mark. `there_is_inst' cheks if there is + * any mark in the map + */ + +bool +cl_uc::inst_at(uint addr) +{ + class cl_rom *rom= (class cl_rom *)mem(MEM_ROM); + + if (!rom) + return(0); + return(rom->inst_map->get(addr)); +} + +void +cl_uc::set_inst_at(uint addr) +{ + class cl_rom *rom= (class cl_rom *)mem(MEM_ROM); + + if (rom) + rom->inst_map->set(addr); +} + +void +cl_uc::del_inst_at(uint addr) +{ + class cl_rom *rom= (class cl_rom *)mem(MEM_ROM); + + if (rom) + rom->inst_map->clear(addr); +} + +bool +cl_uc::there_is_inst(void) +{ + class cl_rom *rom= (class cl_rom *)mem(MEM_ROM); + + if (!rom) + return(0); + return(!(rom->inst_map->empty())); +} + + +/* + * Manipulating HW elements of the CPU + ***************************************************************************** + */ + +/* Register callback hw objects for mem read/write */ + +void +cl_uc::register_hw_read(enum mem_class type, long addr, class cl_hw *hw) +{ + class cl_mem *m; + class cl_memloc *l; + + if ((m= (class cl_mem*)mems->at(type))) + { + if ((l= m->read_locs->get_loc(addr)) == 0) + { + l= new cl_memloc(addr); + l->init(); + m->read_locs->add(l); + } + l->hws->add(hw); + } + else + printf("cl_uc::register_hw_read TROUBLE\n"); +} + +void +cl_uc::register_hw_write(enum mem_class type, long addr, class cl_hw *hw) +{ +} + +/* Looking for a specific HW element */ + +class cl_hw * +cl_uc::get_hw(enum hw_cath cath, int *idx) +{ + class cl_hw *hw; + int i= 0; + + if (idx) + i= *idx; + for (; i < hws->count; i++) + { + hw= (class cl_hw *)(hws->at(i)); + if (hw->cathegory == cath) + break; + } + if (i >= hws->count) + return(0); + if (idx) + *idx= i; + return(hw); +} + +class cl_hw * +cl_uc::get_hw(enum hw_cath cath, int hwid, int *idx) +{ + class cl_hw *hw; + int i= 0; + + if (idx) + i= *idx; + hw= get_hw(cath, &i); + while (hw && + hw->id != hwid) + { + i++; + hw= get_hw(cath, &i); + } + if (hw && + idx) + *idx= i; + return(hw); +} + + +/* + * Help of the command interpreter + */ + +struct dis_entry * +cl_uc::dis_tbl(void) +{ + static struct dis_entry empty= { 0, 0, 0, 0, NULL }; + return(&empty); +} + +struct name_entry * +cl_uc::sfr_tbl(void) +{ + static struct name_entry empty= { 0, 0 }; + return(&empty); +} + +struct name_entry * +cl_uc::bit_tbl(void) +{ + static struct name_entry empty= { 0, 0 }; + return(&empty); +} + +char * +cl_uc::disass(uint addr, char *sep) +{ + char *buf; + + buf= (char*)malloc(100); + strcpy(buf, "uc::do_disass unimplemented\n"); + return(buf); +} + +void +cl_uc::print_disass(uint addr, class cl_console *con) +{ + con->printf("uc::print_disass unimplemented\n"); +} + +void +cl_uc::print_regs(class cl_console *con) +{ + con->printf("No registers\n"); +} + +int +cl_uc::inst_length(uint code) +{ + struct dis_entry *tabl= dis_tbl(); + int i; + + for (i= 0; tabl[i].mnemonic && (code & tabl[i].mask) != tabl[i].code; i++) ; + return(tabl[i].mnemonic?tabl[i].length:1); +} + +bool +cl_uc::get_name(uint addr, struct name_entry tab[], char *buf) +{ + int i; + + i= 0; + while (tab[i].name && + (!(tab[i].cpu_type & type) || + (tab[i].addr != addr))) + i++; + if (tab[i].name) + strcpy(buf, tab[i].name); + return(tab[i].name != NULL); +} + + +/* + * Execution + */ + +int +cl_uc::tick(int cycles) +{ + class cl_hw *hw; + int i, cpc= clock_per_cycle(); + + // increase time + ticks->tick(cycles * cpc); + class it_level *il= (class it_level *)(it_levels->top()); + if (il->level >= 0) + isr_ticks->tick(cycles * cpc); + if (state == stIDLE) + idle_ticks->tick(cycles * cpc); + for (i= 0; i < counters->count; i++) + { + class cl_ticker *t= (class cl_ticker *)(counters->at(i)); + if (t) + { + if ((t->options&TICK_INISR) || + il->level < 0) + t->tick(cycles * cpc); + } + } + + // tick hws + for (i= 0; i < hws->count; i++) + { + hw= (class cl_hw *)(hws->at(i)); + if (hw->flags & HWF_INSIDE) + hw->tick(cycles); + } + return(0); +} + +class cl_ticker * +cl_uc::get_counter(int nr) +{ + if (nr >= counters->count) + return(0); + return((class cl_ticker *)(counters->at(nr))); +} + +class cl_ticker * +cl_uc::get_counter(char *name) +{ + int i; + + if (!name) + return(0); + for (i= 0; i < counters->count; i++) + { + class cl_ticker *t= (class cl_ticker *)(counters->at(i)); + if (t && + t->name && + strcmp(t->name, name) == 0) + return(t); + } + return(0); +} + +void +cl_uc::add_counter(class cl_ticker *ticker, int nr) +{ + while (counters->count <= nr) + counters->add(0); + counters->put_at(nr, ticker); +} + +void +cl_uc::add_counter(class cl_ticker *ticker, char */*name*/) +{ + int i; + + if (counters->count < 1) + counters->add(0); + for (i= 1; i < counters->count; i++) + { + class cl_ticker *t= (class cl_ticker *)(counters->at(i)); + if (!t) + { + counters->put_at(i, ticker); + return; + } + } + counters->add(ticker); +} + +void +cl_uc::del_counter(int nr) +{ + class cl_ticker *t; + + if (nr >= counters->count) + return; + if ((t= (class cl_ticker *)(counters->at(0))) != 0) + delete t; + counters->put_at(nr, 0); +} + +void +cl_uc::del_counter(char *name) +{ + int i; + + if (!name) + return; + for (i= 0; i < counters->count; i++) + { + class cl_ticker *t= (class cl_ticker *)(counters->at(i)); + if (t && + t->name && + strcmp(t->name, name) == 0) + { + delete t; + counters->put_at(i, 0); + return; + } + } +} + +/* + * Fetch without checking for breakpoint hit + */ + +t_mem +cl_uc::fetch(void) +{ + ulong code; + + code= read_mem(MEM_ROM, PC); + PC++; + if (PC >= get_mem_size(MEM_ROM)) + PC= 0; + return(code); +} + +/* + * Fetch but checking for breakpoint hit first + */ + +bool +cl_uc::fetch(ulong *code) +{ + class cl_brk *brk; + int idx; + + if (!code) + return(0); + if (sim->state & SIM_GO) + { + if ((brk= fbrk->get_bp(PC, &idx)) && + (brk->do_hit())) + { + if (brk->perm == brkDYNAMIC) + fbrk->del_bp(PC); + return(1); + } + } + *code= fetch(); + return(0); +} + +int +cl_uc::do_inst(int step) +{ + int res= resGO; + + if (step < 0) + step= 1; + while (step-- && + res == resGO) + { + pre_inst(); + res= exec_inst(); + post_inst(); + } + if (res != resGO) + sim->stop(res); + return(res); +} + +void +cl_uc::pre_inst(void) +{} + +int +cl_uc::exec_inst(void) +{ + return(resGO); +} + +void +cl_uc::post_inst(void) +{} + + +/* + * Time related functions + */ + +double +cl_uc::get_rtime(void) +{ + /* double d; + + d= (double)ticks/xtal; + return(d);*/ + return(ticks->get_rtime(xtal)); +} + +int +cl_uc::clock_per_cycle(void) +{ + return(1); +} + + +/* + * Stack tracking system + */ + +void +cl_uc::st_push(class cl_stack_op *op) +{ + st_ops->push(op); +} + +void +cl_uc::st_call(class cl_stack_op *op) +{ + st_ops->push(op); +} + +int +cl_uc::st_pop(class cl_stack_op *op) +{ + class cl_stack_op *sop= (class cl_stack_op *)(st_ops->pop()); + + if (!sop) + return(1); + return(0); +} + +int +cl_uc::st_ret(class cl_stack_op *op) +{ + class cl_stack_op *sop= (class cl_stack_op *)(st_ops->pop()); + + if (!sop) + return(1); + return(0); +} + + +/* + * Breakpoint handling + */ + +class cl_fetch_brk * +cl_uc::fbrk_at(long addr) +{ + int idx; + + return((class cl_fetch_brk *)(fbrk->get_bp(addr, &idx))); +} + +class cl_ev_brk * +cl_uc::ebrk_at(t_addr addr, char *id) +{ + int i; + class cl_ev_brk *eb; + + for (i= 0; i < ebrk->count; i++) + { + eb= (class cl_ev_brk *)(ebrk->at(i)); + if (eb->addr == addr && + !strcmp(eb->id, id)) + return(eb); + } + return(0); +} + +/*void +cl_uc::rm_fbrk(long addr) +{ + fbrk->del_bp(addr); +}*/ + +void +cl_uc::rm_ebrk(t_addr addr, char *id) +{ + int i; + class cl_ev_brk *eb; + + for (i= 0; i < ebrk->count; i++) + { + eb= (class cl_ev_brk *)(ebrk->at(i)); + if (eb->addr == addr && + !strcmp(eb->id, id)) + ebrk->free_at(i); + } +} + +void +cl_uc::put_breaks(void) +{} + +void +cl_uc::remove_breaks(void) +{} + + +/* End of uc.cc */ diff --git a/sim/ucsim/sim.src/uccl.h b/sim/ucsim/sim.src/uccl.h new file mode 100644 index 00000000..7cd40687 --- /dev/null +++ b/sim/ucsim/sim.src/uccl.h @@ -0,0 +1,191 @@ +/* + * Simulator of microcontrollers (uccl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef UCCL_HEADER +#define UCCL_HEADER + +// prj +#include "stypes.h" +#include "pobjcl.h" + +// sim +#include "hwcl.h" +#include "memcl.h" +#include "brkcl.h" + + +/* Counter to count clock ticks */ + +#define TICK_RUN 0x01 +#define TICK_INISR 0x02 +#define TICK_IDLE 0x03 + +class cl_ticker: public cl_base +{ +public: + unsigned long ticks; + int options; // see TICK_XXX above + int dir; + char *name; + + cl_ticker(int adir, int in_isr, char *aname); + ~cl_ticker(void); + + virtual int tick(int nr); + virtual double get_rtime(double xtal); + virtual void dump(int nr, double xtal, class cl_console *con); +}; + + +/* Abstract microcontroller */ + +class cl_uc: public cl_base +{ +public: + int type; // CPU family + int technology; // CMOS, HMOS + int state; // GO, IDLE, PD + class cl_list *options; + + t_addr PC; // Program Counter + class cl_ticker *ticks; // Nr of XTAL clocks + class cl_ticker *isr_ticks; // Time in ISRs + class cl_ticker *idle_ticks; // Time in idle mode + class cl_list *counters; // User definable timers (tickers) + double xtal; // Clock speed + + class brk_coll *fbrk; // Collection of FETCH break-points + class brk_coll *ebrk; // Collection of EVENT breakpoints + class cl_sim *sim; + class cl_list *mems; + class cl_list *hws; + + class cl_list *it_sources; // Sources of interrupts + class cl_list *it_levels; // Follow interrupt services + class cl_list *st_ops; // Track stack operations + + t_addr sp_max; + t_addr sp_avg; + +public: + cl_uc(class cl_sim *asim); + ~cl_uc(void); + virtual int init(void); + virtual char *id_string(void); + virtual void reset(void); + + // making objects + virtual class cl_mem *mk_mem(enum mem_class type); + virtual t_addr get_mem_size(enum mem_class type); + virtual int get_mem_width(enum mem_class type); + virtual void mk_hw_elements(void); + + // manipulating memories + virtual ulong read_mem(enum mem_class type, long addr); + virtual ulong get_mem(enum mem_class type, long addr); + virtual void write_mem(enum mem_class type, long addr, ulong val); + virtual void set_mem(enum mem_class type, long addr, ulong val); + virtual class cl_mem *mem(enum mem_class type); + virtual uchar *MEM(enum mem_class type); + + // file handling + virtual long read_hex_file(const char *name); + + // instructions, code analyzer + virtual void analyze(uint addr) {} + virtual bool inst_at(uint addr); + virtual void set_inst_at(uint addr); + virtual void del_inst_at(uint addr); + virtual bool there_is_inst(void); + + // manipulating hw elements + virtual void register_hw_read(enum mem_class, long addr, class cl_hw *hw); + virtual void register_hw_write(enum mem_class, long addr, class cl_hw *hw); + virtual class cl_hw *get_hw(enum hw_cath cath, int *idx); + virtual class cl_hw *get_hw(enum hw_cath cath, int hwid, int *idx); + + // "virtual" timers + virtual int tick(int cycles); + virtual class cl_ticker *get_counter(int nr); + virtual class cl_ticker *get_counter(char *name); + virtual void add_counter(class cl_ticker *ticker, int nr); + virtual void add_counter(class cl_ticker *ticker, char *name); + virtual void del_counter(int nr); + virtual void del_counter(char *name); + virtual double get_rtime(void); + virtual int clock_per_cycle(void); + + // execution + virtual t_mem fetch(void); + virtual bool fetch(ulong *code); + virtual int do_inst(int step); + virtual void pre_inst(void); + virtual int exec_inst(void); + virtual void post_inst(void); + + virtual int it_priority(uchar ie_mask) {return(0);} + + // stack tracking + virtual void st_push(class cl_stack_op *op); + virtual void st_call(class cl_stack_op *op); + virtual int st_pop(class cl_stack_op *op); + virtual int st_ret(class cl_stack_op *op); + + // breakpoints + virtual class cl_fetch_brk *fbrk_at(long addr); + virtual class cl_ev_brk *ebrk_at(t_addr addr, char *id); + //virtual void rm_fbrk(long addr); + virtual void rm_ebrk(t_addr addr, char *id); + virtual void put_breaks(void); + virtual void remove_breaks(void); + + // disassembling and symbol recognition + virtual char *disass(uint addr, char *sep); + virtual struct dis_entry *dis_tbl(void); + virtual struct name_entry *sfr_tbl(void); + virtual struct name_entry *bit_tbl(void); + virtual void print_disass(uint addr, class cl_console *con); + virtual void print_regs(class cl_console *con); + virtual int inst_length(uint code); + virtual bool get_name(uint addr, struct name_entry tab[], char *buf); + + /* Following fields and virtual methods defined in uc51 I don't have + energy to redesign them:-( */ +public: + uchar port_pins[3]; // Port pins +public: + virtual void proc_write(uchar *addr) {} + virtual void set_p_flag(void) {} + virtual uchar *get_bit(uchar bitaddr) { return(0); } + virtual void eram2xram(void) {} // Dirty hack for 51R + virtual void xram2eram(void) {} +}; + + +#endif + +/* End of uccl.h */ diff --git a/sim/ucsim/z80.src/(c).1 b/sim/ucsim/z80.src/(c).1 new file mode 100644 index 00000000..d673f9fd --- /dev/null +++ b/sim/ucsim/z80.src/(c).1 @@ -0,0 +1,25 @@ +/* + * Simulator of microcontrollers (@@F@@) + * + * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ diff --git a/sim/ucsim/z80.src/Makefile.in b/sim/ucsim/z80.src/Makefile.in new file mode 100644 index 00000000..c5ff1331 --- /dev/null +++ b/sim/ucsim/z80.src/Makefile.in @@ -0,0 +1,120 @@ +# +# uCsim z80.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = @CXX@ +CPP = @CPP@ +CXXCPP = @CXXCPP@ +RANLIB = @RANLIB@ +INSTALL = @INSTALL@ + +PRJDIR = .. + +DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +CPPFLAGS = @CPPFLAGS@ -I. -I$(PRJDIR) \ + -I$(PRJDIR)/cmd.src -I$(PRJDIR)/sim.src +CFLAGS = @CFLAGS@ -Wall +CXXFLAGS = @CXXFLAGS@ -Wall +M_OR_MM = @M_OR_MM@ + +LIBS = @LIBS@ -L$(PRJDIR) -lsim -lcmd -lutil + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +includedir = @includedir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +srcdir = @srcdir@ + +OBJECTS = sz80.o glob.o \ + inst.o \ + simz80.o z80.o + +Z80ASM = +#TEST_OBJ = test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \ +# test_arith.hex + + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs z80.src tests + +tests: $(TEST_OBJ) + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) -s sz80 $(bindir) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(bindir)/sz80 + + +# Performing self-test +# -------------------- +check: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(bindir) || $(INSTALL) -d $(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: *.cc *.h + $(CXXCPP) $(CPPFLAGS) $(M_OR_MM) *.cc >Makefile.dep + +include Makefile.dep +include clean.mk + +# My rules +# -------- +.SUFFIXES: .asm .hex + +z80.src: sz80 + +sz80: $(OBJECTS) $(PRJDIR)/*.a + $(CXX) $(CXXFLAGS) -o sz80 $(OBJECTS) $(LIBS) + +otherlibs: + cd $(PRJDIR)/cmd.src && $(MAKE) all + cd $(PRJDIR)/sim.src && $(MAKE) all + +.cc.o: + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@ + +.asm.hex: + $(Z80ASM) -l $< -o $@ -e $<.lst + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(PRJDIR)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" PRJDIR="$(PRJDIR)" freshconf;\ + fi + +# End of z80.src/Makefile.in diff --git a/sim/ucsim/z80.src/clean.mk b/sim/ucsim/z80.src/clean.mk new file mode 100644 index 00000000..b8362d00 --- /dev/null +++ b/sim/ucsim/z80.src/clean.mk @@ -0,0 +1,26 @@ +# Deleting all files created by building the program +# -------------------------------------------------- +clean: + rm -f *core *[%~] *.[oa] + rm -f .[a-z]*~ + rm -f sz80 + + +# Deleting all files created by configuring or building the program +# ----------------------------------------------------------------- +distclean: clean + rm -f config.cache config.log config.status + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean + +# End of z80.src/clean.mk diff --git a/sim/ucsim/z80.src/conf.mk b/sim/ucsim/z80.src/conf.mk new file mode 100644 index 00000000..23bc4551 --- /dev/null +++ b/sim/ucsim/z80.src/conf.mk @@ -0,0 +1,10 @@ +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(PRJDIR)/configure.in + cd $(PRJDIR) && $(SHELL) ./config.status + +# End of z80.src/conf.mk diff --git a/sim/ucsim/z80.src/glob.cc b/sim/ucsim/z80.src/glob.cc new file mode 100644 index 00000000..d90e5fc7 --- /dev/null +++ b/sim/ucsim/z80.src/glob.cc @@ -0,0 +1,155 @@ +/* + * Simulator of microcontrollers (glob.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include + +#include "stypes.h" + + +struct dis_entry disass_z80[]= { + { 0x0000, 0xffff, ' ', 1, "nop" }, + { 0x9488, 0xffff, ' ', 1, "clc" }, + { 0x94d8, 0xffff, ' ', 1, "clh" }, + { 0x94f8, 0xffff, ' ', 1, "cli" }, + { 0x94a8, 0xffff, ' ', 1, "cln" }, + { 0x94c8, 0xffff, ' ', 1, "cls" }, + { 0x94e8, 0xffff, ' ', 1, "clt" }, + { 0x94b8, 0xffff, ' ', 1, "clv" }, + { 0x9498, 0xffff, ' ', 1, "clz" }, + { 0x9408, 0xffff, ' ', 1, "sec" }, + { 0x9458, 0xffff, ' ', 1, "seh" }, + { 0x9478, 0xffff, ' ', 1, "sei" }, + { 0x9428, 0xffff, ' ', 1, "sen" }, + { 0x9448, 0xffff, ' ', 1, "ses" }, + { 0x9468, 0xffff, ' ', 1, "set" }, + { 0x9438, 0xffff, ' ', 1, "sev" }, + { 0x9418, 0xffff, ' ', 1, "sez" }, + { 0x1c00, 0xfc00, ' ', 1, "adc %d,%r" }, + { 0x0c00, 0xfc00, ' ', 1, "add %d,%r" }, + { 0x9600, 0xff00, ' ', 1, "adiw %2,%6" }, + { 0x2000, 0xfc00, ' ', 1, "and %d,%r" }, + { 0x7000, 0xf000, ' ', 1, "andi %D,%K" }, + { 0x9405, 0xfe0f, ' ', 1, "asr %d" }, + { 0x9488, 0xff8f, ' ', 1, "bclr %s" }, + { 0xf800, 0xfe08, ' ', 1, "bld %d,%b" }, + { 0xf400, 0xfc07, ' ', 1, "brcc %k" }, + { 0xf000, 0xfc07, ' ', 1, "brcs %k" }, + { 0xf001, 0xfc07, ' ', 1, "breq %k" }, + { 0xf404, 0xfc07, ' ', 1, "brge %k" }, + { 0xf405, 0xfc07, ' ', 1, "brhc %k" }, + { 0xf005, 0xfc07, ' ', 1, "brhs %k" }, + { 0xf407, 0xfc07, ' ', 1, "brid %k" }, + { 0xf007, 0xfc07, ' ', 1, "brie %k" }, + { 0xf000, 0xfc07, ' ', 1, "brlo %k" }, + { 0xf004, 0xfc07, ' ', 1, "brlt %k" }, + { 0xf002, 0xfc07, ' ', 1, "brmi %k" }, + { 0xf401, 0xfc07, ' ', 1, "brne %k" }, + { 0xf402, 0xfc07, ' ', 1, "brpl %k" }, + { 0xf400, 0xfc07, ' ', 1, "brsh %k" }, + { 0xf406, 0xfc07, ' ', 1, "brtc %k" }, + { 0xf006, 0xfc07, ' ', 1, "brts %k" }, + { 0xf403, 0xfc07, ' ', 1, "brvc %k" }, + { 0xf003, 0xfc07, ' ', 1, "brvs %k" }, + { 0xf400, 0xfc00, ' ', 1, "brbc %b,%k" }, + { 0xf000, 0xfc00, ' ', 1, "brbs %b,%k" }, + { 0x9408, 0xff8f, ' ', 1, "bset %s" }, + { 0xfa00, 0xfe00, ' ', 1, "bst %d,%b" }, + { 0x940e, 0xfe0e, ' ', 2, "call %A" }, + { 0x9800, 0xff00, ' ', 1, "cbi %P,%b" }, + { 0x9400, 0xfe0f, ' ', 1, "com %d" }, + { 0x1400, 0xfc00, ' ', 1, "cp %d,%r" }, + { 0x0400, 0xfc00, ' ', 1, "cpc %d,%r" }, + { 0x3000, 0xf000, ' ', 1, "cpi %D,%K" }, + { 0x1000, 0xfc00, ' ', 1, "cpse %d,%r" }, + { 0x940a, 0xfe0f, ' ', 1, "dec %d" }, + { 0x2400, 0xfc00, ' ', 1, "eor %d,%r" }, + { 0x9509, 0xff0f, ' ', 1, "icall" }, + { 0x9409, 0xff0f, ' ', 1, "ijmp" }, + { 0xb000, 0xf800, ' ', 1, "in %d,%p" }, + { 0x9403, 0xfe0f, ' ', 1, "inc %d" }, + { 0x940c, 0xfe0e, ' ', 2, "jmp %A" }, + { 0x900c, 0xfe0f, ' ', 1, "ld %d,X" }, + { 0x900d, 0xfe0f, ' ', 1, "ld %d,X+" }, + { 0x900e, 0xfe0f, ' ', 1, "ld %d,-X" }, + { 0x8008, 0xfe0f, ' ', 1, "ld %d,Y" }, + { 0x9009, 0xfe0f, ' ', 1, "ld %d,Y+" }, + { 0x900a, 0xfe0f, ' ', 1, "ld %d,-Y" }, + { 0x8008, 0xd208, ' ', 1, "ldd %d,Y+%q" }, + { 0x8000, 0xfe0f, ' ', 1, "ld %d,Z" }, + { 0x9001, 0xfe0f, ' ', 1, "ld %d,Z+" }, + { 0x9002, 0xfe0f, ' ', 1, "ld %d,-Z" }, + { 0x8000, 0xd208, ' ', 1, "ldd %d,Z+%q" }, + { 0xe000, 0xf000, ' ', 1, "ldi %D,%K" }, + { 0x9000, 0xfe0f, ' ', 2, "lds %d,%R" }, + { 0x95c8, 0xffff, ' ', 1, "lpm" }, + { 0x95d8, 0xffff, ' ', 1, "elpm" }, // in some devices equal to lpm + { 0x9406, 0xfe0f, ' ', 1, "lsr %d" }, + { 0x2c00, 0xfc00, ' ', 1, "mov %d,%r" }, + { 0x9c00, 0xfc00, ' ', 1, "mul %d,%r" }, + { 0x9401, 0xfe0f, ' ', 1, "neg %d" }, + { 0x2800, 0xfc00, ' ', 1, "or %d,%r" }, + { 0x6000, 0xf000, ' ', 1, "ori %d,%K" }, + { 0xb800, 0xf800, ' ', 1, "out %p,%d" }, + { 0x900f, 0xfe0f, ' ', 1, "pop %d" }, + { 0x920f, 0xfe0f, ' ', 1, "push %d" }, + { 0xd000, 0xf000, ' ', 1, "rcall %a" }, + { 0x9508, 0xff9f, ' ', 1, "ret" }, + { 0x9518, 0xff9f, ' ', 1, "reti" }, + { 0xc000, 0xf000, ' ', 1, "rjmp %a" }, + { 0x9407, 0xfe0f, ' ', 1, "ror %d" }, + { 0x0800, 0xfc00, ' ', 1, "sbc %d,%r" }, + { 0x4000, 0xf000, ' ', 1, "sbci %D,%K" }, + { 0x9a00, 0xff00, ' ', 1, "sbi %P,%b" }, + { 0x9900, 0xff00, ' ', 1, "sbic %P,%b" }, + { 0x9b00, 0xff00, ' ', 1, "sbis %P,%b" }, + { 0x9700, 0xff00, ' ', 1, "sbiw %2,%6" }, + { 0x6000, 0xf000, ' ', 1, "sbr %D,%K" }, + { 0xfc00, 0xfe00, ' ', 1, "sbrc %d,%b" }, + { 0xfe00, 0xfe00, ' ', 1, "sbrs %d,%b" }, + { 0xef0f, 0xff0f, ' ', 1, "ser %D" }, + { 0x9588, 0xffef, ' ', 1, "sleep" }, + { 0x920c, 0xfe0f, ' ', 1, "st X,%d" }, + { 0x920d, 0xfe0f, ' ', 1, "st X+,%d" }, + { 0x920e, 0xfe0f, ' ', 1, "st -X,%d" }, + { 0x8208, 0xfe0f, ' ', 1, "st Y,%d" }, + { 0x9209, 0xfe0f, ' ', 1, "st Y+,%d" }, + { 0x920a, 0xfe0f, ' ', 1, "st -Y,%d" }, + { 0x8208, 0xd208, ' ', 1, "std Y+%q,%d" }, + { 0x8200, 0xfe0f, ' ', 1, "st Z,%d" }, + { 0x9201, 0xfe0f, ' ', 1, "st Z+,%d" }, + { 0x9202, 0xfe0f, ' ', 1, "st -Z,%d" }, + { 0x8200, 0xd208, ' ', 1, "std Z+%q,%d" }, + { 0x9200, 0xfe0f, ' ', 2, "sts %R,%d" }, + { 0x1800, 0xfc00, ' ', 1, "sub %d,%r" }, + { 0x5000, 0xf000, ' ', 1, "subi %D,%K" }, + { 0x9402, 0xfe0f, ' ', 1, "swap %d" }, + { 0x95a8, 0xffef, ' ', 1, "wdr" }, + { 0, 0, 0, 0, NULL } +}; + + +/* End of z80.src/glob.cc */ diff --git a/sim/ucsim/z80.src/glob.h b/sim/ucsim/z80.src/glob.h new file mode 100644 index 00000000..99564021 --- /dev/null +++ b/sim/ucsim/z80.src/glob.h @@ -0,0 +1,39 @@ +/* + * Simulator of microcontrollers (glob.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef GLOB_HEADER +#define GLOB_HEADER + +#include "stypes.h" + + +extern struct dis_entry disass_z80[]; + + +#endif + +/* End of z80.src/glob.h */ diff --git a/sim/ucsim/z80.src/inst.cc b/sim/ucsim/z80.src/inst.cc new file mode 100644 index 00000000..fc1befe5 --- /dev/null +++ b/sim/ucsim/z80.src/inst.cc @@ -0,0 +1,49 @@ +/* + * Simulator of microcontrollers (inst.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "z80cl.h" +#include "regsz80.h" + + +/* + * No Instruction + * NOP + * 0000 0000 0000 0000 + *---------------------------------------------------------------------------- + */ + +int +cl_z80::nop(t_mem code) +{ + return(resGO); +} + + +/* End of z80.src/inst.cc */ diff --git a/sim/ucsim/z80.src/instcl.h b/sim/ucsim/z80.src/instcl.h new file mode 100644 index 00000000..f000e94c --- /dev/null +++ b/sim/ucsim/z80.src/instcl.h @@ -0,0 +1,5 @@ +/* avr.src/instcl.h */ + + virtual int nop(t_mem code); + +/* End of avr.src/instcl.h */ diff --git a/sim/ucsim/z80.src/regsz80.h b/sim/ucsim/z80.src/regsz80.h new file mode 100644 index 00000000..b176a016 --- /dev/null +++ b/sim/ucsim/z80.src/regsz80.h @@ -0,0 +1,72 @@ +/* + * Simulator of microcontrollers (regsz80.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef REGSAVR_HEADER +#define REGSAVR_HEADER + +#include "ddconfig.h" + + +struct t_regpair +{ +#ifdef WORDS_BIGENDIAN + TYPE_UBYTE h; + TYPE_UBYTE l; +#else + TYPE_UBYTE l; + TYPE_UBYTE h; +#endif +}; + +#define DEF_REGPAIR(BIGNAME,smallname) \ + union { \ + TYPE_UWORD BIGNAME; \ + struct t_regpair smallname; \ + } + +struct t_regs +{ + TYPE_UBYTE A; + TYPE_UBYTE F; + DEF_REGPAIR(BC, bc); + DEF_REGPAIR(DE, de); + DEF_REGPAIR(HL, hl); + TYPE_UWORD IX; + TYPE_UWORD IY; + TYPE_UWORD SP; +}; + +#define BIT_C 0x01 +#define BIT_P 0x04 +#define BIT_A 0x10 +#define BIT_Z 0x40 +#define BIT_S 0x80 + + +#endif + +/* End of z80.src/regsz80.h */ diff --git a/sim/ucsim/z80.src/simz80.cc b/sim/ucsim/z80.src/simz80.cc new file mode 100644 index 00000000..6a66e2bd --- /dev/null +++ b/sim/ucsim/z80.src/simz80.cc @@ -0,0 +1,44 @@ +/* + * Simulator of microcontrollers (simz80.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + + +#include "simz80cl.h" +#include "z80cl.h" + + +cl_simz80::cl_simz80(char *more_args, int iargc, char *iargv[]): + cl_sim(more_args, iargc, iargv) +{} + +class cl_uc * +cl_simz80::mk_controller(void) +{ + return(new cl_z80(this)); +} + + +/* End of z80.src/simz80.cc */ diff --git a/sim/ucsim/z80.src/simz80cl.h b/sim/ucsim/z80.src/simz80cl.h new file mode 100644 index 00000000..022b87b8 --- /dev/null +++ b/sim/ucsim/z80.src/simz80cl.h @@ -0,0 +1,45 @@ +/* + * Simulator of microcontrollers (simz80cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SIMZ80CL_HEADER +#define SIMZ80CL_HEADER + +#include "simcl.h" + + +class cl_simz80: public cl_sim +{ +public: + cl_simz80(char *more_args, int iargc, char *iargv[]); + + virtual class cl_uc *mk_controller(void); +}; + + +#endif + +/* End of z80.src/simz80cl.h */ diff --git a/sim/ucsim/z80.src/sz80.cc b/sim/ucsim/z80.src/sz80.cc new file mode 100644 index 00000000..7c857009 --- /dev/null +++ b/sim/ucsim/z80.src/sz80.cc @@ -0,0 +1,46 @@ +/* + * Simulator of microcontrollers (sz80.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include + +#include "globals.h" + +#include "simz80cl.h" + + +int +main(int argc, char *argv[]) +{ + simulator= new cl_simz80(0, argc, argv); + simulator->init(); + simulator->main(); + delete simulator; + return(0); +} + + +/* End of z80.src/sz80.cc */ diff --git a/sim/ucsim/z80.src/z80.cc b/sim/ucsim/z80.src/z80.cc new file mode 100644 index 00000000..47b42d5a --- /dev/null +++ b/sim/ucsim/z80.src/z80.cc @@ -0,0 +1,356 @@ +/* + * Simulator of microcontrollers (z80.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include "i_string.h" + +// prj +#include "pobjcl.h" + +// sim +#include "simcl.h" + +// local +#include "z80cl.h" +#include "glob.h" +#include "regsz80.h" + + +/* + * Base type of Z80 controllers + */ + +cl_z80::cl_z80(class cl_sim *asim): + cl_uc(asim) +{ + type= CPU_Z80; +} + +int +cl_z80::init(void) +{ + cl_uc::init(); /* Memories now exist */ + ram= mem(MEM_XRAM); + rom= mem(MEM_ROM); + return(0); +} + +char * +cl_z80::id_string(void) +{ + return("unspecified Z80"); +} + + +/* + * Making elements of the controller + */ + +t_addr +cl_z80::get_mem_size(enum mem_class type) +{ + switch(type) + { + case MEM_ROM: return(0x10000); + case MEM_XRAM: return(0x10000); + default: return(0); + } + return(cl_uc::get_mem_size(type)); +} + +/*int +cl_z80::get_mem_width(enum mem_class type) +{ + if (type == MEM_ROM) + return(16); + return(cl_uc::get_mem_width(type)); +}*/ + +void +cl_z80::mk_hw_elements(void) +{ + //class cl_base *o; + /* t_uc::mk_hw() does nothing */ +} + + +/* + * Help command interpreter + */ + +struct dis_entry * +cl_z80::dis_tbl(void) +{ + return(disass_z80); +} + +/*struct name_entry * +cl_z80::sfr_tbl(void) +{ + return(0); +}*/ + +/*struct name_entry * +cl_z80::bit_tbl(void) +{ + //FIXME + return(0); +}*/ + +char * +cl_z80::disass(uint addr, char *sep) +{ + char work[256], temp[20]; + char *buf, *p, *b, *t; + uint code, data= 0; + int i; + + p= work; + + code= get_mem(MEM_ROM, addr); + i= 0; + while ((code & dis_tbl()[i].mask) != dis_tbl()[i].code && + dis_tbl()[i].mnemonic) + i++; + if (dis_tbl()[i].mnemonic == NULL) + { + buf= (char*)malloc(30); + strcpy(buf, "UNKNOWN/INVALID"); + return(buf); + } + b= dis_tbl()[i].mnemonic; + + while (*b) + { + if (*b == '%') + { + b++; + switch (*(b++)) + { + case 'd': // Rd .... ...d dddd .... 0<=d<=31 + if (!get_name(data= (code&0x01f0)>>4, sfr_tbl(), temp)) + sprintf(temp, "r%d", data); + break; + case 'D': // Rd .... .... dddd .... 16<=d<=31 + if (!get_name(data= 16+((code&0xf0)>>4), sfr_tbl(), temp)) + sprintf(temp, "r%d", data); + break; + case 'K': // K .... KKKK .... KKKK 0<=K<=255 + sprintf(temp, "%d", ((code&0xf00)>>4)|(code&0xf)); + break; + case 'r': // Rr .... ..r. .... rrrr 0<=r<=31 + if (!get_name(data= ((code&0x0200)>>5)|(code&0x000f), + sfr_tbl(), temp)) + sprintf(temp, "r%d", data); + break; + case '2': // Rdl .... .... ..dd .... dl= {24,26,28,30} + if (!get_name(data= 24+(2*((code&0x0030)>>4)), + sfr_tbl(), temp)) + sprintf(temp, "r%d", data); + break; + case '6': // K .... .... KK.. KKKK 0<=K<=63 + sprintf(temp, "%d", ((code&0xc0)>>2)|(code&0xf)); + break; + case 's': // s .... .... .sss .... 0<=s<=7 + sprintf(temp, "%d", (code&0x70)>>4); + break; + case 'b': // b .... .... .... .bbb 0<=b<=7 + sprintf(temp, "%d", code&0x7); + break; + case 'k': // k .... ..kk kkkk k... -64<=k<=+63 + { + int k= (code&0x3f8)>>3; + if (code&0x200) + k|= -128; + sprintf(temp, "0x%06x", k+1+(signed int)addr); + break; + } + case 'A': // k .... ...k kkkk ...k 0<=k<=64K + // kkkk kkkk kkkk kkkk 0<=k<=4M + sprintf(temp, "0x%06x", + (((code&0x1f0)>>3)|(code&1))*0x10000+ + (uint)get_mem(MEM_ROM, addr+1)); + break; + case 'P': // P .... .... pppp p... 0<=P<=31 + data= (code&0xf8)>>3; + if (!get_name(data+0x20, sfr_tbl(), temp)) + sprintf(temp, "%d", data); + break; + case 'p': // P .... .PP. .... PPPP 0<=P<=63 + data= ((code&0x600)>>5)|(code&0xf); + if (!get_name(data+0x20, sfr_tbl(), temp)) + sprintf(temp, "%d", data); + break; + case 'q': // q ..q. qq.. .... .qqq 0<=q<=63 + sprintf(temp, "%d", + ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&7)); + break; + case 'R': // k SRAM address on second word 0<=k<=65535 + sprintf(temp, "0x%06x", (uint)get_mem(MEM_ROM, addr+1)); + break; + case 'a': // k .... kkkk kkkk kkkk -2k<=k<=2k + { + int k= code&0xfff; + if (code&0x800) + k|= -4096; + sprintf(temp, "0x%06lx", + (k+1+(signed int)addr) % rom->size); + break; + } + default: + strcpy(temp, "?"); + break; + } + t= temp; + while (*t) + *(p++)= *(t++); + } + else + *(p++)= *(b++); + } + *p= '\0'; + + p= strchr(work, ' '); + if (!p) + { + buf= strdup(work); + return(buf); + } + if (sep == NULL) + buf= (char *)malloc(6+strlen(p)+1); + else + buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1); + for (p= work, b= buf; *p != ' '; p++, b++) + *b= *p; + p++; + *b= '\0'; + if (sep == NULL) + { + while (strlen(buf) < 6) + strcat(buf, " "); + } + else + strcat(buf, sep); + strcat(buf, p); + return(buf); +} + +void +cl_z80::print_disass(uint addr, class cl_console *con) +{ + char *dis; + class cl_brk *b; + int i; + + b = fbrk_at(addr); + dis= disass(addr, NULL); + if (b) + con->printf("%c", (b->perm == brkFIX)?'F':'D'); + else + con->printf(" "); + con->printf("%c %06x %04x", + inst_at(addr)?' ':'*', + addr, get_mem(MEM_ROM, addr)); + for (i= 1; i < inst_length(get_mem(MEM_ROM, addr)); i++) + con->printf(" %04x", get_mem(MEM_ROM, addr+i)); + while (i < 2) + { + con->printf(" "); + i++; + } + con->printf(" %s\n", dis); + free(dis); +} + +void +cl_z80::print_regs(class cl_console *con) +{ + con->printf("SZ-A--P-C Flags= 0x%02x %3d %c ", + regs.F, regs.F, isprint(regs.F)?regs.F:'.'); + con->printf("A= 0x%02x %3d %c\n", + regs.A, regs.A, isprint(regs.A)?regs.A:'.'); + con->printf("%c%c-%c--%c-%c\n", + (regs.F&BIT_S)?'1':'0', + (regs.F&BIT_Z)?'1':'0', + (regs.F&BIT_A)?'1':'0', + (regs.F&BIT_P)?'1':'0', + (regs.F&BIT_C)?'1':'0'); + con->printf("BC= 0x%04x [BC]= %02x %3d %c ", + regs.BC, ram->get(regs.BC), ram->get(regs.BC), + isprint(ram->get(regs.BC))?ram->get(regs.BC):'.'); + con->printf("DE= 0x%04x [DE]= %02x %3d %c ", + regs.DE, ram->get(regs.DE), ram->get(regs.DE), + isprint(ram->get(regs.DE))?ram->get(regs.DE):'.'); + con->printf("HL= 0x%04x [HL]= %02x %3d %c\n", + regs.HL, ram->get(regs.HL), ram->get(regs.HL), + isprint(ram->get(regs.HL))?ram->get(regs.HL):'.'); + con->printf("IX= 0x%04x [IX]= %02x %3d %c ", + regs.IX, ram->get(regs.IX), ram->get(regs.IX), + isprint(ram->get(regs.IX))?ram->get(regs.IX):'.'); + con->printf("IY= 0x%04x [IY]= %02x %3d %c ", + regs.IY, ram->get(regs.IY), ram->get(regs.IY), + isprint(ram->get(regs.IY))?ram->get(regs.IY):'.'); + con->printf("SP= 0x%04x [SP]= %02x %3d %c\n", + regs.SP, ram->get(regs.SP), ram->get(regs.SP), + isprint(ram->get(regs.SP))?ram->get(regs.SP):'.'); + + print_disass(PC, con); +} + + +/* + * Execution + */ + +int +cl_z80::exec_inst(void) +{ + t_mem code; + + if (fetch(&code)) + return(resBREAKPOINT); + tick(1); + switch (code) + { + case 0x00: + return(nop(code)); + } + if (PC) + PC--; + else + PC= get_mem_size(MEM_ROM)-1; + //tick(-clock_per_cycle()); + sim->stop(resINV_INST); + return(resINV_INST); +} + + +/* End of z80.src/z80.cc */ diff --git a/sim/ucsim/z80.src/z80cl.h b/sim/ucsim/z80.src/z80cl.h new file mode 100644 index 00000000..a9ef160e --- /dev/null +++ b/sim/ucsim/z80.src/z80cl.h @@ -0,0 +1,69 @@ +/* + * Simulator of microcontrollers (z80cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef Z80CL_HEADER +#define Z80CL_HEADER + +#include "uccl.h" + +#include "regsz80.h" + + +/* + * Base type of Z80 microcontrollers + */ + +class cl_z80: public cl_uc +{ +public: + cl_mem *ram; + cl_mem *rom; + struct t_regs regs; +public: + cl_z80(class cl_sim *asim); + virtual int init(void); + virtual char *id_string(void); + + virtual t_addr get_mem_size(enum mem_class type); + //virtual int get_mem_width(enum mem_class type); + virtual void mk_hw_elements(void); + + virtual struct dis_entry *dis_tbl(void); + //virtual struct name_entry *sfr_tbl(void); + //virtual struct name_entry *bit_tbl(void); + virtual char *disass(uint addr, char *sep); + virtual void print_disass(uint addr, class cl_console *con); + virtual void print_regs(class cl_console *con); + + virtual int exec_inst(void); +#include "instcl.h" +}; + + +#endif + +/* End of z80.src/z80cl.h */ -- 2.30.2