From 07e07068d9af14d29187c984be0c810fda9b9f7a Mon Sep 17 00:00:00 2001 From: Bdale Garbee Date: Fri, 22 Aug 2025 17:22:49 -0600 Subject: [PATCH] merge two docs about EasyEda footprint import --- docs/EasyEDA_footprint_import | 26 +++++++++++++++++++++++++- docs/pcb-rnd-easyeda-import | 22 ---------------------- 2 files changed, 25 insertions(+), 23 deletions(-) delete mode 100644 docs/pcb-rnd-easyeda-import diff --git a/docs/EasyEDA_footprint_import b/docs/EasyEDA_footprint_import index 615e1ff..e223802 100644 --- a/docs/EasyEDA_footprint_import +++ b/docs/EasyEDA_footprint_import @@ -22,5 +22,29 @@ how EasyEDA handles clearance differently than Ringdove. Pay particular attention to unplated holes, where using pcb-rnd's 'hshadow' in the padstack allows forcing clearance around the hole to prevent a fab -from mistakenly assuming you really meant a plated hole. +from mistakenly assuming you really meant a plated hole. Tibor says: + + + the problem is this: + in the industrly, almost everything else than geda/pcb and pcb-rnd has a clearance model that's based on nets, not drawing objects + EasyEDA included + so you typically define that you want 15 mil clearance between Vcc and GND, 10 mil between signals and GND and there's usually a grand fallback default value + but these are all net based, so neither polygons nor padstacks/lines/etc store any clearance value + in such a data model, a footprint obviosuly won't have copper clearance values either + now geda/pcb couldn't handle this in any way, but in pcb-rnd we have a half-way solution + for some years already, you can specify polygon-side clearance + it's still object based, so not the network based approach, but you can more easily emulate the network based approach with it + this is how it works: + you set the padstack's clearance to some very small number, and you set the poygon-enforced clearance to some bigger number + the rule is that in any object-polygon relation the bigger clearance number wins + when pcb-rnd loads an EasyEDA board, we do that, figuring which object ended up in which net and set object clerances from their net based clearance rules + and that's typically done through polygons + that's why padstacks get a very small clearance value: the file format doesn't specify any clearance, and because the footpritn is designed for a net based clearance approach, the closest thing we can do is choosing a small value + btw, you don't need to edit the lht to tune these, we have GUI for this + in fact multiple GUI options, with propedit being able to mass-edit objects + so all in all, what you see is normal and is a side effect of the totally different way we model the world (which is inherited from geda/pcb); in the same time I think EasyEDA pro is pretty much a reimplementation of altium (which is just a fancy name for protel), which has a more centralized way of specifying board parameters + IIRC kicad went for net based clearances too + it's also very common to regard padstacks as parametric objects, so you specify only the shape of the copper pad in your footprint and mask aperture is computed from that using some board-global setting + I can't remember whether easyeda had this or not + if you want tips on how to quick-edit the clearance of those easyeda footprints easily from gui or even CLI actions, let me know, I can help with that diff --git a/docs/pcb-rnd-easyeda-import b/docs/pcb-rnd-easyeda-import deleted file mode 100644 index bc0b47b..0000000 --- a/docs/pcb-rnd-easyeda-import +++ /dev/null @@ -1,22 +0,0 @@ - the problem is this: - in the industrly, almost everything else than geda/pcb and pcb-rnd has a clearance model that's based on nets, not drawing objects - EasyEDA included - so you typically define that you want 15 mil clearance between Vcc and GND, 10 mil between signals and GND and there's usually a grand fallback default value - but these are all net based, so neither polygons nor padstacks/lines/etc store any clearance value - in such a data model, a footprint obviosuly won't have copper clearance values either - now geda/pcb couldn't handle this in any way, but in pcb-rnd we have a half-way solution - for some years already, you can specify polygon-side clearance - it's still object based, so not the network based approach, but you can more easily emulate the network based approach with it - this is how it works: - you set the padstack's clearance to some very small number, and you set the poygon-enforced clearance to some bigger number - the rule is that in any object-polygon relation the bigger clearance number wins - when pcb-rnd loads an EasyEDA board, we do that, figuring which object ended up in which net and set object clerances from their net based clearance rules - and that's typically done through polygons - that's why padstacks get a very small clearance value: the file format doesn't specify any clearance, and because the footpritn is designed for a net based clearance approach, the closest thing we can do is choosing a small value - btw, you don't need to edit the lht to tune these, we have GUI for this - in fact multiple GUI options, with propedit being able to mass-edit objects - so all in all, what you see is normal and is a side effect of the totally different way we model the world (which is inherited from geda/pcb); in the same time I think EasyEDA pro is pretty much a reimplementation of altium (which is just a fancy name for protel), which has a more centralized way of specifying board parameters - IIRC kicad went for net based clearances too - it's also very common to regard padstacks as parametric objects, so you specify only the shape of the copper pad in your footprint and mask aperture is computed from that using some board-global setting - I can't remember whether easyeda had this or not - if you want tips on how to quick-edit the clearance of those easyeda footprints easily from gui or even CLI actions, let me know, I can help with that -- 2.47.2