From 07cbddd43b4358d9f193bdccc860d7563e2aab93 Mon Sep 17 00:00:00 2001 From: epetrich Date: Sun, 29 Feb 2004 02:13:04 +0000 Subject: [PATCH] * src/SDCCpeeph.h, * src/SDCCpeeph.c (pcDistance), * src/port.h, * src/mcs51/ralloc.h, * src/mcs51/ralloc.c (mcs51_regWithIdx), * src/mcs51/main.h, * src/mcs51/main.c (instructionSize, asmLineNode, updateOpRW, mcs51opcodeCompare, asmLineNodeFromLineNode, getInstructionSize, mcs51operandCompare, getRegsRead, getRegsWritten): made instruction size calculation port specific, started basis for some register optimizations * src/mcs51/gen.c (genFunction, genEndFunction): added case to handle missing push/pop of r0/r1. Optimized push/pops * src/mcs51/ralloc.c (packregisters): fixed bug #727095 * device/lib/_modsint.c (_modsint), * device/lib/_modslong.c (_modslong): fixed sign of result in non-asm and stack version so regression tests pass git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@3236 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- ChangeLog | 20 +++ device/lib/_modsint.c | 4 +- device/lib/_modslong.c | 4 +- src/SDCCpeeph.c | 132 +------------- src/SDCCpeeph.h | 4 + src/mcs51/gen.c | 119 ++++++++++++- src/mcs51/main.c | 388 ++++++++++++++++++++++++++++++++++++++++- src/mcs51/main.h | 8 + src/mcs51/ralloc.c | 16 +- src/mcs51/ralloc.h | 4 +- src/port.h | 4 + 11 files changed, 561 insertions(+), 142 deletions(-) diff --git a/ChangeLog b/ChangeLog index aafd0fa0..d3bc5463 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,23 @@ +2004-02-28 Erik Petrich + + * src/SDCCpeeph.h, + * src/SDCCpeeph.c (pcDistance), + * src/port.h, + * src/mcs51/ralloc.h, + * src/mcs51/ralloc.c (mcs51_regWithIdx), + * src/mcs51/main.h, + * src/mcs51/main.c (instructionSize, asmLineNode, updateOpRW, + mcs51opcodeCompare, asmLineNodeFromLineNode, getInstructionSize, + mcs51operandCompare, getRegsRead, getRegsWritten): made instruction + size calculation port specific, started basis for some register + optimizations + * src/mcs51/gen.c (genFunction, genEndFunction): added case to handle + missing push/pop of r0/r1. Optimized push/pops + * src/mcs51/ralloc.c (packregisters): fixed bug #727095 + * device/lib/_modsint.c (_modsint), + * device/lib/_modslong.c (_modslong): fixed sign of result in non-asm + and stack version so regression tests pass + 2004-02-26 Bernhard Held * src/Makefile.in (dep): include SLIBOBJS in dependency check diff --git a/device/lib/_modsint.c b/device/lib/_modsint.c index a46268a3..6aa6bdf1 100644 --- a/device/lib/_modsint.c +++ b/device/lib/_modsint.c @@ -159,8 +159,6 @@ _modsint_dummy (void) _naked jnb acc.7,b_not_negative - cpl F0 - dec r0 clr a @@ -205,7 +203,7 @@ int _modsint (int a, int b) r = _moduint((a < 0 ? -a : a), (b < 0 ? -b : b)); - if ( (a < 0) ^ (b < 0)) + if (a < 0) return -r; else return r; diff --git a/device/lib/_modslong.c b/device/lib/_modslong.c index 22140ee1..975168ed 100644 --- a/device/lib/_modslong.c +++ b/device/lib/_modslong.c @@ -210,8 +210,6 @@ _modslong_dummy (void) _naked jnb acc.7,b_not_negative - cpl F0 - clr a ; b = -b; clr c subb a,b0 @@ -261,7 +259,7 @@ _modslong (long a, long b) r = _modulong((a < 0 ? -a : a), (b < 0 ? -b : b)); - if ( (a < 0) ^ (b < 0)) + if (a < 0) return -r; else return r; diff --git a/src/SDCCpeeph.c b/src/SDCCpeeph.c index 2c493e25..ed9e4bdf 100644 --- a/src/SDCCpeeph.c +++ b/src/SDCCpeeph.c @@ -64,134 +64,6 @@ void pic16_peepRules2pCode(peepRule *); /*-----------------------------------------------------------------*/ /* pcDistance - afinds a label back ward or forward */ /*-----------------------------------------------------------------*/ -int -mcs51_instruction_size(const char *inst) -{ - char *op, op1[256], op2[256]; - int opsize; - const char *p; - - while (*inst && isspace(*inst)) inst++; - - #define ISINST(s) (strncmp(inst, (s), sizeof(s)-1) == 0) - - /* Based on the current (2003-08-22) code generation for the - small library, the top instruction probability is: - - 57% mov/movx/movc - 6% push - 6% pop - 4% inc - 4% lcall - 4% add - 3% clr - 2% subb - */ - /* mov, push, & pop are the 69% of the cases. Check them first! */ - if (ISINST("mov")) - { - if (*(inst+3)=='x') return 1; /* movx */ - if (*(inst+3)=='c') return 1; /* movc */ - goto checkoperands; /* mov */ - } - if (ISINST("push")) return 2; - if (ISINST("pop")) return 2; - - if (ISINST("lcall")) return 3; - if (ISINST("ret")) return 1; - if (ISINST("ljmp")) return 3; - if (ISINST("sjmp")) return 2; - if (ISINST("rlc")) return 1; - if (ISINST("rrc")) return 1; - if (ISINST("rl")) return 1; - if (ISINST("rr")) return 1; - if (ISINST("swap")) return 1; - if (ISINST("jc")) return 2; - if (ISINST("jnc")) return 2; - if (ISINST("jb")) return 3; - if (ISINST("jnb")) return 3; - if (ISINST("jbc")) return 3; - if (ISINST("jmp")) return 1; // always jmp @a+dptr - if (ISINST("jz")) return 2; - if (ISINST("jnz")) return 2; - if (ISINST("cjne")) return 3; - if (ISINST("mul")) return 1; - if (ISINST("div")) return 1; - if (ISINST("da")) return 1; - if (ISINST("xchd")) return 1; - if (ISINST("reti")) return 1; - if (ISINST("nop")) return 1; - if (ISINST("acall")) return 1; - if (ISINST("ajmp")) return 2; - -checkoperands: - p = inst; - while (*p && isalnum(*p)) p++; - for (op = op1, opsize=0; *p && *p != ',' && opsize < sizeof(op1); p++) { - if (!isspace(*p)) *op++ = *p, opsize++; - } - *op = '\0'; - if (*p == ',') p++; - for (op = op2, opsize=0; *p && *p != ',' && opsize < sizeof(op2); p++) { - if (!isspace(*p)) *op++ = *p, opsize++; - } - *op = '\0'; - - #define IS_A(s) (*(s) == 'a' && *(s+1) == '\0') - #define IS_C(s) (*(s) == 'c' && *(s+1) == '\0') - #define IS_Rn(s) (*(s) == 'r' && *(s+1) >= '0' && *(s+1) <= '7') - #define IS_atRi(s) (*(s) == '@' && *(s+1) == 'r') - - if (ISINST("mov")) { - if (IS_C(op1) || IS_C(op2)) return 2; - if (IS_A(op1)) { - if (IS_Rn(op2) || IS_atRi(op2)) return 1; - return 2; - } - if (IS_Rn(op1) || IS_atRi(op1)) { - if (IS_A(op2)) return 1; - return 2; - } - if (strcmp(op1, "dptr") == 0) return 3; - if (IS_A(op2) || IS_Rn(op2) || IS_atRi(op2)) return 2; - return 3; - } - if (ISINST("add") || ISINST("addc") || ISINST("subb") || ISINST("xch")) { - if (IS_Rn(op2) || IS_atRi(op2)) return 1; - return 2; - } - if (ISINST("inc") || ISINST("dec")) { - if (IS_A(op1) || IS_Rn(op1) || IS_atRi(op1)) return 1; - if (strcmp(op1, "dptr") == 0) return 1; - return 2; - } - if (ISINST("anl") || ISINST("orl") || ISINST("xrl")) { - if (IS_C(op1)) return 2; - if (IS_A(op1)) { - if (IS_Rn(op2) || IS_atRi(op2)) return 1; - return 2; - } else { - if (IS_A(op2)) return 2; - return 3; - } - } - if (ISINST("clr") || ISINST("setb") || ISINST("cpl")) { - if (IS_A(op1) || IS_C(op1)) return 1; - return 2; - } - if (ISINST("djnz")) { - if (IS_Rn(op1)) return 2; - return 3; - } - - if (*inst == 'a' && *(inst+1) == 'r' && *(inst+2) >= '0' && *(inst+2) <= '7' && op1[0] == '=') { - /* ignore ar0 = 0x00 type definitions */ - return 0; - } - - fprintf(stderr, "Warning, peephole unrecognized instruction: %s\n", inst); - return 3; -} int pcDistance (lineNode * cpos, char *lbl, bool back) @@ -208,8 +80,8 @@ pcDistance (lineNode * cpos, char *lbl, bool back) *pl->line != ';' && pl->line[strlen (pl->line) - 1] != ':' && !pl->isDebug) { - if (TARGET_IS_MCS51) { - dist += mcs51_instruction_size(pl->line); + if (port->peep.getSize) { + dist += port->peep.getSize(pl); } else { dist += 3; } diff --git a/src/SDCCpeeph.h b/src/SDCCpeeph.h index 24425238..8ada2228 100644 --- a/src/SDCCpeeph.h +++ b/src/SDCCpeeph.h @@ -28,6 +28,9 @@ #define MAX_PATTERN_LEN 128 +struct asmLineNode; /* defined in each port */ +struct lineNode; + typedef struct lineNode { char *line; @@ -35,6 +38,7 @@ typedef struct lineNode unsigned int isInline:1; unsigned int isComment:1; unsigned int isDebug:1; + struct asmLineNode *aln; struct lineNode *prev; struct lineNode *next; } diff --git a/src/mcs51/gen.c b/src/mcs51/gen.c index c9f3132d..e6a90ffc 100644 --- a/src/mcs51/gen.c +++ b/src/mcs51/gen.c @@ -2440,6 +2440,11 @@ genFunction (iCode * ic) emitcode ("push", "%s", mcs51_regWithIdx (i)->dname); } } + else if (mcs51_ptrRegReq) + { + emitcode ("push", "%s", mcs51_regWithIdx (R0_IDX)->dname); + emitcode ("push", "%s", mcs51_regWithIdx (R1_IDX)->dname); + } } else @@ -2573,6 +2578,11 @@ genFunction (iCode * ic) } } } + else if (mcs51_ptrRegReq) + { + emitcode ("push", "%s", mcs51_regWithIdx (R0_IDX)->dname); + emitcode ("push", "%s", mcs51_regWithIdx (R1_IDX)->dname); + } } } @@ -2678,7 +2688,12 @@ static void genEndFunction (iCode * ic) { symbol *sym = OP_SYMBOL (IC_LEFT (ic)); - + lineNode *lnp = lineCurr; + bitVect *regsUsed; + bitVect *regsUsedPrologue; + bitVect *regsUnneeded; + int idx; + _G.currentFunc = NULL; if (IFFUNC_ISNAKED(sym->type)) { @@ -2763,6 +2778,11 @@ genEndFunction (iCode * ic) emitcode ("pop", "%s", mcs51_regWithIdx (i)->dname); } } + else if (mcs51_ptrRegReq) + { + emitcode ("pop", "%s", mcs51_regWithIdx (R1_IDX)->dname); + emitcode ("pop", "%s", mcs51_regWithIdx (R0_IDX)->dname); + } } else @@ -2848,6 +2868,11 @@ genEndFunction (iCode * ic) emitcode ("pop", "%s", mcs51_regWithIdx (i)->dname); } } + else if (mcs51_ptrRegReq) + { + emitcode ("pop", "%s", mcs51_regWithIdx (R1_IDX)->dname); + emitcode ("pop", "%s", mcs51_regWithIdx (R0_IDX)->dname); + } } @@ -2868,6 +2893,90 @@ genEndFunction (iCode * ic) emitcode ("ret", ""); } + if (!port->peep.getRegsRead || !port->peep.getRegsWritten) + return; + + /* If this was an interrupt handler using bank 0 that called another */ + /* function, then all registers must be saved; nothing to optimized. */ + if (IFFUNC_ISISR (sym->type) && IFFUNC_HASFCALL(sym->type) + && !FUNC_REGBANK(sym->type)) + return; + + /* Compute the registers actually used */ + regsUsed = newBitVect (mcs51_nRegs); + regsUsedPrologue = newBitVect (mcs51_nRegs); + while (lnp) + { + if (lnp->ic && lnp->ic->op == FUNCTION) + regsUsedPrologue = bitVectUnion (regsUsedPrologue, port->peep.getRegsWritten(lnp)); + else + regsUsed = bitVectUnion (regsUsed, port->peep.getRegsWritten(lnp)); + + if (lnp->ic && lnp->ic->op == FUNCTION && lnp->prev + && lnp->prev->ic && lnp->prev->ic->op != FUNCTION) + break; + if (!lnp->prev) + break; + lnp = lnp->prev; + } + + if (bitVectBitValue (regsUsedPrologue, CND_IDX) + && !bitVectBitValue (regsUsed, CND_IDX)) + { + regsUsed = bitVectUnion (regsUsed, regsUsedPrologue); + if (IFFUNC_ISISR (sym->type) && !FUNC_REGBANK(sym->type) + && !sym->stack) + bitVectUnSetBit (regsUsed, CND_IDX); + } + else + regsUsed = bitVectUnion (regsUsed, regsUsedPrologue); + + /* If this was an interrupt handler that called another function */ + /* function, then assume A, B, DPH, & DPL may be modified by it. */ + if (IFFUNC_ISISR (sym->type) && IFFUNC_HASFCALL(sym->type)) + { + regsUsed = bitVectSetBit (regsUsed, DPL_IDX); + regsUsed = bitVectSetBit (regsUsed, DPH_IDX); + regsUsed = bitVectSetBit (regsUsed, B_IDX); + regsUsed = bitVectSetBit (regsUsed, A_IDX); + regsUsed = bitVectSetBit (regsUsed, CND_IDX); + } + + /* Remove the unneeded push/pops */ + regsUnneeded = newBitVect (mcs51_nRegs); + while (lnp) + { + if (lnp->ic && (lnp->ic->op == FUNCTION || lnp->ic->op == ENDFUNCTION)) + { + if (!strncmp(lnp->line, "push", 4)) + { + idx = bitVectFirstBit (port->peep.getRegsRead(lnp)); + if (idx>=0 && !bitVectBitValue (regsUsed, idx)) + { + connectLine (lnp->prev, lnp->next); + regsUnneeded = bitVectSetBit (regsUnneeded, idx); + } + } + if (!strncmp(lnp->line, "pop", 3) || !strncmp(lnp->line, "mov", 3)) + { + idx = bitVectFirstBit (port->peep.getRegsWritten(lnp)); + if (idx>=0 && !bitVectBitValue (regsUsed, idx)) + { + connectLine (lnp->prev, lnp->next); + regsUnneeded = bitVectSetBit (regsUnneeded, idx); + } + } + } + lnp = lnp->next; + } + + for (idx = 0; idx < regsUnneeded->size; idx++) + if (bitVectBitValue (regsUnneeded, idx)) + emitcode ("", ";\teliminated unneeded push/pop %s", mcs51_regWithIdx (idx)->dname); + + freeBitVect (regsUnneeded); + freeBitVect (regsUsed); + freeBitVect (regsUsedPrologue); } /*-----------------------------------------------------------------*/ @@ -9584,6 +9693,7 @@ gen51Code (iCode * lic) { iCode *ic; int cln = 0; + /* int cseq = 0; */ _G.currentFunc = NULL; lineHead = lineCurr = NULL; @@ -9629,6 +9739,13 @@ gen51Code (iCode * lic) } cln = ic->lineno; } + #if 0 + if (ic->seqPoint && ic->seqPoint != cseq) + { + emitcode ("", "; sequence point %d", ic->seqPoint); + cseq = ic->seqPoint; + } + #endif if (options.iCodeInAsm) { char regsInUse[80]; int i; diff --git a/src/mcs51/main.c b/src/mcs51/main.c index 9a18499e..ee97d688 100644 --- a/src/mcs51/main.c +++ b/src/mcs51/main.c @@ -46,6 +46,7 @@ static char *_mcs51_keywords[] = }; + void mcs51_assignRegisters (eBBlock ** ebbs, int count); static int regParmFlg = 0; /* determine if we can register a parameter */ @@ -248,6 +249,388 @@ oclsExpense (struct memmap *oclass) return 0; } + + +static int +instructionSize(char *inst, char *op1, char *op2) +{ + #define ISINST(s) (strncmp(inst, (s), sizeof(s)-1) == 0) + #define IS_A(s) (*(s) == 'a' && *(s+1) == '\0') + #define IS_C(s) (*(s) == 'c' && *(s+1) == '\0') + #define IS_Rn(s) (*(s) == 'r' && *(s+1) >= '0' && *(s+1) <= '7') + #define IS_atRi(s) (*(s) == '@' && *(s+1) == 'r') + + /* Based on the current (2003-08-22) code generation for the + small library, the top instruction probability is: + + 57% mov/movx/movc + 6% push + 6% pop + 4% inc + 4% lcall + 4% add + 3% clr + 2% subb + */ + /* mov, push, & pop are the 69% of the cases. Check them first! */ + if (ISINST ("mov")) + { + if (*(inst+3)=='x') return 1; /* movx */ + if (*(inst+3)=='c') return 1; /* movc */ + if (IS_C (op1) || IS_C (op2)) return 2; + if (IS_A (op1)) + { + if (IS_Rn (op2) || IS_atRi (op2)) return 1; + return 2; + } + if (IS_Rn(op1) || IS_atRi(op1)) + { + if (IS_A(op2)) return 1; + return 2; + } + if (strcmp (op1, "dptr") == 0) return 3; + if (IS_A (op2) || IS_Rn (op2) || IS_atRi (op2)) return 2; + return 3; + } + + if (ISINST ("push")) return 2; + if (ISINST ("pop")) return 2; + + if (ISINST ("lcall")) return 3; + if (ISINST ("ret")) return 1; + if (ISINST ("ljmp")) return 3; + if (ISINST ("sjmp")) return 2; + if (ISINST ("rlc")) return 1; + if (ISINST ("rrc")) return 1; + if (ISINST ("rl")) return 1; + if (ISINST ("rr")) return 1; + if (ISINST ("swap")) return 1; + if (ISINST ("jc")) return 2; + if (ISINST ("jnc")) return 2; + if (ISINST ("jb")) return 3; + if (ISINST ("jnb")) return 3; + if (ISINST ("jbc")) return 3; + if (ISINST ("jmp")) return 1; // always jmp @a+dptr + if (ISINST ("jz")) return 2; + if (ISINST ("jnz")) return 2; + if (ISINST ("cjne")) return 3; + if (ISINST ("mul")) return 1; + if (ISINST ("div")) return 1; + if (ISINST ("da")) return 1; + if (ISINST ("xchd")) return 1; + if (ISINST ("reti")) return 1; + if (ISINST ("nop")) return 1; + if (ISINST ("acall")) return 1; + if (ISINST ("ajmp")) return 2; + + + if (ISINST ("add") || ISINST ("addc") || ISINST ("subb") || ISINST ("xch")) + { + if (IS_Rn(op2) || IS_atRi(op2)) return 1; + return 2; + } + if (ISINST ("inc") || ISINST ("dec")) + { + if (IS_A(op1) || IS_Rn(op1) || IS_atRi(op1)) return 1; + if (strcmp(op1, "dptr") == 0) return 1; + return 2; + } + if (ISINST ("anl") || ISINST ("orl") || ISINST ("xrl")) + { + if (IS_C(op1)) return 2; + if (IS_A(op1)) + { + if (IS_Rn(op2) || IS_atRi(op2)) return 1; + return 2; + } + else + { + if (IS_A(op2)) return 2; + return 3; + } + } + if (ISINST ("clr") || ISINST ("setb") || ISINST ("cpl")) + { + if (IS_A(op1) || IS_C(op1)) return 1; + return 2; + } + if (ISINST ("djnz")) + { + if (IS_Rn(op1)) return 2; + return 3; + } + + /* If the instruction is unrecognized, we shouldn't try to optimize. */ + /* Return a large value to discourage optimization. */ + return 999; +} + +static asmLineNode * +newAsmLineNode (void) +{ + asmLineNode *aln; + + aln = Safe_alloc ( sizeof (asmLineNode)); + aln->size = 0; + aln->regsRead = NULL; + aln->regsWritten = NULL; + + return aln; +} + + +typedef struct mcs51operanddata + { + char name[6]; + int regIdx1; + int regIdx2; + } +mcs51operanddata; + +static mcs51operanddata mcs51operandDataTable[] = + { + {"a", A_IDX, -1}, + {"ab", A_IDX, B_IDX}, + {"ac", CND_IDX, -1}, + {"acc", A_IDX, -1}, + {"ar0", R0_IDX, -1}, + {"ar1", R1_IDX, -1}, + {"ar2", R2_IDX, -1}, + {"ar3", R3_IDX, -1}, + {"ar4", R4_IDX, -1}, + {"ar5", R5_IDX, -1}, + {"ar6", R6_IDX, -1}, + {"ar7", R7_IDX, -1}, + {"b", B_IDX, -1}, + {"c", CND_IDX, -1}, + {"cy", CND_IDX, -1}, + {"dph", DPH_IDX, -1}, + {"dpl", DPL_IDX, -1}, + {"dptr", DPL_IDX, DPH_IDX}, + {"f0", CND_IDX, -1}, + {"f1", CND_IDX, -1}, + {"ov", CND_IDX, -1}, + {"p", CND_IDX, -1}, + {"psw", CND_IDX, -1}, + {"r0", R0_IDX, -1}, + {"r1", R1_IDX, -1}, + {"r2", R2_IDX, -1}, + {"r3", R3_IDX, -1}, + {"r4", R4_IDX, -1}, + {"r5", R5_IDX, -1}, + {"r6", R6_IDX, -1}, + {"r7", R7_IDX, -1}, + }; + +static int +mcs51operandCompare (const void *key, const void *member) +{ + return strcmp((const char *)key, ((mcs51operanddata *)member)->name); +} + +static void +updateOpRW (asmLineNode *aln, char *op, char *optype) +{ + mcs51operanddata *opdat; + char *dot; + + dot = strchr(op, '.'); + if (dot) + *dot = '\0'; + + opdat = bsearch (op, mcs51operandDataTable, + sizeof(mcs51operandDataTable)/sizeof(mcs51operanddata), + sizeof(mcs51operanddata), mcs51operandCompare); + + if (opdat && strchr(optype,'r')) + { + if (opdat->regIdx1 >= 0) + aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx1); + if (opdat->regIdx2 >= 0) + aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx2); + } + if (opdat && strchr(optype,'w')) + { + if (opdat->regIdx1 >= 0) + aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx1); + if (opdat->regIdx2 >= 0) + aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx2); + } + if (op[0] == '@') + { + if (!strcmp(op, "@r0")) + aln->regsRead = bitVectSetBit (aln->regsRead, R0_IDX); + if (!strcmp(op, "@r1")) + aln->regsRead = bitVectSetBit (aln->regsRead, R1_IDX); + if (!strstr(op, "dptr")) + { + aln->regsRead = bitVectSetBit (aln->regsRead, DPL_IDX); + aln->regsRead = bitVectSetBit (aln->regsRead, DPH_IDX); + } + if (!strstr(op, "a+")) + aln->regsRead = bitVectSetBit (aln->regsRead, A_IDX); + } +} + +typedef struct mcs51opcodedata + { + char name[6]; + char class[3]; + char pswtype[3]; + char op1type[3]; + char op2type[3]; + } +mcs51opcodedata; + +static mcs51opcodedata mcs51opcodeDataTable[] = + { + {"acall","j", "", "", ""}, + {"ajmp", "j", "", "", ""}, + {"add", "", "w", "rw", "r"}, + {"addc", "", "rw", "rw", "r"}, + {"anl", "", "", "rw", "r"}, + {"cjne", "j", "w", "r", "r"}, + {"clr", "", "", "w", ""}, + {"cpl", "", "", "rw", ""}, + {"da", "", "rw", "rw", ""}, + {"dec", "", "", "rw", ""}, + {"div", "", "w", "rw", ""}, + {"djnz", "j", "", "rw", ""}, + {"inc", "", "", "rw", ""}, + {"jb", "j", "", "r", ""}, + {"jbc", "j", "", "rw", ""}, + {"jc", "j", "", "", ""}, + {"jmp", "j", "", "", ""}, + {"jnb", "j", "", "r", ""}, + {"jnc", "j", "", "", ""}, + {"jnz", "j", "", "", ""}, + {"jz", "j", "", "", ""}, + {"lcall","j", "", "", ""}, + {"ljmp", "j", "", "", ""}, + {"mov", "", "", "w", "r"}, + {"movc", "", "", "w", "r"}, + {"movx", "", "", "w", "r"}, + {"mul", "", "w", "rw", ""}, + {"nop", "", "", "", ""}, + {"orl", "", "", "rw", "r"}, + {"pop", "", "", "w", ""}, + {"push", "", "", "r", ""}, + {"ret", "j", "", "", ""}, + {"reti", "j", "", "", ""}, + {"rl", "", "", "rw", ""}, + {"rlc", "", "rw", "rw", ""}, + {"rr", "", "", "rw", ""}, + {"rrc", "", "rw", "rw", ""}, + {"setb", "", "", "w", ""}, + {"sjmp", "j", "", "", ""}, + {"subb", "", "rw", "rw", "r"}, + {"swap", "", "", "rw", ""}, + {"xch", "", "", "rw", "rw"}, + {"xchd", "", "", "rw", "rw"}, + {"xrl", "", "", "rw", "r"}, + }; + +static int +mcs51opcodeCompare (const void *key, const void *member) +{ + return strcmp((const char *)key, ((mcs51opcodedata *)member)->name); +} + +static asmLineNode * +asmLineNodeFromLineNode (lineNode *ln) +{ + asmLineNode *aln = newAsmLineNode(); + char *op, op1[256], op2[256]; + int opsize; + const char *p; + char inst[8]; + mcs51opcodedata *opdat; + + p = ln->line; + + while (*p && isspace(*p)) p++; + for (op = inst, opsize=1; *p; p++) + { + if (isspace(*p) || *p == ';' || *p == ':' || *p == '=') + break; + else + if (opsize < sizeof(inst)) + *op++ = tolower(*p), opsize++; + } + *op = '\0'; + + if (*p == ';' || *p == ':' || *p == '=') + return aln; + + while (*p && isspace(*p)) p++; + if (*p == '=') + return aln; + + for (op = op1, opsize=1; *p && *p != ','; p++) + { + if (!isspace(*p) && opsize < sizeof(op1)) + *op++ = tolower(*p), opsize++; + } + *op = '\0'; + + if (*p == ',') p++; + for (op = op2, opsize=1; *p && *p != ','; p++) + { + if (!isspace(*p) && opsize < sizeof(op2)) + *op++ = tolower(*p), opsize++; + } + *op = '\0'; + + aln->size = instructionSize(inst, op1, op2); + + aln->regsRead = newBitVect (END_IDX); + aln->regsWritten = newBitVect (END_IDX); + + opdat = bsearch (inst, mcs51opcodeDataTable, + sizeof(mcs51opcodeDataTable)/sizeof(mcs51opcodedata), + sizeof(mcs51opcodedata), mcs51opcodeCompare); + + if (opdat) + { + updateOpRW (aln, op1, opdat->op1type); + updateOpRW (aln, op2, opdat->op2type); + if (strchr(opdat->pswtype,'r')) + aln->regsRead = bitVectSetBit (aln->regsRead, CND_IDX); + if (strchr(opdat->pswtype,'w')) + aln->regsWritten = bitVectSetBit (aln->regsWritten, CND_IDX); + } + + return aln; +} + +static int +getInstructionSize (lineNode *line) +{ + if (!line->aln) + line->aln = asmLineNodeFromLineNode (line); + + return line->aln->size; +} + +static bitVect * +getRegsRead (lineNode *line) +{ + if (!line->aln) + line->aln = asmLineNodeFromLineNode (line); + + return line->aln->regsRead; +} + +static bitVect * +getRegsWritten (lineNode *line) +{ + if (!line->aln) + line->aln = asmLineNodeFromLineNode (line); + + return line->aln->regsWritten; +} + + /** $1 is always the basename. $2 is always the output file. $3 varies @@ -295,7 +678,10 @@ PORT mcs51_port = 1 }, { - _defaultRules + _defaultRules, + getInstructionSize, + getRegsRead, + getRegsWritten }, { /* Sizes: char, short, int, long, ptr, fptr, gptr, bit, float, max */ diff --git a/src/mcs51/main.h b/src/mcs51/main.h index 65552254..4c423f68 100644 --- a/src/mcs51/main.h +++ b/src/mcs51/main.h @@ -1,6 +1,14 @@ #ifndef MAIN_INCLUDE #define MAIN_INCLUDE +typedef struct asmLineNode + { + int size; + bitVect *regsRead; + bitVect *regsWritten; + } +asmLineNode; + bool x_parseOptions (char **argv, int *pargc); void x_setDefaultOptions (void); void x_finaliseOptions (void); diff --git a/src/mcs51/ralloc.c b/src/mcs51/ralloc.c index 2036408d..88f13108 100644 --- a/src/mcs51/ralloc.c +++ b/src/mcs51/ralloc.c @@ -74,9 +74,13 @@ regs regs8051[] = {REG_GPR, X10_IDX, REG_GPR, "x10", "x10", "xreg", 2, 1}, {REG_GPR, X11_IDX, REG_GPR, "x11", "x11", "xreg", 3, 1}, {REG_GPR, X12_IDX, REG_GPR, "x12", "x12", "xreg", 4, 1}, - {REG_CND, CND_IDX, REG_CND, "C", "C", "xreg", 0, 1}, + {REG_CND, CND_IDX, REG_CND, "C", "psw", "0xd0", 0, 1}, + {0, DPL_IDX, 0, "dpl", "dpl", "0x82", 0, 0}, + {0, DPH_IDX, 0, "dph", "dph", "0x83", 0, 0}, + {0, B_IDX, 0, "b", "b", "0xf0", 0, 0}, + {0, A_IDX, 0, "a", "acc", "0xe0", 0, 0}, }; -int mcs51_nRegs = 13; +int mcs51_nRegs = 17; static void spillThis (symbol *); static void freeAllRegs (); @@ -125,7 +129,7 @@ mcs51_regWithIdx (int idx) { int i; - for (i = 0; i < mcs51_nRegs; i++) + for (i = 0; i < sizeof(regs8051)/sizeof(regs); i++) if (regs8051[i].rIdx == idx) return ®s8051[i]; @@ -2822,6 +2826,12 @@ packRegisters (eBBlock ** ebpp, int blockno) mcs51_ptrRegReq += ((OP_SYMBOL (IC_RESULT (ic))->onStack || OP_SYMBOL (IC_RESULT (ic))->iaccess || SPEC_OCLS(OP_SYMBOL (IC_RESULT (ic))->etype) == idata) ? 1 : 0); + if (POINTER_GET (ic) && IS_SYMOP (IC_LEFT (ic)) + && getSize (OP_SYMBOL (IC_LEFT (ic))->type) <= (unsigned int) PTRSIZE) + mcs51_ptrRegReq ++; + if (POINTER_SET (ic) && IS_SYMOP (IC_RESULT (ic)) + && getSize (OP_SYMBOL (IC_RESULT (ic))->type) <= (unsigned int) PTRSIZE) + mcs51_ptrRegReq ++; } } diff --git a/src/mcs51/ralloc.h b/src/mcs51/ralloc.h index fc8d87a9..978ccfc5 100644 --- a/src/mcs51/ralloc.h +++ b/src/mcs51/ralloc.h @@ -33,7 +33,9 @@ enum R5_IDX, R6_IDX, R7_IDX, R0_IDX, R1_IDX, X8_IDX, X9_IDX, X10_IDX, X11_IDX, - X12_IDX, CND_IDX + X12_IDX, CND_IDX, + DPL_IDX, DPH_IDX, B_IDX, A_IDX, + END_IDX }; diff --git a/src/port.h b/src/port.h index 9281f663..010a3efd 100644 --- a/src/port.h +++ b/src/port.h @@ -7,6 +7,7 @@ #include "SDCCicode.h" #include "SDCCargs.h" +#include "SDCCpeeph.h" #define TARGET_ID_MCS51 1 #define TARGET_ID_GBZ80 2 @@ -113,6 +114,9 @@ typedef struct { /** Default peephole rules */ char *default_rules; + int (*getSize)(lineNode *line); + bitVect * (*getRegsRead)(lineNode *line); + bitVect * (*getRegsWritten)(lineNode *line); } peep; -- 2.30.2