From e0fcbaee124d3e8c4c11bdda662f88e082352058 Mon Sep 17 00:00:00 2001 From: jcorgan Date: Mon, 8 Sep 2008 01:00:12 +0000 Subject: [PATCH] Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5 --- Makefile.am | 2 +- bootstrap | 3 + config/Makefile.am | 1 + config/grc_gr_usrp2.m4 | 37 + config/grc_usrp2.m4 | 86 + configure.ac | 2 + gnuradio-core/src/utils/Makefile.am | 1 + gnuradio-core/src/utils/read_cshort_binary.m | 46 + gr-usrp2/Makefile.am | 24 + gr-usrp2/src/Makefile.am | 136 + gr-usrp2/src/qa_usrp2.py | 40 + gr-usrp2/src/run_tests.in | 17 + gr-usrp2/src/rx_16sc_handler.cc | 31 + gr-usrp2/src/rx_16sc_handler.h | 75 + gr-usrp2/src/rx_32fc_handler.cc | 31 + gr-usrp2/src/rx_32fc_handler.h | 76 + gr-usrp2/src/usrp2.i | 146 + gr-usrp2/src/usrp2_sink_32fc.cc | 46 + gr-usrp2/src/usrp2_sink_32fc.h | 47 + gr-usrp2/src/usrp2_sink_base.cc | 49 + gr-usrp2/src/usrp2_sink_base.h | 46 + gr-usrp2/src/usrp2_source_16sc.cc | 77 + gr-usrp2/src/usrp2_source_16sc.h | 54 + gr-usrp2/src/usrp2_source_32fc.cc | 77 + gr-usrp2/src/usrp2_source_32fc.h | 54 + gr-usrp2/src/usrp2_source_base.cc | 92 + gr-usrp2/src/usrp2_source_base.h | 85 + gr-utils/src/python/Makefile.am | 4 +- gr-utils/src/python/usrp2_fft.py | 268 + gr-utils/src/python/usrp2_rx_cfile.py | 119 + usrp2/Makefile.am | 23 + usrp2/doc/inband-signaling-eth | 390 + usrp2/firmware/AUTHORS | 2 + usrp2/firmware/COPYING | 674 + usrp2/firmware/ChangeLog | 22 + usrp2/firmware/INSTALL | 234 + usrp2/firmware/Makefile.am | 21 + usrp2/firmware/Makefile.common | 59 + usrp2/firmware/NEWS | 0 usrp2/firmware/README | 5 + usrp2/firmware/apps/Makefile.am | 63 + usrp2/firmware/apps/app_common_v2.c | 477 + usrp2/firmware/apps/app_common_v2.h | 62 + usrp2/firmware/apps/app_passthru_v2.c | 244 + usrp2/firmware/apps/app_passthru_v2.h | 54 + usrp2/firmware/apps/bitrot/tx_drop.c | 261 + usrp2/firmware/apps/bitrot/tx_drop2.c | 292 + .../apps/bitrot/tx_drop_rate_limited.c | 233 + usrp2/firmware/apps/blink_leds.c | 40 + usrp2/firmware/apps/blink_leds2.c | 53 + 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usrp2/fpga/testbench/cmdfile create mode 100644 usrp2/fpga/timing/time_receiver.v create mode 100644 usrp2/fpga/timing/time_sender.v create mode 100644 usrp2/fpga/timing/time_sync.v create mode 100644 usrp2/fpga/timing/time_transfer_tb.v create mode 100644 usrp2/fpga/timing/timer.v create mode 100644 usrp2/fpga/top/eth_test/eth_sim_top.v create mode 100644 usrp2/fpga/top/eth_test/eth_tb.v create mode 100644 usrp2/fpga/top/single_u2_sim/single_u2_sim.v create mode 100644 usrp2/fpga/top/tcl/ise_helper.tcl create mode 100755 usrp2/fpga/top/u2_core/u2_core.v create mode 100644 usrp2/fpga/top/u2_fpga/Makefile create mode 100644 usrp2/fpga/top/u2_fpga/u2_fpga.ise create mode 100755 usrp2/fpga/top/u2_fpga/u2_fpga.ucf create mode 100644 usrp2/fpga/top/u2_fpga/u2_fpga_top.prj create mode 100644 usrp2/fpga/top/u2_fpga/u2_fpga_top.v create mode 100644 usrp2/fpga/top/u2_rev2/Makefile create mode 100644 usrp2/fpga/top/u2_rev2/u2_rev2.ucf create mode 100644 usrp2/fpga/top/u2_rev2/u2_rev2.v create mode 100644 usrp2/fpga/top/u2_rev3/Makefile create mode 100644 usrp2/fpga/top/u2_rev3/u2_rev3.ucf create mode 100644 usrp2/fpga/top/u2_rev3/u2_rev3.v create mode 100755 usrp2/fpga/top/u2plus/u2plus.ucf create mode 100644 usrp2/fpga/top/u2plus/u2plus.v create mode 100644 usrp2/host/Makefile.am create mode 100644 usrp2/host/apps/Makefile.am create mode 100644 usrp2/host/apps/find_usrps.cc create mode 100755 usrp2/host/apps/gen_2tone.py create mode 100644 usrp2/host/apps/gen_const.cc create mode 100755 usrp2/host/apps/gen_sine.py create mode 100644 usrp2/host/apps/rx_samples.cc create mode 100644 usrp2/host/apps/rx_streaming_samples.cc create mode 100755 usrp2/host/apps/stdin_int32_fft.py create mode 100755 usrp2/host/apps/streaming_fft.py create mode 100755 usrp2/host/apps/test.sh create mode 100644 usrp2/host/apps/tx_samples.cc create mode 100644 usrp2/host/apps/usrp2_burn_mac_addr.cc create mode 100644 usrp2/host/include/Makefile.am create mode 100644 usrp2/host/include/usrp2/Makefile.am create mode 100644 usrp2/host/include/usrp2/copiers.h create mode 100644 usrp2/host/include/usrp2/copy_handler.h create mode 100644 usrp2/host/include/usrp2/data_handler.h create mode 100644 usrp2/host/include/usrp2/metadata.h create mode 100644 usrp2/host/include/usrp2/rx_nop_handler.h create mode 100644 usrp2/host/include/usrp2/rx_sample_handler.h create mode 100644 usrp2/host/include/usrp2/strtod_si.h create mode 100644 usrp2/host/include/usrp2/tune_result.h create mode 100644 usrp2/host/include/usrp2/usrp2.h create mode 100644 usrp2/host/include/usrp2/usrp2_cdefs.h create mode 100644 usrp2/host/lib/Makefile.am create mode 100644 usrp2/host/lib/control.cc create mode 100644 usrp2/host/lib/control.h create mode 100644 usrp2/host/lib/copiers.cc create mode 100644 usrp2/host/lib/copy_handler.cc create mode 100644 usrp2/host/lib/data_handler.cc create mode 100644 usrp2/host/lib/eth_buffer.cc create mode 100644 usrp2/host/lib/eth_buffer.h create mode 100644 usrp2/host/lib/eth_common.h create mode 100644 usrp2/host/lib/ethernet.cc create mode 100644 usrp2/host/lib/ethernet.h create mode 100644 usrp2/host/lib/find.cc create mode 100644 usrp2/host/lib/open_usrp2_socket.cc create mode 100644 usrp2/host/lib/open_usrp2_socket.h create mode 100644 usrp2/host/lib/pktfilter.cc create mode 100644 usrp2/host/lib/pktfilter.h create mode 100644 usrp2/host/lib/ring.cc create mode 100644 usrp2/host/lib/ring.h create mode 100644 usrp2/host/lib/rx_nop_handler.cc create mode 100644 usrp2/host/lib/rx_sample_handler.cc create mode 100644 usrp2/host/lib/strtod_si.c create mode 100644 usrp2/host/lib/usrp2.cc create mode 100644 usrp2/host/lib/usrp2_bytesex.h create mode 100644 usrp2/host/lib/usrp2_impl.cc create mode 100644 usrp2/host/lib/usrp2_impl.h create mode 100644 usrp2/host/lib/usrp2_socket_opener.cc create mode 100644 usrp2/host/lib/usrp2_thread.cc create mode 100644 usrp2/host/lib/usrp2_thread.h create mode 100644 usrp2/host/usrp2.pc.in diff --git a/Makefile.am b/Makefile.am index 9262c5bc..91b0e5d2 100644 --- a/Makefile.am +++ b/Makefile.am @@ -32,5 +32,5 @@ EXTRA_DIST = \ README.hacking \ README.building-boost -SUBDIRS = @build_dirs@ +SUBDIRS = @build_dirs@ $(subdirs) DIST_SUBDIRS = @build_dirs@ @skipped_dirs@ @with_dirs@ diff --git a/bootstrap b/bootstrap index 7daff90d..463ff165 100755 --- a/bootstrap +++ b/bootstrap @@ -28,3 +28,6 @@ autoheader libtoolize --automake automake --add-missing -Wno-portability -Wno-override -Wnone #automake --add-missing -Wno-portability + +# Run bootstrap in any subprojects +(cd usrp2/firmware ; ./bootstrap) diff --git a/config/Makefile.am b/config/Makefile.am index abc34e34..0ee6096a 100644 --- a/config/Makefile.am +++ b/config/Makefile.am @@ -74,6 +74,7 @@ m4macros = \ gr_check_usrp.m4 \ grc_pmt.m4 \ grc_usrp.m4 \ + grc_usrp2.m4 \ grc_gr_msdd6000.m4 \ gr_doxygen.m4 \ gr_fortran.m4 \ diff --git a/config/grc_gr_usrp2.m4 b/config/grc_gr_usrp2.m4 new file mode 100644 index 00000000..223cac03 --- /dev/null +++ b/config/grc_gr_usrp2.m4 @@ -0,0 +1,37 @@ +dnl Copyright 2008 Free Software Foundation, Inc. +dnl +dnl This file is part of GNU Radio +dnl +dnl GNU Radio is free software; you can redistribute it and/or modify +dnl it under the terms of the GNU General Public License as published by +dnl the Free Software Foundation; either version 3, or (at your option) +dnl any later version. +dnl +dnl GNU Radio is distributed in the hope that it will be useful, +dnl but WITHOUT ANY WARRANTY; without even the implied warranty of +dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +dnl GNU General Public License for more details. +dnl +dnl You should have received a copy of the GNU General Public License +dnl along with GNU Radio; see the file COPYING. If not, write to +dnl the Free Software Foundation, Inc., 51 Franklin Street, +dnl Boston, MA 02110-1301, USA. + +AC_DEFUN([GRC_GR_USRP2],[ + GRC_ENABLE(gr-usrp2) + + dnl Don't do gr-usrp if gnuradio-core or usrp2 skipped + GRC_CHECK_DEPENDENCY(gr-usrp2, usrp2) + GRC_CHECK_DEPENDENCY(gr-usrp2, gnuradio-core) + + AC_CONFIG_FILES([ \ + gr-usrp2/Makefile \ + gr-usrp2/src/Makefile \ + gr-usrp2/src/run_tests \ + ]) + + GRC_BUILD_CONDITIONAL(gr-usrp2,[ + dnl run_tests is created from run_tests.in. Make it executable. + AC_CONFIG_COMMANDS([run_tests_usrp2], [chmod +x gr-usrp2/src/run_tests]) + ]) +]) diff --git a/config/grc_usrp2.m4 b/config/grc_usrp2.m4 new file mode 100644 index 00000000..f842a79a --- /dev/null +++ b/config/grc_usrp2.m4 @@ -0,0 +1,86 @@ +dnl Copyright 2008 Free Software Foundation, Inc. +dnl +dnl This file is part of GNU Radio +dnl +dnl GNU Radio is free software; you can redistribute it and/or modify +dnl it under the terms of the GNU General Public License as published by +dnl the Free Software Foundation; either version 3, or (at your option) +dnl any later version. +dnl +dnl GNU Radio is distributed in the hope that it will be useful, +dnl but WITHOUT ANY WARRANTY; without even the implied warranty of +dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +dnl GNU General Public License for more details. +dnl +dnl You should have received a copy of the GNU General Public License +dnl along with GNU Radio; see the file COPYING. If not, write to +dnl the Free Software Foundation, Inc., 51 Franklin Street, +dnl Boston, MA 02110-1301, USA. + +AC_DEFUN([GRC_USRP2],[ + GRC_ENABLE(usrp2) + + dnl Don't do usrp if omnithread or gruel is skipped + GRC_CHECK_DEPENDENCY(usrp2, gruel) + GRC_CHECK_DEPENDENCY(usrp2, omnithread) + + dnl USRP2 host code only works on Linux at the moment + AC_MSG_CHECKING([whether host_cpu is linux*]) + case "$host_os" in + linux*) + AC_MSG_RESULT("yes") + ;; + *) + AC_MSG_RESULT("no") + echo "USRP2 requires Linux host OS, not found" + passed="no" + ;; + esac + + dnl If execution gets to here, $passed will be: + dnl with : if the --with code didn't error out + dnl yes : if the --enable code passed muster and all dependencies are met + dnl no : otherwise + if test $passed = yes; then + dnl Only do firmware if mb-gcc can be found + AC_CHECK_PROG([MB_GCC],[mb-gcc],[yes],[no]) + if test $MB_GCC = yes; then + dnl Adds usrp2/firmware to $(subdirs), hierarchical build + AC_CONFIG_SUBDIRS([usrp2/firmware]) + fi + + dnl Needed for usrp2_socket_opener + AC_CHECK_HEADERS(arpa/inet.h byteswap.h linux/if_packet.h sys/socket.h sys/un.h) + AC_CHECK_MEMBERS([struct msghdr.msg_control, + struct msghdr.msg_accrights, + struct cmsgcred.cmcred_uid, + struct ucred.uid], + [],[], + [#define __USE_GNU 1 + #include + #include + #include ]) + fi + if test $passed != with; then + dnl how and where to find INCLUDES and LA + USRP2_INCLUDES="-I\${abs_top_srcdir}/usrp2/host/include \ + -I\${abs_top_srcdir}/usrp2/firmware/include" + USRP2_LA="\${abs_top_builddir}/usrp2/host/lib/libusrp2.la" + fi + + dnl Include the usrp2 INCLUDES and LA + AC_SUBST(USRP2_INCLUDES) + AC_SUBST(USRP2_LA) + + AC_CONFIG_FILES([ \ + usrp2/Makefile + usrp2/host/Makefile \ + usrp2/host/usrp2.pc \ + usrp2/host/include/Makefile + usrp2/host/include/usrp2/Makefile + usrp2/host/lib/Makefile + usrp2/host/apps/Makefile + ]) + + GRC_BUILD_CONDITIONAL(usrp2) +]) diff --git a/configure.ac b/configure.ac index bae9f344..4b581a16 100644 --- a/configure.ac +++ b/configure.ac @@ -272,7 +272,9 @@ GRC_GNURADIO_CORE GRC_PMT GRC_MBLOCK dnl this must come after GRC_PMT GRC_USRP +GRC_USRP2 GRC_GR_USRP dnl this must come after GRC_USRP +GRC_GR_USRP2 GRC_GR_GCELL dnl this must come after GRC_GCELL and GRC_GNURADIO_CORE GRC_GR_MSDD6000 GRC_GR_AUDIO_ALSA diff --git a/gnuradio-core/src/utils/Makefile.am b/gnuradio-core/src/utils/Makefile.am index 78c80dab..07960a07 100644 --- a/gnuradio-core/src/utils/Makefile.am +++ b/gnuradio-core/src/utils/Makefile.am @@ -39,6 +39,7 @@ EXTRA_DIST = \ read_float_binary.m \ read_int_binary.m \ read_short_binary.m \ + read_cshort_binary.m \ single_pole_iir.m \ write_float_binary.m \ write_short_binary.m diff --git a/gnuradio-core/src/utils/read_cshort_binary.m b/gnuradio-core/src/utils/read_cshort_binary.m new file mode 100644 index 00000000..04706710 --- /dev/null +++ b/gnuradio-core/src/utils/read_cshort_binary.m @@ -0,0 +1,46 @@ +% +% Copyright 2001,2008 Free Software Foundation, Inc. +% +% This file is part of GNU Radio +% +% GNU Radio is free software; you can redistribute it and/or modify +% it under the terms of the GNU General Public License as published by +% the Free Software Foundation; either version 3, or (at your option) +% any later version. +% +% GNU Radio is distributed in the hope that it will be useful, +% but WITHOUT ANY WARRANTY; without even the implied warranty of +% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +% GNU General Public License for more details. +% +% You should have received a copy of the GNU General Public License +% along with GNU Radio; see the file COPYING. If not, write to +% the Free Software Foundation, Inc., 51 Franklin Street, +% Boston, MA 02110-1301, USA. +% + +function cv = read_cshort_binary (filename, count) + + %% usage: read_cshort_binary (filename, [count]) + %% + %% open filename and return the contents, treating them as + %% signed short integers + %% + + m = nargchk (1,2,nargin); + if (m) + usage (m); + end + + if (nargin < 2) + count = Inf; + end + + f = fopen (filename, 'rb'); + if (f < 0) + cv = 0; + else + v = fread (f, count, 'short'); + fclose (f); + cv = v(1:2:end)+v(2:2:end)*j; + end diff --git a/gr-usrp2/Makefile.am b/gr-usrp2/Makefile.am new file mode 100644 index 00000000..a9a7a3a8 --- /dev/null +++ b/gr-usrp2/Makefile.am @@ -0,0 +1,24 @@ +# +# Copyright 2001,2006,2008 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +include $(top_srcdir)/Makefile.common + +SUBDIRS = src diff --git a/gr-usrp2/src/Makefile.am b/gr-usrp2/src/Makefile.am new file mode 100644 index 00000000..da626d59 --- /dev/null +++ b/gr-usrp2/src/Makefile.am @@ -0,0 +1,136 @@ +# +# Copyright 2004,2005,2006,2008 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +include $(top_srcdir)/Makefile.common + +# ---------------------------------------------------------------------- +# C++ block API interface librar(ies) +# +# libgr-usrp.so +# ---------------------------------------------------------------------- +AM_CPPFLAGS = \ + $(STD_DEFINES_AND_INCLUDES) \ + $(GRUEL_INCLUDES) \ + $(PYTHON_CPPFLAGS) \ + $(USRP2_INCLUDES) \ + $(WITH_INCLUDES) + +lib_LTLIBRARIES = libgr-usrp2.la + +libgr_usrp2_la_SOURCES = \ + rx_16sc_handler.cc \ + rx_32fc_handler.cc \ + usrp2_source_base.cc \ + usrp2_source_16sc.cc \ + usrp2_source_32fc.cc +# usrp2_source_16sc.cc +# usrp2_sink_base.cc +# usrp2_sink_32fc.cc +# usrp2_sink_16sc.cc + +libgr_usrp2_la_LIBADD = \ + $(USRP2_LA) \ + $(GNURADIO_CORE_LA) + +grinclude_HEADERS = \ + usrp2_source_base.h \ + usrp2_source_32fc.h \ + usrp2_source_16sc.h +# usrp2_sink_base.h \ +# usrp2_sink_32fc.h \ +# usrp2_sink_16sc.h + +noinst_HEADERS = \ + rx_16sc_handler.h \ + rx_32fc_handler.h + +# ---------------------------------------------------------------------- +# Python SWIG wrapper around C++ library +# +# usrp2.py +# _usrp2.so +# ---------------------------------------------------------------------- + +# Python installation locations +ourpythondir = $(grpythondir) +ourlibdir = $(grpyexecdir) + +# SWIG interface files +LOCAL_IFILES = $(srcdir)/usrp2.i +NON_LOCAL_IFILES = $(GNURADIO_I) +ALL_IFILES = $(LOCAL_IFILES) $(NON_LOCAL_IFILES) + +# Install the SWIG interface files +swiginclude_HEADERS = $(LOCAL_IFILES) + +# Generated by SWIG wrapper generator +BUILT_SOURCES = usrp2.cc usrp2.py + +# Install the SWIG python output +ourpython_PYTHON = usrp2.py + +# Arguments to the swig wrapper generator +SWIGPYTHONARGS = \ + $(STD_DEFINES_AND_INCLUDES) \ + $(SWIGPYTHONFLAGS) \ + $(USRP2_INCLUDES) \ + $(WITH_INCLUDES) \ + $(WITH_SWIG_INCLUDES) + +# Invoke SWIG wrapper generator +usrp2.cc usrp2.py: $(ALL_IFILES) + $(SWIG) $(SWIGPYTHONARGS) -module usrp2 -o usrp2.cc $(LOCAL_IFILES) + +# Create the Python shared library +ourlib_LTLIBRARIES = _usrp2.la +_usrp2_la_SOURCES = usrp2.cc +_usrp2_la_CXXFLAGS = @swig_CXXFLAGS@ +_usrp2_la_LDFLAGS = $(swig_CXXFLAGS) $(NO_UNDEFINED) -module -avoid-version + +# Link the library as needed +_usrp2_la_LIBADD = \ + $(PYTHON_LDFLAGS) \ + libgr-usrp2.la \ + $(GNURADIO_CORE_LA) \ + $(USRP2_LIBS) \ + -lstdc++ + +# Don't distribute output of swig +dist-hook: + @for file in $(BUILT_SOURCES); do echo $(RM) $(distdir)/$$file; done + @for file in $(BUILT_SOURCES); do $(RM) $(distdir)/$$file; done + +# ---------------------------------------------------------------------- +# Local Python files, not installed +# +# qa_usrp2.py +# ---------------------------------------------------------------------- + +noinst_PYTHON = qa_usrp2.py + + +# ---------------------------------------------------------------------- +# Miscellaneous build operations +# ---------------------------------------------------------------------- + +EXTRA_DIST = run_tests.in +TESTS = run_tests +MOSTLYCLEANFILES = $(BUILT_SOURCES) *.pyc diff --git a/gr-usrp2/src/qa_usrp2.py b/gr-usrp2/src/qa_usrp2.py new file mode 100755 index 00000000..bc6664a1 --- /dev/null +++ b/gr-usrp2/src/qa_usrp2.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python +# +# Copyright 2005,2008 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gr_unittest +import usrp2 + +class qa_usrp2(gr_unittest.TestCase): + + def setUp(self): + self.tb = gr.top_block() + + def tearDown(self): + self.tb = None + + def test_000_nop (self): + """Just see if we can import the module... + They may not have a USRP2 connected, etc. Don't try to run anything""" + pass + +if __name__ == '__main__': + gr_unittest.main () diff --git a/gr-usrp2/src/run_tests.in b/gr-usrp2/src/run_tests.in new file mode 100644 index 00000000..99190b81 --- /dev/null +++ b/gr-usrp2/src/run_tests.in @@ -0,0 +1,17 @@ +#!/bin/sh + +# 1st parameter is absolute path to component source directory +# 2nd parameter is absolute path to component build directory +# 3rd parameter is path to Python QA directory + +# For OS/X +DYLD_LIBRARY_PATH=@abs_top_builddir@/usrp2/host/lib/legacy:@abs_top_builddir@/usrp2/host/lib/legacy/.libs:$DYLD_LIBRARY_PATH +export DYLD_LIBRARY_PATH + +# For Win32 +PATH=@abs_top_builddir@/usrp2/host/lib/legacy:@abs_top_builddir@/usrp2/host/lib/legacy/.libs:$PATH + +@top_builddir@/run_tests.sh \ + @abs_top_srcdir@/gr-usrp2 \ + @abs_top_builddir@/gr-usrp2 \ + @srcdir@ diff --git a/gr-usrp2/src/rx_16sc_handler.cc b/gr-usrp2/src/rx_16sc_handler.cc new file mode 100644 index 00000000..a3ab2a2b --- /dev/null +++ b/gr-usrp2/src/rx_16sc_handler.cc @@ -0,0 +1,31 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +rx_16sc_handler::~rx_16sc_handler() +{ +} diff --git a/gr-usrp2/src/rx_16sc_handler.h b/gr-usrp2/src/rx_16sc_handler.h new file mode 100644 index 00000000..cb83d860 --- /dev/null +++ b/gr-usrp2/src/rx_16sc_handler.h @@ -0,0 +1,75 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_RX_16SC_HANDLER_H +#define INCLUDED_RX_16SC_HANDLER_H + +#include +#include + +#define RX_16SC_HANDLER_DEBUG 0 + +class rx_16sc_handler : public usrp2::rx_nop_handler +{ + std::complex *d_dest; + + // Private constructor + rx_16sc_handler(uint64_t max_samples, uint64_t max_quantum, std::complex *dest) + : rx_nop_handler(max_samples, max_quantum), d_dest(dest) {} + +public: + // Shared pointer to one of these + typedef boost::shared_ptr sptr; + + // Factory function to return a shared pointer to a new instance + static sptr make(uint64_t max_samples, uint64_t max_quantum, std::complex *dest) + { + if (RX_16SC_HANDLER_DEBUG) + printf("rx_16sc_handler: max_samples=%li max_quantum=%li\n", max_samples, max_quantum); + + return sptr(new rx_16sc_handler(max_samples, max_quantum, dest)); + } + + // Invoked by USRP2 API when samples are available + bool operator()(const uint32_t *items, size_t nitems, const usrp2::rx_metadata *metadata) + { + if (RX_16SC_HANDLER_DEBUG) + printf("rx_16sc_handler: called with items=%zu ", nitems); + + // Copy/reformat/endian swap USRP2 data to destination buffer + usrp2::copy_u2_complex_16_to_host_complex_16(nitems, items, d_dest); + d_dest += nitems; + + // FIXME: do something with metadata + + // Determine if there is room to be called again + bool ok = rx_nop_handler::operator()(items, nitems, metadata); + if (RX_16SC_HANDLER_DEBUG) + printf("ok to call again=%i\n", ok); + + return ok; + } + + ~rx_16sc_handler(); +}; + +#endif /* INCLUDED_RX_16SC_HANDLER_H */ diff --git a/gr-usrp2/src/rx_32fc_handler.cc b/gr-usrp2/src/rx_32fc_handler.cc new file mode 100644 index 00000000..f8347633 --- /dev/null +++ b/gr-usrp2/src/rx_32fc_handler.cc @@ -0,0 +1,31 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include + +rx_32fc_handler::~rx_32fc_handler() +{ +} diff --git a/gr-usrp2/src/rx_32fc_handler.h b/gr-usrp2/src/rx_32fc_handler.h new file mode 100644 index 00000000..87502796 --- /dev/null +++ b/gr-usrp2/src/rx_32fc_handler.h @@ -0,0 +1,76 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_RX_32FC_HANDLER_H +#define INCLUDED_RX_32FC_HANDLER_H + +#include +#include +#include + +#define RX_32FC_HANDLER_DEBUG 0 + +class rx_32fc_handler : public usrp2::rx_nop_handler +{ + gr_complex *d_dest; + + // Private constructor + rx_32fc_handler(uint64_t max_samples, uint64_t max_quantum, gr_complex *dest) + : rx_nop_handler(max_samples, max_quantum), d_dest(dest) {} + +public: + // Shared pointer to one of these + typedef boost::shared_ptr sptr; + + // Factory function to return a shared pointer to a new instance + static sptr make(uint64_t max_samples, uint64_t max_quantum, gr_complex *dest) + { + if (RX_32FC_HANDLER_DEBUG) + printf("rx_32fc_handler: max_samples=%li max_quantum=%li\n", max_samples, max_quantum); + + return sptr(new rx_32fc_handler(max_samples, max_quantum, dest)); + } + + // Invoked by USRP2 API when samples are available + bool operator()(const uint32_t *items, size_t nitems, const usrp2::rx_metadata *metadata) + { + if (RX_32FC_HANDLER_DEBUG) + printf("rx_32fc_handler: called with items=%zu ", nitems); + + // Copy/reformat/endian swap USRP2 data to destination buffer + usrp2::copy_u2_complex_16_to_host_complex_float(nitems, items, d_dest); + d_dest += nitems; + + // FIXME: do something with metadata + + // Determine if there is room to be called again + bool ok = rx_nop_handler::operator()(items, nitems, metadata); + if (RX_32FC_HANDLER_DEBUG) + printf("ok to call again=%i\n", ok); + + return ok; + } + + ~rx_32fc_handler(); +}; + +#endif /* INCLUDED_RX_32FC_HANDLER_H */ diff --git a/gr-usrp2/src/usrp2.i b/gr-usrp2/src/usrp2.i new file mode 100644 index 00000000..fba6c18e --- /dev/null +++ b/gr-usrp2/src/usrp2.i @@ -0,0 +1,146 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +%feature("autodoc", "1"); // generate python docstrings + +%include "exception.i" +%import "gnuradio.i" // the common stuff + +%{ +#include +//#include "usrp2_sink_32fc.h" +#include "usrp2_source_16sc.h" +#include "usrp2_source_32fc.h" +%} + +%include + +#if 0 +// ---------------------------------------------------------------- + +class usrp2_sink_base : public gr_sync_block { + +protected: + usrp2_sink_base(const std::string &name, + gr_io_signature_sptr input_signature) + throw (std::runtime_error); + +public: + ~usrp2_sink_base(); + +}; + +// ---------------------------------------------------------------- + +GR_SWIG_BLOCK_MAGIC(usrp2,sink_32fc) + +usrp2_sink_32fc_sptr +usrp2_make_sink_32fc() throw (std::runtime_error); + +class usrp2_sink_32fc : public usrp2_sink_base { + +protected: + usrp2_sink_32fc(); + +public: + ~usrp2_sink_32fc(); + +}; +#endif + +// ---------------------------------------------------------------- + +class usrp2_source_base : public gr_sync_block { + +protected: + usrp2_source_base(const char *name, + gr_io_signature_sptr output_signature) + throw (std::runtime_error); + +public: + ~usrp2_source_base(); +}; + +// ---------------------------------------------------------------- + +GR_SWIG_BLOCK_MAGIC(usrp2,source_32fc) + +usrp2_source_32fc_sptr +usrp2_make_source_32fc(const std::string ifc, const std::string mac) + throw (std::runtime_error); + +class usrp2_source_32fc : public usrp2_source_base { + +protected: + usrp2_source_32fc(const std::string &ifc, const std::string &mac); + +public: + ~usrp2_source_32fc(); + + bool set_gain(double gain); + %rename(_real_set_center_freq) set_center_freq; + bool set_center_freq(double frequency, usrp2::tune_result *r); + bool set_decim(int decimation_factor); + + std::string mac_addr(); +}; + +// ---------------------------------------------------------------- + +GR_SWIG_BLOCK_MAGIC(usrp2,source_16sc) + +usrp2_source_16sc_sptr +usrp2_make_source_16sc(const std::string ifc, const std::string mac) + throw (std::runtime_error); + +class usrp2_source_16sc : public usrp2_source_base { + +protected: + usrp2_source_16sc(const std::string &ifc, const std::string &mac); + +public: + ~usrp2_source_16sc(); + + bool set_gain(double gain); + %rename(_real_set_center_freq) set_center_freq; + bool set_center_freq(double frequency, usrp2::tune_result *r); + bool set_decim(int decimation_factor); + + std::string mac_addr(); +}; + +// ---------------------------------------------------------------- + +// create a more pythonic interface +%pythoncode %{ + +def __set_center_freq(self, freq): + tr = tune_result() + r = self._real_set_center_freq(freq, tr) + if r: + return tr + else: + return None + +usrp2_source_32fc_sptr.set_center_freq = __set_center_freq +usrp2_source_16sc_sptr.set_center_freq = __set_center_freq +%} diff --git a/gr-usrp2/src/usrp2_sink_32fc.cc b/gr-usrp2/src/usrp2_sink_32fc.cc new file mode 100644 index 00000000..56cde6ba --- /dev/null +++ b/gr-usrp2/src/usrp2_sink_32fc.cc @@ -0,0 +1,46 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include + +usrp2_sink_32fc_sptr +usrp2_make_sink_32fc() throw (std::runtime_error) +{ + return usrp2_sink_32fc_sptr(new usrp2_sink_32fc()); +} + +usrp2_sink_32fc::usrp2_sink_32fc() throw (std::runtime_error) + : usrp2_sink_base("usrp2_sink_32fc", + gr_make_io_signature(1, 1, sizeof(gr_complex))) +{ +} + +usrp2_sink_32fc::~usrp2_sink_32fc() +{ +} diff --git a/gr-usrp2/src/usrp2_sink_32fc.h b/gr-usrp2/src/usrp2_sink_32fc.h new file mode 100644 index 00000000..eeb80b19 --- /dev/null +++ b/gr-usrp2/src/usrp2_sink_32fc.h @@ -0,0 +1,47 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_USRP2_SINK_32FC_H +#define INCLUDED_USRP2_SINK_32FC_H + +#include + +class usrp2_sink_32fc; +typedef boost::shared_ptr usrp2_sink_32fc_sptr; + +usrp2_sink_32fc_sptr +usrp2_make_sink_32fc() throw (std::runtime_error); + +class usrp2_sink_32fc : public usrp2_sink_base { +private: + + friend usrp2_sink_32fc_sptr + usrp2_make_sink_32fc() throw (std::runtime_error); + +protected: + usrp2_sink_32fc() throw (std::runtime_error); + +public: + ~usrp2_sink_32fc(); +}; + +#endif /* INCLUDED_USRP2_SINK_32FC_H */ diff --git a/gr-usrp2/src/usrp2_sink_base.cc b/gr-usrp2/src/usrp2_sink_base.cc new file mode 100644 index 00000000..ebef9390 --- /dev/null +++ b/gr-usrp2/src/usrp2_sink_base.cc @@ -0,0 +1,49 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include + +usrp2_sink_base::usrp2_sink_base(const std::string &name, + gr_io_signature_sptr input_signature) + throw (std::runtime_error) + : gr_sync_block(name, + input_signature, + gr_make_io_signature(0, 0, 0)) +{ +} + +usrp2_sink_base::~usrp2_sink_base () +{ +} + +int +usrp2_sink_base::work(int noutput_items, + gr_vector_const_void_star &input_items, + gr_vector_void_star &output_items) +{ + return noutput_items; +} diff --git a/gr-usrp2/src/usrp2_sink_base.h b/gr-usrp2/src/usrp2_sink_base.h new file mode 100644 index 00000000..a999a6ca --- /dev/null +++ b/gr-usrp2/src/usrp2_sink_base.h @@ -0,0 +1,46 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_USRP2_SINK_BASE_H +#define INCLUDED_USRP2_SINK_BASE_H + +#include +#include + +class usrp2_sink_base : public gr_sync_block { + +private: + +protected: + usrp2_sink_base(const std::string &name, + gr_io_signature_sptr input_signature) + throw (std::runtime_error); + +public: + ~usrp2_sink_base(); + + int work(int noutput_items, + gr_vector_const_void_star &input_items, + gr_vector_void_star &output_items); +}; + +#endif /* INCLUDED_USRP2_SINK_BASE_H */ diff --git a/gr-usrp2/src/usrp2_source_16sc.cc b/gr-usrp2/src/usrp2_source_16sc.cc new file mode 100644 index 00000000..b60b61c1 --- /dev/null +++ b/gr-usrp2/src/usrp2_source_16sc.cc @@ -0,0 +1,77 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include + +#define USRP2_SOURCE_16SC_DEBUG 0 + +usrp2_source_16sc_sptr +usrp2_make_source_16sc(const std::string &ifc, const std::string &mac_addr) + throw (std::runtime_error) +{ + return usrp2_source_16sc_sptr(new usrp2_source_16sc(ifc, mac_addr)); +} + +usrp2_source_16sc::usrp2_source_16sc(const std::string &ifc, const std::string &mac_addr) + throw (std::runtime_error) + : usrp2_source_base("usrp2_source_16sc", + gr_make_io_signature(1, 1, sizeof(std::complex)), + ifc, mac_addr) +{ + set_output_multiple(USRP2_MIN_RX_SAMPLES); +} + +usrp2_source_16sc::~usrp2_source_16sc() +{ +} + +int +usrp2_source_16sc::work(int noutput_items, + gr_vector_const_void_star &input_items, + gr_vector_void_star &output_items) +{ + if (USRP2_SOURCE_16SC_DEBUG) + printf("work: noutput_items=%i\n", noutput_items); + + std::complex *out = (std::complex *)output_items[0]; + + rx_16sc_handler::sptr handler = rx_16sc_handler::make(noutput_items, USRP2_MIN_RX_SAMPLES, out); + + bool ok = d_u2->rx_samples(0, handler.get()); + if (!ok) + std::cerr << "usrp2::rx_samples() failed" << std::endl; + + int j = handler->nsamples(); + int f = handler->nframes(); + + if (USRP2_SOURCE_16SC_DEBUG) + printf("work: produced=%i items from %i frames\n\n", j, f); + + return j; +} diff --git a/gr-usrp2/src/usrp2_source_16sc.h b/gr-usrp2/src/usrp2_source_16sc.h new file mode 100644 index 00000000..fa277f73 --- /dev/null +++ b/gr-usrp2/src/usrp2_source_16sc.h @@ -0,0 +1,54 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_USRP2_SOURCE_C_H +#define INCLUDED_USRP2_SOURCE_C_H + +#include + +class usrp2_source_16sc; +typedef boost::shared_ptr usrp2_source_16sc_sptr; + +usrp2_source_16sc_sptr +usrp2_make_source_16sc(const std::string &ifc="eth0", + const std::string &mac="") + throw (std::runtime_error); + +class usrp2_source_16sc : public usrp2_source_base { + +private: + friend usrp2_source_16sc_sptr + usrp2_make_source_16sc(const std::string &ifc, + const std::string &mac) throw (std::runtime_error); + +protected: + usrp2_source_16sc(const std::string &ifc, const std::string &mac) throw (std::runtime_error); + +public: + ~usrp2_source_16sc(); + + int work(int noutput_items, + gr_vector_const_void_star &input_items, + gr_vector_void_star &output_items); +}; + +#endif /* INCLUDED_USRP2_SOURCE_16SC_H */ diff --git a/gr-usrp2/src/usrp2_source_32fc.cc b/gr-usrp2/src/usrp2_source_32fc.cc new file mode 100644 index 00000000..0d34931a --- /dev/null +++ b/gr-usrp2/src/usrp2_source_32fc.cc @@ -0,0 +1,77 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include + +#define USRP2_SOURCE_32FC_DEBUG 0 + +usrp2_source_32fc_sptr +usrp2_make_source_32fc(const std::string &ifc, const std::string &mac_addr) + throw (std::runtime_error) +{ + return usrp2_source_32fc_sptr(new usrp2_source_32fc(ifc, mac_addr)); +} + +usrp2_source_32fc::usrp2_source_32fc(const std::string &ifc, const std::string &mac_addr) + throw (std::runtime_error) + : usrp2_source_base("usrp2_source_32fc", + gr_make_io_signature(1, 1, sizeof(gr_complex)), + ifc, mac_addr) +{ + set_output_multiple(USRP2_MIN_RX_SAMPLES); +} + +usrp2_source_32fc::~usrp2_source_32fc() +{ +} + +int +usrp2_source_32fc::work(int noutput_items, + gr_vector_const_void_star &input_items, + gr_vector_void_star &output_items) +{ + if (USRP2_SOURCE_32FC_DEBUG) + printf("work: noutput_items=%i\n", noutput_items); + + gr_complex *out = (gr_complex *)output_items[0]; + + rx_32fc_handler::sptr handler = rx_32fc_handler::make(noutput_items, USRP2_MIN_RX_SAMPLES, out); + + bool ok = d_u2->rx_samples(0, handler.get()); + if (!ok) + std::cerr << "usrp2::rx_samples() failed" << std::endl; + + int j = handler->nsamples(); + int f = handler->nframes(); + + if (USRP2_SOURCE_32FC_DEBUG) + printf("work: produced=%i items from %i frames\n\n", j, f); + + return j; +} diff --git a/gr-usrp2/src/usrp2_source_32fc.h b/gr-usrp2/src/usrp2_source_32fc.h new file mode 100644 index 00000000..c6091091 --- /dev/null +++ b/gr-usrp2/src/usrp2_source_32fc.h @@ -0,0 +1,54 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_USRP2_SOURCE_32FC_H +#define INCLUDED_USRP2_SOURCE_32FC_H + +#include + +class usrp2_source_32fc; +typedef boost::shared_ptr usrp2_source_32fc_sptr; + +usrp2_source_32fc_sptr +usrp2_make_source_32fc(const std::string &ifc="eth0", + const std::string &mac="") + throw (std::runtime_error); + +class usrp2_source_32fc : public usrp2_source_base { + +private: + friend usrp2_source_32fc_sptr + usrp2_make_source_32fc(const std::string &ifc, + const std::string &mac) throw (std::runtime_error); + +protected: + usrp2_source_32fc(const std::string &ifc, const std::string &mac) throw (std::runtime_error); + +public: + ~usrp2_source_32fc(); + + int work(int noutput_items, + gr_vector_const_void_star &input_items, + gr_vector_void_star &output_items); +}; + +#endif /* INCLUDED_USRP2_SOURCE_32FC_H */ diff --git a/gr-usrp2/src/usrp2_source_base.cc b/gr-usrp2/src/usrp2_source_base.cc new file mode 100644 index 00000000..631b50c1 --- /dev/null +++ b/gr-usrp2/src/usrp2_source_base.cc @@ -0,0 +1,92 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include + +#define USRP2_SOURCE_BASE_DEBUG 0 + +usrp2_source_base::usrp2_source_base(const char *name, + gr_io_signature_sptr output_signature, + const std::string &ifc, + const std::string &mac) + throw (std::runtime_error) + : gr_sync_block(name, + gr_make_io_signature(0, 0, 0), + output_signature), + d_u2(usrp2::usrp2::sptr()) +{ + d_u2 = usrp2::usrp2::make(ifc, mac); + if (!d_u2) + throw std::runtime_error("Unable to initialize USRP2!"); +} + +usrp2_source_base::~usrp2_source_base () +{ +} + +bool +usrp2_source_base::set_gain(double gain) +{ + return d_u2->set_rx_gain(gain); +} + +bool +usrp2_source_base::set_center_freq(double frequency, usrp2::tune_result *tr) +{ + return d_u2->set_rx_center_freq(frequency, tr); +} + +bool +usrp2_source_base::set_decim(int decimation_factor) +{ + return d_u2->set_rx_decim(decimation_factor); +} + +std::string +usrp2_source_base::mac_addr() +{ + return d_u2->mac_addr(); +} + +bool +usrp2_source_base::start() +{ + if (USRP2_SOURCE_BASE_DEBUG) + printf("usrp2_source_base::start()\n"); + + return d_u2->start_rx_streaming(0); // FIXME: someday sources will have channel #s +} + +bool +usrp2_source_base::stop() +{ + if (USRP2_SOURCE_BASE_DEBUG) + printf("usrp2_source_base::stop()\n"); + + return d_u2->stop_rx_streaming(0); // FIXME: someday sources will have channel #s +} diff --git a/gr-usrp2/src/usrp2_source_base.h b/gr-usrp2/src/usrp2_source_base.h new file mode 100644 index 00000000..34d9fea0 --- /dev/null +++ b/gr-usrp2/src/usrp2_source_base.h @@ -0,0 +1,85 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_USRP2_SOURCE_BASE_H +#define INCLUDED_USRP2_SOURCE_BASE_H + +#include +#include +#include + +// BIG ASS FIXME: get from lower layer MTU calculation +#define USRP2_MIN_RX_SAMPLES 371 + +class usrp2_source_base : public gr_sync_block { + +protected: + usrp2_source_base(const char *name, + gr_io_signature_sptr output_signature, + const std::string &ifc, + const std::string &mac) + throw (std::runtime_error); + + usrp2::usrp2::sptr d_u2; + +public: + ~usrp2_source_base(); + + /*! + * \brief Set receiver gain + */ + bool set_gain(double gain); + + /*! + * \brief Set receiver center frequency + */ + bool set_center_freq(double frequency, usrp2::tune_result *tr); + + /*! + * \brief Set receive decimation rate + */ + bool set_decim(int decimation_factor); + + /*! + * \brief Get USRP2 hardware MAC address + */ + std::string mac_addr(); + + /*! + * \brief Called by scheduler when starting flowgraph + */ + bool start(); + + /*! + * \brief Called by scheduler when stopping flowgraph + */ + bool stop(); + + /*! + * \brief Derived class must override this + */ + virtual int work(int noutput_items, + gr_vector_const_void_star &input_items, + gr_vector_void_star &output_items) = 0; +}; + +#endif /* INCLUDED_USRP2_SOURCE_BASE_H */ diff --git a/gr-utils/src/python/Makefile.am b/gr-utils/src/python/Makefile.am index 6852bbe1..a48180b4 100644 --- a/gr-utils/src/python/Makefile.am +++ b/gr-utils/src/python/Makefile.am @@ -47,6 +47,8 @@ bin_SCRIPTS = \ usrp_rx_nogui.py \ usrp_siggen.py \ usrp_test_counting.py \ - usrp_test_loopback.py + usrp_test_loopback.py \ + usrp2_fft.py \ + usrp2_rx_cfile.py MOSTLYCLEANFILES = *~ *.pyc diff --git a/gr-utils/src/python/usrp2_fft.py b/gr-utils/src/python/usrp2_fft.py new file mode 100755 index 00000000..f4303f1f --- /dev/null +++ b/gr-utils/src/python/usrp2_fft.py @@ -0,0 +1,268 @@ +#!/usr/bin/env python +# +# Copyright 2004,2005,2007,2008 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru +from gnuradio import usrp2 +from gnuradio import eng_notation +from gnuradio.eng_option import eng_option +from gnuradio.wxgui import stdgui2, fftsink2, waterfallsink2, scopesink2, form, slider +from optparse import OptionParser +import wx +import sys +import numpy + +class app_top_block(stdgui2.std_top_block): + def __init__(self, frame, panel, vbox, argv): + stdgui2.std_top_block.__init__(self, frame, panel, vbox, argv) + + self.frame = frame + self.panel = panel + + parser = OptionParser(option_class=eng_option) + parser.add_option("-e", "--interface", type="string", default="eth0", + help="select Ethernet interface, default is eth0") + parser.add_option("-m", "--mac-addr", type="string", default="", + help="select USRP by MAC address, default is auto-select") + #parser.add_option("-A", "--antenna", default=None, + # help="select Rx Antenna (only on RFX-series boards)") + parser.add_option("-d", "--decim", type="int", default=16, + help="set fgpa decimation rate to DECIM [default=%default]") + parser.add_option("-f", "--freq", type="eng_float", default=None, + help="set frequency to FREQ", metavar="FREQ") + parser.add_option("-g", "--gain", type="eng_float", default=None, + help="set gain in dB (default is midpoint)") + parser.add_option("-W", "--waterfall", action="store_true", default=False, + help="Enable waterfall display") + parser.add_option("-S", "--oscilloscope", action="store_true", default=False, + help="Enable oscilloscope display") + parser.add_option("", "--avg-alpha", type="eng_float", default=1e-1, + help="Set fftsink averaging factor, default=[%default]") + parser.add_option("", "--ref-scale", type="eng_float", default=1.0, + help="Set dBFS=0dB input value, default=[%default]") + (options, args) = parser.parse_args() + if len(args) != 0: + parser.print_help() + sys.exit(1) + self.options = options + self.show_debug_info = True + + self.u = usrp2.source_32fc(options.interface, options.mac_addr) + self.u.set_decim(options.decim) + + #input_rate = self.u.adc_freq() / self.u.decim_rate() + input_rate = 100e6/options.decim + + if options.waterfall: + self.scope = \ + waterfallsink2.waterfall_sink_c (panel, fft_size=1024, sample_rate=input_rate) + elif options.oscilloscope: + self.scope = scopesink2.scope_sink_c(panel, sample_rate=input_rate) + else: + self.scope = fftsink2.fft_sink_c (panel, fft_size=1024, sample_rate=input_rate, + ref_scale=options.ref_scale, ref_level=0.0, y_divs = 10, + avg_alpha=options.avg_alpha) + + self.connect(self.u, self.scope) + + self._build_gui(vbox) + self._setup_events() + + # set initial values + + if options.gain is None: + # if no gain was specified, use the mid-point in dB + #g = self.subdev.gain_range() + #options.gain = float(g[0]+g[1])/2 + options.gain = 0 + + if options.freq is None: + # if no freq was specified, use the mid-point + #r = self.subdev.freq_range() + #options.freq = float(r[0]+r[1])/2 + options.freq = 0 + + self.set_gain(options.gain) + + #if options.antenna is not None: + # print "Selecting antenna %s" % (options.antenna,) + # self.subdev.select_rx_antenna(options.antenna) + + if self.show_debug_info: + self.myform['decim'].set_value(options.decim) + self.myform['fs@usb'].set_value(100e6/options.decim) #self.u.adc_freq() / self.u.decim_rate()) + #self.myform['dbname'].set_value(self.subdev.name()) + self.myform['baseband'].set_value(0) + self.myform['ddc'].set_value(0) + + if not(self.u.set_center_freq(options.freq)): + self._set_status_msg("Failed to set initial frequency") + + def _set_status_msg(self, msg): + self.frame.GetStatusBar().SetStatusText(msg, 0) + + def _build_gui(self, vbox): + + def _form_set_freq(kv): + return self.set_freq(kv['freq']) + + vbox.Add(self.scope.win, 10, wx.EXPAND) + + # add control area at the bottom + self.myform = myform = form.form() + hbox = wx.BoxSizer(wx.HORIZONTAL) + hbox.Add((5,0), 0, 0) + myform['freq'] = form.float_field( + parent=self.panel, sizer=hbox, label="Center freq", weight=1, + callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) + + hbox.Add((5,0), 0, 0) + #g = self.subdev.gain_range() + g = [0, 100, 1] #FIXME + myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox, label="Gain", + weight=3, + min=int(g[0]), max=int(g[1]), + callback=self.set_gain) + + hbox.Add((5,0), 0, 0) + vbox.Add(hbox, 0, wx.EXPAND) + + self._build_subpanel(vbox) + + def _build_subpanel(self, vbox_arg): + # build a secondary information panel (sometimes hidden) + + # FIXME figure out how to have this be a subpanel that is always + # created, but has its visibility controlled by foo.Show(True/False) + + def _form_set_decim(kv): + return self.set_decim(kv['decim']) + + if not(self.show_debug_info): + return + + panel = self.panel + vbox = vbox_arg + myform = self.myform + + #panel = wx.Panel(self.panel, -1) + #vbox = wx.BoxSizer(wx.VERTICAL) + + hbox = wx.BoxSizer(wx.HORIZONTAL) + hbox.Add((5,0), 0) + + myform['decim'] = form.int_field( + parent=panel, sizer=hbox, label="Decim", + callback=myform.check_input_and_call(_form_set_decim, self._set_status_msg)) + + hbox.Add((5,0), 1) + myform['fs@usb'] = form.static_float_field( + parent=panel, sizer=hbox, label="Fs@USB") + + hbox.Add((5,0), 1) + myform['dbname'] = form.static_text_field( + parent=panel, sizer=hbox) + + hbox.Add((5,0), 1) + myform['baseband'] = form.static_float_field( + parent=panel, sizer=hbox, label="Analog BB") + + hbox.Add((5,0), 1) + myform['ddc'] = form.static_float_field( + parent=panel, sizer=hbox, label="DDC") + + hbox.Add((5,0), 0) + vbox.Add(hbox, 0, wx.EXPAND) + + + def set_freq(self, target_freq): + """ + Set the center frequency we're interested in. + + @param target_freq: frequency in Hz + @rypte: bool + + Tuning is a two step process. First we ask the front-end to + tune as close to the desired frequency as it can. Then we use + the result of that operation and our target_frequency to + determine the value for the digital down converter. + """ + r = self.u.set_center_freq(target_freq) + + if r: + self.myform['freq'].set_value(target_freq) # update displayed value + if self.show_debug_info: + self.myform['baseband'].set_value(r.baseband_freq) + self.myform['ddc'].set_value(r.dxc_freq) + if not self.options.oscilloscope: + self.scope.win.set_baseband_freq(target_freq) + return True + + return False + + def set_gain(self, gain): + self.myform['gain'].set_value(gain) # update displayed value + self.u.set_gain(gain) + + def set_decim(self, decim): + ok = self.u.set_decim(decim) + if not ok: + print "set_decim failed" + #input_rate = self.u.adc_freq() / self.u.decim_rate() + input_rate = 100e6/decim # FIXME + self.scope.set_sample_rate(input_rate) + if self.show_debug_info: # update displayed values + self.myform['decim'].set_value(decim) #self.u.decim_rate()) + self.myform['fs@usb'].set_value(input_rate) #self.u.adc_freq() / self.u.decim_rate()) + return ok + + def _setup_events(self): + if not self.options.waterfall and not self.options.oscilloscope: + self.scope.win.Bind(wx.EVT_LEFT_DCLICK, self.evt_left_dclick) + + def evt_left_dclick(self, event): + (ux, uy) = self.scope.win.GetXY(event) + if event.CmdDown(): + # Re-center on maximum power + points = self.scope.win._points + if self.scope.win.peak_hold: + if self.scope.win.peak_vals is not None: + ind = numpy.argmax(self.scope.win.peak_vals) + else: + ind = int(points.shape()[0]/2) + else: + ind = numpy.argmax(points[:,1]) + (freq, pwr) = points[ind] + target_freq = freq/self.scope.win._scale_factor + print ind, freq, pwr + self.set_freq(target_freq) + else: + # Re-center on clicked frequency + target_freq = ux/self.scope.win._scale_factor + self.set_freq(target_freq) + + +def main (): + app = stdgui2.stdapp(app_top_block, "USRP2 FFT", nstatus=1) + app.MainLoop() + +if __name__ == '__main__': + main () diff --git a/gr-utils/src/python/usrp2_rx_cfile.py b/gr-utils/src/python/usrp2_rx_cfile.py new file mode 100755 index 00000000..9ab28607 --- /dev/null +++ b/gr-utils/src/python/usrp2_rx_cfile.py @@ -0,0 +1,119 @@ +#!/usr/bin/env python + +""" +Read samples from the USRP2 and write to file formatted as binary +outputs single precision complex float values or complex short values (interleaved 16 bit signed short integers). + +""" + +from gnuradio import gr, eng_notation +from gnuradio import usrp2 +from gnuradio.eng_option import eng_option +from optparse import OptionParser +import sys + +n2s = eng_notation.num_to_str + +class rx_cfile_block(gr.top_block): + + def __init__(self, options, filename): + gr.top_block.__init__(self) + + # Create a USRP2 source + if options.output_shorts: + self._u = usrp2.source_16sc(options.interface, options.mac_addr) + self._sink = gr.file_sink(gr.sizeof_short*2, filename) + else: + self._u = usrp2.source_32fc(options.interface, options.mac_addr) + self._sink = gr.file_sink(gr.sizeof_gr_complex, filename) + + # Set receiver decimation rate + self._u.set_decim(options.decim) + + # Set receive daughterboard gain + if options.gain is None: + #g = self._u.gain_range() + #options.gain = float(g[0]+g[1])/2 + options.gain = 0 # Until gain range is implemented + self._u.set_gain(options.gain) + + # Set receive frequency + tr = self._u.set_center_freq(options.freq) + if tr == None: + sys.stderr.write('Failed to set center frequency\n') + raise SystemExit, 1 + + # Create head block if needed wire it up + if options.nsamples is None: + self.connect(self._u, self._sink) + else: + if options.output_shorts: + self._head = gr.head(gr.sizeof_short*2, int(options.nsamples)) + else: + self._head = gr.head(gr.sizeof_gr_complex, int(options.nsamples)) + + self.connect(self._u, self._head, self._sink) + + #input_rate = self.u.adc_freq() / self.u.decim_rate() + input_rate = 100e6/options.decim + + if options.verbose: + print "Network interface:", options.interface + print "USRP2 address:", self._u.mac_addr() + #print "Using RX d'board %s" % (self._u.rx_name(),) + print "Rx gain:", options.gain + print "Rx baseband frequency:", n2s(tr.baseband_freq) + print "Rx DDC frequency:", n2s(tr.dxc_freq) + print "Rx residual frequency:", n2s(tr.residual_freq) + print "Rx decimation rate:", options.decim + print "Rx sample rate:", n2s(input_rate) + if options.nsamples is None: + print "Receiving samples until Ctrl-C" + else: + print "Receving", n2s(options.nsamples), "samples" + if options.output_shorts: + print "Writing 16-bit complex shorts" + else: + print "Writing 32-bit complex floats" + print "Output filename:", filename + +def get_options(): + usage="%prog: [options] output_filename" + parser = OptionParser(option_class=eng_option, usage=usage) + parser.add_option("-e", "--interface", type="string", default="eth0", + help="use specified Ethernet interface [default=%default]") + parser.add_option("-m", "--mac-addr", type="string", default="", + help="use USRP2 at specified MAC address [default=None]") + parser.add_option("-d", "--decim", type="int", default=16, + help="set fgpa decimation rate to DECIM [default=%default]") + parser.add_option("-f", "--freq", type="eng_float", default=None, + help="set frequency to FREQ", metavar="FREQ") + parser.add_option("-g", "--gain", type="eng_float", default=None, + help="set gain in dB (default is midpoint)") + parser.add_option( "-s","--output-shorts", action="store_true", default=False, + help="output interleaved shorts instead of complex floats") + parser.add_option("-N", "--nsamples", type="eng_float", default=None, + help="number of samples to collect [default=+inf]") + parser.add_option("-v", "--verbose", action="store_true", default=False, + help="verbose output") + (options, args) = parser.parse_args () + if len(args) != 1: + parser.print_help() + raise SystemExit, 1 + + if options.freq is None: + parser.print_help() + sys.stderr.write('You must specify the frequency with -f FREQ\n'); + raise SystemExit, 1 + + return (options, args[0]) + + +if __name__ == '__main__': + (options, filename) = get_options() + tb = rx_cfile_block(options, filename) + + try: + tb.run() + except KeyboardInterrupt: + pass diff --git a/usrp2/Makefile.am b/usrp2/Makefile.am new file mode 100644 index 00000000..1ea05890 --- /dev/null +++ b/usrp2/Makefile.am @@ -0,0 +1,23 @@ +# +# Copyright 2008 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +# + +include $(top_srcdir)/Makefile.common + +SUBDIRS = host diff --git a/usrp2/doc/inband-signaling-eth b/usrp2/doc/inband-signaling-eth new file mode 100644 index 00000000..f4f497be --- /dev/null +++ b/usrp2/doc/inband-signaling-eth @@ -0,0 +1,390 @@ +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + + +FIXME Needless to say, this is _very much_ a work in progress + + + +This file specifies the format of ethernet packets used for in-band data +transmission and signaling on the USRP2. + +IN packets are sent towards the host. +OUT packets are sent away from the host. + +The layout is 32-bits wide. All data is transmitted in BIG-endian +format across the ethernet. + + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Chan | mbz |I|S|E| + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Timestamp | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | | + + + + | Payload | + . . + . . + . . + | | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + + + mbz Must be Zero: these bits must be zero in both IN and OUT packets. + + I Send Immediately. Set on Tx data that should be transmitted now. + FIXME: change definition to honor 0xffffffff timestamp. + + S Start of Burst Flag: Set in an OUT packet if the data is the + first segment of what is logically a continuous burst of data. + Must be zero in IN packets. + + E End of Burst Flag: Set in an OUT packet if the data is the + last segment of what is logically a continuous burst of data. + Must be zero in IN packets. Underruns are not reported + when the FPGA runs out of samples between bursts. + + + Chan 5-bit logical channel number. Channel number 0x1f is reserved + for control information. See "Control Channel" below. Other + channels are "data channels." Each data channel is logically + independent of the others. A data channel payload field + contains a sequence of homogeneous samples. The format of the + samples is determined by the configuration associated with the + given channel. It is often the case that the payload field + contains 32-bit complex samples, each containing 16-bit real + and imaginary components. + + Timestamp: 32-bit timestamp. + + FIXME: update to reflect that the time is measured at the + time the samples inserted into or pulled out of the + DSP pipeline, not the A/D time. Using A/D time is problematic + because of group delay through filtering, etc. + + On IN packets, the timestamp indicates the time at which the + first sample of the packet was produced by the A/D converter(s) + for that channel. On OUT packets, the timestamp specifies the + time at which the first sample in the packet should go out the + D/A converter(s) for that channel. If a packet reaches the + head of the transmit queue, and the current time is later than + the timestamp, an error is assumed to have occurred and the + packet is discarded. As a special case, the timestamp + 0xffffffff is interpreted as "Now". + + The time base is a free running 32-bit counter that is + incremented by the A/D sample-clock. + + Payload: Variable length field. Length is specified by the + length of the containing ethernet frame. + + +// FIXME need to revisit this stuff + + O Overrun Flag: set in an IN packet if an overrun condition was + detected. Must be zero in OUT packets. Overrun occurs when + the FPGA has data to transmit to the host and there is no + buffer space available. This generally indicates a problem on + the host. Either it is not keeping up, or it has configured + the FPGA to transmit data at a higher rate than the transport + (USB) can support. + + U Underrun Flag: set in an IN packet if an underrun condition + was detected. Must be zero in OUT packets. Underrun occurs + when the FPGA runs out of samples, and it's not between + bursts. See the "End of Burst flag" below. + + D Dropped Packet Flag: Set in an IN packet if the FPGA + discarded an OUT packet because its timestamp had already + passed. + + + RSSI 6-bit Received Strength Signal Indicator: Must be zero in OUT + packets. In IN packets, indicates RSSI as reported by front end. + FIXME The format and interpretation are to be determined. + + + Tag 4-bit tag for matching IN packets with OUT packets. + [FIXME, write more...] + + + +"Data Channel" payload format: +------------------------------- + +If Chan != 0x1f, the packet is a "data packet" and the payload is a +sequence of homogeneous samples. The format of the samples is +determined by the configuration associated with the given channel. +It is often the case that the payload field contains 32-bit complex +samples, each containing 16-bit real and imaginary components. + + +"Control Channel" payload format: +--------------------------------- + +If Chan == 0x1f, the packet is a "control packet". The control channel +payload consists of a sequence of 0 or more sub-packets. + +Each sub-packet starts on a 32-bit boundary, and consists of an 8-bit +Opcode field, an 8-bit Length field, Length bytes of arguments, and 0, +1, 2 or 3 bytes of padding to align the tail of the sub-packet to +a 32-bit boundary. + +Control channel packets shall be processed at the head of the queue, +and shall observe the timestamp semantics described above. + + +General sub-packet format: +-------------------------- + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+ + | Opcode | Length | ... | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+ + + +Specific sub-packet formats: +---------------------------- + + RID: 8-bit Request-ID. Copied from request sub-packet into corresponding + reply sub-packet. RID allows the host to match requests and replies. + + Reg Number: 8-bit Register Number. + + + +Identify: + + Opcode: OP_ID + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 2 | RID | mbz | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +Identify Reply: + + Opcode: OP_ID_REPLY + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 50 | RID | mbz | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Mac Addr 0 | Mac Addr 1 | Mac Addr 2 | Mac Addr 3 | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Mac Addr 4 | Mac Addr 5 | H/W rev major | H/W rev minor | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Serial Num 0 | Serial Num 1 | Serial Num 2 | Serial Num 3 | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Serial Num 4 | Serial Num 5 | Serial Num 6 | Serial Num 7 | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | | + + + + | | + + FPGA MD5SUM + + | | + + + + | | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | | + + + + | | + + S/W MD5SUM + + | | + + + + | | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +Write Register: + + Opcode: OP_WRITE_REG + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 6 | mbz | Reg Number | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Register Value | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +Write Register Masked: + + Opcode: OP_WRITE_REG_MASKED + + REG[Num] = (REG[Num] & ~Mask) | (Value & Mask) + + That is, only the register bits that correspond to 1's in the + mask are written with the new value. + + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 10 | mbz | Reg Number | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Register Value | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Mask Value | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +Read Register: + + Opcode: OP_READ_REG + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 2 | RID | Reg Number | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +Read Register Reply: + + Opcode: OP_READ_REG_REPLY + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 6 | RID | Reg Number | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Register Value | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +// FIXME these may not be implemented... + +I2C Write: + + Opcode: OP_I2C_WRITE + I2C Addr: 7-bit I2C address + Data: The bytes to write to the I2C bus + Length: Length of Data + 2 + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | Length | RID | I2C Addr | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Data ... . + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +I2C Write Reply: + + Opcode: OP_I2C_WRITE_REPLY + Length: 2 + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 2 | RID | OK | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +OK is 1 if successful, else 0. + + +I2C Read: + + Opcode: OP_I2C_READ + I2C Addr: 7-bit I2C address + Nbytes: Number of bytes to read from I2C bus + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 3 | RID | I2C Addr | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Nbytes | unspecified padding | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +I2C Read Reply: + + Opcode: OP_I2C_READ_REPLY + I2C Addr: 7-bit I2C address + Data: Length - 2 bytes of data read from I2C bus. + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | Length | RID | OK | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Data ... . + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + +OK is 1 if successful, else 0 + + +SPI Write: + + Opcode: OP_SPI_WRITE + Enables: Which SPI enables to assert (mask) + Format: Specifies format of SPI data and Opt Header Bytes + Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format + Data: The bytes to write to the SPI bus + Length: Length of Data + 6 + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | Length | RID | mbz | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Enables | Format | Opt Header Bytes | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Data ... . + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +SPI Write Reply: + + Opcode: OP_SPI_WRITE_REPLY + Length: 2 + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 2 | RID | OK | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +OK is 1 if successful, else 0. + + +SPI Read: + + Opcode: OP_SPI_READ + Enables: Which SPI enables to assert (mask) + Format: Specifies format of SPI data and Opt Header Bytes + Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format + Nbytes: Number of bytes to read from SPI bus. + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 7 | RID | mbz | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Enables | Format | Opt Header Bytes | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Nbytes | unspecified padding | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +SPI Read Reply: + + Opcode: OP_SPI_READ_REPLY + Data: Length - 2 bytes of data read from SPI bus. + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | Length | RID | mbz | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Data ... . + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + +Delay: + + Opcode: OP_DELAY + Ticks: 16-bit unsigned delay count + + Delay Ticks clock ticks before executing next operation. + + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | Opcode | 2 | Ticks | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + diff --git a/usrp2/firmware/AUTHORS b/usrp2/firmware/AUTHORS new file mode 100644 index 00000000..6bd41174 --- /dev/null +++ b/usrp2/firmware/AUTHORS @@ -0,0 +1,2 @@ +Eric Blossom +Matt Ettus diff --git a/usrp2/firmware/COPYING b/usrp2/firmware/COPYING new file mode 100644 index 00000000..94a9ed02 --- /dev/null +++ b/usrp2/firmware/COPYING @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Interpretation of Sections 15 and 16. + + If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/usrp2/firmware/ChangeLog b/usrp2/firmware/ChangeLog new file mode 100644 index 00000000..3154fc43 --- /dev/null +++ b/usrp2/firmware/ChangeLog @@ -0,0 +1,22 @@ +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +# + +Please use the trac interface to see what's changed. +http://gnuradio.org/trac/timeline diff --git a/usrp2/firmware/INSTALL b/usrp2/firmware/INSTALL new file mode 100644 index 00000000..5458714e --- /dev/null +++ b/usrp2/firmware/INSTALL @@ -0,0 +1,234 @@ +Installation Instructions +************************* + +Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005, +2006 Free Software Foundation, Inc. + +This file is free documentation; the Free Software Foundation gives +unlimited permission to copy, distribute and modify it. + +Basic Installation +================== + +Briefly, the shell commands `./configure; make; make install' should +configure, build, and install this package. The following +more-detailed instructions are generic; see the `README' file for +instructions specific to this package. + + The `configure' shell script attempts to guess correct values for +various system-dependent variables used during compilation. It uses +those values to create a `Makefile' in each directory of the package. +It may also create one or more `.h' files containing system-dependent +definitions. Finally, it creates a shell script `config.status' that +you can run in the future to recreate the current configuration, and a +file `config.log' containing compiler output (useful mainly for +debugging `configure'). + + It can also use an optional file (typically called `config.cache' +and enabled with `--cache-file=config.cache' or simply `-C') that saves +the results of its tests to speed up reconfiguring. Caching is +disabled by default to prevent problems with accidental use of stale +cache files. + + If you need to do unusual things to compile the package, please try +to figure out how `configure' could check whether to do them, and mail +diffs or instructions to the address given in the `README' so they can +be considered for the next release. If you are using the cache, and at +some point `config.cache' contains results you don't want to keep, you +may remove or edit it. + + The file `configure.ac' (or `configure.in') is used to create +`configure' by a program called `autoconf'. You need `configure.ac' if +you want to change it or regenerate `configure' using a newer version +of `autoconf'. + +The simplest way to compile this package is: + + 1. `cd' to the directory containing the package's source code and type + `./configure' to configure the package for your system. + + Running `configure' might take a while. While running, it prints + some messages telling which features it is checking for. + + 2. Type `make' to compile the package. + + 3. Optionally, type `make check' to run any self-tests that come with + the package. + + 4. Type `make install' to install the programs and any data files and + documentation. + + 5. You can remove the program binaries and object files from the + source code directory by typing `make clean'. To also remove the + files that `configure' created (so you can compile the package for + a different kind of computer), type `make distclean'. There is + also a `make maintainer-clean' target, but that is intended mainly + for the package's developers. If you use it, you may have to get + all sorts of other programs in order to regenerate files that came + with the distribution. + +Compilers and Options +===================== + +Some systems require unusual options for compilation or linking that the +`configure' script does not know about. Run `./configure --help' for +details on some of the pertinent environment variables. + + You can give `configure' initial values for configuration parameters +by setting variables in the command line or in the environment. Here +is an example: + + ./configure CC=c99 CFLAGS=-g LIBS=-lposix + + *Note Defining Variables::, for more details. + +Compiling For Multiple Architectures +==================================== + +You can compile the package for more than one kind of computer at the +same time, by placing the object files for each architecture in their +own directory. To do this, you can use GNU `make'. `cd' to the +directory where you want the object files and executables to go and run +the `configure' script. `configure' automatically checks for the +source code in the directory that `configure' is in and in `..'. + + With a non-GNU `make', it is safer to compile the package for one +architecture at a time in the source code directory. After you have +installed the package for one architecture, use `make distclean' before +reconfiguring for another architecture. + +Installation Names +================== + +By default, `make install' installs the package's commands under +`/usr/local/bin', include files under `/usr/local/include', etc. You +can specify an installation prefix other than `/usr/local' by giving +`configure' the option `--prefix=PREFIX'. + + You can specify separate installation prefixes for +architecture-specific files and architecture-independent files. If you +pass the option `--exec-prefix=PREFIX' to `configure', the package uses +PREFIX as the prefix for installing programs and libraries. +Documentation and other data files still use the regular prefix. + + In addition, if you use an unusual directory layout you can give +options like `--bindir=DIR' to specify different values for particular +kinds of files. Run `configure --help' for a list of the directories +you can set and what kinds of files go in them. + + If the package supports it, you can cause programs to be installed +with an extra prefix or suffix on their names by giving `configure' the +option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'. + +Optional Features +================= + +Some packages pay attention to `--enable-FEATURE' options to +`configure', where FEATURE indicates an optional part of the package. +They may also pay attention to `--with-PACKAGE' options, where PACKAGE +is something like `gnu-as' or `x' (for the X Window System). The +`README' should mention any `--enable-' and `--with-' options that the +package recognizes. + + For packages that use the X Window System, `configure' can usually +find the X include and library files automatically, but if it doesn't, +you can use the `configure' options `--x-includes=DIR' and +`--x-libraries=DIR' to specify their locations. + +Specifying the System Type +========================== + +There may be some features `configure' cannot figure out automatically, +but needs to determine by the type of machine the package will run on. +Usually, assuming the package is built to be run on the _same_ +architectures, `configure' can figure that out, but if it prints a +message saying it cannot guess the machine type, give it the +`--build=TYPE' option. TYPE can either be a short name for the system +type, such as `sun4', or a canonical name which has the form: + + CPU-COMPANY-SYSTEM + +where SYSTEM can have one of these forms: + + OS KERNEL-OS + + See the file `config.sub' for the possible values of each field. If +`config.sub' isn't included in this package, then this package doesn't +need to know the machine type. + + If you are _building_ compiler tools for cross-compiling, you should +use the option `--target=TYPE' to select the type of system they will +produce code for. + + If you want to _use_ a cross compiler, that generates code for a +platform different from the build platform, you should specify the +"host" platform (i.e., that on which the generated programs will +eventually be run) with `--host=TYPE'. + +Sharing Defaults +================ + +If you want to set default values for `configure' scripts to share, you +can create a site shell script called `config.site' that gives default +values for variables like `CC', `cache_file', and `prefix'. +`configure' looks for `PREFIX/share/config.site' if it exists, then +`PREFIX/etc/config.site' if it exists. Or, you can set the +`CONFIG_SITE' environment variable to the location of the site script. +A warning: not all `configure' scripts look for a site script. + +Defining Variables +================== + +Variables not defined in a site shell script can be set in the +environment passed to `configure'. However, some packages may run +configure again during the build, and the customized values of these +variables may be lost. In order to avoid this problem, you should set +them in the `configure' command line, using `VAR=value'. For example: + + ./configure CC=/usr/local2/bin/gcc + +causes the specified `gcc' to be used as the C compiler (unless it is +overridden in the site shell script). + +Unfortunately, this technique does not work for `CONFIG_SHELL' due to +an Autoconf bug. Until the bug is fixed you can use this workaround: + + CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash + +`configure' Invocation +====================== + +`configure' recognizes the following options to control how it operates. + +`--help' +`-h' + Print a summary of the options to `configure', and exit. + +`--version' +`-V' + Print the version of Autoconf used to generate the `configure' + script, and exit. + +`--cache-file=FILE' + Enable the cache: use and save the results of the tests in FILE, + traditionally `config.cache'. FILE defaults to `/dev/null' to + disable caching. + +`--config-cache' +`-C' + Alias for `--cache-file=config.cache'. + +`--quiet' +`--silent' +`-q' + Do not print messages saying which checks are being made. To + suppress all normal output, redirect it to `/dev/null' (any error + messages will still be shown). + +`--srcdir=DIR' + Look for the package's source code in directory DIR. Usually + `configure' can determine that directory automatically. + +`configure' also accepts some other, not widely useful, options. Run +`configure --help' for more details. + diff --git a/usrp2/firmware/Makefile.am b/usrp2/firmware/Makefile.am new file mode 100644 index 00000000..437f2322 --- /dev/null +++ b/usrp2/firmware/Makefile.am @@ -0,0 +1,21 @@ +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include $(top_srcdir)/Makefile.common + +SUBDIRS = include lib apps + diff --git a/usrp2/firmware/Makefile.common b/usrp2/firmware/Makefile.common new file mode 100644 index 00000000..f2f8f7d6 --- /dev/null +++ b/usrp2/firmware/Makefile.common @@ -0,0 +1,59 @@ +# -*- Makefile -*- +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +STD_INCLUDES = -I$(top_srcdir)/include -I$(top_srcdir)/lib + +#HAL_IO = -DHAL_IO_USES_DBOARD_PINS +HAL_IO = -DHAL_IO_USES_UART + +AM_CPPFLAGS = $(HAL_IO) $(STD_INCLUDES) + +STD_CFLAGS = -O2 -g -Wall -Werror-implicit-function-declaration -mxl-soft-div -msoft-float + +#AM_CFLAGS = $(STD_CFLAGS) -mxl-soft-mul +AM_CFLAGS = $(STD_CFLAGS) -mxl-soft-mul -mxl-barrel-shift +#AM_CFLAGS = $(STD_CFLAGS) -mno-xl-soft-mul +#AM_CFLAGS = $(STD_CFLAGS) -mno-xl-soft-mul -mxl-barrel-shift + + +LINKER_SCRIPT = $(top_srcdir)/lib/microblaze.ld +#AM_LDFLAGS = -Wl,-T$(LINKER_SCRIPT) -Wl,-defsym -Wl,_STACK_SIZE=1024 +#AM_LDFLAGS = -Wl,-T$(LINKER_SCRIPT) -Wl,-Map -Wl,$@.map +AM_LDFLAGS = -Wl,-T$(LINKER_SCRIPT) + + +%.bin : % + mb-objcopy -O binary $< $@ + +%.dump : % + mb-objdump -DSC $< > $@ + +%.rom : %.bin + hexdump -v -e'1/1 "%.2X\n"' $< > $@ + + +.PRECIOUS : %.bin + + +BINS = $(noinst_PROGRAMS:=.bin) +ROMS = $(noinst_PROGRAMS:=.rom) +DUMPS = $(noinst_PROGRAMS:=.dump) + +noinst_DATA = $(BINS) $(ROMS) $(DUMPS) + +CLEANFILES = $(ROMS) $(DUMPS) $(BINS) diff --git a/usrp2/firmware/NEWS b/usrp2/firmware/NEWS new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/firmware/README b/usrp2/firmware/README new file mode 100644 index 00000000..8b72bf9c --- /dev/null +++ b/usrp2/firmware/README @@ -0,0 +1,5 @@ +Stay tuned for additional info as it becomes available ... + + $ ./bootstrap + $ ./configure + $ make diff --git a/usrp2/firmware/apps/Makefile.am b/usrp2/firmware/apps/Makefile.am new file mode 100644 index 00000000..092dd944 --- /dev/null +++ b/usrp2/firmware/apps/Makefile.am @@ -0,0 +1,63 @@ +# +# Copyright 2007,2008 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include $(top_srcdir)/Makefile.common + +LDADD = ../lib/libu2fw.a + +noinst_PROGRAMS = \ + blink_leds \ + blink_leds2 \ + buf_ram_test \ + can_i_sub \ + echo \ + eth_serdes \ + gen_eth_packets \ + hello \ + ibs_rx_test \ + ibs_tx_test \ + rcv_eth_packets \ + rx_only_v2 \ + read_dbids \ + test1 \ + test_db_spi \ + test_i2c \ + test_phy_comm \ + test_lsadc \ + test_lsdac \ + test_serdes \ + timer_test \ + tx_only_v2 \ + tx_standalone \ + txrx \ + serdes_txrx \ + sd_gentest \ + sd_bounce + + +# tx_drop_SOURCES = tx_drop.c app_common.c +# tx_drop_rate_limited_SOURCES = tx_drop_rate_limited.c app_common.c +# tx_drop2_SOURCES = tx_drop2.c app_common.c +rx_only_v2_SOURCES = rx_only_v2.c app_common_v2.c +tx_only_v2_SOURCES = tx_only_v2.c app_common_v2.c +txrx_SOURCES = txrx.c app_common_v2.c +eth_serdes_SOURCES = eth_serdes.c app_passthru_v2.c +serdes_txrx_SOURCES = serdes_txrx.c app_common_v2.c + +noinst_HEADERS = \ + app_common_v2.h \ + app_passthru_v2.h diff --git a/usrp2/firmware/apps/app_common_v2.c b/usrp2/firmware/apps/app_common_v2.c new file mode 100644 index 00000000..4dc254f8 --- /dev/null +++ b/usrp2/firmware/apps/app_common_v2.c @@ -0,0 +1,477 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "app_common_v2.h" +#include "buffer_pool.h" +#include "memcpy_wa.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "print_rmon_regs.h" +#include "db.h" +#include "clocks.h" +#include + +volatile bool link_is_up = false; // eth handler sets this +int cpu_tx_buf_dest_port = PORT_ETH; + +// If this is non-zero, this dbsm could be writing to the ethernet +dbsm_t *ac_could_be_sending_to_eth; + +static unsigned char exp_seqno __attribute__((unused)) = 0; + + +static bool +burn_mac_addr(const op_burn_mac_addr_t *p) +{ + return ethernet_set_mac_addr(&p->addr); +} + +static bool +config_mimo_cmd(const op_config_mimo_t *p) +{ + clocks_mimo_config(p->flags); + return true; +} + +void +set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt) +{ + reply_pkt->ehdr.dst = cmd_pkt->ehdr.src; + reply_pkt->ehdr.ethertype = U2_ETHERTYPE; + reply_pkt->thdr.flags = 0; + reply_pkt->thdr.fifo_status = 0; // written by protocol engine + reply_pkt->thdr.seqno = 0; // written by protocol engine + reply_pkt->thdr.ack = 0; // written by protocol engine + u2p_set_word0(&reply_pkt->fixed, 0, CONTROL_CHAN); + reply_pkt->fixed.timestamp = timer_regs->time; +} + +static void +send_reply(unsigned char *reply, size_t reply_len) +{ + if (reply_len < 64) + reply_len = 64; + + // wait for buffer to become idle + hal_set_leds(0x4, 0x4); + while((buffer_pool_status->status & BPS_IDLE(CPU_TX_BUF)) == 0) + ; + hal_set_leds(0x0, 0x4); + + // copy reply into CPU_TX_BUF + memcpy_wa(buffer_ram(CPU_TX_BUF), reply, reply_len); + + // wait until nobody else is sending to the ethernet + if (ac_could_be_sending_to_eth){ + hal_set_leds(0x8, 0x8); + dbsm_wait_for_opening(ac_could_be_sending_to_eth); + hal_set_leds(0x0, 0x8); + } + + if (0){ + printf("sending_reply to port %d, len = %d\n", cpu_tx_buf_dest_port, reply_len); + print_buffer(buffer_ram(CPU_TX_BUF), reply_len/4); + } + + // fire it off + bp_send_from_buf(CPU_TX_BUF, cpu_tx_buf_dest_port, 1, 0, reply_len/4); + + // wait for it to complete (not long, it's a small pkt) + while((buffer_pool_status->status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))) == 0) + ; + + bp_clear_buf(CPU_TX_BUF); +} + + +static size_t +op_id_cmd(const op_generic_t *p, + void *reply_payload, size_t reply_payload_space) +{ + op_id_reply_t *r = (op_id_reply_t *) reply_payload; + if (reply_payload_space < sizeof(*r)) // no room + return 0; + + // Build reply subpacket + + r->opcode = OP_ID_REPLY; + r->len = sizeof(op_id_reply_t); + r->rid = p->rid; + r->addr = *ethernet_mac_addr(); + r->hw_rev = 0x0000; // FIXME + // r->fpga_md5sum = ; // FIXME + // r->sw_md5sum = ; // FIXME + + // FIXME Add d'board info, including dbid, min/max gain, min/max freq + + return r->len; +} + + +static size_t +config_tx_v2_cmd(const op_config_tx_v2_t *p, + void *reply_payload, size_t reply_payload_space) +{ + op_config_tx_reply_v2_t *r = (op_config_tx_reply_v2_t *) reply_payload; + if (reply_payload_space < sizeof(*r)) + return 0; // no room + + struct tune_result tune_result; + memset(&tune_result, 0, sizeof(tune_result)); + + bool ok = true; + + if (p->valid & CFGV_GAIN){ + ok &= db_set_gain(tx_dboard, p->gain); + } + + if (p->valid & CFGV_FREQ){ + u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo); + bool tune_ok = db_tune(tx_dboard, f, &tune_result); + ok &= tune_ok; + print_tune_result("Tx", tune_ok, f, &tune_result); + } + + if (p->valid & CFGV_INTERP_DECIM){ + int interp = p->interp; + int hb1 = 0; + int hb2 = 0; + + if (!(interp & 1)){ + hb2 = 1; + interp = interp >> 1; + } + + if (!(interp & 1)){ + hb1 = 1; + interp = interp >> 1; + } + + if (p->interp < MIN_INTERP || p->interp > MAX_INTERP) + ok = false; + else { + dsp_tx_regs->interp_rate = (hb1<<9) | (hb2<<8) | interp; + // printf("Interp: %d, register %d\n", p->interp, (hb1<<9) | (hb2<<8) | interp); + } + } + + if (p->valid & CFGV_SCALE_IQ){ + dsp_tx_regs->scale_iq = p->scale_iq; + } + + // Build reply subpacket + + r->opcode = OP_CONFIG_TX_REPLY_V2; + r->len = sizeof(*r); + r->rid = p->rid; + r->ok = ok; + r->inverted = tune_result.inverted; + r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq); + r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq); + r->duc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq); + r->duc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq); + r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq); + r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq); + return r->len; +} + +static size_t +config_rx_v2_cmd(const op_config_rx_v2_t *p, + void *reply_payload, size_t reply_payload_space) +{ + op_config_rx_reply_v2_t *r = (op_config_rx_reply_v2_t *) reply_payload; + if (reply_payload_space < sizeof(*r)) + return 0; // no room + + struct tune_result tune_result; + memset(&tune_result, 0, sizeof(tune_result)); + + bool ok = true; + + if (p->valid & CFGV_GAIN){ + ok &= db_set_gain(rx_dboard, p->gain); + } + + if (p->valid & CFGV_FREQ){ + u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo); + bool tune_ok = db_tune(rx_dboard, f, &tune_result); + ok &= tune_ok; + print_tune_result("Rx", tune_ok, f, &tune_result); + } + + if (p->valid & CFGV_INTERP_DECIM){ + int decim = p->decim; + int hb1 = 0; + int hb2 = 0; + + if(!(decim & 1)) { + hb2 = 1; + decim = decim >> 1; + } + + if(!(decim & 1)) { + hb1 = 1; + decim = decim >> 1; + } + + if (decim < MIN_DECIM || decim > MAX_DECIM) + ok = false; + else { + dsp_rx_regs->decim_rate = (hb1<<9) | (hb2<<8) | decim; + // printf("Decim: %d, register %d\n", p->decim, (hb1<<9) | (hb2<<8) | decim); + } + } + + if (p->valid & CFGV_SCALE_IQ){ + dsp_rx_regs->scale_iq = p->scale_iq; + } + + // Build reply subpacket + + r->opcode = OP_CONFIG_RX_REPLY_V2; + r->len = sizeof(*r); + r->rid = p->rid; + r->ok = ok; + r->inverted = tune_result.inverted; + r->baseband_freq_hi = u2_fxpt_freq_hi(tune_result.baseband_freq); + r->baseband_freq_lo = u2_fxpt_freq_lo(tune_result.baseband_freq); + r->ddc_freq_hi = u2_fxpt_freq_hi(tune_result.dxc_freq); + r->ddc_freq_lo = u2_fxpt_freq_lo(tune_result.dxc_freq); + r->residual_freq_hi = u2_fxpt_freq_hi(tune_result.residual_freq); + r->residual_freq_lo = u2_fxpt_freq_lo(tune_result.residual_freq); + + return r->len; +} + +static size_t +read_time_cmd(const op_generic_t *p, + void *reply_payload, size_t reply_payload_space) +{ + op_read_time_reply_t *r = (op_read_time_reply_t *) reply_payload; + if (reply_payload_space < sizeof(*r)) + return 0; // no room + + r->opcode = OP_READ_TIME_REPLY; + r->len = sizeof(*r); + r->rid = p->rid; + r->time = timer_regs->time; + + return r->len; +} + +static size_t +generic_reply(const op_generic_t *p, + void *reply_payload, size_t reply_payload_space, + bool ok) +{ + op_generic_t *r = (op_generic_t *) reply_payload; + if (reply_payload_space < sizeof(*r)) + return 0; // no room + + r->opcode = p->opcode | OP_REPLY_BIT; + r->len = sizeof(*r); + r->rid = p->rid; + r->ok = ok; + + return r->len; +} + +static size_t +add_eop(void *reply_payload, size_t reply_payload_space) +{ + op_generic_t *r = (op_generic_t *) reply_payload; + if (reply_payload_space < sizeof(*r)) + return 0; // no room + + r->opcode = OP_EOP; + r->len = sizeof(*r); + r->rid = 0; + r->ok = 0; + + return r->len; +} + +void +handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len) +{ + unsigned char reply[sizeof(u2_eth_packet_t) + 4 * sizeof(u2_subpkt_t)] _AL4; + unsigned char *reply_payload = &reply[sizeof(u2_eth_packet_t)]; + int reply_payload_space = sizeof(reply) - sizeof(u2_eth_packet_t); + + // initialize reply + memset(reply, 0, sizeof(reply)); + set_reply_hdr((u2_eth_packet_t *) reply, pkt); + + // point to beginning of payload (subpackets) + unsigned char *payload = ((unsigned char *) pkt) + sizeof(u2_eth_packet_t); + int payload_len = len - sizeof(u2_eth_packet_t); + + size_t subpktlen = 0; + + while (payload_len >= sizeof(op_generic_t)){ + const op_generic_t *gp = (const op_generic_t *) payload; + subpktlen = 0; + + switch(gp->opcode){ + case OP_EOP: // end of subpackets + goto end_of_subpackets; + + case OP_ID: + subpktlen = op_id_cmd(gp, reply_payload, reply_payload_space); + break; + + case OP_CONFIG_TX_V2: + subpktlen = config_tx_v2_cmd((op_config_tx_v2_t *) payload, + reply_payload, reply_payload_space); + break; + + case OP_CONFIG_RX_V2: + subpktlen = config_rx_v2_cmd((op_config_rx_v2_t *) payload, + reply_payload, reply_payload_space); + break; + + case OP_START_RX_STREAMING: + start_rx_streaming_cmd(&pkt->ehdr.src, (op_start_rx_streaming_t *) payload); + subpktlen = generic_reply(gp, reply_payload, reply_payload_space, true); + break; + + case OP_STOP_RX: + stop_rx_cmd(); + subpktlen = generic_reply(gp, reply_payload, reply_payload_space, true); + break; + + case OP_BURN_MAC_ADDR: + subpktlen = generic_reply(gp, reply_payload, reply_payload_space, + burn_mac_addr((op_burn_mac_addr_t *) payload)); + break; + + case OP_CONFIG_MIMO: + subpktlen = generic_reply(gp, reply_payload, reply_payload_space, + config_mimo_cmd((op_config_mimo_t *) payload)); + break; + + case OP_READ_TIME: + subpktlen = read_time_cmd(gp, reply_payload, reply_payload_space); + break; + + default: + printf("app_common_v2: unhandled opcode = %d\n", gp->opcode); + break; + } + + int t = (gp->len + 3) & ~3; // bump to a multiple of 4 + payload += t; + payload_len -= t; + + subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4 + reply_payload += subpktlen; + reply_payload_space -= subpktlen; + } + + end_of_subpackets: + + // add the EOP marker + subpktlen = add_eop(reply_payload, reply_payload_space); + subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4 + reply_payload += subpktlen; + reply_payload_space -= subpktlen; + + send_reply(reply, reply_payload - reply); +} + + +/* + * Called when an ethernet packet is received. + * Return true if we handled it here, otherwise + * it'll be passed on to the DSP Tx pipe + */ +bool +eth_pkt_inspector(dbsm_t *sm, int bufno) +{ + u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno); + size_t byte_len = (buffer_pool_status->last_line[bufno] - 3) * 4; + + //static size_t last_len = 0; + + // hal_toggle_leds(0x1); + + // inspect rcvd frame and figure out what do do. + + if (pkt->ehdr.ethertype != U2_ETHERTYPE) + return true; // ignore, probably bogus PAUSE frame from MAC + + int chan = u2p_chan(&pkt->fixed); + + switch (chan){ + case CONTROL_CHAN: + handle_control_chan_frame(pkt, byte_len); + return true; // we handled the packet + break; + + case 0: + default: +#if 0 + if (last_len != 0){ + if (byte_len != last_len){ + printf("Len: %d last: %d\n", byte_len, last_len); + } + } + last_len = byte_len; + + if((pkt->thdr.seqno) == exp_seqno){ + exp_seqno++; + //putchar('.'); + } + else { + // putchar('S'); + //printf("S%d %d ",exp_seqno,pkt->thdr.seqno); + exp_seqno = pkt->thdr.seqno + 1; + } +#endif + return false; // pass it on to Tx DSP + break; + } +} + +/* + * Called when eth phy state changes (w/ interrupts disabled) + */ +void +link_changed_callback(int speed) +{ + link_is_up = speed != 0; + hal_set_leds(link_is_up ? 0x20 : 0x0, 0x20); + printf("\neth link changed: speed = %d\n", speed); +} + + +void +print_tune_result(char *msg, bool tune_ok, + u2_fxpt_freq_t target_freq, struct tune_result *r) +{ + printf("db_tune %s %s\n", msg, tune_ok ? "true" : "false"); + putstr(" target_freq "); print_fxpt_freq(target_freq); newline(); + putstr(" baseband_freq "); print_fxpt_freq(r->baseband_freq); newline(); + putstr(" dxc_freq "); print_fxpt_freq(r->dxc_freq); newline(); + putstr(" residual_freq "); print_fxpt_freq(r->residual_freq); newline(); + printf(" inverted %s\n", r->inverted ? "true" : "false"); +} diff --git a/usrp2/firmware/apps/app_common_v2.h b/usrp2/firmware/apps/app_common_v2.h new file mode 100644 index 00000000..30f54876 --- /dev/null +++ b/usrp2/firmware/apps/app_common_v2.h @@ -0,0 +1,62 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_APP_COMMON_H +#define INCLUDED_APP_COMMON_H + +#include "bool.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "memory_map.h" +#include "hal_io.h" +#include +#include + +#define CPU_TX_BUF 1 // cpu -> eth + +#define _AL4 __attribute__((aligned (4))) + +extern volatile bool link_is_up; // eth handler sets this + +// If there's a dbsm that sends to the ethernet, put it's address here +extern dbsm_t *ac_could_be_sending_to_eth; + +extern int cpu_tx_buf_dest_port; + +void set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt); + +/* + * Called when an ethernet packet is received. + * Return true if we handled it here, otherwise + * it'll be passed on to the DSP Tx pipe + */ +bool eth_pkt_inspector(dbsm_t *sm, int bufno); + +void link_changed_callback(int speed); + +void +print_tune_result(char *msg, bool tune_ok, + u2_fxpt_freq_t target_freq, struct tune_result *r); + + +void start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p); +void stop_rx_cmd(void); + +void handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len); + +#endif /* INCLUDED_APP_COMMON_H */ diff --git a/usrp2/firmware/apps/app_passthru_v2.c b/usrp2/firmware/apps/app_passthru_v2.c new file mode 100644 index 00000000..1689e8b7 --- /dev/null +++ b/usrp2/firmware/apps/app_passthru_v2.c @@ -0,0 +1,244 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "app_passthru_v2.h" +#include "buffer_pool.h" +#include "memcpy_wa.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "print_rmon_regs.h" +#include "db.h" +#include "clocks.h" +#include + +volatile bool link_is_up = false; // eth handler sets this + + +// If this is non-zero, this dbsm could be writing to the ethernet +dbsm_t *ac_could_be_sending_to_eth; + +//static unsigned char exp_seqno = 0; + +void +set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt) +{ + reply_pkt->ehdr.dst = cmd_pkt->ehdr.src; + reply_pkt->ehdr.ethertype = U2_ETHERTYPE; + reply_pkt->thdr.flags = 0; + reply_pkt->thdr.fifo_status = 0; // written by protocol engine + reply_pkt->thdr.seqno = 0; // written by protocol engine + reply_pkt->thdr.ack = 0; // written by protocol engine + u2p_set_word0(&reply_pkt->fixed, 0, CONTROL_CHAN); + reply_pkt->fixed.timestamp = timer_regs->time; +} + +static void +send_reply(unsigned char *reply, size_t reply_len) +{ + if (reply_len < 64) + reply_len = 64; + + // wait for buffer to become idle + hal_set_leds(0x4, 0x4); + while((buffer_pool_status->status & BPS_IDLE(CPU_TX_BUF)) == 0) + ; + hal_set_leds(0x0, 0x4); + + // copy reply into CPU_TX_BUF + memcpy_wa(buffer_ram(CPU_TX_BUF), reply, reply_len); + + // wait until nobody else is sending to the ethernet + if (ac_could_be_sending_to_eth){ + hal_set_leds(0x8, 0x8); + dbsm_wait_for_opening(ac_could_be_sending_to_eth); + hal_set_leds(0x0, 0x8); + } + + // fire it off + bp_send_from_buf(CPU_TX_BUF, PORT_ETH, 1, 0, reply_len/4); + + // wait for it to complete (not long, it's a small pkt) + while((buffer_pool_status->status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))) == 0) + ; + + bp_clear_buf(CPU_TX_BUF); +} + + +static size_t +op_id_cmd(const op_generic_t *p, + void *reply_payload, size_t reply_payload_space) +{ + op_id_reply_t *r = (op_id_reply_t *) reply_payload; + if (reply_payload_space < sizeof(*r)) // no room + return 0; + + // Build reply subpacket + + r->opcode = OP_ID_REPLY; + r->len = sizeof(op_id_reply_t); + r->rid = p->rid; + r->addr = *ethernet_mac_addr(); + r->hw_rev = 0x0000; // FIXME + // r->fpga_md5sum = ; // FIXME + // r->sw_md5sum = ; // FIXME + + // FIXME Add d'board info, including dbid, min/max gain, min/max freq + + return r->len; +} + +static size_t +add_eop(void *reply_payload, size_t reply_payload_space) +{ + op_generic_t *r = (op_generic_t *) reply_payload; + if (reply_payload_space < sizeof(*r)) + return 0; // no room + + r->opcode = OP_EOP; + r->len = sizeof(*r); + r->rid = 0; + r->ok = 0; + + return r->len; +} + +bool +handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len) +{ + unsigned char reply[sizeof(u2_eth_packet_t) + 4 * sizeof(u2_subpkt_t)] _AL4; + unsigned char *reply_payload = &reply[sizeof(u2_eth_packet_t)]; + int reply_payload_space = sizeof(reply) - sizeof(u2_eth_packet_t); + + bool handled_it = false; + + // initialize reply + memset(reply, 0, sizeof(reply)); + set_reply_hdr((u2_eth_packet_t *) reply, pkt); + + // point to beginning of payload (subpackets) + unsigned char *payload = ((unsigned char *) pkt) + sizeof(u2_eth_packet_t); + int payload_len = len - sizeof(u2_eth_packet_t); + + size_t subpktlen = 0; + + while (payload_len >= sizeof(op_generic_t)){ + const op_generic_t *gp = (const op_generic_t *) payload; + subpktlen = 0; + + switch(gp->opcode){ + case OP_EOP: // end of subpackets + goto end_of_subpackets; + + case OP_ID: + subpktlen = op_id_cmd(gp, reply_payload, reply_payload_space); + handled_it = true; + break; + } + + int t = (gp->len + 3) & ~3; // bump to a multiple of 4 + payload += t; + payload_len -= t; + + subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4 + reply_payload += subpktlen; + reply_payload_space -= subpktlen; + } + + end_of_subpackets: + + if (handled_it){ + // add the EOP marker + subpktlen = add_eop(reply_payload, reply_payload_space); + subpktlen = (subpktlen + 3) & ~3; // bump to a multiple of 4 + reply_payload += subpktlen; + reply_payload_space -= subpktlen; + + send_reply(reply, reply_payload - reply); + } + + return handled_it; +} + + +/* + * Called when an ethernet packet is received. + * Return true if we handled it here, otherwise + * it'll be passed on to the DSP Tx pipe + */ +bool +eth_pkt_inspector(dbsm_t *sm, int bufno) +{ + u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno); + size_t byte_len = (buffer_pool_status->last_line[bufno] - 3) * 4; + + //static size_t last_len = 0; + + // hal_toggle_leds(0x1); + + // inspect rcvd frame and figure out what do do. + + if (pkt->ehdr.ethertype != U2_ETHERTYPE) + return true; // ignore, probably bogus PAUSE frame from MAC + + int chan = u2p_chan(&pkt->fixed); + + switch (chan){ + case CONTROL_CHAN: + return handle_control_chan_frame(pkt, byte_len); + break; + + case 0: + default: +#if 0 + if (last_len != 0){ + if (byte_len != last_len){ + printf("Len: %d last: %d\n", byte_len, last_len); + } + } + last_len = byte_len; + + if((pkt->thdr.seqno) == exp_seqno){ + exp_seqno++; + //putchar('.'); + } + else { + // putchar('S'); + //printf("S%d %d ",exp_seqno,pkt->thdr.seqno); + exp_seqno = pkt->thdr.seqno + 1; + } +#endif + return false; // pass it on to Tx DSP + break; + } +} + +/* + * Called when eth phy state changes (w/ interrupts disabled) + */ +void +link_changed_callback(int speed) +{ + link_is_up = speed != 0; + hal_set_leds(link_is_up ? 0x10 : 0x0, 0x10); + printf("\neth link changed: speed = %d\n", speed); +} diff --git a/usrp2/firmware/apps/app_passthru_v2.h b/usrp2/firmware/apps/app_passthru_v2.h new file mode 100644 index 00000000..10224364 --- /dev/null +++ b/usrp2/firmware/apps/app_passthru_v2.h @@ -0,0 +1,54 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_APP_COMMON_H +#define INCLUDED_APP_COMMON_H + +#include "bool.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "memory_map.h" +#include "hal_io.h" +#include +#include + +#define CPU_TX_BUF 1 // cpu -> eth + +#define _AL4 __attribute__((aligned (4))) + +extern volatile bool link_is_up; // eth handler sets this + + +// If there's a dbsm that sends to the ethernet, put it's address here +extern dbsm_t *ac_could_be_sending_to_eth; + + +void set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt); + +/* + * Called when an ethernet packet is received. + * Return true if we handled it here, otherwise + * it'll be passed on to the DSP Tx pipe + */ +bool eth_pkt_inspector(dbsm_t *sm, int bufno); + +void link_changed_callback(int speed); + +bool handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len); + +#endif /* INCLUDED_APP_COMMON_H */ diff --git a/usrp2/firmware/apps/bitrot/tx_drop.c b/usrp2/firmware/apps/bitrot/tx_drop.c new file mode 100644 index 00000000..d5d6557d --- /dev/null +++ b/usrp2/firmware/apps/bitrot/tx_drop.c @@ -0,0 +1,261 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "app_common.h" +#include "print_rmon_regs.h" +#include +#include +#include + + +/* + * Like tx_only.c, but we discard data packets instead of sending them to the + * DSP TX pipeline. + */ + +int total_rx_pkts = 0; +int total_rx_bytes = 0; + + +static int timer_delta = MASTER_CLK_RATE/1000; // tick at 1kHz + +/* + * This program can respond to queries from the host + * and stream rx samples. + * + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow + * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow + */ +//#define CPU_RX_BUF 0 // eth -> cpu +//#define CPU_TX_BUF 1 // cpu -> eth + +#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer) +#define DSP_RX_BUF_1 3 // dsp rx -> eth +#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer) +#define DSP_TX_BUF_1 5 // eth -> dsp tx + + +/* + * ================================================================ + * configure DSP TX double buffering state machine + * ================================================================ + */ + +// 4 lines of ethernet hdr + 2 lines (word0 + timestamp) +// DSP Tx reads word0 (flags) + timestamp followed by samples + +#define DSP_TX_FIRST_LINE 4 +#define DSP_TX_SAMPLES_PER_FRAME 250 // not used except w/ debugging +#define DSP_TX_EXTRA_LINES 2 // reads word0 + timestamp + +// Receive from ethernet +buf_cmd_args_t dsp_tx_recv_args = { + PORT_ETH, + 0, + BP_LAST_LINE +}; + +// send to DSP Tx +buf_cmd_args_t dsp_tx_send_args = { + PORT_DSP, + DSP_TX_FIRST_LINE, // starts just past ethernet header + 0 // filled in from last_line register +}; + +dbsm_t dsp_tx_sm; // the state machine + + +// ---------------------------------------------------------------- + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +void +timer_irq_handler(unsigned irq) +{ + hal_set_timeout(timer_delta); // schedule next timeout +} + +// Tx DSP underrun +void +underrun_irq_handler(unsigned irq) +{ + putchar('U'); + + dbsm_stop(&dsp_tx_sm); + dsp_tx_regs->clear_state = 1; + dbsm_start(&dsp_tx_sm); // restart sm so we're listening to ethernet again + + // putstr("\nirq: underrun\n"); +} + + +void +start_rx_cmd(const u2_mac_addr_t *host, op_start_rx_t *p) +{ +} + +void +stop_rx_cmd(void) +{ +} + +static void +setup_tx() +{ + dsp_tx_regs->clear_state = 1; + bp_clear_buf(DSP_TX_BUF_0); + bp_clear_buf(DSP_TX_BUF_1); + + int tx_scale = 256; + int interp = 32; + + op_config_tx_t def_config; + memset(&def_config, 0, sizeof(def_config)); + def_config.phase_inc = 408021893; // 9.5 MHz [2**32 * fc/fsample] + def_config.scale_iq = (tx_scale << 16) | tx_scale; + def_config.interp = interp; + + // setup Tx DSP regs + config_tx_cmd(&def_config); +} + + +inline static void +buffer_irq_handler(unsigned irq) +{ + uint32_t status = buffer_pool_status->status; + + if (status & BPS_ERROR_ALL){ + // FIXME rare path, handle error conditions + putstr("Errors! status = "); + puthex32_nl(status); + + printf("total_rx_pkts = %d\n", total_rx_pkts); + printf("total_rx_bytes = %d\n", total_rx_bytes); + + print_rmon_regs(); + + if (status & (BPS_ERROR(DSP_TX_BUF_0) | BPS_ERROR(DSP_TX_BUF_1))){ + dbsm_stop(&dsp_tx_sm); + dsp_tx_regs->clear_state = 1; // try to restart + dbsm_start(&dsp_tx_sm); + return; + } + } + + dbsm_process_status(&dsp_tx_sm, status); + + if (status & BPS_DONE(CPU_TX_BUF)){ + bp_clear_buf(CPU_TX_BUF); + } +} + + +/* + * Called when an ethernet packet is received. + * + * Claim that we handled all the packets, + * dropping those destined for the TX DSP chain + * on the ground. + */ +bool +nop_eth_pkt_inspector(dbsm_t *sm, int bufno) +{ + hal_toggle_leds(0x1); + + u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno); + size_t byte_len = (buffer_pool_status->last_line[bufno] - 1) * 4; + + total_rx_pkts++; + total_rx_bytes += byte_len; + + // inspect rcvd frame and figure out what do do. + + if (pkt->ehdr.ethertype != U2_ETHERTYPE) + return true; // ignore, probably bogus PAUSE frame from MAC + + int chan = u2p_chan(&pkt->fixed); + + switch (chan){ + case CONTROL_CHAN: + handle_control_chan_frame(pkt, byte_len); + return true; // we handled the packet + break; + + case 0: + default: + return true; // We handled the data by dropping it :) + break; + } +} + + +int +main(void) +{ + u2_init(); + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1); + hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1); + + putstr("\ntx_drop\n"); + + // Control LEDs + hal_set_leds(0x0, 0x3); + + pic_register_handler(IRQ_UNDERRUN, underrun_irq_handler); + + ethernet_register_link_changed_callback(link_changed_callback); + ethernet_init(); + + // initialize double buffering state machine for ethernet -> DSP Tx + + dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, + &dsp_tx_recv_args, &dsp_tx_send_args, + nop_eth_pkt_inspector); + + // program tx registers + setup_tx(); + + // kick off the state machine + dbsm_start(&dsp_tx_sm); + + while(1){ + buffer_irq_handler(0); + } +} + diff --git a/usrp2/firmware/apps/bitrot/tx_drop2.c b/usrp2/firmware/apps/bitrot/tx_drop2.c new file mode 100644 index 00000000..7f9b7a56 --- /dev/null +++ b/usrp2/firmware/apps/bitrot/tx_drop2.c @@ -0,0 +1,292 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "app_common.h" +#include "print_rmon_regs.h" +#include +#include +#include + + +/* + * Like tx_only.c, but we discard data packets instead of sending them to the + * DSP TX pipeline. + */ + +int total_rx_pkts = 0; +int total_rx_bytes = 0; + + +static int timer_delta = MASTER_CLK_RATE/1000; // tick at 1kHz + +/* + * This program can respond to queries from the host + * and stream rx samples. + * + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow + * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow + */ +//#define CPU_RX_BUF 0 // eth -> cpu +//#define CPU_TX_BUF 1 // cpu -> eth + +#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer) +#define DSP_RX_BUF_1 3 // dsp rx -> eth +#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer) +#define DSP_TX_BUF_1 5 // eth -> dsp tx + + +/* + * ================================================================ + * configure DSP RX double buffering state machine + * ================================================================ + */ + +// 4 lines of ethernet hdr + 1 line (word0) +// DSP Rx writes timestamp followed by nlines_per_frame of samples +#define DSP_RX_FIRST_LINE 5 +#define DSP_RX_SAMPLES_PER_FRAME 128 +#define DSP_RX_EXTRA_LINES 1 // writes timestamp + +// Receive from DSP Rx +buf_cmd_args_t dsp_rx_recv_args = { + PORT_DSP, + DSP_RX_FIRST_LINE, + BP_LAST_LINE +}; + +// send to ethernet +buf_cmd_args_t dsp_rx_send_args = { + PORT_ETH, + 0, // starts with ethernet header in line 0 + 0, // filled in from last_line register +}; + +dbsm_t dsp_rx_sm; // the state machine + +/* + * ================================================================ + * configure DSP TX double buffering state machine + * ================================================================ + */ + +// 4 lines of ethernet hdr + 2 lines (word0 + timestamp) +// DSP Tx reads word0 (flags) + timestamp followed by samples + +#define DSP_TX_FIRST_LINE 4 +#define DSP_TX_SAMPLES_PER_FRAME 250 // not used except w/ debugging +#define DSP_TX_EXTRA_LINES 2 // reads word0 + timestamp + +// Receive from ethernet +buf_cmd_args_t dsp_tx_recv_args = { + PORT_ETH, + 0, + BP_LAST_LINE +}; + +// send to DSP Tx +buf_cmd_args_t dsp_tx_send_args = { + PORT_DSP, + DSP_TX_FIRST_LINE, // starts just past ethernet header + 0 // filled in from last_line register +}; + +dbsm_t dsp_tx_sm; // the state machine + + +// ---------------------------------------------------------------- + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +void +timer_irq_handler(unsigned irq) +{ + hal_set_timeout(timer_delta); // schedule next timeout +} + +// Tx DSP underrun +void +underrun_irq_handler(unsigned irq) +{ + putchar('U'); + + dbsm_stop(&dsp_tx_sm); + dsp_tx_regs->clear_state = 1; + dbsm_start(&dsp_tx_sm); // restart sm so we're listening to ethernet again + + // putstr("\nirq: underrun\n"); +} + + +void +start_rx_cmd(const u2_mac_addr_t *host, op_start_rx_t *p) +{ +} + +void +stop_rx_cmd(void) +{ +} + +static void +setup_tx() +{ + dsp_tx_regs->clear_state = 1; + bp_clear_buf(DSP_TX_BUF_0); + bp_clear_buf(DSP_TX_BUF_1); + +#if 1 + int tx_scale = 256; + int interp = 32; + + op_config_tx_t def_config; + memset(&def_config, 0, sizeof(def_config)); + def_config.phase_inc = 408021893; // 9.5 MHz [2**32 * fc/fsample] + def_config.scale_iq = (tx_scale << 16) | tx_scale; + def_config.interp = interp; + + // setup Tx DSP regs + config_tx_cmd(&def_config); +#endif +} + + +inline static void +buffer_irq_handler(unsigned irq) +{ + uint32_t status = buffer_pool_status->status; + + if (status & BPS_ERROR_ALL){ + // FIXME rare path, handle error conditions + putstr("Errors! status = "); + puthex32_nl(status); + + printf("total_rx_pkts = %d\n", total_rx_pkts); + printf("total_rx_bytes = %d\n", total_rx_bytes); + + print_rmon_regs(); + + if (status & (BPS_ERROR(DSP_TX_BUF_0) | BPS_ERROR(DSP_TX_BUF_1))){ + dbsm_stop(&dsp_tx_sm); + dsp_tx_regs->clear_state = 1; // try to restart + dbsm_start(&dsp_tx_sm); + return; + } + } + + dbsm_process_status(&dsp_tx_sm, status); + + if (status & BPS_DONE(CPU_TX_BUF)){ + bp_clear_buf(CPU_TX_BUF); + } +} + +/* + * Called when an ethernet packet is received. + * Return true if we handled it here (always!) + */ +bool +nop_eth_pkt_inspector(dbsm_t *sm, int bufno) +{ + hal_toggle_leds(0x1); + + u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno); + size_t byte_len = (buffer_pool_status->last_line[bufno] - 1) * 4; + + total_rx_pkts++; + total_rx_bytes += byte_len; + + // inspect rcvd frame and figure out what do do. + + if (pkt->ehdr.ethertype != U2_ETHERTYPE) + return true; // ignore, probably bogus PAUSE frame from MAC + + int chan = u2p_chan(&pkt->fixed); + + switch (chan){ + case CONTROL_CHAN: + handle_control_chan_frame(pkt, byte_len); + return true; // we handled the packet + break; + + case 0: + default: + return true; // say we handled it + break; + } +} + + +int +main(void) +{ + u2_init(); + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1); + hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1); // no printing... + + putstr("\ntx_drop2\n"); + + // Control LEDs + hal_set_leds(0x0, 0x3); + + // pic_register_handler(IRQ_OVERRUN, overrun_irq_handler); + pic_register_handler(IRQ_UNDERRUN, underrun_irq_handler); + + //pic_register_handler(IRQ_TIMER, timer_irq_handler); + //hal_set_timeout(timer_delta); + + ethernet_register_link_changed_callback(link_changed_callback); + + ethernet_init(); + + // initialize double buffering state machine for ethernet -> DSP Tx + + dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, + &dsp_tx_recv_args, &dsp_tx_send_args, + nop_eth_pkt_inspector); + + // program tx registers + setup_tx(); + + // kick off the state machine + dbsm_start(&dsp_tx_sm); + + while(1){ + buffer_irq_handler(0); + } +} + diff --git a/usrp2/firmware/apps/bitrot/tx_drop_rate_limited.c b/usrp2/firmware/apps/bitrot/tx_drop_rate_limited.c new file mode 100644 index 00000000..0eab25b3 --- /dev/null +++ b/usrp2/firmware/apps/bitrot/tx_drop_rate_limited.c @@ -0,0 +1,233 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "app_common.h" +#include "print_rmon_regs.h" +#include "eth_mac.h" +#include +#include +#include + + +/* + * receive packets from ethernet at a fixed rate and discard them + */ + +int total_rx_pkts = 0; +int total_rx_bytes = 0; + + +static int timer_delta = (int)(MASTER_CLK_RATE * 10e-6); // 10us / tick + + +/* + * This program can respond to queries from the host + * and stream rx samples. + * + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow + * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow + */ +//#define CPU_RX_BUF 0 // eth -> cpu +//#define CPU_TX_BUF 1 // cpu -> eth + +#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer) +#define DSP_RX_BUF_1 3 // dsp rx -> eth +#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer) +#define DSP_TX_BUF_1 5 // eth -> dsp tx + + + +// ---------------------------------------------------------------- + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +static volatile bool receive_packet_now = false; + +void +timer_irq_handler(unsigned irq) +{ + hal_set_timeout(timer_delta); // schedule next timeout + receive_packet_now = true; +} + + +// Tx DSP underrun +void +underrun_irq_handler(unsigned irq) +{ + putchar('U'); +} + + +void +start_rx_cmd(const u2_mac_addr_t *host, op_start_rx_t *p) +{ +} + +void +stop_rx_cmd(void) +{ +} + +static void +setup_tx() +{ + dsp_tx_regs->clear_state = 1; + bp_clear_buf(DSP_TX_BUF_0); + bp_clear_buf(DSP_TX_BUF_1); + + int tx_scale = 256; + int interp = 32; + + op_config_tx_t def_config; + memset(&def_config, 0, sizeof(def_config)); + def_config.phase_inc = 408021893; // 9.5 MHz [2**32 * fc/fsample] + def_config.scale_iq = (tx_scale << 16) | tx_scale; + def_config.interp = interp; + + // setup Tx DSP regs + config_tx_cmd(&def_config); +} + + +/* + * Called when an ethernet packet is received. + * + * Claim that we handled all the packets, + * dropping those destined for the TX DSP chain + * on the ground. + */ +bool +nop_eth_pkt_inspector(dbsm_t *sm, int bufno) +{ + hal_toggle_leds(0x1); + + u2_eth_packet_t *pkt = (u2_eth_packet_t *) buffer_ram(bufno); + size_t byte_len = (buffer_pool_status->last_line[bufno] - 1) * 4; + + total_rx_pkts++; + total_rx_bytes += byte_len; + + // inspect rcvd frame and figure out what do do. + + if (pkt->ehdr.ethertype != U2_ETHERTYPE) + return true; // ignore, probably bogus PAUSE frame from MAC + + int chan = u2p_chan(&pkt->fixed); + + switch (chan){ + case CONTROL_CHAN: + handle_control_chan_frame(pkt, byte_len); + return true; // we handled the packet + break; + + case 0: + default: + return true; // We handled the data by dropping it :) + break; + } +} + + +inline static void +buffer_irq_handler(unsigned irq) +{ + uint32_t status = buffer_pool_status->status; + + if (status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))) + bp_clear_buf(CPU_TX_BUF); + + if (status & (BPS_DONE(DSP_TX_BUF_0) | BPS_ERROR(DSP_TX_BUF_0))){ + bp_clear_buf(DSP_TX_BUF_0); + + if (status & BPS_ERROR(DSP_TX_BUF_0)){ + int crc = eth_mac_read_rmon(0x05); + int fifo_full = eth_mac_read_rmon(0x06); + int too_short_too_long = eth_mac_read_rmon(0x07); + putstr("Errors! status = "); + puthex32_nl(status); + + printf("crc_err\t\t= %d\n", crc); + printf("fifo_full\t\t= %d\n", fifo_full); + printf("too_short_too_long\t= %d\n", too_short_too_long); + + printf("total_rx_pkts = %d\n", total_rx_pkts); + printf("total_rx_bytes = %d\n", total_rx_bytes); + } + else + nop_eth_pkt_inspector(0, DSP_TX_BUF_0); + } + + if (receive_packet_now && (status & BPS_IDLE(DSP_TX_BUF_0))){ + receive_packet_now = false; + bp_receive_to_buf(DSP_TX_BUF_0, PORT_ETH, 1, 0, BP_LAST_LINE); + } +} + + +int +main(void) +{ + u2_init(); + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1); + hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1); + + putstr("\ntx_drop_rate_limited\n"); + + // Control LEDs + hal_set_leds(0x0, 0x3); + + pic_register_handler(IRQ_UNDERRUN, underrun_irq_handler); + + pic_register_handler(IRQ_TIMER, timer_irq_handler); + hal_set_timeout(timer_delta); + + ethernet_register_link_changed_callback(link_changed_callback); + ethernet_init(); + + // program tx registers + setup_tx(); + + // start a receive from ethernet + bp_receive_to_buf(DSP_TX_BUF_0, PORT_ETH, 1, 0, BP_LAST_LINE); + + while(1){ + buffer_irq_handler(0); + } +} + diff --git a/usrp2/firmware/apps/blink_leds.c b/usrp2/firmware/apps/blink_leds.c new file mode 100644 index 00000000..682ca8db --- /dev/null +++ b/usrp2/firmware/apps/blink_leds.c @@ -0,0 +1,40 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "hal_io.h" +#include "nonstdio.h" + +int +main(void) +{ + int counter = 0; + + u2_init(); + + putstr("blink_leds\n"); + while(1){ + output_regs->leds = (counter++ & 0x3); + } + + return 0; +} diff --git a/usrp2/firmware/apps/blink_leds2.c b/usrp2/firmware/apps/blink_leds2.c new file mode 100644 index 00000000..d4bd89a1 --- /dev/null +++ b/usrp2/firmware/apps/blink_leds2.c @@ -0,0 +1,53 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "hal_io.h" +#include "pic.h" +#include "nonstdio.h" + +//#define DELTA_T (MASTER_CLK_RATE/2) // 0.5s (10ns per tick) +#define DELTA_T 5000 // 5 us (10ns per tick) + + +void +timer_handler(unsigned irq) +{ + hal_set_timeout(DELTA_T); // schedule next timeout + hal_toggle_leds(0x2); +} + +int +main(void) +{ + u2_init(); + + putstr("blink_leds2\n"); + pic_register_handler(IRQ_TIMER, timer_handler); + hal_set_timeout(DELTA_T); // schedule next timeout + + while(1){ + hal_toggle_leds(0x1); + } + + return 0; +} diff --git a/usrp2/firmware/apps/buf_ram_test.c b/usrp2/firmware/apps/buf_ram_test.c new file mode 100644 index 00000000..e639166a --- /dev/null +++ b/usrp2/firmware/apps/buf_ram_test.c @@ -0,0 +1,89 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "u2_init.h" +#include "memory_map.h" +#include "bool.h" +#include "nonstdio.h" +#include "hal_io.h" +#include "mdelay.h" + + +static void +write_bufs(void) +{ + int i, n; + int counter = 0; + + for (n = 0; n < NBUFFERS; n++){ + volatile int *p = buffer_ram(n); + for (i = 0; i < BP_NLINES; i++) + p[i] = counter++; + } +} + +// return number of errors detected +static int +check_bufs(void) +{ + int i, n; + int counter = 0; + int nerrors = 0; + + for (n = 0; n < NBUFFERS; n++){ + volatile int *p = buffer_ram(n); + for (i = 0; i < BP_NLINES; i++, counter++){ + int rd = p[i]; + if (rd != counter){ + putchar('b'); + putchar(n + '0'); + putchar('['); + puthex16(i); + putstr("] exp: "); + puthex32(counter); + putstr(" got: "); + puthex32_nl(rd); + nerrors++; + } + } + } + return nerrors; +} + + +int +main(void) +{ + u2_init(); + + output_regs->leds = 0; + + write_bufs(); + int nerrors = check_bufs(); + + if (nerrors == 0){ + output_regs->leds = 0x3; // leds on -> PASS + putstr("PASS\n"); + } + else { + output_regs->leds = 0x0; // leds off -> FAIL + putstr("FAIL\n"); + } + + hal_finish(); + return 0; +} diff --git a/usrp2/firmware/apps/can_i_sub.c b/usrp2/firmware/apps/can_i_sub.c new file mode 100644 index 00000000..ed49791f --- /dev/null +++ b/usrp2/firmware/apps/can_i_sub.c @@ -0,0 +1,25 @@ +#include +#include + +//typedef long long int64_t; + + +int64_t sub(int64_t a, int64_t b); +void print(int64_t d); + +int main(void) +{ + u2_init(); + + int64_t d = sub(462550990848000LL, 462028800000000LL); + print_uint64(d); + newline(); + return 0; +} + +int64_t sub(int64_t a, int64_t b) +{ + return a - b; +} + + diff --git a/usrp2/firmware/apps/double_buffer_fragment.c b/usrp2/firmware/apps/double_buffer_fragment.c new file mode 100644 index 00000000..cfc06124 --- /dev/null +++ b/usrp2/firmware/apps/double_buffer_fragment.c @@ -0,0 +1,138 @@ +#if 0 +void +double_buffering(int port) { + unsigned int localstatus = buffer_pool_status->status; + + if(localstatus & BPS_DONE_0) { + bp_clear_buf(0); + if(buffer_state[0] == FILLING) { + buffer_state[0] = FULL; + if(buffer_state[1] == EMPTY) { + bp_receive_to_buf(1, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500 lines + buffer_state[1] = FILLING; + } + else + dsp_rx_idle = 1; + if(serdes_tx_idle) { + serdes_tx_idle = 0; + bp_send_from_buf(0, port, 1, 10, 509); // SERDES_TX from buffer 0 + buffer_state[0] = EMPTYING; + } + } + else { // buffer was emptying + buffer_state[0] = EMPTY; + if(dsp_rx_idle) { + dsp_rx_idle = 0; + bp_receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 0, use 500 lines + buffer_state[0] = FILLING; + } + if(buffer_state[1] == FULL) { + bp_send_from_buf(1, port, 1, 10, 509); // SERDES_TX from buffer 1 + buffer_state[1] = EMPTYING; + } + else + serdes_tx_idle = 1; + } + putstr("Int Proc'ed 0\n"); + } + + if(localstatus & BPS_DONE_1) { + bp_clear_buf(1); + if(buffer_state[1] == FILLING) { + buffer_state[1] = FULL; + if(buffer_state[0] == EMPTY) { + bp_receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500 lines + buffer_state[0] = FILLING; + } + else + dsp_rx_idle = 1; + if(serdes_tx_idle) { + serdes_tx_idle = 0; + bp_send_from_buf(1, port, 1, 10, 509); // SERDES_TX from buffer 1 + buffer_state[1] = EMPTYING; + } + } + else { // buffer was emptying + buffer_state[1] = EMPTY; + if(dsp_rx_idle) { + dsp_rx_idle = 0; + bp_receive_to_buf(1, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500 lines + buffer_state[1] = FILLING; + } + if(buffer_state[0] == FULL) { + bp_send_from_buf(0, port, 1, 10, 509); // SERDES_TX from buffer 0 + buffer_state[0] = EMPTYING; + } + else + serdes_tx_idle = 1; + } + putstr("Int Proc'ed 1\n"); + } + + if(localstatus & BPS_DONE_2) { + bp_clear_buf(2); + if(buffer_state[2] == FILLING) { + buffer_state[2] = FULL; + if(buffer_state[3] == EMPTY) { + bp_receive_to_buf(3, port, 1, 5, 504); // SERDES_RX to buffer 3, use 500 lines + buffer_state[3] = FILLING; + } + else + serdes_rx_idle = 1; + if(dsp_tx_idle) { + dsp_tx_idle = 0; + bp_send_from_buf(2, 1, 1, 5, 504); // DSP_TX from buffer 2 + buffer_state[2] = EMPTYING; + } + } + else { // buffer was emptying + buffer_state[2] = EMPTY; + if(serdes_rx_idle) { + serdes_rx_idle = 0; + bp_receive_to_buf(2, port, 1, 5, 504); // SERDES_RX to buffer 2 + buffer_state[2] = FILLING; + } + if(buffer_state[3] == FULL) { + bp_send_from_buf(3, 1, 1, 5, 504); // DSP_TX from buffer 3 + buffer_state[3] = EMPTYING; + } + else + dsp_tx_idle = 1; + } + putstr("Int Proc'ed 2\n"); + } + + if(localstatus & BPS_DONE_3) { + bp_clear_buf(3); + if(buffer_state[3] == FILLING) { + buffer_state[3] = FULL; + if(buffer_state[2] == EMPTY) { + bp_receive_to_buf(2, port, 1, 5, 504); // SERDES_RX to buffer 2, use 500 lines + buffer_state[2] = FILLING; + } + else + serdes_rx_idle = 1; + if(dsp_tx_idle) { + dsp_tx_idle = 0; + bp_send_from_buf(3, 1, 1, 5, 504); // DSP_TX from buffer 3 + buffer_state[3] = EMPTYING; + } + } + else { // buffer was emptying + buffer_state[3] = EMPTY; + if(serdes_rx_idle) { + serdes_rx_idle = 0; + bp_receive_to_buf(3, port, 1, 5, 504); // SERDES_RX to buffer 3 + buffer_state[3] = FILLING; + } + if(buffer_state[2] == FULL) { + bp_send_from_buf(2, 1, 1, 5, 504); // DSP_TX from buffer 2 + buffer_state[2] = EMPTYING; + } + else + dsp_tx_idle = 1; + } + putstr("Int Proc'ed 3\n"); + } +} +#endif diff --git a/usrp2/firmware/apps/echo.c b/usrp2/firmware/apps/echo.c new file mode 100644 index 00000000..89108ee8 --- /dev/null +++ b/usrp2/firmware/apps/echo.c @@ -0,0 +1,34 @@ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "u2_init.h" +#include "stdio.h" + +int +main(void) +{ + u2_init(); + + puts("\n>>> echo <<<"); + + while (1){ + int ch = getchar(); + putchar(ch); + } + + return 0; +} diff --git a/usrp2/firmware/apps/eth_serdes.c b/usrp2/firmware/apps/eth_serdes.c new file mode 100644 index 00000000..c47b8ebd --- /dev/null +++ b/usrp2/firmware/apps/eth_serdes.c @@ -0,0 +1,230 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "app_passthru_v2.h" +#include "memcpy_wa.h" +#include "clocks.h" +#include +#include +#include + + +#define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now) + +#if (FW_SETS_SEQNO) +static int fw_seqno __attribute__((unused)); // used when f/w is filling in sequence numbers +#endif + + +/* + * Full duplex Tx and Rx between ethernet and serdes + * + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow + * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow + */ +//#define CPU_RX_BUF 0 // eth -> cpu + +#define DSP_RX_BUF_0 2 // serdes -> eth (double buffer) +#define DSP_RX_BUF_1 3 // serdes -> eth +#define DSP_TX_BUF_0 4 // eth -> serdes (double buffer) +#define DSP_TX_BUF_1 5 // eth -> serdes + +/* + * ================================================================ + * configure serdes double buffering state machine (eth -> serdes) + * ================================================================ + */ + + +// Receive from ethernet +buf_cmd_args_t dsp_tx_recv_args = { + PORT_ETH, + 0, + BP_LAST_LINE +}; + +// send to serdes +buf_cmd_args_t dsp_tx_send_args = { + PORT_SERDES, + 0, + 0 // filled in from last_line register +}; + +dbsm_t dsp_tx_sm; // the state machine + +/* + * ==================================================================== + * configure serdes RX double buffering state machine (serdes -> eth) + * ==================================================================== + */ + +// receive from serdes +buf_cmd_args_t dsp_rx_recv_args = { + PORT_SERDES, + 0, + BP_LAST_LINE +}; + +// send to ETH +buf_cmd_args_t dsp_rx_send_args = { + PORT_ETH, + 0, // starts with ethernet header in line 0 + 0, // filled in from list_line register +}; + +dbsm_t dsp_rx_sm; // the state machine + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +// ---------------------------------------------------------------- + + +#if (FW_SETS_SEQNO) +/* + * Debugging ONLY. This will be handled by the tx_protocol_engine. + * + * This is called when the DSP Rx chain has filled in a packet. + * We set and increment the seqno, then return false, indicating + * that we didn't handle the packet. A bit of a kludge + * but it should work. + */ + +bool +fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false +{ +#if 0 + uint32_t *p = buffer_ram(buf_this); + uint32_t last_line = buffer_pool_status->last_line[buf_this] - sm->last_line_adj; + printf("fw_sets_seqno_inspector: buf_this = %d, last_line = %d\n", + buf_this, last_line); + + print_buffer(p, (last_line + 1)); +#endif + +#if 0 + uint32_t *p = buffer_ram(buf_this); + uint32_t seqno = fw_seqno++; + + // KLUDGE all kinds of nasty magic numbers and embedded knowledge + uint32_t t = p[4]; + t = (t & 0xffff00ff) | ((seqno & 0xff) << 8); + p[4] = t; +#endif + + return false; // we didn't handle the packet +} +#endif + + +inline static void +buffer_irq_handler(unsigned irq) +{ + uint32_t status = buffer_pool_status->status; + + if (0 && (status & ~BPS_IDLE_ALL)){ + putstr("status = "); + puthex32_nl(status); + } + + dbsm_process_status(&dsp_tx_sm, status); + dbsm_process_status(&dsp_rx_sm, status); +} + +int +main(void) +{ + u2_init(); + + putstr("\neth <-> serdes\n"); + + ethernet_register_link_changed_callback(link_changed_callback); + ethernet_init(); + + // clocks_mimo_config(MC_WE_LOCK_TO_SMA | MC_PROVIDE_CLK_TO_MIMO); + clocks_mimo_config(MC_WE_DONT_LOCK | MC_PROVIDE_CLK_TO_MIMO); + +#if 0 + // make bit 15 of Tx gpio's be a s/w output + hal_gpio_set_sel(GPIO_TX_BANK, 15, 's'); + hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000); +#endif + +#if 1 + output_regs->debug_mux_ctrl = 1; + hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff); + hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff); +#endif + + + // initialize double buffering state machine for ethernet -> serdes + + dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, + &dsp_tx_recv_args, &dsp_tx_send_args, + eth_pkt_inspector); + + + // initialize double buffering state machine for serdes -> ethernet + + if (FW_SETS_SEQNO){ + dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, + &dsp_rx_recv_args, &dsp_rx_send_args, + fw_sets_seqno_inspector); + } + else { + dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, + &dsp_rx_recv_args, &dsp_rx_send_args, + dbsm_nop_inspector); + } + + // tell app_common that this dbsm could be sending to the ethernet + ac_could_be_sending_to_eth = &dsp_rx_sm; + + + // kick off the state machines + dbsm_start(&dsp_tx_sm); + dbsm_start(&dsp_rx_sm); + + //int which = 0; + + while(1){ + // hal_gpio_write(GPIO_TX_BANK, which, 0x8000); + // which ^= 0x8000; + + buffer_irq_handler(0); + } +} diff --git a/usrp2/firmware/apps/gen_eth_packets.c b/usrp2/firmware/apps/gen_eth_packets.c new file mode 100644 index 00000000..ce1e8160 --- /dev/null +++ b/usrp2/firmware/apps/gen_eth_packets.c @@ -0,0 +1,181 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "memcpy_wa.h" +#include "print_rmon_regs.h" +#include +#include +#include + + +// ---------------------------------------------------------------- + +static u2_mac_addr_t dst_mac_addr = + {{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }}; + +// ---------------------------------------------------------------- + +// #define PACKET_SIZE 1500 // bytes +// #define ETH_DATA_RATE 1000000 // 1MB/s +// #define ETH_PACKET_RATE (ETH_DATA_RATE/PACKET_SIZE) // 13,3333 pkts/s + +// static int timer_delta = MASTER_CLK_RATE/ETH_PACKET_RATE; // ticks between interrupts + +static int timer_delta = (int)(MASTER_CLK_RATE * 1e-3); // tick at 1 kHz +static int sim_timer_delta = (int)(MASTER_CLK_RATE * 100e-6); // tick at 10 kHz + +static volatile bool send_packet_now = false; // timer handler sets this +static volatile bool link_is_up = false; // eth handler sets this + +int packet_number = 0; + + +#define CPU_TX_BUF 0 // cpu xmits ethernet frames from here +#define CPU_RX_BUF 1 // receive ethernet frames here + +// ---------------------------------------------------------------- + +/* + * Called when eth phy state changes (w/ interrupts disabled) + */ +void +link_changed_callback(int speed) +{ + link_is_up = speed == 0 ? false : true; + hal_set_leds(link_is_up ? 0x2 : 0x0, 0x2); + printf("\neth link changed: speed = %d\n", speed); +} + +void +timer_irq_handler(unsigned irq) +{ + hal_set_timeout(timer_delta); // schedule next timeout + send_packet_now = 1; +} + + +static void +init_packet(int *buf, const u2_eth_packet_t *pkt, int bufnum) +{ + int i = 0; + int mark = ((bufnum & 0xff) << 24) | 0x005A0000; + + for (i = 0; i < BP_NLINES; i++){ + buf[i] = mark | i; + mark ^= 0x00FF0000; + } + + // copy header into buffer + memcpy_wa(buf, pkt, sizeof(*pkt)); +} + +static void +init_packets(void) +{ + u2_eth_packet_t pkt __attribute__((aligned (4))); + + memset(&pkt, 0, sizeof(pkt)); + + pkt.ehdr.dst = dst_mac_addr; + // src address filled in by mac + + pkt.ehdr.ethertype = U2_ETHERTYPE; + pkt.fixed.word0 = 0x01234567; + pkt.fixed.timestamp = 0xffffffff; + + // init just the one we're using + init_packet((void *)buffer_ram(CPU_TX_BUF), &pkt, CPU_TX_BUF); +} + +int +main(void) +{ + int npackets_sent = 0; + + u2_init(); + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + + putstr("\ngen_eth_packets\n"); + + hal_set_leds(0x0, 0x3); + + init_packets(); + + pic_register_handler(IRQ_TIMER, timer_irq_handler); + + if (hwconfig_simulation_p()) + timer_delta = sim_timer_delta; + + hal_set_timeout(timer_delta); + + ethernet_register_link_changed_callback(link_changed_callback); + ethernet_init(); + + if (hwconfig_simulation_p()){ + eth_mac->speed = 4; // hardcode mac speed to 1000 + link_is_up = true; + } + + // fire off a receive from the ethernet + bp_receive_to_buf(CPU_RX_BUF, PORT_ETH, 1, 0, BP_LAST_LINE); + + while(1){ + uint32_t status = buffer_pool_status->status; + + if (status & (BPS_DONE(CPU_RX_BUF) | BPS_ERROR(CPU_RX_BUF))){ + bp_clear_buf(CPU_RX_BUF); + // ignore incoming ethernet packets; they were looped back in sim + bp_receive_to_buf(CPU_RX_BUF, PORT_ETH, 1, 0, BP_LAST_LINE); + } + + if (status & (BPS_DONE(CPU_TX_BUF) | BPS_ERROR(CPU_TX_BUF))){ + bp_clear_buf(CPU_TX_BUF); + npackets_sent++; + if ((npackets_sent & 0xF) == 0) // print after every 16 packets + print_rmon_regs(); + } + + if (link_is_up && send_packet_now && (status & BPS_IDLE(CPU_TX_BUF))){ + send_packet_now = false; + + // kick off the next packet + // FIXME set packet number in packet + + bp_send_from_buf(CPU_TX_BUF, PORT_ETH, 1, 0, 255); // 1KB total + hal_toggle_leds(0x1); + } + } + + hal_finish(); + return 1; +} diff --git a/usrp2/firmware/apps/gen_pause_frames.c b/usrp2/firmware/apps/gen_pause_frames.c new file mode 100644 index 00000000..4eaebcc4 --- /dev/null +++ b/usrp2/firmware/apps/gen_pause_frames.c @@ -0,0 +1,207 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "u2_eth_packet.h" +#include "memcpy_wa.h" +#include +#include + + +// ---------------------------------------------------------------- + +unsigned char dst_mac_addr[6] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff +}; + +// ---------------------------------------------------------------- + +// #define PACKET_SIZE 1500 // bytes +// #define ETH_DATA_RATE 1000000 // 1MB/s +// #define ETH_PACKET_RATE (ETH_DATA_RATE/PACKET_SIZE) // 13,3333 pkts/s + +// static int timer_delta = MASTER_CLK_RATE/ETH_PACKET_RATE; // ticks between interrupts + +static int timer_delta = MASTER_CLK_RATE/1000; // tick at 1kHz + +static volatile bool send_packet_now = false; // timer handler sets this +static volatile bool link_is_up = false; // eth handler sets this + +int packet_number = 0; + +// ---------------------------------------------------------------- + +// debugging output on tx pins +#define LS_MASK 0xE0000 +#define LS_1000 0x80000 +#define LS_100 0x40000 +#define LS_10 0x20000 + + +/* + * Called when eth phy state changes (w/ interrupts disabled) + */ +void +link_changed_callback(int speed) +{ + int v = 0; + switch(speed){ + case 10: + v = LS_10; + link_is_up = true; + break; + + case 100: + v = LS_100; + link_is_up = true; + break; + + case 1000: + v = LS_100; + link_is_up = true; + break; + + default: + v = 0; + link_is_up = false; + break; + } + + hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */ + + putstr("\neth link changed: speed = "); + puthex16_nl(speed); +} + +void +timer_irq_handler(unsigned irq) +{ + hal_set_timeout(timer_delta); // schedule next timeout + send_packet_now = 1; +} + + +void +buffer_irq_handler(unsigned irq) +{ + // FIXME +} + +static void +init_packet(int *buf, const u2_eth_packet_t *pkt, int bufnum) +{ + int i = 0; + int mark = ((bufnum & 0xff) << 24) | 0x005A0000; + + for (i = 0; i < BP_NLINES; i++){ + buf[i] = mark | i; + mark ^= 0x00FF0000; + } + + // copy header into buffer + memcpy_wa(buf, pkt, sizeof(*pkt)); +} + +static void +init_packets(void) +{ + int i; + + u2_eth_packet_t pkt __attribute__((aligned (4))); + + for (i = 0; i < 6; i++){ + pkt.ehdr.dst_addr[i] = dst_mac_addr[i]; + pkt.ehdr.src_addr[i] = 0; // filled in by mac + } + pkt.ehdr.ethertype = U2_ETHERTYPE; + + // fill ALL buffers for debugging + for (i = 0; i < 8; i++) + init_packet((void *)buffer_ram(i), &pkt, i); +} + +static int led_counter = 0; + +int +main(void) +{ + int send_pause = 1; + + u2_init(); + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + + putstr("\ngen_eth_packets\n"); + + // Control LEDs + output_regs->leds = 0x00; + + init_packets(); + + // pic_register_handler(IRQ_BUFFER, buffer_irq_handler); // poll for now + pic_register_handler(IRQ_TIMER, timer_irq_handler); + hal_set_timeout(timer_delta); + + ethernet_register_link_changed_callback(link_changed_callback); + + ethernet_init(); + + eth_mac->pause_frame_send_en = 1; + eth_mac->pause_quanta_set = 16384 / 512; + + // eth_mac->speed = 4; // FIXME hardcode mac speed to 1000 + + while(1){ + if (link_is_up && send_packet_now){ + send_packet_now = false; + + + if (send_pause) + eth_mac->xon_cpu = 1; + else + eth_mac->xon_cpu = 0; + + send_pause ^= 1; + + // kick off the next packet + // FIXME set packet number in packet + +#if 0 + bp_send_from_buf(0, PORT_ETH, 1, 0, 255); // 1KB total + + while ((buffer_pool_status->status & (BPS_DONE_0|BPS_ERROR_0)) == 0) + ; + bp_clear_buf(0); +#endif + + output_regs->leds = ((++led_counter) & 0x1) | (link_is_up ? 0x2 : 0x0); + } + } + + hal_finish(); + return 1; +} diff --git a/usrp2/firmware/apps/hello.c b/usrp2/firmware/apps/hello.c new file mode 100644 index 00000000..bce84309 --- /dev/null +++ b/usrp2/firmware/apps/hello.c @@ -0,0 +1,30 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "u2_init.h" +#include "stdio.h" + +int +main(void) +{ + u2_init(); + + puts("Hello World"); + puts("Goodbye World"); + + return 0; +} diff --git a/usrp2/firmware/apps/ibs_rx_test.c b/usrp2/firmware/apps/ibs_rx_test.c new file mode 100644 index 00000000..bdc04747 --- /dev/null +++ b/usrp2/firmware/apps/ibs_rx_test.c @@ -0,0 +1,82 @@ +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "nonstdio.h" + +#define PORT 2 // ethernet = 2, serdes = 0 +int dsp_rx_buf, dsp_tx_buf, serdes_rx_buf, serdes_tx_buf; +int dsp_rx_idle, dsp_tx_idle, serdes_rx_idle, serdes_tx_idle; + +int buffer_state[4]; + +static void __attribute__((unused)) +wait_until_status_nonzero(void) +{ + while (buffer_pool_status->status == 0) + ; +} + +int +main(void) +{ + int i; + + u2_init(); + + output_regs->adc_ctrl = 0x0A; + + dsp_rx_regs->freq = 0; + dsp_rx_regs->scale_iq = (1 << 16) | 1; + dsp_rx_regs->decim_rate = 8; + + volatile unsigned int *buffer0 = buffer_ram(0); + volatile unsigned int *buffer1 = buffer_ram(1); + volatile unsigned int *buffer2 = buffer_ram(2); + + putstr("Starting RX\n"); + bp_clear_buf(0); + bp_receive_to_buf(0, 1, 1, 0, 99); + + dsp_rx_regs->rx_command = (50 << 9) | 100; // Numlines, lines per frame + dsp_rx_regs->rx_time = 0x2000; + + dsp_rx_regs->rx_command = (137 << 9) | 50; // Numlines, lines per frame + dsp_rx_regs->rx_time = 0x2200; + + while (buffer_pool_status->status == 0) + ; + bp_clear_buf(0); + bp_clear_buf(1); + bp_receive_to_buf(1, 1, 1, 0, 99); + while (buffer_pool_status->status == 0) + ; + bp_clear_buf(2); + bp_receive_to_buf(2, 1, 1, 0, 99); + while (buffer_pool_status->status == 0) + ; + + for(i=0;i<100;i++) { + puthex(i); + putstr(" "); + puthex_nl(buffer0[i]); + } + for(i=0;i<60;i++) { + puthex(i); + putstr(" "); + puthex_nl(buffer1[i]); + } + for(i=0;i<60;i++) { + puthex(i); + putstr(" "); + puthex_nl(buffer2[i]); + } + //while(timer_regs -> time < 0x6000) + // {} + + putstr("Done\n"); + hal_finish(); + + return 1; +} diff --git a/usrp2/firmware/apps/ibs_tx_test.c b/usrp2/firmware/apps/ibs_tx_test.c new file mode 100644 index 00000000..ff9446d9 --- /dev/null +++ b/usrp2/firmware/apps/ibs_tx_test.c @@ -0,0 +1,160 @@ +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "nonstdio.h" + +// Globals +#define EMPTY 0 +#define FILLING 1 +#define FULL 2 +#define EMPTYING 3 + +#define PORT 2 // ethernet = 2, serdes = 0 +int dsp_rx_buf, dsp_tx_buf, serdes_rx_buf, serdes_tx_buf; +int dsp_rx_idle, dsp_tx_idle, serdes_rx_idle, serdes_tx_idle; + +int buffer_state[4]; + +static void +wait_until_status_nonzero(void) +{ + while (buffer_pool_status->status == 0) + ; +} + +int +main(void) +{ + int i; + + u2_init(); + + dsp_tx_regs->freq = 0; + dsp_tx_regs->scale_iq = (1 << 16) | 1; + dsp_tx_regs->interp_rate = 8; + + // Write data to be sent into the first buffer + volatile unsigned int *buffer0 = buffer_ram(0); + volatile unsigned int *buffer1 = buffer_ram(1); + + + putstr("Starting to fill in RAM\n"); + for(i=0;i<512;i++) + buffer0[i] = i; + putstr("Filled in RAM\n"); + + buffer0[0] = 7; // start and end of buffer, send immediately + buffer0[1] = 0x0000; // start time + bp_clear_buf(0); + bp_send_from_buf(0, 1, 1, 0, 9); + while (buffer_pool_status->status == 0) + ; + while(timer_regs -> time < 0x6000) + {} + + buffer0[0] = 3; // start and end of buffer + buffer0[1] = 0x8000; // start time + bp_clear_buf(0); + bp_send_from_buf(0, 1, 1, 0, 9); + while (buffer_pool_status->status == 0) + ; + while(timer_regs -> time < 0x8400) + {} + + buffer0[0] = 3; // start and end of buffer + buffer0[1] = 0x8800; // start time + bp_clear_buf(0); + bp_send_from_buf(0, 1, 1, 0, 9); + while (buffer_pool_status->status == 0) + ; + while(timer_regs -> time < 0x9000) + {} + + buffer0[0] = 0x2; // not last + buffer0[1] = 0x9100; // start time + bp_clear_buf(0); + bp_send_from_buf(0, 1, 1, 0, 9); + while (buffer_pool_status->status == 0) + ; + buffer0[0] = 0x1; // last + buffer0[1] = 0x0000; // start time + bp_clear_buf(0); + bp_send_from_buf(0, 1, 1, 0, 9); + while (buffer_pool_status->status == 0) + ; + + + buffer0[0] = 0x3; // first and last + buffer0[1] = 0x8000; // Time in the past + bp_clear_buf(0); + bp_send_from_buf(0, 1, 1, 0, 9); + while (buffer_pool_status->status == 0) + ; + + /* + buffer0[0] = 0x2; // not last + buffer0[1] = 0x9600; // start time + bp_clear_buf(0); + bp_send_from_buf(0, 1, 1, 0, 9); + while (buffer_pool_status->status == 0) + ; + */ + + while(timer_regs -> time < 0xa000) + {} + + putstr("Done\n"); + + while(1) + {} + hal_finish(); + + // Send a bunch, let them pile up in FIFO + bp_send_from_buf(0, 2, 1, 21, 80); wait_until_status_nonzero(); + bp_clear_buf(0); + putstr("First add'l TX done\n"); + bp_send_from_buf(0, 2, 1, 81, 288); wait_until_status_nonzero(); + bp_clear_buf(0); + bp_send_from_buf(0, 2, 1, 289, 292); wait_until_status_nonzero(); + bp_clear_buf(0); + bp_send_from_buf(0, 2, 1, 293, 326); wait_until_status_nonzero(); + bp_clear_buf(0); + bp_send_from_buf(0, 2, 1, 327, 399); wait_until_status_nonzero(); + bp_clear_buf(0); + bp_send_from_buf(0, 2, 1, 400, 511); wait_until_status_nonzero(); + bp_clear_buf(0); + putstr("All add'l TX done\n"); + + bp_receive_to_buf(1, 2, 1, 21, 80); wait_until_status_nonzero(); + bp_clear_buf(1); + putstr("First add'l RX done\n"); + bp_receive_to_buf(1, 2, 1, 81, 288); wait_until_status_nonzero(); + bp_clear_buf(1); + bp_receive_to_buf(1, 2, 1, 289, 292); wait_until_status_nonzero(); + bp_clear_buf(1); + bp_receive_to_buf(1, 2, 1, 293, 326); wait_until_status_nonzero(); + bp_clear_buf(1); + bp_receive_to_buf(1, 2, 1, 327, 399); wait_until_status_nonzero(); + bp_clear_buf(1); + bp_receive_to_buf(1, 2, 1, 400, 511); wait_until_status_nonzero(); + bp_clear_buf(1); + putstr("All add'l RX done\n"); + + for(i=0;i<512;i++) + if(buffer0[i] != buffer1[i]) { + putstr("ERROR at location: "); + puthex_nl(i); + putstr("Value sent: "); + puthex_nl(buffer0[i]); + putstr("Value rcvd: "); + puthex_nl(buffer1[i]); + //break; + } + + putstr("Done Testing\n"); + + hal_finish(); + return 1; +} diff --git a/usrp2/firmware/apps/rcv_eth_packets.c b/usrp2/firmware/apps/rcv_eth_packets.c new file mode 100644 index 00000000..92e41d92 --- /dev/null +++ b/usrp2/firmware/apps/rcv_eth_packets.c @@ -0,0 +1,233 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "memcpy_wa.h" +#include +#include + + +// ---------------------------------------------------------------- + +static u2_mac_addr_t dst_mac_addr = + {{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }}; + + +// ---------------------------------------------------------------- + +#define PACKET_SIZE 1500 // bytes +#define ETH_DATA_RATE 1000000 // 1MB/s +#define ETH_PACKET_RATE (ETH_DATA_RATE/PACKET_SIZE) // 13,3333 pkts/s + +#define TIMER_RATE 100000000 // 100 MHz clock + +static int timer_delta = TIMER_RATE/ETH_PACKET_RATE; // ticks between interrupts + +static volatile bool send_packet_now = false; // timer handler sets this +static volatile bool link_is_up = false; // eth handler sets this + +int packet_number = 0; + +// ---------------------------------------------------------------- + +// debugging output on tx pins +#define LS_MASK 0xE0000 +#define LS_1000 0x80000 +#define LS_100 0x40000 +#define LS_10 0x20000 + + +/* + * Called when eth phy state changes (w/ interrupts disabled) + */ +void +link_changed_callback(int speed) +{ + int v = 0; + switch(speed){ + case 10: + v = LS_10; + link_is_up = true; + break; + + case 100: + v = LS_100; + link_is_up = true; + break; + + case 1000: + v = LS_100; + link_is_up = true; + break; + + default: + v = 0; + link_is_up = false; + break; + } + + //hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */ + + putstr("\neth link changed: speed = "); + puthex16_nl(speed); +} + +void +timer_irq_handler(unsigned irq) +{ + hal_set_timeout(timer_delta); // schedule next timeout + send_packet_now = 1; +} + + +void +buffer_irq_handler(unsigned irq) +{ + // FIXME +} + +static void +init_packet(int *buf, const u2_eth_packet_t *pkt, int bufnum) +{ + int i = 0; + int mark = ((bufnum & 0xff) << 24) | 0x005A0000; + + for (i = 0; i < BP_NLINES; i++){ + buf[i] = mark | i; + mark ^= 0x00FF0000; + } + + // copy header into buffer + memcpy_wa(buf, pkt, sizeof(*pkt)); +} + +static void +init_packets(void) +{ + int i; + + u2_eth_packet_t pkt __attribute__((aligned (4))); + + pkt.ehdr.dst = dst_mac_addr; + // src filled in by mac + pkt.ehdr.ethertype = U2_ETHERTYPE; + + // fill ALL buffers for debugging + for (i = 0; i < 8; i++) + init_packet((void *)buffer_ram(i), &pkt, i); +} + +int +main(void) +{ + u2_init(); + + int prev_leds = -1; + int new_leds = 0x00; + output_regs->leds = 0x00; + + int peak_hold_count = 0; + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + + putstr("\nrcv_eth_packets\n"); + + init_packets(); + + // pic_register_handler(IRQ_BUFFER, buffer_irq_handler); // poll for now + + // FIXME turn off timer since I don't think MTS and MFS instructions are implemented + // pic_register_handler(IRQ_TIMER, timer_irq_handler); + // hal_set_timeout(timer_delta); + + ethernet_register_link_changed_callback(link_changed_callback); + + ethernet_init(); + + //eth_mac->speed = 4; // FIXME hardcode mac speed to 1000 + + // kick off a receive + bp_receive_to_buf(2, PORT_ETH, 1, 0, 511); + + while(1){ + // u2_eth_packet_t pkt; + + new_leds = 0; + if (link_is_up) + new_leds = 0x2; + + if ((buffer_pool_status->status & (BPS_DONE_2|BPS_ERROR_2)) != 0){ + // we've got a packet! + +#if 0 + // copy to stack buffer so we can byte address it + memcpy_wa(&pkt, (void *)buffer_ram(2), sizeof(pkt)); + + putstr("Rx: src: "); + print_mac_addr(pkt.ehdr.dst_addr); + putstr(" dst: "); + print_mac_addr(pkt.ehdr.src_addr); + putstr(" ethtype: "); + puthex16(pkt.ehdr.ethertype); + putstr(" len: "); + int len = (buffer_pool_status->last_line[2] + 1) * 4; + puthex16_nl(len); +#else + volatile int *bp = buffer_ram(2); + int i; + for (i = 0; i < 16; i++){ + puthex8(i); + putchar(':'); + puthex32_nl(bp[i]); + } +#endif + + // kick off next receive + bp_clear_buf(2); + bp_receive_to_buf(2, PORT_ETH, 1, 0, 511); + + peak_hold_count = 2048 * 10; + } + + if (peak_hold_count > 0){ + peak_hold_count--; + new_leds |= 0x1; + } + + if (new_leds != prev_leds){ + prev_leds = new_leds; + output_regs->leds = new_leds; + } + } + + hal_finish(); + return 1; +} diff --git a/usrp2/firmware/apps/read_dbids.c b/usrp2/firmware/apps/read_dbids.c new file mode 100644 index 00000000..4caabd88 --- /dev/null +++ b/usrp2/firmware/apps/read_dbids.c @@ -0,0 +1,59 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + + +int main(void) +{ + u2_init(); + + puts("\nread_dbids"); + + unsigned char dbid_tx[2]; + unsigned char dbid_rx[2]; + bool ok; + + ok = eeprom_read(I2C_ADDR_TX_A, 1, dbid_tx, 2); + if (!ok){ + puts("failed to read Tx Daugherboard EEPROM"); + } + else { + putstr("Tx Daugherboard ID: "); + puthex8(dbid_tx[1]); // MSB + puthex8(dbid_tx[0]); // LSB + newline(); + } + + ok = eeprom_read(I2C_ADDR_RX_A, 1, dbid_rx, 2); + if (!ok){ + puts("failed to read Rx Daugherboard EEPROM"); + } + else { + putstr("Rx Daugherboard ID: "); + puthex8(dbid_rx[1]); // MSB + puthex8(dbid_rx[0]); // LSB + newline(); + } + + return 0; +} diff --git a/usrp2/firmware/apps/rx_only_v2.c b/usrp2/firmware/apps/rx_only_v2.c new file mode 100644 index 00000000..fc590741 --- /dev/null +++ b/usrp2/firmware/apps/rx_only_v2.c @@ -0,0 +1,263 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "memcpy_wa.h" +#include "dbsm.h" +#include "app_common_v2.h" +#include +#include +#include +#include +#include + + +#define FW_SETS_SEQNO 1 // define to 0 or 1 + +#if (FW_SETS_SEQNO) +static int fw_seqno; // used when f/w is filling in sequence numbers +#endif + +/* + * This program can respond to queries from the host + * and stream rx samples. + * + * Buffer 0 is used for rcvd frames from ethernet + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow + */ +#define CPU_RX_BUF 0 // eth -> cpu +//#define CPU_TX_BUF 1 // cpu -> eth +#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer) +#define DSP_RX_BUF_1 3 // dsp rx -> eth + + +// variables for streaming mode + +static bool streaming_p = false; +static int streaming_frame_count = 0; +#define FRAMES_PER_CMD 1000 + + +/* + * ================================================================ + * configure DSP RX double buffering state machine + * ================================================================ + */ + +// 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0) +// DSP Rx writes timestamp followed by nlines_per_frame of samples +#define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1) + +// receive from DSP +buf_cmd_args_t dsp_rx_recv_args = { + PORT_DSP, + DSP_RX_FIRST_LINE, + BP_LAST_LINE +}; + +// send to ETH +buf_cmd_args_t dsp_rx_send_args = { + PORT_ETH, + 0, // starts with ethernet header in line 0 + 0, // filled in from list_line register +}; + +dbsm_t dsp_rx_sm; // the state machine + +// ---------------------------------------------------------------- + + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +void link_changed_callback(int speed); +static volatile bool link_is_up = false; // eth handler sets this + + +void +start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p) +{ + host_mac_addr = *host; // remember who we're sending to + + /* + * Construct ethernet header and word0 and preload into two buffers + */ + u2_eth_packet_t pkt; + memset(&pkt, 0, sizeof(pkt)); + pkt.ehdr.dst = *host; + pkt.ehdr.ethertype = U2_ETHERTYPE; + u2p_set_word0(&pkt.fixed, 0, 0); + // DSP RX will fill in timestamp + + memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt)); + memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt)); + + + if (FW_SETS_SEQNO) + fw_seqno = 0; + + // setup RX DSP regs + dsp_rx_regs->clear_state = 1; // reset + + if (1){ // we're streaming + streaming_p = true; + streaming_frame_count = FRAMES_PER_CMD; + dsp_rx_regs->rx_command = + MK_RX_CMD(FRAMES_PER_CMD * p->items_per_frame, p->items_per_frame, + 1, 1); // set "chain" bit + + // kick off the state machine + dbsm_start(&dsp_rx_sm); + dsp_rx_regs->rx_time = 0; // enqueue first of two commands + + // make sure this one and the rest have the "now" and "chain" bits set. + dsp_rx_regs->rx_command = + MK_RX_CMD(FRAMES_PER_CMD * p->items_per_frame, p->items_per_frame, + 1, 1); + dsp_rx_regs->rx_time = 0; // enqueue second command + } +#if 0 + else { + streaming_p = false; + dsp_rx_regs->rx_command = + MK_RX_CMD(p->total_samples, p->items_per_frame, p->rx_now, 0); + + // kick off the state machine + dbsm_start(&dsp_rx_sm); + dsp_rx_regs->rx_time = p->rx_time; + } +#endif +} + + +void +stop_rx_cmd(void) +{ + streaming_p = false; + dsp_rx_regs->clear_state = 1; // flush cmd queue + bp_clear_buf(DSP_RX_BUF_0); + bp_clear_buf(DSP_RX_BUF_1); +} + +inline static void +buffer_irq_handler(unsigned irq) +{ + uint32_t status = buffer_pool_status->status; + + if (status & BPS_DONE(CPU_RX_BUF)){ // we've rcvd a frame from ethernet + bp_clear_buf(CPU_RX_BUF); + eth_pkt_inspector(0, CPU_RX_BUF); + bp_receive_to_buf(CPU_RX_BUF, PORT_ETH, 1, 0, BP_LAST_LINE); + } + if (status & BPS_ERROR(CPU_RX_BUF)){ // error from ethernet + bp_clear_buf(CPU_RX_BUF); + bp_receive_to_buf(CPU_RX_BUF, PORT_ETH, 1, 0, BP_LAST_LINE); + } + + dbsm_process_status(&dsp_rx_sm, status); + + if (status & BPS_DONE(CPU_TX_BUF)){ + bp_clear_buf(CPU_TX_BUF); + } +} + +#if (FW_SETS_SEQNO) +/* + * Debugging ONLY. This will be handled by the tx_protocol_engine. + * + * This is called when the DSP Rx chain has filled in a packet. + * We set and increment the seqno, then return false, indicating + * that we didn't handle the packet. A bit of a kludge + * but it should work. + */ +bool +fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false +{ + uint32_t *p = buffer_ram(buf_this); + uint32_t seqno = fw_seqno++; + + // KLUDGE all kinds of nasty magic numbers and embedded knowledge + uint32_t t = p[4]; + t = (t & 0xffff00ff) | ((seqno & 0xff) << 8); + p[4] = t; + + // queue up another rx command when required + if (streaming_p && --streaming_frame_count == 0){ + streaming_frame_count = FRAMES_PER_CMD; + dsp_rx_regs->rx_time = 0; + } + + return false; // we didn't handle the packet +} +#endif + + +int +main(void) +{ + u2_init(); + + putstr("\nrx_only_v2\n"); + + ethernet_register_link_changed_callback(link_changed_callback); + ethernet_init(); + + // initialize double buffering state machine for DSP RX -> Ethernet + + if (FW_SETS_SEQNO){ + dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, + &dsp_rx_recv_args, &dsp_rx_send_args, + fw_sets_seqno_inspector); + } + else { + dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, + &dsp_rx_recv_args, &dsp_rx_send_args, + dbsm_nop_inspector); + } + + // setup receive from ETH + bp_receive_to_buf(CPU_RX_BUF, PORT_ETH, 1, 0, BP_LAST_LINE); + + + while(1){ + buffer_irq_handler(0); + + int pending = pic_regs->pending; // poll for under or overrun + + if (pending & PIC_OVERRUN_INT){ + dbsm_handle_rx_overrun(&dsp_rx_sm); + pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt + putchar('O'); + } + } +} diff --git a/usrp2/firmware/apps/sd_bounce.c b/usrp2/firmware/apps/sd_bounce.c new file mode 100644 index 00000000..30e3e3fc --- /dev/null +++ b/usrp2/firmware/apps/sd_bounce.c @@ -0,0 +1,153 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Loopback SERDES to SERDES + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "nonstdio.h" +#include "memset_wa.h" +#include +#include +#include +#include +#include + + + +// ---------------------------------------------------------------- + +#define SERDES_RX_BUF_0 0 +#define SERDES_RX_BUF_1 1 + +/* + * ================================================================ + * configure SD RX double buffering state machine + * ================================================================ + */ + +// receive from SERDES +buf_cmd_args_t sd_recv_args = { + PORT_SERDES, + 0, + BP_LAST_LINE +}; + +// send to SERDES +buf_cmd_args_t sd_send_args = { + PORT_SERDES, + 0, // starts with packet in line 0 + 0, // filled in from list_line register +}; + +dbsm_t sd_sm; // the state machine + + + + +// ---------------------------------------------------------------- + +#if 0 +static bool +check_packet(int *buf, int nlines) +{ + bool ok = true; + int i = 0; + for (i = 0; i < nlines; i++){ + int expected = ((2*i + 0) << 16) | (2*i+1); + if (buf[i] != expected){ + ok = false; + printf("buf[%d] = 0x%x expected = 0x%x\n", i, buf[i], expected); + } + } + return ok; +} + +static void +zero_buffer(int bufno) +{ + memset_wa(buffer_ram(bufno), 0, BP_NLINES * 4); +} +#endif + + +bool +sd_rx_inspector(dbsm_t *sm, int buf_this) +{ + hal_toggle_leds(0x2); + +#if 0 + int last_line = buffer_pool_status->last_line[buf_this]; + bool ok = check_packet(buffer_ram(buf_this), last_line); + static int good = 0; + static int bad = 0; + + if (ok) + good++; + else + bad++; + + if(good+bad == 10000) { + printf("Good %d\tBad %d\n",good,bad); + good = 0; + bad = 0; + } +#endif + + return false; +} + + +inline static void +buffer_irq_handler(void) +{ + uint32_t status = buffer_pool_status->status; + dbsm_process_status(&sd_sm, status); +} + + +int +main(void) +{ + u2_init(); + + putstr("\nsd_bounce\n"); + + // Get our clock from the mimo interface + clocks_mimo_config(MC_WE_LOCK_TO_MIMO); + + dbsm_init(&sd_sm, SERDES_RX_BUF_0, + &sd_recv_args, &sd_send_args, + sd_rx_inspector); + + // kick off the state machine + dbsm_start(&sd_sm); + + while(1){ + buffer_irq_handler(); + } +} diff --git a/usrp2/firmware/apps/sd_gentest.c b/usrp2/firmware/apps/sd_gentest.c new file mode 100644 index 00000000..4824f03f --- /dev/null +++ b/usrp2/firmware/apps/sd_gentest.c @@ -0,0 +1,269 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "nonstdio.h" +#include "memset_wa.h" +#include +#include +#include +#include +#include + +// ---------------------------------------------------------------- + +int packet_number = 0; +volatile bool send_packet_now = 0; + +#define SERDES_TX_BUF 0 +#define SERDES_RX_BUF 1 + + +#define NLINES_PER_PKT 380 + + +// ---------------------------------------------------------------- + +//static int timer_delta = (int)(MASTER_CLK_RATE * 100e-6); +static int timer_delta = 1000000; // .01 second + +void +timer_irq_handler(unsigned irq) +{ + hal_set_timeout(timer_delta); // schedule next timeout + send_packet_now = true; +} + + +static void +init_packet(int *buf) +{ + int i = 0; + for (i = 0; i < BP_NLINES; i++){ + buf[i] = ((2*i + 0) << 16) | (2*i+1); + } +} + +static bool +check_packet(int *buf, int nlines) +{ + bool ok = true; + int i = 0; + for (i = 0; i < nlines; i++){ + int expected = ((2*i + 0) << 16) | (2*i+1); + if (buf[i] != expected){ + ok = false; + printf("buf[%d] = 0x%x expected = 0x%x\n", i, buf[i], expected); + } + } + return ok; +} + +static void +zero_buffer(int bufno) +{ + memset_wa(buffer_ram(bufno), 0, BP_NLINES * 4); +} + +static void +init_packets(void) +{ + // init just the one we're using + init_packet(buffer_ram(SERDES_TX_BUF)); +} + +int +main(void) +{ + u2_init(); + + // We're free running and provide clock to the MIMO interface + clocks_mimo_config(MC_WE_DONT_LOCK | MC_PROVIDE_CLK_TO_MIMO); + + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + // output_regs->debug_mux_ctrl = 1; + // hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + // hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + + putstr("\nsd_gentest\n"); + + // Set up serdes (already enabled) + //output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN | SERDES_LOOPEN); + //output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN); + + init_packets(); + + // pic_register_handler(IRQ_TIMER, timer_irq_handler); + + //if (hwconfig_simulation_p()) + // timer_delta = sim_timer_delta; + + // start a receive from sd + zero_buffer(SERDES_RX_BUF); + bp_receive_to_buf(SERDES_RX_BUF, PORT_SERDES, 1, 0, BP_LAST_LINE); + + // fire off the first packet + bp_send_from_buf(SERDES_TX_BUF, PORT_SERDES, 1, 0, NLINES_PER_PKT); + hal_set_timeout(timer_delta); + int ready_to_send = 0; + + int counter __attribute__((unused)) = 0; + int sent = 1; + int txerr = 0; + int rxerr = 0; + int rcvd = 0; + int rxcrc = 0; + int sent_acc = 0; + int txerr_acc = 0; + int rxerr_acc = 0; + int rcvd_acc = 0; + int rxcrc_acc = 0; + +#define EXPECTING_PKT() ((counter & 0x1) == 0) +#define SEND_PKT() ((counter & 0x1) != 0) + + bool got_packet = false; + + while(1){ + uint32_t status = buffer_pool_status->status; + + if (status & (BPS_DONE(SERDES_RX_BUF))){ + bp_clear_buf(SERDES_RX_BUF); + got_packet = true; + + //hal_toggle_leds(0x2); + + // check packet + int last_line = buffer_pool_status->last_line[SERDES_RX_BUF]-1; + bool ok = check_packet(buffer_ram(SERDES_RX_BUF), last_line); + + if (ok) { + rcvd++; + //putchar('r'); + } + else { + rcvd++; + rxcrc++; + //putchar('P'); + } + // start a receive from sd + zero_buffer(SERDES_RX_BUF); + bp_receive_to_buf(SERDES_RX_BUF, PORT_SERDES, 1, 0, BP_LAST_LINE); + } + + if (status & (BPS_ERROR(SERDES_RX_BUF))){ + bp_clear_buf(SERDES_RX_BUF); + got_packet = true; + rcvd++; + rxerr++; + //putchar('E'); + + // start a receive from sd + zero_buffer(SERDES_RX_BUF); + bp_receive_to_buf(SERDES_RX_BUF, PORT_SERDES, 1, 0, BP_LAST_LINE); + } + + if (status & (BPS_DONE(SERDES_TX_BUF))){ + bp_clear_buf(SERDES_TX_BUF); + //putchar('t'); + bp_send_from_buf(SERDES_TX_BUF, PORT_SERDES, 1, 0, NLINES_PER_PKT); + //mdelay(1); + int i; + for (i = 0; i < 50; i++){ + asm volatile ("or r0, r0, r0\n\ + or r0, r0, r0\n \ + or r0, r0, r0\n \ + or r0, r0, r0\n \ + or r0, r0, r0\n \ + or r0, r0, r0\n \ + or r0, r0, r0\n"); + } + sent ++; + ready_to_send = 1; + //hal_toggle_leds(0x1); + } + + if (status & BPS_ERROR(SERDES_TX_BUF)){ + bp_clear_buf(SERDES_TX_BUF); + sent++; + txerr++; + ready_to_send = 1; + //putchar('X'); + } + + if(sent >=1000) { + printf("Status\tSENT %d\tTXERR %d\t",sent,txerr); + printf("RX %d\tERR %d\tCRC %d\tMISSED %d\n",rcvd, rxerr, rxcrc, sent-rcvd); + sent_acc += sent; sent = 0; + txerr_acc += txerr; txerr = 0; + rcvd_acc += rcvd; rcvd = 0; + rxerr_acc += rxerr; rxerr = 0; + rxcrc_acc += rxcrc; rxcrc = 0; + } + + if(sent_acc >=10000) { + printf("\nOverall\tSENT %d\tTXERR %d\t",sent_acc,txerr_acc); + printf("RX %d\tERR %d\tCRC %d\tMISSED %d\n\n",rcvd_acc, rxerr_acc, rxcrc_acc, sent_acc-rcvd_acc); + sent_acc = 0; + txerr_acc = 0; + rcvd_acc = 0; + rxerr_acc = 0; + rxcrc_acc = 0; + } +#if 0 + int pending = pic_regs->pending; + if (pending & PIC_TIMER_INT){ + hal_set_timeout(timer_delta); + + /* + if (EXPECTING_PKT()){ + if (!got_packet) + putchar('T'); + got_packet = false; + } + + if (SEND_PKT()){ + if (status & BPS_IDLE(SERDES_TX_BUF)) + bp_send_from_buf(SERDES_TX_BUF, PORT_SERDES, 1, 0, NLINES_PER_PKT); + } + counter++; + */ + + putchar('T'); + if(ready_to_send) { + bp_send_from_buf(SERDES_TX_BUF, PORT_SERDES, 1, 0, NLINES_PER_PKT); + counter++; + ready_to_send = 0; + } + + pic_regs->pending = PIC_TIMER_INT; // clear pending interrupt + } +#endif + } + + return 0; +} diff --git a/usrp2/firmware/apps/serdes_to_dsp.c b/usrp2/firmware/apps/serdes_to_dsp.c new file mode 100644 index 00000000..ff226bd9 --- /dev/null +++ b/usrp2/firmware/apps/serdes_to_dsp.c @@ -0,0 +1,188 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "app_common.h" +#include +#include +#include +#include + + +/* + * This program can respond to queries from the host + * and stream rx samples. + * + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow + * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow + */ +//#define CPU_RX_BUF 0 // eth -> cpu +//#define CPU_TX_BUF 1 // cpu -> eth + +#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer) +#define DSP_RX_BUF_1 3 // dsp rx -> eth +#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer) +#define DSP_TX_BUF_1 5 // eth -> dsp tx + +/* + * ================================================================ + * configure DSP TX double buffering state machine + * ================================================================ + */ + +// 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp) +// DSP Tx reads word0 (flags) + timestamp followed by samples + +#define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4) + +// Receive from ethernet +buf_cmd_args_t dsp_tx_recv_args = { + PORT_SERDES, + 0, + BP_LAST_LINE +}; + +// send to DSP Tx +buf_cmd_args_t dsp_tx_send_args = { + PORT_DSP, + DSP_TX_FIRST_LINE, // starts just past transport header + 0 // filled in from last_line register +}; + +dbsm_t dsp_tx_sm; // the state machine + + +// ---------------------------------------------------------------- + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +void +start_rx_cmd(const u2_mac_addr_t *host, op_start_rx_t *p) +{ +} + +void +stop_rx_cmd(void) +{ +} + +static void +setup_tx() +{ + dsp_tx_regs->clear_state = 1; + bp_clear_buf(DSP_TX_BUF_0); + bp_clear_buf(DSP_TX_BUF_1); + + int tx_scale = 256; + int interp = 32; + + op_config_tx_t def_config; + memset(&def_config, 0, sizeof(def_config)); + def_config.phase_inc = 408021893; // 9.5 MHz [2**32 * fc/fsample] + def_config.scale_iq = (tx_scale << 16) | tx_scale; + def_config.interp = interp; + + // setup Tx DSP regs + config_tx_cmd(&def_config); +} + + +inline static void +buffer_irq_handler(unsigned irq) +{ + //hal_toggle_leds(0x2); + + uint32_t status = buffer_pool_status->status; + + dbsm_process_status(&dsp_tx_sm, status); + + if (status & BPS_DONE(CPU_TX_BUF)){ + bp_clear_buf(CPU_TX_BUF); + } +} + +int +main(void) +{ + u2_init(); + + // Get our clock from the mimo interface + + // if(I WANT TO LOCK TO A REFERENCE CLOCK) + // Reg 8, Charge pump on, dig lock det, positive PFD, 47 + ad9510_write_reg(0x08, 0x47); + ad9510_write_reg(0x5A, 0x01); // Update Regs + // if (LOCK_TO_MIMO_REF) + + // Turn on ref output and choose the MIMO connector + output_regs->clk_ctrl = 0x15; + // Turn on ref output and choose the SMA connector + //output_regs->clk_ctrl = 0x14; + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + + putstr("\nserdes_to_dsp\n"); + + ethernet_register_link_changed_callback(link_changed_callback); + ethernet_init(); + + + // initialize double buffering state machine for ethernet -> DSP Tx + + dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, + &dsp_tx_recv_args, &dsp_tx_send_args, + eth_pkt_inspector); + + // program tx registers + setup_tx(); + + // kick off the state machine + dbsm_start(&dsp_tx_sm); + + while(1){ + buffer_irq_handler(0); + + int pending = pic_regs->pending; // poll for under or overrun + + if (pending & PIC_UNDERRUN_INT){ + dbsm_handle_tx_underrun(&dsp_tx_sm); + pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt + putchar('U'); + } + } +} + diff --git a/usrp2/firmware/apps/serdes_txrx.c b/usrp2/firmware/apps/serdes_txrx.c new file mode 100644 index 00000000..8f28a84f --- /dev/null +++ b/usrp2/firmware/apps/serdes_txrx.c @@ -0,0 +1,346 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "app_common_v2.h" +#include "memcpy_wa.h" +#include "clocks.h" +#include +#include +#include + + +#define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now) + +#if (FW_SETS_SEQNO) +static int fw_seqno; // used when f/w is filling in sequence numbers +#endif + + +/* + * Full duplex Tx and Rx between serdes and DSP pipelines + * + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to serdes flow + * Buffers 4 and 5 are used to double-buffer the serdes to DSP Tx flow + */ +//#define CPU_RX_BUF 0 // eth -> cpu + +#define DSP_RX_BUF_0 2 // dsp rx -> serdes (double buffer) +#define DSP_RX_BUF_1 3 // dsp rx -> serdes +#define DSP_TX_BUF_0 4 // serdes -> dsp tx (double buffer) +#define DSP_TX_BUF_1 5 // serdes -> dsp tx + +/* + * ================================================================== + * configure DSP TX double buffering state machine (serdes -> dsp) + * ================================================================== + */ + +// 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp) +// DSP Tx reads word0 (flags) + timestamp followed by samples + +#define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4) + +// Receive from serdes +buf_cmd_args_t dsp_tx_recv_args = { + PORT_SERDES, + 0, + BP_LAST_LINE +}; + +// send to DSP Tx +buf_cmd_args_t dsp_tx_send_args = { + PORT_DSP, + DSP_TX_FIRST_LINE, // starts just past transport header + 0 // filled in from last_line register +}; + +dbsm_t dsp_tx_sm; // the state machine + +/* + * ================================================================= + * configure DSP RX double buffering state machine (dsp -> serdes) + * ================================================================= + */ + +// 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0) +// DSP Rx writes timestamp followed by nlines_per_frame of samples +#define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1) + +// receive from DSP +buf_cmd_args_t dsp_rx_recv_args = { + PORT_DSP, + DSP_RX_FIRST_LINE, + BP_LAST_LINE +}; + +// send to serdes +buf_cmd_args_t dsp_rx_send_args = { + PORT_SERDES, + 0, // starts with ethernet header in line 0 + 0, // filled in from list_line register +}; + +dbsm_t dsp_rx_sm; // the state machine + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +// variables for streaming mode + +static bool streaming_p = false; +static unsigned int streaming_items_per_frame = 0; +static int streaming_frame_count = 0; +#define FRAMES_PER_CMD 1000 + + +// ---------------------------------------------------------------- + + +static void +restart_streaming(void) +{ + // setup RX DSP regs + dsp_rx_regs->clear_state = 1; // reset + + streaming_p = true; + streaming_frame_count = FRAMES_PER_CMD; + + dsp_rx_regs->rx_command = + MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame, + streaming_items_per_frame, + 1, 1); // set "chain" bit + + // kick off the state machine + dbsm_start(&dsp_rx_sm); + + dsp_rx_regs->rx_time = 0; // enqueue first of two commands + + // make sure this one and the rest have the "now" and "chain" bits set. + dsp_rx_regs->rx_command = + MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame, + streaming_items_per_frame, + 1, 1); + + dsp_rx_regs->rx_time = 0; // enqueue second command +} + +void +start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p) +{ + host_mac_addr = *host; // remember who we're sending to + + /* + * Construct ethernet header and word0 and preload into two buffers + */ + u2_eth_packet_t pkt; + memset(&pkt, 0, sizeof(pkt)); + pkt.ehdr.dst = *host; + pkt.ehdr.ethertype = U2_ETHERTYPE; + u2p_set_word0(&pkt.fixed, 0, 0); + // DSP RX will fill in timestamp + + memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt)); + memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt)); + + + if (FW_SETS_SEQNO) + fw_seqno = 0; + + streaming_items_per_frame = p->items_per_frame; + restart_streaming(); +} + + +void +stop_rx_cmd(void) +{ + streaming_p = false; + dsp_rx_regs->clear_state = 1; // flush cmd queue + bp_clear_buf(DSP_RX_BUF_0); + bp_clear_buf(DSP_RX_BUF_1); +} + + +static void +setup_tx() +{ + dsp_tx_regs->clear_state = 1; + bp_clear_buf(DSP_TX_BUF_0); + bp_clear_buf(DSP_TX_BUF_1); + + int tx_scale = 256; + int interp = 32; + + // setup some defaults + + dsp_tx_regs->freq = 0; + dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale; + dsp_tx_regs->interp_rate = interp; +} + + +#if (FW_SETS_SEQNO) +/* + * Debugging ONLY. This will be handled by the tx_protocol_engine. + * + * This is called when the DSP Rx chain has filled in a packet. + * We set and increment the seqno, then return false, indicating + * that we didn't handle the packet. A bit of a kludge + * but it should work. + */ +bool +fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false +{ + uint32_t *p = buffer_ram(buf_this); + uint32_t seqno = fw_seqno++; + + // KLUDGE all kinds of nasty magic numbers and embedded knowledge + uint32_t t = p[4]; + t = (t & 0xffff00ff) | ((seqno & 0xff) << 8); + p[4] = t; + + // queue up another rx command when required + if (streaming_p && --streaming_frame_count == 0){ + streaming_frame_count = FRAMES_PER_CMD; + dsp_rx_regs->rx_time = 0; + } + + return false; // we didn't handle the packet +} +#endif + + +inline static void +buffer_irq_handler(unsigned irq) +{ + uint32_t status = buffer_pool_status->status; + + dbsm_process_status(&dsp_tx_sm, status); + dbsm_process_status(&dsp_rx_sm, status); +} + +int +main(void) +{ + u2_init(); + + putstr("\nSERDES TxRx\n"); + + cpu_tx_buf_dest_port = PORT_SERDES; + + ethernet_register_link_changed_callback(link_changed_callback); + ethernet_init(); + + clocks_mimo_config(MC_WE_LOCK_TO_MIMO); + +#if 0 + // make bit 15 of Tx gpio's be a s/w output + hal_gpio_set_sel(GPIO_TX_BANK, 15, 's'); + hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000); +#endif + +#if 1 + output_regs->debug_mux_ctrl = 1; + hal_gpio_set_sels(GPIO_TX_BANK, "0000000000000000"); + hal_gpio_set_sels(GPIO_RX_BANK, "0000000000000000"); + hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff); + hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff); +#endif + + + // initialize double buffering state machine for ethernet -> DSP Tx + + dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, + &dsp_tx_recv_args, &dsp_tx_send_args, + eth_pkt_inspector); + + + // initialize double buffering state machine for DSP RX -> Ethernet + + if (FW_SETS_SEQNO){ + dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, + &dsp_rx_recv_args, &dsp_rx_send_args, + fw_sets_seqno_inspector); + } + else { + dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, + &dsp_rx_recv_args, &dsp_rx_send_args, + dbsm_nop_inspector); + } + + // tell app_common that this dbsm could be sending to the ethernet + ac_could_be_sending_to_eth = &dsp_rx_sm; + + + // program tx registers + setup_tx(); + + // kick off the state machine + dbsm_start(&dsp_tx_sm); + + //int which = 0; + + while(1){ + // hal_gpio_write(GPIO_TX_BANK, which, 0x8000); + // which ^= 0x8000; + + buffer_irq_handler(0); + + int pending = pic_regs->pending; // poll for under or overrun + + if (pending & PIC_UNDERRUN_INT){ + dbsm_handle_tx_underrun(&dsp_tx_sm); + pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt + putchar('U'); + } + + if (pending & PIC_OVERRUN_INT){ + dbsm_handle_rx_overrun(&dsp_rx_sm); + pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt + + // FIXME Figure out how to handle this robustly. + // Any buffers that are emptying should be allowed to drain... + + if (streaming_p){ + // restart_streaming(); + // FIXME report error + } + else { + // FIXME report error + } + putchar('O'); + } + } +} diff --git a/usrp2/firmware/apps/test1.c b/usrp2/firmware/apps/test1.c new file mode 100644 index 00000000..c3cc3be5 --- /dev/null +++ b/usrp2/firmware/apps/test1.c @@ -0,0 +1,282 @@ +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "nonstdio.h" + +// Globals +#define EMPTY 0 +#define FILLING 1 +#define FULL 2 +#define EMPTYING 3 + +#define PORT 2 // ethernet = 2, serdes = 0 +int dsp_rx_buf, dsp_tx_buf, serdes_rx_buf, serdes_tx_buf; +int dsp_rx_idle, dsp_tx_idle, serdes_rx_idle, serdes_tx_idle; + +int buffer_state[4]; + + +void double_buffering(int port); + +// +// We register this in the secondary interrupt vector. +// It's called on buffer manager interrupts +// +void +buffer_irq_handler(unsigned irq) +{ + double_buffering(PORT); +} + +int +main(void) +{ + int i; + + u2_init(); + + // Control LEDs + output_regs->leds = 0x02; + + // Turn on ADCs + output_regs->adc_ctrl = 0x0A; + + // Set up TX Chain + dsp_tx_regs->freq = 0; + dsp_tx_regs->scale_iq = (1 << 16) | 1; + dsp_tx_regs->interp_rate = 8; + + // Set up RX Chain + dsp_rx_regs->freq = 0; + dsp_rx_regs->scale_iq = (1 << 16) | 1; + dsp_rx_regs->decim_rate = 8; + + // Set up buffer control, using only 4 for now + for(i=0;i<4;i++) + buffer_state[i] = EMPTY; + + // Set up DSP RX + buffer_state[0] = FILLING; + serdes_tx_idle = 1; + bp_receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 0, use 500 lines + + //dsp_rx_regs->run_rx = 1; // Start DSP_RX + putstr("Done DSP RX setup\n"); + + // Set up serdes RX + buffer_state[2] = FILLING; + dsp_tx_idle = 1; + bp_receive_to_buf(2, PORT, 1, 5, 504); + + while (buffer_pool_status->status == 0) // wait for completion of DSP RX + ; + + putstr("Done DSP TX setup\n"); + //dsp_tx_regs->run_tx = 1; + + // register interrupt handler + pic_register_handler(IRQ_BUFFER, buffer_irq_handler); + + while (1) + ; + + hal_finish(); + return 1; +} + +void +double_buffering(int port) { + unsigned int localstatus = buffer_pool_status->status; + + if(localstatus & BPS_DONE_0) { + bp_clear_buf(0); + if(buffer_state[0] == FILLING) { + buffer_state[0] = FULL; + if(buffer_state[1] == EMPTY) { + bp_receive_to_buf(1, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500 lines + buffer_state[1] = FILLING; + } + else + dsp_rx_idle = 1; + if(serdes_tx_idle) { + serdes_tx_idle = 0; + bp_send_from_buf(0, port, 1, 10, 509); // SERDES_TX from buffer 0 + buffer_state[0] = EMPTYING; + } + } + else { // buffer was emptying + buffer_state[0] = EMPTY; + if(dsp_rx_idle) { + dsp_rx_idle = 0; + bp_receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 0, use 500 lines + buffer_state[0] = FILLING; + } + if(buffer_state[1] == FULL) { + bp_send_from_buf(1, port, 1, 10, 509); // SERDES_TX from buffer 1 + buffer_state[1] = EMPTYING; + } + else + serdes_tx_idle = 1; + } + putstr("Int Proc'ed 0\n"); + } + if(localstatus & BPS_DONE_1) { + bp_clear_buf(1); + if(buffer_state[1] == FILLING) { + buffer_state[1] = FULL; + if(buffer_state[0] == EMPTY) { + bp_receive_to_buf(0, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500 lines + buffer_state[0] = FILLING; + } + else + dsp_rx_idle = 1; + if(serdes_tx_idle) { + serdes_tx_idle = 0; + bp_send_from_buf(1, port, 1, 10, 509); // SERDES_TX from buffer 1 + buffer_state[1] = EMPTYING; + } + } + else { // buffer was emptying + buffer_state[1] = EMPTY; + if(dsp_rx_idle) { + dsp_rx_idle = 0; + bp_receive_to_buf(1, 1, 1, 10, 509); // DSP_RX to buffer 1, use 500 lines + buffer_state[1] = FILLING; + } + if(buffer_state[0] == FULL) { + bp_send_from_buf(0, port, 1, 10, 509); // SERDES_TX from buffer 0 + buffer_state[0] = EMPTYING; + } + else + serdes_tx_idle = 1; + } + putstr("Int Proc'ed 1\n"); + } + if(localstatus & BPS_DONE_2) { + bp_clear_buf(2); + if(buffer_state[2] == FILLING) { + buffer_state[2] = FULL; + if(buffer_state[3] == EMPTY) { + bp_receive_to_buf(3, port, 1, 5, 504); // SERDES_RX to buffer 3, use 500 lines + buffer_state[3] = FILLING; + } + else + serdes_rx_idle = 1; + if(dsp_tx_idle) { + dsp_tx_idle = 0; + bp_send_from_buf(2, 1, 1, 5, 504); // DSP_TX from buffer 2 + buffer_state[2] = EMPTYING; + } + } + else { // buffer was emptying + buffer_state[2] = EMPTY; + if(serdes_rx_idle) { + serdes_rx_idle = 0; + bp_receive_to_buf(2, port, 1, 5, 504); // SERDES_RX to buffer 2 + buffer_state[2] = FILLING; + } + if(buffer_state[3] == FULL) { + bp_send_from_buf(3, 1, 1, 5, 504); // DSP_TX from buffer 3 + buffer_state[3] = EMPTYING; + } + else + dsp_tx_idle = 1; + } + putstr("Int Proc'ed 2\n"); + } + if(localstatus & BPS_DONE_3) { + bp_clear_buf(3); + if(buffer_state[3] == FILLING) { + buffer_state[3] = FULL; + if(buffer_state[2] == EMPTY) { + bp_receive_to_buf(2, port, 1, 5, 504); // SERDES_RX to buffer 2, use 500 lines + buffer_state[2] = FILLING; + } + else + serdes_rx_idle = 1; + if(dsp_tx_idle) { + dsp_tx_idle = 0; + bp_send_from_buf(3, 1, 1, 5, 504); // DSP_TX from buffer 3 + buffer_state[3] = EMPTYING; + } + } + else { // buffer was emptying + buffer_state[3] = EMPTY; + if(serdes_rx_idle) { + serdes_rx_idle = 0; + bp_receive_to_buf(3, port, 1, 5, 504); // SERDES_RX to buffer 3 + buffer_state[3] = FILLING; + } + if(buffer_state[2] == FULL) { + bp_send_from_buf(2, 1, 1, 5, 504); // DSP_TX from buffer 2 + buffer_state[2] = EMPTYING; + } + else + dsp_tx_idle = 1; + } + putstr("Int Proc'ed 3\n"); + } +} + +// Spare Code + +#if 0 + // Set up LSDAC + int i = 0; + while(1) { + int command = (3 << 19) | (0 << 16) | (i & 0xffff); + spi_transact(SPI_TXONLY, SPI_SS_TX_DAC, command, 24, 1); // negate TX phase + i++; + } +#endif + +#if 0 + // Write to buffer 0 + int *buf = (int *)(BUFFER_BASE + BUFFER_0); + puthex_nl((int)buf); + + for(i=0;i. + */ + +#include +#include +#include +#include + +int +main(void) +{ + u2_init(); + + puts("\ntest_db_spi"); + + while(1){ + spi_transact(SPI_TXONLY, SPI_SS_RX_DB, 0xCC33, 16, SPIF_PUSH_FALL); + spi_transact(SPI_TXONLY, SPI_SS_TX_DB, 0x33CC, 16, SPIF_PUSH_FALL); + } +} diff --git a/usrp2/firmware/apps/test_i2c.c b/usrp2/firmware/apps/test_i2c.c new file mode 100644 index 00000000..f349ead8 --- /dev/null +++ b/usrp2/firmware/apps/test_i2c.c @@ -0,0 +1,108 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include /* FIXME */ +#include +#include +#include +#include + + + +#define ASSERT_TRUE(x) \ + do { \ + if (!(x)){ \ + printf("ASSERT_TRUE failed on line %d\n", __LINE__); \ + nerrors++; \ + } \ + } while(0) + +#define ASSERT_FALSE(x) \ + do { \ + if (x){ \ + printf("ASSERT_FALSE failed on line %d\n", __LINE__); \ + nerrors++; \ + } \ + } while(0) + + +#define BUFSIZE 128 + +int +main(void) +{ + int i; + bool ok; + int nerrors = 0; + uint8_t buf[BUFSIZE]; + int not_dev_addr = 0x35; // no device with this address on the i2c bus. + int offset; + int len; + + u2_init(); + + puts("test_i2c\n"); + + // try writing a non-existent device + buf[0] = 0xA5; + ok = i2c_write(not_dev_addr, buf, 1); + ASSERT_FALSE(ok); + + // try read from non-existent device + buf[0] = 0; + ok = i2c_read(not_dev_addr, buf, 1); + ASSERT_FALSE(ok); + + // try writing eeprom + offset = 31; + len = 8; + memset(buf, 0, sizeof(buf)); + for (i = 0; i < len; i++) + buf[i] = i; + ok = eeprom_write(I2C_ADDR_MBOARD, offset, buf, len); + ASSERT_TRUE(ok); + + // now try to read it back + offset = 31; + len = 8; + memset(buf, 0, sizeof(buf)); + ok = eeprom_read(I2C_ADDR_MBOARD, offset, buf, len); + ASSERT_TRUE(ok); + + // check result + for (i = 0; i < len; i++){ + if (buf[i] != i){ + printf("buf[%d] = %d, should be %d\n", i, buf[i], i); + nerrors++; + } + } + + if (nerrors == 0){ + output_regs->leds = 0x3; + puts("PASSED\n"); + } + else { + output_regs->leds = 0x0; + puts("FAILED\n"); + } + + hal_finish(); + return 0; +} + diff --git a/usrp2/firmware/apps/test_lsadc.c b/usrp2/firmware/apps/test_lsadc.c new file mode 100644 index 00000000..5fda29cd --- /dev/null +++ b/usrp2/firmware/apps/test_lsadc.c @@ -0,0 +1,57 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +int +main(void) +{ + u2_init(); + + puts("\ntest_lsadc"); + + uint32_t r; + + unsigned int up_counter = 0; + + while (1){ + unsigned int v; + v = up_counter; + + lsdac_write_rx(0, v << 0); + lsdac_write_rx(2, v << 1); + +#if 1 + r = lsadc_read_rx(0); + lsdac_write_rx(1, r & 0x0fff); + //puthex32_nl(r); +#endif + +#if 1 + r = lsadc_read_rx(1); + lsdac_write_rx(3, r & 0x0fff); + //puthex32_nl(r); +#endif + + up_counter++; + } +} diff --git a/usrp2/firmware/apps/test_lsdac.c b/usrp2/firmware/apps/test_lsdac.c new file mode 100644 index 00000000..8c1bf333 --- /dev/null +++ b/usrp2/firmware/apps/test_lsdac.c @@ -0,0 +1,51 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +int +main(void) +{ + u2_init(); + + puts("\ntest_lsdac"); + + unsigned int up_counter = 0; + unsigned int dn_counter = 0; + + while(1){ + unsigned int v; + v = up_counter; + lsdac_write_rx(0, v << 0); + lsdac_write_rx(1, v << 1); + lsdac_write_rx(2, v << 2); + lsdac_write_rx(3, v << 3); + + v = up_counter; + lsdac_write_tx(0, v << 0); + lsdac_write_tx(1, v << 1); + lsdac_write_tx(2, v << 2); + lsdac_write_tx(3, v << 3); + + up_counter++; + dn_counter--; + } +} diff --git a/usrp2/firmware/apps/test_phy_comm.c b/usrp2/firmware/apps/test_phy_comm.c new file mode 100644 index 00000000..7242c6fc --- /dev/null +++ b/usrp2/firmware/apps/test_phy_comm.c @@ -0,0 +1,113 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +// check communication with ethernet PHY chip + +#include "u2_init.h" +#include "memory_map.h" +#include "hal_io.h" +#include "ethernet.h" +#include "pic.h" +#include "nonstdio.h" + + +#define DELTA_T 12500000 // .125s (10ns per tick) +//#define DELTA_T 10000 + +// debugging output on tx pins +#define LS_MASK 0xE0000 +#define LS_1000 0x80000 +#define LS_100 0x40000 +#define LS_10 0x20000 + + + +#define U2_ETHERTYPE 0xBEEF + + +static volatile int led_link_up_flag = 0; + +/* + * Called when eth phy state changes (w/ interrupts disabled) + */ +void +link_changed_callback(int speed) +{ + int v = 0; + switch(speed){ + case 10: + v = LS_10; + led_link_up_flag = 0x2; + break; + + case 100: + v = LS_100; + led_link_up_flag = 0x2; + break; + + case 1000: + v = LS_100; + led_link_up_flag = 0x2; + break; + + default: + v = 0; + led_link_up_flag = 0; + break; + } + + //hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */ + + putstr("\neth link changed: speed = "); + puthex_nl(speed); +} + +void +timer_handler(unsigned irq) +{ + static int led_counter = 0; + + hal_set_timeout(DELTA_T); // schedule next timeout + output_regs->leds = (led_counter++ & 0x1) | led_link_up_flag; +} + +int +main(void) +{ + u2_init(); + + putstr("\n test_phy_comm\n"); + + pic_register_handler(IRQ_TIMER, timer_handler); + hal_set_timeout(DELTA_T); // schedule timeout + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + + ethernet_register_link_changed_callback(link_changed_callback); + + output_regs->phy_ctrl = 1; /* reset the eth PHY */ + output_regs->phy_ctrl = 0; + + ethernet_init(); + + while(1) + ; + + return 0; +} diff --git a/usrp2/firmware/apps/test_serdes.c b/usrp2/firmware/apps/test_serdes.c new file mode 100644 index 00000000..fadf4d86 --- /dev/null +++ b/usrp2/firmware/apps/test_serdes.c @@ -0,0 +1,192 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "memcpy_wa.h" +#include +#include + + +// ---------------------------------------------------------------- + +static u2_mac_addr_t dst_mac_addr = + {{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }}; + +// ---------------------------------------------------------------- + +// #define PACKET_SIZE 1500 // bytes +// #define ETH_DATA_RATE 1000000 // 1MB/s +// #define ETH_PACKET_RATE (ETH_DATA_RATE/PACKET_SIZE) // 13,3333 pkts/s + +// static int timer_delta = MASTER_CLK_RATE/ETH_PACKET_RATE; // ticks between interrupts + +static int timer_delta = MASTER_CLK_RATE/1000; // tick at 1kHz + +static volatile bool send_packet_now = false; // timer handler sets this +static volatile bool link_is_up = false; // eth handler sets this + +int packet_number = 0; + +// ---------------------------------------------------------------- + +// debugging output on tx pins +#define LS_MASK 0xE0000 +#define LS_1000 0x80000 +#define LS_100 0x40000 +#define LS_10 0x20000 + + +/* + * Called when eth phy state changes (w/ interrupts disabled) + */ +void +link_changed_callback(int speed) +{ + int v = 0; + switch(speed){ + case 10: + v = LS_10; + link_is_up = true; + break; + + case 100: + v = LS_100; + link_is_up = true; + break; + + case 1000: + v = LS_100; + link_is_up = true; + break; + + default: + v = 0; + link_is_up = false; + break; + } + + //hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */ + + putstr("\neth link changed: speed = "); + puthex16_nl(speed); +} + +void +timer_irq_handler(unsigned irq) +{ + hal_set_timeout(timer_delta); // schedule next timeout + send_packet_now = 1; +} + + +void +buffer_irq_handler(unsigned irq) +{ + // FIXME +} + +static void +init_packet(int *buf, const u2_eth_packet_t *pkt, int bufnum) +{ + int i = 0; + int mark = ((bufnum & 0xff) << 24) | 0x005A0000; + + for (i = 0; i < BP_NLINES; i++){ + buf[i] = mark | i; + mark ^= 0x00FF0000; + } + + // copy header into buffer + memcpy_wa(buf, pkt, sizeof(*pkt)); +} + +static void +init_packets(void) +{ + int i; + + u2_eth_packet_t pkt __attribute__((aligned (4))); + + pkt.ehdr.dst = dst_mac_addr; + // pkt.ehdr.src filled in by mac + pkt.ehdr.ethertype = U2_ETHERTYPE; + + // fill ALL buffers for debugging + for (i = 0; i < 8; i++) + init_packet((void *)buffer_ram(i), &pkt, i); +} + +static int led_counter = 0; + +int +main(void) +{ + u2_init(); + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + + putstr("\ngen_eth_packets\n"); + + // Control LEDs + output_regs->leds = 0x00; + + init_packets(); + + // pic_register_handler(IRQ_BUFFER, buffer_irq_handler); // poll for now + pic_register_handler(IRQ_TIMER, timer_irq_handler); + hal_set_timeout(timer_delta); + + ethernet_register_link_changed_callback(link_changed_callback); + + ethernet_init(); + + // eth_mac->speed = 4; // FIXME hardcode mac speed to 1000 + int i = 0; + while(1){ + if (link_is_up && send_packet_now){ + send_packet_now = false; + + // kick off the next packet + // FIXME set packet number in packet + + bp_send_from_buf(i, PORT_SERDES, 1, 0, 255); // 1KB total + + //while ((buffer_pool_status->status & (BPS_DONE_0|BPS_ERROR_0)) == 0) + while ((buffer_pool_status->status ) == 0) + ; + bp_clear_buf(i); + i++; + if(i==8) + i=0; + output_regs->leds = ((++led_counter) & 0x1) | (link_is_up ? 0x2 : 0x0); + } + } + + hal_finish(); + return 1; +} diff --git a/usrp2/firmware/apps/timer_test.c b/usrp2/firmware/apps/timer_test.c new file mode 100644 index 00000000..7c1e4644 --- /dev/null +++ b/usrp2/firmware/apps/timer_test.c @@ -0,0 +1,59 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "u2_init.h" +#include "memory_map.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "nonstdio.h" + + +#define DELTA_T 500 // 5 us (10ns per tick) + + +void +timer_handler(unsigned irq) +{ + int t = timer_regs->time; + timer_regs->time = t + DELTA_T; + + putstr("Tick: "); + puthex_nl(t); +} + +int +main(void) +{ + u2_init(); + + // setup timer + + putstr("Setting up timer\n"); + pic_register_handler(IRQ_TIMER, timer_handler); + + int t = timer_regs->time; + timer_regs->time = t + DELTA_T; + + while (1) + ; + + putstr("Done Testing\n"); + + hal_finish(); + return 1; +} diff --git a/usrp2/firmware/apps/tx_only_v2.c b/usrp2/firmware/apps/tx_only_v2.c new file mode 100644 index 00000000..f1e788db --- /dev/null +++ b/usrp2/firmware/apps/tx_only_v2.c @@ -0,0 +1,171 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "app_common_v2.h" +#include +#include +#include +#include +#include + + +/* + * This program can respond to queries from the host + * and stream rx samples. + * + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow + * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow + */ +//#define CPU_RX_BUF 0 // eth -> cpu +//#define CPU_TX_BUF 1 // cpu -> eth + +#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer) +#define DSP_RX_BUF_1 3 // dsp rx -> eth +#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer) +#define DSP_TX_BUF_1 5 // eth -> dsp tx + +/* + * ================================================================ + * configure DSP TX double buffering state machine + * ================================================================ + */ + +// 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp) +// DSP Tx reads word0 (flags) + timestamp followed by samples + +#define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4) + +// Receive from ethernet +buf_cmd_args_t dsp_tx_recv_args = { + PORT_ETH, + 0, + BP_LAST_LINE +}; + +// send to DSP Tx +buf_cmd_args_t dsp_tx_send_args = { + PORT_DSP, + DSP_TX_FIRST_LINE, // starts just past transport header + 0 // filled in from last_line register +}; + +dbsm_t dsp_tx_sm; // the state machine + + +// ---------------------------------------------------------------- + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +void +start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p) +{ + // FIXME nop +} + + +void +stop_rx_cmd(void) +{ + // FIXME nop +} + + +static void +setup_tx() +{ + dsp_tx_regs->clear_state = 1; + bp_clear_buf(DSP_TX_BUF_0); + bp_clear_buf(DSP_TX_BUF_1); + + int tx_scale = 256; + int interp = 32; + + // setup some defaults + + dsp_tx_regs->freq = 0; + dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale; + dsp_tx_regs->interp_rate = interp; +} + + +inline static void +buffer_irq_handler(unsigned irq) +{ + //hal_toggle_leds(0x2); + + uint32_t status = buffer_pool_status->status; + + dbsm_process_status(&dsp_tx_sm, status); + + if (status & BPS_DONE(CPU_TX_BUF)){ + bp_clear_buf(CPU_TX_BUF); + } +} + +int +main(void) +{ + u2_init(); + + putstr("\ntx_only_v2\n"); + + ethernet_register_link_changed_callback(link_changed_callback); + ethernet_init(); + + // initialize double buffering state machine for ethernet -> DSP Tx + + dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, + &dsp_tx_recv_args, &dsp_tx_send_args, + eth_pkt_inspector); + + // program tx registers + setup_tx(); + + // kick off the state machine + dbsm_start(&dsp_tx_sm); + + while(1){ + buffer_irq_handler(0); + + int pending = pic_regs->pending; // poll for under or overrun + + if (pending & PIC_UNDERRUN_INT){ + dbsm_handle_tx_underrun(&dsp_tx_sm); + pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt + putchar('U'); + } + } +} diff --git a/usrp2/firmware/apps/tx_standalone.c b/usrp2/firmware/apps/tx_standalone.c new file mode 100644 index 00000000..25ba8fd4 --- /dev/null +++ b/usrp2/firmware/apps/tx_standalone.c @@ -0,0 +1,338 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "memcpy_wa.h" +#include "dbsm.h" +#include +#include +#include + +#define _AL4 __attribute__((aligned (4))) + +#define USE_BUFFER_INTERRUPT 0 // 0 or 1 + + +static int timer_delta = MASTER_CLK_RATE/1000; // tick at 1kHz + +/* + * This program can respond to queries from the host + * and stream rx samples. + * + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow + * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow + */ +//#define CPU_RX_BUF 0 // eth -> cpu +#define CPU_TX_BUF 1 // cpu -> eth + +#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer) +#define DSP_RX_BUF_1 3 // dsp rx -> eth +#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer) +#define DSP_TX_BUF_1 5 // eth -> dsp tx + + +/* + * ================================================================ + * configure DSP RX double buffering state machine + * ================================================================ + */ + + +// 4 lines of ethernet hdr + 1 line (word0) +// DSP Rx writes timestamp followed by nlines_per_frame of samples +#define DSP_RX_FIRST_LINE 5 +#define DSP_RX_SAMPLES_PER_FRAME 128 +#define DSP_RX_EXTRA_LINES 1 // writes timestamp + +// Receive from DSP Rx +buf_cmd_args_t dsp_rx_recv_args = { + PORT_DSP, + DSP_RX_FIRST_LINE, + BP_LAST_LINE +}; + +// send to ethernet +buf_cmd_args_t dsp_rx_send_args = { + PORT_ETH, + 0, // starts with ethernet header in line 0 + 0, // filled in from last_line register +}; + +dbsm_t dsp_rx_sm; // the state machine + +/* + * ================================================================ + * configure DSP TX double buffering state machine + * ================================================================ + */ + +// 4 lines of ethernet hdr + 2 lines (word0 + timestamp) +// DSP Tx reads word0 (flags) + timestamp followed by samples + +#define DSP_TX_FIRST_LINE 4 +#define DSP_TX_SAMPLES_PER_FRAME 250 // not used except w/ debugging +#define DSP_TX_EXTRA_LINES 2 // reads word0 + timestamp + +// Receive from ethernet +buf_cmd_args_t dsp_tx_recv_args = { + PORT_ETH, + 0, + BP_LAST_LINE +}; + +// send to DSP Tx +buf_cmd_args_t dsp_tx_send_args = { + PORT_DSP, + DSP_TX_FIRST_LINE, // starts just past ethernet header + 0 // filled in from last_line register +}; + +dbsm_t dsp_tx_sm; // the state machine + +/* + * send constant buffer to DSP TX + */ +static inline void +SEND_CONST_TO_DSP_TX(void) +{ + bp_send_from_buf(DSP_TX_BUF_0, PORT_DSP, 1, + DSP_TX_FIRST_LINE, + DSP_TX_FIRST_LINE + DSP_TX_EXTRA_LINES + DSP_TX_SAMPLES_PER_FRAME - 1); +} + +// ---------------------------------------------------------------- + + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +void link_changed_callback(int speed); +static volatile bool link_is_up = false; // eth handler sets this + + +void +timer_irq_handler(unsigned irq) +{ + hal_set_timeout(timer_delta); // schedule next timeout +} + +// Tx DSP underrun +void +underrun_irq_handler(unsigned irq) +{ + dsp_tx_regs->clear_state = 1; + bp_clear_buf(DSP_TX_BUF_0); + bp_clear_buf(DSP_TX_BUF_1); + dbsm_stop(&dsp_tx_sm); + + // FIXME anything else? + + putstr("\nirq: underrun\n"); +} + +// Rx DSP overrun +void +overrun_irq_handler(unsigned irq) +{ + dsp_rx_regs->clear_state = 1; + bp_clear_buf(DSP_RX_BUF_0); + bp_clear_buf(DSP_RX_BUF_1); + dbsm_stop(&dsp_rx_sm); + + // FIXME anything else? + + putstr("\nirq: overrun\n"); +} + +static void +start_tx_transfers(void) +{ + bp_clear_buf(DSP_TX_BUF_0); // FIXME, really goes in state machine + bp_clear_buf(DSP_TX_BUF_1); + + // fill everything with a constant 32k + 0j + + uint32_t const_sample = (32000 << 16) | 0; + int i; + for (i = 0; i < BP_NLINES; i++){ + buffer_ram(DSP_TX_BUF_0)[i] = const_sample; + buffer_ram(DSP_TX_BUF_1)[i] = const_sample; + } + + /* + * Construct ethernet header and word0 and preload into two buffers + */ + u2_eth_packet_t pkt; + memset(&pkt, 0, sizeof(pkt)); + //pkt.ehdr.dst = *host; + pkt.ehdr.ethertype = U2_ETHERTYPE; + u2p_set_word0(&pkt.fixed, + U2P_TX_IMMEDIATE | U2P_TX_START_OF_BURST, 0); + u2p_set_timestamp(&pkt.fixed, T_NOW); + + memcpy_wa(buffer_ram(DSP_TX_BUF_0), &pkt, sizeof(pkt)); + memcpy_wa(buffer_ram(DSP_TX_BUF_1), &pkt, sizeof(pkt)); + + + int tx_scale = 256; + + // setup Tx DSP regs + dsp_tx_regs->clear_state = 1; // reset + dsp_tx_regs->freq = 408021893; // 9.5 MHz [2**32 * fc/fsample] + dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale; + dsp_tx_regs->interp_rate = 32; + + // kick off the state machine + // dbsm_start(&dsp_rx_sm); + + SEND_CONST_TO_DSP_TX(); // send constant buffer to DSP TX +} + + +void +buffer_irq_handler(unsigned irq) +{ + uint32_t status = buffer_pool_status->status; + + if (0){ + putstr("irq: "); + puthex32(status); + putchar('\n'); + } + + if (status & BPS_ERROR_ALL){ + // FIXME rare path, handle error conditions + } + + if (status & BPS_DONE(DSP_TX_BUF_0)){ + bp_clear_buf(DSP_TX_BUF_0); + SEND_CONST_TO_DSP_TX(); + hal_toggle_leds(0x1); + } + +} + +int +main(void) +{ + u2_init(); + + // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output + //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + + putstr("\ntx_only\n"); + + // Control LEDs + hal_set_leds(0x0, 0x3); + + if (USE_BUFFER_INTERRUPT) + pic_register_handler(IRQ_BUFFER, buffer_irq_handler); + + pic_register_handler(IRQ_OVERRUN, overrun_irq_handler); + pic_register_handler(IRQ_UNDERRUN, underrun_irq_handler); + + //pic_register_handler(IRQ_TIMER, timer_irq_handler); + //hal_set_timeout(timer_delta); + + ethernet_register_link_changed_callback(link_changed_callback); + + ethernet_init(); + + // initialize double buffering state machine for DSP RX -> Ethernet + dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, + &dsp_rx_recv_args, &dsp_rx_send_args, + dbsm_nop_inspector); + + // setup receive from ETH + // bp_receive_to_buf(CPU_RX_BUF, PORT_ETH, 1, 0, BP_LAST_LINE); + +#if 0 + if (hwconfig_simulation_p()){ + // If we're simulating, pretend that we got a start command from the host + u2_mac_addr_t host = {{ 0x00, 0x0A, 0xE4, 0x3E, 0xD2, 0xD5 }}; + start_rx_cmd(&host); + } +#endif + + start_tx_transfers(); // send constant buffers to DSP TX + + while(1){ + if (!USE_BUFFER_INTERRUPT) + buffer_irq_handler(0); + } +} + +// ---------------------------------------------------------------- + +// debugging output on tx pins +#define LS_MASK 0xE0000 +#define LS_1000 0x80000 +#define LS_100 0x40000 +#define LS_10 0x20000 + +/* + * Called when eth phy state changes (w/ interrupts disabled) + */ +void +link_changed_callback(int speed) +{ + int v = 0; + switch(speed){ + case 10: + v = LS_10; + link_is_up = true; + break; + + case 100: + v = LS_100; + link_is_up = true; + break; + + case 1000: + v = LS_100; + link_is_up = true; + break; + + default: + v = 0; + link_is_up = false; + break; + } + + //hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */ + + // hal_set_leds(link_is_up ? 0x2 : 0x0, 0x2); + + printf("\neth link changed: speed = %d\n", speed); +} diff --git a/usrp2/firmware/apps/txrx.c b/usrp2/firmware/apps/txrx.c new file mode 100644 index 00000000..13aa8ba2 --- /dev/null +++ b/usrp2/firmware/apps/txrx.c @@ -0,0 +1,344 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "hal_io.h" +#include "buffer_pool.h" +#include "pic.h" +#include "bool.h" +#include "ethernet.h" +#include "nonstdio.h" +#include "usrp2_eth_packet.h" +#include "dbsm.h" +#include "app_common_v2.h" +#include "memcpy_wa.h" +#include +#include +#include + + +#define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now) + +#if (FW_SETS_SEQNO) +static int fw_seqno; // used when f/w is filling in sequence numbers +#endif + + +/* + * Full duplex Tx and Rx between ethernet and DSP pipelines + * + * Buffer 1 is used by the cpu to send frames to the host. + * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow + * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx eth flow + */ +//#define CPU_RX_BUF 0 // eth -> cpu + +#define DSP_RX_BUF_0 2 // dsp rx -> eth (double buffer) +#define DSP_RX_BUF_1 3 // dsp rx -> eth +#define DSP_TX_BUF_0 4 // eth -> dsp tx (double buffer) +#define DSP_TX_BUF_1 5 // eth -> dsp tx + +/* + * ================================================================ + * configure DSP TX double buffering state machine (eth -> dsp) + * ================================================================ + */ + +// 4 lines of ethernet hdr + 1 line transport hdr + 2 lines (word0 + timestamp) +// DSP Tx reads word0 (flags) + timestamp followed by samples + +#define DSP_TX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4) + +// Receive from ethernet +buf_cmd_args_t dsp_tx_recv_args = { + PORT_ETH, + 0, + BP_LAST_LINE +}; + +// send to DSP Tx +buf_cmd_args_t dsp_tx_send_args = { + PORT_DSP, + DSP_TX_FIRST_LINE, // starts just past transport header + 0 // filled in from last_line register +}; + +dbsm_t dsp_tx_sm; // the state machine + +/* + * ================================================================ + * configure DSP RX double buffering state machine (dsp -> eth) + * ================================================================ + */ + +// 4 lines of ethernet hdr + 1 line transport hdr + 1 line (word0) +// DSP Rx writes timestamp followed by nlines_per_frame of samples +#define DSP_RX_FIRST_LINE ((sizeof(u2_eth_hdr_t) + sizeof(u2_transport_hdr_t))/4 + 1) + +// receive from DSP +buf_cmd_args_t dsp_rx_recv_args = { + PORT_DSP, + DSP_RX_FIRST_LINE, + BP_LAST_LINE +}; + +// send to ETH +buf_cmd_args_t dsp_rx_send_args = { + PORT_ETH, + 0, // starts with ethernet header in line 0 + 0, // filled in from list_line register +}; + +dbsm_t dsp_rx_sm; // the state machine + + +// The mac address of the host we're sending to. +u2_mac_addr_t host_mac_addr; + + +// variables for streaming mode + +static bool streaming_p = false; +static unsigned int streaming_items_per_frame = 0; +static int streaming_frame_count = 0; +#define FRAMES_PER_CMD 1000 + + +// ---------------------------------------------------------------- + + +static void +restart_streaming(void) +{ + // setup RX DSP regs + dsp_rx_regs->clear_state = 1; // reset + + streaming_p = true; + streaming_frame_count = FRAMES_PER_CMD; + + dsp_rx_regs->rx_command = + MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame, + streaming_items_per_frame, + 1, 1); // set "chain" bit + + // kick off the state machine + dbsm_start(&dsp_rx_sm); + + dsp_rx_regs->rx_time = 0; // enqueue first of two commands + + // make sure this one and the rest have the "now" and "chain" bits set. + dsp_rx_regs->rx_command = + MK_RX_CMD(FRAMES_PER_CMD * streaming_items_per_frame, + streaming_items_per_frame, + 1, 1); + + dsp_rx_regs->rx_time = 0; // enqueue second command +} + +void +start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t *p) +{ + host_mac_addr = *host; // remember who we're sending to + + /* + * Construct ethernet header and word0 and preload into two buffers + */ + u2_eth_packet_t pkt; + memset(&pkt, 0, sizeof(pkt)); + pkt.ehdr.dst = *host; + pkt.ehdr.ethertype = U2_ETHERTYPE; + u2p_set_word0(&pkt.fixed, 0, 0); + // DSP RX will fill in timestamp + + memcpy_wa(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt)); + memcpy_wa(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt)); + + + if (FW_SETS_SEQNO) + fw_seqno = 0; + + streaming_items_per_frame = p->items_per_frame; + restart_streaming(); +} + + +void +stop_rx_cmd(void) +{ + streaming_p = false; + dsp_rx_regs->clear_state = 1; // flush cmd queue + bp_clear_buf(DSP_RX_BUF_0); + bp_clear_buf(DSP_RX_BUF_1); +} + + +static void +setup_tx() +{ + dsp_tx_regs->clear_state = 1; + bp_clear_buf(DSP_TX_BUF_0); + bp_clear_buf(DSP_TX_BUF_1); + + int tx_scale = 256; + int interp = 32; + + // setup some defaults + + dsp_tx_regs->freq = 0; + dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale; + dsp_tx_regs->interp_rate = interp; +} + + +#if (FW_SETS_SEQNO) +/* + * Debugging ONLY. This will be handled by the tx_protocol_engine. + * + * This is called when the DSP Rx chain has filled in a packet. + * We set and increment the seqno, then return false, indicating + * that we didn't handle the packet. A bit of a kludge + * but it should work. + */ +bool +fw_sets_seqno_inspector(dbsm_t *sm, int buf_this) // returns false +{ + uint32_t *p = buffer_ram(buf_this); + uint32_t seqno = fw_seqno++; + + // KLUDGE all kinds of nasty magic numbers and embedded knowledge + uint32_t t = p[4]; + t = (t & 0xffff00ff) | ((seqno & 0xff) << 8); + p[4] = t; + + // queue up another rx command when required + if (streaming_p && --streaming_frame_count == 0){ + streaming_frame_count = FRAMES_PER_CMD; + dsp_rx_regs->rx_time = 0; + } + + return false; // we didn't handle the packet +} +#endif + + +inline static void +buffer_irq_handler(unsigned irq) +{ + uint32_t status = buffer_pool_status->status; + + dbsm_process_status(&dsp_tx_sm, status); + dbsm_process_status(&dsp_rx_sm, status); +} + +int +main(void) +{ + u2_init(); + + putstr("\nTxRx\n"); + print_mac_addr(ethernet_mac_addr()->addr); + newline(); + + ethernet_register_link_changed_callback(link_changed_callback); + ethernet_init(); + + +#if 0 + // make bit 15 of Tx gpio's be a s/w output + hal_gpio_set_sel(GPIO_TX_BANK, 15, 's'); + hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000); +#endif + + output_regs->debug_mux_ctrl = 1; +#if 0 + hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); + hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); + hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff); + hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff); +#endif + + + // initialize double buffering state machine for ethernet -> DSP Tx + + dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, + &dsp_tx_recv_args, &dsp_tx_send_args, + eth_pkt_inspector); + + + // initialize double buffering state machine for DSP RX -> Ethernet + + if (FW_SETS_SEQNO){ + dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, + &dsp_rx_recv_args, &dsp_rx_send_args, + fw_sets_seqno_inspector); + } + else { + dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, + &dsp_rx_recv_args, &dsp_rx_send_args, + dbsm_nop_inspector); + } + + // tell app_common that this dbsm could be sending to the ethernet + ac_could_be_sending_to_eth = &dsp_rx_sm; + + + // program tx registers + setup_tx(); + + // kick off the state machine + dbsm_start(&dsp_tx_sm); + + //int which = 0; + + while(1){ + // hal_gpio_write(GPIO_TX_BANK, which, 0x8000); + // which ^= 0x8000; + + buffer_irq_handler(0); + + int pending = pic_regs->pending; // poll for under or overrun + + if (pending & PIC_UNDERRUN_INT){ + dbsm_handle_tx_underrun(&dsp_tx_sm); + pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt + putchar('U'); + } + + if (pending & PIC_OVERRUN_INT){ + dbsm_handle_rx_overrun(&dsp_rx_sm); + pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt + + // FIXME Figure out how to handle this robustly. + // Any buffers that are emptying should be allowed to drain... + + if (streaming_p){ + // restart_streaming(); + // FIXME report error + } + else { + // FIXME report error + } + putchar('O'); + } + } +} diff --git a/usrp2/firmware/bootstrap b/usrp2/firmware/bootstrap new file mode 100755 index 00000000..5b4ab09a --- /dev/null +++ b/usrp2/firmware/bootstrap @@ -0,0 +1,30 @@ +#!/bin/sh + +# Copyright 2001,2005 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. + + +rm -fr config.cache autom4te*.cache + +aclocal +autoconf +autoheader +# libtoolize --automake +automake --add-missing -Wno-portability + diff --git a/usrp2/firmware/config.guess b/usrp2/firmware/config.guess new file mode 100644 index 00000000..278f9e9e --- /dev/null +++ b/usrp2/firmware/config.guess @@ -0,0 +1,1516 @@ +#! /bin/sh +# Attempt to guess a canonical system name. +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +# 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, +# Inc. + +timestamp='2007-07-22' + +# This file is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA +# 02110-1301, USA. +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + + +# Originally written by Per Bothner . +# Please send patches to . Submit a context +# diff and a properly formatted ChangeLog entry. +# +# This script attempts to guess a canonical system name similar to +# config.sub. If it succeeds, it prints the system name on stdout, and +# exits with 0. Otherwise, it exits with 1. +# +# The plan is that this can be called by configure scripts if you +# don't specify an explicit build system type. + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] + +Output the configuration name of the system \`$me' is run on. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.guess ($timestamp) + +Originally written by Per Bothner. +Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 +Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit ;; + --version | -v ) + echo "$version" ; exit ;; + --help | --h* | -h ) + echo "$usage"; exit ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" >&2 + exit 1 ;; + * ) + break ;; + esac +done + +if test $# != 0; then + echo "$me: too many arguments$help" >&2 + exit 1 +fi + +trap 'exit 1' 1 2 15 + +# CC_FOR_BUILD -- compiler used by this script. Note that the use of a +# compiler to aid in system detection is discouraged as it requires +# temporary files to be created and, as you can see below, it is a +# headache to deal with in a portable fashion. + +# Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still +# use `HOST_CC' if defined, but it is deprecated. + +# Portable tmp directory creation inspired by the Autoconf team. + +set_cc_for_build=' +trap "exitcode=\$?; (rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null) && exit \$exitcode" 0 ; +trap "rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null; exit 1" 1 2 13 15 ; +: ${TMPDIR=/tmp} ; + { tmp=`(umask 077 && mktemp -d "$TMPDIR/cgXXXXXX") 2>/dev/null` && test -n "$tmp" && test -d "$tmp" ; } || + { test -n "$RANDOM" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir $tmp) ; } || + { tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir $tmp) && echo "Warning: creating insecure temp directory" >&2 ; } || + { echo "$me: cannot create a temporary directory in $TMPDIR" >&2 ; exit 1 ; } ; +dummy=$tmp/dummy ; +tmpfiles="$dummy.c $dummy.o $dummy.rel $dummy" ; +case $CC_FOR_BUILD,$HOST_CC,$CC in + ,,) echo "int x;" > $dummy.c ; + for c in cc gcc c89 c99 ; do + if ($c -c -o $dummy.o $dummy.c) >/dev/null 2>&1 ; then + CC_FOR_BUILD="$c"; break ; + fi ; + done ; + if test x"$CC_FOR_BUILD" = x ; then + CC_FOR_BUILD=no_compiler_found ; + fi + ;; + ,,*) CC_FOR_BUILD=$CC ;; + ,*,*) CC_FOR_BUILD=$HOST_CC ;; +esac ; set_cc_for_build= ;' + +# This is needed to find uname on a Pyramid OSx when run in the BSD universe. +# (ghazi@noc.rutgers.edu 1994-08-24) +if (test -f /.attbin/uname) >/dev/null 2>&1 ; then + PATH=$PATH:/.attbin ; export PATH +fi + +UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown +UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown +UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown +UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown + +# Note: order is significant - the case branches are not exclusive. + +case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in + *:NetBSD:*:*) + # NetBSD (nbsd) targets should (where applicable) match one or + # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, + # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently + # switched to ELF, *-*-netbsd* would select the old + # object file format. This provides both forward + # compatibility and a consistent mechanism for selecting the + # object file format. + # + # Note: NetBSD doesn't particularly care about the vendor + # portion of the name. We always set it to "unknown". + sysctl="sysctl -n hw.machine_arch" + UNAME_MACHINE_ARCH=`(/sbin/$sysctl 2>/dev/null || \ + /usr/sbin/$sysctl 2>/dev/null || echo unknown)` + case "${UNAME_MACHINE_ARCH}" in + armeb) machine=armeb-unknown ;; + arm*) machine=arm-unknown ;; + sh3el) machine=shl-unknown ;; + sh3eb) machine=sh-unknown ;; + sh5el) machine=sh5le-unknown ;; + *) machine=${UNAME_MACHINE_ARCH}-unknown ;; + esac + # The Operating System including object format, if it has switched + # to ELF recently, or will in the future. + case "${UNAME_MACHINE_ARCH}" in + arm*|i386|m68k|ns32k|sh3*|sparc|vax) + eval $set_cc_for_build + if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep __ELF__ >/dev/null + then + # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). + # Return netbsd for either. FIX? + os=netbsd + else + os=netbsdelf + fi + ;; + *) + os=netbsd + ;; + esac + # The OS release + # Debian GNU/NetBSD machines have a different userland, and + # thus, need a distinct triplet. However, they do not need + # kernel version information, so it can be replaced with a + # suitable tag, in the style of linux-gnu. + case "${UNAME_VERSION}" in + Debian*) + release='-gnu' + ;; + *) + release=`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'` + ;; + esac + # Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM: + # contains redundant information, the shorter form: + # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. + echo "${machine}-${os}${release}" + exit ;; + *:OpenBSD:*:*) + UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} + exit ;; + *:ekkoBSD:*:*) + echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE} + exit ;; + *:SolidBSD:*:*) + echo ${UNAME_MACHINE}-unknown-solidbsd${UNAME_RELEASE} + exit ;; + macppc:MirBSD:*:*) + echo powerpc-unknown-mirbsd${UNAME_RELEASE} + exit ;; + *:MirBSD:*:*) + echo ${UNAME_MACHINE}-unknown-mirbsd${UNAME_RELEASE} + exit ;; + alpha:OSF1:*:*) + case $UNAME_RELEASE in + *4.0) + UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` + ;; + *5.*) + UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` + ;; + esac + # According to Compaq, /usr/sbin/psrinfo has been available on + # OSF/1 and Tru64 systems produced since 1995. I hope that + # covers most systems running today. This code pipes the CPU + # types through head -n 1, so we only detect the type of CPU 0. + ALPHA_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^ The alpha \(.*\) processor.*$/\1/p' | head -n 1` + case "$ALPHA_CPU_TYPE" in + "EV4 (21064)") + UNAME_MACHINE="alpha" ;; + "EV4.5 (21064)") + UNAME_MACHINE="alpha" ;; + "LCA4 (21066/21068)") + UNAME_MACHINE="alpha" ;; + "EV5 (21164)") + UNAME_MACHINE="alphaev5" ;; + "EV5.6 (21164A)") + UNAME_MACHINE="alphaev56" ;; + "EV5.6 (21164PC)") + UNAME_MACHINE="alphapca56" ;; + "EV5.7 (21164PC)") + UNAME_MACHINE="alphapca57" ;; + "EV6 (21264)") + UNAME_MACHINE="alphaev6" ;; + "EV6.7 (21264A)") + UNAME_MACHINE="alphaev67" ;; + "EV6.8CB (21264C)") + UNAME_MACHINE="alphaev68" ;; + "EV6.8AL (21264B)") + UNAME_MACHINE="alphaev68" ;; + "EV6.8CX (21264D)") + UNAME_MACHINE="alphaev68" ;; + "EV6.9A (21264/EV69A)") + UNAME_MACHINE="alphaev69" ;; + "EV7 (21364)") + UNAME_MACHINE="alphaev7" ;; + "EV7.9 (21364A)") + UNAME_MACHINE="alphaev79" ;; + esac + # A Pn.n version is a patched version. + # A Vn.n version is a released version. + # A Tn.n version is a released field test version. + # A Xn.n version is an unreleased experimental baselevel. + # 1.2 uses "1.2" for uname -r. + echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` + exit ;; + Alpha\ *:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # Should we change UNAME_MACHINE based on the output of uname instead + # of the specific Alpha model? + echo alpha-pc-interix + exit ;; + 21064:Windows_NT:50:3) + echo alpha-dec-winnt3.5 + exit ;; + Amiga*:UNIX_System_V:4.0:*) + echo m68k-unknown-sysv4 + exit ;; + *:[Aa]miga[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-amigaos + exit ;; + *:[Mm]orph[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-morphos + exit ;; + *:OS/390:*:*) + echo i370-ibm-openedition + exit ;; + *:z/VM:*:*) + echo s390-ibm-zvmoe + exit ;; + *:OS400:*:*) + echo powerpc-ibm-os400 + exit ;; + arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) + echo arm-acorn-riscix${UNAME_RELEASE} + exit ;; + arm:riscos:*:*|arm:RISCOS:*:*) + echo arm-unknown-riscos + exit ;; + SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) + echo hppa1.1-hitachi-hiuxmpp + exit ;; + Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) + # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. + if test "`(/bin/universe) 2>/dev/null`" = att ; then + echo pyramid-pyramid-sysv3 + else + echo pyramid-pyramid-bsd + fi + exit ;; + NILE*:*:*:dcosx) + echo pyramid-pyramid-svr4 + exit ;; + DRS?6000:unix:4.0:6*) + echo sparc-icl-nx6 + exit ;; + DRS?6000:UNIX_SV:4.2*:7* | DRS?6000:isis:4.2*:7*) + case `/usr/bin/uname -p` in + sparc) echo sparc-icl-nx7; exit ;; + esac ;; + sun4H:SunOS:5.*:*) + echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) + echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*) + echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:6*:*) + # According to config.sub, this is the proper way to canonicalize + # SunOS6. Hard to guess exactly what SunOS6 will be like, but + # it's likely to be more like Solaris than SunOS4. + echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:*:*) + case "`/usr/bin/arch -k`" in + Series*|S4*) + UNAME_RELEASE=`uname -v` + ;; + esac + # Japanese Language versions have a version number like `4.1.3-JL'. + echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` + exit ;; + sun3*:SunOS:*:*) + echo m68k-sun-sunos${UNAME_RELEASE} + exit ;; + sun*:*:4.2BSD:*) + UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` + test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3 + case "`/bin/arch`" in + sun3) + echo m68k-sun-sunos${UNAME_RELEASE} + ;; + sun4) + echo sparc-sun-sunos${UNAME_RELEASE} + ;; + esac + exit ;; + aushp:SunOS:*:*) + echo sparc-auspex-sunos${UNAME_RELEASE} + exit ;; + # The situation for MiNT is a little confusing. The machine name + # can be virtually everything (everything which is not + # "atarist" or "atariste" at least should have a processor + # > m68000). The system name ranges from "MiNT" over "FreeMiNT" + # to the lowercase version "mint" (or "freemint"). Finally + # the system name "TOS" denotes a system which is actually not + # MiNT. But MiNT is downward compatible to TOS, so this should + # be no problem. + atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) + echo m68k-milan-mint${UNAME_RELEASE} + exit ;; + hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) + echo m68k-hades-mint${UNAME_RELEASE} + exit ;; + *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) + echo m68k-unknown-mint${UNAME_RELEASE} + exit ;; + m68k:machten:*:*) + echo m68k-apple-machten${UNAME_RELEASE} + exit ;; + powerpc:machten:*:*) + echo powerpc-apple-machten${UNAME_RELEASE} + exit ;; + RISC*:Mach:*:*) + echo mips-dec-mach_bsd4.3 + exit ;; + RISC*:ULTRIX:*:*) + echo mips-dec-ultrix${UNAME_RELEASE} + exit ;; + VAX*:ULTRIX*:*:*) + echo vax-dec-ultrix${UNAME_RELEASE} + exit ;; + 2020:CLIX:*:* | 2430:CLIX:*:*) + echo clipper-intergraph-clix${UNAME_RELEASE} + exit ;; + mips:*:*:UMIPS | mips:*:*:RISCos) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c +#ifdef __cplusplus +#include /* for printf() prototype */ + int main (int argc, char *argv[]) { +#else + int main (argc, argv) int argc; char *argv[]; { +#endif + #if defined (host_mips) && defined (MIPSEB) + #if defined (SYSTYPE_SYSV) + printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_SVR4) + printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) + printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); + #endif + #endif + exit (-1); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && + dummyarg=`echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` && + SYSTEM_NAME=`$dummy $dummyarg` && + { echo "$SYSTEM_NAME"; exit; } + echo mips-mips-riscos${UNAME_RELEASE} + exit ;; + Motorola:PowerMAX_OS:*:*) + echo powerpc-motorola-powermax + exit ;; + Motorola:*:4.3:PL8-*) + echo powerpc-harris-powermax + exit ;; + Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) + echo powerpc-harris-powermax + exit ;; + Night_Hawk:Power_UNIX:*:*) + echo powerpc-harris-powerunix + exit ;; + m88k:CX/UX:7*:*) + echo m88k-harris-cxux7 + exit ;; + m88k:*:4*:R4*) + echo m88k-motorola-sysv4 + exit ;; + m88k:*:3*:R3*) + echo m88k-motorola-sysv3 + exit ;; + AViiON:dgux:*:*) + # DG/UX returns AViiON for all architectures + UNAME_PROCESSOR=`/usr/bin/uname -p` + if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] + then + if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ + [ ${TARGET_BINARY_INTERFACE}x = x ] + then + echo m88k-dg-dgux${UNAME_RELEASE} + else + echo m88k-dg-dguxbcs${UNAME_RELEASE} + fi + else + echo i586-dg-dgux${UNAME_RELEASE} + fi + exit ;; + M88*:DolphinOS:*:*) # DolphinOS (SVR3) + echo m88k-dolphin-sysv3 + exit ;; + M88*:*:R3*:*) + # Delta 88k system running SVR3 + echo m88k-motorola-sysv3 + exit ;; + XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) + echo m88k-tektronix-sysv3 + exit ;; + Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) + echo m68k-tektronix-bsd + exit ;; + *:IRIX*:*:*) + echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` + exit ;; + ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. + echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id + exit ;; # Note that: echo "'`uname -s`'" gives 'AIX ' + i*86:AIX:*:*) + echo i386-ibm-aix + exit ;; + ia64:AIX:*:*) + if [ -x /usr/bin/oslevel ] ; then + IBM_REV=`/usr/bin/oslevel` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} + exit ;; + *:AIX:2:3) + if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + + main() + { + if (!__power_pc()) + exit(1); + puts("powerpc-ibm-aix3.2.5"); + exit(0); + } +EOF + if $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` + then + echo "$SYSTEM_NAME" + else + echo rs6000-ibm-aix3.2.5 + fi + elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then + echo rs6000-ibm-aix3.2.4 + else + echo rs6000-ibm-aix3.2 + fi + exit ;; + *:AIX:*:[45]) + IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` + if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then + IBM_ARCH=rs6000 + else + IBM_ARCH=powerpc + fi + if [ -x /usr/bin/oslevel ] ; then + IBM_REV=`/usr/bin/oslevel` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${IBM_ARCH}-ibm-aix${IBM_REV} + exit ;; + *:AIX:*:*) + echo rs6000-ibm-aix + exit ;; + ibmrt:4.4BSD:*|romp-ibm:BSD:*) + echo romp-ibm-bsd4.4 + exit ;; + ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and + echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to + exit ;; # report: romp-ibm BSD 4.3 + *:BOSX:*:*) + echo rs6000-bull-bosx + exit ;; + DPX/2?00:B.O.S.:*:*) + echo m68k-bull-sysv3 + exit ;; + 9000/[34]??:4.3bsd:1.*:*) + echo m68k-hp-bsd + exit ;; + hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) + echo m68k-hp-bsd4.4 + exit ;; + 9000/[34678]??:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + case "${UNAME_MACHINE}" in + 9000/31? ) HP_ARCH=m68000 ;; + 9000/[34]?? ) HP_ARCH=m68k ;; + 9000/[678][0-9][0-9]) + if [ -x /usr/bin/getconf ]; then + sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` + sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` + case "${sc_cpu_version}" in + 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 + 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 + 532) # CPU_PA_RISC2_0 + case "${sc_kernel_bits}" in + 32) HP_ARCH="hppa2.0n" ;; + 64) HP_ARCH="hppa2.0w" ;; + '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 + esac ;; + esac + fi + if [ "${HP_ARCH}" = "" ]; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + + #define _HPUX_SOURCE + #include + #include + + int main () + { + #if defined(_SC_KERNEL_BITS) + long bits = sysconf(_SC_KERNEL_BITS); + #endif + long cpu = sysconf (_SC_CPU_VERSION); + + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1"); break; + case CPU_PA_RISC2_0: + #if defined(_SC_KERNEL_BITS) + switch (bits) + { + case 64: puts ("hppa2.0w"); break; + case 32: puts ("hppa2.0n"); break; + default: puts ("hppa2.0"); break; + } break; + #else /* !defined(_SC_KERNEL_BITS) */ + puts ("hppa2.0"); break; + #endif + default: puts ("hppa1.0"); break; + } + exit (0); + } +EOF + (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` + test -z "$HP_ARCH" && HP_ARCH=hppa + fi ;; + esac + if [ ${HP_ARCH} = "hppa2.0w" ] + then + eval $set_cc_for_build + + # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating + # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler + # generating 64-bit code. GNU and HP use different nomenclature: + # + # $ CC_FOR_BUILD=cc ./config.guess + # => hppa2.0w-hp-hpux11.23 + # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess + # => hppa64-hp-hpux11.23 + + if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | + grep __LP64__ >/dev/null + then + HP_ARCH="hppa2.0w" + else + HP_ARCH="hppa64" + fi + fi + echo ${HP_ARCH}-hp-hpux${HPUX_REV} + exit ;; + ia64:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + echo ia64-hp-hpux${HPUX_REV} + exit ;; + 3050*:HI-UX:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + int + main () + { + long cpu = sysconf (_SC_CPU_VERSION); + /* The order matters, because CPU_IS_HP_MC68K erroneously returns + true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct + results, however. */ + if (CPU_IS_PA_RISC (cpu)) + { + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; + case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; + default: puts ("hppa-hitachi-hiuxwe2"); break; + } + } + else if (CPU_IS_HP_MC68K (cpu)) + puts ("m68k-hitachi-hiuxwe2"); + else puts ("unknown-hitachi-hiuxwe2"); + exit (0); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` && + { echo "$SYSTEM_NAME"; exit; } + echo unknown-hitachi-hiuxwe2 + exit ;; + 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) + echo hppa1.1-hp-bsd + exit ;; + 9000/8??:4.3bsd:*:*) + echo hppa1.0-hp-bsd + exit ;; + *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) + echo hppa1.0-hp-mpeix + exit ;; + hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) + echo hppa1.1-hp-osf + exit ;; + hp8??:OSF1:*:*) + echo hppa1.0-hp-osf + exit ;; + i*86:OSF1:*:*) + if [ -x /usr/sbin/sysversion ] ; then + echo ${UNAME_MACHINE}-unknown-osf1mk + else + echo ${UNAME_MACHINE}-unknown-osf1 + fi + exit ;; + parisc*:Lites*:*:*) + echo hppa1.1-hp-lites + exit ;; + C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) + echo c1-convex-bsd + exit ;; + C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit ;; + C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) + echo c34-convex-bsd + exit ;; + C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) + echo c38-convex-bsd + exit ;; + C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) + echo c4-convex-bsd + exit ;; + CRAY*Y-MP:*:*:*) + echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*[A-Z]90:*:*:*) + echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ + | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ + -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ + -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*TS:*:*:*) + echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*T3E:*:*:*) + echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*SV1:*:*:*) + echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + *:UNICOS/mp:*:*) + echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) + FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` + FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` + echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit ;; + 5000:UNIX_System_V:4.*:*) + FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` + echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit ;; + i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) + echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} + exit ;; + sparc*:BSD/OS:*:*) + echo sparc-unknown-bsdi${UNAME_RELEASE} + exit ;; + *:BSD/OS:*:*) + echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} + exit ;; + *:FreeBSD:*:*) + case ${UNAME_MACHINE} in + pc98) + echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + amd64) + echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + *) + echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + esac + exit ;; + i*:CYGWIN*:*) + echo ${UNAME_MACHINE}-pc-cygwin + exit ;; + *:MINGW*:*) + echo ${UNAME_MACHINE}-pc-mingw32 + exit ;; + i*:windows32*:*) + # uname -m includes "-pc" on this system. + echo ${UNAME_MACHINE}-mingw32 + exit ;; + i*:PW*:*) + echo ${UNAME_MACHINE}-pc-pw32 + exit ;; + *:Interix*:[3456]*) + case ${UNAME_MACHINE} in + x86) + echo i586-pc-interix${UNAME_RELEASE} + exit ;; + EM64T | authenticamd) + echo x86_64-unknown-interix${UNAME_RELEASE} + exit ;; + esac ;; + [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) + echo i${UNAME_MACHINE}-pc-mks + exit ;; + i*:Windows_NT*:* | Pentium*:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we + # UNAME_MACHINE based on the output of uname instead of i386? + echo i586-pc-interix + exit ;; + i*:UWIN*:*) + echo ${UNAME_MACHINE}-pc-uwin + exit ;; + amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*) + echo x86_64-unknown-cygwin + exit ;; + p*:CYGWIN*:*) + echo powerpcle-unknown-cygwin + exit ;; + prep*:SunOS:5.*:*) + echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + *:GNU:*:*) + # the GNU system + echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` + exit ;; + *:GNU/*:*:*) + # other systems with GNU libc and userland + echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu + exit ;; + i*86:Minix:*:*) + echo ${UNAME_MACHINE}-pc-minix + exit ;; + arm*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit ;; + avr32*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit ;; + cris:Linux:*:*) + echo cris-axis-linux-gnu + exit ;; + crisv32:Linux:*:*) + echo crisv32-axis-linux-gnu + exit ;; + frv:Linux:*:*) + echo frv-unknown-linux-gnu + exit ;; + ia64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit ;; + m32r*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit ;; + m68*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit ;; + mips:Linux:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #undef CPU + #undef mips + #undef mipsel + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) + CPU=mipsel + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) + CPU=mips + #else + CPU= + #endif + #endif +EOF + eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' + /^CPU/{ + s: ::g + p + }'`" + test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } + ;; + mips64:Linux:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #undef CPU + #undef mips64 + #undef mips64el + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) + CPU=mips64el + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) + CPU=mips64 + #else + CPU= + #endif + #endif +EOF + eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' + /^CPU/{ + s: ::g + p + }'`" + test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } + ;; + or32:Linux:*:*) + echo or32-unknown-linux-gnu + exit ;; + ppc:Linux:*:*) + echo powerpc-unknown-linux-gnu + exit ;; + ppc64:Linux:*:*) + echo powerpc64-unknown-linux-gnu + exit ;; + alpha:Linux:*:*) + case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in + EV5) UNAME_MACHINE=alphaev5 ;; + EV56) UNAME_MACHINE=alphaev56 ;; + PCA56) UNAME_MACHINE=alphapca56 ;; + PCA57) UNAME_MACHINE=alphapca56 ;; + EV6) UNAME_MACHINE=alphaev6 ;; + EV67) UNAME_MACHINE=alphaev67 ;; + EV68*) UNAME_MACHINE=alphaev68 ;; + esac + objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null + if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi + echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} + exit ;; + parisc:Linux:*:* | hppa:Linux:*:*) + # Look for CPU level + case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in + PA7*) echo hppa1.1-unknown-linux-gnu ;; + PA8*) echo hppa2.0-unknown-linux-gnu ;; + *) echo hppa-unknown-linux-gnu ;; + esac + exit ;; + parisc64:Linux:*:* | hppa64:Linux:*:*) + echo hppa64-unknown-linux-gnu + exit ;; + s390:Linux:*:* | s390x:Linux:*:*) + echo ${UNAME_MACHINE}-ibm-linux + exit ;; + sh64*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit ;; + sh*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit ;; + sparc:Linux:*:* | sparc64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit ;; + vax:Linux:*:*) + echo ${UNAME_MACHINE}-dec-linux-gnu + exit ;; + x86_64:Linux:*:*) + echo x86_64-unknown-linux-gnu + exit ;; + xtensa:Linux:*:*) + echo xtensa-unknown-linux-gnu + exit ;; + i*86:Linux:*:*) + # The BFD linker knows what the default object file format is, so + # first see if it will tell us. cd to the root directory to prevent + # problems with other programs or directories called `ld' in the path. + # Set LC_ALL=C to ensure ld outputs messages in English. + ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ + | sed -ne '/supported targets:/!d + s/[ ][ ]*/ /g + s/.*supported targets: *// + s/ .*// + p'` + case "$ld_supported_targets" in + elf32-i386) + TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" + ;; + a.out-i386-linux) + echo "${UNAME_MACHINE}-pc-linux-gnuaout" + exit ;; + coff-i386) + echo "${UNAME_MACHINE}-pc-linux-gnucoff" + exit ;; + "") + # Either a pre-BFD a.out linker (linux-gnuoldld) or + # one that does not give us useful --help. + echo "${UNAME_MACHINE}-pc-linux-gnuoldld" + exit ;; + esac + # Determine whether the default compiler is a.out or elf + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + #ifdef __ELF__ + # ifdef __GLIBC__ + # if __GLIBC__ >= 2 + LIBC=gnu + # else + LIBC=gnulibc1 + # endif + # else + LIBC=gnulibc1 + # endif + #else + #if defined(__INTEL_COMPILER) || defined(__PGI) || defined(__SUNPRO_C) || defined(__SUNPRO_CC) + LIBC=gnu + #else + LIBC=gnuaout + #endif + #endif + #ifdef __dietlibc__ + LIBC=dietlibc + #endif +EOF + eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' + /^LIBC/{ + s: ::g + p + }'`" + test x"${LIBC}" != x && { + echo "${UNAME_MACHINE}-pc-linux-${LIBC}" + exit + } + test x"${TENTATIVE}" != x && { echo "${TENTATIVE}"; exit; } + ;; + i*86:DYNIX/ptx:4*:*) + # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. + # earlier versions are messed up and put the nodename in both + # sysname and nodename. + echo i386-sequent-sysv4 + exit ;; + i*86:UNIX_SV:4.2MP:2.*) + # Unixware is an offshoot of SVR4, but it has its own version + # number series starting with 2... + # I am not positive that other SVR4 systems won't match this, + # I just have to hope. -- rms. + # Use sysv4.2uw... so that sysv4* matches it. + echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} + exit ;; + i*86:OS/2:*:*) + # If we were able to find `uname', then EMX Unix compatibility + # is probably installed. + echo ${UNAME_MACHINE}-pc-os2-emx + exit ;; + i*86:XTS-300:*:STOP) + echo ${UNAME_MACHINE}-unknown-stop + exit ;; + i*86:atheos:*:*) + echo ${UNAME_MACHINE}-unknown-atheos + exit ;; + i*86:syllable:*:*) + echo ${UNAME_MACHINE}-pc-syllable + exit ;; + i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) + echo i386-unknown-lynxos${UNAME_RELEASE} + exit ;; + i*86:*DOS:*:*) + echo ${UNAME_MACHINE}-pc-msdosdjgpp + exit ;; + i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) + UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` + if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then + echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} + else + echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} + fi + exit ;; + i*86:*:5:[678]*) + # UnixWare 7.x, OpenUNIX and OpenServer 6. + case `/bin/uname -X | grep "^Machine"` in + *486*) UNAME_MACHINE=i486 ;; + *Pentium) UNAME_MACHINE=i586 ;; + *Pent*|*Celeron) UNAME_MACHINE=i686 ;; + esac + echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} + exit ;; + i*86:*:3.2:*) + if test -f /usr/options/cb.name; then + UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then + UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` + (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 + (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ + && UNAME_MACHINE=i586 + (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ + && UNAME_MACHINE=i686 + (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ + && UNAME_MACHINE=i686 + echo ${UNAME_MACHINE}-pc-sco$UNAME_REL + else + echo ${UNAME_MACHINE}-pc-sysv32 + fi + exit ;; + pc:*:*:*) + # Left here for compatibility: + # uname -m prints for DJGPP always 'pc', but it prints nothing about + # the processor, so we play safe by assuming i386. + echo i386-pc-msdosdjgpp + exit ;; + Intel:Mach:3*:*) + echo i386-pc-mach3 + exit ;; + paragon:*:*:*) + echo i860-intel-osf1 + exit ;; + i860:*:4.*:*) # i860-SVR4 + if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then + echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 + else # Add other i860-SVR4 vendors below as they are discovered. + echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 + fi + exit ;; + mini*:CTIX:SYS*5:*) + # "miniframe" + echo m68010-convergent-sysv + exit ;; + mc68k:UNIX:SYSTEM5:3.51m) + echo m68k-convergent-sysv + exit ;; + M680?0:D-NIX:5.3:*) + echo m68k-diab-dnix + exit ;; + M68*:*:R3V[5678]*:*) + test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;; + 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0) + OS_REL='' + test -r /etc/.relid \ + && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4.3${OS_REL}; exit; } + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; + 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4; exit; } ;; + m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) + echo m68k-unknown-lynxos${UNAME_RELEASE} + exit ;; + mc68030:UNIX_System_V:4.*:*) + echo m68k-atari-sysv4 + exit ;; + TSUNAMI:LynxOS:2.*:*) + echo sparc-unknown-lynxos${UNAME_RELEASE} + exit ;; + rs6000:LynxOS:2.*:*) + echo rs6000-unknown-lynxos${UNAME_RELEASE} + exit ;; + PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) + echo powerpc-unknown-lynxos${UNAME_RELEASE} + exit ;; + SM[BE]S:UNIX_SV:*:*) + echo mips-dde-sysv${UNAME_RELEASE} + exit ;; + RM*:ReliantUNIX-*:*:*) + echo mips-sni-sysv4 + exit ;; + RM*:SINIX-*:*:*) + echo mips-sni-sysv4 + exit ;; + *:SINIX-*:*:*) + if uname -p 2>/dev/null >/dev/null ; then + UNAME_MACHINE=`(uname -p) 2>/dev/null` + echo ${UNAME_MACHINE}-sni-sysv4 + else + echo ns32k-sni-sysv + fi + exit ;; + PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort + # says + echo i586-unisys-sysv4 + exit ;; + *:UNIX_System_V:4*:FTX*) + # From Gerald Hewes . + # How about differentiating between stratus architectures? -djm + echo hppa1.1-stratus-sysv4 + exit ;; + *:*:*:FTX*) + # From seanf@swdc.stratus.com. + echo i860-stratus-sysv4 + exit ;; + i*86:VOS:*:*) + # From Paul.Green@stratus.com. + echo ${UNAME_MACHINE}-stratus-vos + exit ;; + *:VOS:*:*) + # From Paul.Green@stratus.com. + echo hppa1.1-stratus-vos + exit ;; + mc68*:A/UX:*:*) + echo m68k-apple-aux${UNAME_RELEASE} + exit ;; + news*:NEWS-OS:6*:*) + echo mips-sony-newsos6 + exit ;; + R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) + if [ -d /usr/nec ]; then + echo mips-nec-sysv${UNAME_RELEASE} + else + echo mips-unknown-sysv${UNAME_RELEASE} + fi + exit ;; + BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. + echo powerpc-be-beos + exit ;; + BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. + echo powerpc-apple-beos + exit ;; + BePC:BeOS:*:*) # BeOS running on Intel PC compatible. + echo i586-pc-beos + exit ;; + SX-4:SUPER-UX:*:*) + echo sx4-nec-superux${UNAME_RELEASE} + exit ;; + SX-5:SUPER-UX:*:*) + echo sx5-nec-superux${UNAME_RELEASE} + exit ;; + SX-6:SUPER-UX:*:*) + echo sx6-nec-superux${UNAME_RELEASE} + exit ;; + SX-7:SUPER-UX:*:*) + echo sx7-nec-superux${UNAME_RELEASE} + exit ;; + SX-8:SUPER-UX:*:*) + echo sx8-nec-superux${UNAME_RELEASE} + exit ;; + SX-8R:SUPER-UX:*:*) + echo sx8r-nec-superux${UNAME_RELEASE} + exit ;; + Power*:Rhapsody:*:*) + echo powerpc-apple-rhapsody${UNAME_RELEASE} + exit ;; + *:Rhapsody:*:*) + echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} + exit ;; + *:Darwin:*:*) + UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown + case $UNAME_PROCESSOR in + unknown) UNAME_PROCESSOR=powerpc ;; + esac + echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} + exit ;; + *:procnto*:*:* | *:QNX:[0123456789]*:*) + UNAME_PROCESSOR=`uname -p` + if test "$UNAME_PROCESSOR" = "x86"; then + UNAME_PROCESSOR=i386 + UNAME_MACHINE=pc + fi + echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} + exit ;; + *:QNX:*:4*) + echo i386-pc-qnx + exit ;; + NSE-?:NONSTOP_KERNEL:*:*) + echo nse-tandem-nsk${UNAME_RELEASE} + exit ;; + NSR-?:NONSTOP_KERNEL:*:*) + echo nsr-tandem-nsk${UNAME_RELEASE} + exit ;; + *:NonStop-UX:*:*) + echo mips-compaq-nonstopux + exit ;; + BS2000:POSIX*:*:*) + echo bs2000-siemens-sysv + exit ;; + DS/*:UNIX_System_V:*:*) + echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} + exit ;; + *:Plan9:*:*) + # "uname -m" is not consistent, so use $cputype instead. 386 + # is converted to i386 for consistency with other x86 + # operating systems. + if test "$cputype" = "386"; then + UNAME_MACHINE=i386 + else + UNAME_MACHINE="$cputype" + fi + echo ${UNAME_MACHINE}-unknown-plan9 + exit ;; + *:TOPS-10:*:*) + echo pdp10-unknown-tops10 + exit ;; + *:TENEX:*:*) + echo pdp10-unknown-tenex + exit ;; + KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) + echo pdp10-dec-tops20 + exit ;; + XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) + echo pdp10-xkl-tops20 + exit ;; + *:TOPS-20:*:*) + echo pdp10-unknown-tops20 + exit ;; + *:ITS:*:*) + echo pdp10-unknown-its + exit ;; + SEI:*:*:SEIUX) + echo mips-sei-seiux${UNAME_RELEASE} + exit ;; + *:DragonFly:*:*) + echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` + exit ;; + *:*VMS:*:*) + UNAME_MACHINE=`(uname -p) 2>/dev/null` + case "${UNAME_MACHINE}" in + A*) echo alpha-dec-vms ; exit ;; + I*) echo ia64-dec-vms ; exit ;; + V*) echo vax-dec-vms ; exit ;; + esac ;; + *:XENIX:*:SysV) + echo i386-pc-xenix + exit ;; + i*86:skyos:*:*) + echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE}` | sed -e 's/ .*$//' + exit ;; + i*86:rdos:*:*) + echo ${UNAME_MACHINE}-pc-rdos + exit ;; +esac + +#echo '(No uname command or uname output not recognized.)' 1>&2 +#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 + +eval $set_cc_for_build +cat >$dummy.c < +# include +#endif +main () +{ +#if defined (sony) +#if defined (MIPSEB) + /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, + I don't know.... */ + printf ("mips-sony-bsd\n"); exit (0); +#else +#include + printf ("m68k-sony-newsos%s\n", +#ifdef NEWSOS4 + "4" +#else + "" +#endif + ); exit (0); +#endif +#endif + +#if defined (__arm) && defined (__acorn) && defined (__unix) + printf ("arm-acorn-riscix\n"); exit (0); +#endif + +#if defined (hp300) && !defined (hpux) + printf ("m68k-hp-bsd\n"); exit (0); +#endif + +#if defined (NeXT) +#if !defined (__ARCHITECTURE__) +#define __ARCHITECTURE__ "m68k" +#endif + int version; + version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; + if (version < 4) + printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); + else + printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); + exit (0); +#endif + +#if defined (MULTIMAX) || defined (n16) +#if defined (UMAXV) + printf ("ns32k-encore-sysv\n"); exit (0); +#else +#if defined (CMU) + printf ("ns32k-encore-mach\n"); exit (0); +#else + printf ("ns32k-encore-bsd\n"); exit (0); +#endif +#endif +#endif + +#if defined (__386BSD__) + printf ("i386-pc-bsd\n"); exit (0); +#endif + +#if defined (sequent) +#if defined (i386) + printf ("i386-sequent-dynix\n"); exit (0); +#endif +#if defined (ns32000) + printf ("ns32k-sequent-dynix\n"); exit (0); +#endif +#endif + +#if defined (_SEQUENT_) + struct utsname un; + + uname(&un); + + if (strncmp(un.version, "V2", 2) == 0) { + printf ("i386-sequent-ptx2\n"); exit (0); + } + if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ + printf ("i386-sequent-ptx1\n"); exit (0); + } + printf ("i386-sequent-ptx\n"); exit (0); + +#endif + +#if defined (vax) +# if !defined (ultrix) +# include +# if defined (BSD) +# if BSD == 43 + printf ("vax-dec-bsd4.3\n"); exit (0); +# else +# if BSD == 199006 + printf ("vax-dec-bsd4.3reno\n"); exit (0); +# else + printf ("vax-dec-bsd\n"); exit (0); +# endif +# endif +# else + printf ("vax-dec-bsd\n"); exit (0); +# endif +# else + printf ("vax-dec-ultrix\n"); exit (0); +# endif +#endif + +#if defined (alliant) && defined (i860) + printf ("i860-alliant-bsd\n"); exit (0); +#endif + + exit (1); +} +EOF + +$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && + { echo "$SYSTEM_NAME"; exit; } + +# Apollos put the system type in the environment. + +test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } + +# Convex versions that predate uname can use getsysinfo(1) + +if [ -x /usr/convex/getsysinfo ] +then + case `getsysinfo -f cpu_type` in + c1*) + echo c1-convex-bsd + exit ;; + c2*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit ;; + c34*) + echo c34-convex-bsd + exit ;; + c38*) + echo c38-convex-bsd + exit ;; + c4*) + echo c4-convex-bsd + exit ;; + esac +fi + +cat >&2 < in order to provide the needed +information to handle your system. + +config.guess timestamp = $timestamp + +uname -m = `(uname -m) 2>/dev/null || echo unknown` +uname -r = `(uname -r) 2>/dev/null || echo unknown` +uname -s = `(uname -s) 2>/dev/null || echo unknown` +uname -v = `(uname -v) 2>/dev/null || echo unknown` + +/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` +/bin/uname -X = `(/bin/uname -X) 2>/dev/null` + +hostinfo = `(hostinfo) 2>/dev/null` +/bin/universe = `(/bin/universe) 2>/dev/null` +/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` +/bin/arch = `(/bin/arch) 2>/dev/null` +/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` +/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` + +UNAME_MACHINE = ${UNAME_MACHINE} +UNAME_RELEASE = ${UNAME_RELEASE} +UNAME_SYSTEM = ${UNAME_SYSTEM} +UNAME_VERSION = ${UNAME_VERSION} +EOF + +exit 1 + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: diff --git a/usrp2/firmware/config.sub b/usrp2/firmware/config.sub new file mode 100644 index 00000000..1761d8bd --- /dev/null +++ b/usrp2/firmware/config.sub @@ -0,0 +1,1626 @@ +#! /bin/sh +# Configuration validation subroutine script. +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +# 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, +# Inc. + +timestamp='2007-06-28' + +# This file is (in principle) common to ALL GNU software. +# The presence of a machine in this file suggests that SOME GNU software +# can handle that machine. It does not imply ALL GNU software can. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA +# 02110-1301, USA. +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + + +# Please send patches to . Submit a context +# diff and a properly formatted ChangeLog entry. +# +# Configuration subroutine to validate and canonicalize a configuration type. +# Supply the specified configuration type as an argument. +# If it is invalid, we print an error message on stderr and exit with code 1. +# Otherwise, we print the canonical config type on stdout and succeed. + +# This file is supposed to be the same for all GNU packages +# and recognize all the CPU types, system types and aliases +# that are meaningful with *any* GNU software. +# Each package is responsible for reporting which valid configurations +# it does not support. The user should be able to distinguish +# a failure to support a valid configuration from a meaningless +# configuration. + +# The goal of this file is to map all the various variations of a given +# machine specification into a single specification in the form: +# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM +# or in some cases, the newer four-part form: +# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM +# It is wrong to echo any other type of specification. + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] CPU-MFR-OPSYS + $0 [OPTION] ALIAS + +Canonicalize a configuration name. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.sub ($timestamp) + +Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 +Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit ;; + --version | -v ) + echo "$version" ; exit ;; + --help | --h* | -h ) + echo "$usage"; exit ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" + exit 1 ;; + + *local*) + # First pass through any local machine types. + echo $1 + exit ;; + + * ) + break ;; + esac +done + +case $# in + 0) echo "$me: missing argument$help" >&2 + exit 1;; + 1) ;; + *) echo "$me: too many arguments$help" >&2 + exit 1;; +esac + +# Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). +# Here we must recognize all the valid KERNEL-OS combinations. +maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` +case $maybe_os in + nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \ + uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \ + storm-chaos* | os2-emx* | rtmk-nova*) + os=-$maybe_os + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` + ;; + *) + basic_machine=`echo $1 | sed 's/-[^-]*$//'` + if [ $basic_machine != $1 ] + then os=`echo $1 | sed 's/.*-/-/'` + else os=; fi + ;; +esac + +### Let's recognize common machines as not being operating systems so +### that things like config.sub decstation-3100 work. We also +### recognize some manufacturers as not being operating systems, so we +### can provide default operating systems below. +case $os in + -sun*os*) + # Prevent following clause from handling this invalid input. + ;; + -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ + -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ + -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ + -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ + -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ + -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ + -apple | -axis | -knuth | -cray) + os= + basic_machine=$1 + ;; + -sim | -cisco | -oki | -wec | -winbond) + os= + basic_machine=$1 + ;; + -scout) + ;; + -wrs) + os=-vxworks + basic_machine=$1 + ;; + -chorusos*) + os=-chorusos + basic_machine=$1 + ;; + -chorusrdb) + os=-chorusrdb + basic_machine=$1 + ;; + -hiux*) + os=-hiuxwe2 + ;; + -sco6) + os=-sco5v6 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco5) + os=-sco3.2v5 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco4) + os=-sco3.2v4 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2.[4-9]*) + os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2v[4-9]*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco5v6*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco*) + os=-sco3.2v2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -udk*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -isc) + os=-isc2.2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -clix*) + basic_machine=clipper-intergraph + ;; + -isc*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -lynx*) + os=-lynxos + ;; + -ptx*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` + ;; + -windowsnt*) + os=`echo $os | sed -e 's/windowsnt/winnt/'` + ;; + -psos*) + os=-psos + ;; + -mint | -mint[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; +esac + +# Decode aliases for certain CPU-COMPANY combinations. +case $basic_machine in + # Recognize the basic CPU types without company name. + # Some are omitted here because they have special meanings below. + 1750a | 580 \ + | a29k \ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ + | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ + | bfin \ + | c4x | clipper \ + | d10v | d30v | dlx | dsp16xx \ + | fido | fr30 | frv \ + | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ + | i370 | i860 | i960 | ia64 \ + | ip2k | iq2000 \ + | m32c | m32r | m32rle | m68000 | m68k | m88k \ + | maxq | mb | microblaze | mcore | mep \ + | mips | mipsbe | mipseb | mipsel | mipsle \ + | mips16 \ + | mips64 | mips64el \ + | mips64vr | mips64vrel \ + | mips64orion | mips64orionel \ + | mips64vr4100 | mips64vr4100el \ + | mips64vr4300 | mips64vr4300el \ + | mips64vr5000 | mips64vr5000el \ + | mips64vr5900 | mips64vr5900el \ + | mipsisa32 | mipsisa32el \ + | mipsisa32r2 | mipsisa32r2el \ + | mipsisa64 | mipsisa64el \ + | mipsisa64r2 | mipsisa64r2el \ + | mipsisa64sb1 | mipsisa64sb1el \ + | mipsisa64sr71k | mipsisa64sr71kel \ + | mipstx39 | mipstx39el \ + | mn10200 | mn10300 \ + | mt \ + | msp430 \ + | nios | nios2 \ + | ns16k | ns32k \ + | or32 \ + | pdp10 | pdp11 | pj | pjl \ + | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ + | pyramid \ + | score \ + | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ + | sh64 | sh64le \ + | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ + | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ + | spu | strongarm \ + | tahoe | thumb | tic4x | tic80 | tron \ + | v850 | v850e \ + | we32k \ + | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \ + | z8k) + basic_machine=$basic_machine-unknown + ;; + m6811 | m68hc11 | m6812 | m68hc12) + # Motorola 68HC11/12. + basic_machine=$basic_machine-unknown + os=-none + ;; + m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) + ;; + ms1) + basic_machine=mt-unknown + ;; + + # We use `pc' rather than `unknown' + # because (1) that's what they normally are, and + # (2) the word "unknown" tends to confuse beginning users. + i*86 | x86_64) + basic_machine=$basic_machine-pc + ;; + # Object if more than one company name word. + *-*-*) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; + # Recognize the basic CPU types with company name. + 580-* \ + | a29k-* \ + | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ + | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ + | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ + | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ + | avr-* | avr32-* \ + | bfin-* | bs2000-* \ + | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ + | clipper-* | craynv-* | cydra-* \ + | d10v-* | d30v-* | dlx-* \ + | elxsi-* \ + | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ + | h8300-* | h8500-* \ + | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ + | i*86-* | i860-* | i960-* | ia64-* \ + | ip2k-* | iq2000-* \ + | m32c-* | m32r-* | m32rle-* \ + | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ + | m88110-* | m88k-* | maxq-* | mcore-* \ + | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ + | mips16-* \ + | mips64-* | mips64el-* \ + | mips64vr-* | mips64vrel-* \ + | mips64orion-* | mips64orionel-* \ + | mips64vr4100-* | mips64vr4100el-* \ + | mips64vr4300-* | mips64vr4300el-* \ + | mips64vr5000-* | mips64vr5000el-* \ + | mips64vr5900-* | mips64vr5900el-* \ + | mipsisa32-* | mipsisa32el-* \ + | mipsisa32r2-* | mipsisa32r2el-* \ + | mipsisa64-* | mipsisa64el-* \ + | mipsisa64r2-* | mipsisa64r2el-* \ + | mipsisa64sb1-* | mipsisa64sb1el-* \ + | mipsisa64sr71k-* | mipsisa64sr71kel-* \ + | mipstx39-* | mipstx39el-* \ + | mmix-* \ + | mt-* \ + | msp430-* \ + | nios-* | nios2-* \ + | none-* | np1-* | ns16k-* | ns32k-* \ + | orion-* \ + | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ + | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ + | pyramid-* \ + | romp-* | rs6000-* \ + | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ + | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ + | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ + | sparclite-* \ + | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \ + | tahoe-* | thumb-* \ + | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ + | tron-* \ + | v850-* | v850e-* | vax-* \ + | we32k-* \ + | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \ + | xstormy16-* | xtensa-* \ + | ymp-* \ + | z8k-*) + ;; + # Recognize the various machine names and aliases which stand + # for a CPU type and a company and sometimes even an OS. + 386bsd) + basic_machine=i386-unknown + os=-bsd + ;; + 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) + basic_machine=m68000-att + ;; + 3b*) + basic_machine=we32k-att + ;; + a29khif) + basic_machine=a29k-amd + os=-udi + ;; + abacus) + basic_machine=abacus-unknown + ;; + adobe68k) + basic_machine=m68010-adobe + os=-scout + ;; + alliant | fx80) + basic_machine=fx80-alliant + ;; + altos | altos3068) + basic_machine=m68k-altos + ;; + am29k) + basic_machine=a29k-none + os=-bsd + ;; + amd64) + basic_machine=x86_64-pc + ;; + amd64-*) + basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + amdahl) + basic_machine=580-amdahl + os=-sysv + ;; + amiga | amiga-*) + basic_machine=m68k-unknown + ;; + amigaos | amigados) + basic_machine=m68k-unknown + os=-amigaos + ;; + amigaunix | amix) + basic_machine=m68k-unknown + os=-sysv4 + ;; + apollo68) + basic_machine=m68k-apollo + os=-sysv + ;; + apollo68bsd) + basic_machine=m68k-apollo + os=-bsd + ;; + aux) + basic_machine=m68k-apple + os=-aux + ;; + balance) + basic_machine=ns32k-sequent + os=-dynix + ;; + c90) + basic_machine=c90-cray + os=-unicos + ;; + convex-c1) + basic_machine=c1-convex + os=-bsd + ;; + convex-c2) + basic_machine=c2-convex + os=-bsd + ;; + convex-c32) + basic_machine=c32-convex + os=-bsd + ;; + convex-c34) + basic_machine=c34-convex + os=-bsd + ;; + convex-c38) + basic_machine=c38-convex + os=-bsd + ;; + cray | j90) + basic_machine=j90-cray + os=-unicos + ;; + craynv) + basic_machine=craynv-cray + os=-unicosmp + ;; + cr16) + basic_machine=cr16-unknown + os=-elf + ;; + crds | unos) + basic_machine=m68k-crds + ;; + crisv32 | crisv32-* | etraxfs*) + basic_machine=crisv32-axis + ;; + cris | cris-* | etrax*) + basic_machine=cris-axis + ;; + crx) + basic_machine=crx-unknown + os=-elf + ;; + da30 | da30-*) + basic_machine=m68k-da30 + ;; + decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) + basic_machine=mips-dec + ;; + decsystem10* | dec10*) + basic_machine=pdp10-dec + os=-tops10 + ;; + decsystem20* | dec20*) + basic_machine=pdp10-dec + os=-tops20 + ;; + delta | 3300 | motorola-3300 | motorola-delta \ + | 3300-motorola | delta-motorola) + basic_machine=m68k-motorola + ;; + delta88) + basic_machine=m88k-motorola + os=-sysv3 + ;; + djgpp) + basic_machine=i586-pc + os=-msdosdjgpp + ;; + dpx20 | dpx20-*) + basic_machine=rs6000-bull + os=-bosx + ;; + dpx2* | dpx2*-bull) + basic_machine=m68k-bull + os=-sysv3 + ;; + ebmon29k) + basic_machine=a29k-amd + os=-ebmon + ;; + elxsi) + basic_machine=elxsi-elxsi + os=-bsd + ;; + encore | umax | mmax) + basic_machine=ns32k-encore + ;; + es1800 | OSE68k | ose68k | ose | OSE) + basic_machine=m68k-ericsson + os=-ose + ;; + fx2800) + basic_machine=i860-alliant + ;; + genix) + basic_machine=ns32k-ns + ;; + gmicro) + basic_machine=tron-gmicro + os=-sysv + ;; + go32) + basic_machine=i386-pc + os=-go32 + ;; + h3050r* | hiux*) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + h8300hms) + basic_machine=h8300-hitachi + os=-hms + ;; + h8300xray) + basic_machine=h8300-hitachi + os=-xray + ;; + h8500hms) + basic_machine=h8500-hitachi + os=-hms + ;; + harris) + basic_machine=m88k-harris + os=-sysv3 + ;; + hp300-*) + basic_machine=m68k-hp + ;; + hp300bsd) + basic_machine=m68k-hp + os=-bsd + ;; + hp300hpux) + basic_machine=m68k-hp + os=-hpux + ;; + hp3k9[0-9][0-9] | hp9[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k2[0-9][0-9] | hp9k31[0-9]) + basic_machine=m68000-hp + ;; + hp9k3[2-9][0-9]) + basic_machine=m68k-hp + ;; + hp9k6[0-9][0-9] | hp6[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k7[0-79][0-9] | hp7[0-79][0-9]) + basic_machine=hppa1.1-hp + ;; + hp9k78[0-9] | hp78[0-9]) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][13679] | hp8[0-9][13679]) + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][0-9] | hp8[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hppa-next) + os=-nextstep3 + ;; + hppaosf) + basic_machine=hppa1.1-hp + os=-osf + ;; + hppro) + basic_machine=hppa1.1-hp + os=-proelf + ;; + i370-ibm* | ibm*) + basic_machine=i370-ibm + ;; +# I'm not sure what "Sysv32" means. Should this be sysv3.2? + i*86v32) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv32 + ;; + i*86v4*) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv4 + ;; + i*86v) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv + ;; + i*86sol2) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-solaris2 + ;; + i386mach) + basic_machine=i386-mach + os=-mach + ;; + i386-vsta | vsta) + basic_machine=i386-unknown + os=-vsta + ;; + iris | iris4d) + basic_machine=mips-sgi + case $os in + -irix*) + ;; + *) + os=-irix4 + ;; + esac + ;; + isi68 | isi) + basic_machine=m68k-isi + os=-sysv + ;; + m88k-omron*) + basic_machine=m88k-omron + ;; + magnum | m3230) + basic_machine=mips-mips + os=-sysv + ;; + merlin) + basic_machine=ns32k-utek + os=-sysv + ;; + mingw32) + basic_machine=i386-pc + os=-mingw32 + ;; + mingw32ce) + basic_machine=arm-unknown + os=-mingw32ce + ;; + miniframe) + basic_machine=m68000-convergent + ;; + *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; + mips3*-*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` + ;; + mips3*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown + ;; + monitor) + basic_machine=m68k-rom68k + os=-coff + ;; + morphos) + basic_machine=powerpc-unknown + os=-morphos + ;; + msdos) + basic_machine=i386-pc + os=-msdos + ;; + ms1-*) + basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` + ;; + mvs) + basic_machine=i370-ibm + os=-mvs + ;; + ncr3000) + basic_machine=i486-ncr + os=-sysv4 + ;; + netbsd386) + basic_machine=i386-unknown + os=-netbsd + ;; + netwinder) + basic_machine=armv4l-rebel + os=-linux + ;; + news | news700 | news800 | news900) + basic_machine=m68k-sony + os=-newsos + ;; + news1000) + basic_machine=m68030-sony + os=-newsos + ;; + news-3600 | risc-news) + basic_machine=mips-sony + os=-newsos + ;; + necv70) + basic_machine=v70-nec + os=-sysv + ;; + next | m*-next ) + basic_machine=m68k-next + case $os in + -nextstep* ) + ;; + -ns2*) + os=-nextstep2 + ;; + *) + os=-nextstep3 + ;; + esac + ;; + nh3000) + basic_machine=m68k-harris + os=-cxux + ;; + nh[45]000) + basic_machine=m88k-harris + os=-cxux + ;; + nindy960) + basic_machine=i960-intel + os=-nindy + ;; + mon960) + basic_machine=i960-intel + os=-mon960 + ;; + nonstopux) + basic_machine=mips-compaq + os=-nonstopux + ;; + np1) + basic_machine=np1-gould + ;; + nsr-tandem) + basic_machine=nsr-tandem + ;; + op50n-* | op60c-*) + basic_machine=hppa1.1-oki + os=-proelf + ;; + openrisc | openrisc-*) + basic_machine=or32-unknown + ;; + os400) + basic_machine=powerpc-ibm + os=-os400 + ;; + OSE68000 | ose68000) + basic_machine=m68000-ericsson + os=-ose + ;; + os68k) + basic_machine=m68k-none + os=-os68k + ;; + pa-hitachi) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + paragon) + basic_machine=i860-intel + os=-osf + ;; + pbd) + basic_machine=sparc-tti + ;; + pbb) + basic_machine=m68k-tti + ;; + pc532 | pc532-*) + basic_machine=ns32k-pc532 + ;; + pc98) + basic_machine=i386-pc + ;; + pc98-*) + basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentium | p5 | k5 | k6 | nexgen | viac3) + basic_machine=i586-pc + ;; + pentiumpro | p6 | 6x86 | athlon | athlon_*) + basic_machine=i686-pc + ;; + pentiumii | pentium2 | pentiumiii | pentium3) + basic_machine=i686-pc + ;; + pentium4) + basic_machine=i786-pc + ;; + pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) + basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumpro-* | p6-* | 6x86-* | athlon-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentium4-*) + basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pn) + basic_machine=pn-gould + ;; + power) basic_machine=power-ibm + ;; + ppc) basic_machine=powerpc-unknown + ;; + ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppcle | powerpclittle | ppc-le | powerpc-little) + basic_machine=powerpcle-unknown + ;; + ppcle-* | powerpclittle-*) + basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64) basic_machine=powerpc64-unknown + ;; + ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64le | powerpc64little | ppc64-le | powerpc64-little) + basic_machine=powerpc64le-unknown + ;; + ppc64le-* | powerpc64little-*) + basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ps2) + basic_machine=i386-ibm + ;; + pw32) + basic_machine=i586-unknown + os=-pw32 + ;; + rdos) + basic_machine=i386-pc + os=-rdos + ;; + rom68k) + basic_machine=m68k-rom68k + os=-coff + ;; + rm[46]00) + basic_machine=mips-siemens + ;; + rtpc | rtpc-*) + basic_machine=romp-ibm + ;; + s390 | s390-*) + basic_machine=s390-ibm + ;; + s390x | s390x-*) + basic_machine=s390x-ibm + ;; + sa29200) + basic_machine=a29k-amd + os=-udi + ;; + sb1) + basic_machine=mipsisa64sb1-unknown + ;; + sb1el) + basic_machine=mipsisa64sb1el-unknown + ;; + sde) + basic_machine=mipsisa32-sde + os=-elf + ;; + sei) + basic_machine=mips-sei + os=-seiux + ;; + sequent) + basic_machine=i386-sequent + ;; + sh) + basic_machine=sh-hitachi + os=-hms + ;; + sh5el) + basic_machine=sh5le-unknown + ;; + sh64) + basic_machine=sh64-unknown + ;; + sparclite-wrs | simso-wrs) + basic_machine=sparclite-wrs + os=-vxworks + ;; + sps7) + basic_machine=m68k-bull + os=-sysv2 + ;; + spur) + basic_machine=spur-unknown + ;; + st2000) + basic_machine=m68k-tandem + ;; + stratus) + basic_machine=i860-stratus + os=-sysv4 + ;; + sun2) + basic_machine=m68000-sun + ;; + sun2os3) + basic_machine=m68000-sun + os=-sunos3 + ;; + sun2os4) + basic_machine=m68000-sun + os=-sunos4 + ;; + sun3os3) + basic_machine=m68k-sun + os=-sunos3 + ;; + sun3os4) + basic_machine=m68k-sun + os=-sunos4 + ;; + sun4os3) + basic_machine=sparc-sun + os=-sunos3 + ;; + sun4os4) + basic_machine=sparc-sun + os=-sunos4 + ;; + sun4sol2) + basic_machine=sparc-sun + os=-solaris2 + ;; + sun3 | sun3-*) + basic_machine=m68k-sun + ;; + sun4) + basic_machine=sparc-sun + ;; + sun386 | sun386i | roadrunner) + basic_machine=i386-sun + ;; + sv1) + basic_machine=sv1-cray + os=-unicos + ;; + symmetry) + basic_machine=i386-sequent + os=-dynix + ;; + t3e) + basic_machine=alphaev5-cray + os=-unicos + ;; + t90) + basic_machine=t90-cray + os=-unicos + ;; + tic54x | c54x*) + basic_machine=tic54x-unknown + os=-coff + ;; + tic55x | c55x*) + basic_machine=tic55x-unknown + os=-coff + ;; + tic6x | c6x*) + basic_machine=tic6x-unknown + os=-coff + ;; + tx39) + basic_machine=mipstx39-unknown + ;; + tx39el) + basic_machine=mipstx39el-unknown + ;; + toad1) + basic_machine=pdp10-xkl + os=-tops20 + ;; + tower | tower-32) + basic_machine=m68k-ncr + ;; + tpf) + basic_machine=s390x-ibm + os=-tpf + ;; + udi29k) + basic_machine=a29k-amd + os=-udi + ;; + ultra3) + basic_machine=a29k-nyu + os=-sym1 + ;; + v810 | necv810) + basic_machine=v810-nec + os=-none + ;; + vaxv) + basic_machine=vax-dec + os=-sysv + ;; + vms) + basic_machine=vax-dec + os=-vms + ;; + vpp*|vx|vx-*) + basic_machine=f301-fujitsu + ;; + vxworks960) + basic_machine=i960-wrs + os=-vxworks + ;; + vxworks68) + basic_machine=m68k-wrs + os=-vxworks + ;; + vxworks29k) + basic_machine=a29k-wrs + os=-vxworks + ;; + w65*) + basic_machine=w65-wdc + os=-none + ;; + w89k-*) + basic_machine=hppa1.1-winbond + os=-proelf + ;; + xbox) + basic_machine=i686-pc + os=-mingw32 + ;; + xps | xps100) + basic_machine=xps100-honeywell + ;; + ymp) + basic_machine=ymp-cray + os=-unicos + ;; + z8k-*-coff) + basic_machine=z8k-unknown + os=-sim + ;; + none) + basic_machine=none-none + os=-none + ;; + +# Here we handle the default manufacturer of certain CPU types. It is in +# some cases the only manufacturer, in others, it is the most popular. + w89k) + basic_machine=hppa1.1-winbond + ;; + op50n) + basic_machine=hppa1.1-oki + ;; + op60c) + basic_machine=hppa1.1-oki + ;; + romp) + basic_machine=romp-ibm + ;; + mmix) + basic_machine=mmix-knuth + ;; + rs6000) + basic_machine=rs6000-ibm + ;; + vax) + basic_machine=vax-dec + ;; + pdp10) + # there are many clones, so DEC is not a safe bet + basic_machine=pdp10-unknown + ;; + pdp11) + basic_machine=pdp11-dec + ;; + we32k) + basic_machine=we32k-att + ;; + sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele) + basic_machine=sh-unknown + ;; + sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v) + basic_machine=sparc-sun + ;; + cydra) + basic_machine=cydra-cydrome + ;; + orion) + basic_machine=orion-highlevel + ;; + orion105) + basic_machine=clipper-highlevel + ;; + mac | mpw | mac-mpw) + basic_machine=m68k-apple + ;; + pmac | pmac-mpw) + basic_machine=powerpc-apple + ;; + *-unknown) + # Make sure to match an already-canonicalized machine name. + ;; + *) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; +esac + +# Here we canonicalize certain aliases for manufacturers. +case $basic_machine in + *-digital*) + basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` + ;; + *-commodore*) + basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` + ;; + *) + ;; +esac + +# Decode manufacturer-specific aliases for certain operating systems. + +if [ x"$os" != x"" ] +then +case $os in + # First match some system type aliases + # that might get confused with valid system types. + # -solaris* is a basic system type, with this one exception. + -solaris1 | -solaris1.*) + os=`echo $os | sed -e 's|solaris1|sunos4|'` + ;; + -solaris) + os=-solaris2 + ;; + -svr4*) + os=-sysv4 + ;; + -unixware*) + os=-sysv4.2uw + ;; + -gnu/linux*) + os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` + ;; + # First accept the basic system types. + # The portable systems comes first. + # Each alternative MUST END IN A *, to match a version number. + # -sysv* is not here because it comes later, after sysvr4. + -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ + | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ + | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ + | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ + | -aos* \ + | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ + | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ + | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ + | -openbsd* | -solidbsd* \ + | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ + | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ + | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ + | -chorusos* | -chorusrdb* \ + | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ + | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \ + | -uxpv* | -beos* | -mpeix* | -udk* \ + | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ + | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ + | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ + | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ + | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ + | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ + | -skyos* | -haiku* | -rdos* | -toppers* | -drops*) + # Remember, each alternative MUST END IN *, to match a version number. + ;; + -qnx*) + case $basic_machine in + x86-* | i*86-*) + ;; + *) + os=-nto$os + ;; + esac + ;; + -nto-qnx*) + ;; + -nto*) + os=`echo $os | sed -e 's|nto|nto-qnx|'` + ;; + -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ + | -windows* | -osx | -abug | -netware* | -os9* | -beos* | -haiku* \ + | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) + ;; + -mac*) + os=`echo $os | sed -e 's|mac|macos|'` + ;; + -linux-dietlibc) + os=-linux-dietlibc + ;; + -linux*) + os=`echo $os | sed -e 's|linux|linux-gnu|'` + ;; + -sunos5*) + os=`echo $os | sed -e 's|sunos5|solaris2|'` + ;; + -sunos6*) + os=`echo $os | sed -e 's|sunos6|solaris3|'` + ;; + -opened*) + os=-openedition + ;; + -os400*) + os=-os400 + ;; + -wince*) + os=-wince + ;; + -osfrose*) + os=-osfrose + ;; + -osf*) + os=-osf + ;; + -utek*) + os=-bsd + ;; + -dynix*) + os=-bsd + ;; + -acis*) + os=-aos + ;; + -atheos*) + os=-atheos + ;; + -syllable*) + os=-syllable + ;; + -386bsd) + os=-bsd + ;; + -ctix* | -uts*) + os=-sysv + ;; + -nova*) + os=-rtmk-nova + ;; + -ns2 ) + os=-nextstep2 + ;; + -nsk*) + os=-nsk + ;; + # Preserve the version number of sinix5. + -sinix5.*) + os=`echo $os | sed -e 's|sinix|sysv|'` + ;; + -sinix*) + os=-sysv4 + ;; + -tpf*) + os=-tpf + ;; + -triton*) + os=-sysv3 + ;; + -oss*) + os=-sysv3 + ;; + -svr4) + os=-sysv4 + ;; + -svr3) + os=-sysv3 + ;; + -sysvr4) + os=-sysv4 + ;; + # This must come after -sysvr4. + -sysv*) + ;; + -ose*) + os=-ose + ;; + -es1800*) + os=-ose + ;; + -xenix) + os=-xenix + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + os=-mint + ;; + -aros*) + os=-aros + ;; + -kaos*) + os=-kaos + ;; + -zvmoe) + os=-zvmoe + ;; + -none) + ;; + *) + # Get rid of the `-' at the beginning of $os. + os=`echo $os | sed 's/[^-]*-//'` + echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 + exit 1 + ;; +esac +else + +# Here we handle the default operating systems that come with various machines. +# The value should be what the vendor currently ships out the door with their +# machine or put another way, the most popular os provided with the machine. + +# Note that if you're going to try to match "-MANUFACTURER" here (say, +# "-sun"), then you have to tell the case statement up towards the top +# that MANUFACTURER isn't an operating system. Otherwise, code above +# will signal an error saying that MANUFACTURER isn't an operating +# system, and we'll never get to this point. + +case $basic_machine in + score-*) + os=-elf + ;; + spu-*) + os=-elf + ;; + *-acorn) + os=-riscix1.2 + ;; + arm*-rebel) + os=-linux + ;; + arm*-semi) + os=-aout + ;; + c4x-* | tic4x-*) + os=-coff + ;; + # This must come before the *-dec entry. + pdp10-*) + os=-tops20 + ;; + pdp11-*) + os=-none + ;; + *-dec | vax-*) + os=-ultrix4.2 + ;; + m68*-apollo) + os=-domain + ;; + i386-sun) + os=-sunos4.0.2 + ;; + m68000-sun) + os=-sunos3 + # This also exists in the configure program, but was not the + # default. + # os=-sunos4 + ;; + m68*-cisco) + os=-aout + ;; + mep-*) + os=-elf + ;; + mips*-cisco) + os=-elf + ;; + mips*-*) + os=-elf + ;; + or32-*) + os=-coff + ;; + *-tti) # must be before sparc entry or we get the wrong os. + os=-sysv3 + ;; + sparc-* | *-sun) + os=-sunos4.1.1 + ;; + *-be) + os=-beos + ;; + *-haiku) + os=-haiku + ;; + *-ibm) + os=-aix + ;; + *-knuth) + os=-mmixware + ;; + *-wec) + os=-proelf + ;; + *-winbond) + os=-proelf + ;; + *-oki) + os=-proelf + ;; + *-hp) + os=-hpux + ;; + *-hitachi) + os=-hiux + ;; + i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) + os=-sysv + ;; + *-cbm) + os=-amigaos + ;; + *-dg) + os=-dgux + ;; + *-dolphin) + os=-sysv3 + ;; + m68k-ccur) + os=-rtu + ;; + m88k-omron*) + os=-luna + ;; + *-next ) + os=-nextstep + ;; + *-sequent) + os=-ptx + ;; + *-crds) + os=-unos + ;; + *-ns) + os=-genix + ;; + i370-*) + os=-mvs + ;; + *-next) + os=-nextstep3 + ;; + *-gould) + os=-sysv + ;; + *-highlevel) + os=-bsd + ;; + *-encore) + os=-bsd + ;; + *-sgi) + os=-irix + ;; + *-siemens) + os=-sysv4 + ;; + *-masscomp) + os=-rtu + ;; + f30[01]-fujitsu | f700-fujitsu) + os=-uxpv + ;; + *-rom68k) + os=-coff + ;; + *-*bug) + os=-coff + ;; + *-apple) + os=-macos + ;; + *-atari*) + os=-mint + ;; + *) + os=-none + ;; +esac +fi + +# Here we handle the case where we know the os, and the CPU type, but not the +# manufacturer. We pick the logical manufacturer. +vendor=unknown +case $basic_machine in + *-unknown) + case $os in + -riscix*) + vendor=acorn + ;; + -sunos*) + vendor=sun + ;; + -aix*) + vendor=ibm + ;; + -beos*) + vendor=be + ;; + -hpux*) + vendor=hp + ;; + -mpeix*) + vendor=hp + ;; + -hiux*) + vendor=hitachi + ;; + -unos*) + vendor=crds + ;; + -dgux*) + vendor=dg + ;; + -luna*) + vendor=omron + ;; + -genix*) + vendor=ns + ;; + -mvs* | -opened*) + vendor=ibm + ;; + -os400*) + vendor=ibm + ;; + -ptx*) + vendor=sequent + ;; + -tpf*) + vendor=ibm + ;; + -vxsim* | -vxworks* | -windiss*) + vendor=wrs + ;; + -aux*) + vendor=apple + ;; + -hms*) + vendor=hitachi + ;; + -mpw* | -macos*) + vendor=apple + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + vendor=atari + ;; + -vos*) + vendor=stratus + ;; + esac + basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` + ;; +esac + +echo $basic_machine$os +exit + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: diff --git a/usrp2/firmware/configure.ac b/usrp2/firmware/configure.ac new file mode 100644 index 00000000..bbb223c0 --- /dev/null +++ b/usrp2/firmware/configure.ac @@ -0,0 +1,46 @@ +dnl +dnl Copyright 2007 Free Software Foundation, Inc. +dnl +dnl This program is free software: you can redistribute it and/or modify +dnl it under the terms of the GNU General Public License as published by +dnl the Free Software Foundation, either version 3 of the License, or +dnl (at your option) any later version. +dnl +dnl This program is distributed in the hope that it will be useful, +dnl but WITHOUT ANY WARRANTY; without even the implied warranty of +dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +dnl GNU General Public License for more details. +dnl +dnl You should have received a copy of the GNU General Public License +dnl along with this program. If not, see . +dnl + +AC_INIT +AC_PREREQ(2.57) +AM_CONFIG_HEADER(config.h) +AC_CONFIG_AUX_DIR([.]) +AC_CONFIG_SRCDIR([lib/u2_init.c]) + +AM_INIT_AUTOMAKE(u2f,0.0svn) + +cross_compiling=yes + +AC_PROG_CC([mb-gcc]) +dnl AC_PROG_LD([mb-ld]) + +RANLIB=mb-ranlib +AC_SUBST(RANLIB) + +dnl AC_PROG_RANLIB([mb-ranlib]) + +AC_CHECK_HEADERS(arpa/inet.h netinet/in.h byteswap.h) +AC_C_BIGENDIAN + +AC_CONFIG_FILES([\ + Makefile \ + apps/Makefile \ + include/Makefile \ + lib/Makefile \ +]) + +AC_OUTPUT diff --git a/usrp2/firmware/divisors.py b/usrp2/firmware/divisors.py new file mode 100755 index 00000000..d31bd4da --- /dev/null +++ b/usrp2/firmware/divisors.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python + +speeds = (9600, 19200, 38400, 57600, 115200, 230400) + +master_clk = 100e6 +wb_clk = master_clk / 2 + +def divisor(speed): + div0 = wb_clk // (speed * 16) + div1 = div0 + 1 + actual0 = actual_speed(div0) + actual1 = actual_speed(div1) + if abs(actual0 - speed) < abs(actual1 - speed): + return div0 + else: + return div1 + +def actual_speed(divisor): + return (wb_clk // divisor) / 16 + +def doit(speed): + div = divisor(speed) + actual = actual_speed(div) + rel_error = (actual - speed) / speed + print "target: %6d divisor: %6d actual: %11.4f %6.3f%%" % (speed, div, actual, rel_error*100) + +def main(): + print "wb_clk = %f" % (wb_clk,) + for s in speeds: + doit(s) + +if __name__ == '__main__': + main() + diff --git a/usrp2/firmware/include/Makefile.am b/usrp2/firmware/include/Makefile.am new file mode 100644 index 00000000..a5e33919 --- /dev/null +++ b/usrp2/firmware/include/Makefile.am @@ -0,0 +1,27 @@ +# +# Copyright 2008 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include $(top_srcdir)/Makefile.common + +noinst_HEADERS = \ + usrp2_cdefs.h \ + usrp2_eth_packet.h \ + usrp2_fpga_regs.h \ + usrp2_i2c_addr.h \ + usrp2_mac_addr.h \ + usrp2_mimo_config.h \ + usrp2_types.h diff --git a/usrp2/firmware/include/usrp2_cdefs.h b/usrp2/firmware/include/usrp2_cdefs.h new file mode 100644 index 00000000..71395cda --- /dev/null +++ b/usrp2/firmware/include/usrp2_cdefs.h @@ -0,0 +1,34 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef INCLUDED_USRP2_CDEFS_H +#define INCLUDED_USRP2_CDEFS_H + +/* C++ needs to know that types and declarations are C, not C++. */ +#ifdef __cplusplus +# define __U2_BEGIN_DECLS extern "C" { +# define __U2_END_DECLS } +#else +# define __U2_BEGIN_DECLS +# define __U2_END_DECLS +#endif + +#endif /* INCLUDED_USRP2_CDEFS_H */ diff --git a/usrp2/firmware/include/usrp2_eth_packet.h b/usrp2/firmware/include/usrp2_eth_packet.h new file mode 100644 index 00000000..ca13d61a --- /dev/null +++ b/usrp2/firmware/include/usrp2_eth_packet.h @@ -0,0 +1,374 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_USRP2_ETH_PACKET_H +#define INCLUDED_USRP2_ETH_PACKET_H + +#include "usrp2_cdefs.h" +#include "usrp2_bytesex.h" +#include "usrp2_mac_addr.h" +#include "usrp2_mimo_config.h" + +__U2_BEGIN_DECLS + +#define U2_ETHERTYPE 0xBEEF // used in our frames +#define MAC_CTRL_ETHERTYPE 0x8808 // used in PAUSE frames + +/* + * All these data structures are BIG-ENDIAN on the wire + */ + +// FIXME gcc specific. Really ought to come from compiler.h +#define _AL4 __attribute__((aligned (4))) + +/* + * \brief The classic 14-byte ethernet header + */ +typedef struct { + u2_mac_addr_t dst; + u2_mac_addr_t src; + uint16_t ethertype; +} __attribute__((packed)) u2_eth_hdr_t; + +/*! + * \brief USRP2 transport header + * + * This enables host->usrp2 flow control and dropped packet detection. + */ +typedef struct { + uint16_t flags; // MBZ, may be used for channel in future + uint16_t fifo_status; // free space in Rx fifo in 32-bit lines + uint8_t seqno; // sequence number of this packet + uint8_t ack; // sequence number of next packet expected +} __attribute__((packed)) u2_transport_hdr_t; + + +/* + * The fixed payload header of a USRP2 ethernet packet... + * + * Basically there's 1 word of flags and routing info, and 1 word + * of timestamp that specifies when the data was received, or + * when it should be transmitted. The data samples follow immediately. + * + * Transmit packets (from host to U2) + * + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Chan | mbz |I|S|E| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Timestamp | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * + * Received packets (from U2 to host) + * + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Chan | mbz | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Timestamp | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * mbz == must be zero + */ + +typedef struct { + uint32_t word0; // flags etc + uint32_t timestamp; // time of rx or tx (100 MHz) +} u2_fixed_hdr_t; + + +#define U2P_CHAN_MASK 0x1f +#define U2P_CHAN_SHIFT 27 + +#define U2P_TX_IMMEDIATE 0x00000004 // send samples NOW, else at timestamp +#define U2P_TX_START_OF_BURST 0x00000002 // this frame is the start of a burst +#define U2P_TX_END_OF_BURST 0x00000001 // this frame is the end of a burst + +#define U2P_ALL_FLAGS 0x00000007 + +#define CONTROL_CHAN 0x1f + +static inline int +u2p_chan(u2_fixed_hdr_t *p) +{ + return (ntohl(p->word0) >> U2P_CHAN_SHIFT) & U2P_CHAN_MASK; +} + +inline static uint32_t +u2p_word0(u2_fixed_hdr_t *p) +{ + return ntohl(p->word0); +} + +inline static uint32_t +u2p_timestamp(u2_fixed_hdr_t *p) +{ + return ntohl(p->timestamp); +} + +inline static void +u2p_set_word0(u2_fixed_hdr_t *p, int flags, int chan) +{ + p->word0 = htonl((flags & U2P_ALL_FLAGS) + | ((chan & U2P_CHAN_MASK) << U2P_CHAN_SHIFT)); +} + +inline static void +u2p_set_timestamp(u2_fixed_hdr_t *p, uint32_t ts) +{ + p->timestamp = htonl(ts); +} + +/*! + * \brief consolidated packet: ethernet header + transport header + fixed header + */ +typedef struct { + u2_eth_hdr_t ehdr; + u2_transport_hdr_t thdr; + u2_fixed_hdr_t fixed; +} u2_eth_packet_t; + +/* + * full load of samples: + * ethernet header + transport header + fixed header + maximum number of samples. + * sizeof(u2_eth_samples_t) == 1512 + * (payload is 1498 bytes, two bytes shorter than 1500 byte MTU) + */ + +#define U2_MAX_SAMPLES 371 + +typedef struct { + u2_eth_packet_t hdrs; + uint32_t samples[U2_MAX_SAMPLES]; +} u2_eth_samples_t; + +/* + * Opcodes for control channel + * + * Reply opcodes are the same as the request opcode with the OP_REPLY_BIT set (0x80). + */ +#define OP_REPLY_BIT 0x80 + +#define OP_EOP 0 // marks last subpacket in packet + +#define OP_ID 1 +#define OP_ID_REPLY (OP_ID | OP_REPLY_BIT) +#define OP_BURN_MAC_ADDR 2 +#define OP_BURN_MAC_ADDR_REPLY (OP_BURN_MAC_ADDR | OP_REPLY_BIT) +#define OP_READ_TIME 3 // What time is it? (100 MHz counter) +#define OP_READ_TIME_REPLY (OP_READ_TIME | OP_REPLY_BIT) +#define OP_CONFIG_RX_V2 4 +#define OP_CONFIG_RX_REPLY_V2 (OP_CONFIG_RX_V2 | OP_REPLY_BIT) +#define OP_CONFIG_TX_V2 5 +#define OP_CONFIG_TX_REPLY_V2 (OP_CONFIG_TX_V2 | OP_REPLY_BIT) +#define OP_START_RX_STREAMING 6 +#define OP_START_RX_STREAMING_REPLY (OP_START_RX_STREAMING | OP_REPLY_BIT) +#define OP_STOP_RX 7 +#define OP_STOP_RX_REPLY (OP_STOP_RX | OP_REPLY_BIT) +#define OP_CONFIG_MIMO 8 +#define OP_CONFIG_MIMO_REPLY (OP_CONFIG_MIMO | OP_REPLY_BIT) + + +//#define OP_WRITE_REG xx // not implemented +//#define OP_WRITE_REG_MASKED xx +//#define OP_READ_REG xx +//#define OP_READ_REG_REPLY xx + +/* + * All subpackets are a multiple of 4 bytes long. + * All subpackets start with an 8-bit opcode, an 8-bit len and an 8-bit rid. + */ + + +/*! + * \brief Generic request and reply packet + * + * Used by: + * OP_EOP, OP_BURN_MAC_ADDR_REPLY, OP_START_RX_STREAMING_REPLY, + * OP_STOP_RX_REPLY + */ +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + uint8_t ok; // bool +} _AL4 op_generic_t; + +/*! + * \brief Reply info from a USRP2 + */ +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + uint8_t mbz; + u2_mac_addr_t addr; + uint16_t hw_rev; + uint8_t fpga_md5sum[16]; + uint8_t sw_md5sum[16]; +} _AL4 op_id_reply_t; + +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + uint8_t mbz; + uint32_t items_per_frame; // # of 32-bit data items; MTU=1500: [9,371] +} _AL4 op_start_rx_streaming_t; + +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + u2_mac_addr_t addr; +} _AL4 op_burn_mac_addr_t; + +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + uint8_t mbz; + uint32_t time; +} _AL4 op_read_time_reply_t; + + +/*! + * \brief Configure receiver + */ +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + uint8_t mbz; + // bitmask indicating which of the following fields are valid + uint16_t valid; + uint16_t gain; // fxpt_db (Q9.7) + uint32_t freq_hi; // high 32-bits of 64-bit fxpt_freq (Q44.20) + uint32_t freq_lo; // low 32-bits of 64-bit fxpt_freq (Q44.20) + uint32_t decim; // desired decimation factor (NOT -1) + uint32_t scale_iq; // (scale_i << 16) | scale_q [16.0 format] +} _AL4 op_config_rx_v2_t; + +// bitmask for "valid" field. If the bit is set, there's +// meaningful data in the corresonding field. + +#define CFGV_GAIN 0x0001 // gain field is valid +#define CFGV_FREQ 0x0002 // target_freq field is valid +#define CFGV_INTERP_DECIM 0x0004 // interp or decim is valid +#define CFGV_SCALE_IQ 0x0008 // scale_iq is valid + +/*! + * \brief Reply to receiver configuration + */ +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + uint8_t mbz; + + uint16_t ok; // config was successful (bool) + uint16_t inverted; // spectrum is inverted (bool) + + // RF frequency that corresponds to DC in the IF (fxpt_freq) + uint32_t baseband_freq_hi; + uint32_t baseband_freq_lo; + // DDC frequency (fxpt_freq) + uint32_t ddc_freq_hi; + uint32_t ddc_freq_lo; + // residual frequency (fxpt_freq) + uint32_t residual_freq_hi; + uint32_t residual_freq_lo; + +} _AL4 op_config_rx_reply_v2_t; + +/*! + * \brief Configure transmitter + */ +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + uint8_t mbz; + + // bitmask indicating which of the following fields are valid + uint16_t valid; + uint16_t gain; // fxpt_db (Q9.7) + uint32_t freq_hi; // high 32-bits of 64-bit fxpt_freq (Q44.20) + uint32_t freq_lo; // low 32-bits of 64-bit fxpt_freq (Q44.20) + uint32_t interp; // desired interpolation factor (NOT -1) + uint32_t scale_iq; // (scale_i << 16) | scale_q [16.0 format] +} _AL4 op_config_tx_v2_t; + +/*! + * \brief Reply to configure transmitter + */ +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + uint8_t mbz; + + uint16_t ok; // config was successful (bool) + uint16_t inverted; // spectrum is inverted (bool) + + // RF frequency that corresponds to DC in the IF (fxpt_freq) + uint32_t baseband_freq_hi; + uint32_t baseband_freq_lo; + // DUC frequency (fxpt_freq) + uint32_t duc_freq_hi; + uint32_t duc_freq_lo; + // residual frequency (fxpt_freq) + uint32_t residual_freq_hi; + uint32_t residual_freq_lo; + +} _AL4 op_config_tx_reply_v2_t; + +/*! + * \brief Configure MIMO clocking, etc (uses generic reply) + */ +typedef struct { + uint8_t opcode; + uint8_t len; + uint8_t rid; + uint8_t flags; // from usrp_mimo_config.h +} op_config_mimo_t; + + +/* + * ================================================================ + * union of all of subpacket types + * ================================================================ + */ +typedef union { + + op_generic_t op_generic; + op_id_reply_t op_id_reply; + op_start_rx_streaming_t op_start_rx_streaming; + op_burn_mac_addr_t op_burn_mac_addr; + op_read_time_reply_t op_read_time_reply; + op_config_rx_v2_t op_config_rx_v2; + op_config_rx_reply_v2_t op_config_rx_reply_v2; + op_config_tx_v2_t op_config_tx_v2; + op_config_tx_reply_v2_t op_config_tx_reply_v2; + op_config_mimo_t op_config_mimo; + +} u2_subpkt_t; + + +__U2_END_DECLS + +#endif /* INCLUDED_USRP2_ETH_PACKET_H */ diff --git a/usrp2/firmware/include/usrp2_fpga_regs.h b/usrp2/firmware/include/usrp2_fpga_regs.h new file mode 100644 index 00000000..b0f83df6 --- /dev/null +++ b/usrp2/firmware/include/usrp2_fpga_regs.h @@ -0,0 +1,80 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_USRP2_FPGA_REGS_H +#define INCLUDED_USSRP2_FPGA_REGS_H + +#include "usrp2_cdefs.h" + +__U2_BEGIN_DECLS + +// ---------------------------------------------------------------- + +#define DSP_CORE_TX_BASE 128 + +// DUC center frequency tuning word (phase increment) +#define FR_TX_FREQ_0 (0 + DSP_CORE_TX_BASE) + +// I & Q output scaling, 16.0 format ((I_SCALE << 16) | Q_SCALE) +#define FR_TX_SCALE_0 (1 + DSP_CORE_TX_BASE) + +// Tx interpolation rate (set to 1 less than desired rate) +#define FR_TX_INTERP_RATE_0 (2 + DSP_CORE_TX_BASE) + +// Write 1 (actually anything) to clear tx state +#define FR_TX_CLEAR_STATE_0 (3 + DSP_CORE_TX_BASE) + +// ---------------------------------------------------------------- + +#define DSP_CORE_RX_BASE 160 + +// DDC center frequency tuning word (phase increment) +#define FR_RX_FREQ_0 (0 + DSP_CORE_RX_BASE) + +// I & Q input scaling, 16.0 format ((I_SCALE << 16) | Q_SCALE) +#define FR_RX_SCALE_0 (1 + DSP_CORE_RX_BASE) + +// Rx decimation rate (set to 1 less than desired rate) +#define FR_RX_DECIM_RATE_0 (2 + DSP_CORE_RX_BASE) + +// The next two registers concatenated are the Rx command register. +// +// Writing FR_RX_TIME_TO_RX_0 writes the concatenated value into the +// cmd queue. Thus, if you're writing both, be sure to write +// FR_RX_QTY_0 first. +// +// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +// | Timestamp | +// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + +#define FR_RX_TIME_TO_RX (3 + DSP_CORE_RX_BASE) + +// 23-bits 9-bits +// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +// | number_of_lines | lines_per_frame | +// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + +#define FR_RX_QTY_0 (4 + DSP_CORE_RX_BASE) + +// write a 1 (anything actually) to clear the overrun +#define FR_RX_CLR_OVERRUN_0 (5 + DSP_CORE_RX_BASE) + + +__U2_END_DECLS + +#endif /* INCLUDED_USRP2_FPGA_REGS_H */ diff --git a/usrp2/firmware/include/usrp2_i2c_addr.h b/usrp2/firmware/include/usrp2_i2c_addr.h new file mode 100644 index 00000000..f2599690 --- /dev/null +++ b/usrp2/firmware/include/usrp2_i2c_addr.h @@ -0,0 +1,82 @@ +/* -*- c++ -*- */ +/* + * Copyright 2004,2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_USRP2_I2C_ADDR_H +#define INCLUDED_USRP2_I2C_ADDR_H + +#include "usrp2_cdefs.h" + +__U2_BEGIN_DECLS + +// I2C addresses + +#define I2C_DEV_EEPROM 0x50 // 24LC02[45]: 7-bits 1010xxx + +#define I2C_ADDR_MBOARD (I2C_DEV_EEPROM | 0x0) +#define I2C_ADDR_TX_A (I2C_DEV_EEPROM | 0x4) +#define I2C_ADDR_RX_A (I2C_DEV_EEPROM | 0x5) + + +// format of USRP2 motherboard rom +// 00: 0x00 h/w rev (LSB) +// 01: 0x00 h/w rev (MSB) +// 02: 0x00 MAC addr 0 +// 03: 0x50 MAC addr 1 +// 04: 0xC2 MAC addr 2 +// 05: 0x85 MAC addr 3 +// 06: 0x3. MAC addr 4 +// 07: 0x.. MAC addr 5 + +#define MBOARD_REV_LSB 0x00 +#define MBOARD_REV_MSB 0x01 +#define MBOARD_MAC_ADDR 0x02 + + +// format of daughterboard EEPROM +// 00: 0xDB code for ``I'm a daughterboard'' +// 01: .. Daughterboard ID (LSB) +// 02: .. Daughterboard ID (MSB) +// 03: .. io bits 7-0 direction (bit set if it's an output from m'board) +// 04: .. io bits 15-8 direction (bit set if it's an output from m'board) +// 05: .. ADC0 DC offset correction (LSB) +// 06: .. ADC0 DC offset correction (MSB) +// 07: .. ADC1 DC offset correction (LSB) +// 08: .. ADC1 DC offset correction (MSB) +// ... +// 1f: .. negative of the sum of bytes [0x00, 0x1e] + +#define DB_EEPROM_MAGIC 0x00 +#define DB_EEPROM_MAGIC_VALUE 0xDB +#define DB_EEPROM_ID_LSB 0x01 +#define DB_EEPROM_ID_MSB 0x02 +#define DB_EEPROM_OE_LSB 0x03 +#define DB_EEPROM_OE_MSB 0x04 +#define DB_EEPROM_OFFSET_0_LSB 0x05 // offset correction for ADC or DAC 0 +#define DB_EEPROM_OFFSET_0_MSB 0x06 +#define DB_EEPROM_OFFSET_1_LSB 0x07 // offset correction for ADC or DAC 1 +#define DB_EEPROM_OFFSET_1_MSB 0x08 +#define DB_EEPROM_CHKSUM 0x1f + +#define DB_EEPROM_CLEN 0x20 // length of common portion of eeprom + +#define DB_EEPROM_CUSTOM_BASE DB_EEPROM_CLEN // first avail offset for + // daughterboard specific use +__U2_END_DECLS + +#endif /* INCLUDED_USRP2_I2C_ADDR_H */ + diff --git a/usrp2/firmware/include/usrp2_mac_addr.h b/usrp2/firmware/include/usrp2_mac_addr.h new file mode 100644 index 00000000..da5a69f5 --- /dev/null +++ b/usrp2/firmware/include/usrp2_mac_addr.h @@ -0,0 +1,28 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_USRP2_MAC_ADDR_H +#define INCLUDED_USRP2_MAC_ADDR_H + +#include + +typedef struct { + uint8_t addr[6]; +} u2_mac_addr_t; + +#endif /* INCLUDED_USRP2_MAC_ADDR_H */ diff --git a/usrp2/firmware/include/usrp2_mimo_config.h b/usrp2/firmware/include/usrp2_mimo_config.h new file mode 100644 index 00000000..12967519 --- /dev/null +++ b/usrp2/firmware/include/usrp2_mimo_config.h @@ -0,0 +1,46 @@ +/* -*- c -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef INCLUDED_USRP2_MIMO_CONFIG_H +#define INCLUDED_USRP2_MIMO_CONFIG_H + +#define _MC_WE_LOCK 0x0001 +#define _MC_MIMO_CLK_INPUT 0x0002 // else SMA input + +/* + * Derived masks (use these): + * + * We get our input from 1 of three places: + * Our free running oscilator, our SMA connector, or from the MIMO connector + */ +#define MC_WE_DONT_LOCK 0x0000 +#define MC_WE_LOCK_TO_SMA (_MC_WE_LOCK | 0) +#define MC_WE_LOCK_TO_MIMO (_MC_WE_LOCK | _MC_MIMO_CLK_INPUT) + +/* + * Independent of the source of the clock, we may or may not drive our + * clock onto the mimo connector. Note that there are dedicated clock + * signals in each direction, so disaster doesn't occurs if we're + * unnecessarily providing clock. + */ +#define MC_PROVIDE_CLK_TO_MIMO 0x0004 + + +#endif /* INCLUDED_USRP2_MIMO_CONFIG_H */ diff --git a/usrp2/firmware/include/usrp2_types.h b/usrp2/firmware/include/usrp2_types.h new file mode 100644 index 00000000..83d9f26c --- /dev/null +++ b/usrp2/firmware/include/usrp2_types.h @@ -0,0 +1,106 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_USRP2_TYPES_H +#define INCLUDED_USRP2_TYPES_H + +#include +#include + +__U2_BEGIN_DECLS + +/*! + * \brief Fixed point representation of a frequency in Hertz (VITA-49 compatible) + * + * 64-bit two's complement, with the radix point 20 bits up from the bottom. + * Q44.20 format (20 bits to the right of the radix point) + * + * Values range from +/- 8.79 terahertz with a resolution of 0.95 microhertz. + */ +typedef int64_t u2_fxpt_freq_t; + +#define U2_FPF_RP 20 // location of radix point in u2_fxpt_freq_t + +// macro so we can init structs at compile time +#define U2_DOUBLE_TO_FXPT_FREQ(f) (int64_t)((f) * (1LL << U2_FPF_RP)) + +static inline u2_fxpt_freq_t +u2_double_to_fxpt_freq(double f) +{ + return U2_DOUBLE_TO_FXPT_FREQ(f); +} + +static inline int +u2_fxpt_freq_round_to_int(u2_fxpt_freq_t fx) +{ + return (int)((fx+(1<<(U2_FPF_RP-1)))>>U2_FPF_RP); +} + +static inline double +u2_fxpt_freq_to_double(u2_fxpt_freq_t fx) +{ + return ((double) fx) * 1.0/(1 << U2_FPF_RP); +} + +static inline uint32_t +u2_fxpt_freq_hi(u2_fxpt_freq_t f) +{ + return ((f >> 32) & 0xffffffff); +} + +static inline uint32_t +u2_fxpt_freq_lo(u2_fxpt_freq_t f) +{ + return (f & 0xffffffff); +} + +static inline u2_fxpt_freq_t +u2_fxpt_freq_from_hilo(uint32_t hi, uint32_t lo) +{ + return (((u2_fxpt_freq_t) hi) << 32) | lo; +} + +/*! + * \brief Fixed point representation of a gain in dB (VITA-49 compatible) + * + * 16-bit two's complement, with the radix point 7 bits up from the bottom. + * Q9.7 format (7 bits to the right of the radix point) + */ +typedef int16_t u2_fxpt_gain_t; + +#define U2_FPG_RP 7 // location of radix point in u2_fxpt_gain_t + +// macro so we can init structs at compile time +#define U2_DOUBLE_TO_FXPT_GAIN(g) (int16_t)((g) * (1 << U2_FPG_RP)) + +static inline u2_fxpt_gain_t +u2_double_to_fxpt_gain(double g) +{ + return U2_DOUBLE_TO_FXPT_GAIN(g); +} + +static inline float +u2_fxpt_gain_to_double(u2_fxpt_gain_t fx) +{ + return ((double) fx) * 1.0/(1 << U2_FPG_RP); +} + + +__U2_END_DECLS + + +#endif /* INCLUDED_USRP2_TYPES_H */ diff --git a/usrp2/firmware/lib/Makefile.am b/usrp2/firmware/lib/Makefile.am new file mode 100644 index 00000000..83dd915c --- /dev/null +++ b/usrp2/firmware/lib/Makefile.am @@ -0,0 +1,90 @@ +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include $(top_srcdir)/Makefile.common + +noinst_LIBRARIES = \ + libu2fw.a + + +libu2fw_a_SOURCES = \ + ad9510.c \ + ad9777.c \ + buffer_pool.c \ + clocks.c \ + db_basic.c \ + db_init.c \ + db_rfx.c \ + db_tvrx.c \ + dbsm.c \ + eeprom.c \ + ethernet.c \ + eth_mac.c \ + hal_io.c \ + hal_uart.c \ + i2c.c \ + lsadc.c \ + lsdac.c \ + mdelay.c \ + memcpy_wa.c \ + memset_wa.c \ + nonstdio.c \ + pic.c \ + print_mac_addr.c \ + print_rmon_regs.c \ + print_fxpt.c \ + print_buffer.c \ + printf.c \ + spi.c \ + u2_init.c + + +noinst_HEADERS = \ + ad9510.h \ + ad9777.h \ + ad9777_regs.h \ + bool.h \ + buffer_pool.h \ + clocks.h \ + db.h \ + db_base.h \ + dbsm.h \ + eth_mac.h \ + eth_mac_regs.h \ + eth_phy.h \ + ethernet.h \ + hal_io.h \ + hal_uart.h \ + i2c.h \ + lsadc.h \ + lsdac.h \ + mdelay.h \ + memcpy_wa.h \ + memory_map.h \ + memset_wa.h \ + nonstdio.h \ + pic.h \ + print_rmon_regs.h \ + spi.h \ + stdint.h \ + stdio.h \ + u2_init.h \ + usrp2_bytesex.h \ + wb16550.h + +EXTRA_DIST = \ + microblaze.ld diff --git a/usrp2/firmware/lib/ad9510.c b/usrp2/firmware/lib/ad9510.c new file mode 100644 index 00000000..4d3acb65 --- /dev/null +++ b/usrp2/firmware/lib/ad9510.c @@ -0,0 +1,42 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "ad9510.h" +#include "spi.h" +#include + +#define RD (1 << 15) +#define WR (0 << 15) + +void +ad9510_write_reg(int regno, uint8_t value) +{ + uint32_t inst = WR | (regno & 0xff); + uint32_t v = (inst << 8) | (value & 0xff); + spi_transact(SPI_TXONLY, SPI_SS_AD9510, v, 24, SPIF_PUSH_FALL); +} + +int +ad9510_read_reg(int regno) +{ + uint32_t inst = RD | (regno & 0xff); + uint32_t v = (inst << 8) | 0; + uint32_t r = spi_transact(SPI_TXRX, SPI_SS_AD9510, v, 24, + SPIF_PUSH_FALL | SPIF_LATCH_FALL); + return r & 0xff; +} diff --git a/usrp2/firmware/lib/ad9510.h b/usrp2/firmware/lib/ad9510.h new file mode 100644 index 00000000..a395e522 --- /dev/null +++ b/usrp2/firmware/lib/ad9510.h @@ -0,0 +1,30 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_AD9510_H +#define INCLUDED_AD9510_H + +#include + +/* + * Analog Device AD9510 1.2 GHz Clock Distribution IC w/ PLL + */ + +void ad9510_write_reg(int regno, uint8_t value); +int ad9510_read_reg(int regno); + +#endif /* INCLUDED_AD9510_H */ diff --git a/usrp2/firmware/lib/ad9777.c b/usrp2/firmware/lib/ad9777.c new file mode 100644 index 00000000..734ccd7e --- /dev/null +++ b/usrp2/firmware/lib/ad9777.c @@ -0,0 +1,47 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "ad9777.h" +#include "memory_map.h" +#include "spi.h" + +#define IB_RD 0x80 +#define IB_WR 0x00 +#define IB_XFER_1 0x00 +#define IB_XFER_2 0x20 +#define IB_XFER_3 0x40 +#define IB_XFER_4 0x60 +#define IB_ADDR_MASK 0x1f + +void +ad9777_write_reg(int regno, uint8_t value) +{ + uint8_t instr = IB_WR | IB_XFER_1 | (regno & IB_ADDR_MASK); + spi_transact(SPI_TXONLY, SPI_SS_AD9777, + (instr << 8) | (value & 0xff), 16, SPIF_PUSH_FALL); +} + +int +ad9777_read_reg(int regno) +{ + uint8_t instr = IB_RD | IB_XFER_1 | (regno & IB_ADDR_MASK); + uint32_t r = spi_transact(SPI_TXRX, SPI_SS_AD9777, + (instr << 8) | 0, 16, + SPIF_PUSH_FALL | SPIF_LATCH_RISE); + return r & 0xff; +} diff --git a/usrp2/firmware/lib/ad9777.h b/usrp2/firmware/lib/ad9777.h new file mode 100644 index 00000000..d4d10491 --- /dev/null +++ b/usrp2/firmware/lib/ad9777.h @@ -0,0 +1,31 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_AD9777_H +#define INCLUDED_AD9777_H + +#include +#include "ad9777_regs.h" + +/* + * Analog Devices AD9777 16-bit, 160 MS/s, Dual Interpolating TxDAC + */ + +void ad9777_write_reg(int regno, uint8_t value); +int ad9777_read_reg(int regno); + +#endif /* INCLUDED_AD9777_H */ diff --git a/usrp2/firmware/lib/ad9777_regs.h b/usrp2/firmware/lib/ad9777_regs.h new file mode 100644 index 00000000..de2936c1 --- /dev/null +++ b/usrp2/firmware/lib/ad9777_regs.h @@ -0,0 +1,71 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_AD9777_REGS_H +#define INCLUDED_AD9777_REGS_H + +#define R0_SW_RESET (1 << 5) +#define R0_SLEEP (1 << 4) +#define R0_POWER_DN (1 << 3) +#define R0_1R (1 << 2) +#define R0_2R (0 << 2) +#define R0_PLL_LOCKED (1 << 1) + +#define R1_INTERP_1X 0x00 +#define R1_INTERP_2X 0x40 +#define R1_INTERP_4X 0x80 +#define R1_INTERP_8X 0xC0 +#define R1_MOD_NONE 0x00 +#define R1_MOD_FS_2 0x10 // Fs/2 +#define R1_MOD_FS_4 0x20 // Fs/4 +#define R1_MOD_FS_8 0x30 // Fs/8 +#define R1_ZERO_STUFF (1 << 3) // N.B., doubles output rate +#define R1_REAL_MIX (1 << 2) +#define R1_CMPLX_MIX (0 << 2) +#define R1_POS_EXP (1 << 1) // exp(+jwt) +#define R1_NEG_EXP (0 << 1) // exp(-jwt) +#define R1_DATACLK_OUT (1 << 0) + +#define R2_2S_COMP (0 << 7) +#define R2_2PORT_MODE (0 << 6) +#define R2_1PORT_MODE (1 << 6) + +#define R3_PLL_DIV_1 0x00 +#define R3_PLL_DIV_2 0x01 +#define R3_PLL_DIV_4 0x02 +#define R3_PLL_DIV_8 0x03 + +#define R4_PLL_ON (1 << 7) +#define R4_CP_MANUAL (1 << 6) +#define R4_CP_AUTO (0 << 6) +#define R4_CP_50uA (0x00 | R4_CP_MANUAL) +#define R4_CP_100uA (0x01 | R4_CP_MANUAL) +#define R4_CP_200uA (0x02 | R4_CP_MANUAL) +#define R4_CP_400uA (0x03 | R4_CP_MANUAL) +#define R4_CP_800uA (0x07 | R4_CP_MANUAL) + +#define R5_I_FINE_GAIN(g) (g) // 8-bits +#define R6_I_COARSE_GAIN(g) ((g) & 0xf) // low 4-bits + +#define R9_Q_FINE_GAIN(g) (g) // 8-bits +#define R10_Q_COARSE_GAIN(g) ((g) & 0xf) // low 4-bits + + +// FIXME more registers for offset and gain control... + + +#endif /* INCLUDED_AD9777_REGS_H */ diff --git a/usrp2/firmware/lib/bool.h b/usrp2/firmware/lib/bool.h new file mode 100644 index 00000000..36f472d4 --- /dev/null +++ b/usrp2/firmware/lib/bool.h @@ -0,0 +1,26 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_BOOL_H +#define INCLUDED_BOOL_H + +typedef int bool; +#define true 1 +#define false 0 + +#endif /* INCLUDED_BOOL_H */ diff --git a/usrp2/firmware/lib/buffer_pool.c b/usrp2/firmware/lib/buffer_pool.c new file mode 100644 index 00000000..77e7c521 --- /dev/null +++ b/usrp2/firmware/lib/buffer_pool.c @@ -0,0 +1,72 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "memory_map.h" +#include "buffer_pool.h" +#include "hal_io.h" + +void +bp_init(void) +{ + int i; + bp_disable_port(PORT_SERDES); + bp_disable_port(PORT_DSP); + bp_disable_port(PORT_ETH); + bp_disable_port(PORT_RAM); + + for (i = 0; i < NBUFFERS; i++) + bp_clear_buf(i); +} + +#ifndef INLINE_BUFFER_POOL + +void +bp_clear_buf(int bufnum) +{ + buffer_pool_ctrl->ctrl = BPC_BUFFER(bufnum) | BPC_PORT_NIL | BPC_CLR; +} + +void +bp_disable_port(int portnum) +{ + // disable buffer connections to this port + buffer_pool_ctrl->ctrl = BPC_BUFFER_NIL | BPC_PORT(portnum); +} + +void +bp_receive_to_buf(int bufnum, int port, int step, int fl, int ll) +{ + buffer_pool_ctrl->ctrl = (BPC_READ + | BPC_BUFFER(bufnum) + | BPC_PORT(port) + | BPC_STEP(step) + | BPC_FIRST_LINE(fl) + | BPC_LAST_LINE(ll)); +} + +void +bp_send_from_buf(int bufnum, int port, int step, int fl, int ll) +{ + buffer_pool_ctrl->ctrl = (BPC_WRITE + | BPC_BUFFER(bufnum) + | BPC_PORT(port) + | BPC_STEP(step) + | BPC_FIRST_LINE(fl) + | BPC_LAST_LINE(ll)); +} + +#endif diff --git a/usrp2/firmware/lib/buffer_pool.h b/usrp2/firmware/lib/buffer_pool.h new file mode 100644 index 00000000..145b20f8 --- /dev/null +++ b/usrp2/firmware/lib/buffer_pool.h @@ -0,0 +1,75 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_BUFFER_POOL_H +#define INCLUDED_BUFFER_POOL_H + +#include "memory_map.h" + +// Buffer Pool Management + + +// define to have common buffer operations inlined +#define INLINE_BUFFER_POOL 1 + +void bp_init(void); + +#ifndef INLINE_BUFFER_POOL + +void bp_clear_buf(int bufnum); +void bp_disable_port(int portnum); +void bp_receive_to_buf(int bufnum, int port, int step, int fl, int ll); +void bp_send_from_buf(int bufnum, int port, int step, int fl, int ll); + +#else + +static inline void +bp_clear_buf(int bufnum) +{ + buffer_pool_ctrl->ctrl = BPC_BUFFER(bufnum) | BPC_PORT_NIL | BPC_CLR; +} + +static inline void +bp_disable_port(int portnum) +{ + // disable buffer connections to this port + buffer_pool_ctrl->ctrl = BPC_BUFFER_NIL | BPC_PORT(portnum); +} + +static inline void +bp_receive_to_buf(int bufnum, int port, int step, int fl, int ll) +{ + buffer_pool_ctrl->ctrl = (BPC_READ + | BPC_BUFFER(bufnum) + | BPC_PORT(port) + | BPC_STEP(step) + | BPC_FIRST_LINE(fl) + | BPC_LAST_LINE(ll)); +} + +static inline void +bp_send_from_buf(int bufnum, int port, int step, int fl, int ll) +{ + buffer_pool_ctrl->ctrl = (BPC_WRITE + | BPC_BUFFER(bufnum) + | BPC_PORT(port) + | BPC_STEP(step) + | BPC_FIRST_LINE(fl) + | BPC_LAST_LINE(ll)); +} +#endif +#endif diff --git a/usrp2/firmware/lib/clocks.c b/usrp2/firmware/lib/clocks.c new file mode 100644 index 00000000..bfcaa734 --- /dev/null +++ b/usrp2/firmware/lib/clocks.c @@ -0,0 +1,182 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif +#include + +#include "memory_map.h" +#include "ad9510.h" +#include "spi.h" + +void +clocks_init(void) +{ + // Set up basic clocking functions in AD9510 + ad9510_write_reg(0x45, 0x00); // CLK2 drives distribution + ad9510_write_reg(0x3D, 0x00); // Turn on output 1 (FPGA CLK), normal levels + ad9510_write_reg(0x4B, 0x80); // Bypass divider 1 + ad9510_write_reg(0x5A, 0x01); // Update Regs + + spi_wait(); + + // Set up PLL for 10 MHz reference + // Reg 4, A counter, Don't Care + ad9510_write_reg(0x05, 0x00); // Reg 5, B counter MSBs, 0 + ad9510_write_reg(0x06, 0x05); // Reg 6, B counter LSBs, 5 + // Reg 7, Loss of reference detect, doesn't work yet, 0 + ad9510_write_reg(0x5A, 0x01); // Update Regs + + + // FIXME, probably need interface to this... + timesync_regs->tick_control = 4; + + // Primary clock configuration + clocks_mimo_config(MC_WE_DONT_LOCK); + + // Set up other clocks + + clocks_enable_test_clk(false); + clocks_enable_tx_dboard(false, 0); + clocks_enable_rx_dboard(false, 0); + + // ETH phy clock + ad9510_write_reg(0x41, 0x01); // Turn off output 5 (phy_clk) + ad9510_write_reg(0x53, 0x80); // Bypass divider + ad9510_write_reg(0x5A, 0x01); // Update Regs + + // Enable clock to ADCs and DACs + ad9510_write_reg(0x3F, 0x00); // Turn on output 3 (DAC CLK), normal levels + ad9510_write_reg(0x4F, 0x80); // Bypass Div #3 + + ad9510_write_reg(0x40, 0x02); // Turn on out 4 (ADC clk), LVDS + ad9510_write_reg(0x51, 0x80); // Bypass Div #4 + + ad9510_write_reg(0x5A, 0x01); // Update Regs +} + + +void +clocks_mimo_config(int flags) +{ + if (flags & _MC_WE_LOCK){ + // Reg 8, Charge pump on, dig lock det, positive PFD, 47 + ad9510_write_reg(0x08, 0x47); + } + else { + // Reg 8, Charge pump off, dig lock det, positive PFD + ad9510_write_reg(0x08, 0x00); + } + + // Reg 9, Charge pump current, 0x40=3mA, 0x00=650uA + ad9510_write_reg(0x09, 0x00); + // Reg A, Prescaler of 2, everything normal 04 + ad9510_write_reg(0x0A, 0x04); + // Reg B, R Div MSBs, 0 + ad9510_write_reg(0x0B, 0x00); + // Reg C, R Div LSBs, 1 + ad9510_write_reg(0x0C, 0x01); + // Reg D, Antibacklash, Digital lock det, 0 + + ad9510_write_reg(0x5A, 0x01); // Update Regs + + spi_wait(); + + // Allow for clock switchover + + if (flags & _MC_WE_LOCK){ // WE LOCK + if (flags & _MC_MIMO_CLK_INPUT) { + // Turn on ref output and choose the MIMO connector + output_regs->clk_ctrl = 0x15; + } + else { + // turn on ref output and choose the SMA + output_regs->clk_ctrl = 0x1C; + } + } + else { // WE DONT LOCK + // Disable both ext clk inputs + output_regs->clk_ctrl = 0x10; + } + + // Do we drive a clock onto the MIMO connector? + + if (flags & MC_PROVIDE_CLK_TO_MIMO) { + ad9510_write_reg(0x3E, 0x00); // Turn on output 2 (clk_exp_out), normal levels + ad9510_write_reg(0x4D, 0x00); // Turn on Div2 + ad9510_write_reg(0x4C, 0x44); // Set Div2 = 10, output a 10 MHz clock + } + else { + ad9510_write_reg(0x3E, 0x02); // Turn off output 2 (clk_exp_out) + ad9510_write_reg(0x4D, 0x80); // Bypass divider 2 + } + ad9510_write_reg(0x5A, 0x01); // Update Regs +} + +void +clocks_enable_test_clk(bool enable) +{ + if (enable){ + ad9510_write_reg(0x3C, 0x08); // Turn on output 0 -- Test output + ad9510_write_reg(0x49, 0x80); // Bypass divider 0 + } + else { + ad9510_write_reg(0x3C, 0x02); // Turn off output 0 + } + ad9510_write_reg(0x5A, 0x01); // Update Regs +} + + +void +clocks_enable_rx_dboard(bool enable, int divisor) +{ + if (enable){ + ad9510_write_reg(0x43, 0x08); // enable output 7 (db_rx_clk), CMOS + + if (divisor == 0){ + ad9510_write_reg(0x57, 0x80); // Bypass Div #7, 100 MHz clock + } + else { + // FIXME Matt, do something with divisor... + } + } + else { + ad9510_write_reg(0x43, 0x01); // Turn off output 7 (db_rx_clk) + } + ad9510_write_reg(0x5A, 0x01); // Update Regs +} + + +void +clocks_enable_tx_dboard(bool enable, int divisor) +{ + if (enable){ + ad9510_write_reg(0x42, 0x08); // enable output 6 (db_tx_clk), CMOS + if (divisor == 0) { + ad9510_write_reg(0x55, 0x80); // Bypass Div #6, 100 MHz clock + } + else { + // FIXME Matt, do something with divisor + } + } + else { + ad9510_write_reg(0x42, 0x01); // Turn off output 6 (db_tx_clk) + } + ad9510_write_reg(0x5A, 0x01); // Update Regs +} diff --git a/usrp2/firmware/lib/clocks.h b/usrp2/firmware/lib/clocks.h new file mode 100644 index 00000000..c43cfcb1 --- /dev/null +++ b/usrp2/firmware/lib/clocks.h @@ -0,0 +1,63 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_CLOCKS_H +#define INCLUDED_CLOCKS_H + +/* + * Routines to configure our multitude of clocks + */ + +#include +#include + + +/*! + * One time call to initialize all clocks to a reasonable state. We + * come out of here using our free running 100MHz oscilator and not + * providing a clock to the MIMO connector (CMC_WE_DONT_LOCK) + */ +void clocks_init(void); + + +/*! + * \brief MIMO clock configuration. + * + * Configure our master clock source, and whether or not we drive a + * clock onto the mimo connector. See MC_flags in usrp2_mimo_config.h. + */ +void clocks_mimo_config(int flags); + +/*! + * \brief Enable or disable test clock (extra clock signal) + */ +void clocks_enable_test_clk(bool enable); + +/*! + * \brief Enable or disable clock to Rx daughterboard + */ +void clocks_enable_rx_dboard(bool enable, int divisor); + + +/*! + * \brief Enable or disable clock to Tx daughterboard + */ +void clocks_enable_tx_dboard(bool enable, int divisor); + + +#endif /* INCLUDED_CLOCKS_H */ diff --git a/usrp2/firmware/lib/db.h b/usrp2/firmware/lib/db.h new file mode 100644 index 00000000..5828fb00 --- /dev/null +++ b/usrp2/firmware/lib/db.h @@ -0,0 +1,94 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Interface to daughterboard code + */ + +#ifndef INCLUDED_DB_H +#define INCLUDED_DB_H + +#include + + +struct db_base; + +/* pointers to daughterboard structures */ +extern struct db_base *tx_dboard; +extern struct db_base *rx_dboard; + + +//! Intermediate tuning information + +struct tune_result +{ + //! The RF frequency that corresponds to DC in the IF from the daughterboard + u2_fxpt_freq_t baseband_freq; + + //! The DDC/DUC frequency used to down/up convert to/from the target frequency + u2_fxpt_freq_t dxc_freq; + + //! Any differerence btwn target and actual (typically < 0.01 Hz) + u2_fxpt_freq_t residual_freq; + + //! Is the complex baseband spectrum inverted + bool inverted; +}; + + +/*! + * \brief One-time init at powerup + * + * Sets rx_dboard, tx_dboard and initializes daughterboards. + */ +void +db_init(void); + +/*! + * \brief Two stage tuning. Given target_freq, tune LO and DDC/DUC + * + * \param[in] db is the daughterboard instance + * \param[in] target_freq is the freq to translate the complex baseband to/from. + * \param[out] result provides details of the resulting configuration. + * + */ +bool +db_tune(struct db_base *db, u2_fxpt_freq_t target_freq, struct tune_result *result); + + +/* + * Set only the DDC frequency + */ +bool +db_set_ddc_freq(u2_fxpt_freq_t dxc_freq, u2_fxpt_freq_t *actual_dxc_freq); + +/* + * Set only the DUC frequency + */ +bool +db_set_duc_freq(u2_fxpt_freq_t dxc_freq, u2_fxpt_freq_t *actual_dxc_freq); + + +/*! + * \brief Set gain + */ +bool +db_set_gain(struct db_base *db, u2_fxpt_gain_t gain); + + +#endif /* INCLUDED_DB_H */ diff --git a/usrp2/firmware/lib/db_base.h b/usrp2/firmware/lib/db_base.h new file mode 100644 index 00000000..9b5ce051 --- /dev/null +++ b/usrp2/firmware/lib/db_base.h @@ -0,0 +1,68 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_DB_BASE_H +#define INCLUDED_DB_BASE_H + +#include +#include + +/*! + * \brief "base class" for firmware version of daughterboard code + */ +struct db_base { + uint16_t dbid; //< daughterboard ID + + uint16_t is_tx : 1; //< is this a transmit db? + uint16_t is_quadrature : 1; + uint16_t i_and_q_swapped : 1; + uint16_t spectrum_inverted : 1; + + uint16_t output_enables; //< bitmask of which pins should be outputs from FPGA + uint16_t used_pins; //< bitmask of pins used by the daughterboard + + u2_fxpt_freq_t freq_min; //< min freq that can be set (Hz) + u2_fxpt_freq_t freq_max; //< max freq that can be set (Hz) + + u2_fxpt_gain_t gain_min; //< min gain that can be set (dB) + u2_fxpt_gain_t gain_max; //< max gain that can be set (dB) + u2_fxpt_gain_t gain_step_size; //< (dB) + + // u2_fxpt_freq_t lo_offset; + + /* + * Auto T/R control values + */ + uint32_t atr_mask; //< which bits to control + uint32_t atr_txval; //< value to use when transmitting + uint32_t atr_rxval; //< value to use when receiving + + //! delay in clk ticks from when Tx fifo gets data to when T/R switches + // uint32_t atr_tx_delay; + + //! delay in clk ticks from when Tx fifo goes empty to when T/R switches + // uint32_t atr_rx_delay; + + bool (*init)(struct db_base *); + bool (*set_freq)(struct db_base *, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc); + bool (*set_gain)(struct db_base *, u2_fxpt_gain_t gain); + bool (*set_tx_enable)(struct db_base *, bool on); +}; + + +#endif /* INCLUDED_DB_BASE_H */ diff --git a/usrp2/firmware/lib/db_basic.c b/usrp2/firmware/lib/db_basic.c new file mode 100644 index 00000000..0f1ad650 --- /dev/null +++ b/usrp2/firmware/lib/db_basic.c @@ -0,0 +1,161 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + + +#include + +bool db_basic_init(struct db_base *db); +bool db_basic_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc); +bool db_basic_set_gain(struct db_base *db, u2_fxpt_gain_t gain); +bool db_basic_set_tx_enable(struct db_base *, bool on); + +struct db_basic { + struct db_base base; +}; + + +struct db_basic db_basic_tx = { + .base.dbid = 0x0000, + .base.is_tx = true, + .base.output_enables = 0x0000, + .base.used_pins = 0x0000, + .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(-90e9), + .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(90e9), + .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0), + .base.atr_mask = 0, + .base.atr_txval = 0, + .base.atr_rxval = 0, + //.base.atr_tx_delay = 0, + //.base.atr_rx_delay = 0, + + .base.init = db_basic_init, + .base.set_freq = db_basic_set_freq, + .base.set_gain = db_basic_set_gain, + .base.set_tx_enable = db_basic_set_tx_enable, +}; + +struct db_basic db_basic_rx = { + .base.dbid = 0x0001, + .base.is_tx = false, + .base.output_enables = 0x0000, + .base.used_pins = 0x0000, + .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(-90e9), + .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(90e9), + .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.is_quadrature = false, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0), + .base.atr_mask = 0, + .base.atr_txval = 0, + .base.atr_rxval = 0, + //.base.atr_tx_delay = 0, + //.base.atr_rx_delay = 0, + + .base.init = db_basic_init, + .base.set_freq = db_basic_set_freq, + .base.set_gain = db_basic_set_gain, + .base.set_tx_enable = db_basic_set_tx_enable, +}; + +struct db_basic db_lf_tx = { + .base.dbid = 0x000e, + .base.is_tx = true, + .base.output_enables = 0x0000, + .base.used_pins = 0x0000, + .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(-32e6), + .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(32e6), + .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0), + .base.atr_mask = 0, + .base.atr_txval = 0, + .base.atr_rxval = 0, + //.base.atr_tx_delay = 0, + //.base.atr_rx_delay = 0, + + .base.init = db_basic_init, + .base.set_freq = db_basic_set_freq, + .base.set_gain = db_basic_set_gain, + .base.set_tx_enable = db_basic_set_tx_enable, +}; + +struct db_basic db_lf_rx = { + .base.dbid = 0x000f, + .base.is_tx = false, + .base.output_enables = 0x0000, + .base.used_pins = 0x0000, + .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(0), + .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(32e6), + .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0), + .base.is_quadrature = false, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0), + .base.atr_mask = 0, + .base.atr_txval = 0, + .base.atr_rxval = 0, + //.base.atr_tx_delay = 0, + //.base.atr_rx_delay = 0, + + .base.init = db_basic_init, + .base.set_freq = db_basic_set_freq, + .base.set_gain = db_basic_set_gain, + .base.set_tx_enable = db_basic_set_tx_enable, +}; + + +bool +db_basic_init(struct db_base *db) +{ + return true; +} + +bool +db_basic_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc) +{ + *dc = 0; + return true; +} + +bool +db_basic_set_gain(struct db_base *db, u2_fxpt_gain_t gain) +{ + return true; +} + +bool +db_basic_set_tx_enable(struct db_base *db, bool on) +{ + return true; +} + diff --git a/usrp2/firmware/lib/db_init.c b/usrp2/firmware/lib/db_init.c new file mode 100644 index 00000000..d47beb11 --- /dev/null +++ b/usrp2/firmware/lib/db_init.c @@ -0,0 +1,340 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +struct db_base *tx_dboard; // the tx daughterboard that's installed +struct db_base *rx_dboard; // the rx daughterboard that's installed + +extern struct db_base db_basic_tx; +extern struct db_base db_basic_rx; +extern struct db_base db_lf_tx; +extern struct db_base db_lf_rx; +extern struct db_base db_rfx_400_tx; +extern struct db_base db_rfx_400_rx; +extern struct db_base db_tvrx1; +extern struct db_base db_tvrx2; +extern struct db_base db_tvrx3; + +struct db_base *all_dboards[] = { + &db_basic_tx, + &db_basic_rx, + &db_lf_tx, + &db_lf_rx, + &db_rfx_400_tx, + &db_rfx_400_rx, + &db_tvrx1, + &db_tvrx2, + &db_tvrx3, + 0 +}; + + +typedef enum { UDBE_OK, UDBE_NO_EEPROM, UDBE_INVALID_EEPROM } usrp_dbeeprom_status_t; + +static usrp_dbeeprom_status_t +read_raw_dboard_eeprom (unsigned char *buf, int i2c_addr) +{ + if (!eeprom_read (i2c_addr, 0, buf, DB_EEPROM_CLEN)) + return UDBE_NO_EEPROM; + + if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE) + return UDBE_INVALID_EEPROM; + + int sum = 0; + unsigned int i; + for (i = 0; i < DB_EEPROM_CLEN; i++) + sum += buf[i]; + + if ((sum & 0xff) != 0) + return UDBE_INVALID_EEPROM; + + return UDBE_OK; +} + + +/* + * Return DBID, -1 or -2 + */ +static int +read_dboard_eeprom(int i2c_addr) +{ + unsigned char buf[DB_EEPROM_CLEN]; + + usrp_dbeeprom_status_t s = read_raw_dboard_eeprom (buf, i2c_addr); + + //printf("\nread_raw_dboard_eeprom: %d\n", s); + + switch (s){ + case UDBE_OK: + return (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB]; + + case UDBE_NO_EEPROM: + default: + return -1; + + case UDBE_INVALID_EEPROM: + return -2; + } +} + + +static struct db_base * +lookup_dbid(int dbid) +{ + if (dbid < 0) + return 0; + + int i; + for (i = 0; all_dboards[i]; i++) + if (all_dboards[i]->dbid == dbid) + return all_dboards[i]; + + return 0; +} + +static struct db_base * +lookup_dboard(int i2c_addr, struct db_base *default_db, char *msg) +{ + struct db_base *db; + int dbid = read_dboard_eeprom(i2c_addr); + printf("%s dbid: 0x%x\n", msg, dbid); + + if (dbid < 0){ // there was some kind of problem. Treat as Basic Tx + return default_db; + } + else if ((db = lookup_dbid(dbid)) == 0){ + return default_db; + printf("No daugherboard code for dbid = 0x%x\n", dbid); + } + return db; +} + +static void +set_atr_regs(int bank, struct db_base *db) +{ + uint32_t val[4]; + int shift; + int mask; + int i; + + val[ATR_IDLE] = db->atr_rxval; + val[ATR_RX] = db->atr_rxval; + val[ATR_TX] = db->atr_txval; + val[ATR_FULL] = db->atr_txval; + + if (bank == GPIO_TX_BANK){ + mask = 0xffff0000; + shift = 16; + } + else { + mask = 0x0000ffff; + shift = 0; + } + + for (i = 0; i < 4; i++){ + int t = (atr_regs->v[i] & ~mask) | ((val[i] << shift) & mask); + //printf("atr_regs[%d] = 0x%x\n", i, t); + atr_regs->v[i] = t; + } +} + +static void +set_gpio_mode(int bank, struct db_base *db) +{ + int i; + + hal_gpio_set_ddr(bank, db->output_enables, 0xffff); + set_atr_regs(bank, db); + + for (i = 0; i < 16; i++){ + if (db->used_pins & (1 << i)){ + // set to either GPIO_SEL_SW or GPIO_SEL_ATR + hal_gpio_set_sel(bank, i, (db->atr_mask & (1 << i)) ? 'a' : 's'); + } + } +} + +void +db_init(void) +{ + + tx_dboard = lookup_dboard(I2C_ADDR_TX_A, &db_basic_tx, "Tx"); + //printf("db_init: tx dbid = 0x%x\n", tx_dboard->dbid); + set_gpio_mode(GPIO_TX_BANK, tx_dboard); + tx_dboard->init(tx_dboard); + + rx_dboard = lookup_dboard(I2C_ADDR_RX_A, &db_basic_rx, "Rx"); + //printf("db_init: rx dbid = 0x%x\n", rx_dboard->dbid); + set_gpio_mode(GPIO_RX_BANK, rx_dboard); + rx_dboard->init(rx_dboard); +} + +/*! + * Calculate the frequency to use for setting the digital down converter. + * + * \param[in] target_freq desired RF frequency (Hz) + * \param[in] baseband_freq the RF frequency that corresponds to DC in the IF. + * + * \param[out] dxc_freq is the value for the ddc + * \param[out] inverted is true if we're operating in an inverted Nyquist zone. +*/ +void +calc_dxc_freq(u2_fxpt_freq_t target_freq, u2_fxpt_freq_t baseband_freq, + u2_fxpt_freq_t *dxc_freq, bool *inverted) +{ + u2_fxpt_freq_t fs = U2_DOUBLE_TO_FXPT_FREQ(100e6); // converter sample rate + u2_fxpt_freq_t delta = target_freq - baseband_freq; + + printf("calc_dxc_freq\n"); + printf(" fs = "); print_fxpt_freq(fs); newline(); + printf(" target = "); print_fxpt_freq(target_freq); newline(); + printf(" baseband = "); print_fxpt_freq(baseband_freq); newline(); + printf(" delta = "); print_fxpt_freq(delta); newline(); + +#if 0 + printf("--- printed as uint64_t ---\n"); + printf(" fs = "); print_uint64(fs); newline(); + printf(" target = "); print_uint64(target_freq); newline(); + printf(" baseband = "); print_uint64(baseband_freq); newline(); + printf(" delta = "); print_uint64(delta); newline(); +#endif + + if (delta >= 0){ + while (delta > fs) + delta -= fs; + if (delta <= fs/2){ // non-inverted region + *dxc_freq = -delta; + *inverted = false; + } + else { // inverted region + *dxc_freq = delta - fs; + *inverted = true; + } + } + else { + while (delta < -fs){ + delta += fs; + if (delta >= -fs/2){ // non-inverted region + *dxc_freq = -delta; + *inverted = false; + } + else { // inverted region + *dxc_freq = delta + fs; + *inverted = true; + } + } + } +} + + +bool +db_tune(struct db_base *db, u2_fxpt_freq_t target_freq, struct tune_result *result) +{ + memset(result, 0, sizeof(*result)); + bool inverted = false; + u2_fxpt_freq_t dxc_freq; + u2_fxpt_freq_t actual_dxc_freq; + + // Ask the d'board to tune as closely as it can to target_freq + bool ok = db->set_freq(db, target_freq, &result->baseband_freq); + + // Calculate the DDC setting that will downconvert the baseband from the + // daughterboard to our target frequency. + calc_dxc_freq(target_freq, result->baseband_freq, &dxc_freq, &inverted); + + // If the spectrum is inverted, and the daughterboard doesn't do + // quadrature downconversion, we can fix the inversion by flipping the + // sign of the dxc_freq... (This only happens using the basic_rx board) + + if (db->spectrum_inverted) + inverted = !inverted; + + if (inverted && !db->is_quadrature){ + dxc_freq = -dxc_freq; + inverted = !inverted; + } + + if (db->is_tx){ + dxc_freq = -dxc_freq; // down conversion versus up conversion + ok &= db_set_duc_freq(dxc_freq, &actual_dxc_freq); + } + else { + ok &= db_set_ddc_freq(dxc_freq, &actual_dxc_freq); + } + + result->dxc_freq = dxc_freq; + result->residual_freq = dxc_freq - actual_dxc_freq; + result->inverted = inverted; + return ok; +} + +static int32_t +compute_freq_control_word(u2_fxpt_freq_t target_freq, u2_fxpt_freq_t *actual_freq) +{ + // If we were using floating point, we'd calculate + // master = 100e6; + // v = (int) rint(target_freq / master_freq) * pow(2.0, 32.0); + + printf("compute_freq_control_word\n"); + printf(" target_freq = "); print_fxpt_freq(target_freq); newline(); + + int32_t master_freq = 100000000; // 100M + + int32_t v = ((target_freq << 12)) / master_freq; + printf(" fcw = %d\n", v); + + *actual_freq = (v * (int64_t) master_freq) >> 12; + + printf(" actual = "); print_fxpt_freq(*actual_freq); newline(); + + return v; +} + + +bool +db_set_ddc_freq(u2_fxpt_freq_t dxc_freq, u2_fxpt_freq_t *actual_dxc_freq) +{ + int32_t v = compute_freq_control_word(dxc_freq, actual_dxc_freq); + dsp_rx_regs->freq = v; + return true; +} + +bool +db_set_duc_freq(u2_fxpt_freq_t dxc_freq, u2_fxpt_freq_t *actual_dxc_freq) +{ + int32_t v = compute_freq_control_word(dxc_freq, actual_dxc_freq); + dsp_tx_regs->freq = v; + return true; +} + +bool +db_set_gain(struct db_base *db, u2_fxpt_gain_t gain) +{ + return db->set_gain(db, gain); +} diff --git a/usrp2/firmware/lib/db_rfx.c b/usrp2/firmware/lib/db_rfx.c new file mode 100644 index 00000000..d5611292 --- /dev/null +++ b/usrp2/firmware/lib/db_rfx.c @@ -0,0 +1,609 @@ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +bool rfx_init_rx(struct db_base *db); +bool rfx_init_tx(struct db_base *db); +bool rfx_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc); +bool rfx_set_gain_rx(struct db_base *db, u2_fxpt_gain_t gain); +bool rfx_set_gain_tx(struct db_base *db, u2_fxpt_gain_t gain); +bool rfx_set_tx_enable(struct db_base *, bool on); + +// Control Latch Defines +#define P 0 // Prescalar value for setting in regs, must match the next line... +#define PRESCALER 8 // Presacalar value for computations +#define PD 0 // Power down, 0 = normal operation +#define PL 0 // PLL power output +#define MTLD 1 // Mute till lock detect +#define CPGAIN 0 // Charge pump gain, use setting 1, also in N-reg +#define CP3S 0 // Charge pump tri-state, 0 = normal operation +#define PDP 1 // Phase detector polarity +#define MUXOUT 1 // Digital lock detect, active high +#define CR 0 // normal operation +#define PC 1 // core power + +// N Latch Defines +#define DIVSEL 0 // N Counter always operates on full rate +#define N_RSV 0 + +// R Latch Defines +#define R_RSV 0 +#define R_BSC 3 +#define R_TMB 0 +#define R_LDP 1 +#define R_ABP 0 +#define R_DIV 16 + +#define phdet_freq (U2_DOUBLE_TO_FXPT_FREQ(100e6/R_DIV)) + +// IO Pin functions +#define POWER_UP (1 << 7) // Low enables power supply +#define ANT_SW (1 << 6) // On TX DB, 0 = TX, 1 = RX, on RX DB 0 = main ant, 1 = RX2 +#define MIX_EN (1 << 5) // Enable appropriate mixer +#define LOCKDET_MASK (1 << 2) // Input pin + +struct db_rfx_common { + // RFX common stuff + unsigned char DIV2; + unsigned char CP1; + unsigned char CP2; + int freq_mult; + int spi_mask; +}; + +struct db_rfx_dummy { + struct db_base base; + struct db_rfx_common common; +}; + + +struct db_rfx_400_rx { + struct db_base base; + struct db_rfx_common common; +}; + +struct db_rfx_400_tx { + struct db_base base; + struct db_rfx_common common; +}; + +struct db_rfx_900_rx { + struct db_base base; + struct db_rfx_common common; +}; + +struct db_rfx_900_tx { + struct db_base base; + struct db_rfx_common common; +}; + +struct db_rfx_1200_rx { + struct db_base base; + struct db_rfx_common common; +}; + +struct db_rfx_1200_tx { + struct db_base base; + struct db_rfx_common common; +}; + +struct db_rfx_1800_rx { + struct db_base base; + struct db_rfx_common common; +}; + +struct db_rfx_1800_tx { + struct db_base base; + struct db_rfx_common common; +}; + +struct db_rfx_2400_rx { + struct db_base base; + struct db_rfx_common common; +}; + +struct db_rfx_2400_tx { + struct db_base base; + struct db_rfx_common common; +}; + + +/* + * The class instances + */ +struct db_rfx_400_rx db_rfx_400_rx = { + .base.dbid = 0x0024, + .base.is_tx = false, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_rx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_rx, + .base.set_tx_enable = 0, + .base.atr_mask = 0x00E0, + .base.atr_txval = POWER_UP, + .base.atr_rxval = POWER_UP|MIX_EN, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 0, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_RX_DB, + .common.freq_mult = 2 +}; + + +struct db_rfx_400_tx db_rfx_400_tx = { + .base.dbid = 0x0028, + .base.is_tx = true, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_tx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_tx, + .base.set_tx_enable = rfx_set_tx_enable, + .base.atr_mask = 0x00E0, + .base.atr_txval = POWER_UP|MIX_EN, + .base.atr_rxval = POWER_UP|ANT_SW, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 1, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_TX_DB, + .common.freq_mult = 2 +}; + +struct db_rfx_900_rx db_rfx_900_rx = { + .base.dbid = 0x0025, + .base.is_tx = false, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_rx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_rx, + .base.set_tx_enable = 0, + .base.atr_mask = 0x00E0, + .base.atr_txval = 0, + .base.atr_rxval = MIX_EN, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 1, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_RX_DB, + .common.freq_mult = 2 +}; + + +struct db_rfx_900_tx db_rfx_900_tx = { + .base.dbid = 0x0029, + .base.is_tx = true, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_tx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_tx, + .base.set_tx_enable = rfx_set_tx_enable, + .base.atr_mask = 0x00E0, + .base.atr_txval = MIX_EN, + .base.atr_rxval = ANT_SW, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 1, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_TX_DB, + .common.freq_mult = 2 +}; + +struct db_rfx_1200_rx db_rfx_1200_rx = { + .base.dbid = 0x0026, + .base.is_tx = false, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_rx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_rx, + .base.set_tx_enable = 0, + .base.atr_mask = 0x00E0, + .base.atr_txval = 0, + .base.atr_rxval = MIX_EN, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 1, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_RX_DB, + .common.freq_mult = 2 +}; + + +struct db_rfx_1200_tx db_rfx_1200_tx = { + .base.dbid = 0x002a, + .base.is_tx = true, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_tx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_tx, + .base.set_tx_enable = rfx_set_tx_enable, + .base.atr_mask = 0x00E0, + .base.atr_txval = MIX_EN, + .base.atr_rxval = ANT_SW, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 1, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_TX_DB, + .common.freq_mult = 2 +}; + +struct db_rfx_1800_rx db_rfx_1800_rx = { + .base.dbid = 0x0034, + .base.is_tx = false, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_rx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_rx, + .base.set_tx_enable = 0, + .base.atr_mask = 0x00E0, + .base.atr_txval = 0, + .base.atr_rxval = MIX_EN, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 0, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_RX_DB, + .common.freq_mult = 1 +}; + + +struct db_rfx_1800_tx db_rfx_1800_tx = { + .base.dbid = 0x0035, + .base.is_tx = true, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_tx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_tx, + .base.set_tx_enable = rfx_set_tx_enable, + .base.atr_mask = 0x00E0, + .base.atr_txval = MIX_EN, + .base.atr_rxval = ANT_SW, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 0, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_TX_DB, + .common.freq_mult = 1 +}; + + +struct db_rfx_2400_rx db_rfx_2400_rx = { + .base.dbid = 0x0027, + .base.is_tx = false, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_rx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_rx, + .base.set_tx_enable = 0, + .base.atr_mask = 0x00E0, + .base.atr_txval = 0, + .base.atr_rxval = MIX_EN, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 0, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_RX_DB, + .common.freq_mult = 1 +}; + + +struct db_rfx_2400_tx db_rfx_2400_tx = { + .base.dbid = 0x002b, + .base.is_tx = true, + .base.output_enables = 0x00E0, + .base.used_pins = 0x00FF, + //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = true, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = rfx_init_tx, + .base.set_freq = rfx_set_freq, + .base.set_gain = rfx_set_gain_tx, + .base.set_tx_enable = rfx_set_tx_enable, + .base.atr_mask = 0x00E0, + .base.atr_txval = MIX_EN, + .base.atr_rxval = ANT_SW, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.DIV2 = 0, + .common.CP1 = 7, + .common.CP2 = 7, + .common.spi_mask = SPI_SS_TX_DB, + .common.freq_mult = 1 +}; + + +bool +rfx_init_tx(struct db_base *dbb) +{ + //struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb; + clocks_enable_tx_dboard(true, 0); + return true; +} + +bool +rfx_init_rx(struct db_base *dbb) +{ + //struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb; + clocks_enable_rx_dboard(true, 0); + + // test gain + dbb->set_gain(dbb,U2_DOUBLE_TO_FXPT_GAIN(45.0)); + printf("set the gain\n"); + return true; +} + +bool +rfx_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc) +{ + *dc = 0; + struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb; + //u2_fxpt_freq_t desired_n = db->common.freq_mult*freq/phdet_freq; + //int N_DIV = u2_fxpt_freq_round_to_int(desired_n); + u2_fxpt_freq_t desired_n = ((1LL<<20) * db->common.freq_mult*freq)/phdet_freq; + int N_DIV = u2_fxpt_freq_round_to_int(desired_n); + int B = N_DIV/PRESCALER; + int A = N_DIV - PRESCALER*B; + + if(Bcommon.DIV2<<22)|(CPGAIN<<21)|(B<<8)|(N_RSV<<7)|(A<<2)|2; + int C = (P<<22)|(PD<<20)|(db->common.CP2<<17)|(db->common.CP1<<14)|(PL<<12)| + (MTLD<<11)|(CPGAIN<<10)|(CP3S<<9)|(PDP<<8)|(MUXOUT<<5)|(CR<<4)|(PC<<2)|0; + + spi_transact(SPI_TXONLY,db->common.spi_mask,R,24,SPIF_PUSH_FALL); + spi_transact(SPI_TXONLY,db->common.spi_mask,C,24,SPIF_PUSH_FALL); + mdelay(10); + spi_transact(SPI_TXONLY,db->common.spi_mask,N,24,SPIF_PUSH_FALL); + + printf("A = %d, B = %d, N_DIV = %d\n",A, B, N_DIV); + *dc = (N_DIV * phdet_freq) / db->common.freq_mult; + return true; +} + +bool +rfx_set_gain_tx(struct db_base *dbb, u2_fxpt_gain_t gain) +{ + // There is no analog gain control on TX + return true; +} + +bool +rfx_set_gain_rx(struct db_base *dbb, u2_fxpt_gain_t gain) +{ + struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb; + + u2_fxpt_gain_t MAXGAIN = U2_DOUBLE_TO_FXPT_GAIN(70.0); + + int offset_q8 = (int)(1.2/3.3*4096*(1<<15)); + int slope_q8 = (int)(-1.0/45.0*4096/3.3*256); + int dacword = ((slope_q8 * gain) + offset_q8)>>15; + printf("DACWORD %d\n",dacword); + lsdac_write_rx(1,dacword); + return true; + /* + def set_gain(self, gain): + """ + Set the gain. + + @param gain: gain in decibels + @returns True/False + """ + maxgain = self.gain_range()[1] - self._u.pga_max() + mingain = self.gain_range()[0] + if gain > maxgain: + pga_gain = gain-maxgain + assert pga_gain <= self._u.pga_max() + agc_gain = maxgain + else: + pga_gain = 0 + agc_gain = gain + V_maxgain = .2 + V_mingain = 1.2 + V_fullscale = 3.3 + dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale + assert dac_value>=0 and dac_value<4096 + return self._u.write_aux_dac(self._which, 0, int(dac_value)) and \ + self._set_pga(int(pga_gain)) + + def gain_range(self): + return (self._u.pga_min(), self._u.pga_max() + 70, 0.05) -- For 900-2400 + return (self._u.pga_min(), self._u.pga_max() + 45, 0.035) -- For 400 + */ +} + + +bool +rfx_set_tx_enable(struct db_base *dbb, bool on) +{ + struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb; + + // FIXME + + return false; +} + +bool +rfx_lock_detect(struct db_base *dbb) +{ + struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb; + int pins; + pins = hal_gpio_read( db->base.is_tx ? GPIO_TX_BANK : GPIO_RX_BANK ); + if(pins & LOCKDET_MASK) + return true; + return false; +} + +/* + def select_rx_antenna(self, which_antenna): + """ + Specify which antenna port to use for reception. + @param which_antenna: either 'TX/RX' or 'RX2' + """ + if which_antenna in (0, 'TX/RX'): + self._u.write_io(self._which, 0, RX2_RX1N) + elif which_antenna in (1, 'RX2'): + self._u.write_io(self._which, RX2_RX1N, RX2_RX1N) + else: + raise ValueError, "which_antenna must be either 'TX/RX' or 'RX2'" + + def set_gain(self, gain): + """ + Set the gain. + + @param gain: gain in decibels + @returns True/False + """ + maxgain = self.gain_range()[1] - self._u.pga_max() + mingain = self.gain_range()[0] + if gain > maxgain: + pga_gain = gain-maxgain + assert pga_gain <= self._u.pga_max() + agc_gain = maxgain + else: + pga_gain = 0 + agc_gain = gain + V_maxgain = .2 + V_mingain = 1.2 + V_fullscale = 3.3 + dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) + V_mingain)*4096/V_fullscale + assert dac_value>=0 and dac_value<4096 + return self._u.write_aux_dac(self._which, 0, int(dac_value)) and \ + self._set_pga(int(pga_gain)) + + def gain_range(self): + return (self._u.pga_min(), self._u.pga_max() + 70, 0.05) -- For 900-2400 + return (self._u.pga_min(), self._u.pga_max() + 45, 0.035) -- For 400 + +*/ diff --git a/usrp2/firmware/lib/db_tvrx.c b/usrp2/firmware/lib/db_tvrx.c new file mode 100644 index 00000000..062d7189 --- /dev/null +++ b/usrp2/firmware/lib/db_tvrx.c @@ -0,0 +1,240 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +bool tvrx_init(struct db_base *db); +bool tvrx_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc); +bool tvrx_set_gain(struct db_base *db, u2_fxpt_gain_t gain); + +#define I2C_ADDR 0x60 +#define ref_freq (U2_DOUBLE_TO_FXPT_FREQ(4e6)/640*8) + +#define ref_div 640 /* choices are 640, 512, 1024 */ + +#if (ref_div == 640) +#define ref_div_byte 0 +#else +#if (ref_div == 512) +#define ref_div_byte 0x6 +#else +#define ref_div_byte 0x2 +#endif +#endif + +#define fast_tuning 0x40 + +#define control_byte_1 (0x88|fast_tuning|ref_div_byte) + + +struct db_tvrx_common { + // TVRX common stuff + u2_fxpt_freq_t first_if; + u2_fxpt_freq_t second_if; +}; + +struct db_tvrx_dummy { + struct db_base base; + struct db_tvrx_common common; +}; + +struct db_tvrx1 { + struct db_base base; + struct db_tvrx_common common; +}; + +struct db_tvrx2 { + struct db_base base; + struct db_tvrx_common common; +}; + +struct db_tvrx3 { + struct db_base base; + struct db_tvrx_common common; +}; + +/* The class instances */ +struct db_tvrx1 db_tvrx1 = { + .base.dbid = 0x0003, + .base.is_tx = false, + .base.output_enables = 0x0000, + .base.used_pins = 0x0000, + .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(50e6), + .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(860e6), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = false, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = tvrx_init, + .base.set_freq = tvrx_set_freq, + .base.set_gain = tvrx_set_gain, + .base.set_tx_enable = 0, + .base.atr_mask = 0x0000, + .base.atr_txval = 0, + .base.atr_rxval = 0, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.first_if = U2_DOUBLE_TO_FXPT_FREQ(43.75e6), + .common.second_if = U2_DOUBLE_TO_FXPT_FREQ(5.75e6), +}; + +struct db_tvrx2 db_tvrx2 = { + .base.dbid = 0x000c, + .base.is_tx = false, + .base.output_enables = 0x0000, + .base.used_pins = 0x0000, + .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(50e6), + .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(860e6), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = false, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = tvrx_init, + .base.set_freq = tvrx_set_freq, + .base.set_gain = tvrx_set_gain, + .base.set_tx_enable = 0, + .base.atr_mask = 0x0000, + .base.atr_txval = 0, + .base.atr_rxval = 0, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.first_if = U2_DOUBLE_TO_FXPT_FREQ(44e6), + .common.second_if = U2_DOUBLE_TO_FXPT_FREQ(44e6), +}; + +struct db_tvrx3 db_tvrx3 = { + .base.dbid = 0x0040, + .base.is_tx = false, + .base.output_enables = 0x0000, + .base.used_pins = 0x0000, + .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(50e6), + .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(860e6), + //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx), + //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx), + .base.is_quadrature = false, + .base.i_and_q_swapped = false, + .base.spectrum_inverted = false, + //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6), + .base.init = tvrx_init, + .base.set_freq = tvrx_set_freq, + .base.set_gain = tvrx_set_gain, + .base.set_tx_enable = 0, + .base.atr_mask = 0x0000, + .base.atr_txval = 0, + .base.atr_rxval = 0, + // .base.atr_tx_delay = + // .base.atr_rx_delay = + .common.first_if = U2_DOUBLE_TO_FXPT_FREQ(44e6), + .common.second_if = U2_DOUBLE_TO_FXPT_FREQ(44e6), +}; + +bool +tvrx_init(struct db_base *dbb) +{ + struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb; + db->base.set_gain(dbb,U2_DOUBLE_TO_FXPT_GAIN(94.0)); + return true; +} + +bool +tvrx_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc) +{ + *dc = 0; + if (freq < dbb->freq_min || freq > dbb->freq_max) + return false; + + struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb; + + u2_fxpt_freq_t target_lo_freq = freq + db->common.first_if; + int N_DIV = u2_fxpt_freq_round_to_int(((1LL<<20) * target_lo_freq)/ref_freq); + + u2_fxpt_freq_t actual_lo_freq = ref_freq * N_DIV; + u2_fxpt_freq_t actual_freq = actual_lo_freq - db->common.first_if; + if(N_DIV > 32767) + return false; + + printf("N_DIV = %d, actual_freq = %d, actual_lo_freq = %d\n", + N_DIV, u2_fxpt_freq_round_to_int(actual_freq),u2_fxpt_freq_round_to_int(actual_freq)); + + char buf[4]; + buf[0] = (N_DIV>>8) & 0xff; + buf[1] = N_DIV & 0xff; + buf[2] = control_byte_1; + buf[3] = (freq < U2_DOUBLE_TO_FXPT_FREQ(158e6)) ? 0xa8 : // VHF LOW + (freq < U2_DOUBLE_TO_FXPT_FREQ(464e6)) ? 0x98 : // VHF HIGH + 0x38; // UHF + + *dc = actual_freq - db->common.second_if; + return i2c_write(I2C_ADDR,buf,4); +} + +bool +tvrx_set_gain(struct db_base *dbb, u2_fxpt_gain_t gain) +{ + struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb; + int rfgain; + int ifgain; + if(gain>U2_DOUBLE_TO_FXPT_GAIN(95.0)) + return false; + if(gain<0) + return false; + + if(gain>U2_DOUBLE_TO_FXPT_GAIN(60.0)) { + rfgain = U2_DOUBLE_TO_FXPT_GAIN(60.0); + ifgain = gain-U2_DOUBLE_TO_FXPT_GAIN(60.0); + } else { + rfgain = gain; + ifgain = 0; + } + + int rf_slope_q8 = 256 * 4096 * 2.5 / 60.0 / 1.22 / 3.3; + int rf_offset_q8 = 128 * 256 * 4096 * 1.25 / 1.22 / 3.3; + int if_slope_q8 = 256 * 4096 * 2.25 / 35.0 / 1.22 / 3.3; + int if_offset_q8 = 128 * 256 * 4096 * 1.4 / 1.22 / 3.3; + + + int rfdac = (rfgain*rf_slope_q8 + rf_offset_q8)>>15; + int ifdac = (ifgain*if_slope_q8 + if_offset_q8)>>15; + lsdac_write_rx(0,rfdac); + lsdac_write_rx(1,ifdac); + + printf("Setting gain %d, rf %d, if %d\n",gain,rfdac,ifdac); + return true; +} + + +bool +tvrx_lock_detect(struct db_base *dbb) +{ + struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb; + return true; +} diff --git a/usrp2/firmware/lib/dbsm.c b/usrp2/firmware/lib/dbsm.c new file mode 100644 index 00000000..5e2042be --- /dev/null +++ b/usrp2/firmware/lib/dbsm.c @@ -0,0 +1,298 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Double Buffering State Machine + */ + +#include "dbsm.h" +#include "memory_map.h" +#include "buffer_pool.h" +#include "bool.h" +#include "nonstdio.h" +#include + +typedef enum { + BS_EMPTY, + BS_FILLING, + BS_FULL, + BS_EMPTYING, +} buffer_state_t; + +buffer_state_t buffer_state[NBUFFERS]; + +bool +dbsm_nop_inspector(dbsm_t *sm, int buf_this) +{ + return false; +} + +void +dbsm_init(dbsm_t *sm, int buf0, + const buf_cmd_args_t *recv, const buf_cmd_args_t *send, + inspector_t inspect) +{ + if (buf0 & 0x1) // must be even + abort(); + + sm->buf0 = buf0; + sm->running = false; + sm->recv_args = *recv; + sm->send_args = *send; + + sm->rx_idle = true; + sm->tx_idle = true; + + sm->inspect = inspect; + + // How much to adjust the last_line register. + // It's 1 for everything but the ethernet. + sm->last_line_adj = recv->port == PORT_ETH ? 3 : 1; + + buffer_state[sm->buf0] = BS_EMPTY; + buffer_state[sm->buf0 ^ 1] = BS_EMPTY; + + sm->precomputed_receive_to_buf_ctrl_word[0] = + (BPC_READ + | BPC_BUFFER(sm->buf0) + | BPC_PORT(sm->recv_args.port) + | BPC_STEP(1) + | BPC_FIRST_LINE(sm->recv_args.first_line) + | BPC_LAST_LINE(sm->recv_args.last_line)); + + sm->precomputed_receive_to_buf_ctrl_word[1] = + (BPC_READ + | BPC_BUFFER(sm->buf0 ^ 1) + | BPC_PORT(sm->recv_args.port) + | BPC_STEP(1) + | BPC_FIRST_LINE(sm->recv_args.first_line) + | BPC_LAST_LINE(sm->recv_args.last_line)); + + sm->precomputed_send_from_buf_ctrl_word[0] = + (BPC_WRITE + | BPC_BUFFER(sm->buf0) + | BPC_PORT(sm->send_args.port) + | BPC_STEP(1) + | BPC_FIRST_LINE(sm->send_args.first_line) + | BPC_LAST_LINE(0)); // last line filled in at runtime + + sm->precomputed_send_from_buf_ctrl_word[1] = + (BPC_WRITE + | BPC_BUFFER(sm->buf0 ^ 1) + | BPC_PORT(sm->send_args.port) + | BPC_STEP(1) + | BPC_FIRST_LINE(sm->send_args.first_line) + | BPC_LAST_LINE(0)); // last line filled in at runtime + +} + +static inline void +dbsm_receive_to_buf(dbsm_t *sm, int bufno) +{ + buffer_pool_ctrl->ctrl = sm->precomputed_receive_to_buf_ctrl_word[bufno & 1]; +} + +static inline void +dbsm_send_from_buf(dbsm_t *sm, int bufno) +{ + buffer_pool_ctrl->ctrl = + (sm->precomputed_send_from_buf_ctrl_word[bufno & 1] + | BPC_LAST_LINE(buffer_pool_status->last_line[bufno] - sm->last_line_adj)); +} + +void +dbsm_start(dbsm_t *sm) +{ + // printf("dbsm_start: buf0 = %d, recv_port = %d\n", sm->buf0, sm->recv_args.port); + + sm->running = true; + + buffer_state[sm->buf0] = BS_EMPTY; + buffer_state[sm->buf0 ^ 1] = BS_EMPTY; + + bp_clear_buf(sm->buf0); + bp_clear_buf(sm->buf0 ^ 1); + + sm->tx_idle = true; + sm->rx_idle = false; + dbsm_receive_to_buf(sm, sm->buf0); + buffer_state[sm->buf0] = BS_FILLING; + +} + + +void +dbsm_stop(dbsm_t *sm) +{ + sm->running = false; + bp_clear_buf(sm->buf0); + bp_clear_buf(sm->buf0 ^ 1); + buffer_state[sm->buf0] = BS_EMPTY; + buffer_state[sm->buf0 ^ 1] = BS_EMPTY; +} + +static void dbsm_process_helper(dbsm_t *sm, int buf_this); +static void dbsm_error_helper(dbsm_t *sm, int buf_this); + +void +dbsm_process_status(dbsm_t *sm, uint32_t status) +{ + if (!sm->running) + return; + + if (status & (BPS_ERROR(sm->buf0) | BPS_ERROR(sm->buf0 ^ 1))){ + putchar('E'); + // Most likely an ethernet Rx error. We just restart the transfer. + if (status & (BPS_ERROR(sm->buf0))) + dbsm_error_helper(sm, sm->buf0); + + if (status & (BPS_ERROR(sm->buf0 ^ 1))) + dbsm_error_helper(sm, sm->buf0 ^ 1); + } + + if (status & BPS_DONE(sm->buf0)) + dbsm_process_helper(sm, sm->buf0); + + if (status & BPS_DONE(sm->buf0 ^ 1)) + dbsm_process_helper(sm, sm->buf0 ^ 1); +} + +static void +dbsm_process_helper(dbsm_t *sm, int buf_this) +{ + int buf_other = buf_this ^ 1; + + if (1){ + bp_clear_buf(buf_this); + + if (buffer_state[buf_this] == BS_FILLING){ + buffer_state[buf_this] = BS_FULL; + // + // does s/w handle this packet? + // + if (sm->inspect(sm, buf_this)){ + // s/w handled the packet; refill the buffer + dbsm_receive_to_buf(sm, buf_this); + buffer_state[buf_this] = BS_FILLING; + } + + else { // s/w didn't handle this; pass it on + + if(buffer_state[buf_other] == BS_EMPTY){ + dbsm_receive_to_buf(sm, buf_other); + buffer_state[buf_other] = BS_FILLING; + } + else + sm->rx_idle = true; + + if (sm->tx_idle){ + sm->tx_idle = false; + dbsm_send_from_buf(sm, buf_this); + buffer_state[buf_this] = BS_EMPTYING; + } + } + } + else { // buffer was emptying + buffer_state[buf_this] = BS_EMPTY; + if (sm->rx_idle){ + sm->rx_idle = false; + dbsm_receive_to_buf(sm, buf_this); + buffer_state[buf_this] = BS_FILLING; + } + if (buffer_state[buf_other] == BS_FULL){ + dbsm_send_from_buf(sm, buf_other); + buffer_state[buf_other] = BS_EMPTYING; + } + else + sm->tx_idle = true; + } + } +} + +static void +dbsm_error_helper(dbsm_t *sm, int buf_this) +{ + bp_clear_buf(buf_this); // clears ERROR flag + + if (buffer_state[buf_this] == BS_FILLING){ + dbsm_receive_to_buf(sm, buf_this); // restart the xfer + } + else { // buffer was emptying + dbsm_send_from_buf(sm, buf_this); // restart the xfer + } +} + +/* + * Handle DSP Tx underrun + */ +void +dbsm_handle_tx_underrun(dbsm_t *sm) +{ + // clear the DSP Tx state machine + dsp_tx_regs->clear_state = 1; + + // If there's a buffer that's empyting, clear it & flush xfer + + if (buffer_state[sm->buf0] == BS_EMPTYING){ + bp_clear_buf(sm->buf0); + dsp_tx_regs->clear_state = 1; // flush partial packet + // drop frame in progress on ground. Pretend it finished + dbsm_process_helper(sm, sm->buf0); + } + else if (buffer_state[sm->buf0 ^ 1] == BS_EMPTYING){ + bp_clear_buf(sm->buf0 ^ 1); + dsp_tx_regs->clear_state = 1; // flush partial packet + // drop frame in progress on ground. Pretend it finished + dbsm_process_helper(sm, sm->buf0 ^ 1); + } +} + +/* + * Handle DSP Rx overrun + */ +void +dbsm_handle_rx_overrun(dbsm_t *sm) +{ + dsp_rx_regs->clear_state = 1; + + // If there's a buffer that's filling, clear it. + // Any restart will be the job of the caller. + + if (buffer_state[sm->buf0] == BS_FILLING) + bp_clear_buf(sm->buf0); + + if (buffer_state[sm->buf0 ^1] == BS_FILLING) + bp_clear_buf(sm->buf0 ^ 1); +} + +void +dbsm_wait_for_opening(dbsm_t *sm) +{ + if (buffer_state[sm->buf0] == BS_EMPTYING){ + // wait for xfer to complete + int mask = BPS_DONE(sm->buf0) | BPS_ERROR(sm->buf0) | BPS_IDLE(sm->buf0); + while ((buffer_pool_status->status & mask) == 0) + ; + } + else if (buffer_state[sm->buf0 ^ 1] == BS_EMPTYING){ + // wait for xfer to complete + int mask = BPS_DONE(sm->buf0 ^ 1) | BPS_ERROR(sm->buf0 ^ 1) | BPS_IDLE(sm->buf0 ^ 1); + while ((buffer_pool_status->status & mask) == 0) + ; + } +} diff --git a/usrp2/firmware/lib/dbsm.h b/usrp2/firmware/lib/dbsm.h new file mode 100644 index 00000000..3a64bf0d --- /dev/null +++ b/usrp2/firmware/lib/dbsm.h @@ -0,0 +1,90 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_DBSM_H +#define INCLUDED_DBSM_H + +/* + * Double Buffering State Machine + */ + +#include +#include "bool.h" + +struct _dbsm; +typedef struct _dbsm dbsm_t; + +/* + * pointer to function that does packet inspection. + * + * If one of these returns true, it means that the s/w + * handled that packet, and that it should NOT be passed + * on to the normal destination port. + */ +typedef bool (*inspector_t)(dbsm_t *sm, int buf_this); + +bool dbsm_nop_inspector(dbsm_t *sm, int buf_this); // returns false + + +typedef struct +{ + uint16_t port; + uint16_t first_line; + uint16_t last_line; +} buf_cmd_args_t; + +/*! + * double buffer state machine + */ +struct _dbsm +{ + uint8_t buf0; // Must be even. This machine uses buf0 and buf0+1 + uint8_t running; + uint8_t rx_idle; + uint8_t tx_idle; + buf_cmd_args_t recv_args; + buf_cmd_args_t send_args; + inspector_t inspect; + uint32_t precomputed_receive_to_buf_ctrl_word[2]; + uint32_t precomputed_send_from_buf_ctrl_word[2]; + int last_line_adj; +}; + +void dbsm_init(dbsm_t *sm, int buf0, + const buf_cmd_args_t *recv, const buf_cmd_args_t *send, + inspector_t inspect); + +void dbsm_start(dbsm_t *sm); +void dbsm_stop(dbsm_t *sm); +void dbsm_process_status(dbsm_t *sm, uint32_t status); +void dbsm_handle_tx_underrun(dbsm_t *sm); +void dbsm_handle_rx_overrun(dbsm_t *sm); + +/* + * The cpu calls this when it want to ensure that it can send a buffer + * to the same destination being used by this state machine. + * + * If neither buffer is EMPTYING it returns immediately. If a buffer + * is EMPYTING, it waits for the h/w to transition to the DONE or + * ERROR state. + * + * When this function returns, the caller queues it's buffer and busy + * waits for it to complete. + */ +void dbsm_wait_for_opening(dbsm_t *sm); + +#endif /* INCLUDED_DBSM_H */ diff --git a/usrp2/firmware/lib/eeprom.c b/usrp2/firmware/lib/eeprom.c new file mode 100644 index 00000000..b12ffe08 --- /dev/null +++ b/usrp2/firmware/lib/eeprom.c @@ -0,0 +1,69 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "i2c.h" +#include "mdelay.h" + +static const int EEPROM_PAGESIZE = 16; + +bool +eeprom_write (int i2c_addr, int eeprom_offset, const void *buf, int len) +{ + unsigned char cmd[2]; + const unsigned char *p = (unsigned char *) buf; + + // The simplest thing that could possibly work: + // all writes are single byte writes. + // + // We could speed this up using the page write feature, + // but we write so infrequently, why bother... + + while (len-- > 0){ + cmd[0] = eeprom_offset++; + cmd[1] = *p++; + bool r = i2c_write (i2c_addr, cmd, sizeof (cmd)); + mdelay (10); // delay 10ms worst case write time + if (!r) + return false; + } + return true; +} + +bool +eeprom_read (int i2c_addr, int eeprom_offset, void *buf, int len) +{ + unsigned char *p = (unsigned char *) buf; + + // We setup a random read by first doing a "zero byte write". + // Writes carry an address. Reads use an implicit address. + + unsigned char cmd[1]; + cmd[0] = eeprom_offset; + if (!i2c_write (i2c_addr, cmd, sizeof (cmd))) + return false; + + while (len > 0){ + // int n = std::min (len, MAX_EP0_PKTSIZE); + int n = len; + if (!i2c_read (i2c_addr, p, n)) + return false; + len -= n; + p += n; + } + return true; +} + diff --git a/usrp2/firmware/lib/eth_mac.c b/usrp2/firmware/lib/eth_mac.c new file mode 100644 index 00000000..f0b3a57b --- /dev/null +++ b/usrp2/firmware/lib/eth_mac.c @@ -0,0 +1,134 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "eth_mac.h" +#include "memory_map.h" +#include "bool.h" +#include "eth_phy.h" // for simulation constants +#include "mdelay.h" + + +#define PHY_ADDR 1 + +void +eth_mac_set_addr(const u2_mac_addr_t *src) +{ + int i; + + // tell mac our source address and enable automatic insertion on Tx. + eth_mac->mac_tx_add_prom_wr = 0; // just in case + for (i = 0; i < 6; i++){ + eth_mac->mac_tx_add_prom_add = i; + eth_mac->mac_tx_add_prom_data = src->addr[i]; + eth_mac->mac_tx_add_prom_wr = 1; + mdelay(1); + eth_mac->mac_tx_add_prom_wr = 0; + mdelay(1); + } + eth_mac->mac_tx_add_en = 1; // overwrite pkt src addr field with this stuff + + // set up receive destination address filter + eth_mac->mac_rx_add_prom_wr = 0; // just in case + for (i = 0; i < 6; i++){ + eth_mac->mac_rx_add_prom_add = i; + eth_mac->mac_rx_add_prom_data = src->addr[i]; + eth_mac->mac_rx_add_prom_wr = 1; + mdelay(1); + eth_mac->mac_rx_add_prom_wr = 0; + mdelay(1); + } + // eth_mac->mac_rx_add_chk_en = 1; // FIXME enable when everything's working +} + + +void +eth_mac_init(const u2_mac_addr_t *src) +{ + eth_mac->miimoder = 25; // divider from CPU clock (50MHz/25 = 2MHz) + + eth_mac_set_addr(src); + + // set rx flow control high and low water marks + // unsigned int lwmark = (2*2048 + 64)/4; // 2 * 2048-byte frames + 1 * 64-byte pause frame + // eth_mac->fc_hwmark = lwmark + 2048/4; // plus a 2048-byte frame + + eth_mac->fc_lwmark = 600; // there are currently 2047 lines in the fifo + eth_mac->fc_hwmark = 1200; + + //eth_mac->tx_pause_en = 0; // pay attn to pause frames sent to us + //eth_mac->pause_quanta_set = 38; // a bit more than 1 max frame 16kb/512 + fudge + //eth_mac->pause_frame_send_en = 0; // enable sending pause frames +} + +int +eth_mac_read_rmon(int addr) +{ + int t; + + eth_mac->rmon_rd_addr = addr; + eth_mac->rmon_rd_apply = 1; + while(eth_mac->rmon_rd_grant == 0) + ; + + t = eth_mac->rmon_rd_dout; + eth_mac->rmon_rd_apply = 0; + return t; +} + +int +eth_mac_miim_read(int addr) +{ + if (hwconfig_simulation_p()){ + switch(addr){ + case PHY_LINK_AN: + return LANSR_MASTER | LANSR_LINK_GOOD | LANSR_SPEED_1000; + default: + return 0; + } + } + + int phy_addr = PHY_ADDR; + eth_mac->miiaddress = ((addr & 0x1f) << 8) | phy_addr; + eth_mac->miicommand = MIIC_RSTAT; + + while((eth_mac->miistatus & MIIS_BUSY) != 0) + ; + + return eth_mac->miirx_data; +} + +void +eth_mac_miim_write(int addr, int value) +{ + int phy_addr = PHY_ADDR; + eth_mac->miiaddress = ((addr & 0x1f) << 8) | phy_addr; + eth_mac->miitx_data = value; + eth_mac->miicommand = MIIC_WCTRLDATA; + + while((eth_mac->miistatus & MIIS_BUSY) != 0) + ; +} + +int +eth_mac_miim_read_status(void) +{ + if (hwconfig_simulation_p()) + return 0; + + return eth_mac->miistatus; +} diff --git a/usrp2/firmware/lib/eth_mac.h b/usrp2/firmware/lib/eth_mac.h new file mode 100644 index 00000000..291994c5 --- /dev/null +++ b/usrp2/firmware/lib/eth_mac.h @@ -0,0 +1,32 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_ETH_MAC_H +#define INCLUDED_ETH_MAC_H + +#include "usrp2_mac_addr.h" + +void eth_mac_init(const u2_mac_addr_t *src); + +void eth_mac_set_addr(const u2_mac_addr_t *src); +int eth_mac_read_rmon(int addr); +int eth_mac_miim_read(int addr); +void eth_mac_miim_write(int addr, int value); +int eth_mac_miim_read_status(void); + +#endif /* INCLUDED_ETH_MAC_H */ diff --git a/usrp2/firmware/lib/eth_mac_regs.h b/usrp2/firmware/lib/eth_mac_regs.h new file mode 100644 index 00000000..bb6d2519 --- /dev/null +++ b/usrp2/firmware/lib/eth_mac_regs.h @@ -0,0 +1,97 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_ETH_MAC_REGS_H +#define INCLUDED_ETH_MAC_REGS_H + +/* + * See opencores.org 10_100_1000 Mbps Tri-mode Ethernet MAC Specification + * + * In reality, these are 16-bit regs, but are assigned + * on 32-bit boundaries. Because we're little endian, + * declaring them "int" works. + */ +typedef struct { + volatile int tx_hwmark; + volatile int tx_lwmark; + + //! if set, send pause frames automatically + volatile int pause_frame_send_en; + + //! quanta value for pause frame in units of 512 bit times. + volatile int pause_quanta_set; + + volatile int ifg_set; + volatile int full_duplex; + volatile int max_retry; + volatile int mac_tx_add_en; + volatile int mac_tx_add_prom_data; + volatile int mac_tx_add_prom_add; + volatile int mac_tx_add_prom_wr; + + //! if set, other end can pause us (i.e., we pay attention to pause frames) + volatile int tx_pause_en; + + // Flow Control high and low water marks + //! when space available (in 32-bit lines) > hwmark, send un-pause frame + volatile int fc_hwmark; + + //! when space avail (in 32-bit lines) < lwmark, send pause frame + volatile int fc_lwmark; + + volatile int mac_rx_add_chk_en; + volatile int mac_rx_add_prom_data; + volatile int mac_rx_add_prom_add; + volatile int mac_rx_add_prom_wr; + volatile int broadcast_filter_en; + volatile int broadcast_bucket_depth; + volatile int broadcast_bucket_interval; + volatile int rx_append_crc; + volatile int rx_hwmark; + volatile int rx_lwmark; + volatile int crc_chk_en; + volatile int rx_ifg_set; + volatile int rx_max_length; + volatile int rx_min_length; + volatile int rmon_rd_addr; // performance counter access + volatile int rmon_rd_apply; + volatile int rmon_rd_grant; // READONLY + volatile int rmon_rd_dout; // READONLY + volatile int dummy; // READONLY + volatile int line_loop_en; + volatile int speed; + volatile int miimoder; + volatile int miicommand; + volatile int miiaddress; + volatile int miitx_data; + volatile int miirx_data; + volatile int miistatus; +} eth_mac_regs_t; + +// miicommand register +#define MIIC_SCANSSTAT (1 << 0) // Scan status +#define MIIC_RSTAT (1 << 1) // Read status +#define MIIC_WCTRLDATA (1 << 2) // Write control data + +// miistatus register +#define MIIS_LINKFAIL (1 << 0) // The link failed +#define MIIS_BUSY (1 << 1) // The MII is busy (operation in progress) +#define MIIS_NVALID (1 << 2) // The data in the status register is invalid + // This it is only valid when the scan status is active. + +#endif /* INCLUDED_ETH_MAC_REGS_H */ diff --git a/usrp2/firmware/lib/eth_phy.h b/usrp2/firmware/lib/eth_phy.h new file mode 100644 index 00000000..6c16f97b --- /dev/null +++ b/usrp2/firmware/lib/eth_phy.h @@ -0,0 +1,219 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Much of this was extracted from the Linux e1000_hw.h file */ + +#ifndef INCLUDED_ETH_PHY_H +#define INCLUDED_ETH_PHY_H + +/* PHY 1000 MII Register/Bit Definitions */ +/* PHY Registers defined by IEEE */ + +#define PHY_CTRL 0x00 /* Control Register */ +#define PHY_STATUS 0x01 /* Status Regiser */ +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ + +/* PHY 1000 MII Register additions in DP83856 */ +/* The part implements 0x00 thru 0x1f; we use these. */ + +#define PHY_LINK_AN 0x11 /* Link and Auto Negotiation Status Reg */ +#define PHY_INT_STATUS 0x14 /* Interupt Status Reg (RO) */ +#define PHY_INT_MASK 0x15 /* Interrupt Mask Reg (RW) */ +#define PHY_INT_CLEAR 0x17 /* Interrupt Clear Reg (RW) */ + + +/* Bit definitions for some of the registers above */ + +/* PHY Control Register (PHY_CTRL) */ +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ +#define MII_CR_POWER_DOWN 0x0800 /* Power down */ +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ + +/* PHY Status Register (PHY_STATUS) */ +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ + +/* Autoneg Advertisement Register (PHY_AUTONEG_ADV) */ +#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ +#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ +#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ +#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ +#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ +#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ +#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ +#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ +#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ +#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Link Partner Ability Register (Base Page) (PHY_LP_ABILITY) */ +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ +#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ +#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ +#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ +#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ +#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ +#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ +#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ +#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ +#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Autoneg Expansion Register (PHY_AUTONEG_EXP) */ +#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ +#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ +#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ +#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ + +/* Next Page TX Register (PHY_NEXT_PAGE_TX) */ +#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ + +/* Link Partner Next Page Register (PHY_LP_NEXT_PAGE) */ +#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ +#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ + +/* 1000BASE-T Control Register (PHY_1000T_CTRL) */ +#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ +#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ +#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ +#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ + /* 0=DTE device */ +#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ + /* 0=Configure PHY as Slave */ +#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ + /* 0=Automatic Master/Slave config */ +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ +#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ +#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ +#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ +#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ + +/* 1000BASE-T Status Register (PHY_1000T_STATUS) */ +#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ +#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ +#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ +#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ +#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ +#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ +#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ +#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 +#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 +#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 +#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 +#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 + +/* Extended Status Register (PHY_EXT_STATUS) */ +#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ +#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ +#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ +#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ + +#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ +#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ + +#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ + /* (0=enable, 1=disable) */ + +/* Link and Auto Negotiation Status Reg (PHY_LINK_AN) [READ-ONLY] */ +#define LANSR_MASTER 0x0001 /* 1=PHY is currently in master mode */ +#define LANSR_FULL_DUPLEX 0x0002 /* 1=PHY is currently full duplex */ +#define LANSR_LINK_GOOD 0x0004 /* 1=a good link is established */ +#define LANSR_SPEED_MASK 0x0018 +#define LANSR_SPEED_10 0x0000 /* 10Mb/s */ +#define LANSR_SPEED_100 0x0008 /* 100Mb/s */ +#define LANSR_SPEED_1000 0x0010 /* 1000Mb/s */ +#define LANSR_SPEED_RSRVD 0x0018 /* reserved */ +#define LANSR_NON_COMP_MODE 0x0020 /* 1=detects only in non-compliant mode */ +#define LANSR_DEEP_LOOPBACK 0x0040 /* 1=the PHY operates in deep loopback mode */ +#define LANSR_SHALLOW_LOOPBACK 0x0080 /* 1=the PHY operates in shallow loopback mode */ +#define LANSR_RSRVD_8 0x0100 /* reserved */ +#define LANSR_FIFO_ERR 0x0200 /* 1=FIFO error occurred */ +#define LANSR_MDIX_XOVER 0x0400 /* 1=PHY's MDI is in cross-over mode */ +#define LANSR_RSRVD_11 0x0800 /* resevered */ +#define LANSR_TP_POLARITY_REV 0xf000 /* Twisted pair polarity status A:D([15:12]) 1=reversed */ + +/* Interrupt status, mask and clear regs (PHY_INT_{STATUS,MASK,CLEAR}) */ +#define PHY_INT_RSRVD_0 0x0001 /* reserved */ +#define PHY_INT_RSRVD_1 0x0002 /* reserved */ +#define PHY_INT_RSRVD_2 0x0004 /* reserved */ +#define PHY_INT_REM_FLT_CNG 0x0008 /* Remote Fault Changed */ +#define PHY_INT_AN_CMPL 0x0010 /* Auto-negotiation completion */ +#define PHY_INT_NXT_PG_RCVD 0x0020 /* Next Page Received */ +#define PHY_INT_JABBER_CNG 0x0040 /* Jabber Changed */ +#define PHY_INT_NO_LINK 0x0080 /* No link after auto-negotiation */ +#define PHY_INT_NO_HCD 0x0100 /* AN couldn't determine highest common denominator */ +#define PHY_INT_MAS_SLA_ERR 0x0200 /* Master / Slave Error: couldn't resolve */ +#define PHY_INT_PRL_DET_FLT 0x0400 /* Parallel detection fault */ +#define PHY_INT_POL_CNG 0x0800 /* Polarity of any channel changed */ +#define PHY_INT_MDIX_CNG 0x1000 /* MDIX changed. A pair swap occurred. */ +#define PHY_INT_DPLX_CNG 0x2000 /* Duplex changed */ +#define PHY_INT_LNK_CNG 0x4000 /* Link changed (asserted when a link is established or broken) */ +#define PHY_INT_SPD_CNG 0x8000 /* Speed changed */ + +#endif /* INCLUDED_ETH_PHY_H */ diff --git a/usrp2/firmware/lib/ethernet.c b/usrp2/firmware/lib/ethernet.c new file mode 100644 index 00000000..0e2f4616 --- /dev/null +++ b/usrp2/firmware/lib/ethernet.c @@ -0,0 +1,281 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "ethernet.h" +#include "memory_map.h" +#include "eth_phy.h" +#include "eth_mac.h" +#include "eth_mac_regs.h" +#include "pic.h" +#include "hal_io.h" +#include "nonstdio.h" +#include "bool.h" +#include "i2c.h" +#include "usrp2_i2c_addr.h" + + +#define VERBOSE 0 + +static ethernet_t ed_state; +static ethernet_link_changed_callback_t ed_callback = 0; + +void +ethernet_register_link_changed_callback(ethernet_link_changed_callback_t new_callback) +{ + ed_callback = new_callback; +} + + +static void +ed_set_mac_speed(int speed) +{ + switch(speed){ + case 10: + eth_mac->speed = 1; + break; + case 100: + eth_mac->speed = 2; + break; + case 1000: + eth_mac->speed = 4; + break; + default: + break; + } +} + +static void +ed_link_up(int speed) +{ + // putstr("ed_link_up: "); puthex16_nl(speed); + + ed_set_mac_speed(speed); + + if (ed_callback) // fire link changed callback + (*ed_callback)(speed); +} + +static void +ed_link_down(void) +{ + // putstr("ed_link_down\n"); + + if (ed_callback) // fire link changed callback + (*ed_callback)(0); +} + + +static void +ed_link_speed_change(int speed) +{ + ed_link_down(); + ed_link_up(speed); +} + +/* + * Read the PHY state register to determine link state and speed + */ +static void +ed_check_phy_state(void) +{ + int lansr = eth_mac_miim_read(PHY_LINK_AN); + eth_link_state_t new_state = LS_UNKNOWN; + int new_speed = S_UNKNOWN; + + if (VERBOSE){ + putstr("LANSR: "); + puthex16_nl(lansr); + } + + if (lansr & LANSR_LINK_GOOD){ // link's up + if (VERBOSE) + puts(" LINK_GOOD"); + + new_state = LS_UP; + switch (lansr & LANSR_SPEED_MASK){ + case LANSR_SPEED_10: + new_speed = 10; + break; + + case LANSR_SPEED_100: + new_speed = 100; + break; + + case LANSR_SPEED_1000: + new_speed = 1000; + break; + + default: + new_speed = S_UNKNOWN; + break; + } + } + else { // link's down + if (VERBOSE) + puts(" NOT LINK_GOOD"); + + new_state = LS_DOWN; + new_speed = S_UNKNOWN; + } + + if (new_state != ed_state.link_state){ + ed_state.link_state = new_state; // remember new state + if (new_state == LS_UP) + ed_link_up(new_speed); + else if (new_state == LS_DOWN) + ed_link_down(); + } + else if (new_state == LS_UP && new_speed != ed_state.link_speed){ + ed_state.link_speed = new_speed; // remember new speed + ed_link_speed_change(new_speed); + } +} + +/* + * This is fired when the ethernet PHY state changes + */ +static void +eth_phy_irq_handler(unsigned irq) +{ + ed_check_phy_state(); + eth_mac_miim_write(PHY_INT_CLEAR, ~0); // clear all ints +} + +void +ethernet_init(void) +{ + eth_mac_init(ethernet_mac_addr()); + + ed_state.link_state = LS_UNKNOWN; + ed_state.link_speed = S_UNKNOWN; + + // initialize MAC registers + eth_mac->tx_hwmark = 0x1e; + eth_mac->tx_lwmark = 0x19; + + eth_mac->crc_chk_en = 1; + eth_mac->rx_max_length = 2048; + + // configure PAUSE frame stuff + eth_mac->tx_pause_en = 1; // pay attn to pause frames sent to us + + eth_mac->pause_quanta_set = 38; // a bit more than 1 max frame 16kb/512 + fudge + eth_mac->pause_frame_send_en = 1; // enable sending pause frames + + + // setup PHY to interrupt on changes + + unsigned mask = + (PHY_INT_AN_CMPL // auto-neg completed + | PHY_INT_NO_LINK // no link after auto-neg + | PHY_INT_NO_HCD // no highest common denominator + | PHY_INT_MAS_SLA_ERR // couldn't resolve master/slave + | PHY_INT_PRL_DET_FLT // parallel detection fault + | PHY_INT_LNK_CNG // link established or broken + | PHY_INT_SPD_CNG // speed changed + ); + + eth_mac_miim_write(PHY_INT_CLEAR, ~0); // clear all pending interrupts + eth_mac_miim_write(PHY_INT_MASK, mask); // enable the ones we want + + pic_register_handler(IRQ_PHY, eth_phy_irq_handler); + + // Advertise that we handle PAUSE frames and asymmetric pause direction. + int t = eth_mac_miim_read(PHY_AUTONEG_ADV); + eth_mac_miim_write(PHY_AUTONEG_ADV, t | NWAY_AR_PAUSE | NWAY_AR_ASM_DIR); + + // Restart autonegotation. + // We want to ensure that we're advertising our PAUSE capabilities. + t = eth_mac_miim_read(PHY_CTRL); + eth_mac_miim_write(PHY_CTRL, t | MII_CR_RESTART_AUTO_NEG); +} + +static bool +unprogrammed(const u2_mac_addr_t *t) +{ + int i; + bool all_zeros = true; + bool all_ones = true; + for (i = 0; i < 6; i++){ + all_zeros &= t->addr[i] == 0x00; + all_ones &= t->addr[i] == 0xff; + } + return all_ones | all_zeros; +} + +static int8_t src_addr_initialized = false; +static u2_mac_addr_t src_addr = {{ + 0x00, 0x50, 0xC2, 0x85, 0x3f, 0xff + }}; + +const u2_mac_addr_t * +ethernet_mac_addr(void) +{ + if (!src_addr_initialized){ // fetch from eeprom + src_addr_initialized = true; + + // if we're simulating, don't read the EEPROM model, it's REALLY slow + if (hwconfig_simulation_p()) + return &src_addr; + + u2_mac_addr_t tmp; + bool ok = eeprom_read(I2C_ADDR_MBOARD, MBOARD_MAC_ADDR, &tmp.addr[0], 6); + if (!ok || unprogrammed(&tmp)){ + // use the default + } + else + src_addr = tmp; + } + + return &src_addr; +} + +bool +ethernet_set_mac_addr(const u2_mac_addr_t *t) +{ + bool ok = eeprom_write(I2C_ADDR_MBOARD, MBOARD_MAC_ADDR, &t->addr[0], 6); + if (ok){ + src_addr = *t; + src_addr_initialized = true; + eth_mac_set_addr(t); + } + + return ok; +} + +int +ethernet_check_errors(void) +{ + // these registers are reset when read + + int r = 0; + if (eth_mac_read_rmon(0x05) != 0) + r |= RME_RX_CRC; + if (eth_mac_read_rmon(0x06) != 0) + r |= RME_RX_FIFO_FULL; + if (eth_mac_read_rmon(0x07) != 0) + r |= RME_RX_2SHORT_2LONG; + + if (eth_mac_read_rmon(0x25) != 0) + r |= RME_TX_JAM_DROP; + if (eth_mac_read_rmon(0x26) != 0) + r |= RME_TX_FIFO_UNDER; + if (eth_mac_read_rmon(0x27) != 0) + r |= RME_TX_FIFO_OVER; + + return r; +} diff --git a/usrp2/firmware/lib/ethernet.h b/usrp2/firmware/lib/ethernet.h new file mode 100644 index 00000000..4e549046 --- /dev/null +++ b/usrp2/firmware/lib/ethernet.h @@ -0,0 +1,75 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_ETHERNET_H +#define INCLUDED_ETHERNET_H + +#include "usrp2_mac_addr.h" +#include "bool.h" + +typedef void (*ethernet_link_changed_callback_t)(int speed); + + +/*! + * \brief one time call to initialize ethernet + */ +void ethernet_init(void); + +/*! + * \brief Specify the function to call on link state changes. + * + * When the link comes up, speed is the link speed in Mbit/s. + * When the link goes down, speed is 0. + */ +void ethernet_register_link_changed_callback(ethernet_link_changed_callback_t cb); + +/*! + * \returns ethernet MAC address + */ +const u2_mac_addr_t *ethernet_mac_addr(void); + +/*! + * \brief write mac address to eeprom and begin using it + */ +bool ethernet_set_mac_addr(const u2_mac_addr_t *t); + + +/* + * \brief read RMON regs and return error mask + */ +int ethernet_check_errors(void); + +#define RME_RX_CRC 0x0001 +#define RME_RX_FIFO_FULL 0x0002 +#define RME_RX_2SHORT_2LONG 0x0004 + +#define RME_TX_JAM_DROP 0x0010 +#define RME_TX_FIFO_UNDER 0x0020 +#define RME_TX_FIFO_OVER 0x0040 + + +typedef enum { LS_UNKNOWN, LS_DOWN, LS_UP } eth_link_state_t; + +#define S_UNKNOWN (-1) // unknown link speed + +typedef struct { + eth_link_state_t link_state; + int link_speed; // in Mb/s +} ethernet_t; + +#endif /* INCLUDED_ETHERNET_H */ diff --git a/usrp2/firmware/lib/hal_io.c b/usrp2/firmware/lib/hal_io.c new file mode 100644 index 00000000..54190682 --- /dev/null +++ b/usrp2/firmware/lib/hal_io.c @@ -0,0 +1,312 @@ +/* -*- c -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +// conditionalized on HAL_IO_USES_DBOARD_PINS && HAL_IO_USES_UART + +#include "hal_io.h" +#include "memory_map.h" +#include "hal_uart.h" +#include "bool.h" +#include +#include +//#include + +/* + * ======================================================================== + * GPIOS + * ======================================================================== + */ +void +hal_gpio_set_ddr(int bank, int value, int mask) +{ + bank &= 0x1; + + if (bank == GPIO_TX_BANK){ // tx in top half + value <<= 16; + mask <<= 16; + } + else { + value &= 0xffff; + mask &= 0xffff; + } + + int ei = hal_disable_ints(); + gpio_base->ddr = (gpio_base->ddr & ~mask) | (value & mask); + hal_restore_ints(ei); +} + +static bool +code_to_int(char code, int *val) +{ + switch(code){ + case 's': *val = GPIO_SEL_SW; return true; + case 'a': *val = GPIO_SEL_ATR; return true; + case '0': *val = GPIO_SEL_DEBUG_0; return true; + case '1': *val = GPIO_SEL_DEBUG_1; return true; + case '.': + default: + return false; + } +} + +void +hal_gpio_set_sel(int bank, int bitno, char code) +{ + bank &= 0x1; + int t; + + if (!code_to_int(code, &t)) + return; + + int val = t << (2 * bitno); + int mask = 0x3 << (2 * bitno); + + volatile uint32_t *sel = bank == GPIO_TX_BANK ? &gpio_base->tx_sel : &gpio_base->rx_sel; + int ei = hal_disable_ints(); + int v = (*sel & ~mask) | (val & mask); + *sel = v; + hal_restore_ints(ei); + + if (0) + printf("hal_gpio_set_sel(bank=%d, bitno=%d, code=%c) *sel = 0x%x\n", + bank, bitno, code, v); +} + +void +hal_gpio_set_sels(int bank, char *codes) +{ + //assert(strlen(codes) == 16); + + int val = 0; + int mask = 0; + int i; + + for (i = 15; i >= 0; i--){ + val <<= 2; + mask <<= 2; + int t; + if (code_to_int(codes[i], &t)){ + val |= t; + mask |= 0x3; + } + } + + volatile uint32_t *sel = bank == GPIO_TX_BANK ? &gpio_base->tx_sel : &gpio_base->rx_sel; + int ei = hal_disable_ints(); + *sel = (*sel & ~mask) | (val & mask); + hal_restore_ints(ei); +} + + +/*! + * \brief write \p value to gpio pins specified by \p mask. + */ +void +hal_gpio_write(int bank, int value, int mask) +{ + static uint32_t _gpio_io_shadow; + + bank &= 0x1; + + if (bank == GPIO_TX_BANK){ // tx in top half + value <<= 16; + mask <<= 16; + } + else { + value &= 0xffff; + mask &= 0xffff; + } + + //int ei = hal_disable_ints(); + _gpio_io_shadow = (_gpio_io_shadow & ~mask) | (value & mask); + gpio_base->io = _gpio_io_shadow; + //hal_restore_ints(ei); +} + + +/*! + * \brief read GPIO bits + */ +int +hal_gpio_read(int bank) +{ + bank &= 0x1; + int r = gpio_base->io; + if (bank == GPIO_TX_BANK) + r >>= 16; + + return r & 0xffff; +} + +/* + * ======================================================================== + * leds + * ======================================================================== + */ + +static unsigned long leds_shadow = 0; + +void +hal_set_leds(int value, int mask) +{ + int ei = hal_disable_ints(); + leds_shadow = (leds_shadow & ~mask) | (value & mask); + output_regs->leds = leds_shadow; + hal_restore_ints(ei); +} + +void +hal_toggle_leds(int mask) +{ + int ei = hal_disable_ints(); + leds_shadow ^= mask; + output_regs->leds = leds_shadow; + hal_restore_ints(ei); +} + + +// ================================================================ +// primitives +// ================================================================ + +#if defined(HAL_IO_USES_DBOARD_PINS) +// +// Does i/o using high 9-bits of rx daughterboard pins. +// +// 1 1 1 1 1 1 +// 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +// | char |W| | +// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +// +// +// Asserts W when writing char +// + +#define W 0x0080 + +void +hal_io_init(void) +{ + // make high 9 bits of tx daughterboard outputs + hal_gpio_set_rx_mode(15, 7, GPIOM_OUTPUT); + + // and set them to zero + hal_gpio_set_rx(0x0000, 0xff80); +} + +void +hal_finish(void) +{ + volatile unsigned long *p = (unsigned long *) 0xC2F0; + *p = 0; +} + +// %c +inline int +putchar(int ch) +{ + hal_gpio_set_rx((s << 8) | W, 0xff80); + hal_gpio_set_rx(0, 0xff80); + return ch; +} + +#elif defined(HAL_IO_USES_UART) + +void +hal_io_init(void) +{ + hal_uart_init(); +} + +void +hal_finish(void) +{ +} + +// %c +inline int +putchar(int ch) +{ + hal_uart_putc(ch); + return ch; +} + +int +getchar(void) +{ + return hal_uart_getc(); +} + +#else // nop all i/o + +void +hal_io_init(void) +{ +} + +void +hal_finish(void) +{ +} + +// %c +inline int +putchar(int ch) +{ + return ch; +} + +int +getchar(void) +{ + return EOF; +} + +#endif + +// ================================================================ +// (slightly) higher level functions +// +// These are here so we can inline the calls to putchar. +// The rest of the stuff was moved to nonstdio.c +// ================================================================ + +// \n +inline void +newline(void) +{ + putchar('\n'); +} + +int +putstr(const char *s) +{ + while (*s) + putchar(*s++); + + return 0; +} + +int +puts(const char *s) +{ + putstr(s); + putchar('\n'); + return 0; +} diff --git a/usrp2/firmware/lib/hal_io.h b/usrp2/firmware/lib/hal_io.h new file mode 100644 index 00000000..5ffebf57 --- /dev/null +++ b/usrp2/firmware/lib/hal_io.h @@ -0,0 +1,174 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_HAL_IO_H +#define INCLUDED_HAL_IO_H + +#include "memory_map.h" + +void hal_io_init(void); +void hal_finish(); + + +/* + * ------------------------------------------------------------------------ + * The GPIO pins are organized into two banks of 16-bits. + * Bank 0 goes to the Tx daughterboard, Bank 1 goes to the Rx daughterboard. + * + * Each pin may be configured as an input or an output from the FPGA. + * For output pins, there are four signals which may be routed to the + * pin. The four signals are the value written by s/w, the output of + * the ATR controller, or two different sources of debug info from the + * FPGA fabric. + * ------------------------------------------------------------------------ + */ + +#define GPIO_TX_BANK 0 // pins that connect to the Tx daughterboard +#define GPIO_RX_BANK 1 // pins that connect to the Rx daughterboard + + +/*! + * \brief Set the data direction for GPIO pins + * + * If the bit is set, it's an output from the FPGA. + * \param value is a 16-bit bitmask of values + * \param mask is a 16-bit bitmask of which bits to effect. + */ +void hal_gpio_set_ddr(int bank, int value, int mask); + +/*! + * \brief Select the source of the signal for an output pin. + * + * \param code is is one of 's', 'a', '0', '1' + * where 's' selects software output, 'a' selects ATR output, '0' selects + * debug 0, '1' selects debug 1. + */ +void hal_gpio_set_sel(int bank, int bitno, char code); + +/*! + * \brief Select the source of the signal for the output pins. + * + * \param codes is is a string of 16 characters composed of '.', 's', + * 'a', '0', or '1' where '.' means "don't change", 's' selects + * software output, 'a' selects ATR output, '0' selects debug 0, '1' + * selects debug 1. + */ +void hal_gpio_set_sels(int bank, char *codes); + + +/*! + * \brief write \p value to gpio pins specified by \p mask. + */ +void hal_gpio_write(int bank, int value, int mask); + +/*! + * \brief read GPIO bits + */ +int hal_gpio_read(int bank); + + +/* + * ------------------------------------------------------------------------ + * control the leds + * + * Low 4-bits are the general purpose leds on the board + * The next bit is the led on the ethernet connector + * ------------------------------------------------------------------------ + */ + +#define LED_0 0x0001 +#define LED_1 0x0002 +#define LED_3 0x0004 +#define LED_4 0x0008 +#define LED_ETH_CONN 0x0010 + +void hal_set_leds(int value, int mask); +void hal_toggle_leds(int mask); + +/* + * ------------------------------------------------------------------------ + * simple timeouts + * ------------------------------------------------------------------------ + */ + + + +static inline void +hal_set_timeout(int delta_ticks) +{ + int t = timer_regs->time + delta_ticks; + if (t == 0) // kills timer + t = 1; + timer_regs->time = t; +} + +/* + * ------------------------------------------------------------------------ + * interrupt enable/disable + * ------------------------------------------------------------------------ + */ + +/*! + * \brief Disable interrupts and return previous interrupt enable state. + * [Microblaze specific] + */ +static inline int +hal_disable_ints(void) +{ + int result, t0; + + asm volatile("mfs %0, rmsr \n\ + andni %1, %0, 0x2 \n\ + mts rmsr, %1" + : "=r" (result), "=r" (t0)); + return result; +} + +/*! + * \brief Enable interrupts and return previous interrupt enable state. + * [Microblaze specific] + */ +static inline int +hal_enable_ints(void) +{ + int result, t0; + + asm volatile("mfs %0, rmsr \n\ + ori %1, %0, 0x2 \n\ + mts rmsr, %1" + : "=r" (result), "=r" (t0)); + return result; +} + +/*! + * \brief Set interrupt enable state to \p prev_state. + * [Microblaze specific] + */ +static inline void +hal_restore_ints(int prev_state) +{ + int t0, t1; + asm volatile("andi %0, %2, 0x2 \n\ + mfs %1, rmsr \n\ + andni %1, %1, 0x2 \n\ + or %1, %1, %0 \n\ + mts rmsr, %1" + : "=r" (t0), "=r"(t1) : "r" (prev_state)); +} + +#endif /* INCLUDED_HAL_IO_H */ diff --git a/usrp2/firmware/lib/hal_uart.c b/usrp2/firmware/lib/hal_uart.c new file mode 100644 index 00000000..f1d46fe8 --- /dev/null +++ b/usrp2/firmware/lib/hal_uart.c @@ -0,0 +1,67 @@ +/* -*- c -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "hal_uart.h" +#include "hal_io.h" +#include "memory_map.h" + +// First pass, no interrupts + +// Replaced with divisors.py which generates best divisor +//#define CALC_DIVISOR(rate) (WISHBONE_CLK_RATE / ((rate) * 16)) + +#define NSPEEDS 6 +#define MAX_WB_DIV 4 + +static const uint16_t +divisor_table[MAX_WB_DIV+1][NSPEEDS] = { + { 2, 2, 2, 2, 2, 2}, // 0: can't happen + { 651, 326, 163, 109, 54, 27 }, // 1: 100 MHz + { 326, 163, 81, 54, 27, 14 }, // 2: 50 MHz + { 217, 109, 54, 36, 18, 9 }, // 3: 33.3333 MHz + { 163, 81, 41, 27, 14, 7 }, // 4: 25 MHz +}; + +#define u uart_regs + +void +hal_uart_init(void) +{ + u->clkdiv = 217; // 230400 bps +} + +void +hal_uart_putc(int ch) +{ + if (ch == '\n') // FIXME for now map \n -> \r\n + hal_uart_putc('\r'); + + while (u->txlevel == 0) // wait for fifo to have space + ; + + u->txchar = ch; +} + +int +hal_uart_getc(void) +{ + while ((u->rxlevel) == 0) // wait for data to be ready + ; + + return u->rxchar; +} diff --git a/usrp2/firmware/lib/hal_uart.h b/usrp2/firmware/lib/hal_uart.h new file mode 100644 index 00000000..41e78894 --- /dev/null +++ b/usrp2/firmware/lib/hal_uart.h @@ -0,0 +1,63 @@ +/* -*- c -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_HAL_UART_H +#define INCLUDED_HAL_UART_H + + +/*! + * \brief one-time call to init + */ +void hal_uart_init(void); + +typedef enum { + US_9600, + US_19200, + US_38400, + US_57600, + US_115200, + US_230400, +} hal_uart_speed_t; + +typedef struct { + hal_uart_speed_t speed; +} hal_uart_config_t; + +/*! + * \brief Set uart parameters + * Default is 115,200 bps, 8N1. + */ +void hal_uart_set_config(const hal_uart_config_t *c); + +/*! + * \brief Get uart configuation. + */ +void hal_uart_get_config(hal_uart_config_t *c); + +/*! + * \brief Enqueue \p ch for output over serial port + */ +void hal_uart_putc(int ch); + +/* + * \brief Blocking read of next char from serial port + */ +int hal_uart_getc(void); + + +#endif /* INCLUDED_HAL_UART_H */ diff --git a/usrp2/firmware/lib/i2c.c b/usrp2/firmware/lib/i2c.c new file mode 100644 index 00000000..3f738733 --- /dev/null +++ b/usrp2/firmware/lib/i2c.c @@ -0,0 +1,127 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "i2c.h" +#include "memory_map.h" +#include "stdint.h" + +#define MAX_WB_DIV 4 // maximum wishbone divisor (from 100 MHz MASTER_CLK) + +// prescaler divisor values for 100 kHz I2C [uses 5 * SCLK internally] + +#define PRESCALER(wb_div) (((MASTER_CLK_RATE/(wb_div)) / (5 * 100000)) - 1) + +static uint16_t prescaler_values[MAX_WB_DIV+1] = { + 0xffff, // 0: can't happen + PRESCALER(1), // 1: 100 MHz + PRESCALER(2), // 2: 50 MHz + PRESCALER(3), // 3: 33.333 MHz + PRESCALER(4), // 4: 25 MHz +}; + +void +i2c_init(void) +{ + i2c_regs->ctrl = 0; // disable core + + // setup prescaler depending on wishbone divisor + int wb_div = hwconfig_wishbone_divisor(); + if (wb_div > MAX_WB_DIV) + wb_div = MAX_WB_DIV; + + i2c_regs->prescaler_lo = prescaler_values[wb_div] & 0xff; + i2c_regs->prescaler_hi = (prescaler_values[wb_div] >> 8) & 0xff; + + i2c_regs->ctrl = I2C_CTRL_EN; // enable core + + // FIXME interrupt driven? +} + +static inline void +wait_for_xfer(void) +{ + while (i2c_regs->cmd_status & I2C_ST_TIP) // wait for xfer to complete + ; +} + +static inline bool +wait_chk_ack(void) +{ + wait_for_xfer(); + + if ((i2c_regs->cmd_status & I2C_ST_RXACK) != 0){ // target NAK'd + return false; + } + return true; +} + +bool +i2c_read (unsigned char i2c_addr, unsigned char *buf, unsigned int len) +{ + if (len == 0) // reading zero bytes always works + return true; + + while (i2c_regs->cmd_status & I2C_ST_BUSY) + ; + + i2c_regs->data = (i2c_addr << 1) | 1; // 7 bit address and read bit (1) + // generate START and write addr + i2c_regs->cmd_status = I2C_CMD_WR | I2C_CMD_START; + if (!wait_chk_ack()) + goto fail; + + for (; len > 0; buf++, len--){ + i2c_regs->cmd_status = I2C_CMD_RD | (len == 1 ? (I2C_CMD_NACK | I2C_CMD_STOP) : 0); + wait_for_xfer(); + *buf = i2c_regs->data; + } + return true; + + fail: + i2c_regs->cmd_status = I2C_CMD_STOP; // generate STOP + return false; +} + + +bool +i2c_write(unsigned char i2c_addr, const unsigned char *buf, unsigned int len) +{ + while (i2c_regs->cmd_status & I2C_ST_BUSY) + ; + + i2c_regs->data = (i2c_addr << 1) | 0; // 7 bit address and write bit (0) + + // generate START and write addr (and maybe STOP) + i2c_regs->cmd_status = I2C_CMD_WR | I2C_CMD_START | (len == 0 ? I2C_CMD_STOP : 0); + if (!wait_chk_ack()) + goto fail; + + for (; len > 0; buf++, len--){ + i2c_regs->data = *buf; + i2c_regs->cmd_status = I2C_CMD_WR | (len == 1 ? I2C_CMD_STOP : 0); + if (!wait_chk_ack()) + goto fail; + } + return true; + + fail: + i2c_regs->cmd_status = I2C_CMD_STOP; // generate STOP + return false; +} + + diff --git a/usrp2/firmware/lib/i2c.h b/usrp2/firmware/lib/i2c.h new file mode 100644 index 00000000..ad1e4159 --- /dev/null +++ b/usrp2/firmware/lib/i2c.h @@ -0,0 +1,39 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_I2C_H +#define INCLUDED_I2C_H + +#include "bool.h" + +void i2c_init(void); +bool i2c_read (unsigned char i2c_addr, unsigned char *buf, unsigned int len); +bool i2c_write(unsigned char i2c_addr, const unsigned char *buf, unsigned int len); + + +// Write 24LC024 / 24LC025 EEPROM on motherboard or daughterboard. +// Which EEPROM is determined by i2c_addr. See i2c_addr.h + +bool eeprom_write (int i2c_addr, int eeprom_offset, const void *buf, int len); + +// Read 24LC024 / 24LC025 EEPROM on motherboard or daughterboard. +// Which EEPROM is determined by i2c_addr. See i2c_addr.h + +bool eeprom_read (int i2c_addr, int eeprom_offset, void *buf, int len); + +#endif /* INCLUDED_I2C_H */ diff --git a/usrp2/firmware/lib/lsadc.c b/usrp2/firmware/lib/lsadc.c new file mode 100644 index 00000000..7983552e --- /dev/null +++ b/usrp2/firmware/lib/lsadc.c @@ -0,0 +1,73 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "lsadc.h" +#include "spi.h" +#include "memory_map.h" + + +// AD9712 or AD7922 1 MS/s, 10-/12-bit ADCs + +//#define SPI_SS_DEBUG SPI_SS_RX_DB +#define SPI_SS_DEBUG 0 + + +void +lsadc_init(void) +{ + // nop +} + +/* + * The ADC's are pipelined. That is, you have to tell them + * which of the two inputs you want one cycle ahead of time. + * We could optimize and keep track of which one we used last + * time, but for simplicity we'll always tell it which + * one we want. This takes 2 16-bit xfers, one to set the + * input and one to read the one we want. + */ + +int +_lsadc_read(int which_adc, int slave_select) +{ + uint32_t r; + int channel = which_adc & 0x1; + + // Set CHN and STY equal to channel number. We don't want "daisy chain mode" + uint16_t cmd = (channel << 13) | (channel << 12); + + spi_transact(SPI_TXONLY, slave_select | SPI_SS_DEBUG, + cmd, 16, SPIF_PUSH_RISE | SPIF_LATCH_RISE); + + r = spi_transact(SPI_TXRX, slave_select | SPI_SS_DEBUG, + cmd, 16, SPIF_PUSH_RISE | SPIF_LATCH_RISE); + + return r & 0x0fff; +} + +int +lsadc_read_rx(int which_adc) +{ + return _lsadc_read(which_adc, SPI_SS_RX_ADC); +} + +int +lsadc_read_tx(int which_adc) +{ + return _lsadc_read(which_adc, SPI_SS_TX_ADC); +} diff --git a/usrp2/firmware/lib/lsadc.h b/usrp2/firmware/lib/lsadc.h new file mode 100644 index 00000000..319f34d9 --- /dev/null +++ b/usrp2/firmware/lib/lsadc.h @@ -0,0 +1,45 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_LSADC_H +#define INCLUDED_LSADC_H + +#include "memory_map.h" + +/*! + * \brief One time call to initialize low-speed ADCs. + */ +void lsadc_init(void); + +/*! + * \brief Read one of the low-speed Rx daughterboard ADCs. + * \param which_adc in [0, 1] + * + * \returns 12-bit value in [0,4095] + */ +int lsadc_read_rx(int which_adc); + +/*! + * \brief Read one of the low-speed Tx daughterboard ADCs. + * \param which_adc in [0, 1] + * + * \returns 12-bit value in [0,4095] + */ +int lsadc_read_tx(int which_adc); + + +#endif /* INCLUDED_LSADC_H */ diff --git a/usrp2/firmware/lib/lsdac.c b/usrp2/firmware/lib/lsdac.c new file mode 100644 index 00000000..6bc2e5cb --- /dev/null +++ b/usrp2/firmware/lib/lsdac.c @@ -0,0 +1,68 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "lsdac.h" +#include "spi.h" +#include "memory_map.h" + +// AD5624, AD5623 + +#define CMD(x) ((x) << 19) +#define CMD_WR_INPUT_N CMD(0) // write input N +#define CMD_UP_DAC_N CMD(1) // update DAC N from input reg +#define CMD_WR_INPUT_N_LDAC CMD(2) // write input N, update all +#define CMD_WR_UP_DAC_N CMD(3) // write and update N +#define CMD_WR_PWR_CONFIG CMD(4) // write power up/down config reg +#define CMD_SW_RESET CMD(5) // force s/w reset +#define CMD_WR_LDAC_CFG CMD(6) // write LDAC config reg +#define CMD_WR_INT_REF_CFG CMD(7) // write internal ref cfg reg (AD5623R only) + + +//#define SPI_SS_DEBUG SPI_SS_TX_DB +#define SPI_SS_DEBUG 0 + +inline static void +_write_rx(uint32_t v) +{ + spi_transact(SPI_TXONLY, SPI_SS_RX_DAC | SPI_SS_DEBUG, v, 24, SPIF_PUSH_RISE); +} + +inline static void +_write_tx(uint32_t v) +{ + spi_transact(SPI_TXONLY, SPI_SS_TX_DAC | SPI_SS_DEBUG, v, 24, SPIF_PUSH_RISE); +} + +void +lsdac_init(void) +{ + _write_tx(CMD_SW_RESET | 0x1); // power-on reset + _write_rx(CMD_SW_RESET | 0x1); // power-on reset +} + +void +lsdac_write_rx(int which_dac, int value) +{ + _write_rx(CMD_WR_UP_DAC_N | ((which_dac & 0x7) << 16) | ((value << 4) & 0xffff)); +} + +void +lsdac_write_tx(int which_dac, int value) +{ + _write_tx(CMD_WR_UP_DAC_N | ((which_dac & 0x7) << 16) | ((value << 4) & 0xffff)); +} diff --git a/usrp2/firmware/lib/lsdac.h b/usrp2/firmware/lib/lsdac.h new file mode 100644 index 00000000..9cad917e --- /dev/null +++ b/usrp2/firmware/lib/lsdac.h @@ -0,0 +1,47 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_LSDAC_H +#define INCLUDED_LSDAC_H + +#include "memory_map.h" + +/*! + * \brief One time call to initialize low-speed DACs. + */ +void lsdac_init(void); + +/*! + * \brief Write one of the low-speed Rx daughterboard DACs. + * \param which_dac in [0, 3] + * \param unsigned 12-bit value in [0, 4095] + * + * value maps linearly to output voltage from 0 to 3.3V + */ +void lsdac_write_rx(int which_dac, int value); + +/*! + * \brief Write one of the low-speed Tx daughterboard DACs. + * \param which_dac in [0, 3] + * \param unsigned 12-bit value in [0, 4095] + * + * value maps linearly to output voltage from 0 to 3.3V + */ +void lsdac_write_tx(int which_dac, int value); + + +#endif /* INCLUDED_LSDAC_H */ diff --git a/usrp2/firmware/lib/mdelay.c b/usrp2/firmware/lib/mdelay.c new file mode 100644 index 00000000..c8c119b1 --- /dev/null +++ b/usrp2/firmware/lib/mdelay.c @@ -0,0 +1,73 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "mdelay.h" +#include "memory_map.h" + +// Delay about one millisecond. +// +// Need 33,333 cycles at 33 MHz. +// Each time around the loop is 10 cycles +// + +#define LOOPCNT(wb_div) (MASTER_CLK_RATE/(wb_div) / 10000) + +inline static void +delay_1ms(int loop_count) +{ + int i; + for (i = 0; i < loop_count; i++){ + asm volatile ("or r0, r0, r0\n\ + or r0, r0, r0\n\ + or r0, r0, r0\n\ + or r0, r0, r0\n\ + or r0, r0, r0\n\ + or r0, r0, r0\n\ + or r0, r0, r0\n"); + } +} + +// delay about ms milliseconds +void +mdelay(int ms) +{ + static int loop_count = -1; + + if (hwconfig_simulation_p()) + return; + + if (loop_count < 0){ + // set correct loop_count + static unsigned short lc[8] = { + 0, + LOOPCNT(1), + LOOPCNT(2), + LOOPCNT(3), + LOOPCNT(4), + LOOPCNT(5), + LOOPCNT(6), + LOOPCNT(7) + }; + + loop_count = lc[hwconfig_wishbone_divisor() & 0x7]; + } + + int i; + for (i = 0; i < ms; i++) + delay_1ms(loop_count); +} diff --git a/usrp2/firmware/lib/mdelay.h b/usrp2/firmware/lib/mdelay.h new file mode 100644 index 00000000..226bbb3f --- /dev/null +++ b/usrp2/firmware/lib/mdelay.h @@ -0,0 +1,29 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_MDELAY_H +#define INCLUDED_MDELAY_H + +/*! + * \brief Delay about ms milliseconds + * + * If simulating, _very_ short delay + */ +void mdelay(int ms); + +#endif /* INCLUDED_MDELAY_H */ diff --git a/usrp2/firmware/lib/memcpy_wa.c b/usrp2/firmware/lib/memcpy_wa.c new file mode 100644 index 00000000..ef20efaa --- /dev/null +++ b/usrp2/firmware/lib/memcpy_wa.c @@ -0,0 +1,42 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "memcpy_wa.h" +#include +#include + +/* + * For copying to/from non-byte-adressable memory, such as + * the buffers. dst, src, and nbytes must all satisfy (x % 4 == 0) + */ +void +memcpy_wa(void *dst, const void *src, size_t nbytes) +{ + if (((intptr_t) dst & 0x3) + || ((intptr_t) src & 0x3) + || (nbytes & 0x3)) + exit(1); /* die! */ + + int *dp = (int *) dst; + int *sp = (int *) src; + unsigned nw = nbytes/4; + + unsigned i; + for (i = 0; i < nw; i++) + dp[i] = sp[i]; +} diff --git a/usrp2/firmware/lib/memcpy_wa.h b/usrp2/firmware/lib/memcpy_wa.h new file mode 100644 index 00000000..072fc148 --- /dev/null +++ b/usrp2/firmware/lib/memcpy_wa.h @@ -0,0 +1,32 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_MEMCPY_WA_H +#define INCLUDED_MEMCPY_WA_H + +#include + +/* + * For copying to/from non-byte-adressable memory, such as + * the buffers. dst, src, and nbytes must all satisfy (x % 4 == 0) + */ +void memcpy_wa(void *dst, const void *src, size_t nbytes); + +#endif /* INCLUDED_MEMCPY_WA_H */ + + diff --git a/usrp2/firmware/lib/memory_map.h b/usrp2/firmware/lib/memory_map.h new file mode 100644 index 00000000..7dce59d0 --- /dev/null +++ b/usrp2/firmware/lib/memory_map.h @@ -0,0 +1,583 @@ +/* -*- c -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Overall Memory Map + * 0000-7FFF 32K RAM space (16K on 1500, 24K on 2000, 32K on DSP) + * 8000-BFFF 16K Buffer Pool + * C000-FFFF 16K Peripherals + */ + + +#ifndef INCLUDED_MEMORY_MAP_H +#define INCLUDED_MEMORY_MAP_H + +#include + + +#define MASTER_CLK_RATE 100000000 // 100 MHz + + +//////////////////////////////////////////////////////////////// +// +// Memory map for embedded wishbone bus +// +//////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////// +// Main RAM, Slave 0 + +#define RAM_BASE 0x0000 + +//////////////////////////////////////////////////////////////// +// Buffer Pool RAM, Slave 1 +// +// The buffers themselves are located in Slave 1, Buffer Pool RAM. +// The status registers are in Slave 5, Buffer Pool Status. +// The control register is in Slave 7, Settings Bus. + +#define BUFFER_POOL_RAM_BASE 0x8000 + +#define NBUFFERS 8 +#define BP_NLINES 0x0200 // number of 32-bit lines in a buffer +#define BP_LAST_LINE (BP_NLINES - 1) // last line in a buffer + +#define buffer_pool_ram \ + ((uint32_t *) BUFFER_POOL_RAM_BASE) + +#define buffer_ram(n) (&buffer_pool_ram[(n) * BP_NLINES]) + + +///////////////////////////////////////////////////// +// SPI Core, Slave 2. See core docs for more info +#define SPI_BASE 0xC000 // Base address (16-bit) + +typedef struct { + volatile uint32_t txrx0; + volatile uint32_t txrx1; + volatile uint32_t txrx2; + volatile uint32_t txrx3; + volatile uint32_t ctrl; + volatile uint32_t div; + volatile uint32_t ss; +} spi_regs_t; + +#define spi_regs ((spi_regs_t *) SPI_BASE) + + +// Masks for controlling different peripherals +#define SPI_SS_AD9510 1 +#define SPI_SS_AD9777 2 +#define SPI_SS_RX_DAC 4 +#define SPI_SS_RX_ADC 8 +#define SPI_SS_RX_DB 16 +#define SPI_SS_TX_DAC 32 +#define SPI_SS_TX_ADC 64 +#define SPI_SS_TX_DB 128 + +// Masks for different parts of CTRL reg +#define SPI_CTRL_ASS (1<<13) +#define SPI_CTRL_IE (1<<12) +#define SPI_CTRL_LSB (1<<11) +#define SPI_CTRL_TXNEG (1<<10) +#define SPI_CTRL_RXNEG (1<< 9) +#define SPI_CTRL_GO_BSY (1<< 8) +#define SPI_CTRL_CHAR_LEN_MASK 0x7F + +//////////////////////////////////////////////// +// I2C, Slave 3 +// See Wishbone I2C-Master Core Specification. + +#define I2C_BASE 0xC400 + +typedef struct { + volatile uint32_t prescaler_lo; // r/w + volatile uint32_t prescaler_hi; // r/w + volatile uint32_t ctrl; // r/w + volatile uint32_t data; // wr = transmit reg; rd = receive reg + volatile uint32_t cmd_status; // wr = command reg; rd = status reg +} i2c_regs_t; + +#define i2c_regs ((i2c_regs_t *) I2C_BASE) + +#define I2C_CTRL_EN (1 << 7) // core enable +#define I2C_CTRL_IE (1 << 6) // interrupt enable + +// +// STA, STO, RD, WR, and IACK bits are cleared automatically +// +#define I2C_CMD_START (1 << 7) // generate (repeated) start condition +#define I2C_CMD_STOP (1 << 6) // generate stop condition +#define I2C_CMD_RD (1 << 5) // read from slave +#define I2C_CMD_WR (1 << 4) // write to slave +#define I2C_CMD_NACK (1 << 3) // when a rcvr, send ACK (ACK=0) or NACK (ACK=1) +#define I2C_CMD_RSVD_2 (1 << 2) // reserved +#define I2C_CMD_RSVD_1 (1 << 1) // reserved +#define I2C_CMD_IACK (1 << 0) // set to clear pending interrupt + +#define I2C_ST_RXACK (1 << 7) // Received acknowledgement from slave (1 = NAK, 0 = ACK) +#define I2C_ST_BUSY (1 << 6) // 1 after START signal detected; 0 after STOP signal detected +#define I2C_ST_AL (1 << 5) // Arbitration lost. 1 when core lost arbitration +#define I2C_ST_RSVD_4 (1 << 4) // reserved +#define I2C_ST_RSVD_3 (1 << 3) // reserved +#define I2C_ST_RSVD_2 (1 << 2) // reserved +#define I2C_ST_TIP (1 << 1) // Transfer-in-progress +#define I2C_ST_IP (1 << 0) // Interrupt pending + + +//////////////////////////////////////////////// +// GPIO, Slave 4 +// +// These go to the daughterboard i/o pins + +#define GPIO_BASE 0xC800 + +typedef struct { + volatile uint32_t io; // tx data in high 16, rx in low 16 + volatile uint32_t ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16 + volatile uint32_t tx_sel; // 16 2-bit fields select which source goes to TX DB + volatile uint32_t rx_sel; // 16 2-bit fields select which source goes to RX DB +} gpio_regs_t; + +// each 2-bit sel field is layed out this way +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic +#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric + +#define gpio_base ((gpio_regs_t *) GPIO_BASE) + +/////////////////////////////////////////////////// +// Buffer Pool Status, Slave 5 +// +// The buffers themselves are located in Slave 1, Buffer Pool RAM. +// The status registers are in Slave 5, Buffer Pool Status. +// The control register is in Slave 7, Settings Bus. + +#define BUFFER_POOL_STATUS_BASE 0xCC00 + +typedef struct { + volatile uint32_t last_line[NBUFFERS]; // last line xfer'd in buffer + volatile uint32_t status; // error and done flags + volatile uint32_t hw_config; // see below +} buffer_pool_status_t; + +#define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE) + +/* + * Buffer n's xfer is done. + * Clear this bit by issuing bp_clear_buf(n) + */ +#define BPS_DONE(n) (0x00000001 << (n)) +#define BPS_DONE_0 BPS_DONE(0) +#define BPS_DONE_1 BPS_DONE(1) +#define BPS_DONE_2 BPS_DONE(2) +#define BPS_DONE_3 BPS_DONE(3) +#define BPS_DONE_4 BPS_DONE(4) +#define BPS_DONE_5 BPS_DONE(5) +#define BPS_DONE_6 BPS_DONE(6) +#define BPS_DONE_7 BPS_DONE(7) + +/* + * Buffer n's xfer had an error. + * Clear this bit by issuing bp_clear_buf(n) + */ +#define BPS_ERROR(n) (0x00000100 << (n)) +#define BPS_ERROR_0 BPS_ERROR(0) +#define BPS_ERROR_1 BPS_ERROR(1) +#define BPS_ERROR_2 BPS_ERROR(2) +#define BPS_ERROR_3 BPS_ERROR(3) +#define BPS_ERROR_4 BPS_ERROR(4) +#define BPS_ERROR_5 BPS_ERROR(5) +#define BPS_ERROR_6 BPS_ERROR(6) +#define BPS_ERROR_7 BPS_ERROR(7) + +/* + * Buffer n is idle. A buffer is idle if it's not + * DONE, ERROR, or processing a transaction. If it's + * IDLE, it's safe to start a new transaction. + * + * Clear this bit by starting a xfer with + * bp_send_from_buf or bp_receive_to_buf. + */ +#define BPS_IDLE(n) (0x00010000 << (n)) +#define BPS_IDLE_0 BPS_IDLE(0) +#define BPS_IDLE_1 BPS_IDLE(1) +#define BPS_IDLE_2 BPS_IDLE(2) +#define BPS_IDLE_3 BPS_IDLE(3) +#define BPS_IDLE_4 BPS_IDLE(4) +#define BPS_IDLE_5 BPS_IDLE(5) +#define BPS_IDLE_6 BPS_IDLE(6) +#define BPS_IDLE_7 BPS_IDLE(7) + +/* + * Buffer n has a "slow path" packet in it. + * This bit is orthogonal to the bits above and indicates that + * the FPGA ethernet rx protocol engine has identified this packet + * as one requiring firmware intervention. + */ +#define BPS_SLOWPATH(n) (0x01000000 << (n)) +#define BPS_SLOWPATH_0 BPS_SLOWPATH(0) +#define BPS_SLOWPATH_1 BPS_SLOWPATH(1) +#define BPS_SLOWPATH_2 BPS_SLOWPATH(2) +#define BPS_SLOWPATH_3 BPS_SLOWPATH(3) +#define BPS_SLOWPATH_4 BPS_SLOWPATH(4) +#define BPS_SLOWPATH_5 BPS_SLOWPATH(5) +#define BPS_SLOWPATH_6 BPS_SLOWPATH(6) +#define BPS_SLOWPATH_7 BPS_SLOWPATH(7) + + +#define BPS_DONE_ALL 0x000000ff // mask of all dones +#define BPS_ERROR_ALL 0x0000ff00 // mask of all errors +#define BPS_IDLE_ALL 0x00ff0000 // mask of all idles +#define BPS_SLOWPATH_ALL 0xff000000 // mask of all slowpaths + +// The hw_config register + +#define HWC_SIMULATION 0x80000000 +#define HWC_WB_CLK_DIV_MASK 0x0000000f + +/*! + * \brief return non-zero if we're running under the simulator + */ +inline static int +hwconfig_simulation_p(void) +{ + return buffer_pool_status->hw_config & HWC_SIMULATION; +} + +/*! + * \brief Return Wishbone Clock divisor. + * The processor runs at the Wishbone Clock rate which is MASTER_CLK_RATE / divisor. + */ +inline static int +hwconfig_wishbone_divisor(void) +{ + return buffer_pool_status->hw_config & HWC_WB_CLK_DIV_MASK; +} + +/////////////////////////////////////////////////// +// Ethernet Core, Slave 6 + +#define ETH_BASE 0xD000 + +#include "eth_mac_regs.h" + +#define eth_mac ((eth_mac_regs_t *) ETH_BASE) + +//////////////////////////////////////////////////// +// Settings Bus, Slave #7, Not Byte Addressable! +// +// Output-only from processor point-of-view. +// 1KB of address space (== 256 32-bit write-only regs) + + +#define MISC_OUTPUT_BASE 0xD400 +#define TX_PROTOCOL_ENGINE_BASE 0xD480 +#define RX_PROTOCOL_ENGINE_BASE 0xD4C0 +#define BUFFER_POOL_CTRL_BASE 0xD500 +#define DSP_TX_BASE 0xD600 +#define DSP_RX_BASE 0xD680 + +#define LAST_SETTING_REG 0xD7FC // last valid setting register + +// --- buffer pool control regs --- + +typedef struct { + volatile uint32_t ctrl; +} buffer_pool_ctrl_t; + +// buffer pool ports + +#define PORT_SERDES 0 // serial/deserializer +#define PORT_DSP 1 // DSP tx or rx pipeline +#define PORT_ETH 2 // ethernet tx or rx +#define PORT_RAM 3 // RAM tx or rx + +// the buffer pool ctrl register fields + +#define BPC_BUFFER(n) (((n) & 0xf) << 28) +#define BPC_BUFFER_MASK BPC_BUFFER(~0) +#define BPC_BUFFER_0 BPC_BUFFER(0) +#define BPC_BUFFER_1 BPC_BUFFER(1) +#define BPC_BUFFER_2 BPC_BUFFER(2) +#define BPC_BUFFER_3 BPC_BUFFER(3) +#define BPC_BUFFER_4 BPC_BUFFER(4) +#define BPC_BUFFER_5 BPC_BUFFER(5) +#define BPC_BUFFER_6 BPC_BUFFER(6) +#define BPC_BUFFER_7 BPC_BUFFER(7) +#define BPC_BUFFER_NIL BPC_BUFFER(0x8) // disable + +#define BPC_PORT(n) (((n) & 0x7) << 25) +#define BPC_PORT_MASK BPC_PORT(~0) +#define BPC_PORT_SERDES BPC_PORT(PORT_SERDES) +#define BPC_PORT_DSP BPC_PORT(PORT_DSP) +#define BPC_PORT_ETH BPC_PORT(PORT_ETH) +#define BPC_PORT_RAM BPC_PORT(PORT_RAM) +#define BPC_PORT_NIL BPC_PORT(0x4) // disable + +#define BPC_CLR (1 << 24) // mutually excl commands +#define BPC_READ (1 << 23) +#define BPC_WRITE (1 << 22) + +#define BPC_STEP(step) (((step) & 0xf) << 18) +#define BPC_STEP_MASK BPC_STEP(~0) +#define BPC_LAST_LINE(line) (((line) & 0x1ff) << 9) +#define BPC_LAST_LINE_MASK BPC_LAST_LINE(~0) +#define BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0) +#define BPC_FIRST_LINE_MASK BPC_FIRST_LINE(~0) + +#define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE) + +// --- misc outputs --- + +typedef struct { + volatile uint32_t clk_ctrl; + volatile uint32_t serdes_ctrl; + volatile uint32_t adc_ctrl; + volatile uint32_t leds; + volatile uint32_t phy_ctrl; // LSB is reset line to eth phy + volatile uint32_t debug_mux_ctrl; +} output_regs_t; + +#define SERDES_ENABLE 8 +#define SERDES_PRBSEN 4 +#define SERDES_LOOPEN 2 +#define SERDES_RXEN 1 + +#define ADC_CTRL_ON 0x0F +#define ADC_CTRL_OFF 0x00 + +#define output_regs ((output_regs_t *) MISC_OUTPUT_BASE) + +// --- dsp tx regs --- + +#define MIN_INTERP 1 +#define MAX_INTERP 128 + +typedef struct { + volatile int32_t freq; + volatile uint32_t scale_iq; // {scale_i,scale_q} + volatile uint32_t interp_rate; + volatile uint32_t clear_state; // clears out state machine, fifos, + // NOT freq, scale, interp +} dsp_tx_regs_t; + +#define dsp_tx_regs ((dsp_tx_regs_t *) DSP_TX_BASE) + +// --- dsp rx regs --- + +#define T_NOW (-1) + +#define MIN_DECIM 1 +#define MAX_DECIM 128 + +typedef struct { + volatile int32_t freq; + volatile uint32_t scale_iq; // {scale_i,scale_q} + volatile uint32_t decim_rate; + volatile uint32_t rx_time; // when to begin reception + volatile uint32_t rx_command; // {now, chain, num_lines(21), lines_per_frame(9) + volatile uint32_t clear_state; // clears out state machine, fifos, + // cmd queue, NOT freq, scale, decim + volatile uint32_t dcoffset_i; // Bit 31 high sets fixed offset mode, using lower 14 bits, + // otherwise it is automatic + volatile uint32_t dcoffset_q; // Bit 31 high sets fixed offset mode, using lower 14 bits + volatile uint32_t adc_mux; // 4 bits -- lowest 2 for adc_i, next for adc_q + +} dsp_rx_regs_t; + +#define dsp_rx_regs ((dsp_rx_regs_t *) DSP_RX_BASE) + +#define MK_RX_CMD(num_lines, lines_per_frame, now, chain) \ + (((num_lines) << 9) | ((lines_per_frame) & 0x1ff) \ + | (((now) & 0x1) << 31) | (((chain) & 0x1) << 30)) + +/* + * --- ethernet tx protocol engine regs (write only) --- + * + * These registers control the transmit portion of the ethernet + * protocol engine (out of USRP2). The protocol engine handles fifo + * status and sequence number insertion in outgoing packets, and + * automagically generates status packets when required to inform the + * host of changes in fifo availability. + * + * All outgoing packets have their fifo_status field set to the number + * of 32-bit lines of fifo available in the ethernet Rx fifo (see + * usrp2_eth_packet.h). Seqno's are set if FIXME, else 0. + * + * FIXME clean this up once we know how it's supposed to behave. + */ + +typedef struct { + volatile uint32_t flags; // not yet fully defined (channel?) + volatile uint32_t mac_dst0123; // 4 bytes of destination mac addr + volatile uint32_t mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr + volatile uint32_t mac_src2345; // 4 bytes of destination mac addr + volatile uint32_t seqno; // Write to init seqno. It autoincs on match +} tx_proto_engine_regs_t; + +#define tx_proto_engine ((tx_proto_engine_regs_t *) TX_PROTOCOL_ENGINE_BASE) + +/* + * --- ethernet rx protocol engine regs (write only) --- + * + * These registers control the receive portion of the ethernet + * protocol engine (into USRP2). The protocol engine offloads common + * packet inspection operations so that firmware has less to do on + * "fast path" packets. + * + * The registers define conditions which must be matched for a packet + * to be considered a "fast path" packet. If a received packet + * matches the src and dst mac address, ethertype, flags field, and + * expected seqno number it is considered a "fast path" packet, and + * the expected seqno is updated. If the packet fails to satisfy any + * of the above conditions it's a "slow path" packet, and the + * corresponding SLOWPATH flag will be set buffer_status register. + */ + +typedef struct { + volatile uint32_t flags; // not yet fully defined (channel?) + volatile uint32_t mac_dst0123; // 4 bytes of destination mac addr + volatile uint32_t mac_dst45src01; // 2 bytes of dest mac addr; 2 bytes of src mac addr + volatile uint32_t mac_src2345; // 4 bytes of destination mac addr + volatile uint32_t ethertype_pad; // ethertype in high 16-bits +} rx_proto_engine_regs_t; + +#define rx_proto_engine ((rx_proto_engine_regs_t *) RX_PROTOCOL_ENGINE_BASE) + + + +/////////////////////////////////////////////////// +// Simple Programmable Interrupt Controller, Slave 8 + +#define PIC_BASE 0xD800 + +// Interrupt request lines +// Bit numbers (LSB == 0) that correpond to interrupts into PIC + +#define IRQ_BUFFER 0 // buffer manager +#define IRQ_TIMER 1 +#define IRQ_SPI 2 +#define IRQ_I2C 3 +#define IRQ_PHY 4 // ethernet PHY +#define IRQ_UNDERRUN 5 +#define IRQ_OVERRUN 6 +#define IRQ_PPS 7 // pulse per second +#define IRQ_UART_RX 8 +#define IRQ_UART_TX 9 + +#define IRQ_TO_MASK(x) (1 << (x)) + +#define PIC_BUFFER_INT IRQ_TO_MASK(IRQ_BUFFER) +#define PIC_TIMER_INT IRQ_TO_MASK(IRQ_TIMER) +#define PIC_SPI_INT IRQ_TO_MASK(IRQ_SPI) +#define PIC_I2C_INT IRQ_TO_MASK(IRQ_I2C) +#define PIC_PHY_INT IRQ_TO_MASK(IRQ_PHY) +#define PIC_UNDERRUN_INT IRQ_TO_MASK(IRQ_UNDERRUN) +#define PIC_OVERRUN_INT IRQ_TO_MASK(IRQ_OVERRUN) +#define PIC_PPS_INT IRQ_TO_MASK(IRQ_PPS) +#define PIC_UART_RX_INT IRQ_TO_MASK(IRQ_UART_RX) +#define PIC_UART_TX_INT IRQ_TO_MASK(IRQ_UART_TX) + + +typedef struct { + volatile uint32_t edge_enable; // mask: 1 -> edge triggered, 0 -> level + volatile uint32_t polarity; // mask: 1 -> rising edge + volatile uint32_t mask; // mask: 1 -> disabled + volatile uint32_t pending; // mask: 1 -> pending; write 1's to clear pending ints +} pic_regs_t; + +#define pic_regs ((pic_regs_t *) PIC_BASE) + +/////////////////////////////////////////////////// +// Timer, Slave 9 + +#define TIMER_BASE 0xDC00 + +typedef struct { + volatile uint32_t time; // R: current, W: set time to interrupt +} timer_regs_t; + +#define timer_regs ((timer_regs_t *) TIMER_BASE) + +/////////////////////////////////////////////////// +// UART, Slave 10 + +#define UART_BASE 0xE000 + +typedef struct { + // All elements are 8 bits except for clkdiv (16), but we use uint32 to make + // the hardware for decoding easier + volatile uint32_t clkdiv; // Set to 50e6 divided by baud rate (no x16 factor) + volatile uint32_t txlevel; // Number of spaces in the FIFO for writes + volatile uint32_t rxlevel; // Number of available elements in the FIFO for reads + volatile uint32_t txchar; // Write characters to be sent here + volatile uint32_t rxchar; // Read received characters here +} uart_regs_t; + +#define uart_regs ((uart_regs_t *) UART_BASE) + +/////////////////////////////////////////////////// +// ATR Controller, Slave 11 + +#define ATR_BASE 0xE400 + +typedef struct { + volatile uint32_t v[16]; +} atr_regs_t; + +#define ATR_IDLE 0x0 // indicies into v +#define ATR_TX 0x1 +#define ATR_RX 0x2 +#define ATR_FULL 0x3 + +#define atr_regs ((atr_regs_t *) ATR_BASE) + +/////////////////////////////////////////////////// +// Time Sync Controller, Slave 12 + +#define TIMESYNC_BASE 0xE800 + +typedef struct { + volatile uint32_t tick_control; + volatile uint32_t tick_interval; + volatile uint32_t delta_time; +} timesync_regs_t; + +#define timesync_regs ((timesync_regs_t *) TIMESYNC_BASE) + +/////////////////////////////////////////////////// +// SD Card SPI interface, Slave 13 +// All regs are 8 bits wide, but are accessed as if they are 32 bits + +#define SDSPI_BASE 0xEC00 + +typedef struct { + volatile uint32_t status; + volatile uint32_t clkdiv; + volatile uint32_t send_dat; + volatile uint32_t receive_dat; +} sdspi_regs_t; + +#define sdspi_regs ((sdspi_regs_t *) SDSPI_BASE) + +/////////////////////////////////////////////////// + +#endif + diff --git a/usrp2/firmware/lib/memset_wa.c b/usrp2/firmware/lib/memset_wa.c new file mode 100644 index 00000000..da5da21a --- /dev/null +++ b/usrp2/firmware/lib/memset_wa.c @@ -0,0 +1,45 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "memset_wa.h" +#include +#include + +/* + * For setting non-byte-adressable memory, such as + * the buffers. dst and nbytes must all satisfy (x % 4 == 0) + */ +void * +memset_wa(void *dst, int c, size_t nbytes) +{ + if (((intptr_t) dst & 0x3) + || (nbytes & 0x3)) + exit(1); /* die! */ + + int *dp = (int *) dst; + + c &= 0xff; + int v = (c << 24) | (c << 16) | (c << 8) | c; + unsigned nw = nbytes/4; + + unsigned i; + for (i = 0; i < nw; i++) + dp[i] = v; + + return dst; +} diff --git a/usrp2/firmware/lib/memset_wa.h b/usrp2/firmware/lib/memset_wa.h new file mode 100644 index 00000000..46d903d5 --- /dev/null +++ b/usrp2/firmware/lib/memset_wa.h @@ -0,0 +1,27 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_MEMSET_WA_H +#define INCLUDED_MEMSET_WA_H + +#include + +void *memset_wa(void *s, int c, size_t n); + + +#endif /* INCLUDED_MEMSET_WA_H */ diff --git a/usrp2/firmware/lib/microblaze.ld b/usrp2/firmware/lib/microblaze.ld new file mode 100644 index 00000000..ef816cf2 --- /dev/null +++ b/usrp2/firmware/lib/microblaze.ld @@ -0,0 +1,163 @@ +OUTPUT_FORMAT("elf32-microblaze", "", "") +/* SEARCH_DIR(/home/jwilliams/tmp/microblaze-toolchain-sources/release/lin/microblaze//lib);*/ + +ENTRY(_start) + +MEMORY { + flatmem : ORIGIN = 0x0, LENGTH = 0x00008000 /* 32KB */ +} + +SECTIONS +{ + _TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x50; + .vectors.reset 0x0 : { *(.vectors.reset) } > flatmem + .vectors.sw_exception 0x8 : { *(.vectors.sw_exception) } > flatmem + .vectors.interrupt 0x10 : { *(.vectors.interrupt) } > flatmem + .vectors.hw_exception 0x20 : { *(.vectors.hw_exception) } >flatmem + . = _TEXT_START_ADDR; + _ftext = .; + .text : { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flatmem + _etext = .; + .init : { KEEP (*(.init)) } > flatmem =0 + .fini : { KEEP (*(.fini)) } > flatmem =0 + PROVIDE (__CTOR_LIST__ = .); + PROVIDE (___CTOR_LIST__ = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } > flatmem + PROVIDE (__CTOR_END__ = .); + PROVIDE (___CTOR_END__ = .); + PROVIDE (__DTOR_LIST__ = .); + PROVIDE (___DTOR_LIST__ = .); + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } > flatmem + PROVIDE (__DTOR_END__ = .); + PROVIDE (___DTOR_END__ = .); + . = ALIGN(4); + _frodata = . ; + .rodata : { + *(.rodata) + *(.gnu.linkonce.r.*) + CONSTRUCTORS; /* Is this needed? */ + } > flatmem + _erodata = .; + /* Alignments by 8 to ensure that _SDA2_BASE_ on a word boundary */ + /* Note that .sdata2 and .sbss2 must be contiguous */ + . = ALIGN(8); + _ssrw = .; + .sdata2 : { + *(.sdata2) + *(.gnu.linkonce.s2.*) + } > flatmem + . = ALIGN(4); + .sbss2 : { + PROVIDE (__sbss2_start = .); + *(.sbss2) + *(.gnu.linkonce.sb2.*) + PROVIDE (__sbss2_end = .); + } > flatmem + . = ALIGN(8); + _essrw = .; + _ssrw_size = _essrw - _ssrw; + PROVIDE (_SDA2_BASE_ = _ssrw + (_ssrw_size / 2 )); + . = ALIGN(4); + _fdata = .; + .data : { + *(.data) + *(.gnu.linkonce.d.*) + CONSTRUCTORS; /* Is this needed? */ + } > flatmem + _edata = . ; + /* Added to handle pic code */ + .got : { + *(.got) + } > flatmem + .got1 : { + *(.got1) + } > flatmem + .got2 : { + *(.got2) + } > flatmem + /* Added by Sathya to handle C++ exceptions */ + .eh_frame : { + *(.eh_frame) + } > flatmem + .jcr : { + *(.jcr) + } > flatmem + .gcc_except_table : { + *(.gcc_except_table) + } > flatmem + /* Alignments by 8 to ensure that _SDA_BASE_ on a word boundary */ + /* Note that .sdata and .sbss must be contiguous */ + . = ALIGN(8); + _ssro = .; + .sdata : { + *(.sdata) + *(.gnu.linkonce.s.*) + } > flatmem + . = ALIGN(4); + .sbss : { + PROVIDE (__sbss_start = .); + *(.sbss) + *(.gnu.linkonce.sb.*) + PROVIDE (__sbss_end = .); + } > flatmem + . = ALIGN(8); + _essro = .; + _ssro_size = _essro - _ssro; + PROVIDE (_SDA_BASE_ = _ssro + (_ssro_size / 2 )); + . = ALIGN(4); + _fbss = .; + .bss : { + PROVIDE (__bss_start = .); + *(.bss) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + PROVIDE (__bss_end = .); + _heap = .; + _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x0; + _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x800; + . += _HEAP_SIZE; + _heap_end = .; + . += _STACK_SIZE; + . = ALIGN(8); + _stack = .; + _end = .; + } > flatmem + .tdata : { + *(.tdata) + *(.gnu.linkonce.td.*) + } > flatmem + .tbss : { + *(.tbss) + *(.gnu.linkonce.tb.*) + } > flatmem +} diff --git a/usrp2/firmware/lib/nonstdio.c b/usrp2/firmware/lib/nonstdio.c new file mode 100644 index 00000000..1c991afe --- /dev/null +++ b/usrp2/firmware/lib/nonstdio.c @@ -0,0 +1,80 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +static const char hex[16] = "0123456789ABCDEF"; + +// %x +void +puthex4(unsigned long x) +{ + putchar(hex[x & 0xf]); +} + +// %02x +void +puthex8(unsigned long x) +{ + putchar(hex[(x >> 4) & 0xf]); + putchar(hex[x & 0xf]); +} + +// %04x +void +puthex16(unsigned long x) +{ + puthex8(x >> 8); + puthex8(x); +} + +// %08x +void +puthex32(unsigned long x) +{ + puthex16(x >> 16); + puthex16(x); +} + +void +puthex4_nl(unsigned long x) +{ + puthex4(x); + newline(); +} + +void +puthex8_nl(unsigned long x) +{ + puthex8(x); + newline(); +} + +void +puthex16_nl(unsigned long x) +{ + puthex16(x); + newline(); +} + +void +puthex32_nl(unsigned long x) +{ + puthex32(x); + newline(); +} diff --git a/usrp2/firmware/lib/nonstdio.h b/usrp2/firmware/lib/nonstdio.h new file mode 100644 index 00000000..3fd9e39b --- /dev/null +++ b/usrp2/firmware/lib/nonstdio.h @@ -0,0 +1,46 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_NONSTDIO_H +#define INCLUDED_NONSTDIO_H + +#include +#include +#include + +void putstr(const char *s); // cf puts, no added newline +void puthex4(unsigned long x); // output 1 hex digit +void puthex8(unsigned long x); // output 2 hex digits +void puthex16(unsigned long x); // output 4 hex digits +void puthex32(unsigned long x); // output 8 hex digits +void puthex4_nl(unsigned long x); // ... followed by newline +void puthex8_nl(unsigned long x); +void puthex16_nl(unsigned long x); +void puthex32_nl(unsigned long x); +#define puthex puthex32 +#define puthex_nl puthex32_nl +void newline(); // putchar('\n') + +void print_mac_addr(const unsigned char addr[6]); +void print_fxpt_freq(u2_fxpt_freq_t v); +void print_fxpt_gain(u2_fxpt_gain_t v); +void print_uint64(uint64_t v); + +void print_buffer(uint32_t *buf, size_t n); + +#endif /* INCLUDED_NONSTDIO_H */ diff --git a/usrp2/firmware/lib/pic.c b/usrp2/firmware/lib/pic.c new file mode 100644 index 00000000..592a07ae --- /dev/null +++ b/usrp2/firmware/lib/pic.c @@ -0,0 +1,94 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "pic.h" +#include "hal_io.h" +#include "memory_map.h" + + +#define NVECTORS 8 + +/* + * Our secondary interrupt vector. + */ +irq_handler_t pic_vector[NVECTORS] = { + nop_handler, + nop_handler, + nop_handler, + nop_handler, + nop_handler, + nop_handler, + nop_handler, + nop_handler +}; + + +void +pic_init(void) +{ + // uP is level triggered + + pic_regs->mask = ~0; // mask all interrupts + pic_regs->edge_enable = PIC_TIMER_INT | PIC_PHY_INT; + pic_regs->polarity = ~0 & ~PIC_PHY_INT; // rising edge + pic_regs->pending = ~0; // clear all pending ints +} + +/* + * This magic gets pic_interrupt_handler wired into the + * system interrupt handler with the appropriate prologue and + * epilogue. + */ +void pic_interrupt_handler() __attribute__ ((interrupt_handler)); + +void pic_interrupt_handler() +{ + // pending and not masked interrupts + int live = pic_regs->pending & ~pic_regs->mask; + + // FIXME loop while there are interrupts to service. + // That will reduce our overhead. + + // handle the first one set + int i; + int mask; + for (i=0, mask=1; i < NVECTORS; i++, mask <<= 1){ + if (mask & live){ // handle this one + // puthex_nl(i); + (*pic_vector[i])(i); + pic_regs->pending = mask; // clear pending interrupt + return; + } + } +} + +void +pic_register_handler(unsigned irq, irq_handler_t handler) +{ + if (irq >= NVECTORS) + return; + pic_vector[irq] = handler; + + pic_regs->mask &= ~IRQ_TO_MASK(irq); +} + +void +nop_handler(unsigned irq) +{ + // nop +} diff --git a/usrp2/firmware/lib/pic.h b/usrp2/firmware/lib/pic.h new file mode 100644 index 00000000..68918f9a --- /dev/null +++ b/usrp2/firmware/lib/pic.h @@ -0,0 +1,35 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_PIC_H +#define INCLUDED_PIC_H + +typedef void (*irq_handler_t)(unsigned irq); + +void pic_init(void); +void pic_register_handler(unsigned irq, irq_handler_t handler); + +void nop_handler(unsigned irq); // default handler does nothing + +// FIXME inline assembler +int pic_disable_interrupts(); +int pic_enable_interrupts(); +void pic_restore_interrupts(int prev_status); + + +#endif /* INCLUDED_PIC_H */ diff --git a/usrp2/firmware/lib/print_buffer.c b/usrp2/firmware/lib/print_buffer.c new file mode 100644 index 00000000..9f9104bb --- /dev/null +++ b/usrp2/firmware/lib/print_buffer.c @@ -0,0 +1,36 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include + +void +print_buffer(uint32_t *buf, size_t n) +{ + size_t i; + for (i = 0; i < n; i++){ + if (i % 4 == 0) + puthex16(i * 4); + + putchar(' '); + puthex32(buf[i]); + if (i % 4 == 3) + newline(); + } + + newline(); +} + diff --git a/usrp2/firmware/lib/print_fxpt.c b/usrp2/firmware/lib/print_fxpt.c new file mode 100644 index 00000000..185bbc51 --- /dev/null +++ b/usrp2/firmware/lib/print_fxpt.c @@ -0,0 +1,83 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include + +/* + * print uint64_t + */ +void +print_uint64(uint64_t u) +{ + const char *_hex = "0123456789ABCDEF"; + if (u >= 10) + print_uint64(u/10); + putchar(_hex[u%10]); +} + +static void +print_thousandths(int thousandths) +{ + putchar('.'); + if (thousandths < 100) + putchar('0'); + if (thousandths < 10) + putchar('0'); + printf("%d", thousandths); +} + + +void +print_fxpt_freq(u2_fxpt_freq_t v) +{ + if (v < 0){ + v = -v; + putchar('-'); + } + + int64_t int_part = v >> 20; + int32_t frac_part = v & ((1 << 20) - 1); + +#if 0 + // would work, if we had it + printf("%lld.%03d", int_part, (frac_part * 1000) >> 20); +#else + print_uint64(int_part); + print_thousandths((frac_part * 1000) >> 20); +#endif +} + +void +print_fxpt_gain(u2_fxpt_gain_t v) +{ + if (v < 0){ + v = -v; + putchar('-'); + } + + int32_t int_part = v >> 7; + int32_t frac_part = v & ((1 << 7) - 1); + +#if 0 + // would work, if we had it + printf("%d.%03d", int_part, (frac_part * 1000) >> 7); +#else + printf("%d", int_part); + print_thousandths((frac_part * 1000) >> 7); +#endif +} + diff --git a/usrp2/firmware/lib/print_mac_addr.c b/usrp2/firmware/lib/print_mac_addr.c new file mode 100644 index 00000000..838fd614 --- /dev/null +++ b/usrp2/firmware/lib/print_mac_addr.c @@ -0,0 +1,30 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#include "nonstdio.h" + +void +print_mac_addr(const unsigned char addr[6]) +{ + puthex8(addr[0]); putchar(':'); + puthex8(addr[1]); putchar(':'); + puthex8(addr[2]); putchar(':'); + puthex8(addr[3]); putchar(':'); + puthex8(addr[4]); putchar(':'); + puthex8(addr[5]); +} + diff --git a/usrp2/firmware/lib/print_rmon_regs.c b/usrp2/firmware/lib/print_rmon_regs.c new file mode 100644 index 00000000..6d998690 --- /dev/null +++ b/usrp2/firmware/lib/print_rmon_regs.c @@ -0,0 +1,44 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "print_rmon_regs.h" +#include "eth_mac.h" +#include "nonstdio.h" + +void +print_rmon_regs(void) +{ + int i; + for (i=0; i <= 0x10; i++){ + putstr("RMON[0x"); + puthex8(i); + putstr("] = "); + printf("%d\n", eth_mac_read_rmon(i)); + } + + for (i=0x20; i <= 0x30; i++){ + putstr("RMON[0x"); + puthex8(i); + putstr("] = "); + printf("%d\n", eth_mac_read_rmon(i)); + } +} diff --git a/usrp2/firmware/lib/print_rmon_regs.h b/usrp2/firmware/lib/print_rmon_regs.h new file mode 100644 index 00000000..44e52da8 --- /dev/null +++ b/usrp2/firmware/lib/print_rmon_regs.h @@ -0,0 +1,24 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_PRINT_RMON_REGS_H +#define INCLUDED_PRINT_RMON_REGS_H + +void print_rmon_regs(void); + +#endif /* INCLUDED_PRINT_RMON_REGS_H */ diff --git a/usrp2/firmware/lib/printf.c b/usrp2/firmware/lib/printf.c new file mode 100644 index 00000000..45bd57cb --- /dev/null +++ b/usrp2/firmware/lib/printf.c @@ -0,0 +1,134 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Based on code from the SDCC z80 library ;) + */ + +#include +#include + +static void +_printn(unsigned u, unsigned base, char issigned, + void (*emitter)(char, void *), void *pData) +{ + const char *_hex = "0123456789ABCDEF"; + if (issigned && ((int)u < 0)) { + (*emitter)('-', pData); + u = (unsigned)-((int)u); + } + if (u >= base) + _printn(u/base, base, 0, emitter, pData); + (*emitter)(_hex[u%base], pData); +} + +static void +_printf(const char *format, void (*emitter)(char, void *), + void *pData, va_list va) +{ + while (*format) { + if (*format != '%') + (*emitter)(*format, pData); + else { + switch (*++format) { + case 0: /* hit end of format string */ + return; + case 'c': + { + char c = (char)va_arg(va, int); + (*emitter)(c, pData); + break; + } + case 'u': + { + unsigned u = va_arg(va, unsigned); + _printn(u, 10, 0, emitter, pData); + break; + } + case 'd': + { + unsigned u = va_arg(va, unsigned); + _printn(u, 10, 1, emitter, pData); + break; + } + case 'x': + case 'p': + { + unsigned u = va_arg(va, unsigned); + _printn(u, 16, 0, emitter, pData); + break; + } + case 's': + { + char *s = va_arg(va, char *); + while (*s) { + (*emitter)(*s, pData); + s++; + } + break; + } + } + } + format++; + } +} + +static void +_char_emitter(char c, void *pData __attribute__((unused))) +{ + putchar(c); +} + +int +printf(const char *format, ...) +{ + va_list va; + va_start(va, format); + + _printf(format, _char_emitter, NULL, va); + + va_end(va); + + // wrong return value... + return 0; +} + + +#if 0 + +// Totally dangerous. Don't use +static void +_buf_emitter(char c, void *pData) +{ + *((*((char **)pData)))++ = c; +} + +int sprintf(char *pInto, const char *format, ...) +{ + va_list va; + va_start(va, format); + + _printf(format, _buf_emitter, &pInto, va); + *pInto++ = '\0'; + + va_end(va); + + // FIXME wrong return value + return 0; +} +#endif diff --git a/usrp2/firmware/lib/printf.c.smaller b/usrp2/firmware/lib/printf.c.smaller new file mode 100644 index 00000000..4d858648 --- /dev/null +++ b/usrp2/firmware/lib/printf.c.smaller @@ -0,0 +1,134 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Based on code from the SDCC z80 library ;) + */ + +#include +#include +#include /* FIXME refactor into stdio */ + +#define PUTCHAR(x) hal_putc(x) + + +static void +_printn(unsigned u, unsigned base, char issigned) +{ + const char *_hex = "0123456789ABCDEF"; + if (issigned && ((int)u < 0)) { + PUTCHAR('-'); + u = (unsigned)-((int)u); + } + if (u >= base) + _printn(u/base, base, 0); + PUTCHAR(_hex[u%base]); +} + +static void +_printf(const char *format, va_list va) +{ + while (*format) { + if (*format != '%') + PUTCHAR(*format); + else { + switch (*++format) { + case 0: /* hit end of format string */ + return; + case 'c': + { + char c = (char)va_arg(va, int); + PUTCHAR(c); + break; + } + case 'u': + { + unsigned u = va_arg(va, unsigned); + _printn(u, 10, 0); + break; + } + case 'd': + { + unsigned u = va_arg(va, unsigned); + _printn(u, 10, 1); + break; + } + case 'x': + case 'p': + { + unsigned u = va_arg(va, unsigned); + _printn(u, 16, 0); + break; + } + case 's': + { + char *s = va_arg(va, char *); + while (*s) { + PUTCHAR(*s); + s++; + } + break; + } + } + } + format++; + } +} + +#if 0 +static void +_char_emitter(char c, void *pData __attribute__((unused))) +{ + hal_putc(c); +} +#endif + +int +printf(const char *format, ...) +{ + va_list va; + va_start(va, format); + + _printf(format, va); + + // wrong return value... + return 0; +} + + +#if 0 + +// Totally dangerous. Don't use +static void +_buf_emitter(char c, void *pData) +{ + *((*((char **)pData)))++ = c; +} + +int sprintf(char *pInto, const char *format, ...) +{ + va_list va; + va_start(va, format); + + _printf(format, _buf_emitter, &pInto, va); + *pInto++ = '\0'; + + // FIXME wrong return value + return 0; +} +#endif diff --git a/usrp2/firmware/lib/spi.c b/usrp2/firmware/lib/spi.c new file mode 100644 index 00000000..937397df --- /dev/null +++ b/usrp2/firmware/lib/spi.c @@ -0,0 +1,61 @@ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "spi.h" +#include "memory_map.h" + +void +spi_init(void) +{ + /* + * f_sclk = f_wb / ((div + 1) * 2) + */ + spi_regs->div = 1; // 0 = Div by 2 (25 MHz); 1 = Div-by-4 (12.5 MHz) +} + +void +spi_wait(void) +{ + while (spi_regs->ctrl & SPI_CTRL_GO_BSY) + ; +} + +uint32_t +spi_transact(bool readback, int slave, uint32_t data, int length, uint32_t flags) +{ + flags &= (SPI_CTRL_TXNEG | SPI_CTRL_RXNEG); + int ctrl = SPI_CTRL_ASS | (SPI_CTRL_CHAR_LEN_MASK & length) | flags; + + spi_wait(); + + // Tell it which SPI slave device to access + spi_regs->ss = slave & 0xff; + + // Data we will send + spi_regs->txrx0 = data; + + // Run it -- write once and rewrite with GO set + spi_regs->ctrl = ctrl; + spi_regs->ctrl = ctrl | SPI_CTRL_GO_BSY; + + if(readback) { + spi_wait(); + return spi_regs->txrx0; + } + else + return 0; +} diff --git a/usrp2/firmware/lib/spi.h b/usrp2/firmware/lib/spi.h new file mode 100644 index 00000000..0914d6c3 --- /dev/null +++ b/usrp2/firmware/lib/spi.h @@ -0,0 +1,52 @@ +/* -*- c -*- */ +/* + * Copyright 2006,2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_SPI_H +#define INCLUDED_SPI_H + +#include +#include + +/*! + * \brief One time call to initialize SPI + */ +void spi_init(void); + +/*! + * \brief Wait for last SPI transaction to complete. + * Unless you need to know it completed, it's not necessary to call this. + */ +void spi_wait(void); + +#define SPI_TXONLY false // readback: no +#define SPI_TXRX true // readback: yes + +/* + * Flags for spi_transact + */ +#define SPIF_PUSH_RISE 0 // push tx data on rising edge of SCLK +#define SPIF_PUSH_FALL SPI_CTRL_TXNEG // push tx data on falling edge of SCLK +#define SPIF_LATCH_RISE 0 // latch rx data on rising edge of SCLK +#define SPIF_LATCH_FALL SPI_CTRL_RXNEG // latch rx data on falling edge of SCLK + + +uint32_t +spi_transact(bool readback, int slave, uint32_t data, int length, uint32_t flags); + + +#endif /* INCLUDED_SPI_H */ diff --git a/usrp2/firmware/lib/stdint.h b/usrp2/firmware/lib/stdint.h new file mode 100644 index 00000000..8086c25d --- /dev/null +++ b/usrp2/firmware/lib/stdint.h @@ -0,0 +1,34 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_STDINT_H +#define INCLUDED_STDINT_H + +typedef char int8_t; +typedef unsigned char uint8_t; +typedef short int16_t; +typedef unsigned short uint16_t; +typedef int int32_t; +typedef unsigned int uint32_t; +typedef long long int int64_t; +typedef unsigned long long int uint64_t; + +typedef int intptr_t; +typedef unsigned int uintptr_t; + +#endif /* INCLUDED_STDINT_H */ diff --git a/usrp2/firmware/lib/stdio.h b/usrp2/firmware/lib/stdio.h new file mode 100644 index 00000000..12a7ed0b --- /dev/null +++ b/usrp2/firmware/lib/stdio.h @@ -0,0 +1,38 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_STDIO_H +#define INCLUDED_STDIO_H + +// very trimmed down stdio.h See also nonstdio.h + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef EOF +#define EOF (-1) +#endif + +int putchar(int c); +int puts(const char *s); +int printf(const char *format, ...); + +int getchar(void); + +#endif /* INCLUDED_STDIO_H */ diff --git a/usrp2/firmware/lib/u2_init.c b/usrp2/firmware/lib/u2_init.c new file mode 100644 index 00000000..cb4b679c --- /dev/null +++ b/usrp2/firmware/lib/u2_init.c @@ -0,0 +1,111 @@ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "u2_init.h" +#include "memory_map.h" +#include "spi.h" +#include "pic.h" +#include "hal_io.h" +#include "lsadc.h" +#include "lsdac.h" +#include "buffer_pool.h" +#include "hal_uart.h" +#include "i2c.h" +#include "bool.h" +#include "mdelay.h" +#include "ad9777.h" +#include "clocks.h" +#include "db.h" + +//#include "nonstdio.h" + +/* + * We ought to arrange for this to be called before main, but for now, + * we require that the user's main call u2_init as the first thing... + */ +bool +u2_init(void) +{ + // Set GPIOs to inputs + hal_gpio_set_ddr(GPIO_TX_BANK, 0x0000, 0xffff); + hal_gpio_set_ddr(GPIO_RX_BANK, 0x0000, 0xffff); + + hal_gpio_write(GPIO_TX_BANK, 0x0000, 0xffff); // init s/w output value to zero + hal_gpio_write(GPIO_RX_BANK, 0x0000, 0xffff); + + hal_io_init(); + + // init spi, so that we can switch over to the high-speed clock + spi_init(); + + // set up the default clocks + clocks_init(); + + // clocks_enable_test_clk(true); + + // Enable ADCs + output_regs->adc_ctrl = ADC_CTRL_ON; + + // Set up AD9777 DAC + ad9777_write_reg(0, R0_1R); + ad9777_write_reg(1, R1_INTERP_4X | R1_REAL_MIX); + ad9777_write_reg(2, 0); + ad9777_write_reg(3, R3_PLL_DIV_1); + ad9777_write_reg(4, R4_PLL_ON | R4_CP_AUTO); + ad9777_write_reg(5, R5_I_FINE_GAIN(0)); + ad9777_write_reg(6, R6_I_COARSE_GAIN(0xf)); + ad9777_write_reg(7, 0); // I dac offset + ad9777_write_reg(8, 0); + ad9777_write_reg(9, R9_Q_FINE_GAIN(0)); + ad9777_write_reg(10, R10_Q_COARSE_GAIN(0xf)); + ad9777_write_reg(11, 0); // Q dac offset + ad9777_write_reg(12, 0); + + // Set up serdes + output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN); + + pic_init(); // progammable interrupt controller + bp_init(); // buffer pool + i2c_init(); + lsadc_init(); // low-speed ADCs + lsdac_init(); // low-speed DACs + db_init(); // daughterboard init + + hal_enable_ints(); + + // flash all leds to let us know board is alive + hal_set_leds(0x0, 0x1f); + mdelay(100); + hal_set_leds(0x1f, 0x1f); + mdelay(100); + hal_set_leds(0x0, 0x1f); + mdelay(100); + +#if 0 + // test register readback + int rr, vv; + vv = ad9777_read_reg(0); + printf("ad9777 reg[0] = 0x%x\n", vv); + + for (rr = 0x04; rr <= 0x0d; rr++){ + vv = ad9510_read_reg(rr); + printf("ad9510 reg[0x%x] = 0x%x\n", rr, vv); + } +#endif + + return true; +} diff --git a/usrp2/firmware/lib/u2_init.h b/usrp2/firmware/lib/u2_init.h new file mode 100644 index 00000000..901e6125 --- /dev/null +++ b/usrp2/firmware/lib/u2_init.h @@ -0,0 +1,26 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_U2_INIT_H +#define INCLUDED_U2_INIT_H + +/*! + * one-time init + */ +int u2_init(void); + +#endif /* INCLUDED_U2_INIT_H */ diff --git a/usrp2/firmware/lib/usrp2_bytesex.h b/usrp2/firmware/lib/usrp2_bytesex.h new file mode 100644 index 00000000..2b74f2a0 --- /dev/null +++ b/usrp2/firmware/lib/usrp2_bytesex.h @@ -0,0 +1,66 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_USRP2_BYTESEX_H +#define INCLUDED_USRP2_BYTESEX_H + +// The USRP2 speaks big-endian... +// Use the standard include files or provide substitutions for +// htons and friends + +#if defined(HAVE_ARPA_INET_H) +#include +#elif defined(HAVE_NETINET_IN_H) +#include +#else +#include + +#ifdef WORDS_BIGENDIAN // nothing to do... + +static inline uint32_t htonl(uint32_t x){ return x; } +static inline uint16_t htons(uint16_t x){ return x; } +static inline uint32_t ntohl(uint32_t x){ return x; } +static inline uint16_t ntohs(uint16_t x){ return x; } + +#else + +#ifdef HAVE_BYTESWAP_H +#include +#else + +static inline uint16_t +bswap_16 (uint16_t x) +{ + return ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8)); +} + +static inline uint32_t +bswap_32 (uint32_t x) +{ + return ((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >> 8) \ + | (((x) & 0x0000ff00) << 8) | (((x) & 0x000000ff) << 24)); +} +#endif + +static inline uint32_t htonl(uint32_t x){ return bswap_32(x); } +static inline uint16_t htons(uint16_t x){ return bswap_16(x); } +static inline uint32_t ntohl(uint32_t x){ return bswap_32(x); } +static inline uint16_t ntohs(uint16_t x){ return bswap_16(x); } + +#endif +#endif +#endif /* INCLUDED_USRP2_BYTESEX_H */ diff --git a/usrp2/firmware/lib/wb16550.h b/usrp2/firmware/lib/wb16550.h new file mode 100644 index 00000000..7522f443 --- /dev/null +++ b/usrp2/firmware/lib/wb16550.h @@ -0,0 +1,98 @@ +/* -*- c -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + + +// Wishbone National Semiconductor 16550A compatible UART + +#ifndef INCLUDED_WB16550_H +#define INCLUDED_WB16550_H + +#include + +typedef struct { + volatile uint8_t data; // 0 r/w: r: rx fifo, w: tx fifo (if DLAB: LSB of divisor) + volatile uint8_t ier; // 1 r/w: Interrupt Enable Register (if DLAB: MSB of divisor) + volatile uint8_t iir_fcr; // 2 r/w: r: Interrupt ID Register, + // w: Fifo Control Register + volatile uint8_t lcr; // 3 r/w: Line Control Register + volatile uint8_t mcr; // 4 w: Modem Control Register + volatile uint8_t lsr; // 5 r: Line Status Register + volatile uint8_t msr; // 6 r: Modem Status Register + +} wb16550_reg_t; + +#define UART_IER_RDI 0x01 // Enable received data interrupt +#define UART_IER_THRI 0x02 // Enable transmitter holding reg empty int. +#define UART_IER_RLSI 0x04 // Enable receiver line status interrupt +#define UART_IER_MSI 0x08 // Enable modem status interrupt + +#define UART_IIR_NO_INT 0x01 // No interrupts pending +#define UART_IIR_ID_MASK 0x06 // Mask for interrupt ID +#define UART_IIR_MSI 0x00 // Modem status interrupt +#define UART_IIR_THRI 0x02 // Tx holding register empty int +#define UART_IIR_RDI 0x04 // Rx data available int +#define UART_IIR_RLSI 0x06 // Receiver line status int + +#define UART_FCR_ENABLE_FIFO 0x01 // ignore, always enabled +#define UART_FCR_CLEAR_RCVR 0x02 // Clear the RCVR FIFO +#define UART_FCR_CLEAR_XMIT 0x04 // Clear the XMIT FIFO +#define UART_FCR_TRIGGER_MASK 0xC0 // Mask for FIFO trigger range +#define UART_FCR_TRIGGER_1 0x00 // Rx fifo trigger level: 1 byte +#define UART_FCR_TRIGGER_4 0x40 // Rx fifo trigger level: 4 bytes +#define UART_FCR_TRIGGER_8 0x80 // Rx fifo trigger level: 8 bytes +#define UART_FCR_TRIGGER_14 0xC0 // Rx fifo trigger level: 14 bytes + +#define UART_LCR_DLAB 0x80 // Divisor latch access bit +#define UART_LCR_SBC 0x40 // Set break control +#define UART_LCR_SPAR 0x20 // Stick parity +#define UART_LCR_EPAR 0x10 // Even parity select +#define UART_LCR_PARITY 0x08 // Parity Enable +#define UART_LCR_STOP 0x04 // Stop bits: 0=1 bit, 1=2 bits +#define UART_LCR_WLEN5 0x00 // Wordlength: 5 bits +#define UART_LCR_WLEN6 0x01 // Wordlength: 6 bits +#define UART_LCR_WLEN7 0x02 // Wordlength: 7 bits +#define UART_LCR_WLEN8 0x03 // Wordlength: 8 bits + +#define UART_MCR_LOOP 0x10 // Enable loopback test mode +#define UART_MCR_OUT2n 0x08 // Out2 complement (loopback mode) +#define UART_MCR_OUT1n 0x04 // Out1 complement (loopback mode) +#define UART_MCR_RTSn 0x02 // RTS complement +#define UART_MCR_DTRn 0x01 // DTR complement + +#define UART_LSR_TEMT 0x40 // Transmitter empty +#define UART_LSR_THRE 0x20 // Transmit-hold-register empty +#define UART_LSR_BI 0x10 // Break interrupt indicator +#define UART_LSR_FE 0x08 // Frame error indicator +#define UART_LSR_PE 0x04 // Parity error indicator +#define UART_LSR_OE 0x02 // Overrun error indicator +#define UART_LSR_DR 0x01 // Receiver data ready +#define UART_LSR_BRK_ERROR_BITS 0x1E // BI, FE, PE, OE bits +#define UART_LSR_ERROR 0x80 // At least 1 PE, FE or BI are in the fifo + +#define UART_MSR_DCD 0x80 // Data Carrier Detect +#define UART_MSR_RI 0x40 // Ring Indicator +#define UART_MSR_DSR 0x20 // Data Set Ready +#define UART_MSR_CTS 0x10 // Clear to Send +#define UART_MSR_DDCD 0x08 // Delta DCD +#define UART_MSR_TERI 0x04 // Trailing edge ring indicator +#define UART_MSR_DDSR 0x02 // Delta DSR +#define UART_MSR_DCTS 0x01 // Delta CTS +#define UART_MSR_ANY_DELTA 0x0F // Any of the delta bits! + + +#endif // INCLUDED_WB16550_H diff --git a/usrp2/firmware/u2_flash_tool b/usrp2/firmware/u2_flash_tool new file mode 100755 index 00000000..2b66a4ac --- /dev/null +++ b/usrp2/firmware/u2_flash_tool @@ -0,0 +1,116 @@ +#!/usr/bin/env python + +import sys +from optparse import OptionParser + +SECTOR_SIZE = 512 # bytes +MAX_FILE_SIZE = 1 * (2**20) # maximum number of bytes we'll burn to a slot + +FPGA_OFFSET = 0 # offset in flash to fpga image +FIRMWARE_OFFSET = 1 * (2**20) # offset in flash to firmware image + +def read_file_data(filename): + f = open(filename, "rb") + file_data = f.read(MAX_FILE_SIZE) + t = len(file_data) % SECTOR_SIZE + if t != 0: + file_data += (SECTOR_SIZE - t)*chr(0) # pad to an even sector size w/ zeros + return file_data + + +def write_flash(offset, filename, devname): + file_data = read_file_data(filename) + dev = open(devname, "wb") + dev.seek(offset, 0) # seek to absolute byte offset + dev.write(file_data) + dev.flush() + dev.close() + return True + + +def verify_flash(offset, filename, devname): + file_data = read_file_data(filename) + dev = open(devname, "rb") + dev.seek(offset, 0) # seek to absolute byte offset + dev_data = dev.read(len(file_data)) + if len(dev_data) != len(file_data): + sys.stderr.write("short read on device %s\n" % (devname,)) + return False + + if file_data == dev_data: + return True + + # doesn't match + nwrong = 0 + for i in range(len(file_data)): + if dev_data[i] != file_data[i]: + sys.stderr.write("mismatch at offset %7d. Expected 0x%02x, got 0x%02x\n" % ( + i, ord(file_data[i]), ord(dev_data[i]))) + nwrong += 1 + if nwrong > 16: + sys.stderr.write("> 16 errors, stopping comparison\n") + break + return False + +def read_flash(offset, filename, devname): + dev = open(devname, "rb") + dev.seek(offset, 0) # seek to absolute byte offset + dev_data = dev.read(MAX_FILE_SIZE) + dev.close() + open(filename, "wb").write(dev_data) + + +def main(): + parser = OptionParser(usage="%prog: [options] filename") + parser.add_option("-w", "--write", action="store_const", const="write", dest="mode", + help="write FILE to TARGET slot") + parser.add_option("-v", "--verify", action="store_const", const="verify", dest="mode", + help="verify FILE against TARGET slot") + parser.add_option("-r", "--read", action="store_const", const="read", dest="mode", + help="read TARGET slot, write to FILE") + parser.add_option("-t", "--target", type="choice", choices=("fpga", "s/w"), default="s/w", + help="select TARGET slot from: fpga, s/w [default=%default]") + parser.add_option("", "--dev", default=None, + help="specify flash device file, e.g., /dev/sdb. Be careful!") + parser.set_defaults(target="s/w", mode=None) + + (options, args) = parser.parse_args() + if len(args) != 1: + parser.print_help() + raise SystemExit + + filename = args[0] + + if options.mode is None: + sys.stderr.write("specify mode with -w, -v or -r\n") + parser.print_help() + raise SystemExit + + if options.dev is None: + sys.stderr.write("specify the device file with --dev\n") + parser.print_help() + raise SystemExit + + offset = { "fpga" : FPGA_OFFSET, "s/w" : FIRMWARE_OFFSET }[options.target] + + if options.mode == "write": + r = (write_flash(offset, filename, options.dev) + and verify_flash(offset, filename, options.dev)) + elif options.mode == "verify": + r = verify_flash(offset, filename, options.dev) + elif options.mode == "read": + r = read_flash(offset, filename, options.dev) + else: + raise NotImplemented + + if not r: + raise SystemExit, 1 + + +if __name__ == "__main__": + main() + + + + + diff --git a/usrp2/fpga/boot_cpld/_impact.cmd b/usrp2/fpga/boot_cpld/_impact.cmd new file mode 100755 index 00000000..4af86cb0 --- /dev/null +++ b/usrp2/fpga/boot_cpld/_impact.cmd @@ -0,0 +1,34 @@ +loadProjectFile -file "C:\cygwin\home\matt\usrp2\fpga\boot_cpld/boot_cpld.ipf" +setMode -ss +setMode -sm +setMode -hw140 +setMode -spi +setMode -acecf +setMode -acempm +setMode -pff +setMode -bs +setMode -bs +setMode -bs +setMode -bs +setCable -port auto +Identify +identifyMPM +assignFile -p 1 -file "C:/cygwin/home/matt/usrp2/fpga/boot_cpld/boot_cpld.jed" +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Program -p 1 -e -v -defaultVersion 0 +Identify +identifyMPM +Identify +identifyMPM +Identify +identifyMPM +Identify +identifyMPM +Identify +identifyMPM +setMode -bs +deleteDevice -position 1 diff --git a/usrp2/fpga/boot_cpld/boot_cpld.ipf b/usrp2/fpga/boot_cpld/boot_cpld.ipf new file mode 100755 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X^kyJ2KK#c`W)i=>W5$bu^!fh))y_%0 literal 0 HcmV?d00001 diff --git a/usrp2/fpga/boot_cpld/boot_cpld.lfp b/usrp2/fpga/boot_cpld/boot_cpld.lfp new file mode 100755 index 00000000..0f0c8f2e --- /dev/null +++ b/usrp2/fpga/boot_cpld/boot_cpld.lfp @@ -0,0 +1,5 @@ +# begin LFP file C:\cygwin\home\matt\u2f\boot_cpld\boot_cpld.lfp +designfile boot_cpld.v +parttype xc9572xl-vq44-10 +bus_delimiter 0; +set_busdelim_onsave 1; diff --git a/usrp2/fpga/boot_cpld/boot_cpld.ucf b/usrp2/fpga/boot_cpld/boot_cpld.ucf new file mode 100755 index 00000000..789bb1d9 --- /dev/null +++ b/usrp2/fpga/boot_cpld/boot_cpld.ucf @@ -0,0 +1,34 @@ +NET "CLK_25MHZ" LOC = "P5" ; +NET "CLK_25MHZ_EN" LOC = "P6" ; +NET "LED<0>" LOC = "P12" ; +NET "LED<1>" LOC = "P8" ; +NET "LED<2>" LOC = "P7" ; +NET "DEBUG<0>" LOC = "P1" ; +NET "DEBUG<1>" LOC = "P2" ; +NET "DEBUG<2>" LOC = "P3" ; +NET "DEBUG<3>" LOC = "P29" ; +NET "DEBUG<4>" LOC = "P30" ; +NET "DEBUG<5>" LOC = "P31" ; +NET "DEBUG<6>" LOC = "P32" ; +NET "DEBUG<7>" LOC = "P33" ; +NET "DEBUG<8>" LOC = "P34" ; +NET "POR" LOC = "P42" ; +NET "SD_nCS" LOC = "P20" ; +NET "SD_Din" LOC = "P21" ; +NET "SD_CLK" LOC = "P22" ; +NET "SD_Dout" LOC = "P23" ; +NET "SD_DAT1" LOC = "P27" ; +NET "SD_DAT2" LOC = "P28" ; +NET "SD_prot" LOC = "P19" ; +NET "SD_det" LOC = "P36" ; +NET "CFG_INIT_B" LOC = "P38" ; +NET "CFG_Din" LOC = "P37" ; +NET "CFG_CCLK" LOC = "P41" ; +NET "CFG_DONE" LOC = "P40" ; +NET "CFG_PROG_B" LOC = "P39" ; +NET "CPLD_CLK" LOC = "P13" ; +NET "START" LOC = "P14" ; +NET "MODE" LOC = "P18" ; +NET "DONE" LOC = "P16" ; +NET "detached" LOC = "P43" ; +NET "CPLD_misc" LOC = "P44" ; diff --git a/usrp2/fpga/boot_cpld/boot_cpld.v b/usrp2/fpga/boot_cpld/boot_cpld.v new file mode 100755 index 00000000..3c53a799 --- /dev/null +++ b/usrp2/fpga/boot_cpld/boot_cpld.v @@ -0,0 +1,85 @@ +`timescale 1ns / 1ps +// //////////////////////////////////////////////////////////////////////////////// +// Boot CPLD design, only for u2_rev2 +// //////////////////////////////////////////////////////////////////////////////// + +module boot_cpld + (input CLK_25MHZ, + output CLK_25MHZ_EN, + output [2:0] LED, + output [8:0] DEBUG, + input POR, + + // To SD Card + output SD_nCS, + output SD_Din, + output SD_CLK, + input SD_Dout, + input SD_DAT1, // Unused + input SD_DAT2, // Unused + input SD_prot, // Write Protect + input SD_det, // Card Detect + + // To FPGA Config Interface + input CFG_INIT_B, + output CFG_Din, // Also used in Data interface + output CFG_CCLK, + input CFG_DONE, + output CFG_PROG_B, + + // To FPGA data interface + output CPLD_CLK, + input START, + input MODE, + input DONE, + output detached, + input CPLD_misc // Unused for now + ); + + assign CLK_25MHZ_EN = 1'b1; + + assign LED[0] = ~CFG_DONE; + assign LED[1] = CFG_INIT_B; + assign LED[2] = ~CFG_PROG_B; + + wire en_outs; + wire [3:0] set_sel = 4'd0; + + assign CPLD_CLK = CFG_CCLK; + assign DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, CFG_CCLK, CFG_PROG_B, CFG_INIT_B, CFG_DONE, CFG_Din}; + + spi_boot #(.width_set_sel_g(4), // How many sets (16) + .width_bit_cnt_g(6), // Block length (12 is faster, 6 is minimum) + .width_img_cnt_g(2), // How many images per set + .num_bits_per_img_g(20), // Image size, 20 = 1MB + .sd_init_g(1), // SD-specific initialization + .mmc_compat_clk_div_g(0),// No MMC support + .width_mmc_clk_div_g(0), // No MMC support + .reset_level_g(0)) // Active low reset + + spi_boot(.clk_i(CLK_25MHZ), + .reset_i(POR), + + // To SD Card + .spi_clk_o(SD_CLK), + .spi_cs_n_o(SD_nCS), + .spi_data_in_i(SD_Dout), + .spi_data_out_o(SD_Din), + .spi_en_outs_o(en_outs), + + // Data Port + .start_i(START), + .mode_i(MODE), // 0->conf mode, 1->data mode + .detached_o(detached), + .dat_done_i(DONE), + .set_sel_i(set_sel), + + // To FPGA + .config_n_o(CFG_PROG_B), + .cfg_init_n_i(CFG_INIT_B), + .cfg_done_i(CFG_DONE), + .cfg_clk_o(CFG_CCLK), + .cfg_dat_o(CFG_Din) + ); + +endmodule // boot_cpld diff --git a/usrp2/fpga/control_lib/CRC16_D16.v b/usrp2/fpga/control_lib/CRC16_D16.v new file mode 100644 index 00000000..7e2816af --- /dev/null +++ b/usrp2/fpga/control_lib/CRC16_D16.v @@ -0,0 +1,89 @@ +/////////////////////////////////////////////////////////////////////// +// File: CRC16_D16.v +// Date: Sun Jun 17 06:42:55 2007 +// +// Copyright (C) 1999-2003 Easics NV. +// This source file may be used and distributed without restriction +// provided that this copyright statement is not removed from the file +// and that any derivative work contains the original copyright notice +// and the associated disclaimer. +// +// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +// Purpose: Verilog module containing a synthesizable CRC function +// * polynomial: (0 5 12 16) +// * data width: 16 +// +// Info: tools@easics.be +// http://www.easics.com +/////////////////////////////////////////////////////////////////////// + + +module CRC16_D16 + (input [15:0] Data, + input [15:0] CRC, + output [15:0] NewCRC); + + assign NewCRC = nextCRC16_D16(Data,CRC); + + // polynomial: (0 5 12 16) + // data width: 16 + // convention: the first serial data bit is D[15] + function [15:0] nextCRC16_D16; + + input [15:0] Data; + input [15:0] CRC; + + reg [15:0] D; + reg [15:0] C; + reg [15:0] NewCRC; + + begin + + D = Data; + C = CRC; + + NewCRC[0] = D[12] ^ D[11] ^ D[8] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ + C[8] ^ C[11] ^ C[12]; + NewCRC[1] = D[13] ^ D[12] ^ D[9] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ + C[9] ^ C[12] ^ C[13]; + NewCRC[2] = D[14] ^ D[13] ^ D[10] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ + C[10] ^ C[13] ^ C[14]; + NewCRC[3] = D[15] ^ D[14] ^ D[11] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ + C[11] ^ C[14] ^ C[15]; + NewCRC[4] = D[15] ^ D[12] ^ D[8] ^ D[4] ^ C[4] ^ C[8] ^ C[12] ^ + C[15]; + NewCRC[5] = D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ D[4] ^ + D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ + C[13]; + NewCRC[6] = D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[5] ^ + D[1] ^ C[1] ^ C[5] ^ C[6] ^ C[9] ^ C[10] ^ C[12] ^ + C[13] ^ C[14]; + NewCRC[7] = D[15] ^ D[14] ^ D[13] ^ D[11] ^ D[10] ^ D[7] ^ D[6] ^ + D[2] ^ C[2] ^ C[6] ^ C[7] ^ C[10] ^ C[11] ^ C[13] ^ + C[14] ^ C[15]; + NewCRC[8] = D[15] ^ D[14] ^ D[12] ^ D[11] ^ D[8] ^ D[7] ^ D[3] ^ + C[3] ^ C[7] ^ C[8] ^ C[11] ^ C[12] ^ C[14] ^ C[15]; + NewCRC[9] = D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[8] ^ D[4] ^ C[4] ^ + C[8] ^ C[9] ^ C[12] ^ C[13] ^ C[15]; + NewCRC[10] = D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[5] ^ C[5] ^ C[9] ^ + C[10] ^ C[13] ^ C[14]; + NewCRC[11] = D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[6] ^ C[6] ^ C[10] ^ + C[11] ^ C[14] ^ C[15]; + NewCRC[12] = D[15] ^ D[8] ^ D[7] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ C[7] ^ + C[8] ^ C[15]; + NewCRC[13] = D[9] ^ D[8] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ C[8] ^ C[9]; + NewCRC[14] = D[10] ^ D[9] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ C[9] ^ C[10]; + NewCRC[15] = D[11] ^ D[10] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ C[10] ^ + C[11]; + + nextCRC16_D16 = NewCRC; + + end + + endfunction + +endmodule + diff --git a/usrp2/fpga/control_lib/SYSCTRL.sav b/usrp2/fpga/control_lib/SYSCTRL.sav new file mode 100644 index 00000000..43bfef10 --- /dev/null +++ b/usrp2/fpga/control_lib/SYSCTRL.sav @@ -0,0 +1,24 @@ +[size] 1400 971 +[pos] -1 -1 +*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +system_control_tb.aux_clk +@29 +system_control_tb.clk_fpga +@28 +system_control_tb.dsp_clk +system_control_tb.dsp_rst +system_control_tb.proc_rst +system_control_tb.rl_done +system_control_tb.rl_rst +system_control_tb.wb_clk +system_control_tb.wb_rst +system_control_tb.system_control.POR +@22 +system_control_tb.system_control.POR_ctr[3:0] +@28 +system_control_tb.clock_ready +system_control_tb.system_control.half_clk +system_control_tb.system_control.fin_ret_half +system_control_tb.system_control.fin_ret_aux +system_control_tb.system_control.gate_dsp_clk diff --git a/usrp2/fpga/control_lib/WB_SIM.sav b/usrp2/fpga/control_lib/WB_SIM.sav new file mode 100644 index 00000000..467cd35e --- /dev/null +++ b/usrp2/fpga/control_lib/WB_SIM.sav @@ -0,0 +1,47 @@ +[size] 1400 971 +[pos] -1 -1 +*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +wb_sim.wb_rst +wb_sim.wb_clk +@23 +wb_sim.rom_data[47:0] +@22 +wb_sim.rom_addr[15:0] +@28 +wb_sim.start +wb_sim.wb_ack +@22 +wb_sim.wb_adr[15:0] +@28 +wb_sim.wb_cyc +@22 +wb_sim.wb_dat[31:0] +wb_sim.wb_sel[3:0] +@28 +wb_sim.wb_stb +wb_sim.wb_we +@22 +wb_sim.port_output[31:0] +@28 +wb_sim.system_control.POR +wb_sim.system_control.aux_clk +wb_sim.system_control.clk_fpga +@29 +wb_sim.system_control.done +@28 +wb_sim.system_control.dsp_clk +wb_sim.system_control.fin_del1 +wb_sim.system_control.fin_del2 +wb_sim.system_control.fin_del3 +wb_sim.system_control.fin_ret_aux +@29 +wb_sim.system_control.fin_ret_fpga +@28 +wb_sim.system_control.finished +wb_sim.system_control.reset_out +wb_sim.system_control.start +wb_sim.system_control.started +wb_sim.system_control.wb_clk_o +wb_sim.system_control.wb_rst_o +wb_sim.system_control.wb_rst_o_alt diff --git a/usrp2/fpga/control_lib/atr_controller.v b/usrp2/fpga/control_lib/atr_controller.v new file mode 100644 index 00000000..fed2791f --- /dev/null +++ b/usrp2/fpga/control_lib/atr_controller.v @@ -0,0 +1,57 @@ + +// Automatic transmit/receive switching of control pins to daughterboards +// Store everything in registers for now, but could use a RAM for more +// complex state machines in the future + +module atr_controller + (input clk_i, input rst_i, + input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input run_rx, input run_tx, input [31:0] master_time, + output [31:0] ctrl_lines); + + reg [3:0] state; + reg [31:0] atr_ram [0:15]; // DP distributed RAM + + // WB Interface + always @(posedge clk_i) + if(we_i & stb_i & cyc_i) + begin + if(sel_i[3]) + atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24]; + if(sel_i[2]) + atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16]; + if(sel_i[1]) + atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; + if(sel_i[0]) + atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; + end // if (we_i & stb_i & cyc_i) + + always @(posedge clk_i) + dat_o <= atr_ram[adr_i[5:2]]; + + always @(posedge clk_i) + ack_o <= stb_i & cyc_i & ~ack_o; + + // Control side of DP RAM + assign ctrl_lines = atr_ram[state]; + + // Put a more complex state machine with time delays and multiple states here + // if daughterboard requires more complex sequencing + localparam ATR_IDLE = 4'd0; + localparam ATR_TX = 4'd1; + localparam ATR_RX = 4'd2; + localparam ATR_FULL_DUPLEX = 4'd3; + + always @(posedge clk_i) + if(rst_i) + state <= ATR_IDLE; + else + case ({run_rx,run_tx}) + 2'b00 : state <= ATR_IDLE; + 2'b01 : state <= ATR_TX; + 2'b10 : state <= ATR_RX; + 2'b11 : state <= ATR_FULL_DUPLEX; + endcase // case({run_rx,run_tx}) + +endmodule // atr_controller diff --git a/usrp2/fpga/control_lib/bin2gray.v b/usrp2/fpga/control_lib/bin2gray.v new file mode 100644 index 00000000..51340216 --- /dev/null +++ b/usrp2/fpga/control_lib/bin2gray.v @@ -0,0 +1,10 @@ + + +module bin2gray + #(parameter WIDTH=8) + (input [WIDTH-1:0] bin, + output [WIDTH-1:0] gray); + + assign gray = (bin >> 1) ^ bin; + +endmodule // bin2gray diff --git a/usrp2/fpga/control_lib/bootrom.mem b/usrp2/fpga/control_lib/bootrom.mem new file mode 100644 index 00000000..d688b434 --- /dev/null +++ b/usrp2/fpga/control_lib/bootrom.mem @@ -0,0 +1,26 @@ +00000C000F03 +101400000000 + // SPI: Set Divider to div by 2 +// Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds +1018_0000_0001 // SPI: Choose AD9510 +1010_0000_3418 // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word +1000_0000_0010 // SPI: AD9510 A:0 D:10 Set up AD9510 SPI +1010_0000_3518 // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word +ffff_ffff_ffff // terminate +#// First 16 bits are address, last 32 are data +#// First 4 bits of address select which slave +// 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on +// 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels +// 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) +// 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal +// 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current +// 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On +// 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) +// 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 +// 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det +// 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... +// 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care +// 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 +// 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 + // default : addr_data = {13'h5A,8'h01}; // Register Update +// @ 55 // Jump to new address 8'h55 diff --git a/usrp2/fpga/control_lib/buffer_int.v b/usrp2/fpga/control_lib/buffer_int.v new file mode 100644 index 00000000..e362d93f --- /dev/null +++ b/usrp2/fpga/control_lib/buffer_int.v @@ -0,0 +1,191 @@ + +// FIFO Interface to the 2K buffer RAMs +// Read port is read-acknowledge +// FIXME do we want to be able to interleave reads and writes? + +module buffer_int + #(parameter BUFF_NUM = 0) + (// Control Interface + input clk, + input rst, + input [31:0] ctrl_word, + input go, + output done, + output error, + output idle, + + // Buffer Interface + output en_o, + output we_o, + output reg [8:0] addr_o, + output [31:0] dat_to_buf, + input [31:0] dat_from_buf, + + // Write FIFO Interface + input [31:0] wr_dat_i, + input wr_write_i, + input wr_done_i, + input wr_error_i, + output reg wr_ready_o, + output reg wr_full_o, + + // Read FIFO Interface + output [31:0] rd_dat_o, + input rd_read_i, + input rd_done_i, + input rd_error_i, + output reg rd_sop_o, + output reg rd_eop_o + ); + + reg [31:0] ctrl_reg; + reg go_reg; + + always @(posedge clk) + go_reg <= go; + + always @(posedge clk) + if(rst) + ctrl_reg <= 0; + else + if(go & (ctrl_word[31:28] == BUFF_NUM)) + ctrl_reg <= ctrl_word; + + wire [8:0] firstline = ctrl_reg[8:0]; + wire [8:0] lastline = ctrl_reg[17:9]; + wire [3:0] step = ctrl_reg[21:18]; + wire read = ctrl_reg[22]; + wire write = ctrl_reg[23]; + wire clear = ctrl_reg[24]; + //wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block + //wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ? + + assign dat_to_buf = wr_dat_i; + assign rd_dat_o = dat_from_buf; + + localparam IDLE = 3'd0; + localparam PRE_READ = 3'd1; + localparam READING = 3'd2; + localparam WRITING = 3'd3; + localparam ERROR = 3'd4; + localparam DONE = 3'd5; + + reg [2:0] state; + + always @(posedge clk) + if(rst) + begin + state <= IDLE; + rd_sop_o <= 0; + rd_eop_o <= 0; + wr_ready_o <= 0; + wr_full_o <= 0; + end + else + if(clear) + begin + state <= IDLE; + rd_sop_o <= 0; + rd_eop_o <= 0; + wr_ready_o <= 0; + wr_full_o <= 0; + end + else + case(state) + IDLE : + if(go_reg & read) + begin + addr_o <= firstline; + state <= PRE_READ; + end + else if(go_reg & write) + begin + addr_o <= firstline; + state <= WRITING; + wr_ready_o <= 1; + end + + PRE_READ : + begin + state <= READING; + addr_o <= addr_o + 1; + rd_sop_o <= 1; + end + + READING : + if(rd_error_i) + state <= ERROR; + else if(rd_done_i) + state <= DONE; + else if(rd_read_i) + begin + rd_sop_o <= 0; + addr_o <= addr_o + 1; + if(addr_o == lastline) + rd_eop_o <= 1; + else + rd_eop_o <= 0; + if(rd_eop_o) + state <= DONE; + end + + WRITING : + begin + if(wr_error_i) + begin + state <= ERROR; + wr_ready_o <= 0; + end + else + begin + if(wr_write_i) + begin + wr_ready_o <= 0; + addr_o <= addr_o + 1; + if(addr_o == (lastline-1)) + wr_full_o <= 1; + if(addr_o == lastline) + state <= DONE; + end + if(wr_done_i) + begin + state <= DONE; + wr_ready_o <= 0; + end + end // else: !if(wr_error_i) + end // case: WRITING + + DONE : + begin + rd_eop_o <= 0; + rd_sop_o <= 0; + wr_ready_o <= 0; + wr_full_o <= 0; + end + + endcase // case(state) + + // FIXME ignores step for now + + assign we_o = (state == WRITING) && wr_write_i; // FIXME potential critical path + // IF this is a timing problem, we could always write when in this state + assign en_o = ~((state==READING)& ~rd_read_i); // FIXME potential critical path + + assign done = (state == DONE); + assign error = (state == ERROR); + assign idle = (state == IDLE); +endmodule // buffer_int + +// Unused old code + //assign rd_empty_o = (state != READING); // && (state != PRE_READ); + //assign rd_empty_o = rd_empty_reg; // timing fix? + //assign rd_ready_o = (state == READING); + //assign rd_ready_o = ~rd_empty_reg; // timing fix? + + //wire rd_en = (state == PRE_READ) || ((state == READING) && rd_read_i); + //wire wr_en = (state == WRITING) && wr_write_i; // IF this is a timing problem, we could always enable when in this state + //assign en_o = rd_en | wr_en; + + // assign wr_full_o = (state != WRITING); + // assign wr_ready_o = (state == WRITING); + diff --git a/usrp2/fpga/control_lib/buffer_int_tb.v b/usrp2/fpga/control_lib/buffer_int_tb.v new file mode 100644 index 00000000..4fb5c671 --- /dev/null +++ b/usrp2/fpga/control_lib/buffer_int_tb.v @@ -0,0 +1,447 @@ + +module buffer_int_tb (); + + reg clk = 0; + reg rst = 1; + + initial #100 rst = 0; + always #5 clk = ~clk; + + wire en, we; + wire [8:0] addr; + wire [31:0] fifo2buf, buf2fifo; + + wire [31:0] rd_dat_o; + wire rd_sop_o, rd_eop_o; + reg rd_done_i = 0, rd_error_i = 0, rd_read_i = 0; + + reg [31:0] wr_dat_i = 0; + reg wr_write_i=0, wr_done_i = 0, wr_error_i = 0; + wire wr_ready_o, wr_full_o; + + reg clear = 0, write = 0, read = 0; + reg [8:0] firstline = 0, lastline = 0; + wire [3:0] step = 1; + wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline}; + reg go = 0; + wire done, error; + + buffer_int buffer_int + (.clk(clk),.rst(rst), + .ctrl_word(ctrl_word),.go(go), + .done(done),.error(error), + + // Buffer Interface + .en_o(en),.we_o(we),.addr_o(addr), + .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo), + + // Write FIFO Interface + .wr_dat_i(wr_dat_i), .wr_write_i(wr_write_i), .wr_done_i(wr_done_i), .wr_error_i(wr_error_i), + .wr_ready_o(wr_ready_o), .wr_full_o(wr_full_o), + + // Read FIFO Interface + .rd_dat_o(rd_dat_o), .rd_read_i(rd_read_i), .rd_done_i(rd_done_i), .rd_error_i(rd_error_i), + .rd_sop_o(rd_sop_o), .rd_eop_o(rd_eop_o) + ); + + reg ram_en = 0, ram_we = 0; + reg [8:0] ram_addr = 0; + reg [31:0] ram_data = 0; + + ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port + (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(), + .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) ); + + initial + begin + @(negedge rst); + @(posedge clk); + FillRAM; + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing full read, no wait states."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(6,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing full read, 2 wait states."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(6,2); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing full read, done ON the last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(5,2); + rd_done_i <= 1; + ReadALine; + rd_done_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 0 wait states, then nothing after last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(3,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 0 wait states, then done after last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(3,0); + rd_done_i <= 1; + @(posedge clk); + rd_done_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 0 wait states, then done at same time as last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(2,0); + rd_done_i <= 1; + ReadALine; + rd_done_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing partial read, 3 wait states, then error at same time as last."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(2,3); + rd_error_i <= 1; + ReadALine; + rd_error_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(5,10); + $display("Testing Reading too much, 3 wait states."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(9,3); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(500,511); + $display("Testing full read, to the end of the buffer."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(12,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,511); + $display("Testing full read, start to end of the buffer."); + while(!rd_sop_o) + @(posedge clk); + ReadLines(512,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(505,3); + $display("Testing full read, wraparound"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(11,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(10,15); + $display("Testing Full Write, no wait states"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,72); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(18,23); + $display("Testing Full Write, 1 wait states"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,101); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(27,40); + $display("Testing Partial Write, 0 wait states"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,201); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(35,200); + $display("Testing Partial Write, 0 wait states, then done"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,301); + wr_done_i <= 1; + @(posedge clk); + wr_done_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(45,200); + $display("Testing Partial Write, 0 wait states, then done and write simultaneously"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,301); + wr_done_i <= 1; + WriteALine(400); + wr_done_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(55,200); + $display("Testing Partial Write, 0 wait states, then error"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(6,0,501); + wr_error_i <= 1; + @(posedge clk); + wr_error_i <= 0; + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,82); + $display("Testing read after all the writes"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(83,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(508,4); + $display("Testing wraparound write"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(9,0,601); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(506,10); + $display("Reading wraparound write"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(17,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(0,511); + $display("Testing Whole Buffer write"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(512,0,1000); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,511); + $display("Reading Whole Buffer write"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(512,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(5,10); + $display("Testing Write Too Many"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(12,0,2000); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(0,15); + $display("Reading back Write Too Many"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(16,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferWrite(15,20); + $display("Testing Write One Less Than Full"); + while(!wr_ready_o) + @(posedge clk); + WriteLines(5,0,2000); + repeat (10) + @(posedge clk); + + ResetBuffer; + SetBufferRead(13,22); + $display("Reading back Write One Less Than Full"); + while(!rd_sop_o) + @(posedge clk); + ReadLines(10,0); + repeat (10) + @(posedge clk); + + ResetBuffer; + repeat(100) + @(posedge clk); + $finish; + end + + always @(posedge clk) + if(rd_read_i == 1'd1) + $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_dat_o, rd_sop_o, rd_eop_o); + + always @(posedge clk) + if(wr_write_i == 1'd1) + $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_dat_i, wr_ready_o, wr_full_o); + + initial begin + $dumpfile("buffer_int_tb.vcd"); + $dumpvars(0,buffer_int_tb); + end + + task FillRAM; + begin + ram_addr <= 0; + ram_data <= 0; + @(posedge clk); + ram_en <= 1; + ram_we <= 1; + @(posedge clk); + repeat (511) + begin + ram_addr <= ram_addr + 1; + ram_data <= ram_data + 1; + ram_en <= 1; + ram_we <= 1; + @(posedge clk); + end + ram_en <= 0; + ram_we <= 0; + @(posedge clk); + $display("Filled the RAM"); + end + endtask // FillRAM + + task ResetBuffer; + begin + clear <= 1; read <= 0; write <= 0; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Reset"); + end + endtask // ClearBuffer + + task SetBufferWrite; + input [8:0] start; + input [8:0] stop; + begin + clear <= 0; read <= 0; write <= 1; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Write"); + end + endtask // SetBufferWrite + + task SetBufferRead; + input [8:0] start; + input [8:0] stop; + begin + clear <= 0; read <= 1; write <= 0; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Read"); + end + endtask // SetBufferRead + + task ReadALine; + begin + #1 rd_read_i <= 1; + @(posedge clk); + rd_read_i <= 0; + end + endtask // ReadALine + + task ReadLines; + input [9:0] lines; + input [7:0] wait_states; + begin + $display("Read Lines: Number %d, Wait States %d",lines,wait_states); + repeat (lines) + begin + ReadALine; + repeat (wait_states) + @(posedge clk); + end + end + endtask // ReadLines + + task WriteALine; + input [31:0] value; + begin + #1 wr_write_i <= 1; + wr_dat_i <= value; + @(posedge clk); + wr_write_i <= 0; + end + endtask // WriteALine + + task WriteLines; + input [9:0] lines; + input [7:0] wait_states; + input [31:0] value; + begin + $display("Write Lines: Number %d, Wait States %d",lines,wait_states); + repeat(lines) + begin + value <= value + 1; + WriteALine(value); + repeat(wait_states) + @(posedge clk); + end + end + endtask // WriteLines + +endmodule // buffer_int_tb diff --git a/usrp2/fpga/control_lib/buffer_pool.v b/usrp2/fpga/control_lib/buffer_pool.v new file mode 100644 index 00000000..96929623 --- /dev/null +++ b/usrp2/fpga/control_lib/buffer_pool.v @@ -0,0 +1,323 @@ + +// Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer +// is a dual-ported RAM. Port A on each of them is indirectly connected +// to the wishbone bus by a bridge. Port B may be connected any one of the +// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected. The wishbone bus +// provides access to all 8 buffers, and also controls the connections +// between the ports and the buffers, allocating them as needed. + +// wb_adr is 16 bits -- +// bits 13:11 select which buffer +// bits 10:2 select line in buffer +// bits 1:0 are unused (32-bit access only) + +module buffer_pool + (input wb_clk_i, + input wb_rst_i, + input wb_we_i, + input wb_stb_i, + input [15:0] wb_adr_i, + input [31:0] wb_dat_i, + output [31:0] wb_dat_o, + output reg wb_ack_o, + output wb_err_o, + output wb_rty_o, + + input stream_clk, + input stream_rst, + + input set_stb, input [7:0] set_addr, input [31:0] set_data, + output [31:0] status, + output sys_int_o, + + output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3, + output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7, + + // Write Interfaces + input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, input wr0_error_i, output wr0_ready_o, output wr0_full_o, + input [31:0] wr1_dat_i, input wr1_write_i, input wr1_done_i, input wr1_error_i, output wr1_ready_o, output wr1_full_o, + input [31:0] wr2_dat_i, input wr2_write_i, input wr2_done_i, input wr2_error_i, output wr2_ready_o, output wr2_full_o, + input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, input wr3_error_i, output wr3_ready_o, output wr3_full_o, + + // Read Interfaces + output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, input rd0_error_i, output rd0_sop_o, output rd0_eop_o, + output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, input rd1_error_i, output rd1_sop_o, output rd1_eop_o, + output [31:0] rd2_dat_o, input rd2_read_i, input rd2_done_i, input rd2_error_i, output rd2_sop_o, output rd2_eop_o, + output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, input rd3_error_i, output rd3_sop_o, output rd3_eop_o + ); + + wire [7:0] sel_a; + + wire [2:0] which_buf = wb_adr_i[13:11]; // address 15:14 selects the buffer pool + wire [8:0] buf_addra = wb_adr_i[10:2]; // ignore address 1:0, 32-bit access only + + decoder_3_8 dec(.sel(which_buf),.res(sel_a)); + + genvar i; + + wire go; + + reg [2:0] port[0:7]; + reg [3:0] read_src[0:3]; + reg [3:0] write_src[0:3]; + + wire [7:0] done; + wire [7:0] error; + wire [7:0] idle; + + wire [31:0] buf_doa[0:7]; + + wire [7:0] buf_enb; + wire [7:0] buf_web; + wire [8:0] buf_addrb[0:7]; + wire [31:0] buf_dib[0:7]; + wire [31:0] buf_dob[0:7]; + + wire [31:0] wr_dat_i[0:7]; + wire [7:0] wr_write_i; + wire [7:0] wr_done_i; + wire [7:0] wr_error_i; + wire [7:0] wr_ready_o; + wire [7:0] wr_full_o; + + wire [31:0] rd_dat_o[0:7]; + wire [7:0] rd_read_i; + wire [7:0] rd_done_i; + wire [7:0] rd_error_i; + wire [7:0] rd_sop_o; + wire [7:0] rd_eop_o; + + assign status = {8'd0,idle[7:0],error[7:0],done[7:0]}; + + assign s0 = {23'd0,buf_addrb[0]}; + assign s1 = {23'd0,buf_addrb[1]}; + assign s2 = {23'd0,buf_addrb[2]}; + assign s3 = {23'd0,buf_addrb[3]}; + assign s4 = {23'd0,buf_addrb[4]}; + assign s5 = {23'd0,buf_addrb[5]}; + assign s6 = {23'd0,buf_addrb[6]}; + assign s7 = {23'd0,buf_addrb[7]}; + + wire [31:0] fifo_ctrl; + setting_reg #(.my_addr(64)) + sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data), + .out(fifo_ctrl),.changed(go)); + + integer k; + always @(posedge stream_clk) + if(stream_rst) + for(k=0;k<8;k=k+1) + port[k] <= 4; // disabled + else + for(k=0;k<8;k=k+1) + if(go & (fifo_ctrl[31:28]==k)) + port[k] <= fifo_ctrl[27:25]; + + always @(posedge stream_clk) + if(stream_rst) + for(k=0;k<4;k=k+1) + read_src[k] <= 8; // disabled + else + for(k=0;k<4;k=k+1) + if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k)) + read_src[k] <= fifo_ctrl[31:28]; + + always @(posedge stream_clk) + if(stream_rst) + for(k=0;k<4;k=k+1) + write_src[k] <= 8; // disabled + else + for(k=0;k<4;k=k+1) + if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k)) + write_src[k] <= fifo_ctrl[31:28]; + + generate + for(i=0;i<8;i=i+1) + begin : gen_buffer + RAMB16_S36_S36 dpram + (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), + .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i), + .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0), + .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) ); + + /* ram_2port #(.DWIDTH(32),.AWIDTH(9)) buffer + (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i), + .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]), + .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]), + .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); */ + + buffer_int #(.BUFF_NUM(i)) fifo_int + (.clk(stream_clk),.rst(stream_rst), + .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)), + .done(done[i]),.error(error[i]),.idle(idle[i]), + .en_o(buf_enb[i]), + .we_o(buf_web[i]), + .addr_o(buf_addrb[i]), + .dat_to_buf(buf_dib[i]), + .dat_from_buf(buf_dob[i]), + .wr_dat_i(wr_dat_i[i]), + .wr_write_i(wr_write_i[i]), + .wr_done_i(wr_done_i[i]), + .wr_error_i(wr_error_i[i]), + .wr_ready_o(wr_ready_o[i]), + .wr_full_o(wr_full_o[i]), + .rd_dat_o(rd_dat_o[i]), + .rd_read_i(rd_read_i[i]), + .rd_done_i(rd_done_i[i]), + .rd_error_i(rd_error_i[i]), + .rd_sop_o(rd_sop_o[i]), + .rd_eop_o(rd_eop_o[i]) + ); + + // FIXME -- if it is a problem, maybe we don't need enables on these muxes + mux4 #(.WIDTH(32)) + mux4_dat_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_dat_i),.i1(wr1_dat_i), + .i2(wr2_dat_i),.i3(wr3_dat_i),.o(wr_dat_i[i])); + mux4 #(.WIDTH(1)) + mux4_write_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_write_i),.i1(wr1_write_i), + .i2(wr2_write_i),.i3(wr3_write_i),.o(wr_write_i[i])); + mux4 #(.WIDTH(1)) + mux4_wrdone_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_done_i),.i1(wr1_done_i), + .i2(wr2_done_i),.i3(wr3_done_i),.o(wr_done_i[i])); + mux4 #(.WIDTH(1)) + mux4_wrerror_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_error_i),.i1(wr1_error_i), + .i2(wr2_error_i),.i3(wr3_error_i),.o(wr_error_i[i])); + mux4 #(.WIDTH(1)) + mux4_read_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_read_i),.i1(rd1_read_i), + .i2(rd2_read_i),.i3(rd3_read_i),.o(rd_read_i[i])); + mux4 #(.WIDTH(1)) + mux4_rddone_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_done_i),.i1(rd1_done_i), + .i2(rd2_done_i),.i3(rd3_done_i),.o(rd_done_i[i])); + mux4 #(.WIDTH(1)) + mux4_rderror_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_error_i),.i1(rd1_error_i), + .i2(rd2_error_i),.i3(rd3_error_i),.o(rd_error_i[i])); + end // block: gen_buffer + endgenerate + + //---------------------------------------------------------------------- + // Wishbone Outputs + + // Use the following lines if ram output and mux can be made fast enough + + assign wb_err_o = 1'b0; // Unused for now + assign wb_rty_o = 1'b0; // Unused for now + + always @(posedge wb_clk_i) + wb_ack_o <= wb_stb_i & ~wb_ack_o; + assign wb_dat_o = buf_doa[which_buf]; + + // Use this if we can't make the RAM+MUX fast enough + // reg [31:0] wb_dat_o_reg; + // reg stb_d1; + + // always @(posedge wb_clk_i) + // begin + // wb_dat_o_reg <= buf_doa[which_buf]; + // stb_d1 <= wb_stb_i; + // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i); + // end + //assign wb_dat_o = wb_dat_o_reg; + + mux8 #(.WIDTH(1)) + mux8_wr_ready0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), + .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]), + .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr0_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr_full0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]), + .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]), + .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr0_full_o)); + + mux8 #(.WIDTH(1)) + mux8_wr_ready1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), + .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]), + .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr1_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr_full1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]), + .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]), + .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr1_full_o)); + + mux8 #(.WIDTH(1)) + mux8_wr_ready2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), + .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]), + .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr2_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr_full2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]), + .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]), + .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr2_full_o)); + + mux8 #(.WIDTH(1)) + mux8_wr_ready3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), + .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]), + .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr3_ready_o)); + + mux8 #(.WIDTH(1)) + mux8_wr_full3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]), + .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]), + .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr3_full_o)); + + mux8 #(.WIDTH(1)) + mux8_rd_sop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]), + .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]), + .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd0_sop_o)); + + mux8 #(.WIDTH(1)) + mux8_rd_eop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]), + .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]), + .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd0_eop_o)); + + mux8 #(.WIDTH(32)) + mux8_rd_dat_0 (.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]), + .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]), + .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd0_dat_o)); + + mux8 #(.WIDTH(1)) + mux8_rd_sop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]), + .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]), + .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd1_sop_o)); + + mux8 #(.WIDTH(1)) + mux8_rd_eop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]), + .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]), + .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd1_eop_o)); + + mux8 #(.WIDTH(32)) + mux8_rd_dat_1 (.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]), + .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]), + .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd1_dat_o)); + + mux8 #(.WIDTH(1)) + mux8_rd_sop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]), + .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]), + .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd2_sop_o)); + + mux8 #(.WIDTH(1)) + mux8_rd_eop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]), + .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]), + .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd2_eop_o)); + + mux8 #(.WIDTH(32)) + mux8_rd_dat_2 (.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]), + .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]), + .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd2_dat_o)); + + mux8 #(.WIDTH(1)) + mux8_rd_sop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]), + .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]), + .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd3_sop_o)); + + mux8 #(.WIDTH(1)) + mux8_rd_eop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]), + .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]), + .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd3_eop_o)); + + mux8 #(.WIDTH(32)) + mux8_rd_dat_3 (.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]), + .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]), + .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd3_dat_o)); + + assign sys_int_o = (|error) | (|done); + +endmodule // buffer_pool diff --git a/usrp2/fpga/control_lib/buffer_pool_tb.v b/usrp2/fpga/control_lib/buffer_pool_tb.v new file mode 100644 index 00000000..16741438 --- /dev/null +++ b/usrp2/fpga/control_lib/buffer_pool_tb.v @@ -0,0 +1,50 @@ + +module buffer_pool_tb(); + + wire wb_clk_i; + wire wb_rst_i; + wire wb_we_i; + wire wb_stb_i; + wire [15:0] wb_adr_i; + wire [31:0] wb_dat_i; + wire [31:0] wb_dat_o; + wire wb_ack_o; + wire wb_err_o; + wire wb_rty_o; + + wire stream_clk, stream_rst; + + wire set_stb; + wire [7:0] set_addr; + wire [31:0] set_data; + + wire [31:0] wr0_dat_i; + buffer_pool dut + (.wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wb_we_i(wb_we_i), + .wb_stb_i(wb_stb_i), + .wb_adr_i(wb_adr_i), + .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), + .wb_ack_o(wb_ack_o), + .wb_err_o(wb_err_o), + .wb_rty_o(wb_rty_o), + + .stream_clk(stream_clk), + .stream_rst(stream_rst), + + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + + .wr0_dat_i(wr0_dat_i), .wr0_write_i(), .wr0_done_i(), .wr0_error_i(), .wr0_ready_o(), .wr0_full_o(), + .wr1_dat_i(), .wr1_write_i(), .wr1_done_i(), .wr1_error_i(), .wr1_ready_o(), .wr1_full_o(), + .wr2_dat_i(), .wr2_write_i(), .wr2_done_i(), .wr2_error_i(), .wr2_ready_o(), .wr2_full_o(), + .wr3_dat_i(), .wr3_write_i(), .wr3_done_i(), .wr3_error_i(), .wr3_ready_o(), .wr3_full_o(), + + .rd0_dat_o(), .rd0_read_i(), .rd0_done_i(), .rd0_error_i(), .rd0_ready_o(), .rd0_empty_o(), + .rd1_dat_o(), .rd1_read_i(), .rd1_done_i(), .rd1_error_i(), .rd1_ready_o(), .rd1_empty_o(), + .rd2_dat_o(), .rd2_read_i(), .rd2_done_i(), .rd2_error_i(), .rd2_ready_o(), .rd2_empty_o(), + .rd3_dat_o(), .rd3_read_i(), .rd3_done_i(), .rd3_error_i(), .rd3_ready_o(), .rd3_empty_o() + ); + +endmodule // buffer_pool_tb diff --git a/usrp2/fpga/control_lib/cascadefifo.v b/usrp2/fpga/control_lib/cascadefifo.v new file mode 100644 index 00000000..c1a4ab33 --- /dev/null +++ b/usrp2/fpga/control_lib/cascadefifo.v @@ -0,0 +1,50 @@ + + +// This FIFO exists to provide an intermediate point for the data on its +// long trek from one RAM (in the buffer pool) to another (in the longfifo) +// The shortfifo is more flexible in its placement since it is based on +// distributed RAM +// This one should only be used on transmit side applications. I.e. tx_mac, tx_dsp, etc. +// Spartan 3's have slow routing.... +// If we REALLY need to, we could also do this on the output side, +// with for the receive side stuff + +module cascadefifo + #(parameter WIDTH=32, SIZE=9) + (input clk, input rst, + input [WIDTH-1:0] datain, + output [WIDTH-1:0] dataout, + input read, + input write, + input clear, + output full, + output empty, + output [15:0] space, + output [15:0] occupied); + + wire [WIDTH-1:0] data_int; + wire empty_int, full_int, transfer; + wire [4:0] short_space, short_occupied; + wire [15:0] long_space, long_occupied; + + shortfifo #(.WIDTH(WIDTH)) shortfifo + (.clk(clk),.rst(rst),.clear(clear), + .datain(datain), .write(write), .full(full), + .dataout(data_int), .read(transfer), .empty(empty_int), + .space(short_space),.occupied(short_occupied) ); + + longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo + (.clk(clk),.rst(rst),.clear(clear), + .datain(data_int), .write(transfer), .full(full_int), + .dataout(dataout), .read(read), .empty(empty), + .space(long_space),.occupied(long_occupied) ); + + assign transfer = ~empty_int & ~full_int; + + assign space = {11'b0,short_space} + long_space; + assign occupied = {11'b0,short_occupied} + long_occupied; + +endmodule // cascadefifo + + + diff --git a/usrp2/fpga/control_lib/cascadefifo2.v b/usrp2/fpga/control_lib/cascadefifo2.v new file mode 100644 index 00000000..984cc46e --- /dev/null +++ b/usrp2/fpga/control_lib/cascadefifo2.v @@ -0,0 +1,56 @@ + + +// This FIFO exists to provide an intermediate point for the data on its +// long trek from one RAM (in the buffer pool) to another (in the longfifo) +// The shortfifo is more flexible in its placement since it is based on +// distributed RAM + +// This one has the shortfifo on both the in and out sides. +module cascadefifo2 + #(parameter WIDTH=32, SIZE=9) + (input clk, input rst, + input [WIDTH-1:0] datain, + output [WIDTH-1:0] dataout, + input read, + input write, + input clear, + output full, + output empty, + output [15:0] space, + output [15:0] occupied); + + wire [WIDTH-1:0] data_int, data_int2; + wire empty_int, full_int, transfer; + wire empty_int2, full_int2, transfer2; + wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied; + wire [15:0] l_space, l_occupied; + + shortfifo #(.WIDTH(WIDTH)) shortfifo + (.clk(clk),.rst(rst),.clear(clear), + .datain(datain), .write(write), .full(full), + .dataout(data_int), .read(transfer), .empty(empty_int), + .space(s1_space),.occupied(s1_occupied) ); + + longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo + (.clk(clk),.rst(rst),.clear(clear), + .datain(data_int), .write(transfer), .full(full_int), + .dataout(data_int2), .read(transfer2), .empty(empty_int2), + .space(l_space),.occupied(l_occupied) ); + + shortfifo #(.WIDTH(WIDTH)) shortfifo2 + (.clk(clk),.rst(rst),.clear(clear), + .datain(data_int2), .write(transfer2), .full(full_int2), + .dataout(dataout), .read(read), .empty(empty), + .space(s2_space),.occupied(s2_occupied) ); + + assign transfer = ~empty_int & ~full_int; + assign transfer2 = ~empty_int2 & ~full_int2; + + assign space = {11'b0,s1_space} + {11'b0,s2_space} + l_space; + assign occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied; + +endmodule // cascadefifo2 + + + + diff --git a/usrp2/fpga/control_lib/clock_bootstrap_rom.v b/usrp2/fpga/control_lib/clock_bootstrap_rom.v new file mode 100644 index 00000000..46563db6 --- /dev/null +++ b/usrp2/fpga/control_lib/clock_bootstrap_rom.v @@ -0,0 +1,34 @@ + + +module clock_bootstrap_rom(input [15:0] addr, output [47:0] data); + + reg [47:0] rom [0:15]; + + //initial + // $readmemh("bootrom.mem", rom); + + assign data = rom[addr]; + + initial + begin + // First 16 bits are address, last 32 are data + // First 4 bits of address select which slave + rom[0] = 48'h0000_0C00_0F03; // Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds + rom[1] = 48'h1014_0000_0000; // SPI: Set Divider to div by 2 + rom[2] = 48'h1018_0000_0001; // SPI: Choose AD9510 + rom[3] = 48'h1010_0000_3418; // SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word + rom[4] = 48'h1000_0000_0010; // SPI: AD9510 A:0 D:10 Set up AD9510 SPI + rom[5] = 48'h1010_0000_3518; // SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word + rom[6] = 48'hffff_ffff_ffff; // terminate + rom[7] = 48'hffff_ffff_ffff; // terminate + rom[8] = 48'hffff_ffff_ffff; // terminate + rom[9] = 48'hffff_ffff_ffff; // terminate + rom[10] = 48'hffff_ffff_ffff; // terminate + rom[11] = 48'hffff_ffff_ffff; // terminate + rom[12] = 48'hffff_ffff_ffff; // terminate + rom[13] = 48'hffff_ffff_ffff; // terminate + rom[14] = 48'hffff_ffff_ffff; // terminate + rom[15] = 48'hffff_ffff_ffff; // terminate + end // initial begin + +endmodule // clock_bootstrap_rom diff --git a/usrp2/fpga/control_lib/clock_control.v b/usrp2/fpga/control_lib/clock_control.v new file mode 100644 index 00000000..1bbe6bd7 --- /dev/null +++ b/usrp2/fpga/control_lib/clock_control.v @@ -0,0 +1,115 @@ + + +// AD9510 Register Map (from datasheet Rev. A) + +/* INSTRUCTION word format (16 bits) + * 15 Read = 1, Write = 0 + * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream + * 12:0 Address + */ + +/* ADDR Contents Value (hex) + * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate + * 04 A Counter + * 05-06 B Counter + * 07-0A PLL Control + * 0B-0C R Divider + * 0D PLL Control + * 34-3A Fine Delay + * 3C-3F LVPECL Outs + * 40-43 LVDS/CMOS Outs + * 45 Clock select, power down + * 48-57 Dividers + * 58 Func and Sync + * 5A Update regs + */ + + +module clock_control + (input reset, + input aux_clk, // 25MHz, for before fpga clock is active + input clk_fpga, // real 100 MHz FPGA clock + output [1:0] clk_en, // controls source of reference clock + output [1:0] clk_sel, // controls source of reference clock + input clk_func, // FIXME needs to be some kind of out SYNC or reset to 9510 + input clk_status, // Monitor PLL or SYNC status + + output sen, // Enable for the AD9510 + output sclk, // FIXME these need to be shared + input sdi, + output sdo + ); + + wire read = 1'b0; // Always write for now + wire [1:0] w = 2'b00; // Always send 1 byte at a time + + assign clk_sel = 2'b00; // Both outputs from External Ref (SMA) + assign clk_en = 2'b11; // Both outputs enabled + + reg [20:0] addr_data; + + reg [5:0] entry; + reg start; + reg [7:0] counter; + reg [23:0] command; + + always @* + case(entry) + 6'd00 : addr_data = {13'h00,8'h10}; // Serial setup + 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution, everything on + 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels + 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1) + 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge Pump normal + 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current + 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar Div by 2, PLL On + 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits) + 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1 + 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det + 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR causes failure... + 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care + 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0 + 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5 + default : addr_data = {13'h5A,8'h01}; // Register Update + endcase // case(entry) + + wire [5:0] lastentry = 6'd15; + wire done = (counter == 8'd49); + + always @(posedge aux_clk) + if(reset) + begin + entry <= #1 6'd0; + start <= #1 1'b1; + end + else if(start) + start <= #1 1'b0; + else if(done && (entry + // reg [7:0] ram3 [0:(1<<(AWIDTH-2))-1]; + + // Port 1 + always @(posedge clk) + if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]]; + + always @(posedge clk) + if(we1_i & en1_i & sel1_i[3]) + ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24]; + always @(posedge clk) + if(we1_i & en1_i & sel1_i[2]) + ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16]; + always @(posedge clk) + if(we1_i & en1_i & sel1_i[1]) + ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8]; + always @(posedge clk) + if(we1_i & en1_i & sel1_i[0]) + ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0]; + + // Port 2 + always @(posedge clk) + if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]]; + always @(posedge clk) + if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]]; + + always @(posedge clk) + if(we2_i & en2_i & sel2_i[3]) + ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24]; + always @(posedge clk) + if(we2_i & en2_i & sel2_i[2]) + ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16]; + always @(posedge clk) + if(we2_i & en2_i & sel2_i[1]) + ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8]; + always @(posedge clk) + if(we2_i & en2_i & sel2_i[0]) + ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0]; + +endmodule // dpram32 + + diff --git a/usrp2/fpga/control_lib/extram_interface.v b/usrp2/fpga/control_lib/extram_interface.v new file mode 100644 index 00000000..7554592b --- /dev/null +++ b/usrp2/fpga/control_lib/extram_interface.v @@ -0,0 +1,53 @@ + +// Temporary buffer pool storage, mostly useful for pre-generated data streams or +// for making more space to juggle packets in case of eth frames coming out of order + +module extram_interface + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + // Buffer pool interfaces + input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o, + input rd_sop_i, input rd_eop_i, + output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o, + input wr_ready_i, input wr_full_i, + + // RAM Interface + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + input RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn ); + + // Command format -- + // Read/_Write , start address[17:0] + wire [18:0] cmd_in; + wire cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd; + wire empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd; + + // Dummy logic + assign RAM_OEn = 1; + + setting_reg #(.my_addr(0)) + sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(cmd_in),.changed(cmd_stb)); + + reg cmd_stb_d1; + always @(posedge clk) cmd_stb_d1 <= cmd_stb; + assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1; + assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1; + + shortfifo #(.WIDTH(19)) wr_cmd_fifo + (.clk(clk),.rst(rst),.clear(1'b0), + .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd), + .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) ); + + shortfifo #(.WIDTH(19)) rd_cmd_fifo + (.clk(clk),.rst(rst),.clear(1'b0), + .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd), + .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) ); + +endmodule // extram_interface diff --git a/usrp2/fpga/control_lib/fifo_2clock.v b/usrp2/fpga/control_lib/fifo_2clock.v new file mode 100644 index 00000000..6b1eb607 --- /dev/null +++ b/usrp2/fpga/control_lib/fifo_2clock.v @@ -0,0 +1,66 @@ + +module fifo_2clock + #(parameter DWIDTH=32, AWIDTH=9) + (input wclk, input [DWIDTH-1:0] datain, input write, output full, output reg [AWIDTH-1:0] level_wclk, + input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output reg [AWIDTH-1:0] level_rclk, + input arst); + + reg [AWIDTH-1:0] wr_addr, rd_addr; + wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk; + wire [AWIDTH-1:0] next_rd_addr; + wire enb_read; + + // Write side management + wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1; + always @(posedge wclk or posedge arst) + if(arst) + wr_addr <= 0; + else if(write) + wr_addr <= next_wr_addr; + assign full = (next_wr_addr == rd_addr_wclk); + + // RAM for data storage. Data out is registered, complicating the + // read side logic + ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram + (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(), + .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) ); + + // Read side management + reg data_valid; + assign empty = ~data_valid; + assign next_rd_addr = rd_addr + data_valid; + assign enb_read = read | ~data_valid; + + always @(posedge rclk or posedge arst) + if(arst) + rd_addr <= 0; + else if(read) + rd_addr <= rd_addr + 1; + + always @(posedge rclk or posedge arst) + if(arst) + data_valid <= 0; + else + if(read & (next_rd_addr == wr_addr_rclk)) + data_valid <= 0; + else if(next_rd_addr != wr_addr_rclk) + data_valid <= 1; + + // Send pointers across clock domains via gray code + gray_send #(.WIDTH(AWIDTH)) send_wr_addr + (.clk_in(wclk),.addr_in(wr_addr), + .clk_out(rclk),.addr_out(wr_addr_rclk) ); + + gray_send #(.WIDTH(AWIDTH)) send_rd_addr + (.clk_in(rclk),.addr_in(rd_addr), + .clk_out(wclk),.addr_out(rd_addr_wclk) ); + + // Generate fullness info, these are approximate and may be delayed + // and are only for higher-level flow control. + // Only full and empty are guaranteed exact. + always @(posedge wclk) + level_wclk <= wr_addr - rd_addr_wclk; + always @(posedge rclk) + level_rclk <= wr_addr_rclk - rd_addr; + +endmodule // fifo_2clock diff --git a/usrp2/fpga/control_lib/fifo_2clock_casc.v b/usrp2/fpga/control_lib/fifo_2clock_casc.v new file mode 100644 index 00000000..e9b0cfc2 --- /dev/null +++ b/usrp2/fpga/control_lib/fifo_2clock_casc.v @@ -0,0 +1,31 @@ + +module fifo_2clock_casc + #(parameter DWIDTH=32, AWIDTH=9) + (input wclk, input [DWIDTH-1:0] datain, input write, output full, output [AWIDTH-1:0] level_wclk, + input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output [AWIDTH-1:0] level_rclk, + input arst); + + wire full_int, empty_int, full_int2, empty_int2, transfer, transfer2; + wire [DWIDTH-1:0] data_int, data_int2; + + shortfifo #(.WIDTH(DWIDTH)) shortfifo + (.clk(wclk), .rst(arst), .clear(0), + .datain(datain), .write(write), .full(full), + .dataout(data_int), .read(transfer), .empty(empty_int) ); + + assign transfer = ~full_int & ~empty_int; + + fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock + (.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int), .level_wclk(level_wclk), + .rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2), .level_rclk(level_rclk), + .arst(arst) ); + + assign transfer2 = ~full_int2 & ~empty_int2; + + shortfifo #(.WIDTH(DWIDTH)) shortfifo2 + (.clk(rclk), .rst(arst), .clear(0), + .datain(data_int2), .write(transfer2), .full(full_int2), + .dataout(dataout), .read(read), .empty(empty) ); + +endmodule // fifo_2clock_casc + diff --git a/usrp2/fpga/control_lib/fifo_reader.v b/usrp2/fpga/control_lib/fifo_reader.v new file mode 100644 index 00000000..49d05b1a --- /dev/null +++ b/usrp2/fpga/control_lib/fifo_reader.v @@ -0,0 +1,28 @@ + +module fifo_reader + #(parameter rate=4) + (input clk, + input [31:0] data_in, + output read_o + input ready_i, + input done_i + ); + + reg [7:0] state = 0; + + always @(posedge clk) + if(ready) + if(state == rate) + state <= 0; + else + state <= state + 1; + else + state <= 0; + + assign read = (state == rate); + + initial $monitor(data_in); + +endmodule // fifo_reader + + diff --git a/usrp2/fpga/control_lib/fifo_tb.v b/usrp2/fpga/control_lib/fifo_tb.v new file mode 100644 index 00000000..136ed011 --- /dev/null +++ b/usrp2/fpga/control_lib/fifo_tb.v @@ -0,0 +1,153 @@ +module fifo_tb(); + + reg clk, rst; + wire short_full, short_empty, long_full, long_empty; + wire casc_full, casc_empty, casc2_full, casc2_empty; + reg read, write; + + wire [7:0] short_do, long_do; + wire [7:0] casc_do, casc2_do; + reg [7:0] di; + + reg clear = 0; + + shortfifo #(.WIDTH(8)) shortfifo + (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear), + .read(read),.write(write),.full(short_full),.empty(short_empty)); + + longfifo #(.WIDTH(8), .SIZE(4)) longfifo + (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear), + .read(read),.write(write),.full(long_full),.empty(long_empty)); + + cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo + (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear), + .read(read),.write(write),.full(casc_full),.empty(casc_empty)); + + cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2 + (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear), + .read(read),.write(write),.full(casc2_full),.empty(casc2_empty)); + + initial rst = 1; + initial #1000 rst = 0; + initial clk = 0; + always #50 clk = ~clk; + + initial di = 8'hAE; + initial read = 0; + initial write = 0; + + always @(posedge clk) + if(write) + di <= di + 1; + + always @(posedge clk) + begin + if(short_full != long_full) + $display("Error: FULL mismatch"); + if(short_empty != long_empty) + $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)"); + if(read & (short_do != long_do)) + $display("Error: DATA mismatch"); + end + + initial $dumpfile("fifo_tb.vcd"); + initial $dumpvars(0,fifo_tb); + + initial + begin + @(negedge rst); + @(posedge clk); + repeat (10) + @(posedge clk); + write <= 1; + @(posedge clk); + write <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + read <= 1; + @(posedge clk); + read <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + + repeat(10) + begin + write <= 1; + @(posedge clk); + write <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + read <= 1; + @(posedge clk); + read <= 0; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + end // repeat (10) + + write <= 1; + repeat (4) + @(posedge clk); + write <= 0; + @(posedge clk); + read <= 1; + repeat (4) + @(posedge clk); + read <= 0; + @(posedge clk); + + + write <= 1; + repeat (4) + @(posedge clk); + write <= 0; + @(posedge clk); + repeat (4) + begin + read <= 1; + @(posedge clk); + read <= 0; + @(posedge clk); + end + + write <= 1; + @(posedge clk); + @(posedge clk); + read <= 1; + repeat (5) + @(posedge clk); + write <= 0; + @(posedge clk); + @(posedge clk); + read <= 0; + @(posedge clk); + + write <= 1; + repeat (16) + @(posedge clk); + write <= 0; + @(posedge clk); + + read <= 1; + repeat (16) + @(posedge clk); + read <= 0; + @(posedge clk); + + repeat (10) + @(posedge clk); + $finish; + end +endmodule // longfifo_tb diff --git a/usrp2/fpga/control_lib/fifo_writer.v b/usrp2/fpga/control_lib/fifo_writer.v new file mode 100644 index 00000000..064ad3cb --- /dev/null +++ b/usrp2/fpga/control_lib/fifo_writer.v @@ -0,0 +1,31 @@ + +module fifo_writer + #(parameter rate=4) + (input clk, + output [31:0] data_out, + output write_o, + input ready_i, + input done_i + ); + + reg [7:0] state = 0; + + + // FIXME change this to write + always @(posedge clk) + if(ready) + if(state == rate) + state <= 0; + else + state <= state + 1; + else + state <= 0; + + assign read = (state == rate); + + initial $monitor(data_in); + +endmodule // fifo_writer + + + diff --git a/usrp2/fpga/control_lib/gray2bin.v b/usrp2/fpga/control_lib/gray2bin.v new file mode 100644 index 00000000..5df40bd5 --- /dev/null +++ b/usrp2/fpga/control_lib/gray2bin.v @@ -0,0 +1,13 @@ + + +module gray2bin + #(parameter WIDTH=8) + (input [WIDTH-1:0] gray, + output reg [WIDTH-1:0] bin); + + integer i; + always @(gray) + for(i = 0;i>i); + +endmodule // gray2bin diff --git a/usrp2/fpga/control_lib/gray_send.v b/usrp2/fpga/control_lib/gray_send.v new file mode 100644 index 00000000..7fc07d40 --- /dev/null +++ b/usrp2/fpga/control_lib/gray_send.v @@ -0,0 +1,29 @@ + + + +module gray_send + #(parameter WIDTH = 8) + (input clk_in, input [WIDTH-1:0] addr_in, + input clk_out, output reg [WIDTH-1:0] addr_out); + + reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1; + wire [WIDTH-1:0] gray, bin; + + bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) ); + + always @(posedge clk_in) + gray_clkin <= gray; + + always @(posedge clk_out) + gray_clkout <= gray_clkin; + + always @(posedge clk_out) + gray_clkout_d1 <= gray_clkout; + + gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) ); + + // FIXME we may not need the next register, but it may help timing + always @(posedge clk_out) + addr_out <= bin; + +endmodule // gray_send diff --git a/usrp2/fpga/control_lib/icache.v b/usrp2/fpga/control_lib/icache.v new file mode 100644 index 00000000..dd93c88e --- /dev/null +++ b/usrp2/fpga/control_lib/icache.v @@ -0,0 +1,134 @@ + +module icache + #(parameter AWIDTH=14, + parameter CWIDTH=6) + + (input wb_clk_i, + input wb_rst_i, + input [AWIDTH-1:0] iwb_adr_i, + input iwb_stb_i, + output [31:0] iwb_dat_o, + output iwb_ack_o, + input [31:0] iram_dat_i, + output [AWIDTH-1:0] iram_adr_o, + output iram_en_o ); + + localparam TAGWIDTH = AWIDTH-CWIDTH-2; + reg stb_d1, ack_d1, miss_d1; + reg [AWIDTH-1:0] held_addr; + reg [31:0] idata [0:(1<>1)); + wire latch_dat = (clk_ctr == (clk_div - 8'd2)); + wire send_clk_lo = (clk_ctr == (clk_div - 8'd1)); + + wire send_bit = (bit_ready && (bit_ctr != 0)); + assign ready = (bit_ctr == 0); + + always @(posedge clk) + if(rst) + clk_ctr <= 0; + else if(bit_done) + clk_ctr <= 0; + else if(bit_busy) + clk_ctr <= clk_ctr + 1; + else if(send_bit) + clk_ctr <= 1; + + always @(posedge clk) + if(rst) + sd_clk <= 0; + else if(send_clk_hi) + sd_clk <= 1; + else if(send_clk_lo) + sd_clk <= 0; + + always @(posedge clk) + if(rst) + bit_ctr <= 0; + else if(bit_done) + if(bit_ctr == 4'd8) + bit_ctr <= 0; + else + bit_ctr <= bit_ctr + 1; + else if(bit_ready & go) + bit_ctr <= 1; + + reg [7:0] shift_reg; + always @(posedge clk) + if(go) + shift_reg <= send_dat; + else if(latch_dat) + shift_reg <= {shift_reg[6:0],sd_miso}; + + assign sd_mosi = shift_reg[7]; + assign rcv_dat = shift_reg; + +endmodule // sd_spi diff --git a/usrp2/fpga/control_lib/sd_spi_tb.v b/usrp2/fpga/control_lib/sd_spi_tb.v new file mode 100644 index 00000000..e30a5bdf --- /dev/null +++ b/usrp2/fpga/control_lib/sd_spi_tb.v @@ -0,0 +1,40 @@ + + +module sd_spi_tb; + + reg clk = 0; + always #5 clk = ~clk; + reg rst = 1; + initial #32 rst = 0; + + wire sd_clk, sd_mosi, sd_miso; + wire [7:0] clk_div = 12; + wire [7:0] send_dat = 23; + wire [7:0] rcv_dat; + + wire ready; + reg go = 0; + initial + begin + repeat (100) + @(posedge clk); + go <= 1; + @(posedge clk); + go <= 0; + end + + sd_spi dut(.clk(clk),.rst(rst), + .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat), + .go(go),.ready(ready) ); + + initial + begin + $dumpfile("sd_spi_tb.vcd"); + $dumpvars(0,sd_spi_tb); + end + + initial + #10000 $finish(); + +endmodule // sd_spi_tb diff --git a/usrp2/fpga/control_lib/sd_spi_wb.v b/usrp2/fpga/control_lib/sd_spi_wb.v new file mode 100644 index 00000000..53036d36 --- /dev/null +++ b/usrp2/fpga/control_lib/sd_spi_wb.v @@ -0,0 +1,66 @@ + +// Wishbone module for spi communications with an SD Card +// The programming interface is simple -- +// Write the desired clock divider to address 1 (should be 1 or higher) +// Status is in address 0. A 1 indicates the last transaction is done and it is safe to +// send another +// Writing a byte to address 2 sends that byte over SPI. When it is done, +// status (addr 0) goes high again, and the received byte can be read from address 3. + +module sd_spi_wb + (input clk, + input rst, + + // SD Card interface + output sd_clk, + output sd_csn, + output sd_mosi, + input sd_miso, + + input wb_cyc_i, + input wb_stb_i, + input wb_we_i, + input [1:0] wb_adr_i, + input [7:0] wb_dat_i, + output reg [7:0] wb_dat_o, + output reg wb_ack_o); + + localparam ADDR_STATUS = 0; + localparam ADDR_CLKDIV = 1; + localparam ADDR_WRITE = 2; + localparam ADDR_READ = 3; + + wire [7:0] status, rcv_dat; + reg [7:0] clkdiv; + wire ready; + reg ack_d1; + always @(posedge clk) + if(rst) ack_d1 <= 0; + else ack_d1 <= wb_ack_o; + + always @(posedge clk) + if(rst) wb_ack_o <= 0; + else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1; + + always @(posedge clk) + case(wb_adr_i) + ADDR_STATUS : wb_dat_o <= {7'd0,ready}; + ADDR_CLKDIV : wb_dat_o <= clkdiv; + ADDR_READ : wb_dat_o <= rcv_dat; + default : wb_dat_o <= 0; + endcase // case(wb_adr_i) + + always @(posedge clk) + if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o) + case(wb_adr_i) + ADDR_CLKDIV : clkdiv <= wb_dat_i; + endcase // case(wb_adr_i) + + wire go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE); + + sd_spi sd_spi(.clk(clk),.rst(rst), + .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), + .clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat), + .go(go),.ready(ready) ); + +endmodule // sd_spi_wb diff --git a/usrp2/fpga/control_lib/setting_reg.v b/usrp2/fpga/control_lib/setting_reg.v new file mode 100644 index 00000000..ccbaa3d2 --- /dev/null +++ b/usrp2/fpga/control_lib/setting_reg.v @@ -0,0 +1,23 @@ + + +module setting_reg + #(parameter my_addr = 0) + (input clk, input rst, input strobe, input wire [7:0] addr, + input wire [31:0] in, output reg [31:0] out, output reg changed); + + always @(posedge clk) + if(rst) + begin + out <= 32'd0; + changed <= 1'b0; + end + else + if(strobe & (my_addr==addr)) + begin + out <= in; + changed <= 1'b1; + end + else + changed <= 1'b0; + +endmodule // setting_reg diff --git a/usrp2/fpga/control_lib/settings_bus.v b/usrp2/fpga/control_lib/settings_bus.v new file mode 100644 index 00000000..d01a30ab --- /dev/null +++ b/usrp2/fpga/control_lib/settings_bus.v @@ -0,0 +1,49 @@ + +// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock + +module settings_bus + #(parameter AWIDTH=16, parameter DWIDTH=32) + (input wb_clk, + input wb_rst, + input [AWIDTH-1:0] wb_adr_i, + input [DWIDTH-1:0] wb_dat_i, + input wb_stb_i, + input wb_we_i, + output reg wb_ack_o, + input sys_clk, + output strobe, + output reg [7:0] addr, + output reg [31:0] data); + + reg stb_int, stb_int_d1; + + always @(posedge wb_clk) + if(wb_rst) + begin + stb_int <= 1'b0; + addr <= 8'd0; + data <= 32'd0; + end + else if(wb_we_i & wb_stb_i) + begin + stb_int <= 1'b1; + addr <= wb_adr_i[9:2]; + data <= wb_dat_i; + end + else + stb_int <= 1'b0; + + always @(posedge wb_clk) + if(wb_rst) + wb_ack_o <= 0; + else + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + always @(posedge wb_clk) + stb_int_d1 <= stb_int; + + //assign strobe = stb_int & ~stb_int_d1; + assign strobe = stb_int & wb_ack_o; + +endmodule // settings_bus + diff --git a/usrp2/fpga/control_lib/shortfifo.v b/usrp2/fpga/control_lib/shortfifo.v new file mode 100644 index 00000000..83d2c198 --- /dev/null +++ b/usrp2/fpga/control_lib/shortfifo.v @@ -0,0 +1,63 @@ + +module shortfifo + #(parameter WIDTH=32) + (input clk, input rst, + input [WIDTH-1:0] datain, + output [WIDTH-1:0] dataout, + input read, + input write, + input clear, + output reg full, + output reg empty, + output [4:0] space, + output [4:0] occupied); + + reg [3:0] a; + genvar i; + + generate + for (i=0;i>1); + wire stop_now = (bit_ctr == 10) && shift_now; + wire go_now = (bit_ctr == 0) && neg_trans; + + always @(posedge clk) + if(rst) + sr <= 0; + else if(shift_now) + sr <= {rx_d2,sr[7:1]}; + + always @(posedge clk) + if(rst) + baud_ctr <= 0; + else + if(go_now) + baud_ctr <= 1; + else if(stop_now) + baud_ctr <= 0; + else if(baud_ctr >= clkdiv) + baud_ctr <= 1; + else if(baud_ctr != 0) + baud_ctr <= baud_ctr + 1; + + always @(posedge clk) + if(rst) + bit_ctr <= 0; + else + if(go_now) + bit_ctr <= 1; + else if(stop_now) + bit_ctr <= 0; + else if(baud_ctr == clkdiv) + bit_ctr <= bit_ctr + 1; + + wire full; + wire write = ~full & rx_d2 & stop_now; + + medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo + (.clk(clk),.rst(rst), + .datain(sr),.write(write),.full(full), + .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty), + .clear(0),.space(),.occupied(fifo_level) ); + +endmodule // simple_uart_rx diff --git a/usrp2/fpga/control_lib/simple_uart_tx.v b/usrp2/fpga/control_lib/simple_uart_tx.v new file mode 100644 index 00000000..e11a347e --- /dev/null +++ b/usrp2/fpga/control_lib/simple_uart_tx.v @@ -0,0 +1,60 @@ + +module simple_uart_tx + #(parameter DEPTH=0) + (input clk, input rst, + input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output fifo_full, + input [15:0] clkdiv, output baudclk, output reg tx); + + reg [15:0] baud_ctr; + reg [3:0] bit_ctr; + + wire read, empty; + wire [7:0] char_to_send; + + medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo + (.clk(clk),.rst(rst), + .datain(fifo_in),.write(fifo_write),.full(fifo_full), + .dataout(char_to_send),.read(read),.empty(empty), + .clear(0),.space(fifo_level),.occupied() ); + + always @(posedge clk) + if(rst) + baud_ctr <= 0; + else if (baud_ctr >= clkdiv) + baud_ctr <= 0; + else + baud_ctr <= baud_ctr + 1; + + always @(posedge clk) + if(rst) + bit_ctr <= 0; + else if(baud_ctr == clkdiv) + if(bit_ctr == 9) + bit_ctr <= 0; + else if(bit_ctr != 0) + bit_ctr <= bit_ctr + 1; + else if(~empty) + bit_ctr <= 1; + + always @(posedge clk) + if(rst) + tx <= 1; + else + case(bit_ctr) + 0 : tx <= 1; + 1 : tx <= 0; + 2 : tx <= char_to_send[0]; + 3 : tx <= char_to_send[1]; + 4 : tx <= char_to_send[2]; + 5 : tx <= char_to_send[3]; + 6 : tx <= char_to_send[4]; + 7 : tx <= char_to_send[5]; + 8 : tx <= char_to_send[6]; + 9 : tx <= char_to_send[7]; + default : tx <= 1; + endcase // case(bit_ctr) + + assign read = (bit_ctr == 9) && (baud_ctr == clkdiv); + assign baudclk = (baud_ctr == 1); // Only for debug purposes + +endmodule // simple_uart_tx diff --git a/usrp2/fpga/control_lib/spi.v b/usrp2/fpga/control_lib/spi.v new file mode 100644 index 00000000..a80c488e --- /dev/null +++ b/usrp2/fpga/control_lib/spi.v @@ -0,0 +1,84 @@ + + +// AD9510 Register Map (from datasheet Rev. A) + +/* INSTRUCTION word format (16 bits) + * 15 Read = 1, Write = 0 + * 14:13 W1/W0, Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream + * 12:0 Address + */ + +/* ADDR Contents Value (hex) + * 00 Serial Config Port 10 (def) -- MSB first, SDI/SDO separate + * 04 A Counter + * 05-06 B Counter + * 07-0A PLL Control + * 0B-0C R Divider + * 0D PLL Control + * 34-3A Fine Delay + * 3C-3F LVPECL Outs + * 40-43 LVDS/CMOS Outs + * 45 Clock select, power down + * 48-57 Dividers + * 58 Func and Sync + * 5A Update regs + */ + + +module spi + (input reset, + input clk, + + // SPI signals + output sen, + output sclk, + input sdi, + output sdo, + + // Interfaces + input read_1, + input write_1, + input [15:0] command_1, + input [15:0] wdata_1, + output [15:0] rdata_1, + output reg done_1, + input msb_first_1, + input [5:0] command_width_1, + input [5:0] data_width_1, + input [7:0] clkdiv_1 + + ); + + reg [15:0] command, wdata, rdata; + reg done; + + always @(posedge clk) + if(reset) + done_1 <= #1 1'b0; + + always @(posedge clk) + if(reset) + begin + counter <= #1 7'd0; + command <= #1 20'd0; + end + else if(start) + begin + counter <= #1 7'd1; + command <= #1 {read,w,addr_data}; + end + else if( |counter && ~done ) + begin + counter <= #1 counter + 7'd1; + if(~counter[0]) + command <= {command[22:0],1'b0}; + end + + wire done = (counter == 8'd49); + + assign sen = (done | counter == 8'd0); // CSB is high when we're not doing anything + assign sclk = ~counter[0]; + assign sdo = command[23]; + + +endmodule // clock_control diff --git a/usrp2/fpga/control_lib/srl.v b/usrp2/fpga/control_lib/srl.v new file mode 100644 index 00000000..fa28c766 --- /dev/null +++ b/usrp2/fpga/control_lib/srl.v @@ -0,0 +1,21 @@ + +module srl + #(parameter WIDTH=18) + (input clk, + input write, + input [WIDTH-1:0] in, + input [3:0] addr, + output [WIDTH-1:0] out); + + genvar i; + generate + for (i=0;i 5) + clock_present <= 1; + else + ; + else + if(abs_diff<3) + clock_present <= 0; + else + rd_counter <= rd_counter + 1; + +endmodule // ss_rcvr diff --git a/usrp2/fpga/control_lib/system_control.v b/usrp2/fpga/control_lib/system_control.v new file mode 100644 index 00000000..5d89f13d --- /dev/null +++ b/usrp2/fpga/control_lib/system_control.v @@ -0,0 +1,47 @@ +// System bootup order: +// 0 - Internal POR to reset this block. Maybe control it from CPLD in the future? +// 1 - Everything in reset +// 2 - Take RAM Loader out of reset +// 3 - When RAM Loader done, take processor and wishbone out of reset + +module system_control + (input wb_clk_i, + output reg ram_loader_rst_o, + output reg wb_rst_o, + input ram_loader_done_i + ); + + reg POR = 1'b1; + reg [3:0] POR_ctr; + + initial POR_ctr = 4'd0; + always @(posedge wb_clk_i) + if(POR_ctr == 4'd15) + POR <= 1'b0; + else + POR_ctr <= POR_ctr + 4'd1; + + always @(posedge POR or posedge wb_clk_i) + if(POR) + ram_loader_rst_o <= 1'b1; + else + ram_loader_rst_o <= #1 1'b0; + + // Main system reset + reg delayed_rst; + + always @(posedge POR or posedge wb_clk_i) + if(POR) + begin + wb_rst_o <= 1'b1; + delayed_rst <= 1'b1; + end + else if(ram_loader_done_i) + begin + delayed_rst <= 1'b0; + wb_rst_o <= delayed_rst; + end + +endmodule // system_control + + diff --git a/usrp2/fpga/control_lib/system_control_tb.v b/usrp2/fpga/control_lib/system_control_tb.v new file mode 100644 index 00000000..a8eff481 --- /dev/null +++ b/usrp2/fpga/control_lib/system_control_tb.v @@ -0,0 +1,57 @@ + + +module system_control_tb(); + + reg aux_clk, clk_fpga; + wire wb_clk, dsp_clk; + wire wb_rst, dsp_rst, rl_rst, proc_rst; + + reg rl_done, clock_ready; + + initial aux_clk = 1'b0; + always #25 aux_clk = ~aux_clk; + + initial clk_fpga = 1'b0; + + initial clock_ready = 1'b0; + initial + begin + @(negedge proc_rst); + #1003 clock_ready <= 1'b1; + end + + always #7 clk_fpga = ~clk_fpga; + + initial begin + $dumpfile("system_control_tb.vcd"); + $dumpvars(0,system_control_tb); + end + + initial #10000 $finish; + + initial + begin + @(negedge rl_rst); + rl_done <= 1'b0; + #1325 rl_done <= 1'b1; + end + + initial + begin + @(negedge proc_rst); + clock_ready <= 1'b0; + #327 clock_ready <= 1'b1; + end + + system_control + system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga), + .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk), + .ram_loader_rst_o(rl_rst), + .processor_rst_o(proc_rst), + .wb_rst_o(wb_rst), + .dsp_rst_o(dsp_rst), + .ram_loader_done_i(rl_done), + .clock_ready_i(clock_ready), + .debug_o()); + +endmodule // system_control_tb diff --git a/usrp2/fpga/control_lib/traffic_cop.v b/usrp2/fpga/control_lib/traffic_cop.v new file mode 100644 index 00000000..e7579656 --- /dev/null +++ b/usrp2/fpga/control_lib/traffic_cop.v @@ -0,0 +1,25 @@ + +module traffic_cop(); + + +endmodule // traffic_cop + + + +/* + + Traffic Cop to control buffer pool + + Inputs + + Commands + + Basic Operations + + Outputs + + + + + + */ diff --git a/usrp2/fpga/control_lib/wb_1master.v b/usrp2/fpga/control_lib/wb_1master.v new file mode 100644 index 00000000..e56ba1fb --- /dev/null +++ b/usrp2/fpga/control_lib/wb_1master.v @@ -0,0 +1,430 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Bus Top Level //// +//// //// +//// //// +//// Original Author: Johny Chi //// +//// chisuhua@yahoo.com.cn //// +//// Modified By Matt Ettus, matt@ettus.com //// +//// //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Up to 8 slaves share a Wishbone Bus connection to 1 master + + module wb_1master + #(parameter s0_addr_w = 4, // slave 0 address decode width + parameter s0_addr = 4'h0, // slave 0 address + parameter s1_addr_w = 4 , // slave 1 address decode width + parameter s1_addr = 4'h1, // slave 1 address + parameter s215_addr_w = 8 , // slave 2 to slave 7 address decode width + parameter s2_addr = 8'h92, // slave 2 address + parameter s3_addr = 8'h93, // slave 3 address + parameter s4_addr = 8'h94, // slave 4 address + parameter s5_addr = 8'h95, // slave 5 address + parameter s6_addr = 8'h96, // slave 6 address + parameter s7_addr = 8'h97, // slave 7 address + parameter s8_addr = 8'h98, // slave 7 address + parameter s9_addr = 8'h99, // slave 7 address + parameter s10_addr = 8'h9a, // slave 7 address + parameter s11_addr = 8'h9b, // slave 7 address + parameter s12_addr = 8'h9c, // slave 7 address + parameter s13_addr = 8'h9d, // slave 7 address + parameter s14_addr = 8'h9e, // slave 7 address + parameter s15_addr = 8'h9f, // slave 7 address + + parameter dw = 32, // Data bus Width + parameter aw = 32, // Address bus Width + parameter sw = 4) // Number of Select Lines + + (input clk_i, + input rst_i, + + // Master Interface + input [dw-1:0] m0_dat_i, + output [dw-1:0] m0_dat_o, + input [aw-1:0] m0_adr_i, + input [sw-1:0] m0_sel_i, + input m0_we_i, + input m0_cyc_i, + input m0_stb_i, + output m0_ack_o, + output m0_err_o, + output m0_rty_o, + + // Slave Interfaces + input [dw-1:0] s0_dat_i, + output [dw-1:0] s0_dat_o, + output [aw-1:0] s0_adr_o, + output [sw-1:0] s0_sel_o, + output s0_we_o, + output s0_cyc_o, + output s0_stb_o, + input s0_ack_i, + input s0_err_i, + input s0_rty_i, + + input [dw-1:0] s1_dat_i, + output [dw-1:0] s1_dat_o, + output [aw-1:0] s1_adr_o, + output [sw-1:0] s1_sel_o, + output s1_we_o, + output s1_cyc_o, + output s1_stb_o, + input s1_ack_i, + input s1_err_i, + input s1_rty_i, + + input [dw-1:0] s2_dat_i, + output [dw-1:0] s2_dat_o, + output [aw-1:0] s2_adr_o, + output [sw-1:0] s2_sel_o, + output s2_we_o, + output s2_cyc_o, + output s2_stb_o, + input s2_ack_i, + input s2_err_i, + input s2_rty_i, + + input [dw-1:0] s3_dat_i, + output [dw-1:0] s3_dat_o, + output [aw-1:0] s3_adr_o, + output [sw-1:0] s3_sel_o, + output s3_we_o, + output s3_cyc_o, + output s3_stb_o, + input s3_ack_i, + input s3_err_i, + input s3_rty_i, + + input [dw-1:0] s4_dat_i, + output [dw-1:0] s4_dat_o, + output [aw-1:0] s4_adr_o, + output [sw-1:0] s4_sel_o, + output s4_we_o, + output s4_cyc_o, + output s4_stb_o, + input s4_ack_i, + input s4_err_i, + input s4_rty_i, + + input [dw-1:0] s5_dat_i, + output [dw-1:0] s5_dat_o, + output [aw-1:0] s5_adr_o, + output [sw-1:0] s5_sel_o, + output s5_we_o, + output s5_cyc_o, + output s5_stb_o, + input s5_ack_i, + input s5_err_i, + input s5_rty_i, + + input [dw-1:0] s6_dat_i, + output [dw-1:0] s6_dat_o, + output [aw-1:0] s6_adr_o, + output [sw-1:0] s6_sel_o, + output s6_we_o, + output s6_cyc_o, + output s6_stb_o, + input s6_ack_i, + input s6_err_i, + input s6_rty_i, + + input [dw-1:0] s7_dat_i, + output [dw-1:0] s7_dat_o, + output [aw-1:0] s7_adr_o, + output [sw-1:0] s7_sel_o, + output s7_we_o, + output s7_cyc_o, + output s7_stb_o, + input s7_ack_i, + input s7_err_i, + input s7_rty_i, + + input [dw-1:0] s8_dat_i, + output [dw-1:0] s8_dat_o, + output [aw-1:0] s8_adr_o, + output [sw-1:0] s8_sel_o, + output s8_we_o, + output s8_cyc_o, + output s8_stb_o, + input s8_ack_i, + input s8_err_i, + input s8_rty_i, + + input [dw-1:0] s9_dat_i, + output [dw-1:0] s9_dat_o, + output [aw-1:0] s9_adr_o, + output [sw-1:0] s9_sel_o, + output s9_we_o, + output s9_cyc_o, + output s9_stb_o, + input s9_ack_i, + input s9_err_i, + input s9_rty_i, + + input [dw-1:0] s10_dat_i, + output [dw-1:0] s10_dat_o, + output [aw-1:0] s10_adr_o, + output [sw-1:0] s10_sel_o, + output s10_we_o, + output s10_cyc_o, + output s10_stb_o, + input s10_ack_i, + input s10_err_i, + input s10_rty_i, + + input [dw-1:0] s11_dat_i, + output [dw-1:0] s11_dat_o, + output [aw-1:0] s11_adr_o, + output [sw-1:0] s11_sel_o, + output s11_we_o, + output s11_cyc_o, + output s11_stb_o, + input s11_ack_i, + input s11_err_i, + input s11_rty_i, + + input [dw-1:0] s12_dat_i, + output [dw-1:0] s12_dat_o, + output [aw-1:0] s12_adr_o, + output [sw-1:0] s12_sel_o, + output s12_we_o, + output s12_cyc_o, + output s12_stb_o, + input s12_ack_i, + input s12_err_i, + input s12_rty_i, + + input [dw-1:0] s13_dat_i, + output [dw-1:0] s13_dat_o, + output [aw-1:0] s13_adr_o, + output [sw-1:0] s13_sel_o, + output s13_we_o, + output s13_cyc_o, + output s13_stb_o, + input s13_ack_i, + input s13_err_i, + input s13_rty_i, + + input [dw-1:0] s14_dat_i, + output [dw-1:0] s14_dat_o, + output [aw-1:0] s14_adr_o, + output [sw-1:0] s14_sel_o, + output s14_we_o, + output s14_cyc_o, + output s14_stb_o, + input s14_ack_i, + input s14_err_i, + input s14_rty_i, + + input [dw-1:0] s15_dat_i, + output [dw-1:0] s15_dat_o, + output [aw-1:0] s15_adr_o, + output [sw-1:0] s15_sel_o, + output s15_we_o, + output s15_cyc_o, + output s15_stb_o, + input s15_ack_i, + input s15_err_i, + input s15_rty_i + ); + + // //////////////////////////////////////////////////////////////// + // + // Local wires + // + + wire [15:0] ssel_dec; + reg [dw-1:0] i_dat_s; // internal share bus , slave data to master + + // Master output Interface + assign m0_dat_o = i_dat_s; + + always @* + case(ssel_dec) + 1 : i_dat_s <= s0_dat_i; + 2 : i_dat_s <= s1_dat_i; + 4 : i_dat_s <= s2_dat_i; + 8 : i_dat_s <= s3_dat_i; + 16 : i_dat_s <= s4_dat_i; + 32 : i_dat_s <= s5_dat_i; + 64 : i_dat_s <= s6_dat_i; + 128 : i_dat_s <= s7_dat_i; + 256 : i_dat_s <= s8_dat_i; + 512 : i_dat_s <= s9_dat_i; + 1024 : i_dat_s <= s10_dat_i; + 2048 : i_dat_s <= s11_dat_i; + 4096 : i_dat_s <= s12_dat_i; + 8192 : i_dat_s <= s13_dat_i; + 16384 : i_dat_s <= s14_dat_i; + 32768 : i_dat_s <= s15_dat_i; + default : i_dat_s <= s0_dat_i; + endcase // case(ssel_dec) + + assign {m0_ack_o, m0_err_o, m0_rty_o} + = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i | + s8_ack_i | s9_ack_i | s10_ack_i | s11_ack_i | s12_ack_i | s13_ack_i | s14_ack_i | s15_ack_i , + s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i | + s8_err_i | s9_err_i | s10_err_i | s11_err_i | s12_err_i | s13_err_i | s14_err_i | s15_err_i , + s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i | + s8_rty_i | s9_rty_i | s10_rty_i | s11_rty_i | s12_rty_i | s13_rty_i | s14_rty_i | s15_rty_i }; + + // Slave output interfaces + assign s0_adr_o = m0_adr_i; + assign s0_sel_o = m0_sel_i; + assign s0_dat_o = m0_dat_i; + assign s0_we_o = m0_we_i; + assign s0_cyc_o = m0_cyc_i; + assign s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0]; + + assign s1_adr_o = m0_adr_i; + assign s1_sel_o = m0_sel_i; + assign s1_dat_o = m0_dat_i; + assign s1_we_o = m0_we_i; + assign s1_cyc_o = m0_cyc_i; + assign s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1]; + + assign s2_adr_o = m0_adr_i; + assign s2_sel_o = m0_sel_i; + assign s2_dat_o = m0_dat_i; + assign s2_we_o = m0_we_i; + assign s2_cyc_o = m0_cyc_i; + assign s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2]; + + assign s3_adr_o = m0_adr_i; + assign s3_sel_o = m0_sel_i; + assign s3_dat_o = m0_dat_i; + assign s3_we_o = m0_we_i; + assign s3_cyc_o = m0_cyc_i; + assign s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3]; + + assign s4_adr_o = m0_adr_i; + assign s4_sel_o = m0_sel_i; + assign s4_dat_o = m0_dat_i; + assign s4_we_o = m0_we_i; + assign s4_cyc_o = m0_cyc_i; + assign s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4]; + + assign s5_adr_o = m0_adr_i; + assign s5_sel_o = m0_sel_i; + assign s5_dat_o = m0_dat_i; + assign s5_we_o = m0_we_i; + assign s5_cyc_o = m0_cyc_i; + assign s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5]; + + assign s6_adr_o = m0_adr_i; + assign s6_sel_o = m0_sel_i; + assign s6_dat_o = m0_dat_i; + assign s6_we_o = m0_we_i; + assign s6_cyc_o = m0_cyc_i; + assign s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6]; + + assign s7_adr_o = m0_adr_i; + assign s7_sel_o = m0_sel_i; + assign s7_dat_o = m0_dat_i; + assign s7_we_o = m0_we_i; + assign s7_cyc_o = m0_cyc_i; + assign s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7]; + + assign s8_adr_o = m0_adr_i; + assign s8_sel_o = m0_sel_i; + assign s8_dat_o = m0_dat_i; + assign s8_we_o = m0_we_i; + assign s8_cyc_o = m0_cyc_i; + assign s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8]; + + assign s9_adr_o = m0_adr_i; + assign s9_sel_o = m0_sel_i; + assign s9_dat_o = m0_dat_i; + assign s9_we_o = m0_we_i; + assign s9_cyc_o = m0_cyc_i; + assign s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9]; + + assign s10_adr_o = m0_adr_i; + assign s10_sel_o = m0_sel_i; + assign s10_dat_o = m0_dat_i; + assign s10_we_o = m0_we_i; + assign s10_cyc_o = m0_cyc_i; + assign s10_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10]; + + assign s11_adr_o = m0_adr_i; + assign s11_sel_o = m0_sel_i; + assign s11_dat_o = m0_dat_i; + assign s11_we_o = m0_we_i; + assign s11_cyc_o = m0_cyc_i; + assign s11_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11]; + + assign s12_adr_o = m0_adr_i; + assign s12_sel_o = m0_sel_i; + assign s12_dat_o = m0_dat_i; + assign s12_we_o = m0_we_i; + assign s12_cyc_o = m0_cyc_i; + assign s12_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12]; + + assign s13_adr_o = m0_adr_i; + assign s13_sel_o = m0_sel_i; + assign s13_dat_o = m0_dat_i; + assign s13_we_o = m0_we_i; + assign s13_cyc_o = m0_cyc_i; + assign s13_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13]; + + assign s14_adr_o = m0_adr_i; + assign s14_sel_o = m0_sel_i; + assign s14_dat_o = m0_dat_i; + assign s14_we_o = m0_we_i; + assign s14_cyc_o = m0_cyc_i; + assign s14_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14]; + + assign s15_adr_o = m0_adr_i; + assign s15_sel_o = m0_sel_i; + assign s15_dat_o = m0_dat_i; + assign s15_we_o = m0_we_i; + assign s15_cyc_o = m0_cyc_i; + assign s15_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15]; + + // Address decode logic + // WARNING -- must make sure these are mutually exclusive! + assign ssel_dec[0] = (m0_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); + assign ssel_dec[1] = (m0_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); + assign ssel_dec[2] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s2_addr); + assign ssel_dec[3] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s3_addr); + assign ssel_dec[4] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s4_addr); + assign ssel_dec[5] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s5_addr); + assign ssel_dec[6] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s6_addr); + assign ssel_dec[7] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s7_addr); + assign ssel_dec[8] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s8_addr); + assign ssel_dec[9] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s9_addr); + assign ssel_dec[10] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s10_addr); + assign ssel_dec[11] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s11_addr); + assign ssel_dec[12] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s12_addr); + assign ssel_dec[13] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s13_addr); + assign ssel_dec[14] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s14_addr); + assign ssel_dec[15] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == s15_addr); + +endmodule // wb_1master diff --git a/usrp2/fpga/control_lib/wb_bus_writer.v b/usrp2/fpga/control_lib/wb_bus_writer.v new file mode 100644 index 00000000..fc148a0f --- /dev/null +++ b/usrp2/fpga/control_lib/wb_bus_writer.v @@ -0,0 +1,57 @@ + +// wb_bus_writer +// +// WB Bus Master device to send a sequence of single-word transactions +// based on a list in a RAM or ROM (FASM interface) +// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]} +// continues until it gets an all-1s entry + +module wb_bus_writer (input start, + output done, + output reg [15:0] rom_addr, + input [47:0] rom_data, + // WB Master Interface, don't need wb_dat_i + input wb_clk_i, + input wb_rst_i, + output [31:0] wb_dat_o, + input wb_ack_i, + output [15:0] wb_adr_o, + output wb_cyc_o, + output [3:0] wb_sel_o, + output wb_stb_o, + output wb_we_o + ); + +`define IDLE 0 +`define READ 1 + + reg [3:0] state; + + assign done = (state != `IDLE) && (&rom_data); // Done when we see all 1s + + always @(posedge wb_clk_i) + if(wb_rst_i) + begin + rom_addr <= #1 0; + state <= #1 0; + end + else if(start) + begin + rom_addr <= #1 0; + state <= #1 `READ; + end + else if((state == `READ) && wb_ack_i) + if(done) + state <= #1 `IDLE; + else + rom_addr <= #1 rom_addr + 1; + + assign wb_dat_o = rom_data[31:0]; + assign wb_adr_o = rom_data[47:32]; + assign wb_sel_o = 4'b1111; // All writes are the full 32 bits + + assign wb_cyc_o = !done & (state != `IDLE); + assign wb_stb_o = !done & (state != `IDLE); + assign wb_we_o = !done & (state != `IDLE); + +endmodule // wb_bus_writer diff --git a/usrp2/fpga/control_lib/wb_output_pins32.v b/usrp2/fpga/control_lib/wb_output_pins32.v new file mode 100644 index 00000000..1517f206 --- /dev/null +++ b/usrp2/fpga/control_lib/wb_output_pins32.v @@ -0,0 +1,49 @@ + + +// Simple 32-bit Wishbone compatible slave output port +// with 8-bit granularity, modeled after the one in the spec +// Allows for readback +// Assumes a 32-bit wishbone bus +// Lowest order bits get sel[0] +// + +module wb_output_pins32 + (wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o, + wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i, + port_output); + + input wb_rst_i; + input wb_clk_i; + input wire [31:0] wb_dat_i; + output wire [31:0] wb_dat_o; + input wb_we_i; + input wire [3:0] wb_sel_i; + input wb_stb_i; + output wb_ack_o; + input wb_cyc_i; + + output wire [31:0] port_output; + + reg [31:0] internal_reg; + + always @(posedge wb_clk_i) + if(wb_rst_i) + internal_reg <= #1 32'b0; + else + begin + if(wb_stb_i & wb_we_i & wb_sel_i[0]) + internal_reg[7:0] <= #1 wb_dat_i[7:0]; + if(wb_stb_i & wb_we_i & wb_sel_i[1]) + internal_reg[15:8] <= #1 wb_dat_i[15:8]; + if(wb_stb_i & wb_we_i & wb_sel_i[2]) + internal_reg[23:16] <= #1 wb_dat_i[23:16]; + if(wb_stb_i & wb_we_i & wb_sel_i[3]) + internal_reg[31:24] <= #1 wb_dat_i[31:24]; + end // else: !if(wb_rst_i) + + assign wb_dat_o = internal_reg; + assign port_output = internal_reg; + assign wb_ack_o = wb_stb_i; + +endmodule // wb_output_pins32 + diff --git a/usrp2/fpga/control_lib/wb_ram_block.v b/usrp2/fpga/control_lib/wb_ram_block.v new file mode 100644 index 00000000..044d34ca --- /dev/null +++ b/usrp2/fpga/control_lib/wb_ram_block.v @@ -0,0 +1,36 @@ + + +// Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency +// These have to be a multiple of 512 lines (2K) long + +module wb_ram_block + #(parameter AWIDTH=9) + (input clk_i, + input stb_i, + input we_i, + input [AWIDTH-1:0] adr_i, + input [31:0] dat_i, + output reg [31:0] dat_o, + output ack_o); + + reg [31:0] distram [0:1<<(AWIDTH-1)]; + + always @(posedge clk_i) + begin + if(stb_i & we_i) + distram[adr_i] <= dat_i; + dat_o <= distram[adr_i]; + end + + reg stb_d1, ack_d1; + always @(posedge clk_i) + stb_d1 <= stb_i; + + always @(posedge clk_i) + ack_d1 <= ack_o; + + assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1)); +endmodule // wb_ram_block + + + diff --git a/usrp2/fpga/control_lib/wb_ram_dist.v b/usrp2/fpga/control_lib/wb_ram_dist.v new file mode 100644 index 00000000..cffc2f42 --- /dev/null +++ b/usrp2/fpga/control_lib/wb_ram_dist.v @@ -0,0 +1,33 @@ + + +module wb_ram_dist + #(parameter AWIDTH=8) + (input clk_i, + input stb_i, + input we_i, + input [AWIDTH-1:0] adr_i, + input [31:0] dat_i, + input [3:0] sel_i, + output [31:0] dat_o, + output ack_o); + + reg [31:0] distram [0:1<<(AWIDTH-1)]; + + always @(posedge clk_i) + begin + if(stb_i & we_i & sel_i[3]) + distram[adr_i][31:24] <= dat_i[31:24]; + if(stb_i & we_i & sel_i[2]) + distram[adr_i][24:16] <= dat_i[24:16]; + if(stb_i & we_i & sel_i[1]) + distram[adr_i][15:8] <= dat_i[15:8]; + if(stb_i & we_i & sel_i[0]) + distram[adr_i][7:0] <= dat_i[7:0]; + end // always @ (posedge clk_i) + + assign dat_o = distram[adr_i]; + assign ack_o = stb_i; + +endmodule // wb_ram_dist + + diff --git a/usrp2/fpga/control_lib/wb_readback_mux.v b/usrp2/fpga/control_lib/wb_readback_mux.v new file mode 100644 index 00000000..3922b03e --- /dev/null +++ b/usrp2/fpga/control_lib/wb_readback_mux.v @@ -0,0 +1,60 @@ + + +// Note -- clocks must be synchronous (derived from the same source) +// Assumes alt_clk is running at a multiple of wb_clk + +module wb_readback_mux + (input wb_clk_i, + input wb_rst_i, + input wb_stb_i, + input [15:0] wb_adr_i, + output reg [31:0] wb_dat_o, + output reg wb_ack_o, + + input [31:0] word00, + input [31:0] word01, + input [31:0] word02, + input [31:0] word03, + input [31:0] word04, + input [31:0] word05, + input [31:0] word06, + input [31:0] word07, + input [31:0] word08, + input [31:0] word09, + input [31:0] word10, + input [31:0] word11, + input [31:0] word12, + input [31:0] word13, + input [31:0] word14, + input [31:0] word15 + ); + + always @(posedge wb_clk_i) + if(wb_rst_i) + wb_ack_o <= 0; + else + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + always @(posedge wb_clk_i) + case(wb_adr_i[5:2]) + 0 : wb_dat_o <= word00; + 1 : wb_dat_o <= word01; + 2 : wb_dat_o <= word02; + 3 : wb_dat_o <= word03; + 4 : wb_dat_o <= word04; + 5 : wb_dat_o <= word05; + 6 : wb_dat_o <= word06; + 7 : wb_dat_o <= word07; + 8 : wb_dat_o <= word08; + 9 : wb_dat_o <= word09; + 10: wb_dat_o <= word10; + 11: wb_dat_o <= word11; + 12: wb_dat_o <= word12; + 13: wb_dat_o <= word13; + 14: wb_dat_o <= word14; + 15: wb_dat_o <= word15; + endcase // case(addr_reg[3:0]) + +endmodule // wb_readback_mux + + diff --git a/usrp2/fpga/control_lib/wb_regfile_2clock.v b/usrp2/fpga/control_lib/wb_regfile_2clock.v new file mode 100644 index 00000000..e248e516 --- /dev/null +++ b/usrp2/fpga/control_lib/wb_regfile_2clock.v @@ -0,0 +1,107 @@ + +module wb_regfile_2clock + (input wb_clk_i, + input wb_rst_i, + input wb_stb_i, + input wb_we_i, + input [15:0] wb_adr_i, + input [3:0] wb_sel_i, + input [31:0] wb_dat_i, + output [31:0] wb_dat_o, + output wb_ack_o, + input alt_clk, + input alt_rst, + + output reg [31:0] reg00, + output reg [31:0] reg01, + output reg [31:0] reg02, + output reg [31:0] reg03, + output reg [31:0] reg04, + output reg [31:0] reg05, + output reg [31:0] reg06, + output reg [31:0] reg07 + ); + + reg [15:0] addr_reg; + reg [3:0] sel_reg; + reg [31:0] dat_reg; + reg wr_ret1, wr_ret2, we_reg, stb_reg; + + always @(posedge wb_clk_i) + if(wb_rst_i) + begin + addr_reg <= 0; + sel_reg <= 0; + dat_reg <= 0; + end + else if(wb_stb_i & wb_we_i) + begin + addr_reg <= wb_adr_i; + sel_reg <= wb_sel_i; + dat_reg <= wb_dat_i; + end + + always @(posedge wb_clk_i) + if(wb_rst_i) + {we_reg,stb_reg} <= 2'b0; + else + {we_reg,stb_reg} <= {wb_we_i,wb_stb_i}; + + assign wb_ack_o = stb_reg; + + always @(posedge alt_clk) + if(alt_rst) + {wr_ret2, wr_ret1} <= 2'b0; + else + {wr_ret2, wr_ret1} <= {wr_ret1, we_reg & stb_reg}; + + always @(posedge alt_clk) + if(alt_rst) + begin + reg00 <= 0; + reg01 <= 0; + reg02 <= 0; + reg03 <= 0; + reg04 <= 0; + reg05 <= 0; + reg06 <= 0; + reg07 <= 0; + end // if (alt_rst) + else if(wr_ret2) + case(addr_reg[4:2]) + 3'd0: reg00 <= { {sel_reg[3] ? dat_reg[31:24] : reg00[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg00[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg00[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg00[7:0]}}; + 3'd1: reg01 <= { {sel_reg[3] ? dat_reg[31:24] : reg01[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg01[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg01[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg01[7:0]}}; + 3'd2: reg02 <= { {sel_reg[3] ? dat_reg[31:24] : reg02[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg02[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg02[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg02[7:0]}}; + 3'd3: reg03 <= { {sel_reg[3] ? dat_reg[31:24] : reg03[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg03[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg03[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg03[7:0]}}; + 3'd4: reg04 <= { {sel_reg[3] ? dat_reg[31:24] : reg04[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg04[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg04[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg04[7:0]}}; + 3'd5: reg05 <= { {sel_reg[3] ? dat_reg[31:24] : reg05[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg05[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg05[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg05[7:0]}}; + 3'd6: reg06 <= { {sel_reg[3] ? dat_reg[31:24] : reg06[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg06[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg06[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg06[7:0]}}; + 3'd7: reg07 <= { {sel_reg[3] ? dat_reg[31:24] : reg07[31:24]}, + {sel_reg[2] ? dat_reg[23:16] : reg07[23:16]}, + {sel_reg[1] ? dat_reg[15:8] : reg07[15:8]}, + {sel_reg[0] ? dat_reg[7:0] : reg07[7:0]}}; + endcase // case(addr_reg[2:0]) + +endmodule // wb_regfile_2clock + diff --git a/usrp2/fpga/control_lib/wb_semaphore.v b/usrp2/fpga/control_lib/wb_semaphore.v new file mode 100644 index 00000000..a9208e6a --- /dev/null +++ b/usrp2/fpga/control_lib/wb_semaphore.v @@ -0,0 +1,42 @@ + +// up to 8 semaphores + +// After a read operation, the semaphore is always locked +// If it was already locked before the read (meaning someone else holds the lock) +// then a 1 is returned +// If it was not already locked (meaning the reader now holds the lock) +// then a 0 is returned + +// A write operation clears the lock + +module wb_semaphore + #(parameter count=8, DBUS_WIDTH=32) + (input wb_clk_i, + input wb_rst_i, + input [DBUS_WIDTH-1:0] wb_dat_i, + input [2:0] wb_adr_i, + input wb_cyc_i, + input wb_stb_i, + input wb_we_i, + output wb_ack_o, + output [DBUS_WIDTH-1:0] wb_dat_o); + + reg [count-1:0] locked; + + always @(posedge clock) + if(wb_rst_i) + locked <= {count{1'b0}}; + else if(wb_stb_i) + if(wb_we_i) + locked[adr_i] <= 1'b0; + else + locked[adr_i] <= 1'b1; + + assign wb_dat_o[DBUS_WIDTH-1:1] = {(DBUS_WIDTH-1){1'b0}}; + assign wb_dat_o[0] = locked[adr_i]; + assign wb_ack_o = wb_stb_i; + + +endmodule // wb_semaphore + + diff --git a/usrp2/fpga/control_lib/wb_sim.v b/usrp2/fpga/control_lib/wb_sim.v new file mode 100644 index 00000000..b324e145 --- /dev/null +++ b/usrp2/fpga/control_lib/wb_sim.v @@ -0,0 +1,79 @@ + + +module wb_sim(); + + wire wb_clk, wb_rst; + wire start; + + reg POR, aux_clk, clk_fpga; + + initial POR = 1'b1; + initial #103 POR = 1'b0; + + initial aux_clk = 1'b0; + always #25 aux_clk = ~aux_clk; + + initial clk_fpga = 1'bx; + initial #3007 clk_fpga = 1'b0; + always #7 clk_fpga = ~clk_fpga; + + initial begin + $dumpfile("wb_sim.vcd"); + $dumpvars(0,wb_sim); + end + + initial #10000 $finish; + + wire [15:0] rom_addr; + wire [47:0] rom_data; + wire [31:0] wb_dat; + wire [15:0] wb_adr; + wire wb_cyc,wb_stb,wb_we,wb_ack; + wire [3:0] wb_sel; + + wire [31:0] port_output; + + + system_control system_control(.dsp_clk(dsp_clk), + .reset_out(reset_out), + .wb_clk_o(wb_clk), + .wb_rst_o(wb_rst), + .wb_rst_o_alt(wb_rst_o_alt), + .start (start), + .aux_clk(aux_clk), + .clk_fpga(clk_fpga), + .POR (POR), + .done (done)); + + clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data)); + + wb_bus_writer bus_writer(.rom_addr (rom_addr[15:0]), + .wb_dat_o (wb_dat[31:0]), + .wb_adr_o (wb_adr[15:0]), + .wb_cyc_o (wb_cyc), + .wb_sel_o (wb_sel[3:0]), + .wb_stb_o (wb_stb), + .wb_we_o (wb_we), + .start (start), + .done (done), + .rom_data (rom_data[47:0]), + .wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .wb_ack_i (wb_ack)); + + wb_output_pins32 output_pins(.wb_dat_o(), + .wb_ack_o(wb_ack), + .port_output(port_output[31:0]), + .wb_rst_i(wb_rst), + .wb_clk_i(wb_clk), + .wb_dat_i(wb_dat[31:0]), + .wb_we_i(wb_we), + .wb_sel_i(wb_sel[3:0]), + .wb_stb_i(wb_stb), + .wb_cyc_i(wb_cyc)); + + + + +endmodule // wb_sim + diff --git a/usrp2/fpga/coregen/coregen.cgp b/usrp2/fpga/coregen/coregen.cgp new file mode 100644 index 00000000..1ee75a7b --- /dev/null +++ b/usrp2/fpga/coregen/coregen.cgp @@ -0,0 +1,20 @@ +# Date: Mon Feb 4 20:12:22 2008 +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s1500 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +SET workingdirectory = /home/matt/coregen/tmp + diff --git a/usrp2/fpga/coregen/fifo_generator_release_notes.txt b/usrp2/fpga/coregen/fifo_generator_release_notes.txt new file mode 100644 index 00000000..554ec87f --- /dev/null +++ b/usrp2/fpga/coregen/fifo_generator_release_notes.txt @@ -0,0 +1,160 @@ +COPYRIGHT (c) 2006, 2007 XILINX, INC. +ALL RIGHTS RESERVED + +Core name : FIFO Generator +Version : v4.1 +Release Date : August 8, 2007 +File : fifo_generator_release_notes.txt + +Revision History +Date By Version Change Description +======================================================================== +09/2006 Xilinx, Inc. 3.2 Initial creation. +02/2007 Xilinx, Inc. 3.3 Revised for v3.3. +02/2007 Xilinx, Inc. 3.3 Revised for v3.3 rev 1. +08/2007 Xilinx, Inc. 3.4 Revised for v4.1. +======================================================================== + +INTRODUCTION +RELEASE NOTES + 1. General Core Design + 1.1 Enhancements + 1.2 Resolved Issues + 1.3 Outstanding Issues + 2. General Simulation + 2.1 Enhancements + 2.2 Resolved Issues + 2.3 Outstanding Issues + 3. Documentation + 3.1 Enhancements + 3.2 Resolved Issues + 3.3 Outstanding Issues +OTHER GENERAL INFORMATION +TECHNICAL SUPPORT + +======================================================================== + +INTRODUCTION +============ +Thank you using the FIFO Generator core from Xilinx! +In order to obtain the latest core updates and documentation, +please visit the Intellectual Property page located at: +http://www.xilinx.com/ipcenter/index.htm +This document contains the release notes for FIFO Generator v4.1 +which includes enhancements, resolved issues and outstanding known +issues. For release notes and known issues for CORE Generator 9.2i IP +Update 1 and FIFO Generator v4.1 please see Answer Record 25222. + +RELEASE NOTES +============= +This section lists any enhancements, resolved issues and outstanding +known issues. + + +1. General Core Design + 1.1 Enhancements + 1.1.1 Error Correction Checking (ECC) feature support for + Virtex-5 block RAM FIFO configurations + + 1.1.2 Full range data count widths now supported for non-symmetric + aspect ratio configurations + + 1.1.3 Option to define asynchronous reset value for full condition + flags (FULL, ALMOST_FULL, PROG_FULL). Applies to block RAM, + distributed RAM and shift RAM-based FIFO configurations only + + 1.1.4 Support added for use embedded output registers in block RAM + FIFO configurations (Virtex-4 and Virtex-5 only) + + 1.2 Resolved Issues + 1.2.1 Coregen GUI - For built-in FIFOs, GUI reports incorrect + number of built-in FIFO primitives used. + Change request: 4433738 + + 1.2.2 Programmable full flag is always asserted even when FIFO is + empty due to incorrect threshold setting. + Change request: 435835 + + 1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol + .. , these pins should be connected to the same signal" occur + during MAP when targeting Virtex-4 and Virtex-5. + Change request: 338260 + + 1.2.4 Write Data Count and Read Data Count overestimate the number + of words written or read when core is configured with this + combination of options: First-Word-Fall-Through(FWFT), + accurate data count using extra logic, non-symmetric port + aspect ratio. + Change request: 436886 + + 1.2.5 SBITERR and DBITERR outputs are not driven in behavior + models. + Change request: 433637 + + 1.2.6 Maximum programmable empty threshold negate value is + incorrect. + Change request: 433921 + + 1.2.7 Programmable full flag behavior is incorrect when the + core is configured with this combination of options: + FWFT, non-symmetric port aspect ratio, single or + multiple programmable full threshold input port. + Change request: 435874 + + 1.2.8 Programmable empty flag stuck high when the core is + configured with this combination of options: block or + distributed RAM FIFO, single or multiple programmable + empty threshold input port. + Change request: 443569 + + 1.3 Outstanding Issues + 1.3.1 "WARNING:Ngdbuild:452 - logical net + 'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during + NgdBuild although programmable empty or full is not selected. + Warnings can be safely ignored. + Change request: 431975 + +2. General Simulation + 2.1 Enhancements + None at this time. + + 2.2 Resolved Issues + None at this time. + + 2.3 Outstanding Issues + 2.3.1 Ncelab warnings during Verilog structural and timing simulations + in ncsim for Virtex5 Block RAM FIFOs. + The simulations will be successful, but there will be warnings + similar to the following in the log file: "memory index out of + declared bounds" in simprims_ver_virtex5_source.v or + unisims_ver_virtex5_source.v. Cadence does not want to fix this + issue. These warning messages can safely be ignored. + Change request: 423374, 423375 + +3. Documentation + 3.1 Enhancements + 3.1.1 Added clarification on FIFO flag latency. + + 3.1.1 Added clarification on actual FIFO depth. + + 3.2 Resolved Issues + None at this time. + + 3.3 Outstanding Issues + None at this time. + + +TECHNICAL SUPPORT +================= +The fastest method for obtaining specific technical support for the +FIFO Generator core is through the http://support.xilinx.com/ +website. Questions are routed to a team of engineers with specific +expertise in using the FIFO Generator core. Xilinx will provide +technical support for use of this product as described in the FIFO +Generator Datasheet. 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+ + + diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_flist.txt b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_flist.txt new file mode 100644 index 00000000..670d8471 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +fifo_xlnx_2Kx36_2clk.asy +fifo_xlnx_2Kx36_2clk.ngc +fifo_xlnx_2Kx36_2clk.sym +fifo_xlnx_2Kx36_2clk.v +fifo_xlnx_2Kx36_2clk.veo +fifo_xlnx_2Kx36_2clk.vhd +fifo_xlnx_2Kx36_2clk.vho +fifo_xlnx_2Kx36_2clk.xco +fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_2Kx36_2clk_flist.txt +fifo_xlnx_2Kx36_2clk_xmdf.tcl diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_readme.txt b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_readme.txt new file mode 100644 index 00000000..86b8f03e --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_readme.txt @@ -0,0 +1,55 @@ +The following files were generated for 'fifo_xlnx_2Kx36_2clk' in directory +/home/matt/usrp2/fpga/coregen: + +fifo_xlnx_2Kx36_2clk.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +fifo_xlnx_2Kx36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_2Kx36_2clk.sym: + Please see the core data sheet. + +fifo_xlnx_2Kx36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_2Kx36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_2Kx36_2clk.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +fifo_xlnx_2Kx36_2clk.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +fifo_xlnx_2Kx36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_2Kx36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_2Kx36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_2Kx36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl new file mode 100644 index 00000000..cac25efd --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl @@ -0,0 +1,84 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_2Kx36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_2Kx36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_2Kx36_2clk +} +# ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_2Kx36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.asy b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.asy new file mode 100644 index 00000000..ecc80b64 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_xlnx_512x36_2clk +RECTANGLE Normal 32 32 544 672 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 704 144 672 +PIN 144 704 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[8:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[8:0] +PINATTR Polarity OUT + diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.ngc b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.ngc new file mode 100644 index 00000000..618ccf76 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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\ No newline at end of file diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.sym b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.sym new file mode 100644 index 00000000..13e8af33 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.sym @@ -0,0 +1,74 @@ +VERSION 5 +BEGIN SYMBOL fifo_xlnx_512x36_2clk +SYMBOLTYPE BLOCK +TIMESTAMP 2008 7 28 22 45 53 +SYMPIN 0 80 Input din[35:0] +SYMPIN 0 144 Input wr_en +SYMPIN 0 176 Input wr_clk +SYMPIN 0 240 Input rd_en +SYMPIN 0 272 Input rd_clk +SYMPIN 144 704 Input rst +SYMPIN 576 80 Output dout[35:0] +SYMPIN 576 208 Output full +SYMPIN 576 368 Output wr_data_count[8:0] +SYMPIN 576 432 Output empty +SYMPIN 576 592 Output rd_data_count[8:0] +BEGIN DISPLAY 32 32 TEXT fifo_xlnx_512x36_2clk + FONT 40 "Arial" +END DISPLAY +RECTANGLE N 32 32 544 672 +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 144 32 144 +BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 176 32 176 +BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 240 32 240 +BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 272 32 272 +BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 144 704 144 672 +BEGIN DISPLAY 144 668 PIN rst ATTR PinName + ALIGNMENT BCENTER + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 80 544 80 +END LINE +BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 208 544 208 +BEGIN DISPLAY 540 208 PIN full ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 368 544 368 +END LINE +BEGIN DISPLAY 540 368 PIN wr_data_count[8:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 432 544 432 +BEGIN DISPLAY 540 432 PIN empty ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 592 544 592 +END LINE +BEGIN DISPLAY 540 592 PIN rd_data_count[8:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +END SYMBOL diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.v b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.v new file mode 100644 index 00000000..3cc5e29f --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating +// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [8 : 0] rd_data_count; +output [8 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(511), + .C_PROG_FULL_THRESH_NEGATE_VAL(510), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(9), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(0), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of fifo_xlnx_512x36_2clk is "black_box" + +endmodule + diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo new file mode 100644 index 00000000..40747fd2 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [8 : 0] + .wr_data_count(wr_data_count)); // Bus [8 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating +// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vhd b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vhd new file mode 100644 index 00000000..d9c2dd30 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vhd @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating +-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY fifo_xlnx_512x36_2clk IS + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +END fifo_xlnx_512x36_2clk; + +ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS +-- synthesis translate_off +component wrapped_fifo_xlnx_512x36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 1, + c_din_width => 36, + c_has_wr_data_count => 1, + c_full_flags_rst_val => 1, + c_implementation_type => 2, + c_family => "spartan3", + c_use_embedded_reg => 0, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 0, + c_dout_width => 36, + c_msgon_val => 1, + c_rd_depth => 512, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 9, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 9, + c_use_fwft_data_count => 0, + c_has_almost_empty => 0, + c_rd_data_count_width => 9, + c_enable_rlocs => 0, + c_wr_pntr_width => 9, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 9, + c_preload_regs => 1, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 510, + c_wr_depth => 512, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 511, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "512x36", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_fifo_xlnx_512x36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- synthesis translate_on + +END fifo_xlnx_512x36_2clk_a; + diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vho b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vho new file mode 100644 index 00000000..70eac27a --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vho @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component fifo_xlnx_512x36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_xlnx_512x36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating +-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.xco b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.xco new file mode 100644 index 00000000..c67e7e89 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.31 +# Date: Mon Jul 28 22:47:43 2008 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=511 +CSET full_threshold_negate_value=510 +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=9 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=false +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: 43b7cba0 + diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 00000000..f1a6f789 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 00000000..5abd4e09 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,103 @@ + + + + + + +
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+ + + diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt new file mode 100644 index 00000000..e9d38a49 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt @@ -0,0 +1,12 @@ +# Output products list for +fifo_xlnx_512x36_2clk.asy +fifo_xlnx_512x36_2clk.ngc +fifo_xlnx_512x36_2clk.sym +fifo_xlnx_512x36_2clk.v +fifo_xlnx_512x36_2clk.veo +fifo_xlnx_512x36_2clk.vhd +fifo_xlnx_512x36_2clk.vho +fifo_xlnx_512x36_2clk.xco +fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_flist.txt +fifo_xlnx_512x36_2clk_xmdf.tcl diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt new file mode 100644 index 00000000..07bf2079 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt @@ -0,0 +1,55 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk' in directory +/home/jblum/proj/usrp2/trunk/fpga/coregen/: + +fifo_xlnx_512x36_2clk.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +fifo_xlnx_512x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk.sym: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +fifo_xlnx_512x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_512x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl new file mode 100644 index 00000000..42a681df --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl @@ -0,0 +1,84 @@ +# The package naming convention is _xmdf +package provide fifo_xlnx_512x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::fifo_xlnx_512x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk +} +# ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/usrp2/fpga/eth/bench/verilog/100m.scr b/usrp2/fpga/eth/bench/verilog/100m.scr new file mode 100644 index 00000000..0dd59b89 --- /dev/null +++ b/usrp2/fpga/eth/bench/verilog/100m.scr @@ -0,0 +1,38 @@ +// This tests just runs a few packets at 10/100 Mbps and 1 Gbps instead of only the usual 1 Gbps + +// Read from register 24 to confirm that Rx CRC check is enabled +03 00 18 00 01 ff ff + +// Set speed to 1000 Mbps for a starter +01 00 22 00 04 + +// Setup Tx and Rx MAC addresses and type field to "IP" +// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800 +10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00 + +// Transmit a 1000-byte frame 1 time - and expect it to be received again! +20 03 E8 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Set speed to 100 Mbps - this is 10x slower! +01 00 22 00 02 + +// Transmit a 1000-byte frame 1 time - and expect it to be received again! +20 03 E8 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Set speed to 10 Mbps - this is yet another 10x slower! +01 00 22 00 01 + +// Transmit a 1000-byte frame 1 time - and expect it to be received again! +20 03 E8 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Halt +FF diff --git a/usrp2/fpga/eth/bench/verilog/Phy_sim.v b/usrp2/fpga/eth/bench/verilog/Phy_sim.v new file mode 100644 index 00000000..f51ddbd8 --- /dev/null +++ b/usrp2/fpga/eth/bench/verilog/Phy_sim.v @@ -0,0 +1,113 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Phy_sim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: Phy_sim.v,v $ +// Revision 1.3 2006/11/17 17:53:07 maverickist +// no message +// +// Revision 1.2 2006/01/19 14:07:50 maverickist +// verification is complete. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +`timescale 1ns/100ps + +module Phy_sim( + input Gtx_clk, // Used only in GMII mode + output Rx_clk, + output Tx_clk, // Used only in MII mode + input Tx_er, + input Tx_en, + input [7:0] Txd, + output Rx_er, + output Rx_dv, + output [7:0] Rxd, + output Crs, + output Col, + input [2:0] Speed, + input Done +); + +////////////////////////////////////////////////////////////////////// +// this file used to simulate Phy. +// generate clk and loop the Tx data to Rx data +// full duplex mode can be verified on loop mode. +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +// internal signals +////////////////////////////////////////////////////////////////////// +reg Clk_25m; // Used for 100 Mbps mode +reg Clk_2_5m; // Used for 10 Mbps mode + +//wire Rx_clk; +//wire Tx_clk; // Used only in MII mode + + initial + begin + #10; + while ( !Done ) + begin + #20 Clk_25m = 0; + #20 Clk_25m = 1; + end + end + + initial + begin + #10; + while ( !Done ) + begin + #200 Clk_2_5m = 0; + #200 Clk_2_5m = 1; + end + end + + assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; + assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0; + + assign Rx_dv = Tx_en; + assign Rxd = Txd; + assign Rx_er = Tx_er; + assign Crs = Tx_en; + assign Col = 0; + +endmodule diff --git a/usrp2/fpga/eth/bench/verilog/User_int_sim.v b/usrp2/fpga/eth/bench/verilog/User_int_sim.v new file mode 100644 index 00000000..3f4aa249 --- /dev/null +++ b/usrp2/fpga/eth/bench/verilog/User_int_sim.v @@ -0,0 +1,230 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// User_input_sim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: User_int_sim.v,v $ +// Revision 1.3 2006/11/17 17:53:07 maverickist +// no message +// +// Revision 1.2 2006/01/19 14:07:50 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/13 12:15:35 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +module User_int_sim ( + Reset, + Clk_user, + CPU_init_end, + + Rx_mac_ra, + Rx_mac_rd, + Rx_mac_data, + Rx_mac_BE, + Rx_mac_pa, + Rx_mac_sop, + Rx_mac_eop, + + Tx_mac_wa, + Tx_mac_wr, + Tx_mac_data, + Tx_mac_BE, + Tx_mac_sop, + Tx_mac_eop +); + + input Reset; + input Clk_user; + input CPU_init_end; + + input Rx_mac_ra; + output Rx_mac_rd; + input [31:0] Rx_mac_data; + input [1:0] Rx_mac_BE; + input Rx_mac_pa; + input Rx_mac_sop; + input Rx_mac_eop; + + input Tx_mac_wa; + output reg Tx_mac_wr; + output reg [31:0] Tx_mac_data; + output reg [1:0] Tx_mac_BE; // Big endian + output reg Tx_mac_sop; + output reg Tx_mac_eop; + +////////////////////////////////////////////////////////////////////// +// Internal signals +////////////////////////////////////////////////////////////////////// + + reg [4:0] operation; + reg [31:0] data; + reg Rx_mac_rd; + reg Start_tran; + +////////////////////////////////////////////////////////////////////// +//generate Tx user data +////////////////////////////////////////////////////////////////////// + + initial + begin + operation = 0; + data = 0; + end + + task SendPacket; + input [15:0] Length; + input [7:0] StartByte; + + reg [15:0] Counter; + reg [7:0] TxData; + + begin + Counter=Length; + TxData = StartByte; + Tx_mac_sop = 1; // First time + while ( Counter>0 ) + begin + while ( !Tx_mac_wa ) + begin + Tx_mac_wr = 0; + @( posedge Clk_user ); + end + + Tx_mac_data[31:24] = TxData; + Tx_mac_data[23:16] = TxData+1; + Tx_mac_data[15:8] = TxData+2; + Tx_mac_data[ 7:0] = TxData+3; + TxData = TxData+4; + if ( Counter<=4 ) + begin + // Indicate how many bytes are valid + if ( Counter==4 ) + Tx_mac_BE = 2'b00; + else + Tx_mac_BE = Counter; + Tx_mac_eop = 1; + end + Tx_mac_wr = 1; + + if ( Counter >= 4 ) + Counter = Counter - 4; + else + Counter = 0; + @( posedge Clk_user ); + Tx_mac_sop = 0; + end + + Tx_mac_eop = 0; + Tx_mac_wr = 0; + Tx_mac_data = 32'h0; + Tx_mac_BE = 2'b00; + end + endtask + + always @( posedge Clk_user or posedge Reset ) + if (Reset) + Start_tran <= 0; + else if (Tx_mac_eop && !Tx_mac_wa) + Start_tran <= 0; + else if (Tx_mac_wa) + Start_tran <= 1; + + always @(posedge Clk_user) + if (Tx_mac_wa && CPU_init_end) + /* $ip_32W_gen("../data/config.ini",operation,data); */ + ; + else + begin + operation <= 0; + data <= 0; + end + + initial + begin + Tx_mac_sop = 0; + Tx_mac_eop = 0; + Tx_mac_wr = 0; + Tx_mac_data = 32'h0; + Tx_mac_BE = 2'b00; + + #100; + while ( Reset ) + @( posedge Clk_user ); + + @( posedge Clk_user ); + + while ( !CPU_init_end ) + @( posedge Clk_user ); + + SendPacket( 64, 8'h11 ); + repeat( 20 ) + @( posedge Clk_user ); + SendPacket( 1500, 8'h12 ); + + end + +// assign Tx_mac_data = data; +// assign Tx_mac_wr = operation[4]; +// assign Tx_mac_sop = operation[3]; +// assign Tx_mac_eop = operation[2]; +// assign Tx_mac_BE = operation[1:0]; + +////////////////////////////////////////////////////////////////////// +//verify Rx user data +////////////////////////////////////////////////////////////////////// + + always @ (posedge Clk_user or posedge Reset) + if (Reset) + Rx_mac_rd <= 0; + else if (Rx_mac_ra) + Rx_mac_rd <= 1; + else + Rx_mac_rd <= 0; + + always @ (posedge Clk_user ) + if (Rx_mac_pa) + /* $ip_32W_check( Rx_mac_data, + {Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0}); + */ + ; + +endmodule diff --git a/usrp2/fpga/eth/bench/verilog/error.scr b/usrp2/fpga/eth/bench/verilog/error.scr new file mode 100644 index 00000000..af42634a --- /dev/null +++ b/usrp2/fpga/eth/bench/verilog/error.scr @@ -0,0 +1,146 @@ +// This tests sends 5 packets, injecting a bit error in two of them +// to verify the Rx CRC check works. The corresponding RMON statistics +// counter is finally checked to verify that the error was registered + +// Read from register 24 to confirm that Rx CRC check is enabled +03 00 18 00 01 ff ff + +// Set speed to 1000 Mbps +01 00 22 00 04 + +// Setup Tx and Rx MAC addresses and type field to "IP" +// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800 +10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00 + +//--- Packets #0 & 1 -------------------------------------------------------- + +// Transmit a 200-byte frame 1 time - and expect it to be received again! +20 00 C8 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Transmit a 200-byte frame 1 time - but expect to receive it with error! +25 00 C8 00 01 + +// Inject a single bit error in the packet (data bit 0) - this will cause a CRC error +23 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +//--- Packets #2 & 3 -------------------------------------------------------- + +// Transmit a 200-byte frame 1 time - and expect it to be received again! +20 00 C8 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Transmit a 200-byte frame 1 time - but expect to receive it with error! +25 00 C8 00 01 + +// Inject a single bit error in the packet (data bit 7) - this will cause a CRC error +23 00 80 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +//--- Packets #4 & 5 -------------------------------------------------------- + +// Transmit a 200-byte frame 1 time - and expect it to be received again! +20 00 C8 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Transmit a 200-byte frame 1 time - but don't expect it to be received again! +21 00 C8 00 01 + +// Inject a single bit error in the packet (RxEn) - this will cause a packet discard! +// (because it happens early in the packet) +23 01 00 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +//--- Packets #6 & 7 -------------------------------------------------------- + +// Transmit a 200-byte frame 1 time - and expect it to be received again! +20 00 C8 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Transmit a 200-byte frame 1 time - but don't expect it to be received again! +21 00 C8 00 01 + +// Inject a single bit error in the packet (RxEr) +23 02 00 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +//--- Packet #8 ------------------------------------------------------------- + +// Transmit a 200-byte frame 1 time - and expect it to be received again! +20 00 C8 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +//--------------------------------------------------------------------------- + +// Set CPU_rd_addr to address RxCRCErrCounter +01 00 1C 00 05 + +// Assert CPU_rd_apply +01 00 1D 00 01 + +// Kill a little time while waiting for CPU_rd_grant to assert... +02 00 1E +02 00 1E +02 00 1E +02 00 1E + +// Confirm that CPU_rd_grant is asserted +03 00 1E 00 01 ff ff + +// Read & check low part of RxCRCErrCounter (0x0002) +03 00 1F 00 02 ff ff + +// Read & check high part of RxCRCErrCounter (0x0000) +03 00 20 00 00 ff ff + +// Negate CPU_rd_apply +01 00 1D 00 00 + +//--------------------------------------------------------------------------- + +// Set CPU_rd_addr to address RxTooShortTooLongCounter +01 00 1C 00 07 + +// Assert CPU_rd_apply +01 00 1D 00 01 + +// Kill a little time while waiting for CPU_rd_grant to assert... +02 00 1E +02 00 1E +02 00 1E +02 00 1E + +// Confirm that CPU_rd_grant is asserted +03 00 1E 00 01 ff ff + +// Read & check low part of RxTooShortTooLongCounter (0x0002) +03 00 1F 00 02 ff ff + +// Read & check high part of RxTooShortTooLongCounter (0x0000) +03 00 20 00 00 ff ff + +// Negate CPU_rd_apply +01 00 1D 00 00 + + +// Halt +FF diff --git a/usrp2/fpga/eth/bench/verilog/files.lst b/usrp2/fpga/eth/bench/verilog/files.lst new file mode 100644 index 00000000..6175a4d4 --- /dev/null +++ b/usrp2/fpga/eth/bench/verilog/files.lst @@ -0,0 +1,42 @@ +../../rtl/verilog/MAC_rx/Broadcast_filter.v +../../rtl/verilog/MAC_rx/CRC_chk.v +../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v +../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v +../../rtl/verilog/MAC_rx/MAC_rx_FF.v + +../../rtl/verilog/MAC_tx/CRC_gen.v +../../rtl/verilog/MAC_tx/flow_ctrl.v +../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v +../../rtl/verilog/MAC_tx/MAC_tx_ctrl.v +../../rtl/verilog/MAC_tx/MAC_tx_FF.v +../../rtl/verilog/MAC_tx/Ramdon_gen.v + +../../rtl/verilog/miim/eth_clockgen.v +../../rtl/verilog/miim/eth_outputcontrol.v +../../rtl/verilog/miim/eth_shiftreg.v + +../../rtl/verilog/RMON/RMON_addr_gen.v +../../rtl/verilog/RMON/RMON_ctrl.v +../../rtl/verilog/RMON/RMON_dpram.v + +../../rtl/verilog/TECH/duram.v +../../rtl/verilog/TECH/eth_clk_div2.v +../../rtl/verilog/TECH/eth_clk_switch.v + +../../rtl/verilog/TECH/xilinx/BUFGMUX.v +../../rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v + +../../rtl/verilog/Clk_ctrl.v +../../rtl/verilog/eth_miim.v +../../rtl/verilog/MAC_rx.v +../../rtl/verilog/MAC_top.v +../../rtl/verilog/MAC_tx.v +../../rtl/verilog/Phy_int.v +../../rtl/verilog/Reg_int.v +../../rtl/verilog/RMON.v + +../../bench/verilog/Phy_sim.v +../../bench/verilog/User_int_sim.v +../../bench/verilog/host_sim.v +../../bench/verilog/xlnx_glbl.v +../../bench/verilog/tb_top.v diff --git a/usrp2/fpga/eth/bench/verilog/host_sim.v b/usrp2/fpga/eth/bench/verilog/host_sim.v new file mode 100644 index 00000000..55abb850 --- /dev/null +++ b/usrp2/fpga/eth/bench/verilog/host_sim.v @@ -0,0 +1,82 @@ +module host_sim( + input Reset, + input Clk_reg, + output reg CSB, + output reg WRB, + output reg CPU_init_end, + output reg [15:0] CD_in, + input [15:0] CD_out, + output reg [7:0] CA +); + +//////////////////////////////////////// + +task CPU_init; + begin + CA = 0; + CD_in = 0; + WRB = 1; + CSB = 1; + end +endtask + +//////////////////////////////////////// + +task CPU_wr; + input [6:0] Addr; + input [15:0] Data; + begin + CA = {Addr,1'b0}; + CD_in = Data; + WRB = 0; + CSB = 0; + #20; + CA = 0; + CD_in = 0; + WRB = 1; + CSB = 1; + #20; + end +endtask + +///////////////////////////////////////// + +task CPU_rd; + input [6:0] Addr; + begin + CA = {Addr,1'b0}; + WRB = 1; + CSB = 0; + #20; + CA = 0; + WRB = 1; + CSB = 1; + #20; + end +endtask + +///////////////////////////////////////// + +integer i; + +reg [31:0] CPU_data [255:0]; +reg [7:0] write_times; +reg [7:0] write_add; +reg [15:0] write_data; + +initial + begin + CPU_init; + CPU_init_end=0; + //$readmemh("../data/CPU.vec",CPU_data); + //{write_times,write_add,write_data}=CPU_data[0]; + {write_times,write_add,write_data}='b0; + #90; + for (i=0;i (7+6)); + assign Tx_er_Modified = Tx_er ^ ( TxError[9] & TxInPayload ); + assign Tx_en_Modified = Tx_en ^ ( TxError[8] & TxInPayload ); + assign Txd_Modified = Txd ^ ( TxError[7:0] & {8{TxInPayload}} ); + + always @( posedge Reset or posedge Tx_clk ) + if ( Reset ) + begin + InjectError <= 0; + InjectErrorDone <= 0; + TxError <= 'b0; + end + else + if ( InjectError ) + begin + TxError <= InjectError; + InjectError <= 0; + InjectErrorDone <= TxInPayload; + end + else if ( TxInPayload || InjectErrorDone ) + begin + TxError <= 8'h00; + InjectErrorDone <= 0; + end + + //------------------------------------------------------------------------- + // Track pause on Tx interface + + reg TxEnSeenOnce; + integer TxTrackPause; + + always @( posedge Reset or posedge Tx_clk ) + if ( Reset ) + begin + TxEnSeenOnce <= 0; + TxTrackPause <= 0; + end + else + if ( Tx_en ) + begin + if ( TxEnSeenOnce && (TxTrackPause >= 64) ) // 512 bits + $display( "IDLE period on Tx interface ended after %0d Tx clocks (%0d bits, tick ~ %0d)", + TxTrackPause, + (Speed == 4) ? TxTrackPause*8 : TxTrackPause*4, + (Speed == 4) ? TxTrackPause*8/512 : TxTrackPause*4/512 ); + TxEnSeenOnce <= 1; + TxTrackPause <= 0; + end + else + TxTrackPause <= TxTrackPause + 1; + + //------------------------------------------------------------------------- + // Host access routines (register read & write) + //------------------------------------------------------------------------- + + task HostInit; + begin + RST_I <= 1; + + STB_I <= 0; + CYC_I <= 0; + ADR_I <= 'b0; + WE_I <= 0; + DAT_I <= 'b0; + + #100 RST_I <= 0; + + // Wait a couple of clock edges before continuing to allow + // internal logic to get out of reset + repeat( 2 ) + @( posedge CLK_I ); + end + endtask + + task HostWriteReg; + input [6:0] Addr; + input [15:0] Data; + begin + @( posedge CLK_I ); + ADR_I <= Addr; + DAT_I <= Data; + WE_I <= 1; + STB_I <= 1; + CYC_I <= 1; + + @( posedge CLK_I ); + + while ( ~ACK_O ) + @( posedge CLK_I ); + + STB_I <= 0; + CYC_I <= 0; + end + endtask + + task HostReadReg; + input [6:0] Addr; + output [15:0] Data; + begin + @( posedge CLK_I ); + ADR_I <= Addr; + WE_I <= 0; + STB_I <= 1; + CYC_I <= 1; + + @( posedge CLK_I ); + + while ( ~ACK_O ) + @( posedge CLK_I ); + + Data = DAT_O; + STB_I <= 0; + CYC_I <= 0; + end + endtask + + //------------------------------------------------------------------------- + // User interface access routines (packet Tx and Rx) + //------------------------------------------------------------------------- + + `define FIFOSIZE 10000 + + integer FIFO_WrPtr = 0; + integer FIFO_RdPtr = 0; + integer FIFO_ElementCount = 0; + reg [35:0] FIFO_Data[0:`FIFOSIZE]; + + function FIFO_Empty; + input Dummy; + begin + if ( FIFO_ElementCount > 0 ) + FIFO_Empty = 0; + else + FIFO_Empty = 1; + end + endfunction + + function FIFO_Full; + input Dummy; + begin + if ( FIFO_ElementCount < `FIFOSIZE ) + FIFO_Full = 0; + else + FIFO_Full = 1; + end + endfunction + + task FIFO_Wr; + input [35:0] Data; + + begin + if ( !FIFO_Full(0) ) + begin + FIFO_Data[ FIFO_WrPtr ] = Data; + FIFO_WrPtr = (FIFO_WrPtr + 1) % `FIFOSIZE; + FIFO_ElementCount = FIFO_ElementCount + 1; + end + else + begin + $display( "ERROR: FIFO_Wr() - FIFO overflow!" ); + Error = 1; + $finish; + end + end + endtask + + task FIFO_Rd; + output [35:0] Data; + + begin + if ( !FIFO_Empty(0) ) + begin + Data = FIFO_Data[ FIFO_RdPtr ]; + FIFO_RdPtr = (FIFO_RdPtr + 1) % `FIFOSIZE; + FIFO_ElementCount = FIFO_ElementCount - 1; + end + else + begin + $display( "ERROR: FIFO_Rd() - Reading from empty FIFO!" ); + Error = 1; + $finish; + end + end + endtask + + //------------------------------------------------------------------------- + + `define TXDATALEN 8000 + reg [7:0] TxData[0:`TXDATALEN-1]; + reg [7:0] TxAltData[0:`TXDATALEN-1]; + + // By default change payload after Ethernet Header + reg [15:0] TxHeaderLength = 14; + + real TxStartTime; + integer TxPacketCount = 0; + integer TxByteCount; + + task SendPacket; + input [15:0] Length; + // 0: Don't write to FIFO, 1: Write to FIFO, 2: Write Alternate to FIFO, 3: Write IGNORE to FIFO + input [1:0] Wr2FIFO; + + reg [15:0] Counter; + integer TxIndex; + integer i; + + reg [31:0] Tx_fifo_data; + + begin + @( posedge Clk_user ); #1; + + TxPacketCount = TxPacketCount + 1; + TxByteCount = TxByteCount + Length; + + Counter=Length; + TxIndex = 0; + Tx_mac_sop = 1; // First time + + if ( TxStartTime == 0 ) + TxStartTime = $realtime; + + while ( Counter>0 ) + begin + while ( !Tx_mac_wa ) + begin + Tx_mac_wr = 0; + @( posedge Clk_user ); #1; + end + + Tx_mac_data[31:24] = TxData[ TxIndex ]; + Tx_mac_data[23:16] = TxData[ TxIndex+1 ]; + Tx_mac_data[15:8] = TxData[ TxIndex+2 ]; + Tx_mac_data[ 7:0] = TxData[ TxIndex+3 ]; + + // Default take data from regular tx buffer + Tx_fifo_data = Tx_mac_data; + if ( Wr2FIFO==2 ) + begin + // Put content of Alternate Tx buffer on Rx expectancy queue + if ( (TxIndex+0)= TxHeaderLength ) + TxData[ TxIndex ] = TxData[ TxIndex ] + 1; + TxIndex = TxIndex+1; + end + + if ( Counter<=4 ) + begin + // Indicate how many bytes are valid + if ( Counter==4 ) + Tx_mac_BE = 2'b00; + else + Tx_mac_BE = Counter; + Tx_mac_eop = 1; + end + else + begin + Tx_mac_BE = 2'b00; + Tx_mac_eop = 0; + end + + casez ( Wr2FIFO ) + 1, + 2: FIFO_Wr( { Tx_mac_sop, Tx_mac_eop, Tx_mac_BE, Tx_fifo_data } ); + 3: // Ignore + begin + FIFO_Wr( { 2'b11, 2'b00, 32'h00000000 } ); + Wr2FIFO = 0; + end + endcase + + Tx_mac_wr = 1; + + if ( Counter >= 4 ) + Counter = Counter - 4; + else + Counter = 0; + @( posedge Clk_user ); #1; + Tx_mac_sop = 0; + end + + Tx_mac_sop = 1'bx; + Tx_mac_eop = 1'bx; + Tx_mac_wr = 0; + Tx_mac_data = 32'bx; + Tx_mac_BE = 2'bx; + end + endtask + + //------------------------------------------------------------------------- + + reg Negate_Rx_mac_rd; + + always @( posedge Clk_user or posedge Reset ) + if ( Reset ) + Rx_mac_rd <= 0; + else if ( Rx_mac_ra & ~Negate_Rx_mac_rd ) + Rx_mac_rd <= 1; + else + Rx_mac_rd <= 0; + + real RxStartTime; + integer RxPacketCount; + integer RxByteCount; + + reg InPacket; + integer RxPacketLength; + reg IgnoreUntilNextERR; + + always @( posedge Clk_user or posedge Reset ) + if ( Reset ) + begin + InPacket = 0; + RxPacketCount = 0; + Negate_Rx_mac_rd <= 0; + IgnoreUntilNextERR = 0; + end + else + begin + Negate_Rx_mac_rd <= 0; + + if ( Rx_mac_pa ) + begin : RxWord + reg [35:0] RxData; + reg [35:0] Expected; + reg [35:0] Mask; + + RxData = { Rx_mac_sop, Rx_mac_eop, Rx_mac_BE, Rx_mac_data }; + casez ( Rx_mac_BE ) + 2'b01: Mask = 36'hfff000000; + 2'b10: Mask = 36'hfffff0000; + 2'b11: Mask = 36'hfffffff00; + default: Mask = 36'hfffffffff; + endcase + + // Retrieve expected packet data + + if ( !IgnoreUntilNextERR ) + begin + FIFO_Rd( Expected ); + if ( Expected[35] & Expected[34] ) + begin + // Both SOP & EOP are asserted in expectancy data + // - this means that we should ignore all data received until next EOP + $display( "The payload of this packet will be IGNORED - and an ERROR must be signalled!" ); + IgnoreUntilNextERR = 1; + end + end + if ( IgnoreUntilNextERR ) + Mask = 36'h000000000; + + //$display( "DEBUG: RxData=0x%0x, Expected=0x%0x", RxData, Expected ); + + if ( (RxData & Mask) !== (Expected & Mask) ) + begin + $display( "ERROR: Receiving unexpected packet data: Got 0x%0x, expected 0x%0x (Mask=0x%0x)", + RxData, Expected, Mask ); + Error = 1; + end + + if ( InPacket ) + begin + if ( Rx_mac_eop ) + begin + // Ensure Rx_mac_rd is negated for one clock + Negate_Rx_mac_rd <= 1; + if ( Rx_mac_BE==2'b00 ) + RxPacketLength = RxPacketLength + 4; + else + RxPacketLength = RxPacketLength + Rx_mac_BE; + $display( "Rx packet #%0d of length %0d ends", + RxPacketCount, + RxPacketLength ); + RxPacketCount = RxPacketCount + 1; + RxByteCount = RxByteCount + RxPacketLength; + InPacket = 0; + end + else + RxPacketLength = RxPacketLength + 4; + end + else + begin + if ( Rx_mac_sop ) + begin + RxPacketLength = 4; + $display( "Rx packet #%0d begins: 0x%08x", RxPacketCount, Rx_mac_data ); + InPacket = 1; + if ( RxStartTime == 0 ) + RxStartTime = $realtime; + end + else + begin + $display( "ERROR: Unexpectedly reading from Rx FIFO while not receiving a packet!" ); + Error = 1; + end + end + + if ( Rx_mac_err ) + begin + if ( !Rx_mac_eop ) + begin + $display( "ERROR: Rx_mac_err was asserted without Rx_mac_eop also being asserted!" ); + Error = 1; + end + if ( IgnoreUntilNextERR ) + $display( "Info: Rx_mac_err was asserted as expected!" ); + else + begin + $display( "ERROR: Rx_mac_err was unexpectedly asserted!" ); + Error = 1; + end + IgnoreUntilNextERR = 0; + end + end + end + + //------------------------------------------------------------------------- + // Script handling + //------------------------------------------------------------------------- + + integer PC; + + task ScriptWriteReg; + input [15:0] Addr; + input [15:0] Data; + + begin + $display( "WriteReg( 0x%04x, 0x%04x )", Addr, Data ); + HostWriteReg( Addr, Data ); + end + endtask + + task ScriptReadReg; + input [15:0] Addr; + + reg [15:0] Data; + + begin + $write( "ReadReg( 0x%04x ): ", Addr ); + HostReadReg( Addr, Data ); + $display( "0x%04x", Data ); + end + endtask + + task ScriptReadRegAndMatch; + input [15:0] Addr; + input [15:0] Data; + input [15:0] Mask; + + reg [15:0] Read; + + begin + $write( "ReadRegAndMatch( 0x%04x, 0x%04x, 0x%04x ): ", Addr, Data, Mask ); + + HostReadReg( Addr, Read ); + $display( "0x%04x, masked=0x%04x", Read, Read & Mask ); + + if ( Data !== (Read & Mask) ) + begin + $display( "Error: Unexpected data read" ); + Error = 1; + end + end + endtask + + integer RxExpectPacketCount = 0; + + task ScriptSendPacket; + input [15:0] Length; + // 0: Don't receive, 1: Receive & match, 2: Receive & match alternate, 3: Receive & ignore + input [1:0] ExpectToRx; + + begin + $display( "ScriptSendPacket( 0x%04x, %0d )", Length, ExpectToRx ); + SendPacket( Length, ExpectToRx ); + if ( ExpectToRx != 0 ) + RxExpectPacketCount = RxExpectPacketCount + 1; + end + endtask + + `define SCRIPTLEN 10000 + integer i; + reg [7:0] Script[0:`SCRIPTLEN-1]; + + function [15:0] Get16bit; + input Dummy; + + reg [15:0] Data; + + begin + Data[15:8] = Script[PC]; + Data[7:0] = Script[PC+1]; + PC = PC+2; + + Get16bit = Data; + end + endfunction + + task ExecuteScript; + + reg [7:0] OpCode; + reg [15:0] Addr; + reg [15:0] Data; + reg [15:0] Length; + reg [15:0] Count; + reg [15:0] Mask; + + reg ScriptDone; + + begin + ScriptDone = 0; + Error = 0; + PC = 0; + + while ( !ScriptDone ) + begin + OpCode = Script[PC]; + //$write( "PC=%0d, OpCode=%02x: ", PC, OpCode ); + PC = PC+1; + + casez ( OpCode ) + 8'h00: // NOP + begin +// $display( "NOP" ); + #10; + end + 8'h01: // Write + begin + Addr = Get16bit(i); + Data = Get16bit(i); + ScriptWriteReg( Addr, Data ); + end + 8'h02: // Read + begin + Addr = Get16bit(i); + ScriptReadReg( Addr ); + end + 8'h03: // Read & match + begin + Addr = Get16bit(i); + Data = Get16bit(i); + Mask = Get16bit(i); + ScriptReadRegAndMatch( Addr, Data, Mask ); + end + + 8'h0f: // Delay + begin + Count = Get16bit(i); + $display( "Delay %0d", Count ); + while ( Count > 0 ) + begin + #10; + Count = Count - 1; + end + end + + 8'h10: // Setup Tx Data + begin + Addr = Get16bit(i); + Length = Get16bit(i); + $write( "TxData( 0x%04x ), length=%0d: ", Addr, Length ); + while ( Length != 0 ) + begin + TxData[Addr] = Script[PC]; + $write( " 0x%02x", Script[PC] ); + PC = PC + 1; + Addr = Addr + 1; + Length = Length - 1; + end + $display( "" ); + end + + 8'h11: // Setup Alternative Tx Data + begin + Addr = Get16bit(i); + Length = Get16bit(i); + $write( "TxAltData( 0x%04x ), length=%0d: ", Addr, Length ); + while ( Length != 0 ) + begin + TxAltData[Addr] = Script[PC]; + $write( " 0x%02x", Script[PC] ); + PC = PC + 1; + Addr = Addr + 1; + Length = Length - 1; + end + $display( "" ); + end + + 8'h20: // Transmit packet - and put it on Rx expectancy queue + begin + Length = Get16bit(i); // Length in bytes + Count = Get16bit(i); // Number of times + while ( Count != 0 ) + begin + ScriptSendPacket( Length, 1 ); + Count = Count - 1; + end + end + + 8'h21: // Transmit packet - but DON'T put it on Rx expectancy queue + begin + Length = Get16bit(i); // Length in bytes + Count = Get16bit(i); // Number of times + while ( Count != 0 ) + begin + ScriptSendPacket( Length, 0 ); + Count = Count - 1; + end + end + + 8'h22: // Wait + begin : OpCode22 + reg NoTimeOut; + Count = Get16bit(i); // Timeout in ns + if ( Count==0 ) + NoTimeOut = 1; + else + NoTimeOut = 0; + + $display( "Waiting for # of Rx packets = # of Tx packets..." ); + $display( "Timeout = %0d ns - Current # Rx =%0d, Expected=%0d", + Count, RxPacketCount, RxExpectPacketCount ); + + while( (NoTimeOut || (Count != 0)) && ( RxExpectPacketCount != RxPacketCount ) && !Error ) + begin + #1; + if ( !NoTimeOut ) + Count = Count - 1; + //$display( "NoTimeOut=%0d, Count=%0d", NoTimeOut, Count ); + end + + if ( !Error ) + if ( RxExpectPacketCount != RxPacketCount ) + begin + $display( "ERROR: Timeout waiting for Rx packet(s)!" ); + ScriptDone = 1; + Error = 1; + end + else + $display( "...Done waiting (time remaining = %0d ns)!", Count ); + end + + 8'h23: // Inject bit error in Tx packet + begin + InjectError = Get16bit(i); // Get bit error pattern + $display( "Injecting a single bit-error in Tx packet: TxEr=%0d, TxEn=%0d, TxD=0x%02h (0x%03h)", + InjectError[9], InjectError[8], InjectError[7:0], InjectError ); + end + + 8'h24: // Store internally generated PAUSE frame in Rx expect queue + begin + Count = Get16bit(i); // Timeout in ns + $display( "Generating PAUSE frame (tick=%0d) on Rx expect queue", Count ); + RxExpectPacketCount = RxExpectPacketCount + 1; + FIFO_Wr( { 1'b1, 1'b0, 2'b00, 32'h0180c200 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 16'h0001, 16'h0000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h88080001 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, Count, 16'h0000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } ); + FIFO_Wr( { 1'b0, 1'b1, 2'b00, 32'h00000000 } ); + end + + 8'h25: // Transmit packet - and indicate that it must be IGNORED upon reception + begin + Length = Get16bit(i); // Length in bytes + Count = Get16bit(i); // Number of times + while ( Count != 0 ) + begin + ScriptSendPacket( Length, 3 ); + Count = Count - 1; + end + end + + 8'h26: // Transmit packet - and put it on expectancy queue with Alternate header! + begin + Length = Get16bit(i); // Length in bytes + Count = Get16bit(i); // Number of times + while ( Count != 0 ) + begin + ScriptSendPacket( Length, 2 ); + Count = Count - 1; + end + end + + 8'hff: // Halt + begin + $display( "HALT" ); + ScriptDone = 1; + Done = 1; + end + + default: // Unknown opcode + begin + $display( "Unknown instruction encountered @ PC=%0d: OpCode=0x%02x", PC-1, OpCode ); + Error = 1; + end + + endcase + + if ( Error ) + begin + ScriptDone = 1; + Done = 1; + end + end + + if ( Error ) + $display( "ERROR: Test failed!"); + else + begin : ScriptSuccess + real TxTimeElapsed; + real RxTimeElapsed; + real ReferenceTime; + + ReferenceTime = $realtime; + #1; + ReferenceTime = $realtime - ReferenceTime; + + TxTimeElapsed = $realtime - TxStartTime; + RxTimeElapsed = $realtime - RxStartTime; + + $display( "TxStartTime=%0e, Now=%0e", TxStartTime, $realtime ); + $display( "RxStartTime=%0e, Now=%0e", RxStartTime, $realtime ); + + $display( "Tx stats: %0d packet(s) send, total of %0d bytes in %0e ns ~ %1.2f Mbps", + TxPacketCount, TxByteCount, TxTimeElapsed, TxByteCount*8*1e3/TxTimeElapsed ); + $display( "Rx stats: %0d packet(s) received, total of %0d bytes in %0e ns ~ %1.2f Mbps", + RxPacketCount, RxByteCount, RxTimeElapsed, RxByteCount*8*1e3/RxTimeElapsed ); + $display( "Test succeeded!"); + end + + end + endtask + + //------------------------------------------------------------------------- + // Generate all clocks + //------------------------------------------------------------------------- + + // GMII master clock (125 MHz) + initial + begin + #10; + while ( !Done ) + begin + #4 Clk_125M = 0; + #4 Clk_125M = 1; + end + end + + // User (packet) interface clock (100 MHz) + initial + begin + #10; + while ( !Done ) + begin + #5 Clk_user = 0; + #5 Clk_user = 1; + end + end + + // Wishbone host interface clock (50 MHz) + initial + begin + #10; + while ( !Done ) + begin + #10 CLK_I = 0; + #10 CLK_I = 1; + end + end + + //------------------------------------------------------------------------- + + initial + begin + if ( $test$plusargs( "vcd" ) ) + begin + $display( "Turning VCD data dump on" ); + $dumpfile(); + $dumpvars( 0 ); // Dump all signals in entire design + end + end + + //------------------------------------------------------------------------- + + reg [1023:0] ScriptFile; + + initial + begin + HostInit; + + TxStartTime = 0; + RxStartTime = 0; + TxByteCount = 0; + RxByteCount = 0; + + for ( i=0; i<`TXDATALEN; i=i+1 ) + TxData[i] = (i & 8'hff); + + // Fill script memory with HALTs + for ( i=0; i<`SCRIPTLEN; i=i+1 ) + Script[i] = 8'hff; + + if ( !$value$plusargs( "script=%s", ScriptFile ) ) + begin + $display( "Using default script file" ); + ScriptFile = "test.scr"; + end + + $readmemh( ScriptFile, Script ); + +// for ( i=0; i<40; i=i+1 ) +// $display( "Script[%0d]=0x%02x", i, Script[i] ); + + #10; + + ExecuteScript; + end + +endmodule diff --git a/usrp2/fpga/eth/bench/verilog/test.scr b/usrp2/fpga/eth/bench/verilog/test.scr new file mode 100644 index 00000000..2ad127d3 --- /dev/null +++ b/usrp2/fpga/eth/bench/verilog/test.scr @@ -0,0 +1,23 @@ +// This tests just runs trough a couple of different packet lengths + +// Read from register 24 to confirm that Rx CRC check is enabled +03 00 18 00 01 ff ff + +// Set speed to 1000 Mbps +01 00 22 00 04 + +// Setup Tx and Rx MAC addresses and type field to "IP" +// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800 +10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00 + +// Transmit a 320-byte frame 1 time - and expect it to be received again! +20 01 40 00 01 + +// Transmit a 80-byte frame 1 time - and expect it to be received again! +20 00 50 00 01 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Halt +FF diff --git a/usrp2/fpga/eth/bench/verilog/txmac.scr b/usrp2/fpga/eth/bench/verilog/txmac.scr new file mode 100644 index 00000000..caa7db59 --- /dev/null +++ b/usrp2/fpga/eth/bench/verilog/txmac.scr @@ -0,0 +1,93 @@ +// Read from register 24 to confirm that Rx CRC check is enabled +03 00 18 00 01 ff ff + +// Set speed to 1000 Mbps +01 00 22 00 04 + +// Write MAC address 12 35 56 78 9A BC to Rx Address buffer +01 00 10 00 00 +01 00 0f 00 12 +01 00 11 00 01 +01 00 11 00 00 +01 00 10 00 01 +01 00 0f 00 34 +01 00 11 00 01 +01 00 11 00 00 +01 00 10 00 02 +01 00 0f 00 56 +01 00 11 00 01 +01 00 11 00 00 +01 00 10 00 03 +01 00 0f 00 78 +01 00 11 00 01 +01 00 11 00 00 +01 00 10 00 04 +01 00 0f 00 9A +01 00 11 00 01 +01 00 11 00 00 +01 00 10 00 05 +01 00 0f 00 BC +01 00 11 00 01 +01 00 11 00 00 + +// Write 1 to register 14, MAC_rx_add_chk_en +// This turns on the Rx Destination MAC address filter +01 00 0e 00 01 + +// Setup Tx and Rx MAC addresses and type field to "IP" +// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800 +// (i.e. Destination MAC address is 123456789ABC matching the above) +10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00 + +// Setup Alternate Tx and Rx MAC addresses and type field to "IP" +// Set Tx Data at offset 0, length 14 to 123456789ABC 112233445566 0800 +// (i.e. Destination MAC address is 123456789ABC matching the above) +11 00 00 00 0E 12 34 56 78 9A BC 11 22 33 44 55 66 08 00 + +// Transmit a 60-byte frame 3 times - and expect them to be received again! +20 00 3C 00 03 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Write MAC address 11 22 33 44 55 66 to Tx MAC Source Address buffer +01 00 09 00 00 +01 00 08 00 11 +01 00 0a 00 01 +01 00 0a 00 00 +01 00 09 00 01 +01 00 08 00 22 +01 00 0a 00 01 +01 00 0a 00 00 +01 00 09 00 02 +01 00 08 00 33 +01 00 0a 00 01 +01 00 0a 00 00 +01 00 09 00 03 +01 00 08 00 44 +01 00 0a 00 01 +01 00 0a 00 00 +01 00 09 00 04 +01 00 08 00 55 +01 00 0a 00 01 +01 00 0a 00 00 +01 00 09 00 05 +01 00 08 00 66 +01 00 0a 00 01 +01 00 0a 00 00 + +// Transmit a 60 byte frame 3 times - and expect them to be received again! +20 00 3C 00 03 + +// Wait (indefinitely) for missing Rx packets +22 00 00 + +// Write 1 to register 7, MAC_tx_add_en +// This turns on the Tx Source MAC address replacement mechanism +01 00 07 00 01 + +// Transmit a 60 byte frame 3 times - and expect them to be received again with Alternate header! +26 00 3C 00 03 + +// Wait (indefinitely) for missing Rx packets +22 00 00 diff --git a/usrp2/fpga/eth/bench/verilog/xlnx_glbl.v b/usrp2/fpga/eth/bench/verilog/xlnx_glbl.v new file mode 100644 index 00000000..662a60e3 --- /dev/null +++ b/usrp2/fpga/eth/bench/verilog/xlnx_glbl.v @@ -0,0 +1,29 @@ +module xlnx_glbl +( + GSR, + GTS +); + + //-------------------------------------------------------------------------- + // Parameters + //-------------------------------------------------------------------------- + + //-------------------------------------------------------------------------- + // IO declarations + //-------------------------------------------------------------------------- + + output GSR; + output GTS; + + //-------------------------------------------------------------------------- + // Local declarations + //-------------------------------------------------------------------------- + + //-------------------------------------------------------------------------- + // Internal declarations + //-------------------------------------------------------------------------- + + assign GSR = 0; + assign GTS = 0; + +endmodule diff --git a/usrp2/fpga/eth/demo/verilog/RAMB16_S1_S2.v b/usrp2/fpga/eth/demo/verilog/RAMB16_S1_S2.v new file mode 100644 index 00000000..758760b9 --- /dev/null +++ b/usrp2/fpga/eth/demo/verilog/RAMB16_S1_S2.v @@ -0,0 +1,1535 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S2.v,v 1.10 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 2'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [1:0] DOB; + reg [1:0] dob_out; + wire dob_out0, dob_out1; + + input [12:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [12:0] addrb_int; + reg [12:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[0:0]; + assign dob_out = INIT_B[1:0]; + end + else begin + deassign doa_out; + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_addra_13 (addra_int[13], ADDRA[13]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_addrb_11 (addrb_int[11], ADDRB[11]); + buf b_addrb_12 (addrb_int[12], ADDRB[12]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 2; + assign data_addrb_reg = addrb_reg * 2; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:1] == data_addrb_int[14:1])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:1] == data_addrb_int[14:1])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:1] == data_addrb_reg[14:1])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:1] == data_addrb_int[14:1]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[0 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_reg[0 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[0 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S2.v,v 1.10 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 2'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [1:0] DOB; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [12:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [0:0] doa_out = INIT_A[0:0]; + reg [1:0] dob_out = INIT_B[1:0]; + + reg [1:0] mem [8191:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [12:0] addrb_int; + reg [12:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [13:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [1:0] (DOB, dob_out); + buf b_addrb [12:0] (addrb_int, ADDRB); + buf b_dib [1:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 128; count = count + 1) begin + mem[count] = INIT_00[(count * 2) +: 2]; + mem[128 * 1 + count] = INIT_01[(count * 2) +: 2]; + mem[128 * 2 + count] = INIT_02[(count * 2) +: 2]; + mem[128 * 3 + count] = INIT_03[(count * 2) +: 2]; + mem[128 * 4 + count] = INIT_04[(count * 2) +: 2]; + mem[128 * 5 + count] = INIT_05[(count * 2) +: 2]; + mem[128 * 6 + count] = INIT_06[(count * 2) +: 2]; + mem[128 * 7 + count] = INIT_07[(count * 2) +: 2]; + mem[128 * 8 + count] = INIT_08[(count * 2) +: 2]; + mem[128 * 9 + count] = INIT_09[(count * 2) +: 2]; + mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2]; + mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2]; + mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2]; + mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2]; + mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2]; + mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2]; + mem[128 * 16 + count] = INIT_10[(count * 2) +: 2]; + mem[128 * 17 + count] = INIT_11[(count * 2) +: 2]; + mem[128 * 18 + count] = INIT_12[(count * 2) +: 2]; + mem[128 * 19 + count] = INIT_13[(count * 2) +: 2]; + mem[128 * 20 + count] = INIT_14[(count * 2) +: 2]; + mem[128 * 21 + count] = INIT_15[(count * 2) +: 2]; + mem[128 * 22 + count] = INIT_16[(count * 2) +: 2]; + mem[128 * 23 + count] = INIT_17[(count * 2) +: 2]; + mem[128 * 24 + count] = INIT_18[(count * 2) +: 2]; + mem[128 * 25 + count] = INIT_19[(count * 2) +: 2]; + mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2]; + mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2]; + mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2]; + mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2]; + mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2]; + mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2]; + mem[128 * 32 + count] = INIT_20[(count * 2) +: 2]; + mem[128 * 33 + count] = INIT_21[(count * 2) +: 2]; + mem[128 * 34 + count] = INIT_22[(count * 2) +: 2]; + mem[128 * 35 + count] = INIT_23[(count * 2) +: 2]; + mem[128 * 36 + count] = INIT_24[(count * 2) +: 2]; + mem[128 * 37 + count] = INIT_25[(count * 2) +: 2]; + mem[128 * 38 + count] = INIT_26[(count * 2) +: 2]; + mem[128 * 39 + count] = INIT_27[(count * 2) +: 2]; + mem[128 * 40 + count] = INIT_28[(count * 2) +: 2]; + mem[128 * 41 + count] = INIT_29[(count * 2) +: 2]; + mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2]; + mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2]; + mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2]; + mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2]; + mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2]; + mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2]; + mem[128 * 48 + count] = INIT_30[(count * 2) +: 2]; + mem[128 * 49 + count] = INIT_31[(count * 2) +: 2]; + mem[128 * 50 + count] = INIT_32[(count * 2) +: 2]; + mem[128 * 51 + count] = INIT_33[(count * 2) +: 2]; + mem[128 * 52 + count] = INIT_34[(count * 2) +: 2]; + mem[128 * 53 + count] = INIT_35[(count * 2) +: 2]; + mem[128 * 54 + count] = INIT_36[(count * 2) +: 2]; + mem[128 * 55 + count] = INIT_37[(count * 2) +: 2]; + mem[128 * 56 + count] = INIT_38[(count * 2) +: 2]; + mem[128 * 57 + count] = INIT_39[(count * 2) +: 2]; + mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2]; + mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2]; + mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2]; + mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2]; + mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2]; + mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2]; + end + + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 2; + assign data_addrb_reg = addrb_reg * 2; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:1] == data_addrb_int[14:1])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:1] == data_addrb_int[14:1])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:1] == data_addrb_reg[14:1])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:1] == data_addrb_int[14:1]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= 1'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[13:1]][addra_reg[0:0] * 1 +: 1] <= 1'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= 1'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[0:0] * 1 +: 1] <= #100 1'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[0:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[0:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/usrp2/fpga/eth/demo/verilog/demo.ucf b/usrp2/fpga/eth/demo/verilog/demo.ucf new file mode 100644 index 00000000..f3562b46 --- /dev/null +++ b/usrp2/fpga/eth/demo/verilog/demo.ucf @@ -0,0 +1,52 @@ +NET "Reset_n" LOC = "C15"; // PushButton #4 +NET "Clk_100M" LOC = "B15"; +NET "Clk_125M" LOC = "A16"; // GMII only + +NET "RS232_TXD" LOC = "A9"; +NET "RS232_RXD" LOC = "F1"; + +NET "USB_TXD" LOC = "D1"; +NET "USB_RXD" LOC = "A8"; + +NET "PHY_RESET_n" LOC = "E25"; + +NET "PHY_RXC" LOC = "B13"; +NET "PHY_RXD<0>" LOC = "D16"; +NET "PHY_RXD<1>" LOC = "C16"; +NET "PHY_RXD<2>" LOC = "D15"; +NET "PHY_RXD<3>" LOC = "D14"; +NET "PHY_RXD<4>" LOC = "E14"; +NET "PHY_RXD<5>" LOC = "F14"; +NET "PHY_RXD<6>" LOC = "F11"; +NET "PHY_RXD<7>" LOC = "F12"; +NET "PHY_RXDV" LOC = "F13"; +NET "PHY_RXER" LOC = "E13"; + +NET "PHY_GTX_CLK" LOC = "C26"; // GMII only +NET "PHY_TXC" LOC = "A10"; +NET "PHY_TXD<0>" LOC = "H26"; +NET "PHY_TXD<1>" LOC = "H24"; +NET "PHY_TXD<2>" LOC = "G26"; +NET "PHY_TXD<3>" LOC = "G24"; +NET "PHY_TXD<4>" LOC = "F26"; +NET "PHY_TXD<5>" LOC = "F24"; +NET "PHY_TXD<6>" LOC = "E26"; +NET "PHY_TXD<7>" LOC = "E24"; +NET "PHY_TXEN" LOC = "D26"; +NET "PHY_TXER" LOC = "D24"; + +NET "PHY_COL" LOC = "B24"; +NET "PHY_CRS" LOC = "D25"; + +NET "PHY_MDC" LOC = "G25"; +NET "PHY_MDIO" LOC = "H25"; + +NET "LED<1>" LOC = "D13"; // LED #1-4 +NET "LED<2>" LOC = "D12"; +NET "LED<3>" LOC = "C11"; +NET "LED<4>" LOC = "D11"; + +NET "Clk_100M" PERIOD = 10.000 ; # 100 MHz +NET "Clk_125M" PERIOD = 8.000 ; # 125 MHz +NET "PHY_RXC" PERIOD = 8.000 ; # 125 MHz +NET "PHY_TXC" PERIOD = 8.000 ; # 125 MHz diff --git a/usrp2/fpga/eth/demo/verilog/demo.v b/usrp2/fpga/eth/demo/verilog/demo.v new file mode 100644 index 00000000..649903c9 --- /dev/null +++ b/usrp2/fpga/eth/demo/verilog/demo.v @@ -0,0 +1,378 @@ +module demo( + Reset_n, + Clk_100M, + Clk_125M, // GMII only + + RS232_TXD, + RS232_RXD, + + USB_TXD, + USB_RXD, + + //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII) + PHY_RESET_n, + + PHY_RXC, + PHY_RXD, + PHY_RXDV, + PHY_RXER, + + PHY_GTX_CLK, // GMII only + PHY_TXC, + PHY_TXD, + PHY_TXEN, + PHY_TXER, + + PHY_COL, + PHY_CRS, + + PHY_MDC, + PHY_MDIO, + + // Misc. I/Os + LED, + Button +); + + input Reset_n; + input Clk_100M; + input Clk_125M; // GMII + + output RS232_TXD; + input RS232_RXD; + + output USB_TXD; + input USB_RXD; + + //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII) + output PHY_RESET_n; + + input PHY_RXC; + input [7:0] PHY_RXD; + input PHY_RXDV; + input PHY_RXER; + + output PHY_GTX_CLK; // GMII only + input PHY_TXC; + output [7:0] PHY_TXD; + output PHY_TXEN; + output PHY_TXER; + + input PHY_COL; + input PHY_CRS; + + output PHY_MDC; + inout PHY_MDIO; + + // Misc. I/Os + output [1:4] LED; + + input [1:4] Button; + + //------------------------------------------------------------------------- + // Local declarations + //------------------------------------------------------------------------- + + // Rename to "standard" core clock name + wire Clk = Clk_100M; + + reg [27:0] Counter; + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + Counter <= 0; + else + Counter <= Counter + 1; + + assign LED[1:4] = Counter[27:24]; + + //------------------------------------------------------------------------- + // Instantiation of sub-modules + //------------------------------------------------------------------------- + + //--- UART ---------------------------------------------------------------- + + wire UART_RXD; + wire UART_TXD; + wire UART_RxValid; + wire [7:0] UART_RxData; + wire UART_TxReady; + wire UART_TxValid; + wire [7:0] UART_TxData; + + demo_uart demo_uart( + .Reset_n( Reset_n ), + .Clk ( Clk ), + + // Interface to UART PHY + .RXD_i( UART_RXD ), + .TXD_o( UART_TXD ), + + // Clk is divided by (Prescaler+1) to generate 16x the bitrate +`ifdef EHDL_SIMULATION + .Prescaler_i( 16'd3 ), // Corresponds to VERY FAST - for simulation only! +`else + .Prescaler_i( 16'd650 ), // Corresponds to 9600 baud (assuming 100 MHz clock) +`endif + + // Pulsed when RxData is valid + .RxValid_o( UART_RxValid ), + .RxData_o ( UART_RxData ), + + // Asserted when ready for a new Tx byte + .TxReady_o( UART_TxReady ), + + // Pulsed when TxData is valid + .TxValid_i( UART_TxValid ), + .TxData_i ( UART_TxData ) + ); + + // Transmit & receive in parallel on either RS232 or USB/RS232 interface +// assign UART_RXD = RS232_RXD & USB_RXD; // RS232 signals are high when inactive + assign UART_RXD = RS232_RXD; + + assign RS232_TXD = UART_TXD; + assign USB_TXD = UART_TXD; + + //--- UART-to-Wishbone Master --------------------------------------------- + + wire WB_STB_ETH; + wire WB_STB_PDM; + wire WB_STB_PG; + wire WB_CYC; + wire [14:0] WB_ADR; + wire WB_WE; + wire [15:0] WB_DAT_Wr; + wire [15:0] WB_DAT_Rd; + wire WB_ACK; + + demo_wishbone_master demo_wishbone_master( + .Reset_n( Reset_n ), + .Clk ( Clk ), + + //--- UART interface + + // Pulsed when RxData_i is valid + .RxValid_i( UART_RxValid ), + .RxData_i ( UART_RxData ), + + // Asserted when ready for a new Tx byte + .TxReady_i( UART_TxReady ), + + // Pulsed when TxData_o is valid + .TxValid_o( UART_TxValid ), + .TxData_o ( UART_TxData ), + + //--- Wishbone interface + .STB_ETH_O( WB_STB_ETH ), + .STB_PDM_O( WB_STB_PDM ), + .STB_PG_O ( WB_STB_PG ), + .CYC_O ( WB_CYC ), + .ADR_O ( WB_ADR ), + .WE_O ( WB_WE ), + .DAT_O ( WB_DAT_Wr ), + .DAT_I ( WB_DAT_Rd ), + .ACK_I ( WB_ACK ) + ); + + //--- Wishbone clients ---------------------------------------------------- + + //--- Packet Descriptor Memory -------------------------------------------- + + wire [15:0] WB_DAT_Rd_PDM; + wire WB_ACK_PDM; + + wire PDM_Rd; + wire [13:0] PDM_Addr; + wire [31:0] PDM_RdData; + + demo_packet_descriptor_memory demo_packet_descriptor_memory( + .Reset_n( Reset_n ), + .Clk ( Clk ), + + //--- Wishbone interface + .STB_I( WB_STB_PDM ), + .CYC_I( WB_CYC ), + .ADR_I( WB_ADR ), + .WE_I ( WB_WE ), + .DAT_I( WB_DAT_Wr ), + .DAT_O( WB_DAT_Rd_PDM ), + .ACK_O( WB_ACK_PDM ), + + //--- Packet Generator interface + // RdData_o is always valid exactly one clock after Addr_i changes + // and Rd_i is asserted + .Rd_i ( PDM_Rd ), + .Addr_i ( PDM_Addr ), + .RdData_o( PDM_RdData ) + ); + + //--- Packet Generator ---------------------------------------------------- + + wire [15:0] WB_DAT_Rd_PG; + wire WB_ACK_PG; + + wire Rx_mac_ra; + wire Rx_mac_rd; + wire [31:0] Rx_mac_data; + wire [1:0] Rx_mac_BE; + wire Rx_mac_pa; + wire Rx_mac_sop; + wire Rx_mac_err; + wire Rx_mac_eop; + + wire Tx_mac_wa; + wire Tx_mac_wr; + wire [31:0] Tx_mac_data; + wire [1:0] Tx_mac_BE; + wire Tx_mac_sop; + wire Tx_mac_eop; + + demo_packet_generator demo_packet_generator( + .Reset_n( Reset_n ), + .Clk ( Clk ), + + //--- Wishbone interface + .STB_I( WB_STB_PG ), + .CYC_I( WB_CYC ), + .ADR_I( WB_ADR[1:0] ), + .WE_I ( WB_WE ), + .DAT_I( WB_DAT_Wr ), + .DAT_O( WB_DAT_Rd_PG ), + .ACK_O( WB_ACK_PG ), + + //--- Packet Descriptor Memory interface + // RdData_i is always valid exactly one clock after Addr_o changes + // and Rd_o is asserted + .Rd_o ( PDM_Rd ), + .Addr_o ( PDM_Addr ), + .RdData_i( PDM_RdData ), + + //--- User (packet) interface + .Rx_mac_ra ( Rx_mac_ra ), + .Rx_mac_rd ( Rx_mac_rd ), + .Rx_mac_data( Rx_mac_data ), + .Rx_mac_BE ( Rx_mac_BE ), + .Rx_mac_pa ( Rx_mac_pa ), + .Rx_mac_sop ( Rx_mac_sop ), + .Rx_mac_err ( Rx_mac_err ), + .Rx_mac_eop ( Rx_mac_eop ), + + .Tx_mac_wa ( Tx_mac_wa ), + .Tx_mac_wr ( Tx_mac_wr ), + .Tx_mac_data( Tx_mac_data ), + .Tx_mac_BE ( Tx_mac_BE ), + .Tx_mac_sop ( Tx_mac_sop ), + .Tx_mac_eop ( Tx_mac_eop ) + ); + + //--- Simple Wishbone client ---------------------------------------------- + + reg [15:0] Reg1; + reg [15:0] Reg2; + + reg WB_ACK_Reg; + reg [15:0] WB_DAT_Reg; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + WB_ACK_Reg <= 0; + WB_DAT_Reg <= 'b0; + + Reg1 <= 16'h1234; + Reg2 <= 16'hABCD; + end + else + begin + WB_ACK_Reg <= 0; + if ( WB_CYC & ~( WB_STB_ETH | WB_STB_PG | WB_STB_PDM ) ) + begin + WB_ACK_Reg <= 1; + if ( WB_WE ) + begin + if ( WB_ADR[0] ) + Reg2 <= WB_DAT_Wr; + else + Reg1 <= WB_DAT_Wr; + end + else + begin + if ( WB_ADR[0] ) + WB_DAT_Reg <= Reg2; + else + WB_DAT_Reg <= Reg1; + end + end + end + + //--- DUT - Ethernet Core ------------------------------------------------- + + wire [15:0] WB_DAT_Rd_ETH; + wire WB_ACK_ETH; + + wire [2:0] Speed; + + MAC_top dut( + // System signals + .Clk_125M( Clk_125M ), + .Clk_user( Clk ), + .Speed ( Speed ), + + // Wishbone compliant core host interface + .RST_I( ~Reset_n ), + .CLK_I( Clk ), + .STB_I( WB_STB_ETH ), + .CYC_I( WB_CYC ), + .ADR_I( WB_ADR[6:0] ), + .WE_I ( WB_WE ), + .DAT_I( WB_DAT_Wr ), + .DAT_O( WB_DAT_Rd_ETH ), + .ACK_O( WB_ACK_ETH ), + + // User (packet) interface + .Rx_mac_ra ( Rx_mac_ra ), + .Rx_mac_rd ( Rx_mac_rd ), + .Rx_mac_data( Rx_mac_data ), + .Rx_mac_BE ( Rx_mac_BE ), + .Rx_mac_pa ( Rx_mac_pa ), + .Rx_mac_sop ( Rx_mac_sop ), + .Rx_mac_err ( Rx_mac_err ), + .Rx_mac_eop ( Rx_mac_eop ), + + .Tx_mac_wa ( Tx_mac_wa ), + .Tx_mac_wr ( Tx_mac_wr ), + .Tx_mac_data( Tx_mac_data ), + .Tx_mac_BE ( Tx_mac_BE ), + .Tx_mac_sop ( Tx_mac_sop ), + .Tx_mac_eop ( Tx_mac_eop ), + + // PHY interface (GMII/MII) + .Gtx_clk( PHY_GTX_CLK ), // Used only in GMII mode + .Rx_clk ( PHY_RXC ), + .Tx_clk ( PHY_TXC ), // Used only in MII mode + .Tx_er ( PHY_TXER ), + .Tx_en ( PHY_TXEN ), + .Txd ( PHY_TXD ), + .Rx_er ( PHY_RXER ), + .Rx_dv ( PHY_RXDV ), + .Rxd ( PHY_RXD ), + .Crs ( PHY_CRS ), + .Col ( PHY_COL ), + + // MDIO interface (to PHY) + .Mdio( PHY_MDIO ), + .Mdc ( PHY_MDC ) + ); + + //--- Combination of Wishbone read data and acknowledge ------------------- + + assign WB_DAT_Rd = ({16{WB_ACK_Reg}} & WB_DAT_Reg ) | + ({16{WB_ACK_PDM}} & WB_DAT_Rd_PDM) | + ({16{WB_ACK_PG }} & WB_DAT_Rd_PG ) | + ({16{WB_ACK_ETH}} & WB_DAT_Rd_ETH); + + assign WB_ACK = WB_ACK_Reg | WB_ACK_PDM | WB_ACK_PG | WB_ACK_ETH; + + assign PHY_RESET_n = Reset_n; + +endmodule diff --git a/usrp2/fpga/eth/demo/verilog/demo_packet_descriptor_memory.v b/usrp2/fpga/eth/demo/verilog/demo_packet_descriptor_memory.v new file mode 100644 index 00000000..a5588a7d --- /dev/null +++ b/usrp2/fpga/eth/demo/verilog/demo_packet_descriptor_memory.v @@ -0,0 +1,384 @@ +module demo_packet_descriptor_memory( + Reset_n, + Clk, + + //--- Wishbone interface + STB_I, + CYC_I, + ADR_I, + WE_I, + DAT_I, + DAT_O, + ACK_O, + + //--- Packet Generator interface + // RdData_o is always valid exactly one clock after Addr_i changes + // and Rd_i is asserted + Rd_i, + Addr_i, + RdData_o +); + + input Reset_n; + input Clk; + + //--- Wishbone interface + input STB_I; + input CYC_I; + input [14:0] ADR_I; + input WE_I; + input [15:0] DAT_I; + output [15:0] DAT_O; + output ACK_O; + + //--- Packet Generator interface + // RdData_o is always valid exactly one clock after Addr_i changes + // and Rd_i is asserted + input Rd_i; + input [13:0] Addr_i; + output [31:0] RdData_o; + + //------------------------------------------------------------------------- + // Local declarations + //------------------------------------------------------------------------- + + reg ACK_O; + + //------------------------------------------------------------------------- + + wire [15:0] WrDataA = DAT_I; + wire [15:0] RdDataA; + wire [31:0] RdDataB; + + assign DAT_O = RdDataA; + assign RdData_o = RdDataB; + + wire WB_Access = STB_I & CYC_I; + wire WB_AccessClock1; + reg WB_AccessClock2; + + assign WB_AccessClock1 = WB_Access & ~WB_AccessClock2; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + WB_AccessClock2 <= 0; + ACK_O <= 0; + end + else + begin + WB_AccessClock2 <= WB_Access; + ACK_O <= WB_AccessClock1; + end + + //------------------------------------------------------------------------- + // Instantiation of sub-modules + //------------------------------------------------------------------------- + + //--- Instantiation of Xilinx 16 Kbit Dual Port Memory -------------------- + + RAMB16_S1_S2 RAMB16_S1_S2_bit0 ( + .DOA( RdDataA[0] ), + .DOB( { RdDataB[0], RdDataB[16+0] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[0] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit1 ( + .DOA( RdDataA[1] ), + .DOB( { RdDataB[1], RdDataB[16+1] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[1] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit2 ( + .DOA( RdDataA[2] ), + .DOB( { RdDataB[2], RdDataB[16+2] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[2] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit3 ( + .DOA( RdDataA[3] ), + .DOB( { RdDataB[3], RdDataB[16+3] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[3] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit4 ( + .DOA( RdDataA[4] ), + .DOB( { RdDataB[4], RdDataB[16+4] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[4] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit5 ( + .DOA( RdDataA[5] ), + .DOB( { RdDataB[5], RdDataB[16+5] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[5] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit6 ( + .DOA( RdDataA[6] ), + .DOB( { RdDataB[6], RdDataB[16+6] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[6] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit7 ( + .DOA( RdDataA[7] ), + .DOB( { RdDataB[7], RdDataB[16+7] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[7] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit8 ( + .DOA( RdDataA[8] ), + .DOB( { RdDataB[8], RdDataB[16+8] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[8] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit9 ( + .DOA( RdDataA[9] ), + .DOB( { RdDataB[9], RdDataB[16+9] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[9] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit10 ( + .DOA( RdDataA[10] ), + .DOB( { RdDataB[10], RdDataB[16+10] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[10] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit11 ( + .DOA( RdDataA[11] ), + .DOB( { RdDataB[11], RdDataB[16+11] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[11] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit12 ( + .DOA( RdDataA[12] ), + .DOB( { RdDataB[12], RdDataB[16+12] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[12] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit13 ( + .DOA( RdDataA[13] ), + .DOB( { RdDataB[13], RdDataB[16+13] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[13] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit14 ( + .DOA( RdDataA[14] ), + .DOB( { RdDataB[14], RdDataB[16+14] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[14] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + + RAMB16_S1_S2 RAMB16_S1_S2_bit15 ( + .DOA( RdDataA[15] ), + .DOB( { RdDataB[15], RdDataB[16+15] } ), + + .ADDRA( ADR_I[13:0] ), + .DIA ( WrDataA[15] ), + .ENA ( WB_AccessClock1 ), + .CLKA ( Clk ), + .WEA ( WE_I ), + .SSRA ( 1'b0 ), + + .ADDRB( Addr_i[12:0] ), + .DIB ( 2'b00 ), + .ENB ( Rd_i ), + .CLKB ( Clk ), + .WEB ( 1'b0 ), + .SSRB ( 1'b0 ) + ); + +endmodule diff --git a/usrp2/fpga/eth/demo/verilog/demo_packet_generator.v b/usrp2/fpga/eth/demo/verilog/demo_packet_generator.v new file mode 100644 index 00000000..22ad52b4 --- /dev/null +++ b/usrp2/fpga/eth/demo/verilog/demo_packet_generator.v @@ -0,0 +1,274 @@ +module demo_packet_generator( + Reset_n, + Clk, + + //--- Wishbone interface + STB_I, + CYC_I, + ADR_I, + WE_I, + DAT_I, + DAT_O, + ACK_O, + + //--- Packet Descriptor Memory interface + // RdData_i is always valid exactly one clock after Addr_o changes + // and Rd_o is asserted + Rd_o, + Addr_o, + RdData_i, + + //--- User (packet) interface + Rx_mac_ra, + Rx_mac_rd, + Rx_mac_data, + Rx_mac_BE, + Rx_mac_pa, + Rx_mac_sop, + Rx_mac_err, + Rx_mac_eop, + + Tx_mac_wa, + Tx_mac_wr, + Tx_mac_data, + Tx_mac_BE, + Tx_mac_sop, + Tx_mac_eop +); + + input Reset_n; + input Clk; + + //--- Wishbone interface + input STB_I; + input CYC_I; + input [1:0] ADR_I; + input WE_I; + input [15:0] DAT_I; + output [15:0] DAT_O; + output ACK_O; + + //--- Packet Generator interface + // RdData_o is always valid exactly one clock after Addr_o changes + // and Rd_o is asserted + output Rd_o; + output [13:0] Addr_o; + input [31:0] RdData_i; + + //--- User (packet) interface + input Rx_mac_ra; + output Rx_mac_rd; + input [31:0] Rx_mac_data; + input [1:0] Rx_mac_BE; + input Rx_mac_pa; + input Rx_mac_sop; + input Rx_mac_err; + input Rx_mac_eop; + + input Tx_mac_wa; + output Tx_mac_wr; + output [31:0] Tx_mac_data; + output [1:0] Tx_mac_BE; + output Tx_mac_sop; + output Tx_mac_eop; + + //------------------------------------------------------------------------- + // Local declarations + //------------------------------------------------------------------------- + + reg ACK_O; + reg [15:0] DAT_O; + + reg Rd_o; + reg Tx_mac_wr; + reg [1:0] Tx_mac_BE; + reg Tx_mac_sop; + reg Tx_mac_eop; + + //--- Wishbone interface -------------------------------------------------- + + reg [1:0] PG_CFG; + wire PG_Enable = PG_CFG[0]; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + ACK_O <= 0; + DAT_O <= 'b0; + + PG_CFG <= 2'h0; + end + else + begin + ACK_O <= 0; + if ( CYC_I & STB_I ) + begin + ACK_O <= ~ACK_O; // Generate single cycle pulse! + if ( WE_I ) + begin + PG_CFG <= DAT_I; + end + else + begin + DAT_O[1:0] <= PG_CFG; + end + end + end + + //--- Packet Generator FSM ------------------------------------------------ + + parameter PG_FSM_STATE_IDLE = 3'h0; + parameter PG_FSM_STATE_LD_DESC_1 = 3'h1; + parameter PG_FSM_STATE_LD_DESC_2 = 3'h2; + parameter PG_FSM_STATE_RD_HEADER = 3'h3; + parameter PG_FSM_STATE_PAYLOAD_SEQ_NUMBER = 3'h4; + parameter PG_FSM_STATE_PAYLOAD = 3'h5; + parameter PG_FSM_STATE_DONE = 3'h6; + reg [2:0] PG_FSM_State; + + reg [9:0] DescHigh; // Selects currente descriptor + reg [3:0] DescLow; // Index into a single descriptor (16 entries) + + reg PDM_CFG1_LAST; + reg [3:0] PDM_CFG1_REPEAT; + reg [3:0] PDM_CFG1_HDRLEN; + reg [15:0] PDM_CFG2_PAYLDLEN; + + reg [31:0] Tx_mac_data_reg; + reg WriteHeader; + reg [15:0] PayloadRemaining; + reg [31:0] PacketSequenceNumber; + reg [31:0] Payload; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + PG_FSM_State <= PG_FSM_STATE_IDLE; + + Rd_o <= 0; + + DescHigh <= 10'b0; + DescLow <= 4'b0; + + Tx_mac_wr <= 0; + Tx_mac_sop <= 0; + Tx_mac_eop <= 0; + Tx_mac_BE <= 2'b00; + + Tx_mac_data_reg <= 32'b0; + WriteHeader <= 0; + PayloadRemaining <= 16'd0; + + PacketSequenceNumber <= 32'd0; + Payload <= 32'h0; + + { PDM_CFG1_HDRLEN, PDM_CFG1_REPEAT, PDM_CFG1_LAST, PDM_CFG2_PAYLDLEN } <= 'b0; + end + else + begin + casez ( PG_FSM_State ) + PG_FSM_STATE_IDLE: + if ( PG_Enable ) + begin + PG_FSM_State <= PG_FSM_STATE_LD_DESC_1; + Rd_o <= 1; + end + else + begin + DescHigh <= 10'b0; + DescLow <= 4'b0; + end + + PG_FSM_STATE_LD_DESC_1: + begin + PG_FSM_State <= PG_FSM_STATE_LD_DESC_2; + + DescLow <= DescLow + 1; + end + + PG_FSM_STATE_LD_DESC_2: + begin + PG_FSM_State <= PG_FSM_STATE_RD_HEADER; + + { PDM_CFG1_LAST, PDM_CFG1_REPEAT, PDM_CFG1_HDRLEN, PDM_CFG2_PAYLDLEN } <= + { RdData_i[31], RdData_i[23:20], RdData_i[19:16], RdData_i[15:0] }; + end + + PG_FSM_STATE_RD_HEADER: + begin + Tx_mac_wr <= 0; + if ( Tx_mac_wa ) + begin + // Space in Tx FIFO - write next header word + DescLow <= DescLow + 1; + Tx_mac_wr <= 1; + Tx_mac_sop <= ( DescLow == 1 ); // Assert SOP on first header word + WriteHeader <= 1; + if ( DescLow == PDM_CFG1_HDRLEN ) + begin + // The requested number of header words has been read + // - proceed to generate packet payload + PG_FSM_State <= PG_FSM_STATE_PAYLOAD_SEQ_NUMBER; + PayloadRemaining <= PDM_CFG2_PAYLDLEN; + end + end + end + + PG_FSM_STATE_PAYLOAD_SEQ_NUMBER: + begin + WriteHeader <= 0; + Tx_mac_data_reg <= PacketSequenceNumber; + Tx_mac_wr <= 0; + Tx_mac_sop <= 0; + if ( Tx_mac_wa ) + begin + Tx_mac_wr <= 1; + PG_FSM_State <= PG_FSM_STATE_PAYLOAD; + Payload <= 32'h01020304; + PayloadRemaining <= PayloadRemaining - 4; + end + end + + PG_FSM_STATE_PAYLOAD: + begin + Tx_mac_data_reg <= Payload; + Tx_mac_wr <= 0; + if ( Tx_mac_wa ) + begin + Tx_mac_wr <= 1; + Tx_mac_data_reg <= Payload; + Payload[31:24] <= Payload[31:24] + 8'h04; + Payload[23:16] <= Payload[23:16] + 8'h04; + Payload[15: 8] <= Payload[15: 8] + 8'h04; + Payload[ 7: 0] <= Payload[ 7: 0] + 8'h04; + PayloadRemaining <= PayloadRemaining - 4; + if ( PayloadRemaining <= 4 ) + begin + PG_FSM_State <= PG_FSM_STATE_DONE; + + Tx_mac_eop <= 1; + // Indicate how many bytes are valid in this last transfer + Tx_mac_BE <= PayloadRemaining[1:0]; + end + end + end + + PG_FSM_STATE_DONE: + begin + // TBD: Add support for REPEAT, NEXT & LAST! + Tx_mac_wr <= 0; + Tx_mac_eop <= 0; + end + endcase + end + + //------------------------------------------------------------------------- + + assign Tx_mac_data = WriteHeader ? + RdData_i : Tx_mac_data_reg; + + assign Addr_o = { DescHigh, DescLow }; + + assign Rx_mac_rd = 0; + +endmodule diff --git a/usrp2/fpga/eth/demo/verilog/demo_uart.v b/usrp2/fpga/eth/demo/verilog/demo_uart.v new file mode 100644 index 00000000..ba4a3c35 --- /dev/null +++ b/usrp2/fpga/eth/demo/verilog/demo_uart.v @@ -0,0 +1,235 @@ +module demo_uart( + Reset_n, + Clk, + + // Interface to UART PHY (RS232 level converter) + RXD_i, + TXD_o, + + // Clk is divided by (Prescaler+1) to generate 16x the bitrate + Prescaler_i, + + // Pulsed when RxData is valid + RxValid_o, + RxData_o, + + // Asserted when ready for a new Tx byte + TxReady_o, + + // Pulsed when TxData is valid + TxValid_i, + TxData_i +); + + input Reset_n; + input Clk; + + // Interface to UART PHY (RS232 level converter) + input RXD_i; + output TXD_o; + + // Clk is divided by (Prescaler+1) to generate 16x the bitrate + input [15:0] Prescaler_i; + + // Pulsed when RxData is valid + output RxValid_o; + output [7:0] RxData_o; + + // Asserted when ready for a new Tx byte + output TxReady_o; + + // Pulsed when TxData is valid + input TxValid_i; + input [7:0] TxData_i; + + //------------------------------------------------------------------------- + // Local declarations + //------------------------------------------------------------------------- + + reg TXD_o; + reg RxValid_o; + reg [7:0] RxData_o; + reg TxReady_o; + + //------------------------------------------------------------------------- + // Instantiation of sub-modules + //------------------------------------------------------------------------- + + //--- Prescaler generating 16x bitrate clock ------------------------------ + + reg Clk_16x; + reg [15:0] Prescaler; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + Prescaler <= 0; + Clk_16x <= 0; + end + else + begin + if ( Prescaler == Prescaler_i ) + begin + Prescaler <= 0; + Clk_16x <= 1; + end + else + begin + Prescaler <= Prescaler + 1; + Clk_16x <= 0; + end + end + + //--- Transmitter logic --------------------------------------------------- + + reg [3:0] TxCounter; + reg TxSendBit; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + TxCounter <= 0; + TxSendBit <= 0; + end + else + begin + TxSendBit <= 0; + if ( Clk_16x ) + begin + if ( TxCounter == 15 ) + begin + TxCounter <= 0; + TxSendBit <= 1; + end + else + TxCounter <= TxCounter + 1; + end + end + + reg [7:0] TxData_reg; + reg [3:0] TxBitCnt; + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + TXD_o <= 1; + TxReady_o <= 1; + TxData_reg <= 0; + TxBitCnt <= 0; + end + else + begin + if ( TxReady_o ) + begin + if ( TxValid_i ) + begin + TxReady_o <= 0; + TxData_reg <= TxData_i; + TxBitCnt <= 0; + end + end + else + begin + if ( TxSendBit ) + begin + // Only do anything on bit boundaries + casez ( TxBitCnt ) + 0: // Tx START bit + TXD_o <= 0; + 10: // Tx second STOP bit + // Now we're done + TxReady_o <= 1; + default: // Tx data bit + first stop bit + begin + TXD_o <= TxData_reg[0]; + TxData_reg <= { 1'b1, TxData_reg[7:1] }; + end + endcase + + TxBitCnt <= TxBitCnt+1; + end + end + end + + //--- Receiver logic ------------------------------------------------------ + + reg RxHunt; + reg [3:0] RxCounter; + reg RxSampleBit; + reg RxDone; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + RxCounter <= 0; + RxSampleBit <= 0; + + RxHunt <= 1; + end + else + begin + RxSampleBit <= 0; + + if ( RxDone ) + RxHunt <= 1; + + if ( Clk_16x ) + begin + if ( RxHunt ) + begin + if ( RXD_i == 0 ) + begin + // Receiving start bit! + RxHunt <= 0; + // Reset 16x bit counter + RxCounter <= 0; + end + end + else + begin + RxCounter <= RxCounter + 1; + if ( RxCounter == 7 ) + // In middle of Rx bit in next cycle + RxSampleBit <= 1; + end + end + end + + reg [3:0] RxBitCount; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + RxValid_o <= 0; + RxData_o <= 'b0; + RxBitCount <= 0; + RxDone <= 0; + end + else + begin + RxValid_o <= 0; + RxDone <= 0; + + if ( RxSampleBit ) + begin + RxBitCount <= RxBitCount + 1; + + casez ( RxBitCount ) + 0: // START bit - just ignore it + ; + 9: // STOP bit - indicate we're ready again + begin + RxDone <= 1; + RxBitCount <= 0; + end + default: // Rx Data bits + begin + RxData_o <= { RXD_i, RxData_o[7:1] }; + if ( RxBitCount == 8 ) + // Last data bit just received + RxValid_o <= 1; + end + endcase + end + end + +endmodule diff --git a/usrp2/fpga/eth/demo/verilog/demo_wishbone_master.v b/usrp2/fpga/eth/demo/verilog/demo_wishbone_master.v new file mode 100644 index 00000000..b3c64fbc --- /dev/null +++ b/usrp2/fpga/eth/demo/verilog/demo_wishbone_master.v @@ -0,0 +1,376 @@ +module demo_wishbone_master( + Reset_n, + Clk, + + //--- UART interface + + // Pulsed when RxData_i is valid + RxValid_i, + RxData_i, + + // Asserted when ready for a new Tx byte + TxReady_i, + + // Pulsed when TxData_o is valid + TxValid_o, + TxData_o, + + //--- Wishbone interface + STB_ETH_O, + STB_PDM_O, + STB_PG_O, + CYC_O, + ADR_O, + WE_O, + DAT_O, + DAT_I, + ACK_I +); + + input Reset_n; + input Clk; + + //--- UART interface + + // Pulsed when RxData_i is valid + input RxValid_i; + input [7:0] RxData_i; + + // Asserted when ready for a new Tx byte + input TxReady_i; + + // Pulsed when TxData_o is valid + output TxValid_o; + output [7:0] TxData_o; + + output STB_ETH_O; + output STB_PDM_O; + output STB_PG_O; + output CYC_O; + output [14:0] ADR_O; + output WE_O; + output [15:0] DAT_O; + input [15:0] DAT_I; + input ACK_I; + + //------------------------------------------------------------------------- + // Local declarations + //------------------------------------------------------------------------- + + reg TxValid_o; + reg [7:0] TxData_o; + reg STB_ETH_O; + reg STB_PDM_O; + reg STB_PG_O; + reg CYC_O; + reg [14:0] ADR_O; + reg WE_O; + reg [15:0] DAT_O; + + //------------------------------------------------------------------------- + // Instantiation of sub-modules + //------------------------------------------------------------------------- + + //--- Transmit FSM -------------------------------------------------------- + + parameter TX_STATE_IDLE = 0; + parameter TX_STATE_INIT = 1; + parameter TX_STATE_OK = 2; + parameter TX_STATE_ERROR = 3; + parameter TX_STATE_VALUE = 4; + parameter TX_STATE_LF = 5; + + reg [2:0] TxState; + reg [3:0] TxIndex; + reg TxLast; + + wire [15:0] TxValue16; + wire [3:0] TxHexDigit; + wire [7:0] TxHexChar; + reg TxOK; + reg TxERROR; + reg TxValue; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + TxState <= TX_STATE_INIT; + TxIndex <= 0; + TxLast <= 0; + + TxValid_o <= 0; + TxData_o <= 'b0; + end + else + begin + TxValid_o <= 0; + + // Don't do anything in cycle following TxValid_o being pulsed + if ( ~TxValid_o ) + begin + casez ( TxState ) + TX_STATE_INIT: + casez ( TxIndex ) + 0: TxData_o <= "R"; + 1: TxData_o <= "E"; + 2: TxData_o <= "A"; + 3: TxData_o <= "D"; + 4: TxData_o <= "Y"; + default: TxLast <= 1; + endcase + + TX_STATE_OK: + casez ( TxIndex ) + 0: TxData_o <= "O"; + 1: TxData_o <= "K"; + default: TxLast <= 1; + endcase + + TX_STATE_ERROR: + casez ( TxIndex ) + 0: TxData_o <= "E"; + 1: TxData_o <= "R"; + 2: TxData_o <= "R"; + 3: TxData_o <= "O"; + 4: TxData_o <= "R"; + default: TxLast <= 1; + endcase + + TX_STATE_VALUE: + casez ( TxIndex ) + 0,1,2,3: TxData_o <= TxHexChar; + default: TxLast <= 1; + endcase + + TX_STATE_LF: + ; + + default: + begin + if ( TxOK ) + TxState <= TX_STATE_OK; + else if ( TxERROR ) + TxState <= TX_STATE_ERROR; + else if ( TxValue ) + begin + TxState <= TX_STATE_VALUE; + TxIndex <= 0; + end + end + endcase + + if ( (TxState != TX_STATE_IDLE) & TxReady_i ) + begin + TxValid_o <= 1; + + if ( TxLast ) + begin + if ( TxState == TX_STATE_LF ) + begin + TxData_o <= 10; // LF + TxState <= TX_STATE_IDLE; + TxIndex <= 0; + TxLast <= 0; + end + else + begin + TxData_o <= 13; // CR + TxState <= TX_STATE_LF; + end + end + else + TxIndex <= TxIndex + 1; + end + end + end + + assign TxHexDigit = (TxIndex==0) ? TxValue16[15:12] : + (TxIndex==1) ? TxValue16[11: 8] : + (TxIndex==2) ? TxValue16[ 7: 4] : + TxValue16[ 3: 0]; + + assign TxHexChar = (TxHexDigit <= 9) ? (TxHexDigit + "0") : + (TxHexDigit + "A"-'hA); + + //--- Receive FSM --------------------------------------------------------- + + parameter RX_STATE_IDLE = 0; + parameter RX_STATE_VALUE16_FIRST = 1; + parameter RX_STATE_VALUE16 = 2; + parameter RX_STATE_COMMENT = 3; + parameter RX_STATE_CMD = 4; + + reg [2:0] RxState; + + wire IsWhiteSpace = ( RxData_i==" " ) | + ( RxData_i=="\t" ) | + ( RxData_i=="," ) | + ( RxData_i==10 ) | + ( RxData_i==13 ); + wire IsHexDigit = (( RxData_i >= "0" ) & ( RxData_i <= "9" )) | + (( RxData_i >= "a" ) & ( RxData_i <= "f" )) | + (( RxData_i >= "A" ) & ( RxData_i <= "F" )); + wire [3:0] RxHexValue = + (( RxData_i >= "0" ) & ( RxData_i <= "9" )) ? RxData_i[3:0] : + (( RxData_i >= "a" ) & ( RxData_i <= "f" )) ? (RxData_i-"a"+'hA) : + (( RxData_i >= "A" ) & ( RxData_i <= "F" )) ? (RxData_i-"A"+'hA) : 0; + + reg [15:0] RxValue16; + reg RxWrite; + reg RxWrData; + + reg [15:0] RegAddr; + reg [15:0] RegRdData; + + assign TxValue16 = RegRdData; + + always @( negedge Reset_n or posedge Clk ) + if ( ~Reset_n ) + begin + RxState <= RX_STATE_IDLE; + + RxValue16 <= 16'h0; + RxWrite <= 0; + RxWrData <= 0; + + RegAddr <= 'b0; + RegRdData <= 'b0; + + STB_ETH_O <= 0; + STB_PDM_O <= 0; + STB_PG_O <= 0; + CYC_O <= 0; + ADR_O <= 0; + WE_O <= 0; + DAT_O <= 0; + + TxOK <= 0; + TxERROR <= 0; + TxValue <= 0; + end + else + begin + TxOK <= 0; + TxERROR <= 0; + TxValue <= 0; + + if ( RxState == RX_STATE_CMD ) + begin + STB_ETH_O <= ( RegAddr[15:12] == 4'h0 ); + STB_PG_O <= ( RegAddr[15:12] == 4'h1 ); + STB_PDM_O <= ( RegAddr[15] == 1'b1 ); + + CYC_O <= 1; + ADR_O <= RegAddr[14:0]; + WE_O <= RxWrite; + + if ( ACK_I ) + begin + // Register transaction is completing! + CYC_O <= 0; + STB_ETH_O <= 0; + STB_PDM_O <= 0; + STB_PG_O <= 0; + + // Latch data read in case of a read + RegRdData <= DAT_I; + + if ( RxWrite ) + // Transaction was a register write + TxOK <= 1; + else + TxValue <= 1; + + RxState <= RX_STATE_IDLE; + end + end + else if ( (TxState == TX_STATE_IDLE) & RxValid_i ) + begin + // A byte has been received! + + casez ( RxState ) + RX_STATE_IDLE: + if ( (RxData_i == "w") | (RxData_i == "W") ) + begin + // Write Register Command: W rrrr dddd + RxState <= RX_STATE_VALUE16_FIRST; + RxWrite <= 1; + RxWrData <= 0; + end + else if ( (RxData_i == "r") | (RxData_i == "R") ) + begin + // Read Register Command: R rrrr + RxState <= RX_STATE_VALUE16_FIRST; + RxWrite <= 0; + end + else if ( RxData_i == "/" ) + begin + // Comment! + RxState <= RX_STATE_COMMENT; + end + else if ( ~IsWhiteSpace ) + // Unknown command! + TxERROR <= 1; + + RX_STATE_COMMENT: + if ( (RxData_i == 13) | (RxData_i == 10) ) + // CR or LF - end of comment + RxState <= RX_STATE_IDLE; + + RX_STATE_VALUE16_FIRST: + if ( IsHexDigit ) + begin + RxValue16 <= { 12'b0, RxHexValue }; + RxState <= RX_STATE_VALUE16; + end + else if ( ~IsWhiteSpace ) + begin + // Unexpected character! + TxERROR <= 1; + RxState <= RX_STATE_IDLE; + end + + RX_STATE_VALUE16: + if ( IsHexDigit ) + RxValue16 <= { RxValue16[11:0], RxHexValue }; + else if ( IsWhiteSpace ) + begin + // Done collecting 16-bit value + if ( RxWrite ) + begin + // This is a register write + if ( RxWrData ) + begin + // Second time around - just received write data + DAT_O <= RxValue16; + RxState <= RX_STATE_CMD; + end + else + begin + // Just received register address - expecting second argument + RegAddr <= RxValue16; + RxState <= RX_STATE_VALUE16_FIRST; + RxWrData <= 1; // Now receive the write data + end + end + else + begin + // This is a register read + RegAddr <= RxValue16; + RxState <= RX_STATE_CMD; + end + end + else + begin + // Unexpected character! + TxERROR <= 1; + RxState <= RX_STATE_IDLE; + end + + default: + TxERROR <= 1; + endcase + end + end + +endmodule diff --git a/usrp2/fpga/eth/demo/verilog/tb_demo.v b/usrp2/fpga/eth/demo/verilog/tb_demo.v new file mode 100644 index 00000000..c5a8a3f4 --- /dev/null +++ b/usrp2/fpga/eth/demo/verilog/tb_demo.v @@ -0,0 +1,348 @@ +`timescale 1ns / 1ns + +module tb_demo; + + //-------------------- Instantiate Xilinx glbl module ---------------------- + // - this is needed to get ModelSim to work because e.g. I/O buffer models + // refer directly to glbl.GTS and similar signals + + wire GSR; + wire GTS; + xlnx_glbl glbl( .GSR( GSR ), .GTS( GTS ) ); + + reg VLOG_ExitSignal = 0; + reg Done = 0; + reg Error = 0; + + //------------------------------------------------------------------------- + + reg Reset_n; + reg Clk_100M; + reg Clk_125M; + + wire RS232_TXD; + wire RS232_RXD; + + wire USB_TXD; + wire USB_RXD; + + //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII) + wire PHY_RESET_n; + + wire PHY_RXC; + wire [7:0] PHY_RXD; + wire PHY_RXDV; + wire PHY_RXER; + + wire PHY_GTX_CLK; // GMII only + wire PHY_TXC; + wire [7:0] PHY_TXD; + wire PHY_TXEN; + wire PHY_TXER; + + wire PHY_COL = 0; + wire PHY_CRS = 0; + + wire PHY_MDC; + wire PHY_MDIO; + + wire [1:4] LED; + + reg [1:4] Button = 4'b0000; + + //------------------------------------------------------------------------- + // Local declarations + //------------------------------------------------------------------------- + + //------------------------------------------------------------------------- + // Instantiation of sub-modules + //------------------------------------------------------------------------- + + //--- DUT + + demo demo( + .Reset_n ( Reset_n ), + .Clk_100M( Clk_100M ), + .Clk_125M( Clk_125M ), + + .RS232_TXD( RS232_TXD ), + .RS232_RXD( RS232_RXD ), + + .USB_TXD( USB_TXD ), + .USB_RXD( USB_RXD ), + + //--- 10/100/1000BASE-T Ethernet PHY (MII/GMII) + .PHY_RESET_n( PHY_RESET_n ), + + .PHY_RXC ( PHY_RXC ), + .PHY_RXD ( PHY_RXD ), + .PHY_RXDV( PHY_RXDV ), + .PHY_RXER( PHY_RXER ), + + .PHY_GTX_CLK( PHY_GTX_CLK ), // GMII only + .PHY_TXC ( PHY_TXC ), + .PHY_TXD ( PHY_TXD ), + .PHY_TXEN ( PHY_TXEN ), + .PHY_TXER ( PHY_TXER ), + + .PHY_COL( PHY_COL ), + .PHY_CRS( PHY_CRS ), + + .PHY_MDC ( PHY_MDC ), + .PHY_MDIO( PHY_MDIO ), + + // Misc. I/Os + .LED ( LED ), + .Button( Button ) + ); + + //------------------------------------------------------------------------- + // MII/GMII Ethernet PHY model + + reg [2:0] Speed = 3'b000; + + Phy_sim U_Phy_sim( + .Gtx_clk( PHY_GTX_CLK ), + .Rx_clk ( PHY_RXC ), + .Tx_clk ( PHY_TXC ), + .Tx_er ( PHY_TXER ), + .Tx_en ( PHY_TXEN ), + .Txd ( PHY_TXD ), + .Rx_er ( PHY_RXER ), + .Rx_dv ( PHY_RXDV ), + .Rxd ( PHY_RXD ), + .Crs ( PHY_CRS ), + .Col ( PHY_COL ), + .Speed ( Speed ), + .Done ( Done ) + ); + + //------------------------------------------------------------------------- + // Generate all clocks & reset + //------------------------------------------------------------------------- + + // Core master clock (100 MHz) + initial + begin + #10; + while ( !Done ) + begin + #5 Clk_100M = 0; + #5 Clk_100M = 1; + end + end + + // GMII master clock (125 MHz) + initial + begin + #10; + while ( !Done ) + begin + #4 Clk_125M = 0; + #4 Clk_125M = 1; + end + end + + initial + begin + Reset_n = 0; + + #103; + Reset_n = 1; + end + + //--- Emulate UART Transmitter -------------------------------------------- + + parameter PRESCALER_16X = 3; + integer Prescaler; + integer TxLen = 0; + reg [2:0] TxState; + integer TxBit; + reg [1023:0] TxMsg; + reg TXD; + reg TxDone; + + always @( negedge Reset_n or posedge Clk_100M ) + if ( ~Reset_n ) + begin + Prescaler <= 0; + TxState = 0; + TXD = 1; + TxBit = 0; + TxDone <= 0; + end + else + begin + TxDone <= 0; + + if ( Prescaler == ((PRESCALER_16X + 1)*16 -1) ) + Prescaler <= 0; + else + Prescaler <= Prescaler + 1; + + if ( Prescaler==0 ) + begin + casez ( TxState ) + 0: // IDLE + begin + if ( TxLen != 0 ) + begin // Send start bit! + TxBit = (TxLen-1)*8; + TxLen = TxLen - 1; + TXD = 0; + TxState = 1; + end + end + + 1: // Send next data bit + begin + // Send next data bit + TXD = TxMsg[ TxBit ]; + TxBit = TxBit + 1; + if ( (TxBit % 8)==0 ) + // Next send two stop bits + TxState = 2; + end + + 2: // First of two stop bits + begin + TXD = 1; + TxState = 3; + end + + 3: // Second of two stop bits + begin + TXD = 1; + TxState = 0; + if ( TxLen == 0 ) + // Done with transmission! + TxDone <= 1; + end + endcase + end + end + + assign RS232_RXD = TXD; + assign USB_RXD = 1; + + //--- Send commands to the DUT -------------------------------------------- + + initial + begin + #10; + while ( ~Reset_n ) #10; + + // Wait a couple of clock edges before continuing to allow + // internal logic to get out of reset + repeat ( 5 ) + @( posedge Clk_100M ); + + // Wait for the "READY" message to complete transmission + #60000; + + // Select 100 Mbps + Speed = 3'b010; + TxMsg = "W 0022 0002 "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + TxMsg = "W 8000 8003 "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + TxMsg = "W 8001 0011 "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + TxMsg = "W 8002 1234 "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + TxMsg = "W 8003 5678 "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + TxMsg = "W 8004 9ABC "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + TxMsg = "W 8005 DEF0 "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + TxMsg = "W 8006 C5C0 "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + TxMsg = "W 8007 BABE "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + TxMsg = "R 8006 "; + TxLen = 7; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + // Enable PG! + TxMsg = "W 1000 0001 "; + TxLen = 12; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + // Read back that PG has been enabled! + TxMsg = "R 1000 "; + TxLen = 7; + while ( ~TxDone ) + @( posedge Clk_100M ); + + #50000; + + #50000; + + Done = 1; #10; + + $stop; + end + + //--- Directly accesses a register on the internal Wishbone bus, bypassing the UART interface + + task WrReg; + input [15:0] Reg; + input [15:0] Data; + + begin + end + endtask + +endmodule diff --git a/usrp2/fpga/eth/header_ram.v b/usrp2/fpga/eth/header_ram.v new file mode 100644 index 00000000..699f16a4 --- /dev/null +++ b/usrp2/fpga/eth/header_ram.v @@ -0,0 +1,24 @@ + +module header_ram + #(parameter REGNUM=0, + parameter WIDTH=32) + (input clk, + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + + input [3:0] addr, + output [31:0] q + ); + + reg [WIDTH-1:0] mini_ram[0:15]; + wire write_to_ram = (set_stb & (set_addr[7:4]==REGNUM[7:4])); + wire [3:0] ram_addr = write_to_ram ? set_addr[3:0] : addr; + + always @(posedge clk) + if(write_to_ram) + mini_ram[ram_addr] <= set_data; + + assign q = mini_ram[ram_addr]; + +endmodule // header_ram diff --git a/usrp2/fpga/eth/mac_rxfifo_int.v b/usrp2/fpga/eth/mac_rxfifo_int.v new file mode 100644 index 00000000..9393cbd1 --- /dev/null +++ b/usrp2/fpga/eth/mac_rxfifo_int.v @@ -0,0 +1,80 @@ + +module mac_rxfifo_int + (input clk, input rst, + + input Rx_mac_empty, + output Rx_mac_rd, + input [31:0] Rx_mac_data, + input [1:0] Rx_mac_BE, + input Rx_mac_sop, + input Rx_mac_eop, + input Rx_mac_err, + + output [31:0] wr_dat_o, + output wr_write_o, + output wr_done_o, + output wr_error_o, + input wr_ready_i, + input wr_full_i, + + // FIFO Status + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty + ); + + // Write side of short FIFO + // Inputs: full, Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err, Rx_mac_data/BE + // Controls: write, datain, Rx_mac_rd + + wire write, full, read, empty, sop_o, eop_o, error_o; + + // Write side of short FIFO + assign write = ~full & ~Rx_mac_empty; + assign Rx_mac_rd = write; + + shortfifo #(.WIDTH(35)) mac_rx_sfifo + (.clk(clk),.rst(rst),.clear(0), + .datain({Rx_mac_sop,Rx_mac_eop,Rx_mac_err,Rx_mac_data}),.write(write),.full(full), + .dataout({sop_o,eop_o,error_o,wr_dat_o}),.read(read),.empty(empty), + .space(), .occupied(fifo_occupied[4:0]) ); + assign fifo_occupied[15:5] = 0; + assign fifo_full = full; + assign fifo_empty = empty; + + // Read side of short FIFO + // Inputs: empty, dataout, wr_ready_i, wr_full_i + // Controls: read, wr_dat_o, wr_write_o, wr_done_o, wr_error_o + + reg [1:0] rd_state; + localparam RD_IDLE = 0; + localparam RD_HAVEPKT = 1; + localparam RD_XFER = 2; + localparam RD_ERROR = 3; + + always @(posedge clk) + if(rst) + rd_state <= RD_IDLE; + else + case(rd_state) + RD_IDLE : + if(sop_o & ~empty) + rd_state <= RD_HAVEPKT; + RD_HAVEPKT : + if(wr_ready_i) + rd_state <= RD_XFER; + RD_XFER : + if(eop_o & ~empty) + rd_state <= RD_IDLE; + else if(wr_full_i) + rd_state <= RD_HAVEPKT; + RD_ERROR : + rd_state <= RD_IDLE; + endcase // case(rd_state) + + assign read = ~empty & ((rd_state == RD_XFER) | ((rd_state==RD_IDLE)&~sop_o)); + assign wr_write_o = ~empty & (rd_state == RD_XFER); + assign wr_done_o = ~empty & (rd_state == RD_XFER) & eop_o; + assign wr_error_o = ~empty & (rd_state == RD_XFER) & error_o; + +endmodule // mac_rxfifo_int diff --git a/usrp2/fpga/eth/mac_txfifo_int.v b/usrp2/fpga/eth/mac_txfifo_int.v new file mode 100644 index 00000000..38d8d38f --- /dev/null +++ b/usrp2/fpga/eth/mac_txfifo_int.v @@ -0,0 +1,77 @@ + +module mac_txfifo_int + (input clk, input rst, input mac_clk, + + // To MAC + input Tx_mac_wa, + output Tx_mac_wr, + output [31:0] Tx_mac_data, + output [1:0] Tx_mac_BE, + output Tx_mac_sop, + output Tx_mac_eop, + + // To buffer interface + input [31:0] rd_dat_i, + output rd_read_o, + output rd_done_o, + output rd_error_o, + input rd_sop_i, + input rd_eop_i, + + // FIFO Status + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty ); + + wire empty, full, sfifo_write, sfifo_read; + wire [33:0] sfifo_in, sfifo_out; + + /* + shortfifo #(.WIDTH(34)) txmac_sfifo + (.clk(clk),.rst(rst),.clear(0), + .datain(sfifo_in),.write(sfifo_write),.full(full), + .dataout(sfifo_out),.read(sfifo_read),.empty(empty)); + */ + fifo_xlnx_512x36_2clk mac_tx_fifo_2clk + (.rst(rst), + .wr_clk(clk),.din({2'b0,sfifo_in}),.full(full),.wr_en(sfifo_write),.wr_data_count(fifo_occupied[8:0]), + .rd_clk(mac_clk),.dout(sfifo_out),.empty(empty),.rd_en(sfifo_read),.rd_data_count() ); + assign fifo_occupied[15:9] = 0; + assign fifo_full = full; + assign fifo_empty = empty; // Note empty is in wrong clock domain + + // MAC side signals + // We are allowed to do one more write after we are told the FIFO is full + // This allows us to register the _wa signal and speed up timing. + + reg tx_mac_wa_d1; + always @(posedge clk) + tx_mac_wa_d1 <= Tx_mac_wa; + + assign sfifo_read = ~empty & tx_mac_wa_d1; + + assign Tx_mac_wr = sfifo_read; + assign Tx_mac_data = sfifo_out[31:0]; + assign Tx_mac_BE = 0; // Since we only deal with packets that are multiples of 32 bits long + assign Tx_mac_sop = sfifo_out[33]; + assign Tx_mac_eop = sfifo_out[32]; + + + // BUFFER side signals + reg xfer_active; + always @(posedge clk) + if(rst) + xfer_active <= 0; + else if(rd_eop_i & ~full) + xfer_active <= 0; + else if(rd_sop_i) + xfer_active <= 1; + + assign sfifo_in = {rd_sop_i, rd_eop_i, rd_dat_i}; + assign sfifo_write = xfer_active & ~full; + + assign rd_read_o = sfifo_write; + assign rd_done_o = 0; // Always send everything we're given? + assign rd_error_o = 0; // No possible error situations? + +endmodule // mac_txfifo_int diff --git a/usrp2/fpga/eth/rtl/verilog/Clk_ctrl.v b/usrp2/fpga/eth/rtl/verilog/Clk_ctrl.v new file mode 100644 index 00000000..91708264 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/Clk_ctrl.v @@ -0,0 +1,133 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Clk_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: Clk_ctrl.v,v $ +// Revision 1.3 2006/01/19 14:07:52 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module Clk_ctrl( +Reset , +Clk_125M , +//host interface, +Speed , +//Phy interface , +Gtx_clk , +Rx_clk , +Tx_clk , +//interface clk , +MAC_tx_clk , +MAC_rx_clk , +MAC_tx_clk_div , +MAC_rx_clk_div +); +input Reset ; +input Clk_125M ; + //host interface +input [2:0] Speed ; + //Phy interface +output Gtx_clk ;//used only in GMII mode +input Rx_clk ; +input Tx_clk ;//used only in MII mode + //interface clk signals +output MAC_tx_clk ; +output MAC_rx_clk ; +output MAC_tx_clk_div ; +output MAC_rx_clk_div ; + + +// ****************************************************************************** +// internal signals +// ****************************************************************************** +wire Rx_clk_div2 ; +wire Tx_clk_div2 ; +// ****************************************************************************** +// +// ****************************************************************************** + assign Gtx_clk = Clk_125M ; + assign MAC_rx_clk = Rx_clk ; + assign MAC_rx_clk_div = Rx_clk ; + assign MAC_tx_clk = Clk_125M; + assign MAC_tx_clk_div = Clk_125M; + + + /* +eth_clk_div2 U_0_CLK_DIV2( +.Reset (Reset ), +.IN (Rx_clk ), +.OUT (Rx_clk_div2 ) +); + +eth_clk_div2 U_1_CLK_DIV2( +.Reset (Reset ), +.IN (Tx_clk ), +.OUT (Tx_clk_div2 ) +); + +eth_clk_switch U_0_CLK_SWITCH( +.IN_0 (Rx_clk_div2 ), +.IN_1 (Rx_clk ), +.SW (Speed[2] ), +.OUT (MAC_rx_clk_div ) +); + +eth_clk_switch U_1_CLK_SWITCH( +.IN_0 (Tx_clk ), +.IN_1 (Clk_125M ), +.SW (Speed[2] ), +.OUT (MAC_tx_clk ) +); + +eth_clk_switch U_2_CLK_SWITCH( +.IN_0 (Tx_clk_div2 ), +.IN_1 (Clk_125M ), +.SW (Speed[2] ), +.OUT (MAC_tx_clk_div ) +); + + */ +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_rx.v b/usrp2/fpga/eth/rtl/verilog/MAC_rx.v new file mode 100644 index 00000000..0e02e8fc --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_rx.v @@ -0,0 +1,242 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_rx.v,v $ +// Revision 1.4 2006/11/17 17:53:07 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:52 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module MAC_rx + #(parameter RX_FF_DEPTH = 9) + ( +input Reset , +input Clk_user, +input Clk , + //RMII interface +input MCrs_dv , +input [7:0] MRxD , +input MRxErr , + //flow_control signals +output [15:0] pause_quanta, +output pause_quanta_val, +output [15:0] rx_fifo_space, + //user interface +output Rx_mac_empty, +input Rx_mac_rd , +output [31:0] Rx_mac_data , +output [1:0] Rx_mac_BE , +output Rx_mac_sop , +output Rx_mac_eop , +output Rx_mac_err , + //CPU +input MAC_rx_add_chk_en , +input [7:0] MAC_add_prom_data , +input [2:0] MAC_add_prom_add , +input MAC_add_prom_wr , +input broadcast_filter_en , +input [15:0] broadcast_bucket_depth , +input [15:0] broadcast_bucket_interval , +input RX_APPEND_CRC, +input [4:0] Rx_Hwmark , +input [4:0] Rx_Lwmark , +input CRC_chk_en , +input [5:0] RX_IFG_SET , +input [15:0] RX_MAX_LENGTH ,// 1518 +input [6:0] RX_MIN_LENGTH ,// 64 + //RMON interface +output [15:0] Rx_pkt_length_rmon , +output Rx_apply_rmon , +output [2:0] Rx_pkt_err_type_rmon , +output [2:0] Rx_pkt_type_rmon , + + output [15:0] rx_fifo_occupied, + output rx_fifo_full, + output rx_fifo_empty, + output [31:0] debug +); +//****************************************************************************** +//internal signals +//****************************************************************************** + //CRC_chk interface +wire CRC_en ; +wire [7:0] CRC_data; +wire CRC_init; +wire CRC_err ; + //MAC_rx_add_chk interface +wire MAC_add_en ; +wire [7:0] MAC_add_data; +wire MAC_rx_add_chk_err ; + //broadcast_filter +wire broadcast_ptr ; +wire broadcast_drop ; + //MAC_rx_ctrl interface +wire [7:0] Fifo_data ; +wire Fifo_data_en ; +wire Fifo_full ; +wire Fifo_data_err ; +wire Fifo_data_drop ; +wire Fifo_data_end ; + + +//****************************************************************************** +//instantiation +//****************************************************************************** + + +MAC_rx_ctrl U_MAC_rx_ctrl( +.Reset (Reset ), +.Clk (Clk ), + //RMII interface ( //RMII interface ), +.MCrs_dv (MCrs_dv ), +.MRxD (MRxD ), +.MRxErr (MRxErr ), + //CRC_chk interface (//CRC_chk interface ), +.CRC_en (CRC_en ), +.CRC_data (CRC_data ), +.CRC_init (CRC_init ), +.CRC_err (CRC_err ), + //MAC_rx_add_chk interface (//MAC_rx_add_chk interface), +.MAC_add_en (MAC_add_en ), +.MAC_add_data (MAC_add_data ), +.MAC_rx_add_chk_err (MAC_rx_add_chk_err ), + //broadcast_filter (//broadcast_filter ), +.broadcast_ptr (broadcast_ptr ), +.broadcast_drop (broadcast_drop ), + //flow_control signals (//flow_control signals ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ), + //MAC_rx_FF interface (//MAC_rx_FF interface ), +.Fifo_data (Fifo_data ), +.Fifo_data_en (Fifo_data_en ), +.Fifo_data_err (Fifo_data_err ), +.Fifo_data_drop (Fifo_data_drop ), +.Fifo_data_end (Fifo_data_end ), +.Fifo_full (Fifo_full ), + //RMON interface (//RMON interface ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //CPU (//CPU ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ) +); + + assign debug = {28'd0, Fifo_data_en, Fifo_data_err, Fifo_data_end,Fifo_full}; + +MAC_rx_FF #(.RX_FF_DEPTH(RX_FF_DEPTH)) U_MAC_rx_FF ( +.Reset (Reset ), +.Clk_MAC (Clk ), +.Clk_SYS (Clk_user ), + //MAC_rx_ctrl interface (//MAC_rx_ctrl interface ), +.Fifo_data (Fifo_data ), +.Fifo_data_en (Fifo_data_en ), +.Fifo_full (Fifo_full ), +.Fifo_data_err (Fifo_data_err ), +//.Fifo_data_drop (Fifo_data_drop ), +.Fifo_data_end (Fifo_data_end ), +.Fifo_space (rx_fifo_space ), + //CPU (//CPU ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.RX_APPEND_CRC (RX_APPEND_CRC ), + //user interface (//user interface ), +.Rx_mac_empty (Rx_mac_empty ), +.Rx_mac_rd (Rx_mac_rd ), +.Rx_mac_data (Rx_mac_data ), +.Rx_mac_BE (Rx_mac_BE ), +.Rx_mac_sop (Rx_mac_sop ), +.Rx_mac_eop (Rx_mac_eop ), +.Rx_mac_err (Rx_mac_err ), + +.fifo_occupied(rx_fifo_occupied), +.fifo_full_dbg(rx_fifo_full), +.fifo_empty(rx_fifo_empty) +); + + Broadcast_filter U_Broadcast_filter + (.Reset (Reset ), + .Clk (Clk ), + //MAC_rx_ctrl (//MAC_rx_ctrl ), + .broadcast_ptr (broadcast_ptr ), + .broadcast_drop (broadcast_drop ), + //FromCPU (//FromCPU ), + .broadcast_filter_en (broadcast_filter_en ), + .broadcast_bucket_depth (broadcast_bucket_depth ), + .broadcast_bucket_interval (broadcast_bucket_interval ) + ); + +CRC_chk U_CRC_chk( +.Reset (Reset ), +.Clk (Clk ), +.CRC_data (CRC_data ), +.CRC_init (CRC_init ), +.CRC_en (CRC_en ), + //From CPU (//From CPU ), +.CRC_chk_en (CRC_chk_en ), +.CRC_err (CRC_err ) +); + + MAC_rx_add_chk U_MAC_rx_add_chk + (.Reset (Reset ), + .Clk (Clk ), + .Init (CRC_init ), + .data (MAC_add_data ), + .MAC_add_en (MAC_add_en ), + .MAC_rx_add_chk_err (MAC_rx_add_chk_err ), + //From CPU (//From CPU ), + .MAC_rx_add_chk_en (MAC_rx_add_chk_en ), + .MAC_add_prom_data (MAC_add_prom_data ), + .MAC_add_prom_add (MAC_add_prom_add ), + .MAC_add_prom_wr (MAC_add_prom_wr ) + ); + +endmodule // MAC_rx diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_rx/Broadcast_filter.v b/usrp2/fpga/eth/rtl/verilog/MAC_rx/Broadcast_filter.v new file mode 100644 index 00000000..bc95e31d --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_rx/Broadcast_filter.v @@ -0,0 +1,107 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Broadcast_filter.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: Broadcast_filter.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module Broadcast_filter ( +Reset , +Clk , +//MAC_rx_ctrl , +broadcast_ptr , +broadcast_drop , +//FromCPU , +broadcast_filter_en , +broadcast_bucket_depth , +broadcast_bucket_interval +); +input Reset ; +input Clk ; + //MAC_rx_ctrl +input broadcast_ptr ; +output broadcast_drop ; + //FromCPU ; +input broadcast_filter_en ; +input [15:0] broadcast_bucket_depth ; +input [15:0] broadcast_bucket_interval ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [15:0] time_counter ; +reg [15:0] broadcast_counter ; +reg broadcast_drop ; +//****************************************************************************** +// +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + time_counter <=0; + else if (time_counter==broadcast_bucket_interval) + time_counter <=0; + else + time_counter <=time_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_counter <=0; + else if (time_counter==broadcast_bucket_interval) + broadcast_counter <=0; + else if (broadcast_ptr&&broadcast_counter!=broadcast_bucket_depth) + broadcast_counter <=broadcast_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_drop <=0; + else if(broadcast_filter_en&&broadcast_counter==broadcast_bucket_depth) + broadcast_drop <=1; + else + broadcast_drop <=0; + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v b/usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v new file mode 100644 index 00000000..d6bb22b5 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v @@ -0,0 +1,128 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CRC_chk.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: CRC_chk.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module CRC_chk( +Reset , +Clk , +CRC_data , +CRC_init , +CRC_en , +//From CPU +CRC_chk_en , +CRC_err +); +input Reset ; +input Clk ; +input[7:0] CRC_data ; +input CRC_init ; +input CRC_en ; + //From CPU +input CRC_chk_en ; +output CRC_err ; +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [31:0] CRC_reg; +//****************************************************************************** +//input data width is 8bit, and the first bit is bit[0] +function[31:0] NextCRC; + input[7:0] D; + input[31:0] C; + reg[31:0] NewCRC; + begin + NewCRC[0]=C[24]^C[30]^D[1]^D[7]; + NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; + NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; + NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; + NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; + NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; + NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; + NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; + NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4]; + NewCRC[20]=C[12]^C[28]^D[3]; + NewCRC[21]=C[13]^C[29]^D[2]; + NewCRC[22]=C[14]^C[24]^D[7]; + NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5]; + NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; + NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; + NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; + NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; + NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3]; + NewCRC[31]=C[23]^C[29]^D[2]; + NextCRC=NewCRC; + end + endfunction + +always @ (posedge Clk or posedge Reset) + if (Reset) + CRC_reg <=32'hffffffff; + else if (CRC_init) + CRC_reg <=32'hffffffff; + else if (CRC_en) + CRC_reg <=NextCRC(CRC_data,CRC_reg); + +assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b); + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v b/usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v new file mode 100644 index 00000000..e212b898 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v @@ -0,0 +1,167 @@ + +// //////////////////////////////////////////////////////////////////// +// Completely Rewritten by M. Ettus, no John Gao code left +// //////////////////////////////////////////////////////////////////// + +module MAC_rx_FF + #(parameter RX_FF_DEPTH = 9) + (input Reset, + input Clk_MAC, + input Clk_SYS, + + // MAC_rx_ctrl interface + input [7:0] Fifo_data, + input Fifo_data_en, + output Fifo_full, + input Fifo_data_err, + input Fifo_data_end, + output [15:0] Fifo_space, + + // CPU + input RX_APPEND_CRC, + input [4:0] Rx_Hwmark, + input [4:0] Rx_Lwmark, + + // User interface + output Rx_mac_empty, + input Rx_mac_rd, + output [31:0] Rx_mac_data, + output [1:0] Rx_mac_BE, + output Rx_mac_sop, + output Rx_mac_eop, + output Rx_mac_err, + + // FIFO Levels + output [15:0] fifo_occupied, + output fifo_full_dbg, + output fifo_empty + ); + + reg [1:0] FF_state; + reg [2:0] PKT_state; + reg [31:0] staging; + reg [35:0] staging2; + reg line_ready, line_ready_d1; + wire sop_i, eop_i; + reg [1:0] be; + + always @(posedge Clk_MAC or posedge Reset) + if(Reset) + FF_state <= 0; + else + if(Fifo_data_err | Fifo_data_end) + FF_state <= 0; + else if(Fifo_data_en) + FF_state <= FF_state + 1; + + always @(posedge Clk_MAC or posedge Reset) + if(Reset) + staging[31:0] <= 0; + else if(Fifo_data_en) + case(FF_state) + 0 : staging[31:24] <= Fifo_data; + 1 : staging[23:16] <= Fifo_data; + 2 : staging[15:8] <= Fifo_data; + 3 : staging[7:0] <= Fifo_data; + endcase // case(FF_state) + + localparam PKT_idle = 0; + localparam PKT_sop = 1; + localparam PKT_pkt = 2; + localparam PKT_end = 3; + localparam PKT_err = 4; + + always @(posedge Clk_MAC or posedge Reset) + if(Reset) + PKT_state <= 0; + else + case(PKT_state) + PKT_idle : + if(Fifo_data_en) + PKT_state <= PKT_sop; + PKT_sop, PKT_pkt : + if(Fifo_data_err | (line_ready & Fifo_full)) + PKT_state <= PKT_err; + else if(Fifo_data_end) + PKT_state <= PKT_end; + else if(line_ready & ~Fifo_full) + PKT_state <= PKT_pkt; + PKT_end : + PKT_state <= PKT_idle; + PKT_err : + if(~Fifo_full) + PKT_state <= PKT_idle; + endcase // case(PKT_state) + + assign sop_i = (PKT_state == PKT_sop); + assign eop_i = (PKT_state == PKT_end); + + always @(posedge Clk_MAC) + if(line_ready) + staging2 <= {sop_i, eop_i, be[1:0], staging}; + + always @(posedge Clk_MAC) + if(Reset) + line_ready <= 0; + else if((Fifo_data_en & (FF_state==2'd3)) | Fifo_data_end | Fifo_data_err) + line_ready <= 1; + else + line_ready <= 0; + + always @(posedge Clk_MAC) + line_ready_d1 <= line_ready; + + always @(posedge Clk_MAC) + if(Fifo_data_end | Fifo_data_err) + be <= FF_state; + else + be <= 0; + + wire sop_o, eop_o, empty; + wire [1:0] be_o; + wire [RX_FF_DEPTH-1:0] occupied, occupied_sysclk; + wire [31:0] dataout; + +/* + fifo_2clock #(.DWIDTH(36),.AWIDTH(RX_FF_DEPTH)) mac_rx_fifo + (.wclk(Clk_MAC),.datain((PKT_state==PKT_err) ? 36'hF_FFFF_FFFF : staging2),.write(~Fifo_full & (line_ready_d1|(PKT_state==PKT_err))), + .full(Fifo_full),.level_wclk(occupied), + .rclk(Clk_SYS),.dataout({sop_o,eop_o,be_o[1:0],dataout}),.read(Rx_mac_rd), + .empty(empty),.level_rclk(), + .arst(Reset) ); + */ + + fifo_xlnx_2Kx36_2clk mac_rx_ff_core + ( + .din((PKT_state==PKT_err) ? 36'hF_FFFF_FFFF : staging2), // Bus [35 : 0] + .rd_clk(Clk_SYS), + .rd_en(Rx_mac_rd), + .rst(Reset), + .wr_clk(Clk_MAC), + .wr_en(~Fifo_full & (line_ready_d1|(PKT_state==PKT_err))), + .dout({sop_o,eop_o,be_o[1:0],dataout}), // Bus [35 : 0] + .empty(empty), + .full(Fifo_full), + .rd_data_count(occupied_sysclk), // Bus [11 : 0] + .wr_data_count(occupied)); // Bus [11 : 0] + + assign Fifo_space[15:RX_FF_DEPTH] = 0; + assign Fifo_space[RX_FF_DEPTH-1:0] = ~occupied; + assign fifo_occupied = occupied_sysclk; + assign fifo_full_dbg = Fifo_full; // FIXME -- in wrong clock domain + assign fifo_empty = empty; + + // mac side fifo interface + // Input - Rx_mac_rd + // Output - Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err, Rx_mac_data, Rx_mac_BE + + assign Rx_mac_BE = be_o; + assign Rx_mac_sop = sop_o & ~eop_o; + assign Rx_mac_eop = eop_o; + assign Rx_mac_err = sop_o & eop_o; + assign Rx_mac_empty = empty; + assign Rx_mac_data = dataout; + +endmodule // MAC_rx_FF + +// FIXME Should we send out an "almost full" signal instead of full? diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v b/usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v new file mode 100644 index 00000000..0c8d6bd4 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v @@ -0,0 +1,158 @@ +// //////////////////////////////////////////////////////////////////// +// // //// +// // MAC_rx_add_chk.v //// +// // //// +// // This file is part of the Ethernet IP core project //// +// // http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode///// +// // //// +// // Author(s): //// +// // - Jon Gao (gaojon@yahoo.com) //// +// // //// +// // //// +// //////////////////////////////////////////////////////////////////// +// // //// +// // Copyright (C) 2001 Authors //// +// // //// +// // This source file may be used and distributed without //// +// // restriction provided that this copyright statement is not //// +// // removed from the file and that any derivative work contains //// +// // the original copyright notice and the associated disclaimer. //// +// // //// +// // This source file is free software; you can redistribute it //// +// // and/or modify it under the terms of the GNU Lesser General //// +// // Public License as published by the Free Software Foundation; //// +// // either version 2.1 of the License, or (at your option) any //// +// // later version. //// +// // //// +// // This source is distributed in the hope that it will be //// +// // useful, but WITHOUT ANY WARRANTY; without even the implied //// +// // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +// // PURPOSE. See the GNU Lesser General Public License for more //// +// // details. //// +// // //// +// // You should have received a copy of the GNU Lesser General //// +// // Public License along with this source; if not, download it //// +// // from http://www.opencores.org/lgpl.shtml //// +// // //// +// //////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_rx_add_chk.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_add_chk + (Reset , + Clk , + Init , + data , + MAC_add_en , + MAC_rx_add_chk_err , + //From CPU + MAC_rx_add_chk_en , + MAC_add_prom_data , + MAC_add_prom_add , + MAC_add_prom_wr + ); + + input Reset ; + input Clk ; + input Init ; + input [7:0] data ; + input MAC_add_en ; + output MAC_rx_add_chk_err ; + //From CPU + input MAC_rx_add_chk_en ; + input [7:0] MAC_add_prom_data ; + input [2:0] MAC_add_prom_add ; + input MAC_add_prom_wr ; + + // ****************************************************************************** + // internal signals + // ****************************************************************************** + reg [2:0] addr_rd; + wire [2:0] addr_wr; + wire [7:0] din; + //wire [7:0] dout; + reg [7:0] dout; + wire wr_en; + + reg MAC_rx_add_chk_err; + reg MAC_add_prom_wr_dl1; + reg MAC_add_prom_wr_dl2; + reg [7:0] data_dl1 ; + reg MAC_add_en_dl1 ; + + // ****************************************************************************** + // write data from cpu to prom + // ****************************************************************************** + always @ (posedge Clk or posedge Reset) + if (Reset) + begin + data_dl1 <=0; + MAC_add_en_dl1 <=0; + end + else + begin + data_dl1 <=data; + MAC_add_en_dl1 <=MAC_add_en; + end + + always @ (posedge Clk or posedge Reset) + if (Reset) + begin + MAC_add_prom_wr_dl1 <=0; + MAC_add_prom_wr_dl2 <=0; + end + else + begin + MAC_add_prom_wr_dl1 <=MAC_add_prom_wr; + MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1; + end + + assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2; + assign addr_wr =MAC_add_prom_add; + assign din =MAC_add_prom_data; + + // ****************************************************************************** + // mac add verify + // ****************************************************************************** + always @ (posedge Clk or posedge Reset) + if (Reset) + addr_rd <=0; + else if (Init) + addr_rd <=0; + else if (MAC_add_en) + addr_rd <=addr_rd + 1; + + always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_rx_add_chk_err <=0; + else if (Init) + MAC_rx_add_chk_err <=0; + else if (MAC_rx_add_chk_en && MAC_add_en_dl1 && (dout!=data_dl1) ) + MAC_rx_add_chk_err <=1; + + + // ****************************************************************************** + // a port for read ,b port for write . + // ****************************************************************************** + + reg [7:0] address_ram [0:7]; + always @(posedge Clk) + if(wr_en) + address_ram[addr_wr] <= din; + + always @(posedge Clk) + dout <= address_ram[addr_rd]; + +endmodule // MAC_rx_add_chk diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v b/usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v new file mode 100644 index 00000000..5ab79580 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v @@ -0,0 +1,664 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_rx_ctrl.v,v $ +// Revision 1.4 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:37 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_ctrl ( +Reset , +Clk , +//RMII interface +MCrs_dv , // +MRxD , // +MRxErr , // +//CRC_chk interface +CRC_en , +CRC_data, +CRC_init , +CRC_err , +//MAC_rx_add_chk interface +MAC_add_en , +MAC_add_data, +MAC_rx_add_chk_err , +//broadcast_filter +broadcast_ptr , +broadcast_drop , +//flow_control signals +pause_quanta , +pause_quanta_val , +//MAC_rx_FF interface +Fifo_data , +Fifo_data_en , +Fifo_data_err , +Fifo_data_drop , +Fifo_data_end , +Fifo_full , +//RMON interface +Rx_pkt_type_rmon , +Rx_pkt_length_rmon , +Rx_apply_rmon , +Rx_pkt_err_type_rmon , +//CPU +RX_IFG_SET , +RX_MAX_LENGTH, +RX_MIN_LENGTH +); + +input Reset ; +input Clk ; + //RMII interface +input MCrs_dv ; +input [7:0] MRxD ; +input MRxErr ; + //CRC_chk interface +output CRC_en ; +output CRC_init; +output [7:0] CRC_data; +input CRC_err ; + //MAC_rx_add_chk interface +output MAC_add_en ; +output [7:0] MAC_add_data; +input MAC_rx_add_chk_err ; + //broadcast_filter +output broadcast_ptr ; +input broadcast_drop ; + //flow_control signals +output [15:0] pause_quanta ; +output pause_quanta_val ; + //MAC_rx_FF interface +output [7:0] Fifo_data ; +output Fifo_data_en ; +output Fifo_data_err ; +output Fifo_data_drop ; +output Fifo_data_end ; +input Fifo_full; + //RMON interface +output [15:0] Rx_pkt_length_rmon ; +output Rx_apply_rmon ; +output [2:0] Rx_pkt_err_type_rmon ; +output [2:0] Rx_pkt_type_rmon ; + //CPU +input [5:0] RX_IFG_SET ; +input [15:0] RX_MAX_LENGTH ;// 1518 +input [6:0] RX_MIN_LENGTH ;// 64 + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter State_idle =4'd00; +parameter State_preamble =4'd01; +parameter State_SFD =4'd02; +parameter State_data =4'd03; +parameter State_checkCRC =4'd04; +parameter State_OkEnd =4'd07; +parameter State_DropEnd =4'd08; +parameter State_ErrEnd =4'd09; +parameter State_CRCErrEnd =4'd10; +parameter State_FFFullDrop =4'd11; +parameter State_FFFullErrEnd =4'd12; +parameter State_IFG =4'd13; +parameter State_Drop2End =4'd14; + +parameter Pause_idle =4'd0; +parameter Pause_pre_syn =4'd1; +parameter Pause_quanta_hi =4'd2; +parameter Pause_quanta_lo =4'd3; +parameter Pause_syn =4'd4; + +reg [3:0] Current_state /* synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [3:0] Pause_current /* synthesis syn_keep=1 */; +reg [3:0] Pause_next; +reg [5:0] IFG_counter; +reg Crs_dv ; +reg [7:0] RxD ; +reg [7:0] RxD_dl1 ; +reg RxErr ; +reg [15:0] Frame_length_counter; +reg Too_long; +reg Too_short; +reg ProcessingHeader; +//reg Fifo_data_en; +//reg Fifo_data_err; +//reg Fifo_data_drop; +//reg Fifo_data_end; +reg CRC_en; +reg CRC_init; +reg Rx_apply_rmon; +reg [2:0] Rx_pkt_err_type_rmon; +reg MAC_add_en; +reg [2:0] Rx_pkt_type_rmon; +reg [7:0] pause_quanta_h ; +reg [15:0] pause_quanta ; +reg pause_quanta_val ; +reg pause_quanta_val_tmp; +reg pause_frame_ptr ; +reg broadcast_ptr ; +//****************************************************************************** +//delay signals +//****************************************************************************** + +always @ (posedge Reset or posedge Clk) + if (Reset) + begin + Crs_dv <=0; + RxD <=0; + RxErr <=0; + end + else + begin + Crs_dv <=MCrs_dv ; + RxD <=MRxD ; + RxErr <=MRxErr ; + end + +always @ (posedge Reset or posedge Clk) + if (Reset) + RxD_dl1 <=0; + else + RxD_dl1 <=RxD; + +//--------------------------------------------------------------------------- +// Small pre-FIFO (acutally a synchronously clearable shift-register) for +// storing the first part of a packet before writing it to the "real" FIFO +// in MAC_rx_FF. This allows a packet to be dropped safely if an error +// happens in the beginning of a packet (or if the MAC address doesn't pass +// the receive filter!) +//--------------------------------------------------------------------------- + + reg pre_fifo_data_drop; + reg pre_fifo_data_en; + reg pre_fifo_data_err; + reg pre_fifo_data_end; + wire [7:0] pre_fifo_wrdata; + + reg [8+3-1:0] pre_fifo_element_0; + reg [8+3-1:0] pre_fifo_element_1; + reg [8+3-1:0] pre_fifo_element_2; + reg [8+3-1:0] pre_fifo_element_3; + reg [8+3-1:0] pre_fifo_element_4; + reg [8+3-1:0] pre_fifo_element_5; + reg [8+3-1:0] pre_fifo_element_6; + reg [8+3-1:0] pre_fifo_element_7; + reg [8+3-1:0] pre_fifo_element_8; + reg [8+3-1:0] pre_fifo_element_9; + + always @( posedge Reset or posedge Clk ) + if ( Reset ) + begin + pre_fifo_element_0 <= 'b0; + pre_fifo_element_1 <= 'b0; + pre_fifo_element_2 <= 'b0; + pre_fifo_element_3 <= 'b0; + pre_fifo_element_4 <= 'b0; + pre_fifo_element_5 <= 'b0; + pre_fifo_element_6 <= 'b0; + pre_fifo_element_7 <= 'b0; + pre_fifo_element_8 <= 'b0; + pre_fifo_element_9 <= 'b0; + end + else + begin + if ( pre_fifo_data_drop ) + begin + pre_fifo_element_0 <= 'b0; + pre_fifo_element_1 <= 'b0; + pre_fifo_element_2 <= 'b0; + pre_fifo_element_3 <= 'b0; + pre_fifo_element_4 <= 'b0; + pre_fifo_element_5 <= 'b0; + pre_fifo_element_6 <= 'b0; + pre_fifo_element_7 <= 'b0; + pre_fifo_element_8 <= 'b0; + pre_fifo_element_9 <= 'b0; + end + else + begin + pre_fifo_element_0 <= pre_fifo_element_1; + pre_fifo_element_1 <= pre_fifo_element_2; + pre_fifo_element_2 <= pre_fifo_element_3; + pre_fifo_element_3 <= pre_fifo_element_4; + pre_fifo_element_4 <= pre_fifo_element_5; + pre_fifo_element_5 <= pre_fifo_element_6; + pre_fifo_element_6 <= pre_fifo_element_7; + pre_fifo_element_7 <= pre_fifo_element_8; + pre_fifo_element_8 <= pre_fifo_element_9; + pre_fifo_element_9 <= { pre_fifo_data_en, + pre_fifo_data_err, + pre_fifo_data_end, + pre_fifo_wrdata }; + end + end + + assign Fifo_data = pre_fifo_element_0[7:0]; + assign Fifo_data_end = pre_fifo_element_0[8]; + assign Fifo_data_err = pre_fifo_element_0[9]; + assign Fifo_data_en = pre_fifo_element_0[10]; + + assign CRC_data = pre_fifo_wrdata; + assign MAC_add_data = pre_fifo_wrdata; + +//****************************************************************************** +//State_machine +//****************************************************************************** + +always @( posedge Reset or posedge Clk ) + if ( Reset ) + Current_state <= State_idle; + else + Current_state <= Next_state; + +always @ (*) + case (Current_state) + State_idle: + if ( Crs_dv&&RxD==8'h55 ) + Next_state = State_preamble; + else + Next_state = Current_state; + + State_preamble: + if ( !Crs_dv ) + Next_state = State_DropEnd; + else if ( RxErr ) + Next_state = State_DropEnd; + else if ( RxD==8'hd5 ) + Next_state = State_SFD; + else if ( RxD==8'h55 ) + Next_state =Current_state; + else + Next_state = State_DropEnd; + + State_SFD: + if ( !Crs_dv ) + Next_state = State_DropEnd; + else if ( RxErr ) + Next_state = State_DropEnd; + else + Next_state = State_data; + + State_data: + if ( !Crs_dv && !ProcessingHeader && !Too_short && !Too_long ) + Next_state = State_checkCRC; + else if ( !Crs_dv && ProcessingHeader ) + Next_state = State_Drop2End; + else if ( !Crs_dv && (Too_short | Too_long) ) + Next_state = State_ErrEnd; + else if ( Fifo_full ) + Next_state = State_FFFullErrEnd; + else if ( RxErr && ProcessingHeader ) + Next_state = State_Drop2End; + else if ( RxErr || Too_long ) + Next_state = State_ErrEnd; + else if ( MAC_rx_add_chk_err || broadcast_drop ) + Next_state = State_DropEnd; + else + Next_state = State_data; + + State_checkCRC: + if ( CRC_err ) + Next_state = State_CRCErrEnd; + else + Next_state = State_OkEnd; + + State_OkEnd: + Next_state = State_IFG; + + State_ErrEnd: + Next_state = State_IFG; + + State_DropEnd: + Next_state = State_IFG; + + State_Drop2End: + Next_state = State_IFG; + + State_CRCErrEnd: + Next_state = State_IFG; + + State_FFFullErrEnd: + Next_state = State_FFFullDrop; + + State_FFFullDrop: + if ( !Crs_dv ) + Next_state =State_IFG; + else + Next_state =Current_state; + + State_IFG: + if ( IFG_counter==RX_IFG_SET-4 ) // Remove some additional time? + Next_state = State_idle; + else + Next_state = Current_state; + + default: + Next_state = State_idle; + endcase + +always @( posedge Reset or posedge Clk ) + if ( Reset ) + IFG_counter <= 0; + else if ( Current_state!=State_IFG ) + IFG_counter <= 0; + else + IFG_counter <= IFG_counter + 1; + +//****************************************************************************** +//gen fifo interface signals +//****************************************************************************** + +assign pre_fifo_wrdata = RxD_dl1; + +always @( Current_state ) + if ( Current_state==State_data ) + pre_fifo_data_en = 1; + else + pre_fifo_data_en = 0; + +always @( Current_state ) + if ( (Current_state==State_ErrEnd ) || + (Current_state==State_OkEnd ) || + (Current_state==State_CRCErrEnd ) || + (Current_state==State_FFFullErrEnd) || + (Current_state==State_DropEnd ) || + (Current_state==State_Drop2End ) ) + pre_fifo_data_end = 1; + else + pre_fifo_data_end = 0; + +always @( Current_state ) + if ( (Current_state==State_ErrEnd ) || + (Current_state==State_CRCErrEnd ) || + (Current_state==State_FFFullErrEnd) || + (Current_state==State_DropEnd ) || + (Current_state==State_Drop2End ) ) + pre_fifo_data_err = 1; + else + pre_fifo_data_err = 0; + +always @( Current_state ) + if ( (Current_state==State_DropEnd ) || + (Current_state==State_Drop2End) ) + pre_fifo_data_drop = 1; + else + pre_fifo_data_drop = 0; + + // Drop in main Rx FIFO is no longer supported! + assign Fifo_data_drop = 0; + +//****************************************************************************** +//CRC_chk interface +//****************************************************************************** + +always @(Current_state) + if (Current_state==State_data) + CRC_en =1; + else + CRC_en =0; + +always @(Current_state) + if (Current_state==State_SFD) + CRC_init =1; + else + CRC_init =0; + +//****************************************************************************** +//gen rmon signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Frame_length_counter <=0; + else if (Current_state==State_SFD) + Frame_length_counter <=1; + else if (Current_state==State_data) + Frame_length_counter <=Frame_length_counter+ 1'b1; + +always @( Frame_length_counter ) + if ( Frame_length_counter < 8 ) + ProcessingHeader = 1; + else + ProcessingHeader = 0; + +always @ (Frame_length_counter or RX_MIN_LENGTH) + if (Frame_length_counterRX_MAX_LENGTH) + Too_long =1; + else + Too_long =0; + +assign Rx_pkt_length_rmon = Frame_length_counter-1'b1; + +reg [2:0] Rx_apply_rmon_reg; + +always @( posedge Clk or posedge Reset ) + if ( Reset ) + begin + Rx_apply_rmon <= 0; + Rx_apply_rmon_reg <= 'b0; + end + else + begin + if ( (Current_state==State_OkEnd ) || + (Current_state==State_ErrEnd ) || + (Current_state==State_CRCErrEnd ) || + (Current_state==State_Drop2End ) || + (Current_state==State_FFFullErrEnd) ) + Rx_apply_rmon <= 1; + else + if ( Rx_apply_rmon_reg[2] ) + Rx_apply_rmon <= 0; + + Rx_apply_rmon_reg <= { Rx_apply_rmon_reg[1:0], Rx_apply_rmon }; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_err_type_rmon <=0; + else if (Current_state==State_CRCErrEnd) + Rx_pkt_err_type_rmon <=3'b001 ;// + else if (Current_state==State_FFFullErrEnd) + Rx_pkt_err_type_rmon <=3'b010 ;// + else if ( (Current_state==State_ErrEnd) || (Current_state==State_Drop2End) ) + Rx_pkt_err_type_rmon <=3'b011 ;// + else if(Current_state==State_OkEnd) + Rx_pkt_err_type_rmon <=3'b100 ; + + + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_type_rmon <=0; + else if (Current_state==State_OkEnd&&pause_frame_ptr) + Rx_pkt_type_rmon <=3'b100 ;// + else if(Current_state==State_SFD&&Next_state==State_data) + Rx_pkt_type_rmon <={1'b0,MRxD[7:6]}; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_ptr <=0; + else if(Current_state==State_IFG) + broadcast_ptr <=0; + else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11) + broadcast_ptr <=1; + + + +//****************************************************************************** +//MAC add checker signals +//****************************************************************************** +always @ (Frame_length_counter or pre_fifo_data_en) + if(Frame_length_counter>=1&&Frame_length_counter<=6) + MAC_add_en <=pre_fifo_data_en; + else + MAC_add_en <=0; + +//****************************************************************************** +//flow control signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Pause_current <=Pause_idle; + else + Pause_current <=Pause_next; + +always @ (*) + case (Pause_current) + Pause_idle : + if(Current_state==State_SFD) + Pause_next =Pause_pre_syn; + else + Pause_next =Pause_current; + Pause_pre_syn: + case (Frame_length_counter) + 16'd1: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd2: if (RxD_dl1==8'h80) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd3: if (RxD_dl1==8'hc2) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd4: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd5: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd6: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd13: if (RxD_dl1==8'h88) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd14: if (RxD_dl1==8'h08) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd15: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd16: if (RxD_dl1==8'h01) + Pause_next =Pause_quanta_hi; + else + Pause_next =Pause_idle; + default: Pause_next =Pause_current; + endcase + Pause_quanta_hi : + Pause_next =Pause_quanta_lo; + Pause_quanta_lo : + Pause_next =Pause_syn; + Pause_syn : + if (Current_state==State_IFG) + Pause_next =Pause_idle; + else + Pause_next =Pause_current; + default + Pause_next =Pause_idle; + endcase + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_h <=0; + else if(Pause_current==Pause_quanta_hi) + pause_quanta_h <=RxD_dl1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta <=0; + else if(Pause_current==Pause_quanta_lo) + pause_quanta <={pause_quanta_h,RxD_dl1}; + + // The following 2 always blocks are a strange way of holding + // pause_quanta_val high for 2 cycles +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val_tmp <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn) + pause_quanta_val_tmp <=1; + else + pause_quanta_val_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp) + pause_quanta_val <=1; + else + pause_quanta_val <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_frame_ptr <=0; + else if(Pause_current==Pause_syn) + pause_frame_ptr <=1; + else + pause_frame_ptr <=0; + +endmodule + + diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_top.v b/usrp2/fpga/eth/rtl/verilog/MAC_top.v new file mode 100644 index 00000000..d93b287c --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_top.v @@ -0,0 +1,516 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_top.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module MAC_top + #(parameter TX_FF_DEPTH = 9, + parameter RX_FF_DEPTH = 9) + ( + // System signals + input Clk_125M, + input Clk_user, + + input rst_mac, + input rst_user, + + // Wishbone compliant core host interface + input RST_I, // Active high (async) reset of the Wishbone interface + input CLK_I, // Wishbone interface clock (nominally 50 MHz) + input STB_I, // Active high module-select + input CYC_I, // Active high cycle-enable + input [6:0] ADR_I, // Module register address + input WE_I, // Active high for writes, low for reads + input [31:0] DAT_I, // Write data + output [31:0] DAT_O, // Read data + output ACK_O, // Acknowledge output – single high pulse + + // User (packet) interface + output Rx_mac_empty, + input Rx_mac_rd, + output [31:0] Rx_mac_data, + output [1:0] Rx_mac_BE, + output Rx_mac_sop, + output Rx_mac_eop, + output Rx_mac_err, + + output Tx_mac_wa, + input Tx_mac_wr, + input [31:0] Tx_mac_data, + input [1:0] Tx_mac_BE, + input Tx_mac_sop, + input Tx_mac_eop, + + // PHY interface (GMII/MII) + output Gtx_clk, // Used only in GMII mode + input Rx_clk, + input Tx_clk, // Used only in MII mode + output Tx_er, + output Tx_en, + output [7:0] Txd, + input Rx_er, + input Rx_dv, + input [7:0] Rxd, + input Crs, + input Col, + + // MDIO interface (to PHY) + inout Mdio, + output Mdc, + + // FIFO levels + output [15:0] rx_fifo_occupied, + output rx_fifo_full, + output rx_fifo_empty, + output [15:0] tx_fifo_occupied, + output tx_fifo_full, + output tx_fifo_empty, + + // Debug Interface + output [31:0] debug0, + output [31:0] debug1 +); + + wire rst_mac_rx = rst_mac; + wire rst_mac_tx = rst_mac; + wire [2:0] Speed; + + wire [31:0] debug_rx; + wire [31:0] debug_tx0; + wire [31:0] debug_tx1; + + //------------------------------------------------------------------------- + // Local declarations + //------------------------------------------------------------------------- + + // RMON interface + wire [15:0] Rx_pkt_length_rmon; + wire Rx_apply_rmon; + wire [2:0] Rx_pkt_err_type_rmon; + wire [2:0] Rx_pkt_type_rmon; + wire [2:0] Tx_pkt_type_rmon; + wire [15:0] Tx_pkt_length_rmon; + wire Tx_apply_rmon; + wire [2:0] Tx_pkt_err_type_rmon; + + // PHY interface + wire MCrs_dv; + wire [7:0] MRxD; + wire MRxErr; + + // Flow-control signals + wire [15:0] pause_quanta; + wire pause_quanta_val; + wire [15:0] rx_fifo_space; + wire pause_apply, pause_quanta_sub; + wire xon_gen, xoff_gen, xon_gen_complete, xoff_gen_complete; + wire [15:0] fc_hwmark, fc_lwmark; + + //PHY interface + wire [7:0] MTxD; + wire MTxEn; + wire MCRS; + + // Interface clk signals + wire MAC_tx_clk; + wire MAC_rx_clk; + wire MAC_tx_clk_div; + wire MAC_rx_clk_div; + + // Reg signals + wire [4:0] Tx_Hwmark; + wire [4:0] Tx_Lwmark; + wire pause_frame_send_en; + wire [15:0] pause_quanta_set; + wire MAC_tx_add_en; + wire FullDuplex; + wire [3:0] MaxRetry; + wire [5:0] IFGset; + wire [7:0] MAC_tx_add_prom_data; + wire [2:0] MAC_tx_add_prom_add; + wire MAC_tx_add_prom_wr; + wire tx_pause_en; + + // Rx host interface + wire MAC_rx_add_chk_en; + wire [7:0] MAC_rx_add_prom_data; + wire [2:0] MAC_rx_add_prom_add; + wire MAC_rx_add_prom_wr; + wire broadcast_filter_en; + wire RX_APPEND_CRC; + wire [4:0] Rx_Hwmark; + wire [4:0] Rx_Lwmark; + wire CRC_chk_en; + wire [5:0] RX_IFG_SET; + wire [15:0] RX_MAX_LENGTH; + wire [6:0] RX_MIN_LENGTH; + + // RMON host interface + wire [5:0] CPU_rd_addr; + wire CPU_rd_apply; + wire CPU_rd_grant; + wire [31:0] CPU_rd_dout; + + // PHY int host interface + wire Line_loop_en; + + // MII to CPU + wire [7:0] Divider; + wire [15:0] CtrlData; + wire [4:0] Rgad; + wire [4:0] Fiad; + wire NoPre; + wire WCtrlData; + wire RStat; + wire ScanStat; + wire Busy; + wire LinkFail; + wire Nvalid; + wire [15:0] Prsd; + wire WCtrlDataStart; + wire RStatStart; + wire UpdateMIIRX_DATAReg; + wire [15:0] broadcast_bucket_depth; + wire [15:0] broadcast_bucket_interval; + + //------------------------------------------------------------------------- + // Instantiation of sub-modules + //------------------------------------------------------------------------- + + MAC_rx #(.RX_FF_DEPTH(RX_FF_DEPTH)) + U_MAC_rx( + .Reset ( rst_mac_rx ), + .Clk_user ( Clk_user ), + .Clk ( MAC_rx_clk_div ), + + // RMII interface + .MCrs_dv ( MCrs_dv ), + .MRxD ( MRxD ), + .MRxErr ( MRxErr ), + + // Flow-control signals + .pause_quanta ( pause_quanta ), + .pause_quanta_val ( pause_quanta_val ), + .rx_fifo_space ( rx_fifo_space ), + + // User interface + .Rx_mac_empty ( Rx_mac_empty ), + .Rx_mac_rd ( Rx_mac_rd ), + .Rx_mac_data ( Rx_mac_data ), + .Rx_mac_BE ( Rx_mac_BE ), + .Rx_mac_sop ( Rx_mac_sop ), + .Rx_mac_eop ( Rx_mac_eop ), + .Rx_mac_err ( Rx_mac_err ), + + // CPU + .MAC_rx_add_chk_en ( MAC_rx_add_chk_en ), + .MAC_add_prom_data ( MAC_rx_add_prom_data ), + .MAC_add_prom_add ( MAC_rx_add_prom_add ), + .MAC_add_prom_wr ( MAC_rx_add_prom_wr ), + .broadcast_filter_en ( broadcast_filter_en ), + .broadcast_bucket_depth ( broadcast_bucket_depth ), + .broadcast_bucket_interval( broadcast_bucket_interval ), + .RX_APPEND_CRC ( RX_APPEND_CRC ), + .Rx_Hwmark ( Rx_Hwmark ), + .Rx_Lwmark ( Rx_Lwmark ), + .CRC_chk_en ( CRC_chk_en ), + .RX_IFG_SET ( RX_IFG_SET ), + .RX_MAX_LENGTH ( RX_MAX_LENGTH ), + .RX_MIN_LENGTH ( RX_MIN_LENGTH ), + + // RMON interface + .Rx_pkt_length_rmon ( Rx_pkt_length_rmon ), + .Rx_apply_rmon ( Rx_apply_rmon ), + .Rx_pkt_err_type_rmon ( Rx_pkt_err_type_rmon ), + .Rx_pkt_type_rmon ( Rx_pkt_type_rmon ), + + .rx_fifo_occupied(rx_fifo_occupied), + .rx_fifo_full(rx_fifo_full), + .rx_fifo_empty(rx_fifo_empty), + .debug(debug_rx) + ); + + MAC_tx #(.TX_FF_DEPTH(TX_FF_DEPTH)) + U_MAC_tx( + .Reset ( rst_mac_tx ), + .Clk ( MAC_tx_clk_div ), + //.Clk_user ( Clk_user ), + .Clk_user ( MAC_tx_clk_div ), + + // PHY interface + .TxD ( MTxD ), + .TxEn ( MTxEn ), + .CRS ( MCRS ), + + // RMON + .Tx_pkt_type_rmon ( Tx_pkt_type_rmon ), + .Tx_pkt_length_rmon ( Tx_pkt_length_rmon ), + .Tx_apply_rmon ( Tx_apply_rmon ), + .Tx_pkt_err_type_rmon( Tx_pkt_err_type_rmon ), + + // User interface + .Tx_mac_wa ( Tx_mac_wa ), + .Tx_mac_wr ( Tx_mac_wr ), + .Tx_mac_data ( Tx_mac_data ), + .Tx_mac_BE ( Tx_mac_BE ), + .Tx_mac_sop ( Tx_mac_sop ), + .Tx_mac_eop ( Tx_mac_eop ), + + // Host interface + .Tx_Hwmark ( Tx_Hwmark ), + .Tx_Lwmark ( Tx_Lwmark ), + .MAC_tx_add_en ( MAC_tx_add_en ), + .FullDuplex ( FullDuplex ), + .MaxRetry ( MaxRetry ), + .IFGset ( IFGset ), + .MAC_add_prom_data ( MAC_tx_add_prom_data ), + .MAC_add_prom_add ( MAC_tx_add_prom_add ), + .MAC_add_prom_wr ( MAC_tx_add_prom_wr ), + + .pause_apply ( pause_apply ), + .pause_quanta_sub ( pause_quanta_sub ), + .pause_quanta_set ( pause_quanta_set ), + .xoff_gen ( xoff_gen ), + .xon_gen ( xon_gen ), + .xoff_gen_complete ( xoff_gen_complete ), + .xon_gen_complete ( xon_gen_complete ), + .debug0(debug_tx0), + .debug1(debug_tx1) + ); + + // Flow control outbound -- when other side sends PAUSE, we wait + flow_ctrl_tx flow_ctrl_tx + (.rst(rst_mac_tx), + .tx_clk(MAC_tx_clk_div), + // Setting + .tx_pause_en ( tx_pause_en ), + // From RX side + .pause_quanta (pause_quanta), + .pause_quanta_val(pause_quanta_val), // Other guy sent a PAUSE + // To TX side + .pause_apply (pause_apply), // To TX, stop sending new frames + .pause_quanta_sub (pause_quanta_sub) // From TX, indicates we have used up 1 quanta + ); + + flow_ctrl_rx flow_ctrl_rx // When we are running out of RX space, send a PAUSE + (.rst(rst_mac_rx), // FIXME + // Settings + .pause_frame_send_en ( pause_frame_send_en ), + .pause_quanta_set ( pause_quanta_set ), + .fc_hwmark (fc_hwmark), + .fc_lwmark (fc_lwmark), + // From RX side + .rx_clk(MAC_rx_clk_div), + .rx_fifo_space (rx_fifo_space), // Decide if we need to send a PAUSE + // To TX side + .tx_clk(MAC_tx_clk_div), + .xoff_gen (xoff_gen), + .xon_gen(xon_gen), // Tell our TX to send PAUSE frames + .xoff_gen_complete (xoff_gen_complete), + .xon_gen_complete(xon_gen_complete) + ); + + RMON U_RMON( + .Clk ( CLK_I ), + .Reset ( RST_I ), + + // Tx RMON + .Tx_pkt_type_rmon ( Tx_pkt_type_rmon ), + .Tx_pkt_length_rmon ( Tx_pkt_length_rmon ), + .Tx_apply_rmon ( Tx_apply_rmon ), + .Tx_pkt_err_type_rmon( Tx_pkt_err_type_rmon ), + + // Rx RMON + .Rx_pkt_type_rmon ( Rx_pkt_type_rmon ), + .Rx_pkt_length_rmon ( Rx_pkt_length_rmon ), + .Rx_apply_rmon ( Rx_apply_rmon ), + .Rx_pkt_err_type_rmon( Rx_pkt_err_type_rmon ), + + // CPU + .CPU_rd_addr ( CPU_rd_addr ), + .CPU_rd_apply ( CPU_rd_apply ), + .CPU_rd_grant ( CPU_rd_grant ), + .CPU_rd_dout ( CPU_rd_dout ) + ); + + Phy_int U_Phy_int( + .rst_mac_rx ( rst_mac_rx ), + .rst_mac_tx ( rst_mac_tx ), + .MAC_rx_clk ( MAC_rx_clk ), + .MAC_tx_clk ( MAC_tx_clk ), + // Rx interface + .MCrs_dv ( MCrs_dv ), + .MRxD ( MRxD ), + .MRxErr ( MRxErr ), + // Tx interface + .MTxD ( MTxD ), + .MTxEn ( MTxEn ), + .MCRS ( MCRS ), + // PHY interface + .Tx_er ( Tx_er ), + .Tx_en ( Tx_en ), + .Txd ( Txd ), + .Rx_er ( Rx_er ), + .Rx_dv ( Rx_dv ), + .Rxd ( Rxd ), + .Crs ( Crs ), + .Col ( Col ), + // Host interface + .Line_loop_en( Line_loop_en ), + .Speed ( Speed ) ); + + Clk_ctrl U_Clk_ctrl( + .Reset ( rst_mac ), + .Clk_125M ( Clk_125M ), + + // Host interface + .Speed ( Speed ), + + // Phy interface + .Gtx_clk ( Gtx_clk ), + .Rx_clk ( Rx_clk ), + .Tx_clk ( Tx_clk ), + + // Interface clocks + .MAC_tx_clk ( MAC_tx_clk ), + .MAC_rx_clk ( MAC_rx_clk ), + .MAC_tx_clk_div( MAC_tx_clk_div ), + .MAC_rx_clk_div( MAC_rx_clk_div ) + ); + + eth_miim U_eth_miim( + .Clk ( CLK_I ), + .Reset ( RST_I ), + .Divider ( Divider ), + .NoPre ( NoPre ), + .CtrlData ( CtrlData ), + .Rgad ( Rgad ), + .Fiad ( Fiad ), + .WCtrlData ( WCtrlData ), + .RStat ( RStat ), + .ScanStat ( ScanStat ), + .Mdio ( Mdio ), + .Mdc ( Mdc ), + .Busy ( Busy ), + .Prsd ( Prsd ), + .LinkFail ( LinkFail ), + .Nvalid ( Nvalid ), + .WCtrlDataStart ( WCtrlDataStart ), + .RStatStart ( RStatStart ), + .UpdateMIIRX_DATAReg( UpdateMIIRX_DATAReg ) + ); + + Reg_int U_Reg_int( + // Wishbone compliant core host interface + .CLK_I( CLK_I ), + .RST_I( RST_I ), + .STB_I( STB_I ), + .CYC_I( CYC_I ), + .ADR_I( ADR_I ), + .WE_I ( WE_I ), + .DAT_I( DAT_I ), + .DAT_O( DAT_O ), + .ACK_O( ACK_O ), + + // Tx host interface + .Tx_Hwmark ( Tx_Hwmark ), + .Tx_Lwmark ( Tx_Lwmark ), + .MAC_tx_add_en ( MAC_tx_add_en ), + .FullDuplex ( FullDuplex ), + .MaxRetry ( MaxRetry ), + .IFGset ( IFGset ), + .MAC_tx_add_prom_data ( MAC_tx_add_prom_data ), + .MAC_tx_add_prom_add ( MAC_tx_add_prom_add ), + .MAC_tx_add_prom_wr ( MAC_tx_add_prom_wr ), + + // Rx host interface + .MAC_rx_add_chk_en ( MAC_rx_add_chk_en ), + .MAC_rx_add_prom_data ( MAC_rx_add_prom_data ), + .MAC_rx_add_prom_add ( MAC_rx_add_prom_add ), + .MAC_rx_add_prom_wr ( MAC_rx_add_prom_wr ), + .broadcast_filter_en ( broadcast_filter_en ), + .broadcast_bucket_depth ( broadcast_bucket_depth ), + .broadcast_bucket_interval( broadcast_bucket_interval ), + .RX_APPEND_CRC ( RX_APPEND_CRC ), + .Rx_Hwmark ( Rx_Hwmark ), + .Rx_Lwmark ( Rx_Lwmark ), + .CRC_chk_en ( CRC_chk_en ), + .RX_IFG_SET ( RX_IFG_SET ), + .RX_MAX_LENGTH ( RX_MAX_LENGTH ), + .RX_MIN_LENGTH ( RX_MIN_LENGTH ), + + // Flow Control settings + .pause_frame_send_en ( pause_frame_send_en ), + .pause_quanta_set ( pause_quanta_set ), + .tx_pause_en ( tx_pause_en ), + .fc_hwmark ( fc_hwmark ), + .fc_lwmark ( fc_lwmark ), + + // RMON host interface + .CPU_rd_addr ( CPU_rd_addr ), + .CPU_rd_apply ( CPU_rd_apply ), + .CPU_rd_grant ( CPU_rd_grant ), + .CPU_rd_dout ( CPU_rd_dout ), + + // PHY int host interface + .Line_loop_en ( Line_loop_en ), + .Speed ( Speed ), + + // MII to CPU + .Divider ( Divider ), + .CtrlData ( CtrlData ), + .Rgad ( Rgad ), + .Fiad ( Fiad ), + .NoPre ( NoPre ), + .WCtrlData ( WCtrlData ), + .RStat ( RStat ), + .ScanStat ( ScanStat ), + .Busy ( Busy ), + .LinkFail ( LinkFail ), + .Nvalid ( Nvalid ), + .Prsd ( Prsd ), + .WCtrlDataStart ( WCtrlDataStart ), + .RStatStart ( RStatStart ), + .UpdateMIIRX_DATAReg ( UpdateMIIRX_DATAReg ) + ); + + assign debug0 = {xon_gen, xoff_gen, Tx_en, Rx_dv}; + //assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen, xoff_gen_complete}, + // {1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]}, + // {rx_fifo_space}}; + //assign debug0 = debug_tx0; + //assign debug1 = debug_tx1; +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx.v new file mode 100644 index 00000000..50b08dff --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx.v @@ -0,0 +1,245 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_tx.v,v $ +// Revision 1.4 2006/11/17 17:53:07 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:14 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module MAC_tx + #(parameter TX_FF_DEPTH = 9) + ( +input Reset , +input Clk , +input Clk_user , + //PHY interface +output [7:0] TxD , +output TxEn , +input CRS , + //RMON +output [2:0] Tx_pkt_type_rmon , +output [15:0] Tx_pkt_length_rmon , +output Tx_apply_rmon , +output [2:0] Tx_pkt_err_type_rmon, + //user interface +output Tx_mac_wa , +input Tx_mac_wr , +input [31:0] Tx_mac_data , +input [1:0] Tx_mac_BE ,//big endian +input Tx_mac_sop , +input Tx_mac_eop , + //host interface +input [4:0] Tx_Hwmark , +input [4:0] Tx_Lwmark , +input MAC_tx_add_en , +input FullDuplex , +input [3:0] MaxRetry , +input [5:0] IFGset , +input [7:0] MAC_add_prom_data , +input [2:0] MAC_add_prom_add , +input MAC_add_prom_wr , + // Flow control stuff +input pause_apply , +output pause_quanta_sub, +input [15:0] pause_quanta_set , +input xoff_gen, +input xon_gen, +output xoff_gen_complete, +output xon_gen_complete, + output [31:0] debug0, + output [31:0] debug1 +); + + // ****************************************************************************** + // internal signals + // ****************************************************************************** + //CRC_gen Interface +wire CRC_init ; +wire[7:0] Frame_data ; +wire Data_en ; +wire CRC_rd ; +wire CRC_end ; +wire[7:0] CRC_out ; + //Random_gen interface +wire Random_init ; +wire[3:0] RetryCnt ; +wire Random_time_meet ;//levle hight indicate random time passed away + //flow control + //MAC_rx_FF +wire[7:0] Fifo_data ; +wire Fifo_rd ; +wire Fifo_eop ; +wire Fifo_da ; +wire Fifo_rd_finish ; +wire Fifo_rd_retry ; +wire Fifo_ra ; +wire Fifo_data_err_empty ; +wire Fifo_data_err_full ; + //MAC_tx_addr_add +wire MAC_tx_addr_init ; +wire MAC_tx_addr_rd ; +wire[7:0] MAC_tx_addr_data ; + +//****************************************************************************** +//instantiation +//****************************************************************************** +MAC_tx_ctrl U_MAC_tx_ctrl( +.Reset (Reset ), +.Clk (Clk ), + //CRC_gen Interface (//CRC_gen Interface ), +.CRC_init (CRC_init ), +.Frame_data (Frame_data ), +.Data_en (Data_en ), +.CRC_rd (CRC_rd ), +.CRC_end (CRC_end ), +.CRC_out (CRC_out ), + //Random_gen interfac (//Random_gen interfac ), +.Random_init (Random_init ), +.RetryCnt (RetryCnt ), +.Random_time_meet (Random_time_meet ), + //flow control (//flow control ), +.pause_apply (pause_apply ), +.pause_quanta_sub (pause_quanta_sub ), +.xoff_gen (xoff_gen ), +.xoff_gen_complete (xoff_gen_complete ), +.xon_gen (xon_gen ), +.xon_gen_complete (xon_gen_complete ), + //MAC_tx_FF (//MAC_tx_FF ), +.Fifo_data (Fifo_data ), +.Fifo_rd (Fifo_rd ), +.Fifo_eop (Fifo_eop ), +.Fifo_da (Fifo_da ), +.Fifo_rd_finish (Fifo_rd_finish ), +.Fifo_rd_retry (Fifo_rd_retry ), +.Fifo_ra (Fifo_ra ), +.Fifo_data_err_empty (Fifo_data_err_empty ), +.Fifo_data_err_full (Fifo_data_err_full ), + //RMII (//RMII ), +.TxD (TxD ), +.TxEn (TxEn ), +.CRS (CRS ), + //MAC_tx_addr_add (//MAC_tx_addr_add ), +.MAC_tx_addr_rd (MAC_tx_addr_rd ), +.MAC_tx_addr_data (MAC_tx_addr_data ), +.MAC_tx_addr_init (MAC_tx_addr_init ), + //RMON (//RMON ), +.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), +.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), +.Tx_apply_rmon (Tx_apply_rmon ), +.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //CPU (//CPU ), +.pause_quanta_set (pause_quanta_set ), +.MAC_tx_add_en (MAC_tx_add_en ), +.FullDuplex (FullDuplex ), +.MaxRetry (MaxRetry ), +.IFGset (IFGset ) +); + +CRC_gen U_CRC_gen( +.Reset (Reset ), +.Clk (Clk ), +.Init (CRC_init ), +.Frame_data (Frame_data ), +.Data_en (Data_en ), +.CRC_rd (CRC_rd ), +.CRC_out (CRC_out ), +.CRC_end (CRC_end ) +); + + MAC_tx_addr_add U_MAC_tx_addr_add + (.Reset (Reset ), + .Clk (Clk ), + .MAC_tx_addr_rd (MAC_tx_addr_rd ), + .MAC_tx_addr_init (MAC_tx_addr_init ), + .MAC_tx_addr_data (MAC_tx_addr_data ), + //CPU + .MAC_add_prom_data (MAC_add_prom_data ), + .MAC_add_prom_add (MAC_add_prom_add ), + .MAC_add_prom_wr (MAC_add_prom_wr ) + ); + +MAC_tx_FF #(.TX_FF_DEPTH(TX_FF_DEPTH)) U_MAC_tx_FF( +.Reset (Reset ), +.Clk_MAC (Clk ), +.Clk_SYS (Clk_user ), + //MAC_rx_ctrl interf (//MAC_rx_ctrl interf ), +.Fifo_data (Fifo_data ), +.Fifo_rd (Fifo_rd ), +.Fifo_rd_finish (Fifo_rd_finish ), +.Fifo_rd_retry (Fifo_rd_retry ), +.Fifo_eop (Fifo_eop ), +.Fifo_da (Fifo_da ), +.Fifo_ra (Fifo_ra ), +.Fifo_data_err_empty (Fifo_data_err_empty ), +.Fifo_data_err_full (Fifo_data_err_full ), + //user interface (//user interface ), +.Tx_mac_wa (Tx_mac_wa ), +.Tx_mac_wr (Tx_mac_wr ), +.Tx_mac_data (Tx_mac_data ), +.Tx_mac_BE (Tx_mac_BE ), +.Tx_mac_sop (Tx_mac_sop ), +.Tx_mac_eop (Tx_mac_eop ), + //host interface (//host interface ), +.FullDuplex (FullDuplex ), +.Tx_Hwmark (Tx_Hwmark ), +.Tx_Lwmark (Tx_Lwmark ), +.debug0(debug0), +.debug1(debug1) +); + +Random_gen U_Random_gen( +.Reset (Reset ), +.Clk (Clk ), +.Init (Random_init ), +.RetryCnt (RetryCnt ), +.Random_time_meet (Random_time_meet ) +); + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v new file mode 100644 index 00000000..4a16e7c3 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v @@ -0,0 +1,169 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CRC_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: CRC_gen.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module CRC_gen ( +Reset , +Clk , +Init , +Frame_data , +Data_en , +CRC_rd , +CRC_end , +CRC_out + +); +input Reset ; +input Clk ; +input Init ; +input [7:0] Frame_data ; +input Data_en ; +input CRC_rd ; +output [7:0] CRC_out ; +output CRC_end ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [7:0] CRC_out ; +reg [31:0] CRC_reg; +reg CRC_end; +reg [3:0] Counter; +//****************************************************************************** +//****************************************************************************** +//input data width is 8bit, and the first bit is bit[0] +function[31:0] NextCRC; + input[7:0] D; + input[31:0] C; + reg[31:0] NewCRC; + begin + NewCRC[0]=C[24]^C[30]^D[1]^D[7]; + NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; + NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; + NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; + NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; + NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; + NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; + NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; + NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4]; + NewCRC[20]=C[12]^C[28]^D[3]; + NewCRC[21]=C[13]^C[29]^D[2]; + NewCRC[22]=C[14]^C[24]^D[7]; + NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5]; + NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; + NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; + NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; + NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; + NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3]; + NewCRC[31]=C[23]^C[29]^D[2]; + NextCRC=NewCRC; + end + endfunction +//****************************************************************************** + +always @ (posedge Clk) // or posedge Reset) +// if (Reset) +// CRC_reg <=32'hffffffff; +// else + if (Init) + CRC_reg <=32'hffffffff; + else if (Data_en) + CRC_reg <=NextCRC(Frame_data,CRC_reg); + else if (CRC_rd) + CRC_reg <={CRC_reg[23:0],8'hff}; + +always @ (CRC_rd or CRC_reg) +// if (CRC_rd) + CRC_out <=~{ + CRC_reg[24], + CRC_reg[25], + CRC_reg[26], + CRC_reg[27], + CRC_reg[28], + CRC_reg[29], + CRC_reg[30], + CRC_reg[31] + }; +// else +// CRC_out <=0; + +//caculate CRC out length ,4 cycles +//CRC_end aligned to last CRC checksum data +always @(posedge Clk or posedge Reset) + if (Reset) + Counter <=0; + else if (!CRC_rd) + Counter <=0; + else + Counter <=Counter + 1; + +always @ (Counter) + if (Counter==3) + CRC_end=1; + else + CRC_end=0; + +endmodule + + diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v new file mode 100644 index 00000000..e62346fb --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v @@ -0,0 +1,722 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_FF.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module MAC_tx_FF + #(parameter TX_FF_DEPTH = 9) + (input Reset , + input Clk_MAC , + input Clk_SYS , + //MAC_tx_ctrl + output reg [7:0]Fifo_data , + input Fifo_rd , + input Fifo_rd_finish , + input Fifo_rd_retry , + output reg Fifo_eop , + output reg Fifo_da , + output reg Fifo_ra , + output reg Fifo_data_err_empty , + output Fifo_data_err_full , + //user interface + output reg Tx_mac_wa , + input Tx_mac_wr , + input [31:0] Tx_mac_data , + input [1:0] Tx_mac_BE ,//big endian + input Tx_mac_sop , + input Tx_mac_eop , + //host interface + input FullDuplex , + input [4:0] Tx_Hwmark , + input [4:0] Tx_Lwmark , + output [31:0] debug0, + output [31:0] debug1 + ); + +//****************************************************************************** +//internal signals +//****************************************************************************** +localparam MAC_byte3 =4'd00; +localparam MAC_byte2 =4'd01; +localparam MAC_byte1 =4'd02; +localparam MAC_byte0 =4'd03; +localparam MAC_wait_finish =4'd04; +localparam MAC_retry =4'd08; +localparam MAC_idle =4'd09; +localparam MAC_FFEmpty =4'd10; +localparam MAC_FFEmpty_drop =4'd11; +localparam MAC_pkt_sub =4'd12; +localparam MAC_FF_Err =4'd13; + + +reg [3:0] Next_state_MAC ; + + +localparam SYS_idle =4'd0; +localparam SYS_WaitSop =4'd1; +localparam SYS_SOP =4'd2; +localparam SYS_MOP =4'd3; +localparam SYS_DROP =4'd4; +localparam SYS_EOP_ok =4'd5; +localparam SYS_FFEmpty =4'd6; +localparam SYS_EOP_err =4'd7; +localparam SYS_SOP_err =4'd8; + +reg [3:0] Next_state_SYS; + +reg [TX_FF_DEPTH-1:0] Add_wr ; +reg [TX_FF_DEPTH-1:0] Add_wr_ungray ; +reg [TX_FF_DEPTH-1:0] Add_wr_gray ; +reg [TX_FF_DEPTH-1:0] Add_wr_gray_dl1 ; +reg [TX_FF_DEPTH-1:0] Add_wr_gray_dl2 ; + +reg [TX_FF_DEPTH-1:0] Add_rd ; +reg [TX_FF_DEPTH-1:0] Add_rd_reg ; +reg [TX_FF_DEPTH-1:0] Add_rd_gray ; +reg [TX_FF_DEPTH-1:0] Add_rd_gray_dl1 ; +reg [TX_FF_DEPTH-1:0] Add_rd_gray_dl2 ; +reg [TX_FF_DEPTH-1:0] Add_rd_ungray ; +wire[35:0] Din ; +wire[35:0] Dout ; +reg Wr_en ; +wire[TX_FF_DEPTH-1:0] Add_wr_pluse; +wire[TX_FF_DEPTH-1:0] Add_wr_pluse_pluse; +reg [TX_FF_DEPTH-1:TX_FF_DEPTH-5] Add_rd_reg_dl1; + +reg [3:0] Current_state_MAC; +reg [3:0] Current_state_MAC_reg; +reg [3:0] Current_state_SYS; +reg Full; +reg AlmostFull; +reg Empty; +reg [35:0] Dout_reg; +reg Packet_number_sub_edge; +reg Packet_number_add; +reg [5:0] Packet_number_inFF; +reg [5:0] Packet_number_inFF_reg; +reg Dout_reg_en; +reg Add_rd_add; + + +reg Tx_mac_wr_dl1 ; +reg [31:0] Tx_mac_data_dl1 ; +reg [1:0] Tx_mac_BE_dl1 ; +reg FF_FullErr ; +wire[1:0] Dout_BE ; +wire Dout_eop ; +wire Dout_err ; +wire[31:0] Dout_data ; +reg Packet_number_sub_dl1 ; +reg Packet_number_sub_dl2 ; +reg [4:0] Fifo_data_count ; +reg Fifo_ra_tmp ; +reg Pkt_sub_apply_tmp ; +reg Pkt_sub_apply ; +reg Add_rd_reg_rdy_tmp ; +reg Add_rd_reg_rdy ; +reg Add_rd_reg_rdy_dl1 ; +reg Add_rd_reg_rdy_dl2 ; +reg [4:0] Tx_Hwmark_pl ; +reg [4:0] Tx_Lwmark_pl ; +reg Add_rd_jump_tmp ; +reg Add_rd_jump_tmp_pl1 ; +reg Add_rd_jump ; +reg Add_rd_jump_wr_pl1 ; + +//****************************************************************************** +//write data to from FF . +//domain Clk_SYS +//****************************************************************************** +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Current_state_SYS <=SYS_idle; + else + Current_state_SYS <=Next_state_SYS; + +always @ (Current_state_SYS or Tx_mac_wr or Tx_mac_sop or Full or AlmostFull + or Tx_mac_eop ) + case (Current_state_SYS) + SYS_idle: + if (Tx_mac_wr&&Tx_mac_sop&&!Full) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =Current_state_SYS ; + SYS_SOP: + Next_state_SYS =SYS_MOP; + SYS_MOP: + if (AlmostFull) + Next_state_SYS =SYS_DROP; + else if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP_err; + else if (Tx_mac_wr&&Tx_mac_eop) + Next_state_SYS =SYS_EOP_ok; + else + Next_state_SYS =Current_state_SYS ; + SYS_EOP_ok: + if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =SYS_idle; + SYS_EOP_err: + if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =SYS_idle; + SYS_SOP_err: + Next_state_SYS =SYS_DROP; + SYS_DROP: //FIFO overflow + if (Tx_mac_wr&&Tx_mac_eop) + Next_state_SYS =SYS_EOP_err; + else + Next_state_SYS =Current_state_SYS ; + default: + Next_state_SYS =SYS_idle; + endcase + +//delay signals +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Tx_mac_wr_dl1 <=0; + Tx_mac_data_dl1 <=0; + Tx_mac_BE_dl1 <=0; + end + else + begin + Tx_mac_wr_dl1 <=Tx_mac_wr ; + Tx_mac_data_dl1 <=Tx_mac_data ; + Tx_mac_BE_dl1 <=Tx_mac_BE ; + end + +always @(Current_state_SYS) + if (Current_state_SYS==SYS_EOP_err) + FF_FullErr =1; + else + FF_FullErr =0; + +reg Tx_mac_eop_gen; + +always @(Current_state_SYS) + if (Current_state_SYS==SYS_EOP_err||Current_state_SYS==SYS_EOP_ok) + Tx_mac_eop_gen =1; + else + Tx_mac_eop_gen =0; + +assign Din={Tx_mac_eop_gen,FF_FullErr,Tx_mac_BE_dl1,Tx_mac_data_dl1}; + +always @(Current_state_SYS or Tx_mac_wr_dl1) + if ((Current_state_SYS==SYS_SOP||Current_state_SYS==SYS_EOP_ok|| + Current_state_SYS==SYS_MOP||Current_state_SYS==SYS_EOP_err)&&Tx_mac_wr_dl1) + Wr_en = 1; + else + Wr_en = 0; + + +// + + +always @ (posedge Reset or posedge Clk_SYS) + if (Reset) + Add_wr_gray <=0; + else + begin : Add_wr_gray_loop + integer i; + Add_wr_gray[TX_FF_DEPTH-1] <=Add_wr[TX_FF_DEPTH-1]; + for (i=TX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_gray_dl1 <=0; + else + Add_rd_gray_dl1 <=Add_rd_gray; + + always @(posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_gray_dl2 <= 0; + else + Add_rd_gray_dl2 <= Add_rd_gray_dl1; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_jump_wr_pl1 <=0; + else + Add_rd_jump_wr_pl1 <=Add_rd_jump; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_ungray =0; + else if (!Add_rd_jump_wr_pl1) + begin : Add_rd_ungray_loop + integer i; + Add_rd_ungray[TX_FF_DEPTH-1] = Add_rd_gray_dl2[TX_FF_DEPTH-1]; + for (i=TX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_ungray[i] = Add_rd_ungray[i+1]^Add_rd_gray_dl2[i]; + end + +assign Add_wr_pluse =Add_wr+1; +assign Add_wr_pluse_pluse =Add_wr+4; + +always @ (Add_wr_pluse or Add_rd_ungray) + if (Add_wr_pluse==Add_rd_ungray) + Full =1; + else + Full =0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + AlmostFull <=0; + else if (Add_wr_pluse_pluse==Add_rd_ungray) + AlmostFull <=1; + else + AlmostFull <=0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr <= 0; + else if (Wr_en&&!Full) + Add_wr <= Add_wr +1; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Packet_number_sub_dl1 <=0; + Packet_number_sub_dl2 <=0; + end + else + begin + Packet_number_sub_dl1 <=Pkt_sub_apply; + Packet_number_sub_dl2 <=Packet_number_sub_dl1; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_sub_edge <=0; + else if (Packet_number_sub_dl1&!Packet_number_sub_dl2) + Packet_number_sub_edge <=1; + else + Packet_number_sub_edge <=0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_add <=0; + else if (Current_state_SYS==SYS_EOP_ok||Current_state_SYS==SYS_EOP_err) + Packet_number_add <=1; + else + Packet_number_add <=0; + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF <=0; + else if (Packet_number_add&&!Packet_number_sub_edge) + Packet_number_inFF <=Packet_number_inFF + 1'b1; + else if (!Packet_number_add&&Packet_number_sub_edge) + Packet_number_inFF <=Packet_number_inFF - 1'b1; + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF_reg <=0; + else + Packet_number_inFF_reg <=Packet_number_inFF; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Add_rd_reg_rdy_dl1 <=0; + Add_rd_reg_rdy_dl2 <=0; + end + else + begin + Add_rd_reg_rdy_dl1 <=Add_rd_reg_rdy; + Add_rd_reg_rdy_dl2 <=Add_rd_reg_rdy_dl1; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_reg_dl1 <=0; + else if (Add_rd_reg_rdy_dl1&!Add_rd_reg_rdy_dl2) + Add_rd_reg_dl1 <=Add_rd_reg[TX_FF_DEPTH-1:TX_FF_DEPTH-5]; + + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_data_count <=0; + else if (FullDuplex) + Fifo_data_count <=Add_wr[TX_FF_DEPTH-1:TX_FF_DEPTH-5]-Add_rd_ungray[TX_FF_DEPTH-1:TX_FF_DEPTH-5]; + else + Fifo_data_count <=Add_wr[TX_FF_DEPTH-1:TX_FF_DEPTH-5]-Add_rd_reg_dl1[TX_FF_DEPTH-1:TX_FF_DEPTH-5]; //for half duplex backoff requirement + + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_ra_tmp <=0; + else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Lwmark) + Fifo_ra_tmp <=1; + else + Fifo_ra_tmp <=0; + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Tx_Hwmark_pl <=0; + Tx_Lwmark_pl <=0; + end + else + begin + Tx_Hwmark_pl <=Tx_Hwmark; + Tx_Lwmark_pl <=Tx_Lwmark; + end + +always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Tx_mac_wa <=0; + else if (Fifo_data_count>=Tx_Hwmark_pl) + Tx_mac_wa <=0; + else if (Fifo_data_count=0;i=i-1) + Add_rd_gray[i] <= Add_rd[i+1]^Add_rd[i]; + end +// + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_gray_dl1 <=0; + else + Add_wr_gray_dl1 <=Add_wr_gray; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_gray_dl2 <=0; + else + Add_wr_gray_dl2 <=Add_wr_gray_dl1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_ungray =0; + else + begin : Add_wr_ungray_loop + integer i; + Add_wr_ungray[TX_FF_DEPTH-1] = Add_wr_gray_dl2[TX_FF_DEPTH-1]; + for (i=TX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_ungray[i] = Add_wr_ungray[i+1]^Add_wr_gray_dl2[i]; + end + +//empty +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Empty <=1; + else if (Add_rd==Add_wr_ungray) + Empty <=1; + else + Empty <=0; + +//ra +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_ra <=0; + else + Fifo_ra <=Fifo_ra_tmp; + + + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Pkt_sub_apply_tmp <=0; + else if (Current_state_MAC==MAC_pkt_sub) + Pkt_sub_apply_tmp <=1; + else + Pkt_sub_apply_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Pkt_sub_apply <=0; + else if ((Current_state_MAC==MAC_pkt_sub)||Pkt_sub_apply_tmp) + Pkt_sub_apply <=1; + else + Pkt_sub_apply <=0; + +//reg Add_rd for collison retry +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg <=0; + else if (Fifo_rd_finish) + Add_rd_reg <=Add_rd; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg_rdy_tmp <=0; + else if (Fifo_rd_finish) + Add_rd_reg_rdy_tmp <=1; + else + Add_rd_reg_rdy_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg_rdy <=0; + else if (Fifo_rd_finish||Add_rd_reg_rdy_tmp) + Add_rd_reg_rdy <=1; + else + Add_rd_reg_rdy <=0; + + +always @ (Current_state_MAC or Next_state_MAC) + if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3) + Add_rd_add =1; + else + Add_rd_add =0; + + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd <= Add_rd_reg; + else if (Add_rd_add) + Add_rd <= Add_rd + 1; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump_tmp <=1; + else + Add_rd_jump_tmp <=0; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp_pl1 <=0; + else + Add_rd_jump_tmp_pl1 <=Add_rd_jump_tmp; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump <=1; + else if (Add_rd_jump_tmp_pl1) + Add_rd_jump <=0; + +//gen Fifo_data + + +always @ (Dout_data or Current_state_MAC) + case (Current_state_MAC) + MAC_byte3: + Fifo_data =Dout_data[31:24]; + MAC_byte2: + Fifo_data =Dout_data[23:16]; + MAC_byte1: + Fifo_data =Dout_data[15:8]; + MAC_byte0: + Fifo_data =Dout_data[7:0]; + default: + Fifo_data =0; + endcase + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_da <=0; + else if ((Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1|| + Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)&&Fifo_rd&&!Fifo_eop) + Fifo_da <=1; + else + Fifo_da <=0; + +//gen Fifo_data_err_empty +assign Fifo_data_err_full=Dout_err; +//gen Fifo_data_err_empty +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Current_state_MAC_reg <=0; + else + Current_state_MAC_reg <=Current_state_MAC; + +always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_err_empty <=0; + else if (Current_state_MAC_reg==MAC_FFEmpty) + Fifo_data_err_empty <=1; + else + Fifo_data_err_empty <=0; + +//always @ (posedge Clk_MAC) +// if (Current_state_MAC_reg==MAC_FF_Err) +// begin +// $finish(2); +// $display("mac_tx_FF meet error status at time :%t",$time); +// end + +//gen Fifo_eop aligned to last valid data byte +always @ ( Current_state_MAC or Dout_eop or Dout_BE ) + if ( ( ( Current_state_MAC==MAC_byte0 && Dout_BE==2'b00 ) || + ( Current_state_MAC==MAC_byte1 && Dout_BE==2'b11 ) || + ( Current_state_MAC==MAC_byte2 && Dout_BE==2'b10 ) || + ( Current_state_MAC==MAC_byte3 && Dout_BE==2'b01 ) ) && Dout_eop ) + Fifo_eop = 1; + else + Fifo_eop = 0; + + // Dual port RAM for FIFO + ram_2port #(.DWIDTH(36),.AWIDTH(TX_FF_DEPTH)) mac_tx_ff_ram + (.clka(Clk_SYS),.ena(1'b1),.wea(Wr_en),.addra(Add_wr),.dia(Din),.doa(), + .clkb(Clk_MAC),.enb(1'b1),.web(1'b0),.addrb(Add_rd),.dib(36'b0),.dob(Dout) ); + + assign debug0 = + { { 5'd0, Empty, Full, AlmostFull }, + { Current_state_SYS, Current_state_MAC }, + { Fifo_rd, Fifo_rd_finish, Fifo_rd_retry, Fifo_eop, Fifo_da, Fifo_ra, Fifo_data_err_empty, Fifo_data_err_full }, + { 2'b0, Dout_BE, Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop} }; + + assign debug1 = + { { 8'd0 }, + { 8'd0 }, + { 8'd0 }, + { 8'd0 } }; + +endmodule // MAC_tx_FF diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v new file mode 100644 index 00000000..76026ce0 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v @@ -0,0 +1,128 @@ +// //////////////////////////////////////////////////////////////////// +// // //// +// // MAC_tx_addr_add.v //// +// // //// +// // This file is part of the Ethernet IP core project //// +// // http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode///// +// // //// +// // Author(s): //// +// // - Jon Gao (gaojon@yahoo.com) //// +// // //// +// // //// +// //////////////////////////////////////////////////////////////////// +// // //// +// // Copyright (C) 2001 Authors //// +// // //// +// // This source file may be used and distributed without //// +// // restriction provided that this copyright statement is not //// +// // removed from the file and that any derivative work contains //// +// // the original copyright notice and the associated disclaimer. //// +// // //// +// // This source file is free software; you can redistribute it //// +// // and/or modify it under the terms of the GNU Lesser General //// +// // Public License as published by the Free Software Foundation; //// +// // either version 2.1 of the License, or (at your option) any //// +// // later version. //// +// // //// +// // This source is distributed in the hope that it will be //// +// // useful, but WITHOUT ANY WARRANTY; without even the implied //// +// // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +// // PURPOSE. See the GNU Lesser General Public License for more //// +// // details. //// +// // //// +// // You should have received a copy of the GNU Lesser General //// +// // Public License along with this source; if not, download it //// +// // from http://www.opencores.org/lgpl.shtml //// +// // //// +// //////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_tx_addr_add.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:18 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_tx_addr_add + (Reset , + Clk , + MAC_tx_addr_init , + MAC_tx_addr_rd , + MAC_tx_addr_data , + //CPU , + MAC_add_prom_data , + MAC_add_prom_add , + MAC_add_prom_wr + ); + + input Reset ; + input Clk ; + input MAC_tx_addr_rd ; + input MAC_tx_addr_init ; + output [7:0] MAC_tx_addr_data ; + //CPU ; + input [7:0] MAC_add_prom_data ; + input [2:0] MAC_add_prom_add ; + input MAC_add_prom_wr ; + + // ****************************************************************************** + // internal signals + // ****************************************************************************** + reg [2:0] add_rd; + wire [2:0] add_wr; + wire [7:0] din; + //wire [7:0] dout; + reg [7:0] dout; + wire wr_en; + reg MAC_add_prom_wr_dl1; + reg MAC_add_prom_wr_dl2; + // ****************************************************************************** + // write data from cpu to prom + // ****************************************************************************** + always @ (posedge Clk or posedge Reset) + if (Reset) + begin + MAC_add_prom_wr_dl1 <=0; + MAC_add_prom_wr_dl2 <=0; + end + else + begin + MAC_add_prom_wr_dl1 <=MAC_add_prom_wr; + MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1; + end + + assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2; + assign add_wr =MAC_add_prom_add; + assign din =MAC_add_prom_data; + + // ****************************************************************************** + // read data from cpu to prom + // ****************************************************************************** + always @ (posedge Clk or posedge Reset) + if (Reset) + add_rd <=0; + else if (MAC_tx_addr_init) + add_rd <=0; + else if (MAC_tx_addr_rd) + add_rd <=add_rd + 1; + assign MAC_tx_addr_data=dout; + // ****************************************************************************** + // b port for read ,a port for write . + // ****************************************************************************** + + reg [7:0] address_ram [0:7]; + always @(posedge Clk) + if(wr_en) + address_ram[add_wr] <= din; + + always @(posedge Clk) + dout <= address_ram[add_rd]; + +endmodule // MAC_tx_addr_add diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v new file mode 100644 index 00000000..0fd7c603 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v @@ -0,0 +1,648 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_tx_Ctrl.v,v $ +// Revision 1.4 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:38 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_tx_ctrl ( +Reset , +Clk , +//CRC_gen Interface +CRC_init , +Frame_data , +Data_en , +CRC_rd , +CRC_end , +CRC_out , +//Ramdon_gen interfac +Random_init , +RetryCnt , +Random_time_meet , +//flow control +pause_apply , +pause_quanta_sub , +xoff_gen , +xoff_gen_complete , +xon_gen , +xon_gen_complete , +//MAC_tx_FF +Fifo_data , +Fifo_rd , +Fifo_eop , +Fifo_da , +Fifo_rd_finish , +Fifo_rd_retry , +Fifo_ra , +Fifo_data_err_empty , +Fifo_data_err_full , +//RMII +TxD , +TxEn , +CRS , +//MAC_tx_addr_add +MAC_tx_addr_rd , +MAC_tx_addr_data , +MAC_tx_addr_init , +//RMON +Tx_pkt_type_rmon , +Tx_pkt_length_rmon , +Tx_apply_rmon , +Tx_pkt_err_type_rmon, +//CPU +pause_quanta_set , +MAC_tx_add_en , +FullDuplex , +MaxRetry , +IFGset +); + +input Reset ; +input Clk ; + //CRC_gen Interface +output CRC_init ; +output [7:0] Frame_data ; +output Data_en ; +output CRC_rd ; +input CRC_end ; +input [7:0] CRC_out ; + //Ramdon_gen interface +output Random_init ; +output [3:0] RetryCnt ; +input Random_time_meet ;//levle hight indicate random time passed away + //flow control +input pause_apply ; +output pause_quanta_sub ; +input xoff_gen ; +output xoff_gen_complete ; +input xon_gen ; +output xon_gen_complete ; + //MAC_rx_FF +input [7:0] Fifo_data ; +output Fifo_rd ; +input Fifo_eop ; +input Fifo_da ; +output Fifo_rd_finish ; +output Fifo_rd_retry ; +input Fifo_ra ; +input Fifo_data_err_empty ; +input Fifo_data_err_full ; + //RMII +output [7:0] TxD ; +output TxEn ; +input CRS ; + //MAC_tx_addr_add +output MAC_tx_addr_init ; +output MAC_tx_addr_rd ; +input [7:0] MAC_tx_addr_data ; + //RMON +output [2:0] Tx_pkt_type_rmon ; +output [15:0] Tx_pkt_length_rmon ; +output Tx_apply_rmon ; +output [2:0] Tx_pkt_err_type_rmon; + //CPU +input [15:0] pause_quanta_set ; +input MAC_tx_add_en ; +input FullDuplex ; +input [3:0] MaxRetry ; +input [5:0] IFGset ; +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter StateIdle =4'd00; +parameter StatePreamble =4'd01; +parameter StateSFD =4'd02; +parameter StateData =4'd03; +parameter StatePause =4'd04; +parameter StatePAD =4'd05; +parameter StateFCS =4'd06; +parameter StateIFG =4'd07; +parameter StateJam =4'd08; +parameter StateBackOff =4'd09; +parameter StateJamDrop =4'd10; +parameter StateFFEmptyDrop =4'd11; +parameter StateSwitchNext =4'd12; +parameter StateDefer =4'd13; +parameter StateSendPauseFrame =4'd14; + +reg [3:0] Current_state; +reg [3:0] Next_state; +reg [5:0] IFG_counter; +reg [4:0] Preamble_counter;// +reg [7:0] TxD_tmp ; +reg TxEn_tmp ; +reg [15:0] Tx_pkt_length_rmon ; +reg Tx_apply_rmon ; +reg [2:0] Tx_pkt_err_type_rmon; +reg [3:0] RetryCnt ; +reg Random_init ; +reg Fifo_rd_finish ; +reg Fifo_rd_retry ; +reg [7:0] TxD ; +reg TxEn ; +reg CRC_init ; +reg Data_en ; +reg CRC_rd ; +reg Fifo_rd ; +reg MAC_tx_addr_rd ; +reg MAC_header_slot ; +reg MAC_header_slot_tmp ; +reg [2:0] Tx_pkt_type_rmon ; +wire Collision ; +reg MAC_tx_addr_init ; +reg Src_MAC_ptr ; +reg [7:0] IPLengthCounter ;//for pad append +reg [1:0] PADCounter ; +reg [7:0] JamCounter ; +reg PktDrpEvenPtr ; +reg [7:0] pause_counter ; +reg pause_quanta_sub ; +reg [15:0] pause_quanta_set_dl1 ; +reg xoff_gen_complete ; +reg xon_gen_complete ; +//****************************************************************************** +//boundery signal processing +//****************************************************************************** +always @(posedge Clk or posedge Reset) + if (Reset) + begin + pause_quanta_set_dl1 <=0; + end + else + begin + pause_quanta_set_dl1 <=pause_quanta_set ; + end +//****************************************************************************** +//state machine +//****************************************************************************** +assign Collision=TxEn&CRS; + +always @(posedge Clk or posedge Reset) + if (Reset) + IPLengthCounter <=0; + else if (Current_state==StateDefer) + IPLengthCounter <=0; + else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)) + IPLengthCounter <=IPLengthCounter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + PADCounter <=0; + else if (Current_state!=StatePAD) + PADCounter <=0; + else + PADCounter <=PADCounter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + Current_state <=StateDefer; + else + Current_state <=Next_state; + +always @ (*) + case (Current_state) + StateDefer: + if ((FullDuplex)||(!FullDuplex&&!CRS)) + Next_state=StateIFG; + else + Next_state=Current_state; + StateIFG: + if (!FullDuplex&&CRS) + Next_state=StateDefer; + else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time + Next_state=StateIdle; + else + Next_state=Current_state; + StateIdle: + if (!FullDuplex&&CRS) + Next_state=StateDefer; + else if (xoff_gen||xon_gen) + Next_state=StatePreamble; + else if (pause_apply) + Next_state=StatePause; + else if ((FullDuplex||~CRS)&&Fifo_ra) + Next_state=StatePreamble; + else + Next_state=Current_state; + StatePause: + if (pause_counter==512/8) + Next_state=StateDefer; + else if (xoff_gen||xon_gen) + Next_state=StateIdle; + else + Next_state=Current_state; + StatePreamble: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if ((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6)) + Next_state=StateSFD; + else + Next_state=Current_state; + StateSFD: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (xoff_gen||xon_gen) + Next_state=StateSendPauseFrame; + else + Next_state=StateData; + StateSendPauseFrame: + if (IPLengthCounter==17) + Next_state=StatePAD; + else + Next_state=Current_state; + StateData: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (Fifo_data_err_empty) + Next_state=StateFFEmptyDrop; + else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0 + Next_state=StateFCS; + else if (Fifo_eop) + Next_state=StatePAD; + else + Next_state=StateData; + StatePAD: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (IPLengthCounter>=59) + Next_state=StateFCS; + else + Next_state=Current_state; + StateJam: + if (RetryCnt<=MaxRetry&&JamCounter==16) + Next_state=StateBackOff; + else if (RetryCnt>MaxRetry) + Next_state=StateJamDrop; + else + Next_state=Current_state; + StateBackOff: + if (Random_time_meet) + Next_state =StateDefer; + else + Next_state =Current_state; + StateFCS: + if (!FullDuplex&&Collision) + Next_state =StateJam; + else if (CRC_end) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateFFEmptyDrop: + if (Fifo_eop) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateJamDrop: + if (Fifo_eop) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateSwitchNext: + Next_state =StateDefer; + default: + Next_state =StateDefer; + endcase + + + +always @ (posedge Clk or posedge Reset) + if (Reset) + JamCounter <=0; + else if (Current_state!=StateJam) + JamCounter <=0; + else if (Current_state==StateJam) + JamCounter <=JamCounter+1; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + RetryCnt <=0; + else if (Current_state==StateSwitchNext) + RetryCnt <=0; + else if (Current_state==StateJam&&Next_state==StateBackOff) + RetryCnt <=RetryCnt + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + IFG_counter <=0; + else if (Current_state!=StateIFG) + IFG_counter <=0; + else + IFG_counter <=IFG_counter + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Preamble_counter <=0; + else if (Current_state!=StatePreamble) + Preamble_counter <=0; + else + Preamble_counter <=Preamble_counter+ 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + PktDrpEvenPtr <=0; + else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop) + PktDrpEvenPtr <=~PktDrpEvenPtr; +//****************************************************************************** +//generate output signals +//****************************************************************************** +//CRC related +always @(Current_state) + if (Current_state==StateSFD) + CRC_init =1; + else + CRC_init =0; + +assign Frame_data=TxD_tmp; + +always @(Current_state) + if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD) + Data_en =1; + else + Data_en =0; + +always @(Current_state) + if (Current_state==StateFCS) + CRC_rd =1; + else + CRC_rd =0; + +//Ramdon_gen interface +always @(Current_state or Next_state) + if (Current_state==StateJam&&Next_state==StateBackOff) + Random_init =1; + else + Random_init =0; + +//MAC_rx_FF +//data have one cycle delay after fifo read signals +always @ (*) + if (Current_state==StateData || + Current_state==StateSFD&&!(xoff_gen||xon_gen) || + Current_state==StateJamDrop&&PktDrpEvenPtr|| + Current_state==StateFFEmptyDrop&&PktDrpEvenPtr ) + Fifo_rd =1; + else + Fifo_rd =0; + +always @ (Current_state) + if (Current_state==StateSwitchNext) + Fifo_rd_finish =1; + else + Fifo_rd_finish =0; + +always @ (Current_state) + if (Current_state==StateJam) + Fifo_rd_retry =1; + else + Fifo_rd_retry =0; +//RMII +always @(Current_state) + if (Current_state==StatePreamble||Current_state==StateSFD|| + Current_state==StateData||Current_state==StateSendPauseFrame|| + Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam) + TxEn_tmp =1; + else + TxEn_tmp =0; + +//gen txd data +always @(*) + case (Current_state) + StatePreamble: + TxD_tmp =8'h55; + StateSFD: + TxD_tmp =8'hd5; + StateData: + if (Src_MAC_ptr&&MAC_tx_add_en) + TxD_tmp =MAC_tx_addr_data; + else + TxD_tmp =Fifo_data; + StateSendPauseFrame: + if (Src_MAC_ptr&&MAC_tx_add_en) + TxD_tmp =MAC_tx_addr_data; + else + case (IPLengthCounter) + 8'd0: TxD_tmp =8'h01; + 8'd1: TxD_tmp =8'h80; + 8'd2: TxD_tmp =8'hc2; + 8'd3: TxD_tmp =8'h00; + 8'd4: TxD_tmp =8'h00; + 8'd5: TxD_tmp =8'h01; + 8'd12: TxD_tmp =8'h88;//type + 8'd13: TxD_tmp =8'h08;// + 8'd14: TxD_tmp =8'h00;//opcode + 8'd15: TxD_tmp =8'h01; + 8'd16: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8]; + 8'd17: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0]; +// 8'd60: TxD_tmp =8'h26; +// 8'd61: TxD_tmp =8'h6b; +// 8'd62: TxD_tmp =8'hae; +// 8'd63: TxD_tmp =8'h0a; + default:TxD_tmp =0; + endcase + + StatePAD: + TxD_tmp =8'h00; + StateJam: + TxD_tmp =8'h01; //jam sequence + StateFCS: + TxD_tmp =CRC_out; + default: + TxD_tmp =2'b0; + endcase +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + TxD <=0; + TxEn <=0; + end + else + begin + TxD <=TxD_tmp; + TxEn <=TxEn_tmp; + end +//RMON + + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_length_rmon <=0; + else if (Current_state==StateSFD) + Tx_pkt_length_rmon <=0; + else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS) + Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1; + + +reg [2:0] Tx_apply_rmon_reg; + +always @( posedge Clk or posedge Reset ) + if ( Reset ) + begin + Tx_apply_rmon <= 0; + Tx_apply_rmon_reg <= 'b0; + end + else + begin + if ( (Fifo_eop&&Current_state==StateJamDrop) || + (Fifo_eop&&Current_state==StateFFEmptyDrop) || + CRC_end ) + Tx_apply_rmon <= 1; + else + if ( Tx_apply_rmon_reg[2] ) + Tx_apply_rmon <= 0; + + Tx_apply_rmon_reg <= { Tx_apply_rmon_reg[1:0], Tx_apply_rmon }; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_err_type_rmon <=0; + else if(Fifo_eop&&Current_state==StateJamDrop) + Tx_pkt_err_type_rmon <=3'b001;// + else if(Fifo_eop&&Current_state==StateFFEmptyDrop) + Tx_pkt_err_type_rmon <=3'b010;//underflow + else if(Fifo_eop&&Fifo_data_err_full) + Tx_pkt_err_type_rmon <=3'b011;//overflow + else if(CRC_end) + Tx_pkt_err_type_rmon <=3'b100;//normal + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_header_slot_tmp <=0; + else if(Current_state==StateSFD&&Next_state==StateData) + MAC_header_slot_tmp <=1; + else + MAC_header_slot_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_header_slot <=0; + else + MAC_header_slot <=MAC_header_slot_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_type_rmon <=0; + else if (Current_state==StateSendPauseFrame) + Tx_pkt_type_rmon <=3'b100; + else if(MAC_header_slot) + Tx_pkt_type_rmon <={1'b0,TxD[7:6]}; + + +always @(Tx_pkt_length_rmon) + if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11) + Src_MAC_ptr =1; + else + Src_MAC_ptr =0; + +//MAC_tx_addr_add +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_tx_addr_rd <=0; + else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame)) + MAC_tx_addr_rd <=1; + else + MAC_tx_addr_rd <=0; + + always @* + //if ((Tx_pkt_length_rmon==3)&&Fifo_rd) + if (Current_state==StatePreamble) + MAC_tx_addr_init=1; + else + MAC_tx_addr_init=0; + +//************************************************************************************************************** +// CFH: this implementation delays the time it sends an entire Ethernet frame with 512 bits for every pause +// request of 512 bits. Actually, it should only delay the time it takes to transmit 512 bits, not counting +// Ethernet header, CRC, Interframe Gap etc. +// Hence the current implementation waits longer than the pause frame actually requests (~20% more) +//************************************************************************************************************** + +//flow control +always @(posedge Clk or posedge Reset) + if (Reset) + pause_counter <=0; + else if (Current_state!=StatePause) + pause_counter <=0; + else + pause_counter <=pause_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_sub <=0; + else if(pause_counter==512/8) + pause_quanta_sub <=1; + else + pause_quanta_sub <=0; + +// FIXME The below probably won't work if the pause request comes when we are in the wrong state + wire clear_xonxoff = (Current_state==StateSendPauseFrame) & (IPLengthCounter==17); +always @ (posedge Clk or posedge Reset) + if (Reset) + xoff_gen_complete <=0; + else if(clear_xonxoff & xoff_gen) + xoff_gen_complete <=1; + else + xoff_gen_complete <=0; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + xon_gen_complete <=0; + else if(clear_xonxoff & xon_gen) + xon_gen_complete <=1; + else + xon_gen_complete <=0; + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v b/usrp2/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v new file mode 100644 index 00000000..fd57008b --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v @@ -0,0 +1,109 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Random_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module Random_gen( +Reset , +Clk , +Init , +RetryCnt , +Random_time_meet +); +input Reset ; +input Clk ; +input Init ; +input [3:0] RetryCnt ; +output Random_time_meet; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [9:0] Random_sequence ; +reg [9:0] Random ; +reg [9:0] Random_counter ; +reg [7:0] Slot_time_counter; //256*2=512bit=1 slot time +reg Random_time_meet; + +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_sequence <=0; + else + Random_sequence <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])}; + +always @ (RetryCnt or Random_sequence) + case (RetryCnt) + 4'h0 : Random={9'b0,Random_sequence[0]}; + 4'h1 : Random={8'b0,Random_sequence[1:0]}; + 4'h2 : Random={7'b0,Random_sequence[2:0]}; + 4'h3 : Random={6'b0,Random_sequence[3:0]}; + 4'h4 : Random={5'b0,Random_sequence[4:0]}; + 4'h5 : Random={4'b0,Random_sequence[5:0]}; + 4'h6 : Random={3'b0,Random_sequence[6:0]}; + 4'h7 : Random={2'b0,Random_sequence[7:0]}; + 4'h8 : Random={1'b0,Random_sequence[8:0]}; + 4'h9 : Random={ Random_sequence[9:0]}; + default : Random={ Random_sequence[9:0]}; + endcase + +always @ (posedge Clk or posedge Reset) + if (Reset) + Slot_time_counter <=0; + else if(Init) + Slot_time_counter <=0; + else if(!Random_time_meet) + Slot_time_counter <=Slot_time_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_counter <=0; + else if (Init) + Random_counter <=Random; + else if (Random_counter!=0&&Slot_time_counter==255) + Random_counter <=Random_counter -1 ; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_time_meet <=1; + else if (Init) + Random_time_meet <=0; + else if (Random_counter==0) + Random_time_meet <=1; + +endmodule + + diff --git a/usrp2/fpga/eth/rtl/verilog/Phy_int.v b/usrp2/fpga/eth/rtl/verilog/Phy_int.v new file mode 100644 index 00000000..c85d4f64 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/Phy_int.v @@ -0,0 +1,205 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Phy_int.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: Phy_int.v,v $ +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:14 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:36 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module Phy_int + (input rst_mac_rx, + input rst_mac_tx, + input MAC_rx_clk, + input MAC_tx_clk, + + // Rx interface + output reg MCrs_dv, + output reg [7:0] MRxD, + output MRxErr, + + // Tx interface + input [7:0] MTxD, + input MTxEn, + output MCRS, + + // PHY interface + output Tx_er, + output reg Tx_en, + output reg [7:0] Txd, + input Rx_er, + input Rx_dv, + input [7:0] Rxd, + input Crs, + input Col, + + // Host interface + input Line_loop_en, + input [2:0] Speed ); + + //------------------------------------------------------------------------- + // Local declarations + //------------------------------------------------------------------------- + + reg [7:0] MTxD_dl1; + reg MTxEn_dl1; + reg Tx_odd_data_ptr; + reg Rx_odd_data_ptr; + reg Rx_er_dl1; + reg Rx_dv_dl1; + reg Rx_dv_dl2; + reg [7:0] Rxd_dl1; + reg [7:0] Rxd_dl2; + reg Crs_dl1; + + //------------------------------------------------------------------------- + // Tx control + //------------------------------------------------------------------------- + + // Reg boundary signals + always @( posedge MAC_tx_clk or posedge rst_mac_tx ) + if ( rst_mac_tx ) + begin + MTxD_dl1 <= 0; + MTxEn_dl1 <= 0; + end + else + begin + MTxD_dl1 <= MTxD; + MTxEn_dl1 <= MTxEn; + end + + always @( posedge MAC_tx_clk or posedge rst_mac_tx ) + if ( rst_mac_tx ) + Tx_odd_data_ptr <= 0; + else if ( !MTxD_dl1 ) + Tx_odd_data_ptr <= 0; + else + Tx_odd_data_ptr <= !Tx_odd_data_ptr; + + + always @( posedge MAC_tx_clk or posedge rst_mac_tx ) + if ( rst_mac_tx ) + Txd <= 0; + else if ( Speed[2] && MTxEn_dl1 ) + Txd <= MTxD_dl1; + else if ( MTxEn_dl1 && !Tx_odd_data_ptr ) + Txd <= { 4'b0, MTxD_dl1[3:0] }; + else if ( MTxEn_dl1 && Tx_odd_data_ptr ) + Txd <= { 4'b0, MTxD_dl1[7:4] }; + else + Txd <=0; + + always @( posedge MAC_tx_clk or posedge rst_mac_tx ) + if ( rst_mac_tx ) + Tx_en <= 0; + else if ( MTxEn_dl1 ) + Tx_en <= 1; + else + Tx_en <= 0; + + assign Tx_er = 0; + + //------------------------------------------------------------------------- + // Rx control + //------------------------------------------------------------------------- + + // Reg boundery signals + always @( posedge MAC_rx_clk or posedge rst_mac_rx ) + if ( rst_mac_rx ) + begin + Rx_er_dl1 <= 0; + Rx_dv_dl1 <= 0; + Rx_dv_dl2 <= 0; + Rxd_dl1 <= 0; + Rxd_dl2 <= 0; + Crs_dl1 <= 0; + end + else + begin + Rx_er_dl1 <= Rx_er; + Rx_dv_dl1 <= Rx_dv; + Rx_dv_dl2 <= Rx_dv_dl1; + Rxd_dl1 <= Rxd; + Rxd_dl2 <= Rxd_dl1; + Crs_dl1 <= Crs; + end + + assign MRxErr = Rx_er_dl1; + assign MCRS = Crs_dl1; + + always @( posedge MAC_rx_clk or posedge rst_mac_rx ) + if ( rst_mac_rx ) + MCrs_dv <= 0; + else if ( Line_loop_en ) + MCrs_dv <= Tx_en; + else if( Rx_dv_dl2 ) + MCrs_dv <= 1; + else + MCrs_dv <= 0; + + always @ ( posedge MAC_rx_clk or posedge rst_mac_rx ) + if ( rst_mac_rx ) + Rx_odd_data_ptr <= 0; + else if ( !Rx_dv_dl1 ) + Rx_odd_data_ptr <= 0; + else + Rx_odd_data_ptr <= !Rx_odd_data_ptr; + + always @ ( posedge MAC_rx_clk or posedge rst_mac_rx ) + if ( rst_mac_rx ) + MRxD <= 0; + else if( Line_loop_en ) + MRxD <= Txd; + else if( Speed[2] && Rx_dv_dl2 ) + MRxD <= Rxd_dl2; + else if( Rx_dv_dl1 && Rx_odd_data_ptr ) + MRxD <={ Rxd_dl1[3:0], Rxd_dl2[3:0] }; + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/RMON.v b/usrp2/fpga/eth/rtl/verilog/RMON.v new file mode 100644 index 00000000..18a84beb --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/RMON.v @@ -0,0 +1,163 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: RMON.v,v $ +// Revision 1.4 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module RMON + (input Clk , + input Reset , + //Tx_RMON + input [2:0] Tx_pkt_type_rmon , + input [15:0] Tx_pkt_length_rmon , + input Tx_apply_rmon , + input [2:0] Tx_pkt_err_type_rmon, + //Tx_RMON + input [2:0] Rx_pkt_type_rmon , + input [15:0] Rx_pkt_length_rmon , + input Rx_apply_rmon , + input [2:0] Rx_pkt_err_type_rmon, + //CPU + input [5:0] CPU_rd_addr , + input CPU_rd_apply , + output CPU_rd_grant , + output [31:0] CPU_rd_dout + ); + + // ****************************************************************************** + // interface signals + // ****************************************************************************** + wire Reg_apply_0 ; + wire [4:0] Reg_addr_0 ; + wire [15:0] Reg_data_0 ; + wire Reg_next_0 ; + wire Reg_apply_1 ; + wire [4:0] Reg_addr_1 ; + wire [15:0] Reg_data_1 ; + wire Reg_next_1 ; + wire [5:0] Addra ; + wire [31:0] Dina ; + reg [31:0] Douta ; + wire Wea ; + + // ****************************************************************************** + + RMON_addr_gen U_0_Rx_RMON_addr_gen + (.Clk (Clk ), + .Reset (Reset ), + //RMON + .Pkt_type_rmon (Rx_pkt_type_rmon ), + .Pkt_length_rmon (Rx_pkt_length_rmon ), + .Apply_rmon (Rx_apply_rmon ), + .Pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //Rmon_ctrl + .Reg_apply (Reg_apply_0 ), + .Reg_addr (Reg_addr_0 ), + .Reg_data (Reg_data_0 ), + .Reg_next (Reg_next_0 ), + //CPU + .Reg_drop_apply ( ) ); + + RMON_addr_gen U_0_Tx_RMON_addr_gen + (.Clk (Clk ), + .Reset (Reset ), + //RMON + .Pkt_type_rmon (Tx_pkt_type_rmon ), + .Pkt_length_rmon (Tx_pkt_length_rmon ), + .Apply_rmon (Tx_apply_rmon ), + .Pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //Rmon_ctrl + .Reg_apply (Reg_apply_1 ), + .Reg_addr (Reg_addr_1 ), + .Reg_data (Reg_data_1 ), + .Reg_next (Reg_next_1 ), + //CPU + .Reg_drop_apply ( ) ); + + RMON_ctrl U_RMON_ctrl + (.Clk (Clk ), + .Reset (Reset ), + //RMON_ctrl + .Reg_apply_0 (Reg_apply_0 ), + .Reg_addr_0 (Reg_addr_0 ), + .Reg_data_0 (Reg_data_0 ), + .Reg_next_0 (Reg_next_0 ), + .Reg_apply_1 (Reg_apply_1 ), + .Reg_addr_1 (Reg_addr_1 ), + .Reg_data_1 (Reg_data_1 ), + .Reg_next_1 (Reg_next_1 ), + //dual-port ram + .Addra (Addra ), + .Dina (Dina ), + .Douta (Douta ), + .Wea (Wea ), + //CPU + .CPU_rd_addr (CPU_rd_addr ), + .CPU_rd_apply (CPU_rd_apply ), + .CPU_rd_grant (CPU_rd_grant ), + .CPU_rd_dout (CPU_rd_dout ) ); + + reg [31:0] RMON_ram [0:63]; + wire [31:0] Douta_imm = RMON_ram[Addra]; + integer i; + initial + for(i=0;i<64;i=i+1) + RMON_ram[i] = 32'd0; + + always @(posedge Clk) + if(Wea) + RMON_ram[Addra] <= Dina; + + always @(posedge Clk) + Douta <= Douta_imm; + +endmodule // RMON diff --git a/usrp2/fpga/eth/rtl/verilog/RMON/RMON_addr_gen.v b/usrp2/fpga/eth/rtl/verilog/RMON/RMON_addr_gen.v new file mode 100644 index 00000000..9da8d1f8 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/RMON/RMON_addr_gen.v @@ -0,0 +1,295 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON_addr_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: RMON_addr_gen.v,v $ +// Revision 1.4 2006/06/25 04:58:57 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:55 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +module RMON_addr_gen( +Clk , +Reset , +//RMON +Pkt_type_rmon , +Pkt_length_rmon , +Apply_rmon ,//pluse signal looks like eop +Pkt_err_type_rmon , +// +Reg_apply , +Reg_addr , +Reg_data , +Reg_next , +//CPU +Reg_drop_apply +); +input Clk ; +input Reset ; + //RMON +input [2:0] Pkt_type_rmon ; +input [15:0] Pkt_length_rmon ; +input Apply_rmon ;//pluse signal looks like eop +input [2:0] Pkt_err_type_rmon ; + //RMON_ctrl +output Reg_apply ; +output [4:0] Reg_addr ; +output [15:0] Reg_data ; +input Reg_next ; + //CPU +output Reg_drop_apply ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter StateIdle =4'd0; +parameter StatePktLength =4'd1; +parameter StatePktNumber =4'd2; +parameter StatePktType =4'd3; +parameter StatePktRange =4'd4; + +reg [3:0] CurrentState /* synthesys syn_keep=1 */; +reg [3:0] NextState; + +reg [2:0] PktTypeReg ; +reg [15:0] PktLengthReg ; +reg [2:0] PktErrTypeReg ; + +reg Reg_apply ; +reg [4:0] Reg_addr ; +reg [15:0] Reg_data ; +reg Reg_drop_apply ; +//****************************************************************************** +//register boundery signals + +//****************************************************************************** +reg Apply_rmon_dl1; +reg Apply_rmon_dl2; +reg Apply_rmon_pulse; +reg [2:0] Pkt_type_rmon_dl1 ; +reg [15:0] Pkt_length_rmon_dl1 ; +reg [2:0] Pkt_err_type_rmon_dl1 ; + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + Pkt_type_rmon_dl1 <=0; + Pkt_length_rmon_dl1 <=0; + Pkt_err_type_rmon_dl1 <=0; + end + else + begin + Pkt_type_rmon_dl1 <=Pkt_type_rmon ; + Pkt_length_rmon_dl1 <=Pkt_length_rmon ; + Pkt_err_type_rmon_dl1 <=Pkt_err_type_rmon ; + end + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + Apply_rmon_dl1 <=0; + Apply_rmon_dl2 <=0; + end + else + begin + Apply_rmon_dl1 <=Apply_rmon; + Apply_rmon_dl2 <=Apply_rmon_dl1; + end + +always @(Apply_rmon_dl1 or Apply_rmon_dl2) + if (Apply_rmon_dl1&!Apply_rmon_dl2) + Apply_rmon_pulse =1; + else + Apply_rmon_pulse =0; + + + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + PktTypeReg <=0; + PktLengthReg <=0; + PktErrTypeReg <=0; + end + else if (Apply_rmon_pulse&&CurrentState==StateIdle) + begin + PktTypeReg <=Pkt_type_rmon_dl1 ; + PktLengthReg <=Pkt_length_rmon_dl1 ; + PktErrTypeReg <=Pkt_err_type_rmon_dl1 ; + end + + +//****************************************************************************** +//State Machine +//****************************************************************************** +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState <=StateIdle; + else + CurrentState <=NextState; + +always @(CurrentState or Apply_rmon_pulse or Reg_next) + case (CurrentState) + StateIdle: + if (Apply_rmon_pulse) + NextState =StatePktLength; + else + NextState =StateIdle; + StatePktLength: + if (Reg_next) + NextState =StatePktNumber; + else + NextState =CurrentState; + StatePktNumber: + if (Reg_next) + NextState =StatePktType; + else + NextState =CurrentState; + StatePktType: + if (Reg_next) + NextState =StatePktRange; + else + NextState =CurrentState; + StatePktRange: + if (Reg_next) + NextState =StateIdle; + else + NextState =CurrentState; + default: + NextState =StateIdle; + endcase + +//****************************************************************************** +//gen output signals +//****************************************************************************** +//Reg_apply +always @ (CurrentState) + if (CurrentState==StatePktLength||CurrentState==StatePktNumber|| + CurrentState==StatePktType||CurrentState==StatePktRange) + Reg_apply =1; + else + Reg_apply =0; + +//Reg_addr +always @ (posedge Clk or posedge Reset) + if (Reset) + Reg_addr <=0; + else case (CurrentState) + StatePktLength: + Reg_addr <=5'd00; + StatePktNumber: + Reg_addr <=5'd01; + StatePktType: + case(PktTypeReg) + 3'b011: + Reg_addr <=5'd02; //broadcast + 3'b001: + Reg_addr <=5'd03; //multicast + 3'b100: + Reg_addr <=5'd16; //pause frame + default: + Reg_addr <=5'd04; //unicast + endcase + StatePktRange: + case(PktErrTypeReg) + 3'b001: + Reg_addr <=5'd05; + 3'b010: + Reg_addr <=5'd06; + 3'b011: + Reg_addr <=5'd07; + 3'b100: + if (PktLengthReg<64) + Reg_addr <=5'd08; + else if (PktLengthReg==64) + Reg_addr <=5'd09; + else if (PktLengthReg<128) + Reg_addr <=5'd10; + else if (PktLengthReg<256) + Reg_addr <=5'd11; + else if (PktLengthReg<512) + Reg_addr <=5'd12; + else if (PktLengthReg<1024) + Reg_addr <=5'd13; + else if (PktLengthReg<1519) + Reg_addr <=5'd14; + else + Reg_addr <=5'd15; + default: + Reg_addr <=5'd05; + endcase + default: + Reg_addr <=5'd05; + endcase + +//Reg_data +always @ (CurrentState or PktLengthReg) + case (CurrentState) + StatePktLength: + Reg_data =PktLengthReg; + StatePktNumber: + Reg_data =1; + StatePktType: + Reg_data =1; + StatePktRange: + Reg_data =1; + default: + Reg_data =0; + endcase + +//Reg_drop_apply +always @ (posedge Clk or posedge Reset) + if (Reset) + Reg_drop_apply <=0; + else if (CurrentState!=StateIdle&&Apply_rmon_pulse) + Reg_drop_apply <=1; + else + Reg_drop_apply <=0; + + +endmodule + diff --git a/usrp2/fpga/eth/rtl/verilog/RMON/RMON_ctrl.v b/usrp2/fpga/eth/rtl/verilog/RMON/RMON_ctrl.v new file mode 100644 index 00000000..4fc038dc --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/RMON/RMON_ctrl.v @@ -0,0 +1,283 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: RMON_ctrl.v,v $ +// Revision 1.4 2006/06/25 04:58:57 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:55 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +module RMON_ctrl ( +Clk , +Reset , +//RMON_ctrl +Reg_apply_0 , +Reg_addr_0 , +Reg_data_0 , +Reg_next_0 , +Reg_apply_1 , +Reg_addr_1 , +Reg_data_1 , +Reg_next_1 , +//dual-port ram +Addra , +Dina , +Douta , +Wea , +//CPU +CPU_rd_addr , +CPU_rd_apply , +CPU_rd_grant , +CPU_rd_dout + +); +input Clk ; +input Reset ; + //RMON_ctrl +input Reg_apply_0 ; +input [4:0] Reg_addr_0 ; +input [15:0] Reg_data_0 ; +output Reg_next_0 ; +input Reg_apply_1 ; +input [4:0] Reg_addr_1 ; +input [15:0] Reg_data_1 ; +output Reg_next_1 ; + //dual-port ram + //port-a for Rmon +output [5:0] Addra ; +output [31:0] Dina ; +input [31:0] Douta ; +output Wea ; + //CPU +input [5:0] CPU_rd_addr ; +input CPU_rd_apply ; +output CPU_rd_grant ; +output [31:0] CPU_rd_dout ; + + + + +//****************************************************************************** +//internal signals +//****************************************************************************** + +parameter StateCPU =4'd00; +parameter StateMAC0 =4'd01; +parameter StateMAC1 =4'd02; + + +reg [3:0] CurrentState /* synthesys syn_keep=1 */; +reg [3:0] NextState; +reg [3:0] CurrentState_reg; + +reg [4:0] StepCounter; +reg [5:0] Addra ; +reg [31:0] Dina; +reg Reg_next_0 ; +reg Reg_next_1 ; +reg Write; +reg Read; +reg Pipeline; +reg [31:0] CPU_rd_dout ; +reg CPU_rd_apply_reg ; +//****************************************************************************** +//State Machine +//****************************************************************************** + +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState <=StateMAC0; + else + CurrentState <=NextState; + +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState_reg <=StateMAC0; + else if(CurrentState!=StateCPU) + CurrentState_reg <=CurrentState; + +always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg + or Reg_apply_1 + or StepCounter + ) + case(CurrentState) + StateMAC0: + if(!Reg_apply_0&&CPU_rd_apply_reg) + NextState =StateCPU; + else if(!Reg_apply_0) + NextState =StateMAC1; + else + NextState =CurrentState; + StateMAC1: + if(!Reg_apply_1&&CPU_rd_apply_reg) + NextState =StateCPU; + else if(!Reg_apply_1) + NextState =StateMAC0; + else + NextState =CurrentState; + StateCPU: + if (StepCounter==3) + case (CurrentState_reg) + StateMAC0 :NextState =StateMAC0 ; + StateMAC1 :NextState =StateMAC1 ; + default :NextState =StateMAC0; + endcase + else + NextState =CurrentState; + + default: + NextState =StateMAC0; + endcase + + + +always @(posedge Clk or posedge Reset) + if (Reset) + StepCounter <=0; + else if(NextState!=CurrentState) + StepCounter <=0; + else if (StepCounter!=4'hf) + StepCounter <=StepCounter + 1; + +//****************************************************************************** +//temp signals +//****************************************************************************** +always @(StepCounter) + if( StepCounter==1||StepCounter==4|| + StepCounter==7||StepCounter==10) + Read =1; + else + Read =0; + +always @(StepCounter or CurrentState) + if( StepCounter==2||StepCounter==5|| + StepCounter==8||StepCounter==11) + Pipeline =1; + else + Pipeline =0; + +always @(StepCounter or CurrentState) + if( StepCounter==3||StepCounter==6|| + StepCounter==9||StepCounter==12) + Write =1; + else + Write =0; + + +//****************************************************************************** +//gen output signals +//****************************************************************************** +//Addra +always @(*) + case(CurrentState) + StateMAC0 : Addra={1'd0 ,Reg_addr_0 }; + StateMAC1 : Addra={1'd1 ,Reg_addr_1 }; + StateCPU: Addra=CPU_rd_addr; + default: Addra=0; + endcase + +//Dina +always @(posedge Clk or posedge Reset) + if (Reset) + Dina <=0; + else + case(CurrentState) + StateMAC0 : Dina<=Douta+Reg_data_0 ; + StateMAC1 : Dina<=Douta+Reg_data_1 ; + StateCPU: Dina<=0; + default: Dina<=0; + endcase + +assign Wea =Write; +//Reg_next +always @(CurrentState or Pipeline) + if(CurrentState==StateMAC0) + Reg_next_0 =Pipeline; + else + Reg_next_0 =0; + +always @(CurrentState or Pipeline) + if(CurrentState==StateMAC1) + Reg_next_1 =Pipeline; + else + Reg_next_1 =0; + + +//CPU_rd_grant +reg CPU_rd_apply_dl1; +reg CPU_rd_apply_dl2; +//rising edge +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + CPU_rd_apply_dl1 <=0; + CPU_rd_apply_dl2 <=0; + end + else + begin + CPU_rd_apply_dl1 <=CPU_rd_apply; + CPU_rd_apply_dl2 <=CPU_rd_apply_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + CPU_rd_apply_reg <=0; + else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2) + CPU_rd_apply_reg <=1; + else if (CurrentState==StateCPU&&Write) + CPU_rd_apply_reg <=0; + +assign CPU_rd_grant = CPU_rd_apply & CPU_rd_apply_dl1 & CPU_rd_apply_dl2 & !CPU_rd_apply_reg; + +always @ (posedge Clk or posedge Reset) + if (Reset) + CPU_rd_dout <=0; + else if (Pipeline&&CurrentState==StateCPU) + CPU_rd_dout <=Douta; + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/Reg_int.v b/usrp2/fpga/eth/rtl/verilog/Reg_int.v new file mode 100644 index 00000000..f1bea231 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/Reg_int.v @@ -0,0 +1,270 @@ +module Reg_int ( + // Wishbone compliant core host interface + input CLK_I, // Wishbone interface clock (nominally 50 MHz) + input RST_I, // Active high (async) reset of the Wishbone interface + input STB_I, // Active high module-select + input CYC_I, // Active high cycle-enable + input [6:0] ADR_I, // Module register address + input WE_I, // Active high for writes, low for reads + input [31:0] DAT_I, // Write data + output reg [31:0] DAT_O, // Read data + output reg ACK_O, // Acknowledge output – single high pulse + + // Tx host interface + output [4:0] Tx_Hwmark, + output [4:0] Tx_Lwmark, + output MAC_tx_add_en, + output FullDuplex, + output [3:0] MaxRetry, + output [5:0] IFGset, + output [7:0] MAC_tx_add_prom_data, + output [2:0] MAC_tx_add_prom_add, + output MAC_tx_add_prom_wr, + + // Rx host interface + output MAC_rx_add_chk_en, + output [7:0] MAC_rx_add_prom_data, + output [2:0] MAC_rx_add_prom_add, + output MAC_rx_add_prom_wr, + output broadcast_filter_en, + output [15:0] broadcast_bucket_depth, + output [15:0] broadcast_bucket_interval, + output RX_APPEND_CRC, + output [4:0] Rx_Hwmark, + output [4:0] Rx_Lwmark, + output CRC_chk_en, + output [5:0] RX_IFG_SET, + output [15:0] RX_MAX_LENGTH, // Default 1518 + output [6:0] RX_MIN_LENGTH, // Default 64 + + // Flow control settings + output pause_frame_send_en, + output [15:0] pause_quanta_set, + output tx_pause_en, + output [15:0] fc_hwmark, + output [15:0] fc_lwmark, + + // RMON host interface + output [5:0] CPU_rd_addr, + output CPU_rd_apply, + input CPU_rd_grant, + input [31:0] CPU_rd_dout, + + //Phy int host interface + output Line_loop_en, + output [2:0] Speed, + + //MII to CPU + output [7:0] Divider, // Divider for the host clock + output [15:0] CtrlData, // Control Data (to be written to the PHY reg.) + output [4:0] Rgad, // Register Address (within the PHY) + output [4:0] Fiad, // PHY Address + output NoPre, // No Preamble (no 32-bit preamble) + output WCtrlData, // Write Control Data operation + output RStat, // Read Status operation + output ScanStat, // Scan Status operation + input Busy, // Busy Signal + input LinkFail, // Link Integrity Signal + input Nvalid, // Invalid Status (qualifier for the valid scan result) + input [15:0] Prsd, // Read Status Data (data read from the PHY) + input WCtrlDataStart, // This signals resets the WCTRLDATA bit in the MIIM Command register + input RStatStart, // This signal resets the RSTAT BIT in the MIIM Command register + input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data +); + + // New registers for controlling the MII interface + wire [8:0] MIIMODER; + reg [2:0] MIICOMMAND; + wire [12:0] MIIADDRESS; + wire [15:0] MIITX_DATA; + reg [15:0] MIIRX_DATA; + wire [2:0] MIISTATUS; + + // New registers for controlling the MII interface + + // MIIMODER + assign NoPre = MIIMODER[8]; + assign Divider = MIIMODER[7:0]; + // MIICOMMAND + assign WCtrlData = MIICOMMAND[2]; + assign RStat = MIICOMMAND[1]; + assign ScanStat = MIICOMMAND[0]; + // MIIADDRESS + assign Rgad = MIIADDRESS[12:8]; + assign Fiad = MIIADDRESS[4:0]; + // MIITX_DATA + assign CtrlData = MIITX_DATA[15:0]; + // MIISTATUS + assign MIISTATUS[2:0] = { 13'b0, Nvalid, Busy, LinkFail }; + + wire Wr; + + RegCPUData #( 5 ) U_0_000( Tx_Hwmark , 7'd000, 5'h09, RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] ); + RegCPUData #( 5 ) U_0_001( Tx_Lwmark , 7'd001, 5'h08, RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] ); + RegCPUData #( 1 ) U_0_002( pause_frame_send_en , 7'd002, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 16 ) U_0_003( pause_quanta_set , 7'd003, 16'h01af, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] ); + RegCPUData #( 6 ) U_0_004( IFGset , 7'd004, 6'h0c, RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] ); + RegCPUData #( 1 ) U_0_005( FullDuplex , 7'd005, 1'h1, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 4 ) U_0_006( MaxRetry , 7'd006, 4'h2, RST_I, CLK_I, Wr, ADR_I, DAT_I[3:0] ); + RegCPUData #( 1 ) U_0_007( MAC_tx_add_en , 7'd007, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 8 ) U_0_008( MAC_tx_add_prom_data , 7'd008, 8'h00, RST_I, CLK_I, Wr, ADR_I, DAT_I[7:0] ); + RegCPUData #( 3 ) U_0_009( MAC_tx_add_prom_add , 7'd009, 3'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] ); + RegCPUData #( 1 ) U_0_010( MAC_tx_add_prom_wr , 7'd010, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 1 ) U_0_011( tx_pause_en , 7'd011, 1'h1, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 16 ) U_0_012( fc_hwmark , 7'd012, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] ); + RegCPUData #( 16 ) U_0_013( fc_lwmark , 7'd013, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] ); + RegCPUData #( 1 ) U_0_014( MAC_rx_add_chk_en , 7'd014, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 8 ) U_0_015( MAC_rx_add_prom_data , 7'd015, 8'h00, RST_I, CLK_I, Wr, ADR_I, DAT_I[7:0] ); + RegCPUData #( 3 ) U_0_016( MAC_rx_add_prom_add , 7'd016, 3'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] ); + RegCPUData #( 1 ) U_0_017( MAC_rx_add_prom_wr , 7'd017, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 1 ) U_0_018( broadcast_filter_en , 7'd018, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 16 ) U_0_019( broadcast_bucket_depth , 7'd019, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] ); + RegCPUData #( 16 ) U_0_020( broadcast_bucket_interval , 7'd020, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] ); + RegCPUData #( 1 ) U_0_021( RX_APPEND_CRC , 7'd021, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 5 ) U_0_022( Rx_Hwmark , 7'd022, 5'h1a, RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] ); + RegCPUData #( 5 ) U_0_023( Rx_Lwmark , 7'd023, 5'h10, RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] ); + RegCPUData #( 1 ) U_0_024( CRC_chk_en , 7'd024, 1'h1, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 6 ) U_0_025( RX_IFG_SET , 7'd025, 6'h0c, RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] ); + RegCPUData #( 16 ) U_0_026( RX_MAX_LENGTH , 7'd026, 16'h2710, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] ); + RegCPUData #( 7 ) U_0_027( RX_MIN_LENGTH , 7'd027, 7'h40, RST_I, CLK_I, Wr, ADR_I, DAT_I[6:0] ); + RegCPUData #( 6 ) U_0_028( CPU_rd_addr , 7'd028, 6'h00, RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] ); + RegCPUData #( 1 ) U_0_029( CPU_rd_apply , 7'd029, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); +//RegCPUData #( 1 ) U_0_030( CPU_rd_grant , 7'd030, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); +//RegCPUData #( 16 ) U_0_031( CPU_rd_dout_l , 7'd031, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] ); +//RegCPUData #( 16 ) U_0_032( CPU_rd_dout_h , 7'd032, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] ); + RegCPUData #( 1 ) U_0_033( Line_loop_en , 7'd033, 1'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] ); + RegCPUData #( 3 ) U_0_034( Speed , 7'd034, 3'h0, RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] ); + + // New registers for controlling the MDIO interface + RegCPUData #( 9 ) U_0_035( MIIMODER , 7'd035, 9'h064, RST_I, CLK_I, Wr, ADR_I, DAT_I[8:0] ); + // Reg #36 is MIICOMMAND - implemented separately below + RegCPUData #( 13 ) U_0_037( MIIADDRESS , 7'd037, 13'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[12:0] ); + RegCPUData #( 16 ) U_0_038( MIITX_DATA , 7'd038, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] ); + + // Asserted in first clock of 2-cycle access, negated otherwise + wire Access = ~ACK_O & STB_I & CYC_I; + + // Asserted in first clock of 2-cycle write access, negated otherwise + assign Wr = Access & WE_I; + + // MIICOMMAND register - needs special treatment because of auto-resetting bits + always @ ( posedge RST_I or posedge CLK_I ) + if ( RST_I ) + MIICOMMAND <= 0; + else + begin + if ( Wr & ( ADR_I == 7'd036 ) ) + // Write access + MIICOMMAND <= DAT_I; + else + begin + if ( WCtrlDataStart ) + MIICOMMAND[2] <= 0; + if ( RStatStart ) + MIICOMMAND[1] <= 0; + end + end + + // MIIRX_DATA register + always @ ( posedge RST_I or posedge CLK_I ) + if ( RST_I ) + MIIRX_DATA <= 0; + else + if ( UpdateMIIRX_DATAReg ) + MIIRX_DATA <= Prsd; + + // ACK_O is asserted in second clock of 2-cycle access, negated otherwise + always @ ( posedge RST_I or posedge CLK_I ) + if ( RST_I ) + ACK_O <= 0; + else + ACK_O <= Access; + + always @ ( posedge RST_I or posedge CLK_I ) + if(RST_I) + DAT_O <= 0; + else + begin + DAT_O <=0; + if ( Access & ~WE_I ) + casez ( ADR_I ) + 7'd00: DAT_O <= Tx_Hwmark; + 7'd01: DAT_O <= Tx_Lwmark; + 7'd02: DAT_O <= pause_frame_send_en; + 7'd03: DAT_O <= pause_quanta_set; + 7'd04: DAT_O <= IFGset; + 7'd05: DAT_O <= FullDuplex; + 7'd06: DAT_O <= MaxRetry; + 7'd07: DAT_O <= MAC_tx_add_en; + 7'd08: DAT_O <= MAC_tx_add_prom_data; + 7'd09: DAT_O <= MAC_tx_add_prom_add; + 7'd10: DAT_O <= MAC_tx_add_prom_wr; + 7'd11: DAT_O <= tx_pause_en; + 7'd12: DAT_O <= fc_hwmark; + 7'd13: DAT_O <= fc_lwmark; + 7'd14: DAT_O <= MAC_rx_add_chk_en; + 7'd15: DAT_O <= MAC_rx_add_prom_data; + 7'd16: DAT_O <= MAC_rx_add_prom_add; + 7'd17: DAT_O <= MAC_rx_add_prom_wr; + 7'd18: DAT_O <= broadcast_filter_en; + 7'd19: DAT_O <= broadcast_bucket_depth; + 7'd20: DAT_O <= broadcast_bucket_interval; + 7'd21: DAT_O <= RX_APPEND_CRC; + 7'd22: DAT_O <= Rx_Hwmark; + 7'd23: DAT_O <= Rx_Lwmark; + 7'd24: DAT_O <= CRC_chk_en; + 7'd25: DAT_O <= RX_IFG_SET; + 7'd26: DAT_O <= RX_MAX_LENGTH; + 7'd27: DAT_O <= RX_MIN_LENGTH; + 7'd28: DAT_O <= CPU_rd_addr; + 7'd29: DAT_O <= CPU_rd_apply; + 7'd30: DAT_O <= CPU_rd_grant; + 7'd31: DAT_O <= CPU_rd_dout; + //7'd32: DAT_O <= CPU_rd_dout[31:16]; + 7'd33: DAT_O <= Line_loop_en; + 7'd34: DAT_O <= Speed; + + // New registers for controlling MII interface + 7'd35: DAT_O <= MIIMODER; + 7'd36: DAT_O <= MIICOMMAND; + 7'd37: DAT_O <= MIIADDRESS; + 7'd38: DAT_O <= MIITX_DATA; + 7'd39: DAT_O <= MIIRX_DATA; + 7'd40: DAT_O <= MIISTATUS; + endcase + end + +endmodule + +module RegCPUData( + RegOut, + RegAddr, + RegInit, + + Reset, + Clk, + Wr, + Addr, + WrData +); + + parameter WIDTH = 16; + + output reg [WIDTH-1:0] RegOut; + input [6:0] RegAddr; + input [WIDTH-1:0] RegInit; + + input Reset; + input Clk; + input Wr; + input [6:0] Addr; + input [WIDTH-1:0] WrData; + + always @( posedge Reset or posedge Clk ) + if ( Reset ) + RegOut <= RegInit; + else + if ( Wr && ( Addr == RegAddr ) ) + RegOut <= WrData; + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v b/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v new file mode 100644 index 00000000..994907d4 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v @@ -0,0 +1,71 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_clk_div2.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: CLK_DIV2.v,v $ +// Revision 1.3 2006/01/19 14:07:56 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// + +module eth_clk_div2 ( + input Reset, + input IN, + output reg OUT +); + +always @ (posedge IN or posedge Reset) + if (Reset) + OUT <= 0; + else + OUT <= ~OUT; + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_switch.v b/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_switch.v new file mode 100644 index 00000000..c5375743 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_switch.v @@ -0,0 +1,81 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_clk_switch.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: CLK_SWITCH.v,v $ +// Revision 1.3 2006/01/19 14:07:56 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +`include "header.vh" + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// +module eth_clk_switch ( + input IN_0, + input IN_1, + input SW, + output OUT +); + +`ifdef MAC_TARGET_XILINX + + BUFGMUX U_BUFGMUX ( + .O ( OUT ), + .I0( IN_0 ), + .I1( IN_1 ), + .S ( SW ) + ); + +`else + + assign OUT = SW ? IN_1 : IN_0; + +`endif + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/TECH/xilinx/BUFGMUX.v b/usrp2/fpga/eth/rtl/verilog/TECH/xilinx/BUFGMUX.v new file mode 100644 index 00000000..f5bb4a74 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/TECH/xilinx/BUFGMUX.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGMUX.v,v 1.9.34.2 2005/10/21 20:45:30 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 7.1i (H.19) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Mux Buffer with Output State 0 +// /___/ /\ Filename : BUFGMUX.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 100 ps / 10 ps + +module BUFGMUX (O, I0, I1, S); + + output O; + + input I0, I1, S; + + reg q0, q1; + reg q0_enable, q1_enable; + + tri0 GSR = glbl.GSR; + + bufif1 B0 (O, I0, q0); + bufif1 B1 (O, I1, q1); + pulldown P1 (O); + + always @(GSR or I0 or S or q0_enable) + if (GSR) + q0 <= 1; + else if (!I0) + q0 <= !S && q0_enable; + + always @(GSR or I1 or S or q1_enable) + if (GSR) + q1 <= 0; + else if (!I1) + q1 <= S && q1_enable; + + always @(GSR or q1 or I0) + if (GSR) + q0_enable <= 1; + else if (q1) + q0_enable <= 0; + else if (I0) + q0_enable <= !q1; + + always @(GSR or q0 or I1) + if (GSR) + q1_enable <= 0; + else if (q0) + q1_enable <= 0; + else if (I1) + q1_enable <= !q0; + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v b/usrp2/fpga/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v new file mode 100644 index 00000000..80545a9b --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v @@ -0,0 +1,2204 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.9 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S36_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DOA; + output [3:0] DOPA; + reg [31:0] doa_out; + reg [3:0] dopa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15, doa_out16, doa_out17, doa_out18, doa_out19, doa_out20, doa_out21, doa_out22, doa_out23, doa_out24, doa_out25, doa_out26, doa_out27, doa_out28, doa_out29, doa_out30, doa_out31; + wire dopa0_out, dopa1_out, dopa2_out, dopa3_out; + + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA, CLKA, WEA, SSRA; + + output [31:0] DOB; + output [3:0] DOPB; + reg [31:0] dob_out; + reg [3:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; + wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; + + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [31:0] dia_int; + wire [3:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[31:0]; + assign dopa_out = INIT_A[35:32]; + assign dob_out = INIT_B[31:0]; + assign dopb_out = INIT_B[35:32]; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_doa_out8 (doa_out8, doa_out[8]); + buf b_doa_out9 (doa_out9, doa_out[9]); + buf b_doa_out10 (doa_out10, doa_out[10]); + buf b_doa_out11 (doa_out11, doa_out[11]); + buf b_doa_out12 (doa_out12, doa_out[12]); + buf b_doa_out13 (doa_out13, doa_out[13]); + buf b_doa_out14 (doa_out14, doa_out[14]); + buf b_doa_out15 (doa_out15, doa_out[15]); + buf b_doa_out16 (doa_out16, doa_out[16]); + buf b_doa_out17 (doa_out17, doa_out[17]); + buf b_doa_out18 (doa_out18, doa_out[18]); + buf b_doa_out19 (doa_out19, doa_out[19]); + buf b_doa_out20 (doa_out20, doa_out[20]); + buf b_doa_out21 (doa_out21, doa_out[21]); + buf b_doa_out22 (doa_out22, doa_out[22]); + buf b_doa_out23 (doa_out23, doa_out[23]); + buf b_doa_out24 (doa_out24, doa_out[24]); + buf b_doa_out25 (doa_out25, doa_out[25]); + buf b_doa_out26 (doa_out26, doa_out[26]); + buf b_doa_out27 (doa_out27, doa_out[27]); + buf b_doa_out28 (doa_out28, doa_out[28]); + buf b_doa_out29 (doa_out29, doa_out[29]); + buf b_doa_out30 (doa_out30, doa_out[30]); + buf b_doa_out31 (doa_out31, doa_out[31]); + buf b_dopa_out0 (dopa_out0, dopa_out[0]); + buf b_dopa_out1 (dopa_out1, dopa_out[1]); + buf b_dopa_out2 (dopa_out2, dopa_out[2]); + buf b_dopa_out3 (dopa_out3, dopa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dob_out16 (dob_out16, dob_out[16]); + buf b_dob_out17 (dob_out17, dob_out[17]); + buf b_dob_out18 (dob_out18, dob_out[18]); + buf b_dob_out19 (dob_out19, dob_out[19]); + buf b_dob_out20 (dob_out20, dob_out[20]); + buf b_dob_out21 (dob_out21, dob_out[21]); + buf b_dob_out22 (dob_out22, dob_out[22]); + buf b_dob_out23 (dob_out23, dob_out[23]); + buf b_dob_out24 (dob_out24, dob_out[24]); + buf b_dob_out25 (dob_out25, dob_out[25]); + buf b_dob_out26 (dob_out26, dob_out[26]); + buf b_dob_out27 (dob_out27, dob_out[27]); + buf b_dob_out28 (dob_out28, dob_out[28]); + buf b_dob_out29 (dob_out29, dob_out[29]); + buf b_dob_out30 (dob_out30, dob_out[30]); + buf b_dob_out31 (dob_out31, dob_out[31]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + buf b_dopb_out2 (dopb_out2, dopb_out[2]); + buf b_dopb_out3 (dopb_out3, dopb_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_doa8 (DOA[8], doa_out8); + buf b_doa9 (DOA[9], doa_out9); + buf b_doa10 (DOA[10], doa_out10); + buf b_doa11 (DOA[11], doa_out11); + buf b_doa12 (DOA[12], doa_out12); + buf b_doa13 (DOA[13], doa_out13); + buf b_doa14 (DOA[14], doa_out14); + buf b_doa15 (DOA[15], doa_out15); + buf b_doa16 (DOA[16], doa_out16); + buf b_doa17 (DOA[17], doa_out17); + buf b_doa18 (DOA[18], doa_out18); + buf b_doa19 (DOA[19], doa_out19); + buf b_doa20 (DOA[20], doa_out20); + buf b_doa21 (DOA[21], doa_out21); + buf b_doa22 (DOA[22], doa_out22); + buf b_doa23 (DOA[23], doa_out23); + buf b_doa24 (DOA[24], doa_out24); + buf b_doa25 (DOA[25], doa_out25); + buf b_doa26 (DOA[26], doa_out26); + buf b_doa27 (DOA[27], doa_out27); + buf b_doa28 (DOA[28], doa_out28); + buf b_doa29 (DOA[29], doa_out29); + buf b_doa30 (DOA[30], doa_out30); + buf b_doa31 (DOA[31], doa_out31); + buf b_dopa0 (DOPA[0], dopa_out0); + buf b_dopa1 (DOPA[1], dopa_out1); + buf b_dopa2 (DOPA[2], dopa_out2); + buf b_dopa3 (DOPA[3], dopa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dob16 (DOB[16], dob_out16); + buf b_dob17 (DOB[17], dob_out17); + buf b_dob18 (DOB[18], dob_out18); + buf b_dob19 (DOB[19], dob_out19); + buf b_dob20 (DOB[20], dob_out20); + buf b_dob21 (DOB[21], dob_out21); + buf b_dob22 (DOB[22], dob_out22); + buf b_dob23 (DOB[23], dob_out23); + buf b_dob24 (DOB[24], dob_out24); + buf b_dob25 (DOB[25], dob_out25); + buf b_dob26 (DOB[26], dob_out26); + buf b_dob27 (DOB[27], dob_out27); + buf b_dob28 (DOB[28], dob_out28); + buf b_dob29 (DOB[29], dob_out29); + buf b_dob30 (DOB[30], dob_out30); + buf b_dob31 (DOB[31], dob_out31); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + buf b_dopb2 (DOPB[2], dopb_out2); + buf b_dopb3 (DOPB[3], dopb_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dia_8 (dia_int[8], DIA[8]); + buf b_dia_9 (dia_int[9], DIA[9]); + buf b_dia_10 (dia_int[10], DIA[10]); + buf b_dia_11 (dia_int[11], DIA[11]); + buf b_dia_12 (dia_int[12], DIA[12]); + buf b_dia_13 (dia_int[13], DIA[13]); + buf b_dia_14 (dia_int[14], DIA[14]); + buf b_dia_15 (dia_int[15], DIA[15]); + buf b_dia_16 (dia_int[16], DIA[16]); + buf b_dia_17 (dia_int[17], DIA[17]); + buf b_dia_18 (dia_int[18], DIA[18]); + buf b_dia_19 (dia_int[19], DIA[19]); + buf b_dia_20 (dia_int[20], DIA[20]); + buf b_dia_21 (dia_int[21], DIA[21]); + buf b_dia_22 (dia_int[22], DIA[22]); + buf b_dia_23 (dia_int[23], DIA[23]); + buf b_dia_24 (dia_int[24], DIA[24]); + buf b_dia_25 (dia_int[25], DIA[25]); + buf b_dia_26 (dia_int[26], DIA[26]); + buf b_dia_27 (dia_int[27], DIA[27]); + buf b_dia_28 (dia_int[28], DIA[28]); + buf b_dia_29 (dia_int[29], DIA[29]); + buf b_dia_30 (dia_int[30], DIA[30]); + buf b_dia_31 (dia_int[31], DIA[31]); + buf b_dipa_0 (dipa_int[0], DIPA[0]); + buf b_dipa_1 (dipa_int[1], DIPA[1]); + buf b_dipa_2 (dipa_int[2], DIPA[2]); + buf b_dipa_3 (dipa_int[3], DIPA[3]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dib_16 (dib_int[16], DIB[16]); + buf b_dib_17 (dib_int[17], DIB[17]); + buf b_dib_18 (dib_int[18], DIB[18]); + buf b_dib_19 (dib_int[19], DIB[19]); + buf b_dib_20 (dib_int[20], DIB[20]); + buf b_dib_21 (dib_int[21], DIB[21]); + buf b_dib_22 (dib_int[22], DIB[22]); + buf b_dib_23 (dib_int[23], DIB[23]); + buf b_dib_24 (dib_int[24], DIB[24]); + buf b_dib_25 (dib_int[25], DIB[25]); + buf b_dib_26 (dib_int[26], DIB[26]); + buf b_dib_27 (dib_int[27], DIB[27]); + buf b_dib_28 (dib_int[28], DIB[28]); + buf b_dib_29 (dib_int[29], DIB[29]); + buf b_dib_30 (dib_int[30], DIB[30]); + buf b_dib_31 (dib_int[31], DIB[31]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_dipb_2 (dipb_int[2], DIPB[2]); + buf b_dipb_3 (dipb_int[3], DIPB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 32; + assign data_addra_reg = addra_reg * 32; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + assign parity_addra_int = 16384 + addra_int * 4; + assign parity_addra_reg = 16384 + addra_reg * 4; + assign parity_addrb_int = 16384 + addrb_int * 4; + assign parity_addrb_reg = 16384 + addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 32'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dob_out <= 32'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 32'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dob_out <= 32'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 32'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dob_out <= 32'bX; + end + data_collision_b_a[0] <= 0; + end + + + // Parity + always @(posedge memory_collision) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_a_b) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_reg + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_b_a) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 4'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 4'bX; + end + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dopb_out <= 4'bX; + end + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + doa_out[4] <= SRVAL_A[4]; + doa_out[5] <= SRVAL_A[5]; + doa_out[6] <= SRVAL_A[6]; + doa_out[7] <= SRVAL_A[7]; + doa_out[8] <= SRVAL_A[8]; + doa_out[9] <= SRVAL_A[9]; + doa_out[10] <= SRVAL_A[10]; + doa_out[11] <= SRVAL_A[11]; + doa_out[12] <= SRVAL_A[12]; + doa_out[13] <= SRVAL_A[13]; + doa_out[14] <= SRVAL_A[14]; + doa_out[15] <= SRVAL_A[15]; + doa_out[16] <= SRVAL_A[16]; + doa_out[17] <= SRVAL_A[17]; + doa_out[18] <= SRVAL_A[18]; + doa_out[19] <= SRVAL_A[19]; + doa_out[20] <= SRVAL_A[20]; + doa_out[21] <= SRVAL_A[21]; + doa_out[22] <= SRVAL_A[22]; + doa_out[23] <= SRVAL_A[23]; + doa_out[24] <= SRVAL_A[24]; + doa_out[25] <= SRVAL_A[25]; + doa_out[26] <= SRVAL_A[26]; + doa_out[27] <= SRVAL_A[27]; + doa_out[28] <= SRVAL_A[28]; + doa_out[29] <= SRVAL_A[29]; + doa_out[30] <= SRVAL_A[30]; + doa_out[31] <= SRVAL_A[31]; + dopa_out[0] <= SRVAL_A[32]; + dopa_out[1] <= SRVAL_A[33]; + dopa_out[2] <= SRVAL_A[34]; + dopa_out[3] <= SRVAL_A[35]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + dopa_out <= dipa_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + doa_out[16] <= mem[data_addra_int + 16]; + doa_out[17] <= mem[data_addra_int + 17]; + doa_out[18] <= mem[data_addra_int + 18]; + doa_out[19] <= mem[data_addra_int + 19]; + doa_out[20] <= mem[data_addra_int + 20]; + doa_out[21] <= mem[data_addra_int + 21]; + doa_out[22] <= mem[data_addra_int + 22]; + doa_out[23] <= mem[data_addra_int + 23]; + doa_out[24] <= mem[data_addra_int + 24]; + doa_out[25] <= mem[data_addra_int + 25]; + doa_out[26] <= mem[data_addra_int + 26]; + doa_out[27] <= mem[data_addra_int + 27]; + doa_out[28] <= mem[data_addra_int + 28]; + doa_out[29] <= mem[data_addra_int + 29]; + doa_out[30] <= mem[data_addra_int + 30]; + doa_out[31] <= mem[data_addra_int + 31]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + dopa_out[2] <= mem[parity_addra_int + 2]; + dopa_out[3] <= mem[parity_addra_int + 3]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + doa_out[16] <= mem[data_addra_int + 16]; + doa_out[17] <= mem[data_addra_int + 17]; + doa_out[18] <= mem[data_addra_int + 18]; + doa_out[19] <= mem[data_addra_int + 19]; + doa_out[20] <= mem[data_addra_int + 20]; + doa_out[21] <= mem[data_addra_int + 21]; + doa_out[22] <= mem[data_addra_int + 22]; + doa_out[23] <= mem[data_addra_int + 23]; + doa_out[24] <= mem[data_addra_int + 24]; + doa_out[25] <= mem[data_addra_int + 25]; + doa_out[26] <= mem[data_addra_int + 26]; + doa_out[27] <= mem[data_addra_int + 27]; + doa_out[28] <= mem[data_addra_int + 28]; + doa_out[29] <= mem[data_addra_int + 29]; + doa_out[30] <= mem[data_addra_int + 30]; + doa_out[31] <= mem[data_addra_int + 31]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + dopa_out[2] <= mem[parity_addra_int + 2]; + dopa_out[3] <= mem[parity_addra_int + 3]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + mem[data_addra_int + 4] <= dia_int[4]; + mem[data_addra_int + 5] <= dia_int[5]; + mem[data_addra_int + 6] <= dia_int[6]; + mem[data_addra_int + 7] <= dia_int[7]; + mem[data_addra_int + 8] <= dia_int[8]; + mem[data_addra_int + 9] <= dia_int[9]; + mem[data_addra_int + 10] <= dia_int[10]; + mem[data_addra_int + 11] <= dia_int[11]; + mem[data_addra_int + 12] <= dia_int[12]; + mem[data_addra_int + 13] <= dia_int[13]; + mem[data_addra_int + 14] <= dia_int[14]; + mem[data_addra_int + 15] <= dia_int[15]; + mem[data_addra_int + 16] <= dia_int[16]; + mem[data_addra_int + 17] <= dia_int[17]; + mem[data_addra_int + 18] <= dia_int[18]; + mem[data_addra_int + 19] <= dia_int[19]; + mem[data_addra_int + 20] <= dia_int[20]; + mem[data_addra_int + 21] <= dia_int[21]; + mem[data_addra_int + 22] <= dia_int[22]; + mem[data_addra_int + 23] <= dia_int[23]; + mem[data_addra_int + 24] <= dia_int[24]; + mem[data_addra_int + 25] <= dia_int[25]; + mem[data_addra_int + 26] <= dia_int[26]; + mem[data_addra_int + 27] <= dia_int[27]; + mem[data_addra_int + 28] <= dia_int[28]; + mem[data_addra_int + 29] <= dia_int[29]; + mem[data_addra_int + 30] <= dia_int[30]; + mem[data_addra_int + 31] <= dia_int[31]; + mem[parity_addra_int + 0] <= dipa_int[0]; + mem[parity_addra_int + 1] <= dipa_int[1]; + mem[parity_addra_int + 2] <= dipa_int[2]; + mem[parity_addra_int + 3] <= dipa_int[3]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dob_out[16] <= SRVAL_B[16]; + dob_out[17] <= SRVAL_B[17]; + dob_out[18] <= SRVAL_B[18]; + dob_out[19] <= SRVAL_B[19]; + dob_out[20] <= SRVAL_B[20]; + dob_out[21] <= SRVAL_B[21]; + dob_out[22] <= SRVAL_B[22]; + dob_out[23] <= SRVAL_B[23]; + dob_out[24] <= SRVAL_B[24]; + dob_out[25] <= SRVAL_B[25]; + dob_out[26] <= SRVAL_B[26]; + dob_out[27] <= SRVAL_B[27]; + dob_out[28] <= SRVAL_B[28]; + dob_out[29] <= SRVAL_B[29]; + dob_out[30] <= SRVAL_B[30]; + dob_out[31] <= SRVAL_B[31]; + dopb_out[0] <= SRVAL_B[32]; + dopb_out[1] <= SRVAL_B[33]; + dopb_out[2] <= SRVAL_B[34]; + dopb_out[3] <= SRVAL_B[35]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[data_addrb_int + 16] <= dib_int[16]; + mem[data_addrb_int + 17] <= dib_int[17]; + mem[data_addrb_int + 18] <= dib_int[18]; + mem[data_addrb_int + 19] <= dib_int[19]; + mem[data_addrb_int + 20] <= dib_int[20]; + mem[data_addrb_int + 21] <= dib_int[21]; + mem[data_addrb_int + 22] <= dib_int[22]; + mem[data_addrb_int + 23] <= dib_int[23]; + mem[data_addrb_int + 24] <= dib_int[24]; + mem[data_addrb_int + 25] <= dib_int[25]; + mem[data_addrb_int + 26] <= dib_int[26]; + mem[data_addrb_int + 27] <= dib_int[27]; + mem[data_addrb_int + 28] <= dib_int[28]; + mem[data_addrb_int + 29] <= dib_int[29]; + mem[data_addrb_int + 30] <= dib_int[30]; + mem[data_addrb_int + 31] <= dib_int[31]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + mem[parity_addrb_int + 2] <= dipb_int[2]; + mem[parity_addrb_int + 3] <= dipb_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKA *> DOPA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.9 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S36_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DOA; + output [3:0] DOPA; + output [31:0] DOB; + output [3:0] DOPB; + + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA, CLKA, WEA, SSRA; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [31:0] doa_out = INIT_A[31:0]; + reg [3:0] dopa_out = INIT_A[35:32]; + reg [31:0] dob_out = INIT_B[31:0]; + reg [3:0] dopb_out = INIT_B[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [31:0] dia_int; + wire [3:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [31:0] (DOA, doa_out); + buf b_dopa [3:0] (DOPA, dopa_out); + buf b_addra [8:0] (addra_int, ADDRA); + buf b_dia [31:0] (dia_int, DIA); + buf b_dipa [3:0] (dipa_int, DIPA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [31:0] (DOB, dob_out); + buf b_dopb [3:0] (DOPB, dopb_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [31:0] (dib_int, DIB); + buf b_dipb [3:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {dopa_out, doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + initial begin : initialize_mems + +`ifdef UNDEFINED + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end +`else + integer i; + for (i = 0; i < 512; i = i + 1) + begin + mem[i] = 0; + memp[i] = 0; + end + +`endif + +// initiate parity start +`ifdef UNDEFINED + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +`endif +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 32; + assign data_addra_reg = addra_reg * 32; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 32'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg] <= 32'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 32'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision_b_a[0] <= 0; + end + +// x parity start + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 4'bx; + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) + memp[addra_reg] <= 4'bx; + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 4'bx; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end +// x parity end + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {dopa_out, doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + dopa_out <= #100 dipa_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + else begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + memp[addra_int] <= dipa_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/usrp2/fpga/eth/rtl/verilog/elastic_buffer.v b/usrp2/fpga/eth/rtl/verilog/elastic_buffer.v new file mode 100644 index 00000000..56c821b7 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/elastic_buffer.v @@ -0,0 +1,93 @@ + + +module elastic_buffer + ( input rx_clk, + input tx_clk, + input rst, + + input [7:0] rxd, + input rx_dv, + input rx_er, + input crs, + input col, + + output [7:0] rxd_ret, + output rx_dv_ret, + output rx_er_ret, + output crs_ret, + output col_ret ); + + reg [3:0] addr_wr,addr_wr_gray,awg_d1,awg_d2,addr_wr_gray_ret,awgr_d1,addr_wr_ungray,addr_rd; + + reg [11:0] buffer [0:15]; + integer i; + initial + for(i=0;i<16;i=i+1) + buffer[i] <= 0; + + reg [7:0] rxd_d1, rxd_d2; + reg rx_dv_d1,rx_er_d1,crs_d1,col_d1, rx_dv_d2,rx_er_d2,crs_d2,col_d2; + wire rx_dv_ret_adv; + reg rx_dv_ontime; + + always @(posedge rx_clk) + {col_d1,crs_d1,rx_er_d1,rx_dv_d1,rxd_d1} <= {col,crs,rx_er,rx_dv,rxd}; + + always @(posedge rx_clk) + {col_d2,crs_d2,rx_er_d2,rx_dv_d2,rxd_d2} <= {col_d1,crs_d1,rx_er_d1,rx_dv_d1,rxd_d1}; + + always @(posedge rx_clk) + buffer[addr_wr] <= {col_d2,crs_d2,rx_er_d2,rx_dv_d1,rxd_d2}; + + always @(posedge rx_clk or posedge rst) + if(rst) addr_wr <= 0; + else addr_wr <= addr_wr + 1; + + always @(posedge rx_clk) + begin + addr_wr_gray <= {addr_wr[3],^addr_wr[3:2],^addr_wr[2:1],^addr_wr[1:0]}; + awg_d1 <= addr_wr_gray; + awg_d2 <= awg_d1; + end + + always @(posedge tx_clk) + begin + addr_wr_gray_ret <= awg_d2; + awgr_d1 <= addr_wr_gray_ret; + addr_wr_ungray <= {awgr_d1[3],^awgr_d1[3:2],^awgr_d1[3:1],^awgr_d1[3:0]}; + end + + wire [3:0] addr_delta = addr_rd-addr_wr_ungray; + reg [1:0] direction; + localparam retard = 2'd0; + localparam good = 2'd1; + localparam advance = 2'd2; + localparam wayoff = 2'd3; + + always @* + case(addr_delta) + 4'd1, 4'd2, 4'd3, 4'd4, 4'd5 : direction <= retard; + 4'd15, 4'd14, 4'd13, 4'd12, 4'd11 : direction <= advance; + 4'd0 : direction <= good; + default : direction <= wayoff; + endcase // case(addr_delta) + + always @(posedge tx_clk or posedge rst) + if(rst) + addr_rd <= 0; + else if(rx_dv_ret_adv | rx_dv_ontime) + addr_rd <= addr_rd + 1; + else + case(direction) + retard : addr_rd <= addr_rd; + advance : addr_rd <= addr_rd + 2; + good : addr_rd <= addr_rd + 1; + wayoff : addr_rd <= addr_wr_ungray; + endcase // case(direction) + + assign {col_ret,crs_ret,rx_er_ret,rx_dv_ret_adv,rxd_ret} = buffer[addr_rd]; + always @(posedge tx_clk) + rx_dv_ontime <= rx_dv_ret_adv; + + assign rx_dv_ret = rx_dv_ontime; +endmodule // elastic_buffer diff --git a/usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v b/usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v new file mode 100644 index 00000000..757049ec --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v @@ -0,0 +1,66 @@ + +module elastic_buffer_tb; + + reg rx_clk = 0, tx_clk = 0, rst = 1; + + reg [7:0] rxd; + wire [7:0] rxd_ret; + reg rx_dv, rx_er, crs, col; + wire rx_dv_ret, rx_er_ret, crs_ret, col_ret; + + elastic_buffer elastic_buffer + (.rx_clk(rx_clk),.tx_clk(tx_clk),.rst(rst), + .rxd(rxd),.rx_dv(rx_dv),.rx_er(rx_er),.crs(crs),.col(col), + .rxd_ret(rxd_ret),.rx_dv_ret(rx_dv_ret),.rx_er_ret(rx_er_ret), + .crs_ret(crs_ret),.col_ret(col_ret) ); + + always #100 rx_clk = ~rx_clk; + always #101 tx_clk = ~tx_clk; + initial #950 rst = 0; + + initial + begin + {col,crs,rx_er,rx_dv,rxd} <= 0; + @(negedge rst); + @(posedge rx_clk); + + repeat (13) + begin + repeat (284) + @(posedge rx_clk); + SendPKT; + end + repeat (100) + @(posedge rx_clk); + $finish; + end // initial begin + + reg [7:0] rxd_ret_d1; + always @(posedge tx_clk) + rxd_ret_d1 <= rxd_ret; + + wire [7:0] diff = rxd_ret_d1 - rxd_ret; + + wire error = rx_dv_ret && (diff != 8'hFF); + + task SendPKT; + begin + {col,crs,rx_er,rx_dv,rxd} <= 0; + @(posedge rx_clk); + {col,crs,rx_er,rx_dv,rxd} <= {4'hF,8'd1}; + @(posedge rx_clk); + repeat (250) + begin + rxd <= rxd + 1; + @(posedge rx_clk); + end + {col,crs,rx_er,rx_dv,rxd} <= 0; + @(posedge rx_clk); + end + endtask // SendPKT + + initial begin + $dumpfile("elastic_buffer_tb.vcd"); + $dumpvars(0,elastic_buffer_tb); + end +endmodule // elastic_buffer_tb diff --git a/usrp2/fpga/eth/rtl/verilog/eth_miim.v b/usrp2/fpga/eth/rtl/verilog/eth_miim.v new file mode 100644 index 00000000..a15c9420 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/eth_miim.v @@ -0,0 +1,470 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_miim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_miim.v,v $ +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +// Revision 1.4 2005/08/16 12:07:57 Administrator +// no message +// +// Revision 1.3 2005/05/19 07:04:29 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:46 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.5 2003/05/16 10:08:27 mohor +// Busy was set 2 cycles too late. Reported by Dennis Scott. +// +// Revision 1.4 2002/08/14 18:32:10 mohor +// - Busy signal was not set on time when scan status operation was performed +// and clock was divided with more than 2. +// - Nvalid remains valid two more clocks (was previously cleared too soon). +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.2 2001/08/02 09:25:31 mohor +// Unconnected signals are now connected. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +module eth_miim +( + Clk, + Reset, + Divider, + NoPre, + CtrlData, + Rgad, + Fiad, + WCtrlData, + RStat, + ScanStat, + Mdio, + Mdc, + Busy, + Prsd, + LinkFail, + Nvalid, + WCtrlDataStart, + RStatStart, + UpdateMIIRX_DATAReg +); + +input Clk; // Host Clock +input Reset; // General Reset +input [7:0] Divider; // Divider for the host clock +input [15:0] CtrlData; // Control Data (to be written to the PHY reg.) +input [4:0] Rgad; // Register Address (within the PHY) +input [4:0] Fiad; // PHY Address +input NoPre; // No Preamble (no 32-bit preamble) +input WCtrlData; // Write Control Data operation +input RStat; // Read Status operation +input ScanStat; // Scan Status operation +inout Mdio; // MII Management Data In + +output Mdc; // MII Management Data Clock + +output Busy; // Busy Signal +output LinkFail; // Link Integrity Signal +output Nvalid; // Invalid Status (qualifier for the valid scan result) + +output [15:0] Prsd; // Read Status Data (data read from the PHY) + +output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register +output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register +output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + +//parameter Tp = 1; + + +reg Nvalid; +reg EndBusy_d; // Pre-end Busy signal +reg EndBusy; // End Busy signal (stops the operation in progress) + +reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle +reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles +reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles +reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected) +reg WCtrlDataStart_q; +reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle +reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles + +reg RStat_q1; // Read Status operation delayed 1 Clk cycle +reg RStat_q2; // Read Status operation delayed 2 Clk cycles +reg RStat_q3; // Read Status operation delayed 3 Clk cycles +reg RStatStart; // Start Read Status Command (positive edge detected) +reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle +reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles + +reg ScanStat_q1; // Scan Status operation delayed 1 cycle +reg ScanStat_q2; // Scan Status operation delayed 2 cycles +reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn + +wire WriteDataOp; // Write Data Operation (positive edge detected) +wire ReadStatusOp; // Read Status Operation (positive edge detected) +wire ScanStatusOp; // Scan Status Operation (positive edge detected) +wire StartOp; // Start Operation (start of any of the preceding operations) +wire EndOp; // End of Operation + +reg InProgress; // Operation in progress +reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle +reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles +reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles + +reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +reg [6:0] BitCounter; // Bit Counter + + +wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. +wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises. +wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal + + +wire LatchByte1_d2; +wire LatchByte0_d2; +reg LatchByte1_d; +reg LatchByte0_d; +reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register + +reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data + +wire Mdo; // MII Management Data Output +wire MdoEn; // MII Management Data Output Enable +wire Mdi; + +assign Mdi=Mdio; +assign Mdio=MdoEn?Mdo:1'bz; + + + +// Generation of the EndBusy signal. It is used for ending the MII Management operation. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + EndBusy_d <= 1'b0; + EndBusy <= 1'b0; + end + else + begin + EndBusy_d <= ~InProgress_q2 & InProgress_q3; + EndBusy <= EndBusy_d; + end +end + + +// Update MII RX_DATA register +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + UpdateMIIRX_DATAReg <= 0; + else + if(EndBusy & ~WCtrlDataStart_q) + UpdateMIIRX_DATAReg <= 1; + else + UpdateMIIRX_DATAReg <= 0; +end + + + +// Generation of the delayed signals used for positive edge triggering. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlData_q1 <= 1'b0; + WCtrlData_q2 <= 1'b0; + WCtrlData_q3 <= 1'b0; + + RStat_q1 <= 1'b0; + RStat_q2 <= 1'b0; + RStat_q3 <= 1'b0; + + ScanStat_q1 <= 1'b0; + ScanStat_q2 <= 1'b0; + SyncStatMdcEn <= 1'b0; + end + else + begin + WCtrlData_q1 <= WCtrlData; + WCtrlData_q2 <= WCtrlData_q1; + WCtrlData_q3 <= WCtrlData_q2; + + RStat_q1 <= RStat; + RStat_q2 <= RStat_q1; + RStat_q3 <= RStat_q2; + + ScanStat_q1 <= ScanStat; + ScanStat_q2 <= ScanStat_q1; + if(MdcEn) + SyncStatMdcEn <= ScanStat_q2; + end +end + + +// Generation of the Start Commands (Write Control Data or Read Status) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart <= 1'b0; + WCtrlDataStart_q <= 1'b0; + RStatStart <= 1'b0; + end + else + begin + if(EndBusy) + begin + WCtrlDataStart <= 1'b0; + RStatStart <= 1'b0; + end + else + begin + if(WCtrlData_q2 & ~WCtrlData_q3) + WCtrlDataStart <= 1'b1; + if(RStat_q2 & ~RStat_q3) + RStatStart <= 1'b1; + WCtrlDataStart_q <= WCtrlDataStart; + end + end +end + + +// Generation of the Nvalid signal (indicates when the status is invalid) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Nvalid <= 1'b0; + else + begin + if(~InProgress_q2 & InProgress_q3) + begin + Nvalid <= 1'b0; + end + else + begin + if(ScanStat_q2 & ~SyncStatMdcEn) + Nvalid <= 1'b1; + end + end +end + +// Signals used for the generation of the Operation signals (positive edge) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + WCtrlDataStart_q1 <= 1'b0; + WCtrlDataStart_q2 <= 1'b0; + + RStatStart_q1 <= 1'b0; + RStatStart_q2 <= 1'b0; + + InProgress_q1 <= 1'b0; + InProgress_q2 <= 1'b0; + InProgress_q3 <= 1'b0; + + LatchByte0_d <= 1'b0; + LatchByte1_d <= 1'b0; + + LatchByte <= 2'b00; + end + else + begin + if(MdcEn) + begin + WCtrlDataStart_q1 <= WCtrlDataStart; + WCtrlDataStart_q2 <= WCtrlDataStart_q1; + + RStatStart_q1 <= RStatStart; + RStatStart_q2 <= RStatStart_q1; + + LatchByte[0] <= LatchByte0_d; + LatchByte[1] <= LatchByte1_d; + + LatchByte0_d <= LatchByte0_d2; + LatchByte1_d <= LatchByte1_d2; + + InProgress_q1 <= InProgress; + InProgress_q2 <= InProgress_q1; + InProgress_q3 <= InProgress_q2; + end + end +end + + +// Generation of the Operation signals +assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; +assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2; +assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2; +assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; + +// Busy +reg Busy; +always @ (posedge Clk or posedge Reset) + if (Reset) + Busy <=0; + else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid) + Busy <=1; + else + Busy <=0; + +//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid; + + +// Generation of the InProgress signal (indicates when an operation is in progress) +// Generation of the WriteOp signal (indicates when a write is in progress) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + InProgress <= 1'b0; + WriteOp <= 1'b0; + end + else + begin + if(MdcEn) + begin + if(StartOp) + begin + if(~InProgress) + WriteOp <= WriteDataOp; + InProgress <= 1'b1; + end + else + begin + if(EndOp) + begin + InProgress <= 1'b0; + WriteOp <= 1'b0; + end + end + end + end +end + + + +// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + BitCounter[6:0] <= 7'h0; + else + begin + if(MdcEn) + begin + if(InProgress) + begin + if(NoPre & ( BitCounter == 7'h0 )) + BitCounter[6:0] <= 7'h21; + else + BitCounter[6:0] <= BitCounter[6:0] + 1'b1; + end + else + BitCounter[6:0] <= 7'h0; + end + end +end + + +// Operation ends when the Bit Counter reaches 63 +assign EndOp = BitCounter==63; + +assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20))); +assign ByteSelect[1] = InProgress & (BitCounter == 7'h28); +assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30); +assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38); + + +// Latch Byte selects which part of Read Status Data is updated from the shift register +assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37; +assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F; + +wire MdcEn_n; + +// Connecting the Clock Generator Module +eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) + ); + +// Connecting the Shift Register Module +eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), + .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), + .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) + ); + +// Connecting the Output Control Module +eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), + .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), + .Mdo(Mdo), .MdoEn(MdoEn) + ); + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v new file mode 100644 index 00000000..7ded9e08 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v @@ -0,0 +1,85 @@ + +// RX side of flow control -- when we are running out of RX space, send a PAUSE + +module flow_ctrl_rx + (input rst, + //host processor + input pause_frame_send_en, + input [15:0] pause_quanta_set, + input [15:0] fc_hwmark, + input [15:0] fc_lwmark, + // From MAC_rx_ctrl + input rx_clk, + input [15:0] rx_fifo_space, + // MAC_tx_ctrl + input tx_clk, + output reg xoff_gen, + output reg xon_gen, + input xoff_gen_complete, + input xon_gen_complete + ); + + // ****************************************************************************** + // Force our TX to send a PAUSE frame because our RX is nearly full + // ****************************************************************************** + + reg xon_int, xoff_int; + reg [21:0] countdown; + + always @(posedge rx_clk or posedge rst) + if(rst) + begin + xon_int <= 0; + xoff_int <= 0; + end + else + begin + xon_int <= 0; + xoff_int <= 0; + if(pause_frame_send_en) + if(countdown == 0) + if(rx_fifo_space < fc_lwmark) + xoff_int <= 1; + else + ; + else + if(rx_fifo_space > fc_hwmark) + xon_int <= 1; + end // else: !if(rst) + + reg xoff_int_d1, xon_int_d1; + + always @(posedge rx_clk) + xon_int_d1 <= xon_int; + always @(posedge rx_clk) + xoff_int_d1 <= xoff_int; + + always @ (posedge tx_clk or posedge rst) + if (rst) + xoff_gen <=0; + else if (xoff_gen_complete) + xoff_gen <=0; + else if (xoff_int | xoff_int_d1) + xoff_gen <=1; + + always @ (posedge tx_clk or posedge rst) + if (rst) + xon_gen <=0; + else if (xon_gen_complete) + xon_gen <=0; + else if (xon_int | xon_int_d1) + xon_gen <=1; + + wire [15:0] pq_reduced = pause_quanta_set - 2; + + always @(posedge tx_clk or posedge rst) + if(rst) + countdown <= 0; + else if(xoff_gen) + countdown <= {pq_reduced,6'd0}; + else if(xon_gen) + countdown <= 0; + else if(countdown != 0) + countdown <= countdown - 1; + +endmodule // flow_ctrl diff --git a/usrp2/fpga/eth/rtl/verilog/flow_ctrl_tx.v b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_tx.v new file mode 100644 index 00000000..9f7556de --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_tx.v @@ -0,0 +1,36 @@ + +// TX side of flow control -- when other side sends PAUSE, we wait + +module flow_ctrl_tx + (input rst, + input tx_clk, + //host processor + input tx_pause_en, + // From MAC_rx_ctrl + input [15:0] pause_quanta, + input pause_quanta_val, + // MAC_tx_ctrl + output pause_apply, + input pause_quanta_sub); + + // ****************************************************************************** + // Inhibit our TX from transmitting because they sent us a PAUSE frame + // ****************************************************************************** + + reg [15:0] pause_quanta_counter; + reg pqval_d1, pqval_d2; + + always @(posedge tx_clk) pqval_d1 <= pause_quanta_val; + always @(posedge tx_clk) pqval_d2 <= pqval_d1; + + always @ (posedge tx_clk or posedge rst) + if (rst) + pause_quanta_counter <= 0; + else if (pqval_d1 & ~pqval_d2) + pause_quanta_counter <= pause_quanta; + else if((pause_quanta_counter!=0) & pause_quanta_sub) + pause_quanta_counter <= pause_quanta_counter - 1; + + assign pause_apply = tx_pause_en & (pause_quanta_counter != 0); + +endmodule // flow_ctrl diff --git a/usrp2/fpga/eth/rtl/verilog/header.vh b/usrp2/fpga/eth/rtl/verilog/header.vh new file mode 100644 index 00000000..ca0b580e --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/header.vh @@ -0,0 +1,7 @@ +`define MAC_SOURCE_REPLACE_EN 1 +`define MAC_TARGET_CHECK_EN 1 +`define MAC_BROADCAST_FILTER_EN 1 +`define MAC_TX_FF_DEPTH 9 +`define MAC_RX_FF_DEPTH 9 +`define MAC_TARGET_XILINX 1 +// `define MAC_TARGET_ALTERA 1 diff --git a/usrp2/fpga/eth/rtl/verilog/miim/eth_clockgen.v b/usrp2/fpga/eth/rtl/verilog/miim/eth_clockgen.v new file mode 100644 index 00000000..9da732f7 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/miim/eth_clockgen.v @@ -0,0 +1,141 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_clockgen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_clockgen.v,v $ +// Revision 1.2 2005/12/13 12:54:49 maverickist +// first simulation passed +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:45 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:55 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); + +//parameter Tp=1; + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) + +output Mdc; // Output clock +output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises. +output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. + +reg Mdc; +reg [7:0] Counter; + +wire CountEq0; +wire [7:0] CounterPreset; +wire [7:0] TempDivider; + + +assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2 +assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period + + +// Counter counts half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Counter[7:0] <= 8'h1; + else + begin + if(CountEq0) + begin + Counter[7:0] <= CounterPreset[7:0]; + end + else + Counter[7:0] <= Counter - 8'h1; + end +end + + +// Mdc is asserted every other half period +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + Mdc <= 1'b0; + else + begin + if(CountEq0) + Mdc <= ~Mdc; + end +end + + +assign CountEq0 = Counter == 8'h0; +assign MdcEn = CountEq0 & ~Mdc; +assign MdcEn_n = CountEq0 & Mdc; + +endmodule + + diff --git a/usrp2/fpga/eth/rtl/verilog/miim/eth_outputcontrol.v b/usrp2/fpga/eth/rtl/verilog/miim/eth_outputcontrol.v new file mode 100644 index 00000000..3df6c560 --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/miim/eth_outputcontrol.v @@ -0,0 +1,158 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_outputcontrol.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_outputcontrol.v,v $ +// Revision 1.2 2005/12/13 12:54:49 maverickist +// first simulation passed +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:46 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.4 2002/07/09 20:11:59 mohor +// Comment removed. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); + +input Clk; // Host Clock +input Reset; // General Reset +input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +input NoPre; // No Preamble (no 32-bit preamble) +input InProgress; // Operation in progress +input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal +input [6:0] BitCounter; // Bit Counter +input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls. + +output Mdo; // MII Management Data Output +output MdoEn; // MII Management Data Output Enable + +wire SerialEn; + +reg MdoEn_2d; +reg MdoEn_d; +reg MdoEn; + +reg Mdo_2d; +reg Mdo_d; +reg Mdo; // MII Management Data Output + + + +// Generation of the Serial Enable signal (enables the serialization of the data) +assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) ) + | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre )); + + +// Generation of the MdoEn signal +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + MdoEn_2d <= 1'b0; + MdoEn_d <= 1'b0; + MdoEn <= 1'b0; + end + else + begin + if(MdcEn_n) + begin + MdoEn_2d <= SerialEn | InProgress & BitCounter<32; + MdoEn_d <= MdoEn_2d; + MdoEn <= MdoEn_d; + end + end +end + + +// Generation of the Mdo signal. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + Mdo_2d <= 1'b0; + Mdo_d <= 1'b0; + Mdo <= 1'b0; + end + else + begin + if(MdcEn_n) + begin + Mdo_2d <= ~SerialEn & BitCounter<32; + Mdo_d <= ShiftedBit | Mdo_2d; + Mdo <= Mdo_d; + end + end +end + + + +endmodule diff --git a/usrp2/fpga/eth/rtl/verilog/miim/eth_shiftreg.v b/usrp2/fpga/eth/rtl/verilog/miim/eth_shiftreg.v new file mode 100644 index 00000000..0b97bb7b --- /dev/null +++ b/usrp2/fpga/eth/rtl/verilog/miim/eth_shiftreg.v @@ -0,0 +1,159 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_shiftreg.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_shiftreg.v,v $ +// Revision 1.2 2005/12/13 12:54:49 maverickist +// first simulation passed +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:47 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.5 2002/08/14 18:16:59 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.4 2002/03/02 21:06:01 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, + LatchByte, ShiftedBit, Prsd, LinkFail); + + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. +input Mdi; // MII input data +input [4:0] Fiad; // PHY address +input [4:0] Rgad; // Register address (within the selected PHY) +input [15:0]CtrlData; // Control data (data to be written to the PHY) +input WriteOp; // The current operation is a PHY register write operation +input [3:0] ByteSelect; // Byte select +input [1:0] LatchByte; // Byte select for latching (read operation) + +output ShiftedBit; // Bit shifted out of the shift register +output[15:0]Prsd; // Read Status Data (data read from the PHY) +output LinkFail; // Link Integrity Signal + +reg [7:0] ShiftReg; // Shift register for shifting the data in and out +reg [15:0]Prsd; +reg LinkFail; + + + + +// ShiftReg[7:0] :: Shift Register Data +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + ShiftReg[7:0] <= 8'h0; + Prsd[15:0] <= 16'h0; + LinkFail <= 1'b0; + end + else + begin + if(MdcEn_n) + begin + if(|ByteSelect) + begin + case (ByteSelect[3:0]) + 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; + 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10}; + 4'h4 : ShiftReg[7:0] <= CtrlData[15:8]; + 4'h8 : ShiftReg[7:0] <= CtrlData[7:0]; + default : ShiftReg[7:0] <= 8'h0; + endcase + end + else + begin + ShiftReg[7:0] <= {ShiftReg[6:0], Mdi}; + if(LatchByte[0]) + begin + Prsd[7:0] <= {ShiftReg[6:0], Mdi}; + if(Rgad == 5'h01) + LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet + end + else + begin + if(LatchByte[1]) + Prsd[15:8] <= {ShiftReg[6:0], Mdi}; + end + end + end + end +end + + +assign ShiftedBit = ShiftReg[7]; + + +endmodule diff --git a/usrp2/fpga/eth/rx_prot_engine.v b/usrp2/fpga/eth/rx_prot_engine.v new file mode 100644 index 00000000..d34f168d --- /dev/null +++ b/usrp2/fpga/eth/rx_prot_engine.v @@ -0,0 +1,156 @@ + +module rx_prot_engine + #(parameter FIFO_SIZE=11) + (input clk, input rst, + + input Rx_mac_ra, + output Rx_mac_rd, + input [31:0] Rx_mac_data, + input [1:0] Rx_mac_BE, + input Rx_mac_pa, + input Rx_mac_sop, + input Rx_mac_eop, + input Rx_mac_err, + + output [31:0] wr_dat_o, + output wr_write_o, + output wr_done_o, + output wr_error_o, + input wr_ready_i, + input wr_full_i, + output wr_flag_o, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + + output [15:0] rx_fifo_status, + output reg [7:0] rx_seqnum, + output reg [7:0] rx_channel, + output [7:0] rx_flags + ); + + wire read, write, full, empty; + wire eop_i, err_i, eop_o, err_o, flag_i, sop_i, flag_o, sop_o; + wire [31:0] dat_i, dat_o; + reg xfer_active; + + wire [3:0] hdr_adr; + wire [31:0] hdr_dat; + + header_ram #(.REGNUM(48),.WIDTH(32)) rx_header_ram + (.clk(clk),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .addr(hdr_adr),.q(hdr_dat)); + + // Buffer interface side + always @(posedge clk) + if(rst) + xfer_active <= 0; + else if(wr_ready_i & ~empty) + xfer_active <= 1; + else if(eop_o | err_o | wr_full_i) + xfer_active <= 0; + + assign wr_done_o = eop_o & wr_write_o; + assign wr_error_o = err_o & wr_write_o; + assign wr_dat_o = dat_o; + assign wr_write_o = xfer_active & ~empty; + assign read = wr_write_o; + + // FIFO in the middle + cascadefifo2 #(.WIDTH(36),.SIZE(11)) rx_prot_fifo + (.clk(clk),.rst(rst), + .datain({flag_i,sop_i,eop_i,err_i,dat_i}),.write(write),.full(full), + .dataout({flag_o,sop_o,eop_o,err_o,dat_o}),.read(read),.empty(empty), + .clear(0),.fifo_space(rx_fifo_status)); + + // MAC side + localparam ETH_TYPE = 16'hBEEF; + + reg [2:0] prot_state; + localparam PROT_IDLE = 0; + localparam PROT_HDR1 = 1; + localparam PROT_HDR2 = 2; + localparam PROT_HDR3 = 3; + localparam PROT_HDR4 = 4; + localparam PROT_HDR5 = 5; + localparam PROT_PKT = 6; + + // Things to control: flag_i, sop_i, eop_i, err_i, dat_i, write, Rx_mac_rd + // Inputs to SM: Rx_mac_sop, Rx_mac_eop, Rx_mac_ra, Rx_mac_pa, + // Rx_mac_BE, Rx_mac_err, full + + reg flag; + assign dat_i = Rx_mac_data; + assign sop_i = Rx_mac_sop; + assign eop_i = Rx_mac_eop; + assign err_i = Rx_mac_err; + assign flag_i = flag; + assign wr_flag_o = flag_o; + assign Rx_mac_rd = (prot_state != PROT_IDLE) && (~full|~Rx_mac_pa); + assign write = (prot_state != PROT_IDLE) && ~full && Rx_mac_pa; + + assign hdr_adr = {1'b0,prot_state[2:0]}; + + wire [7:0] rx_seqnum_p1 = rx_seqnum + 1; + + always @(posedge clk) + if(rst) + begin + prot_state <= PROT_IDLE; + flag <= 0; + end + else if(prot_state == PROT_IDLE) + begin + flag <= 0; + if(Rx_mac_ra) + prot_state <= PROT_HDR1; + end + else if(write) + case(prot_state) + PROT_HDR1 : + begin + prot_state <= PROT_HDR2; + if(hdr_dat != Rx_mac_data) + flag <= 1; + end + PROT_HDR2 : + begin + prot_state <= PROT_HDR3; + if(hdr_dat != Rx_mac_data) + flag <= 1; + end + PROT_HDR3 : + begin + prot_state <= PROT_HDR4; + if(hdr_dat != Rx_mac_data) + flag <= 1; + end + PROT_HDR4 : + begin + prot_state <= PROT_HDR5; + if(hdr_dat[31:16] != Rx_mac_data[31:16]) + flag <= 1; + rx_channel <= hdr_dat[15:8]; + end + PROT_HDR5 : + begin + prot_state <= PROT_PKT; + if((rx_seqnum_p1) != Rx_mac_data[15:8]) + flag <= 1; + end + PROT_PKT : + if(Rx_mac_eop | Rx_mac_err) + prot_state <= PROT_IDLE; + endcase // case(prot_state) + + always @(posedge clk) + if(rst) + rx_seqnum <= 8'hFF; + else if(set_stb & (set_addr == 54)) + rx_seqnum <= set_data[7:0]; + else if(write & (prot_state == PROT_HDR5) & ((rx_seqnum_p1) == Rx_mac_data[15:8]) & ~flag) + rx_seqnum <= rx_seqnum + 1; + + // Error cases -- Rx_mac_error, BE != 0 +endmodule // rx_prot_engine diff --git a/usrp2/fpga/eth/tx_prot_engine.v b/usrp2/fpga/eth/tx_prot_engine.v new file mode 100644 index 00000000..894d74a1 --- /dev/null +++ b/usrp2/fpga/eth/tx_prot_engine.v @@ -0,0 +1,144 @@ + +module tx_prot_engine + (input clk, input rst, + + // To MAC + input Tx_mac_wa, + output Tx_mac_wr, + output [31:0] Tx_mac_data, + output [1:0] Tx_mac_BE, + output Tx_mac_sop, + output Tx_mac_eop, + + // To buffer interface + input [31:0] rd_dat_i, + output rd_read_o, + output rd_done_o, + output rd_error_o, + input rd_sop_i, + input rd_eop_i, + + // To control + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + + // Protocol Stuff + input [15:0] rx_fifo_status, + input [7:0] rx_seqnum + //input [7:0] tx_channel, + //input [7:0] tx_flags + ); + + wire [3:0] hdr_adr; + wire [31:0] hdr_dat; + wire [7:0] tx_channel; + + header_ram #(.REGNUM(32),.WIDTH(32)) tx_header_ram + (.clk(clk),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .addr(hdr_adr),.q(hdr_dat)); + + setting_reg #(.my_addr(32)) sr_channel + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data), + .out(tx_channel),.changed()); + + // Might as well use a shortfifo here since they are basically free + wire empty, full, sfifo_write, sfifo_read; + wire [33:0] sfifo_in, sfifo_out; + + shortfifo #(.WIDTH(34)) txmac_sfifo + (.clk(clk),.rst(rst),.clear(0), + .datain(sfifo_in),.write(sfifo_write),.full(full), + .dataout(sfifo_out),.read(sfifo_read),.empty(empty)); + + // MAC side signals + // Inputs -- Tx_mac_wa, sfifo_out, empty + // outputs -- sfifo_read, Tx_mac_data, Tx_mac_wr, Tx_mac_BE, Tx_mac_sop, Tx_mac_eop + + // We are allowed to do one more write after we are told the FIFO is full + // This allows us to register the _wa signal and speed up timing. + reg tx_mac_wa_d1; + always @(posedge clk) + tx_mac_wa_d1 <= Tx_mac_wa; + + reg [2:0] prot_state; + localparam PROT_IDLE = 0; + localparam PROT_HDR1 = 1; + localparam PROT_HDR2 = 2; + localparam PROT_HDR3 = 3; + localparam PROT_HDR4 = 4; + localparam PROT_HDR5 = 5; + localparam PROT_PKT = 6; + + reg [7:0] tx_seqnum; + reg all_match; + always @(posedge clk) + if(rst) + tx_seqnum <= 0; + else if(set_stb & (set_addr == 36)) + tx_seqnum <= set_data[7:0]; + else if(tx_mac_wa_d1 & all_match & (prot_state == PROT_HDR5)) + tx_seqnum <= tx_seqnum + 1; + + always @(posedge clk) + if(rst) + prot_state <= PROT_IDLE; + else + if(tx_mac_wa_d1 & ~empty) + case(prot_state) + PROT_IDLE : + prot_state <= PROT_HDR1; + PROT_HDR1 : + prot_state <= PROT_HDR2; + PROT_HDR2 : + prot_state <= PROT_HDR3; + PROT_HDR3 : + prot_state <= PROT_HDR4; + PROT_HDR4 : + prot_state <= PROT_HDR5; + PROT_HDR5 : + prot_state <= PROT_PKT; + PROT_PKT : + if(sfifo_out[32] & ~empty) + prot_state <= PROT_IDLE; + default : + prot_state <= PROT_IDLE; + endcase // case(prot_state) + + assign hdr_adr = {1'b0,prot_state}; + wire match = (hdr_dat == sfifo_out[31:0]); + always @(posedge clk) + if(prot_state == PROT_IDLE) + all_match <= 1; + else if(tx_mac_wa_d1 & ~empty & + ((prot_state==PROT_HDR1)|(prot_state==PROT_HDR2)|(prot_state==PROT_HDR3))) + all_match <= all_match & match; + + localparam ETH_TYPE = 16'hBEEF; + assign Tx_mac_data = + ((prot_state == PROT_HDR5) & all_match) ? {rx_fifo_status,tx_seqnum,rx_seqnum} : + sfifo_out[31:0]; + assign sfifo_read = (prot_state != PROT_IDLE) & ~empty & tx_mac_wa_d1; + assign Tx_mac_wr = sfifo_read; + assign Tx_mac_BE = 0; // Since we only deal with packets that are multiples of 32 bits long + assign Tx_mac_sop = sfifo_out[33]; + assign Tx_mac_eop = sfifo_out[32]; + + // BUFFER side signals + reg xfer_active; + always @(posedge clk) + if(rst) + xfer_active <= 0; + else if(rd_eop_i & ~full) + xfer_active <= 0; + else if(rd_sop_i) + xfer_active <= 1; + + assign sfifo_in = {rd_sop_i, rd_eop_i, rd_dat_i}; + assign sfifo_write = xfer_active & ~full; + + assign rd_read_o = sfifo_write; + assign rd_done_o = 0; // Always send everything we're given? + assign rd_error_o = 0; // No possible error situations? + +endmodule // tx_prot_engine diff --git a/usrp2/fpga/models/BUFG.v b/usrp2/fpga/models/BUFG.v new file mode 100644 index 00000000..a935c628 --- /dev/null +++ b/usrp2/fpga/models/BUFG.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5 2005/03/14 22:32:51 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Buffer +// /___/ /\ Filename : BUFG.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 100 ps / 10 ps + + +module BUFG (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/usrp2/fpga/models/CY7C1356C/cy1356.inp b/usrp2/fpga/models/CY7C1356C/cy1356.inp new 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+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0001001000110100_0_X_X_X_X_X_X_1 +XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0110011001100110_0_X_X_X_X_X_X_1 +XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0001001000110100_0_X_X_X_X_X_X_1 +XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0010001000100010_0_1_X_X_X_X_X_0 +xxxxxxxxxxxxxxxx_xxxxxxxxxxxxxxxx_0011001100110011_0_1_x_x_x_x_x_x +xxxxxxxxxxxxxxxx_xxxxxxxxxxxxxxxx_ZZZZZZZZZZZZZZZZ_0_1_x_x_x_x_x_x +//Lines =126 + + diff --git a/usrp2/fpga/models/CY7C1356C/cy1356.v b/usrp2/fpga/models/CY7C1356C/cy1356.v new file mode 100644 index 00000000..9197eea6 --- /dev/null +++ b/usrp2/fpga/models/CY7C1356C/cy1356.v @@ -0,0 +1,485 @@ +`define sb200 +//************************************************************************ +//************************************************************************ +//** This model is the property of Cypress Semiconductor Corp and is ** +//** protected by the US copyright laws, any unauthorized copying and ** +//** distribution is prohibited. Cypress reserves the right to change ** +//** any of the functional specifications without any prior notice. ** +//** Cypress is not liable for any damages which may result from the ** +//** use of this functional model. ** +//** ** +//** File Name : CY7C1356 ** +//** ** +//** Revision : 1.0 - 08/03/2004 ** +//** ** +//** The timings are to be selected by the user depending upon the ** +//** frequency of operation from the datasheet. ** +//** ** +//** Model : CY7C1356C - NoBL Pipelined SRAM ** +//** Queries : MPD Applications ** +//** Website: www.cypress.com/support ** +//************************************************************************ +//************************************************************************ + +`timescale 1ns / 10ps + +// NOTE : Any setup/hold errors will force input signal to x state +// or if results indeterminant (write addr) core is reset x + +// define fixed values + +`define wordsize (18 -1) // +`define no_words (1048576 -1) // 1M x 18 RAM + +module cy1356 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); + +inout [`wordsize:0] d; +input clk, // clock input (R) + we_b, // byte write enable(L) + adv_lb, // burst(H)/load(L) address + ce1b, // chip enable(L) + ce2, // chip enable(H) + ce3b, // chip enable(L) + oeb, // async output enable(L)(read) + cenb, // clock enable(L) + mode; // interleave(H)/linear(L) burst +input [1:0] bws; // byte write select(L) +input [18:0] a; // address bus + +// *** NOTE DEVICE OPERATES #0.01 AFTER CLOCK *** +// *** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT *** + + +//********************************************************************** +// Timings for 225MHz +//********************************************************************** +`ifdef sb225 + `define teohz #2.8 + `define teolz #0 + `define tchz #2.8 + `define tclz #1.25 + + `define tco #2.8 + `define tdoh #1.25 + `define tas 1.4 + `define tah 0.4 +`endif +//*********************************************************************** +// Timings for 200MHz +//********************************************************************** +`ifdef sb200 + `define teohz #3.2 + `define teolz #0 + `define tchz #3.2 + `define tclz #1.5 + + `define tco #3.2 + `define tdoh #1.5 + + `define tas 1.5 + `define tah 0.5 +`endif +//*********************************************************************** + +//********************************************************************** +// This model is configured for 166 MHz Operation (CY7C1356-166). +//********************************************************************** +`ifdef sb166 + `define teohz #3.5 + `define teolz #0 + `define tchz #3.5 + `define tclz #1.5 + + `define tco #3.5 + `define tdoh #1.5 + + `define tas 1.5 + `define tah 0.5 +`endif + +reg notifier; // error support reg's +reg noti1_0; +reg noti1_1; +reg noti1_2; +reg noti1_3; +reg noti1_4; +reg noti1_5; +reg noti1_6; +reg noti2; + + +wire chipen; // combined chip enable (high for an active chip) + +reg chipen_d; // _d = delayed +reg chipen_o; // _o = operational = delayed sig or _d sig + +wire writestate; // holds 1 if any of writebus is low +reg writestate_d; +reg writestate_o; + +wire loadcyc; // holds 1 for load cycles (setup and hold checks) +wire writecyc; // holds 1 for write cycles (setup and hold checks) +wire [1:0] bws; // holds the bws values + +wire [1:0] writebusb; // holds the "internal" bws bus based on we_b +reg [1:0] writebusb_d; +reg [1:0] writebusb_o; + +wire [2:0] operation; // holds chipen, adv_ld and writestate +reg [2:0] operation_d; +reg [2:0] operation_o; + +wire [18:0] a; // address input bus +reg [18:0] a_d; +reg [18:0] a_o; + +reg [`wordsize:0] do; // data output reg +reg [`wordsize:0] di; // data input bus +reg [`wordsize:0] dd; // data delayed bus + +wire tristate; // tristate output (on a bytewise basis) when asserted +reg cetri; // register set by chip disable which sets the tristate +reg oetri; // register set by oe which sets the tristate +reg enable; // register to make the ram enabled when equal to 1 +reg [18:0] addreg; // register to hold the input address +reg [`wordsize:0] pipereg; // register for the output data + +reg [`wordsize:0] mem [0:`no_words]; // RAM array + +reg [`wordsize:0] writeword; // temporary holding register for the write data +reg burstinit; // register to hold a[0] for burst type +reg [18:0] i; // temporary register used to write to all mem locs. +reg writetri; // tristate +reg lw, bw; // pipelined write functions +reg we_bl; + + +wire [`wordsize:0] d = !tristate ? do[`wordsize:0] : 18'bz ; // data bus + +assign chipen = (adv_lb == 1 ) ? chipen_d : + ~ce1b & ce2 & ~ce3b ; + +assign writestate = ~& writebusb; + +assign operation = {chipen, adv_lb, writestate}; + +assign writebusb[1:0] = ( we_b ==0 & adv_lb ==0) ? bws[1:0]: + ( we_b ==1 & adv_lb ==0) ? 2'b11 : + ( we_bl ==0 & adv_lb ==1) ? bws[1:0]: + ( we_bl ==1 & adv_lb ==1) ? 2'b11 : + 2'bxx ; + +assign loadcyc = chipen & !cenb; + +assign writecyc = writestate_d & enable & ~cenb & chipen; // check + +assign tristate = cetri | writetri | oetri; + +pullup (mode); + +// formers for notices/errors etc +// +//$display("NOTICE : xxx :"); +//$display("WARNING : xxx :"); +//$display("ERROR *** : xxx :"); + + +// initialize the output to be tri-state, ram to be disabled + +initial + begin +// signals + + writetri = 0; + cetri = 1; + enable = 0; + lw = 0; + bw = 0; + +// error signals + + notifier = 0; + noti1_0 = 0; + noti1_1 = 0; + noti1_2 = 0; + noti1_3 = 0; + noti1_4 = 0; + noti1_5 = 0; + noti1_6 = 0; + noti2 = 0; + +end + + + +// asynchronous OE + +always @(oeb) +begin + if (oeb == 1) + oetri <= `teohz 1; + else + oetri <= `teolz 0; +end + +// *** SETUP / HOLD VIOLATIONS *** + +always @(noti2) +begin +$display("NOTICE : 020 : Data bus corruption"); + force d =18'bx; + #1; + release d; +end + +always @(noti1_0) +begin +$display("NOTICE : 010 : Byte write corruption"); + force bws = 2'bx; + #1; + release bws; +end + +always @(noti1_1) +begin +$display("NOTICE : 011 : Byte enable corruption"); + force we_b = 1'bx; + #1; + release we_b; +end + +always @(noti1_2) +begin +$display("NOTICE : 012 : CE1B corruption"); + force ce1b =1'bx; + #1; + release ce1b; +end + +always @(noti1_3) +begin +$display("NOTICE : 013 : CE2 corruption"); + force ce2 =1'bx; + #1; + release ce2; +end + +always @(noti1_4) +begin +$display("NOTICE : 014 : CE3B corruption"); + force ce3b =1'bx; + #1; + release ce3b; +end + +always @(noti1_5) +begin +$display("NOTICE : 015 : CENB corruption"); + force cenb =1'bx; + #1; + release cenb; +end + +always @(noti1_6) +begin +$display("NOTICE : 016 : ADV_LB corruption"); + force adv_lb = 1'bx; + #1; + release adv_lb; +end + +// synchronous functions from clk edge + +always @(posedge clk) +if (!cenb) +begin +#0.01; + // latch conditions on adv_lb + + if (adv_lb) + we_bl <= we_bl; + else + we_bl <= we_b; + + chipen_d <= chipen; + + + chipen_o <= chipen; + writestate_o <= writestate; + writestate_d <= writestate_o; + writebusb_o <= writebusb; + writebusb_d <= writebusb_o; + operation_o <= operation; + a_o <= a; + a_d <= a_o; + di = d; + + // execute previously pipelined fns + + if (lw) begin + loadwrite; + lw =0; + end + + if (bw) begin + burstwrite; + bw =0; + end + + // decode input/piplined state + + casex (operation_o) + 3'b0?? : turnoff; + 3'b101 : setlw; + 3'b111 : setbw; + 3'b100 : loadread; + 3'b110 : burstread; + default : unknown; // output unknown values and display an error message + endcase + + do <= `tco pipereg; + +end + +// *** task section *** + +task read; +begin + if (enable) cetri <= `tclz 0; + writetri <= `tchz 0; + do <= `tdoh 18'hx; + pipereg = mem[addreg]; +end +endtask + +task write; +begin + if (enable) cetri <= `tclz 0; + writeword = mem[addreg]; // set up a word to hold the data for the current location + /* overwrite the current word for the bytes being written to */ + if (!writebusb_d[1]) writeword[17:9] = di[17:9]; + if (!writebusb_d[0]) writeword[8:0] = di[8:0]; + writeword = writeword & writeword; //convert z to x states + mem[addreg] = writeword; // store the new word into the memory location + //writetri <= `tchz 1; // tristate the outputs +end +endtask + +task setlw; +begin + lw =1; + writetri <= `tchz 1; // tristate the outputs +end +endtask + +task setbw; +begin + bw =1; + writetri <= `tchz 1; // tristate the outputs +end +endtask + +task loadread; +begin + burstinit = a_o[0]; + addreg = a_o; + enable = 1; + read; +end +endtask + +task loadwrite; +begin + burstinit = a_d[0]; + addreg = a_d; + enable = 1; + write; +end +endtask + +task burstread; +begin + burst; + read; +end +endtask + +task burstwrite; +begin + burst; + write; +end +endtask + +task unknown; +begin + do = 18'bx; + // $display ("Unknown function: Operation = %b\n", operation); +end +endtask + +task turnoff; +begin + enable = 0; + cetri <= `tchz 1; + pipereg = 18'h0; +end +endtask + +task burst; +begin + if (burstinit == 0 || mode == 0) + begin + case (addreg[1:0]) + 2'b00: addreg[1:0] = 2'b01; + 2'b01: addreg[1:0] = 2'b10; + 2'b10: addreg[1:0] = 2'b11; + 2'b11: addreg[1:0] = 2'b00; + default: addreg[1:0] = 2'bxx; + endcase + end + else + begin + case (addreg[1:0]) + 2'b00: addreg[1:0] = 2'b11; + 2'b01: addreg[1:0] = 2'b00; + 2'b10: addreg[1:0] = 2'b01; + 2'b11: addreg[1:0] = 2'b10; + default: addreg[1:0] = 2'bxx; + endcase + end +end +endtask + +// IO checks + +specify +// specify the setup and hold checks + +// notifier will wipe memory as result is indeterminent + +$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier); + +// noti1 should make ip = 'bx; + +$setuphold(posedge clk, bws, `tas, `tah, noti1_0); + +$setuphold(posedge clk, we_b, `tas, `tah, noti1_1); +$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2); +$setuphold(posedge clk, ce2, `tas, `tah, noti1_3); +$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4); + +// noti2 should make d = 18'hxxxxx; + +$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2); + +// add extra tests here. + +$setuphold(posedge clk, cenb, `tas, `tah, noti1_5); +$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6); + +endspecify + +endmodule + + diff --git a/usrp2/fpga/models/CY7C1356C/readme.txt b/usrp2/fpga/models/CY7C1356C/readme.txt new file mode 100644 index 00000000..3578c80d --- /dev/null +++ b/usrp2/fpga/models/CY7C1356C/readme.txt @@ -0,0 +1,33 @@ +*************************** +Cypress Semiconductor +MPD Applications +Verilog model for NoBL SRAM CY7C1356 +Created: August 04, 2004 +Rev: 1.0 +*************************** + +This is the verilog model for the CY7C1356 along with the testbench and test vectors. + +Contact support@cypress.com if you have any questions. + +This directory has 4 files. including this readme. + +1)cy7c1356c.v -> Verilog model for CY7C1356c + +2)cy1356.inp -> Test Vector File used for testing the verilog model + +3)testbench.v -> Test bench used for testing the verilog model + + +COMPILING METHOD : +------------------ + + verilog +define+
+ + Ex: + verilog +define+sb133 CY7C1356c.v testbench.v + +VERIFIED WITH: +-------------- + +VERILOG-XL 2.2 \ No newline at end of file diff --git a/usrp2/fpga/models/CY7C1356C/testbench.v b/usrp2/fpga/models/CY7C1356C/testbench.v new file mode 100644 index 00000000..5dde89e6 --- /dev/null +++ b/usrp2/fpga/models/CY7C1356C/testbench.v @@ -0,0 +1,189 @@ +`timescale 1ns / 10ps + + +// +// CY7C1356 +// Simulatiom of Verilog model +// +// + +// +// test bench for US vector input +// +// + +// define speed 166MHz + +`define tx10 #6 +`define tx08 #4.8 +`define tx05 #3 +`define tx04 #2.4 +`define tx02 #1.2 + +/* +`define tx10 #4.0 // period +`define tx08 #3.2 //0.8 period +`define tx05 #2.0 //0.5 period 250MHZ +`define tx04 #1.6 //0.4 period +`define tx02 #0.8 //0.2 period + +`define tx10 #4.4 // period +`define tx08 #3.52 //0.8 period +`define tx05 #2.2 //0.5 period 225MHZ +`define tx04 #1.76 //0.4 period +`define tx02 #0.88 //0.2 period + +`define tx10 #5 // period +`define tx08 #4 //0.8 period +`define tx05 #2.5 //0.5 period 200MHZ +`define tx04 #2.0 //0.4 period +`define tx02 #1.0 //0.2 period +*/ + + +module rw_test; + +`define num_vectors 126 +`define impi {a[15:0],io[15:0],tsti[15:0],cenb,ce1b,ce2,ce3b,bweb,bwb,adv_lb} + + +reg [57:1] lsim_vectors [1:`num_vectors]; + + +reg clk; +reg adv_lb; +reg ce1b; //cs1b +reg ce2; //cs2 +reg ce3b; //cs3b +reg [1:0] bwb; +reg bweb; +reg oeb; +reg ftb; +reg mode; //lbob +reg cenb; //zz +reg tp42; //sclk +reg tp39; //se +reg tp38; //tm +reg [19:0] a; +reg [17:0] io; +reg [17:0] tsti; +reg vddq; +reg vssqr; +reg iosel; + + +wire [17:0] d = iosel ? io[17:0] : 18'bz; + +reg noti3; +reg strb,j; +integer vector,i; + + + +cy1356 testram ( d, clk, a, bwb, bweb, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode); + +initial +begin + $dumpfile("dumpfile.dump"); + $dumpvars(0,rw_test); +end + +initial +begin +io = 18'bz; +ftb = 1; +oeb = 0; +a[19:16] = 4'h0; +mode = 0; +strb = 0; +tp38 = 0; +tp39 = 0; +tp42 = 0; +`tx02; +forever `tx05 strb = ~strb; +end + +initial +begin +clk = 0; +forever `tx05 clk =~clk; +end + +initial + begin + + $readmemb("cy1356.inp", lsim_vectors); //load input vector file + + `impi = lsim_vectors[1]; //apply 1st test vector + + for (vector = 2; vector <= `num_vectors; vector = vector + 1) + @(posedge strb) + begin + + `impi = lsim_vectors[vector]; + + + + io[16:13] = io[07:04]; + io[12:09] = io[07:04]; + io[07:04] = io[03:00]; + io[03:00] = io[03:00]; + + io[17] = io[16] ^^ io[15] ^^ io[14] ^^ io[13] ^^ io[11] ^^ io[11] ^^ io[10] ^^ io[9]; + io[8] = io[7] ^^ io[6] ^^ io[5] ^^ io[4] ^^ io[3] ^^ io[2] ^^ io[1] ^^ io[0]; + + tsti[16:13] = tsti[07:04]; + tsti[12:09] = tsti[07:04]; + tsti[07:04] = tsti[03:00]; + tsti[03:00] = tsti[03:00]; + + tsti[17] = tsti[16] ^^ tsti[15] ^^ tsti[14] ^^ tsti[13] ^^ tsti[11] ^^ tsti[11] ^^ tsti[10] ^^ tsti[9]; + tsti[8] = tsti[7] ^^ tsti[6] ^^ tsti[5] ^^ tsti[4] ^^ tsti[3] ^^ tsti[2] ^^ tsti[1] ^^ tsti[0]; + + if (io === 18'hxxxxx) + iosel = `tx05 0; + else + iosel = `tx05 1; + + end + #15 $finish; // This prevents simulation beyond end of test patterns + end + +always@(posedge clk) +begin + + if (io !== 18'hxxxxx) //input cycle + begin + $display("NOTICE : 001 : line = %d OK",vector -1); + end + else //do the test + begin + if (d == tsti) + begin + $display("NOTICE : 002 : line = %d OK",vector -1); + end + else + begin + j =0; + for (i =0;i< 18; i=i+1) + begin + if(tsti[i] !== 1'bx) + begin + if (d[i] !== tsti[i]) j = 1; + end + else + j = 0; + end + if (j) + $display("ERROR *** : 003 : line = %d data = %b test = %b",vector -1,d,tsti); + else + $display("NOTICE : 003 : line = %d OK",vector -1); + end + end +end + +endmodule + + + + diff --git a/usrp2/fpga/models/FIFO_GENERATOR_V4_3.v b/usrp2/fpga/models/FIFO_GENERATOR_V4_3.v new file mode 100644 index 00000000..3489ee50 --- /dev/null +++ b/usrp2/fpga/models/FIFO_GENERATOR_V4_3.v @@ -0,0 +1,4093 @@ +/* + * $RDCfile: $ $Revision: 1.1.2.6 $ $Date: 2007/11/28 17:15:18 $ + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing theis design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard. Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * This copyright and support notice must be retained as part + * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. + * All rights reserved. + * + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V4_3.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v4_3.vhd + * | + * +-fifo_generator_v4_3_bhv_as + * | + * +-fifo_generator_v4_3_bhv_ss + * | + * +-fifo_generator_v4_3_bhv_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V4_3 +( + BACKUP, //not used + BACKUP_MARKER, //not used + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, //not used + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, //not used + INT_CLK, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + + SBITERR, + DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : not used in bhv model + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Not used + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Not used + * INT_CLK : Internal Clock + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /**************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; //not used + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; //not used + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; //not used + parameter C_FAMILY = "virtex2"; //not used in bhv model + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; //not used + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_INT_CLK = 0; //not used in bhv model + parameter C_HAS_MEMINIT_FILE = 0; //not used + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; //not used + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; //not used + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; //not used + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; //not used + parameter C_OPTIMIZATION_MODE = 0; //not used + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = 512; //not used in bhv model + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; //not used in bhv model + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; //not used in bhv model + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; //not used in bhv model + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; //not used in bhv model + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; //not used + parameter C_MSGON_VAL = 1; //not used + + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : + (C_IMPLEMENTATION_TYPE==1 ? 0 : + (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); + + /***************************************************************************** + * Declare Input and Output Ports + ****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + assign SBITERR = 1'b0; + assign DBITERR = 1'b0; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v4_3_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH + ) + gen_ss + ( + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v4_3_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v4_3_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v4_3_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_USE_DOUT_RST, + C_VALID_LOW, + C_UNDERFLOW_LOW + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = RST; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST) begin + if (RST) begin + EMPTY_P0_OUT_Q <= 1; + ALMOSTEMPTY_P0_OUT_Q <= 1; + end else begin + EMPTY_P0_OUT_Q <= EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST) begin + if (RST && (C_HAS_RST == 1) ) begin + DATA_COUNT_FWFT <= 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin + $display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + $finish; + end + end //initial + +endmodule //FIFO_GENERATOR_V4_3 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v4_3_bhv_ver_as + ( + WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID, + UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY + ); + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RST; + input WR_CLK; + input WR_EN; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + + // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 + // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) + // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 + // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 + parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR); + // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 0 + // 1 | 4 | C_RD_PNTR_WIDTH | 0 + // 1 | 2 | C_RD_PNTR_WIDTH | 1 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + parameter EXTRA_WORDS_DC = ( C_DEPTH_RATIO_RD > 2)? + 0:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The read pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + /* ORIGINAL CODE - Removed 10/24/07 jeo + //Amount of data stored in the FIFO scaled to read words + // (Do not include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Amount of data stored in the FIFO scaled to read words + // (Include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Not used in the code. + wire [31:0] num_read_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_fwft_dc : num_read_words_dc; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized = + num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft = + num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + //Used to calculate ideal_rd_count (RD_DATA_COUNT) + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_sized_fwft : num_read_words_sized; + */ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + + + + + + /************************** + * Write Data Count + *************************/ + /* ORIGINAL CODE - Removed 10/24/07 jeo + + //Calculate the Data Count value for the number of write words, when not + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + wire [31:0] num_write_words_dc = + (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH) + 1; + + //Calculate the Data Count value for the number of write words, when using + // First-Word Fall-Through with extra logic for Data Counts. This takes into + // consideration the number of words that are expected to be stored in the + // FWFT register stages (it always assumes they are filled). + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + //EXTRA_WORDS_DC is the number of words added to write_words due to FWFT. + wire [31:0] num_write_words_fwft_dc = + (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH) + 1) + EXTRA_WORDS_DC ; + + wire [31:0] num_write_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_write_words_fwft_dc : num_write_words_dc; + + + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized = + num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft = + num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i = C_USE_FWFT_DATA_COUNT? + num_write_words_sized_fwft:num_write_words_sized; + + */ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + //Internal reset signals + reg rd_rst_asreg =0; + reg rd_rst_asreg_d1 =0; + reg rd_rst_asreg_d2 =0; + reg rd_rst_reg =0; + reg rd_rst_d1 =0; + reg wr_rst_asreg =0; + reg wr_rst_asreg_d1 =0; + reg wr_rst_asreg_d2 =0; + reg wr_rst_reg =0; + reg wr_rst_d1 =0; + + wire rd_rst_comb; + wire rd_rst_i; + wire wr_rst_comb; + wire wr_rst_i; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + begin + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr]; + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + ideal_dout_d1 = 0 ; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //Outputs + assign ALMOST_EMPTY = ideal_almost_empty; + assign ALMOST_FULL = ideal_almost_full; + + //Dout may change behavior based on latency + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = ideal_rd_count; + + //Underflow may change behavior based on latency or active-low + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + + //Write acknowledge may be active low + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = ideal_wr_count; + + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + assign wr_rst_i = C_HAS_RST ? wr_rst_reg : 0; + assign rd_rst_i = C_HAS_RST ? rd_rst_reg : 0; + + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= 1'b0; + end else begin + wr_rst_asreg <= wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= wr_rst_asreg; + wr_rst_asreg_d2 <= wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= 1'b1; + end else begin + wr_rst_reg <= 1'b0; + end + end + + always @(posedge WR_CLK or posedge wr_rst_i) begin + if (wr_rst_i == 1'b1) begin + wr_rst_d1 <= 1'b1; + end else begin + wr_rst_d1 <= wr_rst_i; + end + end + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= 1'b0; + end else begin + rd_rst_asreg <= rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= rd_rst_asreg; + rd_rst_asreg_d2 <= rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= 1'b1; + end else begin + rd_rst_reg <= 1'b0; + end + end + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + valid_d1 <= valid_i; + end + end + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1 && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + ideal_dout_d1 <= ideal_dout; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + always @(posedge WR_CLK) begin + ideal_overflow <= WR_EN & ideal_full; + end + + always @(posedge RD_CLK) begin + ideal_underflow <= ideal_empty & RD_EN; + end + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= 0; + next_num_wr_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr_wrclk <= C_RD_DEPTH - 1; + ideal_wr_ack <= 0; + ideal_full <= C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= C_FULL_FLAGS_RST_VAL; + ideal_wr_count <= 0; + + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + prog_full_d <= C_FULL_FLAGS_RST_VAL; + + end else begin //wr_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (ideal_full == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + //With DEPTH-1 words in the FIFO, it is almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + //FIFO is really not close to full, so change flag status. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //This write is CAUSING the FIFO to go full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //Still 2 from full + ideal_full <= 1'b0; + //2 from full, and writing, so set almost_full + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //Not even close to full. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= 0; + + //Implied statements: + //ideal_empty <= ideal_empty; + //ideal_almost_empty <= ideal_almost_empty; + + //Check for full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) + ideal_full <= 1'b1; + else + ideal_full <= 1'b0; + + //Check for almost_full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1) + ideal_almost_full <= 1'b1; + else + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + end + + /********************************************************* + * Programmable FULL flags + *********************************************************/ + //Single Programmable Full Constant Threshold + if (C_PROG_FULL_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL; + end + + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL; + end + + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH; + prog_full_actual_thresh_negate = PROG_FULL_THRESH; + end + + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE; + end + end //C_PROG_FULL_TYPE + + if (num_write_words_pf==0) begin + prog_full_d <= 1'b0; + end else begin + if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + == prog_full_actual_thresh_assert-1) && WR_EN) begin + prog_full_d <= 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + >= prog_full_actual_thresh_assert) begin + prog_full_d <= 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + < prog_full_actual_thresh_negate) begin + prog_full_d <= 1'b0; + end + end + + if (wr_rst_d1==1 && wr_rst_i==0) begin + ideal_prog_full <= 0; + end else begin + ideal_prog_full <= prog_full_d; + end + num_wr_bits <= next_num_wr_bits; + rd_ptr_wrclk <= rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= 0; + next_num_rd_bits <= 0; + rd_ptr <= C_RD_DEPTH -1; + wr_ptr_rdclk <= C_WR_DEPTH -1; + if (C_USE_DOUT_RST == 1) begin + ideal_dout <= dout_reset_val; + end else begin + ideal_dout <= ideal_dout; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + ideal_rd_count <= 0; + + ideal_prog_empty <= 1'b1; + prog_empty_d <= 1; + + + end else begin //rd_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + // (Subtract 2 read-sized words when using Preload 0) + + //Single Programmable Empty Constant Threshold + if (C_PROG_EMPTY_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; + end + + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + + //Single Programmable Empty Constant Threshold + end else if (C_PROG_EMPTY_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; + + end + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; + end + end + + if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) + && RD_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + <= prog_empty_actual_thresh_assert) begin + prog_empty_d <= 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + > prog_empty_actual_thresh_negate) begin + prog_empty_d <= 1'b0; + end + + + ideal_prog_empty <= prog_empty_d; + num_rd_bits <= next_num_rd_bits; + wr_ptr_rdclk <= wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v4_3_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v4_3_bhv_ver_ss + ( + CLK, RST, SRST, DIN, WR_EN, RD_EN, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, + ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, + PROG_FULL, PROG_EMPTY + ); + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + //Inputs + input CLK; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_EN; + input RST; + input SRST; + input WR_EN; + + //Outputs + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output UNDERFLOW; + output WR_ACK; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire SRST; + wire WR_EN; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire UNDERFLOW; + wire WR_ACK; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + + //Internal reset signals + reg rst_asreg =0; + reg rst_asreg_d1 =0; + reg rst_asreg_d2 =0; + reg rst_reg =0; + reg rst_d1 =0; + wire rst_comb; + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + begin + ideal_dout <= memory[rd_ptr]; + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + assign ALMOST_EMPTY = ideal_almost_empty; + assign ALMOST_FULL = ideal_almost_full; + + //Dout may change behavior based on latency + assign ideal_dout_out= (C_USE_EMBEDDED_REG==1 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + + //Trim data count differently depending on set widths + always @(num_read_words) begin + if (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) begin + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else begin + DATA_COUNT = + num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + end //always + + //Underflow may change behavior based on latency or active-low + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + + + //Write acknowledge may be active low + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_comb = !rst_asreg_d2 && rst_asreg; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= 1'b0; + end else begin + rst_asreg <= rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= rst_asreg; + rst_asreg_d2 <= rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= 1'b1; + end else begin + rst_reg <= 1'b0; + end + end + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= 1'b0; + end else begin + valid_d1 <= valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1 && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + if (srst_i && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + ideal_dout_d1 <= ideal_dout; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + always @(posedge CLK) begin + ideal_overflow <= WR_EN & ideal_full; + ideal_underflow <= ideal_empty & RD_EN; + end + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= rst_i; + rst_qq <= rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + /******Initialize Read Domain Signals*********************************/ + if (C_MEMORY_TYPE == 1 && C_USE_DOUT_RST == 1) begin + ideal_dout <= dout_reset_val; + end + end + end //always + + always @(posedge CLK or posedge rst_i) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= 0; + ideal_full <= C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + if (C_MEMORY_TYPE != 1 && C_USE_DOUT_RST == 1) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + end else begin + if (srst_i) begin + // SRST is available only for Sync BRAM and Sync DRAM. + // Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= 0; + ideal_full <= 0; //'0' + ideal_almost_full <= 0; //'0' + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1 ) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + end + + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= 1; + + //FIFO is one from FULL and going FULL + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= 1; + + //2 from full, and writing, so set almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read will fail + ideal_valid <= 1'b0; + + //FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //This read will make FIFO go empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= 0; + + //Not near empty + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read unsuccessful + ideal_valid <= 1'b0; + + //Report empty condition + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + // No read + num_bits <= num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + // Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= num_read_words; + num_write_words_q <= num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge rst_i) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (rst_i) begin + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= 1'b1; + prog_full_d <= C_FULL_FLAGS_RST_VAL; + prog_empty_d <= 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + ideal_prog_full <= 1'b0; + ideal_prog_empty <= 1'b1; + prog_full_d <= 1'b0; + prog_empty_d <= 1'b1; + end + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (rst_q && !rst_i) begin + ideal_prog_full <= 1'b0; + prog_full_d <= 1'b0; + end else begin + ideal_prog_full <= prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v4_3_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v4_3_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + RD_EN, + FIFOEMPTY, + FIFODATA, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = C_HAS_RST ? RD_RST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= 1'b0; + else + ram_valid_i <= ram_valid_i; + end + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= 1'b0; + else + read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= 1'b1; + empty_q <= 1'b1; + end else begin + // rising clock edge + empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + empty_q <= empty_i; + end + end //always + + //Register RD_EN from user to calculate USERUNDERFLOW. + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + rd_en_q <= 1'b0; + end else begin + // rising clock edge + rd_en_q <= RD_EN; + end + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + begin + almost_empty_i <= 1'b1; + almost_empty_q <= 1'b1; + end + else // rising clock edge + begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) + begin + almost_empty_i <= FIFOEMPTY; + end + almost_empty_q <= empty_i; + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i && C_USE_DOUT_RST == 1) //asynchronous reset (active high) + USERDATA <= hexstr_conv(C_DOUT_RST_VAL); + else // rising clock edge + if (ram_regout_en) + USERDATA <= FIFODATA; + end //always + + + + + +endmodule diff --git a/usrp2/fpga/models/M24LC024B.v b/usrp2/fpga/models/M24LC024B.v new file mode 100644 index 00000000..45e04b45 --- /dev/null +++ b/usrp2/fpga/models/M24LC024B.v @@ -0,0 +1,459 @@ +// Modified 11/14/07 to simulate the 24lc024, which responds to the address pins + +// ******************************************************************************************************* +// ** ** +// ** M24LC024B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) ** +// ** ** +// ******************************************************************************************************* +// ** ** +// ** COPYRIGHT (c) 2003 YOUNG ENGINEERING ** +// ** ALL RIGHTS RESERVED ** +// ** ** +// ** THIS PROGRAM IS CONFIDENTIAL AND A TRADE SECRET OF YOUNG ENGINEERING. THE RECEIPT OR ** +// ** POSSESSION OF THIS PROGRAM DOES NOT CONVEY ANY RIGHTS TO REPRODUCE OR DISCLOSE ITS ** +// ** CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN ** +// ** PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING. ** +// ** ** +// ******************************************************************************************************* +// ** Revision : 1.1 ** +// ** Modified Date : 07/19/2004 ** +// ** Revision History: ** +// ** ** +// ** 02/01/2003: Initial design ** +// ** 07/19/2004: Fixed the timing checks and the open-drain modeling for SDA. ** +// ** ** +// ******************************************************************************************************* +// ** TABLE OF CONTENTS ** +// ******************************************************************************************************* +// **---------------------------------------------------------------------------------------------------** +// ** DECLARATIONS ** +// **---------------------------------------------------------------------------------------------------** +// **---------------------------------------------------------------------------------------------------** +// ** INITIALIZATION ** +// **---------------------------------------------------------------------------------------------------** +// **---------------------------------------------------------------------------------------------------** +// ** CORE LOGIC ** +// **---------------------------------------------------------------------------------------------------** +// ** 1.01: START Bit Detection ** +// ** 1.02: STOP Bit Detection ** +// ** 1.03: Input Shift Register ** +// ** 1.04: Input Bit Counter ** +// ** 1.05: Control Byte Register ** +// ** 1.06: Byte Address Register ** +// ** 1.07: Write Data Buffer ** +// ** 1.08: Acknowledge Generator ** +// ** 1.09: Acknowledge Detect ** +// ** 1.10: Write Cycle Timer ** +// ** 1.11: Write Cycle Processor ** +// ** 1.12: Read Data Multiplexor ** +// ** 1.13: Read Data Processor ** +// ** 1.14: SDA Data I/O Buffer ** +// ** ** +// **---------------------------------------------------------------------------------------------------** +// ** DEBUG LOGIC ** +// **---------------------------------------------------------------------------------------------------** +// ** 2.01: Memory Data Bytes ** +// ** 2.02: Write Data Buffer ** +// ** ** +// **---------------------------------------------------------------------------------------------------** +// ** TIMING CHECKS ** +// **---------------------------------------------------------------------------------------------------** +// ** ** +// ******************************************************************************************************* + + +`timescale 1ns/10ps + +module M24LC024B (A0, A1, A2, WP, SDA, SCL, RESET); + + input A0; // unconnected pin + input A1; // unconnected pin + input A2; // unconnected pin + + input WP; // write protect pin + + inout SDA; // serial data I/O + input SCL; // serial data clock + + input RESET; // system reset + + +// ******************************************************************************************************* +// ** DECLARATIONS ** +// ******************************************************************************************************* + + reg SDA_DO; // serial data - output + reg SDA_OE; // serial data - output enable + + wire SDA_DriveEnable; // serial data output enable + reg SDA_DriveEnableDlyd; // serial data output enable - delayed + + reg [03:00] BitCounter; // serial bit counter + + reg START_Rcvd; // START bit received flag + reg STOP_Rcvd; // STOP bit received flag + reg CTRL_Rcvd; // control byte received flag + reg ADDR_Rcvd; // byte address received flag + reg MACK_Rcvd; // master acknowledge received flag + + reg WrCycle; // memory write cycle + reg RdCycle; // memory read cycle + + reg [07:00] ShiftRegister; // input data shift register + + reg [07:00] ControlByte; // control byte register + wire RdWrBit; // read/write control bit + + reg [07:00] StartAddress; // memory access starting address + reg [02:00] PageAddress; // memory page address + + reg [07:00] WrDataByte [0:7]; // memory write data buffer + wire [07:00] RdDataByte; // memory read data + + reg [15:00] WrCounter; // write buffer counter + + reg [02:00] WrPointer; // write buffer pointer + reg [07:00] RdPointer; // read address pointer + + reg WriteActive; // memory write cycle active + + reg [07:00] MemoryBlock [0:255]; // EEPROM data memory array + + integer LoopIndex; // iterative loop index + + integer tAA; // timing parameter + integer tWC; // timing parameter + + +// ******************************************************************************************************* +// ** INITIALIZATION ** +// ******************************************************************************************************* + + initial tAA = 900; // SCL to SDA output delay + initial tWC = 5000000; // memory write cycle time + //initial tWC = 50000; // shortened memory write cycle time to speed up sims + + initial begin + SDA_DO = 0; + SDA_OE = 0; + end + + initial begin + START_Rcvd = 0; + STOP_Rcvd = 0; + CTRL_Rcvd = 0; + ADDR_Rcvd = 0; + MACK_Rcvd = 0; + end + + initial begin + BitCounter = 0; + ControlByte = 0; + end + + initial begin + WrCycle = 0; + RdCycle = 0; + + WriteActive = 0; + end + + +// ******************************************************************************************************* +// ** CORE LOGIC ** +// ******************************************************************************************************* +// ------------------------------------------------------------------------------------------------------- +// 1.01: START Bit Detection +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SDA) begin + if (SCL == 1) begin + START_Rcvd <= 1; + STOP_Rcvd <= 0; + CTRL_Rcvd <= 0; + ADDR_Rcvd <= 0; + MACK_Rcvd <= 0; + + WrCycle <= #1 0; + RdCycle <= #1 0; + + BitCounter <= 0; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.02: STOP Bit Detection +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SDA) begin + if (SCL == 1) begin + START_Rcvd <= 0; + STOP_Rcvd <= 1; + CTRL_Rcvd <= 0; + ADDR_Rcvd <= 0; + MACK_Rcvd <= 0; + + WrCycle <= #1 0; + RdCycle <= #1 0; + + BitCounter <= 10; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.03: Input Shift Register +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + ShiftRegister[00] <= SDA; + ShiftRegister[01] <= ShiftRegister[00]; + ShiftRegister[02] <= ShiftRegister[01]; + ShiftRegister[03] <= ShiftRegister[02]; + ShiftRegister[04] <= ShiftRegister[03]; + ShiftRegister[05] <= ShiftRegister[04]; + ShiftRegister[06] <= ShiftRegister[05]; + ShiftRegister[07] <= ShiftRegister[06]; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.04: Input Bit Counter +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + if (BitCounter < 10) BitCounter <= BitCounter + 1; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.05: Control Byte Register +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (START_Rcvd & (BitCounter == 8)) begin + if (!WriteActive & (ShiftRegister[07:04] == 4'b1010) + & (ShiftRegister[3:1] == {A2,A1,A0})) begin + if (ShiftRegister[00] == 0) WrCycle <= 1; + if (ShiftRegister[00] == 1) RdCycle <= 1; + + ControlByte <= ShiftRegister[07:00]; + + CTRL_Rcvd <= 1; + end + + START_Rcvd <= 0; + end + end + + assign RdWrBit = ControlByte[00]; + +// ------------------------------------------------------------------------------------------------------- +// 1.06: Byte Address Register +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (CTRL_Rcvd & (BitCounter == 8)) begin + if (RdWrBit == 0) begin + StartAddress <= ShiftRegister[07:00]; + RdPointer <= ShiftRegister[07:00]; + + ADDR_Rcvd <= 1; + end + + WrCounter <= 0; + WrPointer <= 0; + + CTRL_Rcvd <= 0; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.07: Write Data Buffer +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (ADDR_Rcvd & (BitCounter == 8)) begin + if ((WP == 0) & (RdWrBit == 0)) begin + WrDataByte[WrPointer] <= ShiftRegister[07:00]; + + WrCounter <= WrCounter + 1; + WrPointer <= WrPointer + 1; + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.08: Acknowledge Generator +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (!WriteActive) begin + if (BitCounter == 8) begin + if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin + SDA_DO <= 0; + SDA_OE <= 1; + end + end + if (BitCounter == 9) begin + BitCounter <= 0; + + if (!RdCycle) begin + SDA_DO <= 0; + SDA_OE <= 0; + end + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.09: Acknowledge Detect +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + if (RdCycle & (BitCounter == 8)) begin + if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1; + end + end + + always @(negedge SCL) MACK_Rcvd <= 0; + +// ------------------------------------------------------------------------------------------------------- +// 1.10: Write Cycle Timer +// ------------------------------------------------------------------------------------------------------- + + always @(posedge STOP_Rcvd) begin + if (WrCycle & (WP == 0) & (WrCounter > 0)) begin + WriteActive = 1; + #(tWC); + WriteActive = 0; + end + end + + always @(posedge STOP_Rcvd) begin + #(1.0); + STOP_Rcvd = 0; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.11: Write Cycle Processor +// ------------------------------------------------------------------------------------------------------- + + always @(posedge WriteActive) begin + for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin + PageAddress = StartAddress[02:00] + LoopIndex; + + MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]]; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.12: Read Data Multiplexor +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (BitCounter == 8) begin + if (WrCycle & ADDR_Rcvd) begin + RdPointer <= StartAddress + WrPointer + 1; + end + if (RdCycle) begin + RdPointer <= RdPointer + 1; + end + end + end + + assign RdDataByte = MemoryBlock[RdPointer[07:00]]; + +// ------------------------------------------------------------------------------------------------------- +// 1.13: Read Data Processor +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (RdCycle) begin + if (BitCounter == 8) begin + SDA_DO <= 0; + SDA_OE <= 0; + end + else if (BitCounter == 9) begin + SDA_DO <= RdDataByte[07]; + + if (MACK_Rcvd) SDA_OE <= 1; + end + else begin + SDA_DO <= RdDataByte[7-BitCounter]; + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.14: SDA Data I/O Buffer +// ------------------------------------------------------------------------------------------------------- + + bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd); + + assign SDA_DriveEnable = !SDA_DO & SDA_OE; + always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable; + + +// ******************************************************************************************************* +// ** DEBUG LOGIC ** +// ******************************************************************************************************* +// ------------------------------------------------------------------------------------------------------- +// 2.01: Memory Data Bytes +// ------------------------------------------------------------------------------------------------------- + + wire [07:00] MemoryByte00 = MemoryBlock[00]; + wire [07:00] MemoryByte01 = MemoryBlock[01]; + wire [07:00] MemoryByte02 = MemoryBlock[02]; + wire [07:00] MemoryByte03 = MemoryBlock[03]; + wire [07:00] MemoryByte04 = MemoryBlock[04]; + wire [07:00] MemoryByte05 = MemoryBlock[05]; + wire [07:00] MemoryByte06 = MemoryBlock[06]; + wire [07:00] MemoryByte07 = MemoryBlock[07]; + + wire [07:00] MemoryByte08 = MemoryBlock[08]; + wire [07:00] MemoryByte09 = MemoryBlock[09]; + wire [07:00] MemoryByte0A = MemoryBlock[10]; + wire [07:00] MemoryByte0B = MemoryBlock[11]; + wire [07:00] MemoryByte0C = MemoryBlock[12]; + wire [07:00] MemoryByte0D = MemoryBlock[13]; + wire [07:00] MemoryByte0E = MemoryBlock[14]; + wire [07:00] MemoryByte0F = MemoryBlock[15]; + +// ------------------------------------------------------------------------------------------------------- +// 2.02: Write Data Buffer +// ------------------------------------------------------------------------------------------------------- + + wire [07:00] WriteData_0 = WrDataByte[00]; + wire [07:00] WriteData_1 = WrDataByte[01]; + wire [07:00] WriteData_2 = WrDataByte[02]; + wire [07:00] WriteData_3 = WrDataByte[03]; + wire [07:00] WriteData_4 = WrDataByte[04]; + wire [07:00] WriteData_5 = WrDataByte[05]; + wire [07:00] WriteData_6 = WrDataByte[06]; + wire [07:00] WriteData_7 = WrDataByte[07]; + + +// ******************************************************************************************************* +// ** TIMING CHECKS ** +// ******************************************************************************************************* + + wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0); + + specify + specparam + tHI = 600, // SCL pulse width - high + tLO = 1300, // SCL pulse width - low + tSU_STA = 600, // SCL to SDA setup time + tHD_STA = 600, // SCL to SDA hold time + tSU_DAT = 100, // SDA to SCL setup time + tSU_STO = 600; // SCL to SDA setup time + + $width (posedge SCL, tHI); + $width (negedge SCL, tLO); + + $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA); + $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT); + $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO); + + $hold (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA); + endspecify + +endmodule diff --git a/usrp2/fpga/models/M24LC02B.v b/usrp2/fpga/models/M24LC02B.v new file mode 100644 index 00000000..4d9e2c6e --- /dev/null +++ b/usrp2/fpga/models/M24LC02B.v @@ -0,0 +1,455 @@ +// ******************************************************************************************************* +// ** ** +// ** M24LC02B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) ** +// ** ** +// ******************************************************************************************************* +// ** ** +// ** COPYRIGHT (c) 2003 YOUNG ENGINEERING ** +// ** ALL RIGHTS RESERVED ** +// ** ** +// ** THIS PROGRAM IS CONFIDENTIAL AND A TRADE SECRET OF YOUNG ENGINEERING. THE RECEIPT OR ** +// ** POSSESSION OF THIS PROGRAM DOES NOT CONVEY ANY RIGHTS TO REPRODUCE OR DISCLOSE ITS ** +// ** CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY DESCRIBE, IN WHOLE OR IN ** +// ** PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING. ** +// ** ** +// ******************************************************************************************************* +// ** Revision : 1.1 ** +// ** Modified Date : 07/19/2004 ** +// ** Revision History: ** +// ** ** +// ** 02/01/2003: Initial design ** +// ** 07/19/2004: Fixed the timing checks and the open-drain modeling for SDA. ** +// ** ** +// ******************************************************************************************************* +// ** TABLE OF CONTENTS ** +// ******************************************************************************************************* +// **---------------------------------------------------------------------------------------------------** +// ** DECLARATIONS ** +// **---------------------------------------------------------------------------------------------------** +// **---------------------------------------------------------------------------------------------------** +// ** INITIALIZATION ** +// **---------------------------------------------------------------------------------------------------** +// **---------------------------------------------------------------------------------------------------** +// ** CORE LOGIC ** +// **---------------------------------------------------------------------------------------------------** +// ** 1.01: START Bit Detection ** +// ** 1.02: STOP Bit Detection ** +// ** 1.03: Input Shift Register ** +// ** 1.04: Input Bit Counter ** +// ** 1.05: Control Byte Register ** +// ** 1.06: Byte Address Register ** +// ** 1.07: Write Data Buffer ** +// ** 1.08: Acknowledge Generator ** +// ** 1.09: Acknowledge Detect ** +// ** 1.10: Write Cycle Timer ** +// ** 1.11: Write Cycle Processor ** +// ** 1.12: Read Data Multiplexor ** +// ** 1.13: Read Data Processor ** +// ** 1.14: SDA Data I/O Buffer ** +// ** ** +// **---------------------------------------------------------------------------------------------------** +// ** DEBUG LOGIC ** +// **---------------------------------------------------------------------------------------------------** +// ** 2.01: Memory Data Bytes ** +// ** 2.02: Write Data Buffer ** +// ** ** +// **---------------------------------------------------------------------------------------------------** +// ** TIMING CHECKS ** +// **---------------------------------------------------------------------------------------------------** +// ** ** +// ******************************************************************************************************* + + +`timescale 1ns/10ps + +module M24LC02B (A0, A1, A2, WP, SDA, SCL, RESET); + + input A0; // unconnected pin + input A1; // unconnected pin + input A2; // unconnected pin + + input WP; // write protect pin + + inout SDA; // serial data I/O + input SCL; // serial data clock + + input RESET; // system reset + + +// ******************************************************************************************************* +// ** DECLARATIONS ** +// ******************************************************************************************************* + + reg SDA_DO; // serial data - output + reg SDA_OE; // serial data - output enable + + wire SDA_DriveEnable; // serial data output enable + reg SDA_DriveEnableDlyd; // serial data output enable - delayed + + reg [03:00] BitCounter; // serial bit counter + + reg START_Rcvd; // START bit received flag + reg STOP_Rcvd; // STOP bit received flag + reg CTRL_Rcvd; // control byte received flag + reg ADDR_Rcvd; // byte address received flag + reg MACK_Rcvd; // master acknowledge received flag + + reg WrCycle; // memory write cycle + reg RdCycle; // memory read cycle + + reg [07:00] ShiftRegister; // input data shift register + + reg [07:00] ControlByte; // control byte register + wire RdWrBit; // read/write control bit + + reg [07:00] StartAddress; // memory access starting address + reg [02:00] PageAddress; // memory page address + + reg [07:00] WrDataByte [0:7]; // memory write data buffer + wire [07:00] RdDataByte; // memory read data + + reg [15:00] WrCounter; // write buffer counter + + reg [02:00] WrPointer; // write buffer pointer + reg [07:00] RdPointer; // read address pointer + + reg WriteActive; // memory write cycle active + + reg [07:00] MemoryBlock [0:255]; // EEPROM data memory array + + integer LoopIndex; // iterative loop index + + integer tAA; // timing parameter + integer tWC; // timing parameter + + +// ******************************************************************************************************* +// ** INITIALIZATION ** +// ******************************************************************************************************* + + initial tAA = 900; // SCL to SDA output delay + initial tWC = 5000000; // memory write cycle time + + initial begin + SDA_DO = 0; + SDA_OE = 0; + end + + initial begin + START_Rcvd = 0; + STOP_Rcvd = 0; + CTRL_Rcvd = 0; + ADDR_Rcvd = 0; + MACK_Rcvd = 0; + end + + initial begin + BitCounter = 0; + ControlByte = 0; + end + + initial begin + WrCycle = 0; + RdCycle = 0; + + WriteActive = 0; + end + + +// ******************************************************************************************************* +// ** CORE LOGIC ** +// ******************************************************************************************************* +// ------------------------------------------------------------------------------------------------------- +// 1.01: START Bit Detection +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SDA) begin + if (SCL == 1) begin + START_Rcvd <= 1; + STOP_Rcvd <= 0; + CTRL_Rcvd <= 0; + ADDR_Rcvd <= 0; + MACK_Rcvd <= 0; + + WrCycle <= #1 0; + RdCycle <= #1 0; + + BitCounter <= 0; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.02: STOP Bit Detection +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SDA) begin + if (SCL == 1) begin + START_Rcvd <= 0; + STOP_Rcvd <= 1; + CTRL_Rcvd <= 0; + ADDR_Rcvd <= 0; + MACK_Rcvd <= 0; + + WrCycle <= #1 0; + RdCycle <= #1 0; + + BitCounter <= 10; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.03: Input Shift Register +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + ShiftRegister[00] <= SDA; + ShiftRegister[01] <= ShiftRegister[00]; + ShiftRegister[02] <= ShiftRegister[01]; + ShiftRegister[03] <= ShiftRegister[02]; + ShiftRegister[04] <= ShiftRegister[03]; + ShiftRegister[05] <= ShiftRegister[04]; + ShiftRegister[06] <= ShiftRegister[05]; + ShiftRegister[07] <= ShiftRegister[06]; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.04: Input Bit Counter +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + if (BitCounter < 10) BitCounter <= BitCounter + 1; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.05: Control Byte Register +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (START_Rcvd & (BitCounter == 8)) begin + if (!WriteActive & (ShiftRegister[07:04] == 4'b1010)) begin + if (ShiftRegister[00] == 0) WrCycle <= 1; + if (ShiftRegister[00] == 1) RdCycle <= 1; + + ControlByte <= ShiftRegister[07:00]; + + CTRL_Rcvd <= 1; + end + + START_Rcvd <= 0; + end + end + + assign RdWrBit = ControlByte[00]; + +// ------------------------------------------------------------------------------------------------------- +// 1.06: Byte Address Register +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (CTRL_Rcvd & (BitCounter == 8)) begin + if (RdWrBit == 0) begin + StartAddress <= ShiftRegister[07:00]; + RdPointer <= ShiftRegister[07:00]; + + ADDR_Rcvd <= 1; + end + + WrCounter <= 0; + WrPointer <= 0; + + CTRL_Rcvd <= 0; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.07: Write Data Buffer +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (ADDR_Rcvd & (BitCounter == 8)) begin + if ((WP == 0) & (RdWrBit == 0)) begin + WrDataByte[WrPointer] <= ShiftRegister[07:00]; + + WrCounter <= WrCounter + 1; + WrPointer <= WrPointer + 1; + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.08: Acknowledge Generator +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (!WriteActive) begin + if (BitCounter == 8) begin + if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin + SDA_DO <= 0; + SDA_OE <= 1; + end + end + if (BitCounter == 9) begin + BitCounter <= 0; + + if (!RdCycle) begin + SDA_DO <= 0; + SDA_OE <= 0; + end + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.09: Acknowledge Detect +// ------------------------------------------------------------------------------------------------------- + + always @(posedge SCL) begin + if (RdCycle & (BitCounter == 8)) begin + if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1; + end + end + + always @(negedge SCL) MACK_Rcvd <= 0; + +// ------------------------------------------------------------------------------------------------------- +// 1.10: Write Cycle Timer +// ------------------------------------------------------------------------------------------------------- + + always @(posedge STOP_Rcvd) begin + if (WrCycle & (WP == 0) & (WrCounter > 0)) begin + WriteActive = 1; + #(tWC); + WriteActive = 0; + end + end + + always @(posedge STOP_Rcvd) begin + #(1.0); + STOP_Rcvd = 0; + end + +// ------------------------------------------------------------------------------------------------------- +// 1.11: Write Cycle Processor +// ------------------------------------------------------------------------------------------------------- + + always @(posedge WriteActive) begin + for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin + PageAddress = StartAddress[02:00] + LoopIndex; + + MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]]; + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.12: Read Data Multiplexor +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (BitCounter == 8) begin + if (WrCycle & ADDR_Rcvd) begin + RdPointer <= StartAddress + WrPointer + 1; + end + if (RdCycle) begin + RdPointer <= RdPointer + 1; + end + end + end + + assign RdDataByte = MemoryBlock[RdPointer[07:00]]; + +// ------------------------------------------------------------------------------------------------------- +// 1.13: Read Data Processor +// ------------------------------------------------------------------------------------------------------- + + always @(negedge SCL) begin + if (RdCycle) begin + if (BitCounter == 8) begin + SDA_DO <= 0; + SDA_OE <= 0; + end + else if (BitCounter == 9) begin + SDA_DO <= RdDataByte[07]; + + if (MACK_Rcvd) SDA_OE <= 1; + end + else begin + SDA_DO <= RdDataByte[7-BitCounter]; + end + end + end + +// ------------------------------------------------------------------------------------------------------- +// 1.14: SDA Data I/O Buffer +// ------------------------------------------------------------------------------------------------------- + + bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd); + + assign SDA_DriveEnable = !SDA_DO & SDA_OE; + always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable; + + +// ******************************************************************************************************* +// ** DEBUG LOGIC ** +// ******************************************************************************************************* +// ------------------------------------------------------------------------------------------------------- +// 2.01: Memory Data Bytes +// ------------------------------------------------------------------------------------------------------- + + wire [07:00] MemoryByte00 = MemoryBlock[00]; + wire [07:00] MemoryByte01 = MemoryBlock[01]; + wire [07:00] MemoryByte02 = MemoryBlock[02]; + wire [07:00] MemoryByte03 = MemoryBlock[03]; + wire [07:00] MemoryByte04 = MemoryBlock[04]; + wire [07:00] MemoryByte05 = MemoryBlock[05]; + wire [07:00] MemoryByte06 = MemoryBlock[06]; + wire [07:00] MemoryByte07 = MemoryBlock[07]; + + wire [07:00] MemoryByte08 = MemoryBlock[08]; + wire [07:00] MemoryByte09 = MemoryBlock[09]; + wire [07:00] MemoryByte0A = MemoryBlock[10]; + wire [07:00] MemoryByte0B = MemoryBlock[11]; + wire [07:00] MemoryByte0C = MemoryBlock[12]; + wire [07:00] MemoryByte0D = MemoryBlock[13]; + wire [07:00] MemoryByte0E = MemoryBlock[14]; + wire [07:00] MemoryByte0F = MemoryBlock[15]; + +// ------------------------------------------------------------------------------------------------------- +// 2.02: Write Data Buffer +// ------------------------------------------------------------------------------------------------------- + + wire [07:00] WriteData_0 = WrDataByte[00]; + wire [07:00] WriteData_1 = WrDataByte[01]; + wire [07:00] WriteData_2 = WrDataByte[02]; + wire [07:00] WriteData_3 = WrDataByte[03]; + wire [07:00] WriteData_4 = WrDataByte[04]; + wire [07:00] WriteData_5 = WrDataByte[05]; + wire [07:00] WriteData_6 = WrDataByte[06]; + wire [07:00] WriteData_7 = WrDataByte[07]; + + +// ******************************************************************************************************* +// ** TIMING CHECKS ** +// ******************************************************************************************************* + + wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0); + + specify + specparam + tHI = 600, // SCL pulse width - high + tLO = 1300, // SCL pulse width - low + tSU_STA = 600, // SCL to SDA setup time + tHD_STA = 600, // SCL to SDA hold time + tSU_DAT = 100, // SDA to SCL setup time + tSU_STO = 600; // SCL to SDA setup time + + $width (posedge SCL, tHI); + $width (negedge SCL, tLO); + + $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA); + $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT); + $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO); + + $hold (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA); + endspecify + +endmodule diff --git a/usrp2/fpga/models/MULT18X18S.v b/usrp2/fpga/models/MULT18X18S.v new file mode 100644 index 00000000..5d39eeaa --- /dev/null +++ b/usrp2/fpga/models/MULT18X18S.v @@ -0,0 +1,20 @@ + +// Model of the Xilinx mult18x18s for signed 18x18 bit multiplies, +// As in the Spartan 3 series + +module MULT18X18S + (output reg signed [35:0] P, + input signed [17:0] A, + input signed [17:0] B, + input C, // Clock + input CE, // Clock Enable + input R // Synchronous Reset + ); + + always @(posedge C) + if(R) + P <= 36'sd0; + else if(CE) + P <= A * B; + +endmodule // MULT18X18S diff --git a/usrp2/fpga/models/RAMB16_S36_S36.v b/usrp2/fpga/models/RAMB16_S36_S36.v new file mode 100644 index 00000000..f1a92c7c --- /dev/null +++ b/usrp2/fpga/models/RAMB16_S36_S36.v @@ -0,0 +1,2194 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S36_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DOA; + output [3:0] DOPA; + reg [31:0] doa_out; + reg [3:0] dopa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15, doa_out16, doa_out17, doa_out18, doa_out19, doa_out20, doa_out21, doa_out22, doa_out23, doa_out24, doa_out25, doa_out26, doa_out27, doa_out28, doa_out29, doa_out30, doa_out31; + wire dopa0_out, dopa1_out, dopa2_out, dopa3_out; + + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA, CLKA, WEA, SSRA; + + output [31:0] DOB; + output [3:0] DOPB; + reg [31:0] dob_out; + reg [3:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; + wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; + + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [31:0] dia_int; + wire [3:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[31:0]; + assign dopa_out = INIT_A[35:32]; + assign dob_out = INIT_B[31:0]; + assign dopb_out = INIT_B[35:32]; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_doa_out8 (doa_out8, doa_out[8]); + buf b_doa_out9 (doa_out9, doa_out[9]); + buf b_doa_out10 (doa_out10, doa_out[10]); + buf b_doa_out11 (doa_out11, doa_out[11]); + buf b_doa_out12 (doa_out12, doa_out[12]); + buf b_doa_out13 (doa_out13, doa_out[13]); + buf b_doa_out14 (doa_out14, doa_out[14]); + buf b_doa_out15 (doa_out15, doa_out[15]); + buf b_doa_out16 (doa_out16, doa_out[16]); + buf b_doa_out17 (doa_out17, doa_out[17]); + buf b_doa_out18 (doa_out18, doa_out[18]); + buf b_doa_out19 (doa_out19, doa_out[19]); + buf b_doa_out20 (doa_out20, doa_out[20]); + buf b_doa_out21 (doa_out21, doa_out[21]); + buf b_doa_out22 (doa_out22, doa_out[22]); + buf b_doa_out23 (doa_out23, doa_out[23]); + buf b_doa_out24 (doa_out24, doa_out[24]); + buf b_doa_out25 (doa_out25, doa_out[25]); + buf b_doa_out26 (doa_out26, doa_out[26]); + buf b_doa_out27 (doa_out27, doa_out[27]); + buf b_doa_out28 (doa_out28, doa_out[28]); + buf b_doa_out29 (doa_out29, doa_out[29]); + buf b_doa_out30 (doa_out30, doa_out[30]); + buf b_doa_out31 (doa_out31, doa_out[31]); + buf b_dopa_out0 (dopa_out0, dopa_out[0]); + buf b_dopa_out1 (dopa_out1, dopa_out[1]); + buf b_dopa_out2 (dopa_out2, dopa_out[2]); + buf b_dopa_out3 (dopa_out3, dopa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dob_out16 (dob_out16, dob_out[16]); + buf b_dob_out17 (dob_out17, dob_out[17]); + buf b_dob_out18 (dob_out18, dob_out[18]); + buf b_dob_out19 (dob_out19, dob_out[19]); + buf b_dob_out20 (dob_out20, dob_out[20]); + buf b_dob_out21 (dob_out21, dob_out[21]); + buf b_dob_out22 (dob_out22, dob_out[22]); + buf b_dob_out23 (dob_out23, dob_out[23]); + buf b_dob_out24 (dob_out24, dob_out[24]); + buf b_dob_out25 (dob_out25, dob_out[25]); + buf b_dob_out26 (dob_out26, dob_out[26]); + buf b_dob_out27 (dob_out27, dob_out[27]); + buf b_dob_out28 (dob_out28, dob_out[28]); + buf b_dob_out29 (dob_out29, dob_out[29]); + buf b_dob_out30 (dob_out30, dob_out[30]); + buf b_dob_out31 (dob_out31, dob_out[31]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + buf b_dopb_out2 (dopb_out2, dopb_out[2]); + buf b_dopb_out3 (dopb_out3, dopb_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_doa8 (DOA[8], doa_out8); + buf b_doa9 (DOA[9], doa_out9); + buf b_doa10 (DOA[10], doa_out10); + buf b_doa11 (DOA[11], doa_out11); + buf b_doa12 (DOA[12], doa_out12); + buf b_doa13 (DOA[13], doa_out13); + buf b_doa14 (DOA[14], doa_out14); + buf b_doa15 (DOA[15], doa_out15); + buf b_doa16 (DOA[16], doa_out16); + buf b_doa17 (DOA[17], doa_out17); + buf b_doa18 (DOA[18], doa_out18); + buf b_doa19 (DOA[19], doa_out19); + buf b_doa20 (DOA[20], doa_out20); + buf b_doa21 (DOA[21], doa_out21); + buf b_doa22 (DOA[22], doa_out22); + buf b_doa23 (DOA[23], doa_out23); + buf b_doa24 (DOA[24], doa_out24); + buf b_doa25 (DOA[25], doa_out25); + buf b_doa26 (DOA[26], doa_out26); + buf b_doa27 (DOA[27], doa_out27); + buf b_doa28 (DOA[28], doa_out28); + buf b_doa29 (DOA[29], doa_out29); + buf b_doa30 (DOA[30], doa_out30); + buf b_doa31 (DOA[31], doa_out31); + buf b_dopa0 (DOPA[0], dopa_out0); + buf b_dopa1 (DOPA[1], dopa_out1); + buf b_dopa2 (DOPA[2], dopa_out2); + buf b_dopa3 (DOPA[3], dopa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dob16 (DOB[16], dob_out16); + buf b_dob17 (DOB[17], dob_out17); + buf b_dob18 (DOB[18], dob_out18); + buf b_dob19 (DOB[19], dob_out19); + buf b_dob20 (DOB[20], dob_out20); + buf b_dob21 (DOB[21], dob_out21); + buf b_dob22 (DOB[22], dob_out22); + buf b_dob23 (DOB[23], dob_out23); + buf b_dob24 (DOB[24], dob_out24); + buf b_dob25 (DOB[25], dob_out25); + buf b_dob26 (DOB[26], dob_out26); + buf b_dob27 (DOB[27], dob_out27); + buf b_dob28 (DOB[28], dob_out28); + buf b_dob29 (DOB[29], dob_out29); + buf b_dob30 (DOB[30], dob_out30); + buf b_dob31 (DOB[31], dob_out31); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + buf b_dopb2 (DOPB[2], dopb_out2); + buf b_dopb3 (DOPB[3], dopb_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dia_8 (dia_int[8], DIA[8]); + buf b_dia_9 (dia_int[9], DIA[9]); + buf b_dia_10 (dia_int[10], DIA[10]); + buf b_dia_11 (dia_int[11], DIA[11]); + buf b_dia_12 (dia_int[12], DIA[12]); + buf b_dia_13 (dia_int[13], DIA[13]); + buf b_dia_14 (dia_int[14], DIA[14]); + buf b_dia_15 (dia_int[15], DIA[15]); + buf b_dia_16 (dia_int[16], DIA[16]); + buf b_dia_17 (dia_int[17], DIA[17]); + buf b_dia_18 (dia_int[18], DIA[18]); + buf b_dia_19 (dia_int[19], DIA[19]); + buf b_dia_20 (dia_int[20], DIA[20]); + buf b_dia_21 (dia_int[21], DIA[21]); + buf b_dia_22 (dia_int[22], DIA[22]); + buf b_dia_23 (dia_int[23], DIA[23]); + buf b_dia_24 (dia_int[24], DIA[24]); + buf b_dia_25 (dia_int[25], DIA[25]); + buf b_dia_26 (dia_int[26], DIA[26]); + buf b_dia_27 (dia_int[27], DIA[27]); + buf b_dia_28 (dia_int[28], DIA[28]); + buf b_dia_29 (dia_int[29], DIA[29]); + buf b_dia_30 (dia_int[30], DIA[30]); + buf b_dia_31 (dia_int[31], DIA[31]); + buf b_dipa_0 (dipa_int[0], DIPA[0]); + buf b_dipa_1 (dipa_int[1], DIPA[1]); + buf b_dipa_2 (dipa_int[2], DIPA[2]); + buf b_dipa_3 (dipa_int[3], DIPA[3]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dib_16 (dib_int[16], DIB[16]); + buf b_dib_17 (dib_int[17], DIB[17]); + buf b_dib_18 (dib_int[18], DIB[18]); + buf b_dib_19 (dib_int[19], DIB[19]); + buf b_dib_20 (dib_int[20], DIB[20]); + buf b_dib_21 (dib_int[21], DIB[21]); + buf b_dib_22 (dib_int[22], DIB[22]); + buf b_dib_23 (dib_int[23], DIB[23]); + buf b_dib_24 (dib_int[24], DIB[24]); + buf b_dib_25 (dib_int[25], DIB[25]); + buf b_dib_26 (dib_int[26], DIB[26]); + buf b_dib_27 (dib_int[27], DIB[27]); + buf b_dib_28 (dib_int[28], DIB[28]); + buf b_dib_29 (dib_int[29], DIB[29]); + buf b_dib_30 (dib_int[30], DIB[30]); + buf b_dib_31 (dib_int[31], DIB[31]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_dipb_2 (dipb_int[2], DIPB[2]); + buf b_dipb_3 (dipb_int[3], DIPB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 32; + assign data_addra_reg = addra_reg * 32; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + assign parity_addra_int = 16384 + addra_int * 4; + assign parity_addra_reg = 16384 + addra_reg * 4; + assign parity_addrb_int = 16384 + addrb_int * 4; + assign parity_addrb_reg = 16384 + addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 32'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dob_out <= 32'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 32'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dob_out <= 32'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 32'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dob_out <= 32'bX; + end + data_collision_b_a[0] <= 0; + end + + + // Parity + always @(posedge memory_collision) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_a_b) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_reg + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_b_a) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 4'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 4'bX; + end + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dopb_out <= 4'bX; + end + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + doa_out[4] <= SRVAL_A[4]; + doa_out[5] <= SRVAL_A[5]; + doa_out[6] <= SRVAL_A[6]; + doa_out[7] <= SRVAL_A[7]; + doa_out[8] <= SRVAL_A[8]; + doa_out[9] <= SRVAL_A[9]; + doa_out[10] <= SRVAL_A[10]; + doa_out[11] <= SRVAL_A[11]; + doa_out[12] <= SRVAL_A[12]; + doa_out[13] <= SRVAL_A[13]; + doa_out[14] <= SRVAL_A[14]; + doa_out[15] <= SRVAL_A[15]; + doa_out[16] <= SRVAL_A[16]; + doa_out[17] <= SRVAL_A[17]; + doa_out[18] <= SRVAL_A[18]; + doa_out[19] <= SRVAL_A[19]; + doa_out[20] <= SRVAL_A[20]; + doa_out[21] <= SRVAL_A[21]; + doa_out[22] <= SRVAL_A[22]; + doa_out[23] <= SRVAL_A[23]; + doa_out[24] <= SRVAL_A[24]; + doa_out[25] <= SRVAL_A[25]; + doa_out[26] <= SRVAL_A[26]; + doa_out[27] <= SRVAL_A[27]; + doa_out[28] <= SRVAL_A[28]; + doa_out[29] <= SRVAL_A[29]; + doa_out[30] <= SRVAL_A[30]; + doa_out[31] <= SRVAL_A[31]; + dopa_out[0] <= SRVAL_A[32]; + dopa_out[1] <= SRVAL_A[33]; + dopa_out[2] <= SRVAL_A[34]; + dopa_out[3] <= SRVAL_A[35]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + dopa_out <= dipa_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + doa_out[16] <= mem[data_addra_int + 16]; + doa_out[17] <= mem[data_addra_int + 17]; + doa_out[18] <= mem[data_addra_int + 18]; + doa_out[19] <= mem[data_addra_int + 19]; + doa_out[20] <= mem[data_addra_int + 20]; + doa_out[21] <= mem[data_addra_int + 21]; + doa_out[22] <= mem[data_addra_int + 22]; + doa_out[23] <= mem[data_addra_int + 23]; + doa_out[24] <= mem[data_addra_int + 24]; + doa_out[25] <= mem[data_addra_int + 25]; + doa_out[26] <= mem[data_addra_int + 26]; + doa_out[27] <= mem[data_addra_int + 27]; + doa_out[28] <= mem[data_addra_int + 28]; + doa_out[29] <= mem[data_addra_int + 29]; + doa_out[30] <= mem[data_addra_int + 30]; + doa_out[31] <= mem[data_addra_int + 31]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + dopa_out[2] <= mem[parity_addra_int + 2]; + dopa_out[3] <= mem[parity_addra_int + 3]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + doa_out[16] <= mem[data_addra_int + 16]; + doa_out[17] <= mem[data_addra_int + 17]; + doa_out[18] <= mem[data_addra_int + 18]; + doa_out[19] <= mem[data_addra_int + 19]; + doa_out[20] <= mem[data_addra_int + 20]; + doa_out[21] <= mem[data_addra_int + 21]; + doa_out[22] <= mem[data_addra_int + 22]; + doa_out[23] <= mem[data_addra_int + 23]; + doa_out[24] <= mem[data_addra_int + 24]; + doa_out[25] <= mem[data_addra_int + 25]; + doa_out[26] <= mem[data_addra_int + 26]; + doa_out[27] <= mem[data_addra_int + 27]; + doa_out[28] <= mem[data_addra_int + 28]; + doa_out[29] <= mem[data_addra_int + 29]; + doa_out[30] <= mem[data_addra_int + 30]; + doa_out[31] <= mem[data_addra_int + 31]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + dopa_out[2] <= mem[parity_addra_int + 2]; + dopa_out[3] <= mem[parity_addra_int + 3]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + mem[data_addra_int + 4] <= dia_int[4]; + mem[data_addra_int + 5] <= dia_int[5]; + mem[data_addra_int + 6] <= dia_int[6]; + mem[data_addra_int + 7] <= dia_int[7]; + mem[data_addra_int + 8] <= dia_int[8]; + mem[data_addra_int + 9] <= dia_int[9]; + mem[data_addra_int + 10] <= dia_int[10]; + mem[data_addra_int + 11] <= dia_int[11]; + mem[data_addra_int + 12] <= dia_int[12]; + mem[data_addra_int + 13] <= dia_int[13]; + mem[data_addra_int + 14] <= dia_int[14]; + mem[data_addra_int + 15] <= dia_int[15]; + mem[data_addra_int + 16] <= dia_int[16]; + mem[data_addra_int + 17] <= dia_int[17]; + mem[data_addra_int + 18] <= dia_int[18]; + mem[data_addra_int + 19] <= dia_int[19]; + mem[data_addra_int + 20] <= dia_int[20]; + mem[data_addra_int + 21] <= dia_int[21]; + mem[data_addra_int + 22] <= dia_int[22]; + mem[data_addra_int + 23] <= dia_int[23]; + mem[data_addra_int + 24] <= dia_int[24]; + mem[data_addra_int + 25] <= dia_int[25]; + mem[data_addra_int + 26] <= dia_int[26]; + mem[data_addra_int + 27] <= dia_int[27]; + mem[data_addra_int + 28] <= dia_int[28]; + mem[data_addra_int + 29] <= dia_int[29]; + mem[data_addra_int + 30] <= dia_int[30]; + mem[data_addra_int + 31] <= dia_int[31]; + mem[parity_addra_int + 0] <= dipa_int[0]; + mem[parity_addra_int + 1] <= dipa_int[1]; + mem[parity_addra_int + 2] <= dipa_int[2]; + mem[parity_addra_int + 3] <= dipa_int[3]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dob_out[16] <= SRVAL_B[16]; + dob_out[17] <= SRVAL_B[17]; + dob_out[18] <= SRVAL_B[18]; + dob_out[19] <= SRVAL_B[19]; + dob_out[20] <= SRVAL_B[20]; + dob_out[21] <= SRVAL_B[21]; + dob_out[22] <= SRVAL_B[22]; + dob_out[23] <= SRVAL_B[23]; + dob_out[24] <= SRVAL_B[24]; + dob_out[25] <= SRVAL_B[25]; + dob_out[26] <= SRVAL_B[26]; + dob_out[27] <= SRVAL_B[27]; + dob_out[28] <= SRVAL_B[28]; + dob_out[29] <= SRVAL_B[29]; + dob_out[30] <= SRVAL_B[30]; + dob_out[31] <= SRVAL_B[31]; + dopb_out[0] <= SRVAL_B[32]; + dopb_out[1] <= SRVAL_B[33]; + dopb_out[2] <= SRVAL_B[34]; + dopb_out[3] <= SRVAL_B[35]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[data_addrb_int + 16] <= dib_int[16]; + mem[data_addrb_int + 17] <= dib_int[17]; + mem[data_addrb_int + 18] <= dib_int[18]; + mem[data_addrb_int + 19] <= dib_int[19]; + mem[data_addrb_int + 20] <= dib_int[20]; + mem[data_addrb_int + 21] <= dib_int[21]; + mem[data_addrb_int + 22] <= dib_int[22]; + mem[data_addrb_int + 23] <= dib_int[23]; + mem[data_addrb_int + 24] <= dib_int[24]; + mem[data_addrb_int + 25] <= dib_int[25]; + mem[data_addrb_int + 26] <= dib_int[26]; + mem[data_addrb_int + 27] <= dib_int[27]; + mem[data_addrb_int + 28] <= dib_int[28]; + mem[data_addrb_int + 29] <= dib_int[29]; + mem[data_addrb_int + 30] <= dib_int[30]; + mem[data_addrb_int + 31] <= dib_int[31]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + mem[parity_addrb_int + 2] <= dipb_int[2]; + mem[parity_addrb_int + 3] <= dipb_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKA *> DOPA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S36_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DOA; + output [3:0] DOPA; + output [31:0] DOB; + output [3:0] DOPB; + + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA, CLKA, WEA, SSRA; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [31:0] doa_out = INIT_A[31:0]; + reg [3:0] dopa_out = INIT_A[35:32]; + reg [31:0] dob_out = INIT_B[31:0]; + reg [3:0] dopb_out = INIT_B[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [31:0] dia_int; + wire [3:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [31:0] (DOA, doa_out); + buf b_dopa [3:0] (DOPA, dopa_out); + buf b_addra [8:0] (addra_int, ADDRA); + buf b_dia [31:0] (dia_int, DIA); + buf b_dipa [3:0] (dipa_int, DIPA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [31:0] (DOB, dob_out); + buf b_dopb [3:0] (DOPB, dopb_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [31:0] (dib_int, DIB); + buf b_dipb [3:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {dopa_out, doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end + +// initiate parity start + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 32; + assign data_addra_reg = addra_reg * 32; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 32'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg] <= 32'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 32'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision_b_a[0] <= 0; + end + +// x parity start + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 4'bx; + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) + memp[addra_reg] <= 4'bx; + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 4'bx; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end +// x parity end + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {dopa_out, doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + dopa_out <= #100 dipa_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + else begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + memp[addra_int] <= dipa_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/usrp2/fpga/models/SRL16E.v b/usrp2/fpga/models/SRL16E.v new file mode 100644 index 00000000..e71a419a --- /dev/null +++ b/usrp2/fpga/models/SRL16E.v @@ -0,0 +1,53 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.7 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Clock Enable +// /___/ /\ Filename : SRL16E.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + + +module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D); + + parameter INIT = 16'h0000; + + output Q; + + input A0, A1, A2, A3, CE, CLK, D; + + reg [15:0] data; + + + assign Q = data[{A3, A2, A1, A0}]; + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + always @(posedge CLK) + begin + if (CE == 1'b1) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + end + + +endmodule + diff --git a/usrp2/fpga/models/SRLC16E.v b/usrp2/fpga/models/SRLC16E.v new file mode 100644 index 00000000..a68bbe9e --- /dev/null +++ b/usrp2/fpga/models/SRLC16E.v @@ -0,0 +1,61 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRLC16E.v,v 1.6.158.1 2007/03/09 18:13:20 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 8.1i (I.13) +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Carry and Clock Enable +// /___/ /\ Filename : SRLC16E.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + + +module SRLC16E (Q, Q15, A0, A1, A2, A3, CE, CLK, D); + + parameter INIT = 16'h0000; + + output Q, Q15; + + input A0, A1, A2, A3, CE, CLK, D; + + reg [15:0] data; + wire [3:0] addr; + wire q_int; + + buf b_a3 (addr[3], A3); + buf b_a2 (addr[2], A2); + buf b_a1 (addr[1], A1); + buf b_a0 (addr[0], A0); + + buf b_q_int (q_int, data[addr]); + buf b_q (Q, q_int); + buf b_q15_int (q15_int, data[15]); + buf b_q15 (Q15, q15_int); + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + always @(posedge CLK) begin + if (CE == 1'b1) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + end + + +endmodule + diff --git a/usrp2/fpga/models/adc_model.v b/usrp2/fpga/models/adc_model.v new file mode 100644 index 00000000..247472c3 --- /dev/null +++ b/usrp2/fpga/models/adc_model.v @@ -0,0 +1,49 @@ + +module adc_model + (input clk, input rst, + output [13:0] adc_a, + output adc_ovf_a, + input adc_on_a, + input adc_oe_a, + output [13:0] adc_b, + output adc_ovf_b, + input adc_on_b, + input adc_oe_b + ); + + math_real math ( ) ; + + reg [13:0] adc_a_int = 0; + reg [13:0] adc_b_int = 0; + + assign adc_a = adc_oe_a ? adc_a_int : 14'bz; + assign adc_ovf_a = adc_oe_a ? 1'b0 : 1'bz; + assign adc_b = adc_oe_b ? adc_b_int : 14'bz; + assign adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz; + + real phase = 0; + real sample_rate = 100000000; + real freq = 330000/sample_rate; // 330 kHz + + real scale = math.pow(2,13)-2; + always @(posedge clk) + if(rst) + begin + adc_a_int <= 0; + adc_b_int <= 0; + end + else + begin + if(adc_on_a) + //adc_a_int <= $rtoi(math.round(math.sin(phase*math.MATH_2_PI)*scale)) ; + adc_a_int <= adc_a_int + 3; + if(adc_on_b) + adc_b_int <= adc_b_int - 7; + //adc_b_int <= $rtoi(math.round(math.cos(phase*math.MATH_2_PI)*scale)) ; + if(phase > 1) + phase <= phase + freq - 1; + else + phase <= phase + freq; + end + +endmodule // adc_model diff --git a/usrp2/fpga/models/cpld_model.v b/usrp2/fpga/models/cpld_model.v new file mode 100644 index 00000000..c886433a --- /dev/null +++ b/usrp2/fpga/models/cpld_model.v @@ -0,0 +1,96 @@ + +module cpld_model + (input aux_clk, input start, input mode, input done, + output dout, output reg sclk, output detached); + + reg [7:0] rom[0:65535]; + + reg [15:0] addr; + reg [7:0] data; + assign dout = data[7]; + + reg [2:0] state, bitcnt; + + localparam IDLE = 3'd0; + localparam READ = 3'd1; + localparam BIT1 = 3'd2; + localparam BIT2 = 3'd3; + localparam DONE = 3'd4; + localparam DETACHED = 3'd5; + localparam ERROR = 3'd7; + + integer i; + reg [1023:0] ROMFile; + + initial begin + for (i=0;i<65536;i=i+1) begin + rom[i] <= 32'h0; + end + if ( !$value$plusargs( "rom=%s", ROMFile ) ) + begin + $display( "Using default ROM file, 'flash.rom'" ); + ROMFile = "flash.rom"; + end + else + $display( "Using %s as ROM file.", ROMFile); + + #1 $readmemh( ROMFile,rom ); + end + + initial addr = 16'd0; + initial data = 8'd0; + initial state = IDLE; + initial bitcnt = 3'd0; + initial sclk = 1'b0; + + always @(posedge aux_clk) + case(state) + IDLE : + if(start) + if(~mode) + state <= READ; + else + state <= ERROR; + READ : + if(done) + state <= DONE; + else + begin + data <= rom[addr]; + addr <= addr + 1; + bitcnt <= 3'd0; + if(addr==16'hFFFF) + state <= ERROR; + else + state <= BIT1; + end // else: !if(start) + BIT1 : + begin + sclk <= 1'b1; + state <= BIT2; + end + BIT2 : + begin + sclk <= 1'b0; + data <= {data[6:0],1'b0}; + bitcnt <= bitcnt + 1; + if(bitcnt==7) + state <= READ; + else + state <=BIT1; + end + DONE : + begin + if(start) + state <= ERROR; + else + state <= DETACHED; + end + DETACHED : + if(start) + state <= ERROR; + endcase // case(state) + + assign detached = (state == DETACHED) || (state == IDLE); + +endmodule // cpld_model diff --git a/usrp2/fpga/models/math_real.v b/usrp2/fpga/models/math_real.v new file mode 100644 index 00000000..e30f68ee --- /dev/null +++ b/usrp2/fpga/models/math_real.v @@ -0,0 +1,495 @@ +/* + * This is a general recreation of the VHDL ieee.math_real package. + */ + +module math_real ; + // Constants for use below and for general reference + // TODO: Bring it out to 12 (or more???) places beyond the decimal? + localparam MATH_E = 2.7182818284; + localparam MATH_1_OVER_E = 0.3678794411; + localparam MATH_PI = 3.1415926536; + localparam MATH_2_PI = 6.2831853071; + localparam MATH_1_OVER_PI = 0.3183098861; + localparam MATH_PI_OVER_2 = 1.5707963267; + localparam MATH_PI_OVER_3 = 1.0471975511; + localparam MATH_PI_OVER_4 = 0.7853981633; + localparam MATH_3_PI_OVER_2 = 4.7123889803; + localparam MATH_LOG_OF_2 = 0.6931471805; + localparam MATH_LOG_OF_10 = 2.3025850929; + localparam MATH_LOG2_OF_E = 1.4426950408; + localparam MATH_LOG10_OF_E = 0.4342944819; + localparam MATH_SQRT_2 = 1.4142135623; + localparam MATH_1_OVER_SQRT_2= 0.7071067811; + localparam MATH_SQRT_PI = 1.7724538509; + localparam MATH_DEG_TO_RAD = 0.0174532925; + localparam MATH_RAD_TO_DEG = 57.2957795130; + + // The number of iterations to do for the Taylor series approximations + localparam EXPLOG_ITERATIONS = 19; + localparam COS_ITERATIONS = 8; + + /* Conversion Routines */ + + // Return the sign of a particular number. + function real sign ; + input real x ; + begin + sign = x < 0.0 ? 1.0 : 0.0 ; + end + endfunction + + // Return the trunc function of a number + function real trunc ; + input real x ; + begin + trunc = x - mod(x,1.0) ; + end + endfunction + + // Return the ceiling function of a number. + function real ceil ; + input real x ; + real retval ; + begin + retval = mod(x,1.0) ; + if( retval != 0.0 && x > 0.0 ) retval = x+1.0 ; + else retval = x ; + ceil = trunc(retval) ; + end + endfunction + + // Return the floor function of a number + function real floor ; + input real x ; + real retval ; + begin + retval = mod(x,1.0) ; + if( retval != 0.0 && x < 0.0 ) retval = x - 1.0 ; + else retval = x ; + floor = trunc(retval) ; + end + endfunction + + // Return the round function of a number + function real round ; + input real x ; + real retval ; + begin + retval = x > 0.0 ? x + 0.5 : x - 0.5 ; + round = trunc(retval) ; + end + endfunction + + // Return the fractional remainder of (x mod m) + function real mod ; + input real x ; + input real m ; + real retval ; + begin + retval = x ; + if( retval > m ) begin + while( retval > m ) begin + retval = retval - m ; + end + end + else begin + while( retval < -m ) begin + retval = retval + m ; + end + end + mod = retval ; + end + endfunction + + // Return the max between two real numbers + function real realmax ; + input real x ; + input real y ; + begin + realmax = x > y ? x : y ; + end + endfunction + + // Return the min between two real numbers + function real realmin ; + input real x ; + input real y ; + begin + realmin = x > y ? y : x ; + end + endfunction + + /* Random Numbers */ + + // Generate Gaussian distributed variables + function real gaussian ; + input real mean ; + input real var ; + real u1, u2, v1, v2, s ; + begin + s = 1.0 ; + while( s >= 1.0 ) begin + // Two random numbers between 0 and 1 + u1 = $random/4294967296.0 + 0.5 ; + u2 = $random/4294967296.0 + 0.5 ; + // Adjust to be between -1,1 + v1 = 2*u1-1.0 ; + v2 = 2*u2-1.0 ; + // Polar mag squared + s = (v1*v1 + v2*v2) ; + end + gaussian = mean + sqrt((-2.0*log(s))/s) * v1 * sqrt(var) ; + // gaussian2 = mean + sqrt(-2*log(s)/s)*v2 * sqrt(var) ; + end + endfunction + + /* Roots and Log Functions */ + + // Return the square root of a number + function real sqrt ; + input real x ; + real retval ; + begin + sqrt = (x == 0.0) ? 0.0 : powr(x,0.5) ; + end + endfunction + + // Return the cube root of a number + function real cbrt ; + input real x ; + real retval ; + begin + cbrt = (x == 0.0) ? 0.0 : powr(x,1.0/3.0) ; + end + endfunction + + // Return the absolute value of a real value + function real abs ; + input real x ; + begin + abs = (x > 0.0) ? x : -x ; + end + endfunction + + // Return a real value raised to an integer power + function real pow ; + input real b ; + input integer x ; + integer absx ; + real retval ; + begin + retval = 1.0 ; + absx = abs(x) ; + repeat(absx) begin + retval = b*retval ; + end + pow = x < 0 ? (1.0/retval) : retval ; + end + endfunction + + // Return a real value raised to a real power + function real powr ; + input real b ; + input real x ; + begin + powr = exp(x*log(b)) ; + end + endfunction + + // Return the evaluation of e^x where e is the natural logarithm base + // NOTE: This is the Taylor series expansion of e^x + function real exp ; + input real x ; + real retval ; + integer i ; + real nm1_fact ; + real powm1 ; + begin + nm1_fact = 1.0 ; + powm1 = 1.0 ; + retval = 1.0 ; + for( i = 1 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin + powm1 = x*powm1 ; + nm1_fact = nm1_fact * i ; + retval = retval + powm1/nm1_fact ; + end + exp = retval ; + end + endfunction + + // Return the evaluation log(x) + function real log ; + input real x ; + integer i ; + real whole ; + real xm1oxp1 ; + real retval ; + real newx ; + begin + retval = 0.0 ; + whole = 0.0 ; + newx = x ; + while( newx > MATH_E ) begin + whole = whole + 1.0 ; + newx = newx / MATH_E ; + end + xm1oxp1 = (newx-1.0)/(newx+1.0) ; + for( i = 0 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin + retval = retval + pow(xm1oxp1,2*i+1)/(2.0*i+1.0) ; + end + log = whole+2.0*retval ; + end + endfunction + + // Return the evaluation ln(x) (same as log(x)) + function real ln ; + input real x ; + begin + ln = log(x) ; + end + endfunction + + // Return the evaluation log_2(x) + function real log2 ; + input real x ; + begin + log2 = log(x)/MATH_LOG_OF_2 ; + end + endfunction + + function real log10 ; + input real x ; + begin + log10 = log(x)/MATH_LOG_OF_10 ; + end + endfunction + + function real log_base ; + input real x ; + input real b ; + begin + log_base = log(x)/log(b) ; + end + endfunction + + /* Trigonometric Functions */ + + // Internal function to reduce a value to be between [-pi:pi] + function real reduce ; + input real x ; + real retval ; + begin + retval = x ; + while( abs(retval) > MATH_PI ) begin + retval = retval > MATH_PI ? + (retval - MATH_2_PI) : + (retval + MATH_2_PI) ; + end + reduce = retval ; + end + endfunction + + // Return the cos of a number in radians + function real cos ; + input real x ; + integer i ; + integer sign ; + real newx ; + real retval ; + real xsqnm1 ; + real twonm1fact ; + begin + newx = reduce(x) ; + xsqnm1 = 1.0 ; + twonm1fact = 1.0 ; + retval = 1.0 ; + for( i = 1 ; i < COS_ITERATIONS ; i = i + 1 ) begin + sign = -2*(i % 2)+1 ; + xsqnm1 = xsqnm1*newx*newx ; + twonm1fact = twonm1fact * (2.0*i) * (2.0*i-1.0) ; + retval = retval + sign*(xsqnm1/twonm1fact) ; + end + cos = retval ; + end + endfunction + + // Return the sin of a number in radians + function real sin ; + input real x ; + begin + sin = cos(x - MATH_PI_OVER_2) ; + end + endfunction + + // Return the tan of a number in radians + function real tan ; + input real x ; + begin + tan = sin(x) / cos(x) ; + end + endfunction + + // Return the arcsin in radians of a number + function real arcsin ; + input real x ; + begin + arcsin = 2.0*arctan(x/(1.0+sqrt(1.0-x*x))) ; + end + endfunction + + // Return the arccos in radians of a number + function real arccos ; + input real x ; + begin + arccos = MATH_PI_OVER_2-arcsin(x) ; + end + endfunction + + // Return the arctan in radians of a number + // TODO: Make sure this REALLY does work as it is supposed to! + function real arctan ; + input real x ; + real retval ; + real y ; + real newx ; + real twoiotwoip1 ; + integer i ; + integer mult ; + begin + retval = 1.0 ; + twoiotwoip1 = 1.0 ; + mult = 1 ; + newx = abs(x) ; + while( newx > 1.0 ) begin + mult = mult*2 ; + newx = newx/(1.0+sqrt(1.0+newx*newx)) ; + end + y = 1.0 ; + for( i = 1 ; i < 2*COS_ITERATIONS ; i = i + 1 ) begin + y = y*((newx*newx)/(1+newx*newx)) ; + twoiotwoip1 = twoiotwoip1 * (2.0*i)/(2.0*i+1.0) ; + retval = retval + twoiotwoip1*y ; + end + retval = retval * (newx/(1+newx*newx)) ; + retval = retval * mult ; + + arctan = (x > 0.0) ? retval : -retval ; + end + endfunction + + // Return the arctan in radians of a ratio x/y + // TODO: Test to make sure this works as it is supposed to! + function real arctan_xy ; + input real x ; + input real y ; + real retval ; + begin + retval = 0.0 ; + if( x < 0.0 ) retval = MATH_PI - arctan(-abs(y)/x) ; + else if( x > 0.0 ) retval = arctan(abs(y)/x) ; + else if( x == 0.0 ) retval = MATH_PI_OVER_2 ; + arctan_xy = (y < 0.0) ? -retval : retval ; + end + endfunction + + /* Hyperbolic Functions */ + + // Return the sinh of a number + function real sinh ; + input real x ; + begin + sinh = (exp(x) - exp(-x))/2.0 ; + end + endfunction + + // Return the cosh of a number + function real cosh ; + input real x ; + begin + cosh = (exp(x) + exp(-x))/2.0 ; + end + endfunction + + // Return the tanh of a number + function real tanh ; + input real x ; + real e2x ; + begin + e2x = exp(2.0*x) ; + tanh = (e2x+1.0)/(e2x-1.0) ; + end + endfunction + + // Return the arcsinh of a number + function real arcsinh ; + input real x ; + begin + arcsinh = log(x+sqrt(x*x+1.0)) ; + end + endfunction + + // Return the arccosh of a number + function real arccosh ; + input real x ; + begin + arccosh = ln(x+sqrt(x*x-1.0)) ; + end + endfunction + + // Return the arctanh of a number + function real arctanh ; + input real x ; + begin + arctanh = 0.5*ln((1.0+x)/(1.0-x)) ; + end + endfunction + /* + initial begin + $display( "cos(MATH_PI_OVER_3): %f", cos(MATH_PI_OVER_3) ) ; + $display( "sin(MATH_PI_OVER_3): %f", sin(MATH_PI_OVER_3) ) ; + $display( "sign(-10): %f", sign(-10) ) ; + $display( "realmax(MATH_PI,MATH_E): %f", realmax(MATH_PI,MATH_E) ) ; + $display( "realmin(MATH_PI,MATH_E): %f", realmin(MATH_PI,MATH_E) ) ; + $display( "mod(MATH_PI,MATH_E): %f", mod(MATH_PI,MATH_E) ) ; + $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ; + $display( "ceil(4.0): %f", ceil(4.0) ) ; + $display( "ceil(3.99999999999999): %f", ceil(3.99999999999999) ) ; + $display( "pow(MATH_PI,2): %f", pow(MATH_PI,2) ) ; + $display( "gaussian(1.0,1.0): %f", gaussian(1.0,1.0) ) ; + $display( "round(MATH_PI): %f", round(MATH_PI) ) ; + $display( "trunc(-MATH_PI): %f", trunc(-MATH_PI) ) ; + $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ; + $display( "floor(MATH_PI): %f", floor(MATH_PI) ) ; + $display( "round(e): %f", round(MATH_E)) ; + $display( "ceil(-e): %f", ceil(-MATH_E)) ; + $display( "exp(MATH_PI): %f", exp(MATH_PI) ) ; + $display( "log2(MATH_PI): %f", log2(MATH_PI) ) ; + $display( "log_base(pow(2,32),2): %f", log_base(pow(2,32),2) ) ; + $display( "ln(0.1): %f", log(0.1) ) ; + $display( "cbrt(7): %f", cbrt(7) ) ; + $display( "cos(MATH_2_PI): %f", cos(20*MATH_2_PI) ) ; + $display( "sin(-MATH_2_PI): %f", sin(-50*MATH_2_PI) ) ; + $display( "sinh(MATH_E): %f", sinh(MATH_E) ) ; + $display( "cosh(MATH_2_PI): %f", cosh(MATH_2_PI) ) ; + $display( "arctan_xy(-4,3): %f", arctan_xy(-4,3) ) ; + $display( "arctan(MATH_PI): %f", arctan(MATH_PI) ) ; + $display( "arctan(-MATH_E/2): %f", arctan(-MATH_E/2) ) ; + $display( "arctan(MATH_PI_OVER_2): %f", arctan(MATH_PI_OVER_2) ) ; + $display( "arctan(1/7) = %f", arctan(1.0/7.0) ) ; + $display( "arctan(3/79) = %f", arctan(3.0/79.0) ) ; + $display( "pi/4 ?= %f", 5*arctan(1.0/7.0)+2*arctan(3.0/79.0) ) ; + $display( "arcsin(1.0): %f", arcsin(1.0) ) ; + $display( "cos(pi/2): %f", cos(MATH_PI_OVER_2)) ; + $display( "arccos(cos(pi/2)): %f", arccos(cos(MATH_PI_OVER_2)) ) ; + $display( "cos(0): %f", cos(0) ) ; + $display( "cos(MATH_PI_OVER_4): %f", cos(MATH_PI_OVER_4) ) ; + $display( "cos(MATH_PI_OVER_2): %f", cos(MATH_PI_OVER_2) ) ; + $display( "cos(3*MATH_PI_OVER_4): %f", cos(3*MATH_PI_OVER_4) ) ; + $display( "cos(MATH_PI): %f", cos(MATH_PI) ) ; + $display( "cos(5*MATH_PI_OVER_4): %f", cos(5*MATH_PI_OVER_4) ) ; + $display( "cos(6*MATH_PI_OVER_4): %f", cos(6*MATH_PI_OVER_4) ) ; + $display( "cos(7*MATH_PI_OVER_4): %f", cos(7*MATH_PI_OVER_4) ) ; + $display( "cos(8*MATH_PI_OVER_4): %f", cos(8*MATH_PI_OVER_4) ) ; + end*/ + +endmodule diff --git a/usrp2/fpga/models/serdes_model.v b/usrp2/fpga/models/serdes_model.v new file mode 100644 index 00000000..f10e5555 --- /dev/null +++ b/usrp2/fpga/models/serdes_model.v @@ -0,0 +1,34 @@ + +module serdes_model + (input ser_tx_clk, + input ser_tkmsb, + input ser_tklsb, + input [15:0] ser_t, + + output ser_rx_clk, + output ser_rkmsb, + output ser_rklsb, + output [15:0] ser_r, + + input even, + input error); + + wire [15:0] ser_r_odd; + wire ser_rklsb_odd, ser_rkmsb_odd; + + reg [7:0] hold_dat; + reg hold_k; + + always @(posedge ser_tx_clk) hold_k <= ser_tklsb; + always @(posedge ser_tx_clk) hold_dat <= ser_t[15:8]; + assign ser_rklsb_odd = hold_k; + assign ser_rkmsb_odd = ser_tklsb; + assign ser_r_odd = {ser_t[7:0], hold_dat}; + + // Set outputs + assign ser_rx_clk = ser_tx_clk; + assign ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd; + assign ser_rklsb = even ? ser_tklsb : ser_rklsb_odd; + assign ser_r = error ^ (even ? ser_t : ser_r_odd); + +endmodule // serdes_model diff --git a/usrp2/fpga/models/uart_rx.v b/usrp2/fpga/models/uart_rx.v new file mode 100644 index 00000000..f698a50f --- /dev/null +++ b/usrp2/fpga/models/uart_rx.v @@ -0,0 +1,48 @@ + + +// Simple printout of characters from the UART +// Only does 8N1, requires the baud clock + +module uart_rx (input baudclk, input rxd); + reg [8:0] sr = 9'b0; + reg [3:0] baud_ctr = 4'b0; + + /* + wire byteclk = baud_ctr[3]; + reg rxd_d1 = 0; + always @(posedge baudclk) + rxd_d1 <= rxd; + + always @(posedge baudclk) + if(rxd_d1 != rxd) + baud_ctr <= 0; + else + baud_ctr <= baud_ctr + 1; +*/ + + wire byteclk = baudclk; + + always @(posedge byteclk) + sr <= { rxd, sr[8:1] }; + + reg [3:0] state = 0; + always @(posedge byteclk) + case(state) + 0 : + if(~sr[8] & sr[7]) // found start bit + state <= 1; + 1, 2, 3, 4, 5, 6, 7, 8 : + state <= state + 1; + 9 : + begin + state <= 0; + $write("%c",sr[7:0]); + if(~sr[8]) + $display("Error, no stop bit\n"); + end + default : + state <= 0; + endcase // case(state) + +endmodule // uart_rx + diff --git a/usrp2/fpga/opencores/8b10b/8b10b_a.mem b/usrp2/fpga/opencores/8b10b/8b10b_a.mem new file mode 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from OpenCores. They are from +Chuck Benz. See http://asics.chuckbenz.com + + diff --git a/usrp2/fpga/opencores/8b10b/decode_8b10b.v b/usrp2/fpga/opencores/8b10b/decode_8b10b.v new file mode 100644 index 00000000..0b2a8ac5 --- /dev/null +++ b/usrp2/fpga/opencores/8b10b/decode_8b10b.v @@ -0,0 +1,165 @@ +// Chuck Benz, Hollis, NH Copyright (c)2002 +// +// The information and description contained herein is the +// property of Chuck Benz. +// +// Permission is granted for any reuse of this information +// and description as long as this copyright notice is +// preserved. Modifications may be made as long as this +// notice is preserved. + +// per Widmer and Franaszek + +module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err) ; + input [9:0] datain ; + input dispin ; + output [8:0] dataout ; + output dispout ; + output code_err ; + output disp_err ; + + wire ai = datain[0] ; + wire bi = datain[1] ; + wire ci = datain[2] ; + wire di = datain[3] ; + wire ei = datain[4] ; + wire ii = datain[5] ; + wire fi = datain[6] ; + wire gi = datain[7] ; + wire hi = datain[8] ; + wire ji = datain[9] ; + + wire aeqb = (ai & bi) | (!ai & !bi) ; + wire ceqd = (ci & di) | (!ci & !di) ; + wire p22 = (ai & bi & !ci & !di) | + (ci & di & !ai & !bi) | + ( !aeqb & !ceqd) ; + wire p13 = ( !aeqb & !ci & !di) | + ( !ceqd & !ai & !bi) ; + wire p31 = ( !aeqb & ci & di) | + ( !ceqd & ai & bi) ; + + wire p40 = ai & bi & ci & di ; + wire p04 = !ai & !bi & !ci & !di ; + + wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31. + wire disp6a2 = p31 & dispin ; // disp is ++ after 4 bits + wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits + + wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 | + (ei & ii & di)) & (ei | ii | di)) ; + + // The 5B/6B decoding special cases where ABCDE != abcde + + wire p22bceeqi = p22 & bi & ci & (ei == ii) ; + wire p22bncneeqi = p22 & !bi & !ci & (ei == ii) ; + wire p13in = p13 & !ii ; + wire p31i = p31 & ii ; + wire p13dei = p13 & di & ei & ii ; + wire p22aceeqi = p22 & ai & ci & (ei == ii) ; + wire p22ancneeqi = p22 & !ai & !ci & (ei == ii) ; + wire p13en = p13 & !ei ; + wire anbnenin = !ai & !bi & !ei & !ii ; + wire abei = ai & bi & ei & ii ; + wire cdei = ci & di & ei & ii ; + wire cndnenin = !ci & !di & !ei & !ii ; + + // non-zero disparity cases: + wire p22enin = p22 & !ei & !ii ; + wire p22ei = p22 & ei & ii ; + //wire p13in = p12 & !ii ; + //wire p31i = p31 & ii ; + wire p31dnenin = p31 & !di & !ei & !ii ; + //wire p13dei = p13 & di & ei & ii ; + wire p31e = p31 & ei ; + + wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi | + p13en | abei | cndnenin ; + wire compb = p22bceeqi | p31i | p13dei | p22aceeqi | + p13en | abei | cndnenin ; + wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi | + p13en | anbnenin | cndnenin ; + wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi | + p13en | abei | cndnenin ; + wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi | + p13en | anbnenin | cndnenin ; + + wire ao = ai ^ compa ; + wire bo = bi ^ compb ; + wire co = ci ^ compc ; + wire do = di ^ compd ; + wire eo = ei ^ compe ; + + wire feqg = (fi & gi) | (!fi & !gi) ; + wire heqj = (hi & ji) | (!hi & !ji) ; + wire fghj22 = (fi & gi & !hi & !ji) | + (!fi & !gi & hi & ji) | + ( !feqg & !heqj) ; + wire fghjp13 = ( !feqg & !hi & !ji) | + ( !heqj & !fi & !gi) ; + wire fghjp31 = ( (!feqg) & hi & ji) | + ( !heqj & fi & gi) ; + + wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ; + + wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) | + (p13 & !ei & ii & gi & hi & ji) | + (p31 & ei & !ii & !gi & !hi & !ji)) ; + + wire alt7 = (fi & !gi & !hi & // 1000 cases, where disp6b is 1 + ((dispin & ci & di & !ei & !ii) | ko | + (dispin & !ci & di & !ei & !ii))) | + (!fi & gi & hi & // 0111 cases, where disp6b is 0 + (( !dispin & !ci & !di & ei & ii) | ko | + ( !dispin & ci & !di & ei & ii))) ; + + wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii) ; + // k28 with positive disp into fghi - .1, .2, .5, and .6 special cases + wire k28p = ! (ci | di | ei | ii) ; + wire fo = (ji & !fi & (hi | !gi | k28p)) | + (fi & !ji & (!hi | gi | !k28p)) | + (k28p & gi & hi) | + (!k28p & !gi & !hi) ; + wire go = (ji & !fi & (hi | !gi | !k28p)) | + (fi & !ji & (!hi | gi |k28p)) | + (!k28p & gi & hi) | + (k28p & !gi & !hi) ; + wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) | + (fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) | + (!fi & gi & hi & ji) | (fi & !gi & !hi & !ji) ; + + wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii) ; + wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii) ; + wire disp4p = fghjp31 ; + wire disp4n = fghjp13 ; + + assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) | + (p13 & !ei & !ii) | (p31 & ei & ii) | + (ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) | + (ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) | + (!p31 & ei & !ii & !gi & !hi & !ji) | + (!p13 & !ei & ii & gi & hi & ji) | + (((ei & ii & !gi & !hi & !ji) | + (!ei & !ii & gi & hi & ji)) & + ! ((ci & di & ei) | (!ci & !di & !ei))) | + (disp6p & disp4p) | (disp6n & disp4n) | + (ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) | + (!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) | + (fi & gi & !hi & !ji & disp6p) | + (!fi & !gi & hi & ji & disp6n) | + (ci & di & ei & ii & !fi & !gi & !hi) | + (!ci & !di & !ei & !ii & fi & gi & hi) ; + + assign dataout = {ko, ho, go, fo, eo, do, co, bo, ao} ; + + // my disp err fires for any legal codes that violate disparity, may fire for illegal codes + assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) | + (dispin & !disp6n & fi & gi) | + (dispin & ai & bi & ci) | + (dispin & !disp6n & disp4p) | + (!dispin & !disp6p & !fi & !gi) | + (!dispin & !ai & !bi & !ci) | + (!dispin & !disp6p & disp4n) | + (disp6p & disp4p) | (disp6n & disp4n)) ; + +endmodule diff --git a/usrp2/fpga/opencores/8b10b/encode_8b10b.v b/usrp2/fpga/opencores/8b10b/encode_8b10b.v new file mode 100644 index 00000000..c1f09b9c --- /dev/null +++ b/usrp2/fpga/opencores/8b10b/encode_8b10b.v @@ -0,0 +1,120 @@ +// Chuck Benz, Hollis, NH Copyright (c)2002 +// +// The information and description contained herein is the +// property of Chuck Benz. +// +// Permission is granted for any reuse of this information +// and description as long as this copyright notice is +// preserved. Modifications may be made as long as this +// notice is preserved. + +// per Widmer and Franaszek + +module encode_8b10b (datain, dispin, dataout, dispout) ; + input [8:0] datain ; + input dispin ; // 0 = neg disp; 1 = pos disp + output [9:0] dataout ; + output dispout ; + + + wire ai = datain[0] ; + wire bi = datain[1] ; + wire ci = datain[2] ; + wire di = datain[3] ; + wire ei = datain[4] ; + wire fi = datain[5] ; + wire gi = datain[6] ; + wire hi = datain[7] ; + wire ki = datain[8] ; + + wire aeqb = (ai & bi) | (!ai & !bi) ; + wire ceqd = (ci & di) | (!ci & !di) ; + wire l22 = (ai & bi & !ci & !di) | + (ci & di & !ai & !bi) | + ( !aeqb & !ceqd) ; + wire l40 = ai & bi & ci & di ; + wire l04 = !ai & !bi & !ci & !di ; + wire l13 = ( !aeqb & !ci & !di) | + ( !ceqd & !ai & !bi) ; + wire l31 = ( !aeqb & ci & di) | + ( !ceqd & ai & bi) ; + + // The 5B/6B encoding + + wire ao = ai ; + wire bo = (bi & !l40) | l04 ; + wire co = l04 | ci | (ei & di & !ci & !bi & !ai) ; + wire do = di & ! (ai & bi & ci) ; + wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ; + wire io = (l22 & !ei) | + (ei & !di & !ci & !(ai&bi)) | // D16, D17, D18 + (ei & l40) | + (ki & ei & di & ci & !bi & !ai) | // K.28 + (ei & !di & ci & !bi & !ai) ; + + // pds16 indicates cases where d-1 is assumed + to get our encoded value + wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ; + // nds16 indicates cases where d-1 is assumed - to get our encoded value + wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ; + + // ndos6 is pds16 cases where d-1 is + yields - disp out - all of them + wire ndos6 = pd1s6 ; + // pdos6 is nds16 cases where d-1 is - yields + disp out - all but one + wire pdos6 = ki | (ei & !l22 & !l13) ; + + + // some Dx.7 and all Kx.7 cases result in run length of 5 case unless + // an alternate coding is used (referred to as Dx.A7, normal is Dx.P7) + // specifically, D11, D13, D14, D17, D18, D19. + wire alt7 = fi & gi & hi & (ki | + (dispin ? (!ei & di & l31) : (ei & !di & l13))) ; + + + wire fo = fi & ! alt7 ; + wire go = gi | (!fi & !gi & !hi) ; + wire ho = hi ; + wire jo = (!hi & (gi ^ fi)) | alt7 ; + + // nd1s4 is cases where d-1 is assumed - to get our encoded value + wire nd1s4 = fi & gi ; + // pd1s4 is cases where d-1 is assumed + to get our encoded value + wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ; + + // ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some + wire ndos4 = (!fi & !gi) ; + // pdos4 is nd1s4 cases where d-1 is - yields + disp out + wire pdos4 = fi & gi & hi ; + + // only legal K codes are K28.0->.7, K23/27/29/30.7 + // K28.0->7 is ei=di=ci=1,bi=ai=0 + // K23 is 10111 + // K27 is 11011 + // K29 is 11101 + // K30 is 11110 - so K23/27/29/30 are ei & l31 + wire illegalk = ki & + (ai | bi | !ci | !di | !ei) & // not K28.0->7 + (!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7 + + // now determine whether to do the complementing + // complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set + wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ; + + // disparity out of 5b6b is disp in with pdso6 and ndso6 + // pds16 indicates cases where d-1 is assumed + to get our encoded value + // ndos6 is cases where d-1 is + yields - disp out + // nds16 indicates cases where d-1 is assumed - to get our encoded value + // pdos6 is cases where d-1 is - yields + disp out + // disp toggles in all ndis16 cases, and all but that 1 nds16 case + + wire disp6 = dispin ^ (ndos6 | pdos6) ; + + wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ; + assign dispout = disp6 ^ (ndos4 | pdos4) ; + + assign dataout = {(jo ^ compls4), (ho ^ compls4), + (go ^ compls4), (fo ^ compls4), + (io ^ compls6), (eo ^ compls6), + (do ^ compls6), (co ^ compls6), + (bo ^ compls6), (ao ^ compls6)} ; + +endmodule diff --git a/usrp2/fpga/opencores/8b10b/validate_8b10b.v b/usrp2/fpga/opencores/8b10b/validate_8b10b.v new file mode 100644 index 00000000..926b1081 --- /dev/null +++ b/usrp2/fpga/opencores/8b10b/validate_8b10b.v @@ -0,0 +1,168 @@ +// Chuck Benz, Hollis, NH Copyright (c)2002 +// +// The information and description contained herein is the +// property of Chuck Benz. +// +// Permission is granted for any reuse of this information +// and description as long as this copyright notice is +// preserved. Modifications may be made as long as this +// notice is preserved. + +// 11-OCT-2002: updated with clearer messages, and checking decodeout + +`timescale 1ns / 1ns +module test_8b10b ; + reg [29:0] code8b10b [0:267] ; + reg [8:0] testin ; + reg dispin ; + reg [10:0] i ; + wire [9:0] testout ; + wire dispout, decodedisp, decodeerr, disperr ; + wire [8:0] decodeout ; + // My data file is 30 columns. Column 1 becomes [29], 2 becomes [28], etc.. + // code[0] is last Column (30) + // First column, [29] is K indication + // columns 2:9, [28:21], are data byte, aka 'm' and 'n' of Dm.n + // columns 10:19, [20:11] are 10b symbol if starting disparity was negative, 0 + // columns 20:29, [10:1] are 10b symbol if starting disparity was positive, 1 + // column 30, [0], is a 1 if symbol results in a disparity flip + // 0 for a balanced symbol (5 '1's, 5 '0's). + + wire [29:0] code = code8b10b[i] ; + wire [9:0] expect_0_disp = {code[11], code[12], code[13], code[14], code[15], + code[16], code[17], code[18], code[19], code[20]} ; + wire [9:0] expect_1_disp = {code[1], code[2], code[3], code[4], code[5], + code[6], code[7], code[8], code[9], code[10]} ; + + reg [1023:0] legal ; // mark every used 10b symbol as legal, leave rest marked as not + reg [2047:0] okdisp ; // now mark every used combination of symbol and starting disparity + reg [8:0] mapcode [1023:0] ; + reg [10:0] codedisp0, codedisp1 ; + reg [9:0] decodein ; + reg decdispin ; + integer errors ; + + encode_8b10b DUTE (testin, dispin, testout, dispout) ; + decode_8b10b DUTD (decodein, decdispin, decodeout, decodedisp, decodeerr, disperr) ; + + always @ (code) testin = code[29:21] ; + + initial begin + errors = 0 ; + $readmemb ("8b10b_a.mem", code8b10b) ; + //$vcdpluson ; + $dumpvars (0); + $display ("\n\nFirst, test by trying all 268 (256 Dx.y and 12 Kx.y)") ; + $display ("valid inputs, with both + and - starting disparity."); + $display ("We check that the encoder output and ending disparity is correct."); + $display ("We also check that the decoder matches."); + for (i = 0 ; i < 268 ; i = i + 1) begin + // testin = code[29:21] ; + dispin = 0 ; + #1 + decodein = testout ; + decdispin = dispin ; + #1 +// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ; + if (testout != expect_0_disp) + $display ("bad code0 %b %b %b %b %b", dispin, testin, dispout, testout, expect_0_disp) ; + if (dispout != (dispin ^ code[0])) + $display ("bad disp0 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ; + if (0 != (9'b1_1111_1111 & (testin ^ decodeout))) + $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if (decodedisp != dispout) + $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if ((testout != expect_0_disp) | decodeerr | + (dispout != (dispin ^ code[0])) | (decodedisp != dispout)) + errors = errors + 1 ; + + dispin = 1 ; + #1 + decodein = testout ; + decdispin = dispin ; + #1 +// $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2, DUTD.fghjp31, DUTD.feqg, DUTD.heqj, DUTD.fghj22, DUTD.fi, DUTD.gi, DUTD.hi, DUTD.ji, DUTD.dispout}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ; + if (testout != expect_1_disp) + $display ("bad code1 %b %b %b %b %b", dispin, testin, dispout, testout, expect_1_disp) ; + if (dispout != (dispin ^ code[0])) + $display ("bad disp1 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ; + if (0 != (9'b1_1111_1111 & (testin ^ decodeout))) + $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if (decodedisp != dispout) + $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin, dispout, testout, decodeout) ; + if ((testout != expect_1_disp) | decodeerr | + (dispout != (dispin ^ code[0])) | (decodedisp != dispout)) + errors = errors + 1 ; + end + $display ("%d errors in that testing.\n", errors) ; + + // Now, having verified all legal codes, lets run some illegal codes + // at the decoder... how to figure illegal codes ? 2048 possible cases, + // lets mark the OK ones... + legal = 0 ; + okdisp = 0 ; + for (i = 0 ; i < 268 ; i = i + 1) begin + #1 +// $display ("i=%d: %b %b %d %d %x %x", i, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp) ; + legal[expect_0_disp] = 1 ; + legal[expect_1_disp] = 1 ; + codedisp0 = expect_0_disp ; + codedisp1 = {1'b1, expect_1_disp} ; + okdisp[codedisp0] = 1 ; + okdisp[codedisp1] = 1 ; + mapcode[expect_0_disp] = code[29:21] ; + mapcode[expect_1_disp] = code[29:21] ; + end + + $display ("Now lets test all (legal and illegal) codes into the decoder."); + $display ("checking all possible decode inputs") ; + for (i = 0 ; i < 1024 ; i = i + 1) begin + decodein = i ; + decdispin = 0 ; + codedisp1 = 1024 | i ; + #1 + if (((legal[i] == 0) & (decodeerr != 1)) | + (legal[i] & (mapcode[i] != decodeout)) | + (legal[i] & (disperr != !okdisp[i]))) + $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", + decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i]) ; + if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ; + if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ; + if (legal[i] & (disperr != 1) & !okdisp[i]) $display ("ERR: disp err should be asserted") ; + else if (legal[i] & (disperr != 0) & okdisp[i]) + $display ("ERR: disp err should not be asserted") ; + + if (((legal[i] == 0) & (decodeerr != 1)) | + (legal[i] & !disperr & !okdisp[i]) | + (legal[i] & (mapcode[i] != decodeout)) | + (legal[i] & disperr & okdisp[i])) + errors = errors + 1 ; + + decdispin = 1 ; + #1 + if (((legal[i] == 0) & (decodeerr != 1)) | + (legal[i] & (mapcode[i] != decodeout)) | + (legal[i] & (disperr != !okdisp[i|1024]))) + $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", + decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i|1024]) ; + if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ; + if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ; + if (legal[i] & (disperr != 1) & !okdisp[i|1024]) $display ("ERR: disp err should be asserted") ; + else if (legal[i] & (disperr != 0) & okdisp[i|1024]) + $display ("ERR: disp err should not be asserted") ; + if (((legal[i] == 0) & (decodeerr != 1)) | + (legal[i] & !disperr & !okdisp[i|1024]) | + (legal[i] & (mapcode[i] != decodeout)) | + (legal[i] & disperr & okdisp[i|1024])) + errors = errors + 1 ; + end // for (i = 0 ; i < 1024 ; i = i + 1) + + $display ("\nDone testing decoder.\n") ; + $display ("Total error count: %d", errors); + if (errors == 0) $display ("Congratulations!\n"); + $finish ; + end // initial begin + +endmodule diff --git a/usrp2/fpga/opencores/README b/usrp2/fpga/opencores/README new file mode 100644 index 00000000..d63b7cbd --- /dev/null +++ b/usrp2/fpga/opencores/README @@ -0,0 +1,11 @@ +All the subdirectories of this directory contain code from the OpenCores +project, checked out directly from the OpenCores CVS server. You can update +any directory to the latest OpenCores code by doing "cvs up" in that. +This is not recommended unless you know what you are doing. + + +Each directory contains its own copyright and licensing information. We +believe that we have the right to distribute all of these files in the form +in which we provide them. If this is not the case, please notify Matt Ettus, +matt@ettus.com. + diff --git a/usrp2/fpga/opencores/aemb/CVS/Entries b/usrp2/fpga/opencores/aemb/CVS/Entries new file mode 100644 index 00000000..093a9a86 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/CVS/Entries @@ -0,0 +1,4 @@ +D/rtl//// +D/sim//// +D/sw//// +D/doc//// diff --git a/usrp2/fpga/opencores/aemb/CVS/Repository b/usrp2/fpga/opencores/aemb/CVS/Repository new file mode 100644 index 00000000..967f2ced --- /dev/null +++ b/usrp2/fpga/opencores/aemb/CVS/Repository @@ -0,0 +1 @@ +aemb diff --git a/usrp2/fpga/opencores/aemb/CVS/Root b/usrp2/fpga/opencores/aemb/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/aemb/CVS/Template b/usrp2/fpga/opencores/aemb/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/aemb/doc/CVS/Entries b/usrp2/fpga/opencores/aemb/doc/CVS/Entries new file mode 100644 index 00000000..16bb46ac --- /dev/null +++ b/usrp2/fpga/opencores/aemb/doc/CVS/Entries @@ -0,0 +1,2 @@ +/aeMB_datasheet.pdf/1.3/Tue Jan 15 18:38:57 2008/-kb/ +D diff --git a/usrp2/fpga/opencores/aemb/doc/CVS/Repository b/usrp2/fpga/opencores/aemb/doc/CVS/Repository new file mode 100644 index 00000000..41df302a --- /dev/null +++ b/usrp2/fpga/opencores/aemb/doc/CVS/Repository @@ -0,0 +1 @@ +aemb/doc diff --git a/usrp2/fpga/opencores/aemb/doc/CVS/Root b/usrp2/fpga/opencores/aemb/doc/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/doc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/aemb/doc/CVS/Template b/usrp2/fpga/opencores/aemb/doc/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/aemb/doc/aeMB_datasheet.pdf b/usrp2/fpga/opencores/aemb/doc/aeMB_datasheet.pdf new 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zz60|jkr*to{?Ld06oLj~6Y(4vB;?RKFi6CqxPgVi(ZpD=FaRJC7AzbKC&q$B?B63k zfEfw_lt9!MxMd5060Hr0iO7G5yKp4Y9DpAnU_|!am;D)s-0)^VQ6W6JurLU$Ve5_C zKU2W!&d$KA4WO0%mw!1YD`%j_(Z3#~KnB7nl!P>3gsT!)r7&=e3=Ay|lS0T~;HaxI mXov*nswn9HZej!y6(uLQnc>}jon-(lVDFLh@JOr3kpDkW%CvO= literal 0 HcmV?d00001 diff --git a/usrp2/fpga/opencores/aemb/rtl/CVS/Entries b/usrp2/fpga/opencores/aemb/rtl/CVS/Entries new file mode 100644 index 00000000..428c5622 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/fpga/opencores/aemb/rtl/CVS/Repository b/usrp2/fpga/opencores/aemb/rtl/CVS/Repository new file mode 100644 index 00000000..e2c1eab7 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/CVS/Repository @@ -0,0 +1 @@ +aemb/rtl diff --git a/usrp2/fpga/opencores/aemb/rtl/CVS/Root b/usrp2/fpga/opencores/aemb/rtl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/aemb/rtl/CVS/Template b/usrp2/fpga/opencores/aemb/rtl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries b/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries new file mode 100644 index 00000000..ad3a7dea --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries @@ -0,0 +1,38 @@ +/aeMB_bpcu.v/1.4/Mon Feb 4 17:16:00 2008// +/aeMB_core.v/1.9/Mon Feb 4 17:16:00 2008// +/aeMB_ctrl.v/1.10/Mon Feb 4 17:16:00 2008// +/aeMB_edk32.v/1.14/Mon Feb 4 17:16:00 2008// +/aeMB_ibuf.v/1.10/Tue May 20 17:45:01 2008// +/aeMB_regf.v/1.3/Mon Feb 4 17:16:00 2008// +/aeMB_sim.v/1.1/Mon Feb 4 17:16:00 2008// +/aeMB_xecu.v/1.12/Tue May 20 17:48:57 2008// +/aeMB2_aslu.v/1.10/Tue May 20 18:13:50 2008// +/aeMB2_bpcu.v/1.5/Tue May 20 18:13:50 2008// +/aeMB2_brcc.v/1.3/Tue May 20 18:13:50 2008// +/aeMB2_bsft.v/1.3/Tue May 20 18:13:50 2008// +/aeMB2_ctrl.v/1.7/Tue May 20 18:13:51 2008// +/aeMB2_dparam.v/1.1/Tue May 20 18:13:51 2008// +/aeMB2_dwbif.v/1.7/Tue May 20 18:13:51 2008// +/aeMB2_edk32.v/1.8/Tue May 20 18:13:51 2008// +/aeMB2_edk62.v/1.8/Tue May 20 18:13:51 2008// +/aeMB2_exec.v/1.4/Tue May 20 18:13:51 2008// +/aeMB2_gprf.v/1.4/Tue May 20 18:13:51 2008// +/aeMB2_iche.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_idmx.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_intu.v/1.7/Tue May 20 18:13:51 2008// +/aeMB2_iwbif.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_memif.v/1.3/Tue May 20 18:13:51 2008// +/aeMB2_mult.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_ofid.v/1.2/Tue May 20 18:13:51 2008// +/aeMB2_opmx.v/1.3/Tue May 20 18:13:51 2008// +/aeMB2_pipe.v/1.4/Tue May 20 18:13:51 2008// +/aeMB2_regf.v/1.3/Tue May 20 18:13:51 2008// +/aeMB2_regs.v/1.4/Tue May 20 18:13:51 2008// +/aeMB2_sfrf.v/1.2/Tue May 20 18:13:51 2008// +/aeMB2_sim.v/1.2/Tue May 20 18:13:51 2008// +/aeMB2_sparam.v/1.2/Tue May 20 18:13:51 2008// +/aeMB2_spsram.v/1.1/Tue May 20 18:13:51 2008// +/aeMB2_sysc.v/1.5/Tue May 20 18:13:51 2008// +/aeMB2_tpsram.v/1.3/Tue May 20 18:13:51 2008// +/aeMB2_xslif.v/1.7/Tue May 20 18:13:52 2008// +D diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Repository b/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Repository new file mode 100644 index 00000000..a9de1955 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Repository @@ -0,0 +1 @@ +aemb/rtl/verilog diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Root b/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Template b/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_bpcu.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_bpcu.v new file mode 100644 index 00000000..a7c686e7 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_bpcu.v @@ -0,0 +1,184 @@ +// $Id: aeMB_bpcu.v,v 1.4 2007/11/14 22:14:34 sybreon Exp $ +// +// AEMB BRANCH PROGRAMME COUNTER UNIT +// +// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +// +// This file is part of AEMB. +// +// AEMB is free software: you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as +// published by the Free Software Foundation, either version 3 of the +// License, or (at your option) any later version. +// +// AEMB is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +// Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with AEMB. If not, see . +// +// $Log: aeMB_bpcu.v,v $ +// Revision 1.4 2007/11/14 22:14:34 sybreon +// Changed interrupt handling system (reported by M. Ettus). +// +// Revision 1.3 2007/11/10 16:39:38 sybreon +// Upgraded license to LGPLv3. +// Significant performance optimisations. +// +// Revision 1.2 2007/11/02 19:20:58 sybreon +// Added better (beta) interrupt support. +// Changed MSR_IE to disabled at reset as per MB docs. +// +// Revision 1.1 2007/11/02 03:25:39 sybreon +// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. +// Fixed various minor data hazard bugs. +// Code compatible with -O0/1/2/3/s generated code. +// + +module aeMB_bpcu (/*AUTOARG*/ + // Outputs + iwb_adr_o, rPC, rPCLNK, rBRA, rDLY, + // Inputs + rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, gclk, grst, gena + ); + parameter IW = 24; + + // INST WISHBONE + output [IW-1:2] iwb_adr_o; + + // INTERNAL + output [31:2] rPC, rPCLNK; + output rBRA; + output rDLY; + //output [1:0] rATOM; + //output [1:0] xATOM; + + input [1:0] rMXALT; + input [5:0] rOPC; + input [4:0] rRD, rRA; + input [31:0] rRESULT; // ALU + input [31:0] rDWBDI; // RAM + input [31:0] rREGA; + //input [1:0] rXCE; + + // SYSTEM + input gclk, grst, gena; + + // --- BRANCH CONTROL -------------------------------------------- + // Controls the branch and delay flags + + wire fRTD = (rOPC == 6'o55); + wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57); + wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56); + + wire [31:0] wREGA; + assign wREGA = (rMXALT == 2'o2) ? rDWBDI : + (rMXALT == 2'o1) ? rRESULT : + rREGA; + + wire wBEQ = (wREGA == 32'd0); + wire wBNE = ~wBEQ; + wire wBLT = wREGA[31]; + wire wBLE = wBLT | wBEQ; + wire wBGE = ~wBLT; + wire wBGT = ~wBLE; + + reg xXCC; + always @(/*AUTOSENSE*/rRD or wBEQ or wBGE or wBGT or wBLE or wBLT + or wBNE) + case (rRD[2:0]) + 3'o0: xXCC <= wBEQ; + 3'o1: xXCC <= wBNE; + 3'o2: xXCC <= wBLT; + 3'o3: xXCC <= wBLE; + 3'o4: xXCC <= wBGT; + 3'o5: xXCC <= wBGE; + default: xXCC <= 1'bX; + endcase // case (rRD[2:0]) + + reg rBRA, xBRA; + reg rDLY, xDLY; + wire fSKIP = rBRA & !rDLY; + + always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD + or xXCC) + //if (rBRA | |rXCE) begin + if (rBRA) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xBRA <= 1'h0; + xDLY <= 1'h0; + // End of automatics + end else begin + xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD; + xBRA <= (fRTD | fBRU) ? 1'b1 : + (fBCC) ? xXCC : + 1'b0; + end + + // --- PC PIPELINE ------------------------------------------------ + // PC and related changes + + reg [31:2] rIPC, xIPC; + reg [31:2] rPC, xPC; + reg [31:2] rPCLNK, xPCLNK; + + assign iwb_adr_o = rIPC[IW-1:2]; + + always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin + //xPCLNK <= (^rATOM) ? rPC : rPC; + xPCLNK <= rPC; + //xPC <= (^rATOM) ? rIPC : rRESULT[31:2]; + xPC <= rIPC; + //xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); + /* + case (rXCE) + 2'o1: xIPC <= 30'h2; + 2'o2: xIPC <= 30'h4; + 2'o3: xIPC <= 30'h6; + default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); + endcase // case (rXCE) + */ + xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1); + end + + // --- ATOMIC CONTROL --------------------------------------------- + // This is used to indicate 'safe' instruction borders. + + wire wIMM = (rOPC == 6'o54) & !fSKIP; + wire wRTD = (rOPC == 6'o55) & !fSKIP; + wire wBCC = xXCC & ((rOPC == 6'o47) | (rOPC == 6'o57)) & !fSKIP; + wire wBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)) & !fSKIP; + + wire fATOM = ~(wIMM | wRTD | wBCC | wBRU | rBRA); + reg [1:0] rATOM, xATOM; + + always @(/*AUTOSENSE*/fATOM or rATOM) + xATOM <= {rATOM[0], (rATOM[0] ^ fATOM)}; + + + // --- SYNC PIPELINE ---------------------------------------------- + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rATOM <= 2'h0; + rBRA <= 1'h0; + rDLY <= 1'h0; + rIPC <= 30'h0; + rPC <= 30'h0; + rPCLNK <= 30'h0; + // End of automatics + end else if (gena) begin + rIPC <= #1 xIPC; + rBRA <= #1 xBRA; + rPC <= #1 xPC; + rPCLNK <= #1 xPCLNK; + rDLY <= #1 xDLY; + rATOM <= #1 xATOM; + end + +endmodule // aeMB_bpcu diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core.v new file mode 100644 index 00000000..20ce9852 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core.v @@ -0,0 +1,137 @@ +// $Id: aeMB_core.v,v 1.9 2007/11/23 14:06:41 sybreon Exp $ +// +// AEMB 32'bit RISC MICROPROCESSOR CORE +// +// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +// +// This file is part of AEMB. +// +// AEMB is free software: you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as +// published by the Free Software Foundation, either version 3 of the +// License, or (at your option) any later version. +// +// AEMB is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +// Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with AEMB. If not, see . +// +// HISTORY +// $Log: aeMB_core.v,v $ +// Revision 1.9 2007/11/23 14:06:41 sybreon +// Old version deprecated. +// +// Revision 1.8 2007/10/22 19:12:59 sybreon +// Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. +// +// Revision 1.7 2007/05/30 18:44:30 sybreon +// Added interrupt support. +// +// Revision 1.6 2007/05/17 09:08:21 sybreon +// Removed asynchronous reset signal. +// +// Revision 1.5 2007/04/27 00:23:55 sybreon +// Added code documentation. +// Improved size & speed of rtl/verilog/aeMB_aslu.v +// +// Revision 1.4 2007/04/25 22:15:04 sybreon +// Added support for 8-bit and 16-bit data types. +// +// Revision 1.3 2007/04/11 04:30:43 sybreon +// Added pipeline stalling from incomplete bus cycles. +// Separated sync and async portions of code. +// +// Revision 1.2 2007/04/04 06:13:23 sybreon +// Removed unused signals +// +// Revision 1.1 2007/03/09 17:52:17 sybreon +// initial import +// + + +module aeMB_core (/*AUTOARG*/ + // Outputs + iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, + fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, + // Inputs + sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, + fsl_ack_i, dwb_dat_i, dwb_ack_i + ); + // Instruction WB address space + parameter ISIZ = 32; + // Data WB address space + parameter DSIZ = 32; + // Multiplier + parameter MUL = 1; + // Barrel Shifter + parameter BSF = 1; + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [DSIZ-1:2] dwb_adr_o; // From edk32 of aeMB_edk32.v + output [31:0] dwb_dat_o; // From edk32 of aeMB_edk32.v + output [3:0] dwb_sel_o; // From edk32 of aeMB_edk32.v + output dwb_stb_o; // From edk32 of aeMB_edk32.v + output dwb_wre_o; // From edk32 of aeMB_edk32.v + output [6:2] fsl_adr_o; // From edk32 of aeMB_edk32.v + output [31:0] fsl_dat_o; // From edk32 of aeMB_edk32.v + output fsl_stb_o; // From edk32 of aeMB_edk32.v + output [1:0] fsl_tag_o; // From edk32 of aeMB_edk32.v + output fsl_wre_o; // From edk32 of aeMB_edk32.v + output [ISIZ-1:2] iwb_adr_o; // From edk32 of aeMB_edk32.v + output iwb_stb_o; // From edk32 of aeMB_edk32.v + // End of automatics + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input dwb_ack_i; // To edk32 of aeMB_edk32.v + input [31:0] dwb_dat_i; // To edk32 of aeMB_edk32.v + input fsl_ack_i; // To edk32 of aeMB_edk32.v + input [31:0] fsl_dat_i; // To edk32 of aeMB_edk32.v + input iwb_ack_i; // To edk32 of aeMB_edk32.v + input [31:0] iwb_dat_i; // To edk32 of aeMB_edk32.v + input sys_clk_i; // To edk32 of aeMB_edk32.v + input sys_int_i; // To edk32 of aeMB_edk32.v + input sys_rst_i; // To edk32 of aeMB_edk32.v + // End of automatics + /*AUTOWIRE*/ + + // INSTANTIATIONS ///////////////////////////////////////////////////////////////// + + /* + aeMB_edk32 AUTO_TEMPLATE ( + .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), + .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), + ); + */ + + aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF) + edk32 (/*AUTOINST*/ + // Outputs + .dwb_adr_o (dwb_adr_o[DSIZ-1:2]), // Templated + .dwb_dat_o (dwb_dat_o[31:0]), + .dwb_sel_o (dwb_sel_o[3:0]), + .dwb_stb_o (dwb_stb_o), + .dwb_wre_o (dwb_wre_o), + .fsl_adr_o (fsl_adr_o[6:2]), + .fsl_dat_o (fsl_dat_o[31:0]), + .fsl_stb_o (fsl_stb_o), + .fsl_tag_o (fsl_tag_o[1:0]), + .fsl_wre_o (fsl_wre_o), + .iwb_adr_o (iwb_adr_o[ISIZ-1:2]), // Templated + .iwb_stb_o (iwb_stb_o), + // Inputs + .dwb_ack_i (dwb_ack_i), + .dwb_dat_i (dwb_dat_i[31:0]), + .fsl_ack_i (fsl_ack_i), + .fsl_dat_i (fsl_dat_i[31:0]), + .iwb_ack_i (iwb_ack_i), + .iwb_dat_i (iwb_dat_i[31:0]), + .sys_int_i (sys_int_i), + .sys_clk_i (sys_clk_i), + .sys_rst_i (sys_rst_i)); + + +endmodule // aeMB_core diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v new file mode 100644 index 00000000..9ffa20ff --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v @@ -0,0 +1,62 @@ + +// Wrapper for aeMB core: +// Drive wb_cyc_o (just tied to wb_stb_o for now) +// Make input reset active high (like the signal name makes it sound....) +// No longer needed +// Make it big-endian like the standard MicroBlaze + +module aeMB_core_BE + #(parameter ISIZ=32, parameter DSIZ=32, + parameter MUL=0, parameter BSF=0) + (input sys_clk_i, + input sys_rst_i, + + output iwb_stb_o, + output [ISIZ-1:0] iwb_adr_o, + input [31:0] iwb_dat_i, + input iwb_ack_i, + + output dwb_we_o, + output dwb_stb_o, + output [DSIZ-1:0] dwb_adr_o, + output [31:0] dwb_dat_o, + input [31:0] dwb_dat_i, + input dwb_ack_i, + output [3:0] dwb_sel_o, + output dwb_cyc_o, + + input sys_int_i, + input sys_exc_i); + + assign dwb_cyc_o = dwb_stb_o; + + aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF)) + aeMB_edk32 (.sys_clk_i(sys_clk_i), + .sys_rst_i(sys_rst_i), + + .iwb_stb_o(iwb_stb_o), + .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), + .iwb_ack_i(iwb_ack_i), + .iwb_dat_i(iwb_dat_i), + + .dwb_wre_o(dwb_we_o), + .dwb_stb_o(dwb_stb_o), + .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), + .dwb_ack_i(dwb_ack_i), + .dwb_sel_o(dwb_sel_o), + .dwb_dat_i(dwb_dat_i), + .dwb_dat_o(dwb_dat_o), + + .fsl_wre_o(), + .fsl_tag_o(), + .fsl_stb_o(), + .fsl_dat_o(), + .fsl_adr_o(), + .fsl_dat_i(32'b0), + .fsl_ack_i(1'b0), + .sys_int_i(sys_int_i) ); + + assign iwb_adr_o[1:0] = 2'b0; + assign dwb_adr_o[1:0] = 2'b0; + +endmodule // aeMB_core_BE diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v new file mode 100644 index 00000000..88d4e51c --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v @@ -0,0 +1,336 @@ +// $Id: aeMB_ctrl.v,v 1.10 2007/11/30 16:44:40 sybreon Exp $ +// +// AEMB CONTROL UNIT +// +// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +// +// This file is part of AEMB. +// +// AEMB is free software: you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as +// published by the Free Software Foundation, either version 3 of the +// License, or (at your option) any later version. +// +// AEMB is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +// Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with AEMB. If not, see . +// +// $Log: aeMB_ctrl.v,v $ +// Revision 1.10 2007/11/30 16:44:40 sybreon +// Minor code cleanup. +// +// Revision 1.9 2007/11/15 09:26:43 sybreon +// Fixed minor typo causing synthesis failure. +// +// Revision 1.8 2007/11/14 23:19:24 sybreon +// Fixed minor typo. +// +// Revision 1.7 2007/11/14 22:14:34 sybreon +// Changed interrupt handling system (reported by M. Ettus). +// +// Revision 1.6 2007/11/10 16:39:38 sybreon +// Upgraded license to LGPLv3. +// Significant performance optimisations. +// +// Revision 1.5 2007/11/09 20:51:52 sybreon +// Added GET/PUT support through a FSL bus. +// +// Revision 1.4 2007/11/08 17:48:14 sybreon +// Fixed data WISHBONE arbitration problem (reported by J Lee). +// +// Revision 1.3 2007/11/08 14:17:47 sybreon +// Parameterised optional components. +// +// Revision 1.2 2007/11/02 19:20:58 sybreon +// Added better (beta) interrupt support. +// Changed MSR_IE to disabled at reset as per MB docs. +// +// Revision 1.1 2007/11/02 03:25:40 sybreon +// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. +// Fixed various minor data hazard bugs. +// Code compatible with -O0/1/2/3/s generated code. +// + +module aeMB_ctrl (/*AUTOARG*/ + // Outputs + rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o, + fsl_stb_o, fsl_wre_o, + // Inputs + rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG, + dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena + ); + // INTERNAL + //output [31:2] rPCLNK; + output [1:0] rMXDST; + output [1:0] rMXSRC, rMXTGT, rMXALT; + output [2:0] rMXALU; + output [4:0] rRW; + + input rDLY; + input [15:0] rIMM; + input [10:0] rALT; + input [5:0] rOPC; + input [4:0] rRD, rRA, rRB; + input [31:2] rPC; + input rBRA; + input rMSR_IE; + input [31:0] xIREG; + + // DATA WISHBONE + output dwb_stb_o; + output dwb_wre_o; + input dwb_ack_i; + + // INST WISHBONE + input iwb_ack_i; + + // FSL WISHBONE + output fsl_stb_o; + output fsl_wre_o; + input fsl_ack_i; + + // SYSTEM + input gclk, grst, gena; + + // --- DECODE INSTRUCTIONS + // TODO: Simplify + + wire [5:0] wOPC; + wire [4:0] wRD, wRA, wRB; + wire [10:0] wALT; + + assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian + + wire fSFT = (rOPC == 6'o44); + wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4); + + wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30); + wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31); + wire fDIV = (rOPC == 6'o22); + + wire fRTD = (rOPC == 6'o55); + wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57); + wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56); + wire fBRA = fBRU & rRA[3]; + + wire fIMM = (rOPC == 6'o54); + wire fMOV = (rOPC == 6'o45); + + wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6); + wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7); + wire fLDST = (&rOPC[5:4]); + + wire fPUT = (rOPC == 6'o33) & rRB[4]; + wire fGET = (rOPC == 6'o33) & !rRB[4]; + + + wire wSFT = (wOPC == 6'o44); + wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4); + + wire wMUL = (wOPC == 6'o20) | (wOPC == 6'o30); + wire wBSF = (wOPC == 6'o21) | (wOPC == 6'o31); + wire wDIV = (wOPC == 6'o22); + + wire wRTD = (wOPC == 6'o55); + wire wBCC = (wOPC == 6'o47) | (wOPC == 6'o57); + wire wBRU = (wOPC == 6'o46) | (wOPC == 6'o56); + wire wBRA = wBRU & wRA[3]; + + wire wIMM = (wOPC == 6'o54); + wire wMOV = (wOPC == 6'o45); + + wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6); + wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7); + wire wLDST = (&wOPC[5:4]); + + wire wPUT = (wOPC == 6'o33) & wRB[4]; + wire wGET = (wOPC == 6'o33) & !wRB[4]; + + + // --- BRANCH SLOT REGISTERS --------------------------- + + reg [31:2] rPCLNK, xPCLNK; + reg [1:0] rMXDST, xMXDST; + reg [4:0] rRW, xRW; + + reg [1:0] rMXSRC, xMXSRC; + reg [1:0] rMXTGT, xMXTGT; + reg [1:0] rMXALT, xMXALT; + + + // --- OPERAND SELECTOR --------------------------------- + + wire wRDWE = |xRW; + wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE; + wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE; + wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE; + wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE; + + always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M + or wBFWD_R or wBRU or wOPC) + //if (rBRA | |rXCE) begin + if (rBRA) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xMXALT <= 2'h0; + xMXSRC <= 2'h0; + xMXTGT <= 2'h0; + // End of automatics + end else begin + xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC + (wAFWD_M) ? 2'o2 : // RAM + (wAFWD_R) ? 2'o1 : // FWD + 2'o0; // REG + xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM + (wBFWD_M) ? 2'o2 : // RAM + (wBFWD_R) ? 2'o1 : // FWD + 2'o0; // REG + xMXALT <= (wAFWD_M) ? 2'o2 : // RAM + (wAFWD_R) ? 2'o1 : // FWD + 2'o0; // REG + end // else: !if(rBRA) + + // --- ALU CONTROL --------------------------------------- + + reg [2:0] rMXALU, xMXALU; + + always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV + or wMUL or wSFT) + //if (rBRA | |rXCE) begin + if (rBRA) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xMXALU <= 3'h0; + // End of automatics + end else begin + xMXALU <= (wBRA | wMOV) ? 3'o3 : + (wSFT) ? 3'o2 : + (wLOG) ? 3'o1 : + (wMUL) ? 3'o4 : + (wBSF) ? 3'o5 : + (wDIV) ? 3'o6 : + 3'o0; + end // else: !if(rBRA) + + // --- DELAY SLOT REGISTERS ------------------------------ + + wire fSKIP = (rBRA & !rDLY); + + always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP + or fSTR or rRD) + if (fSKIP) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xMXDST <= 2'h0; + xRW <= 5'h0; + // End of automatics + end else begin + xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 : + (fLOD | fGET) ? 2'o2 : + (fBRU) ? 2'o1 : + 2'o0; + xRW <= rRD; + end // else: !if(fSKIP) + + + // --- DATA WISHBONE ---------------------------------- + + wire fDACK = !(dwb_stb_o ^ dwb_ack_i); + + reg rDWBSTB, xDWBSTB; + reg rDWBWRE, xDWBWRE; + + assign dwb_stb_o = rDWBSTB; + assign dwb_wre_o = rDWBWRE; + + + always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i) + //if (fSKIP | |rXCE) begin + if (fSKIP) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xDWBSTB <= 1'h0; + xDWBWRE <= 1'h0; + // End of automatics + end else begin + xDWBSTB <= (fLOD | fSTR) & iwb_ack_i; + xDWBWRE <= fSTR & iwb_ack_i; + end + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rDWBSTB <= 1'h0; + rDWBWRE <= 1'h0; + // End of automatics + end else if (fDACK) begin + rDWBSTB <= #1 xDWBSTB; + rDWBWRE <= #1 xDWBWRE; + end + + + // --- FSL WISHBONE ----------------------------------- + + wire fFACK = !(fsl_stb_o ^ fsl_ack_i); + + reg rFSLSTB, xFSLSTB; + reg rFSLWRE, xFSLWRE; + + assign fsl_stb_o = rFSLSTB; + assign fsl_wre_o = rFSLWRE; + + always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i) + //if (fSKIP | |rXCE) begin + if (fSKIP) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xFSLSTB <= 1'h0; + xFSLWRE <= 1'h0; + // End of automatics + end else begin + xFSLSTB <= (fPUT | fGET) & iwb_ack_i; + xFSLWRE <= fPUT & iwb_ack_i; + end + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rFSLSTB <= 1'h0; + rFSLWRE <= 1'h0; + // End of automatics + end else if (fFACK) begin + rFSLSTB <= #1 xFSLSTB; + rFSLWRE <= #1 xFSLWRE; + end + + // --- PIPELINE CONTROL DELAY ---------------------------- + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rMXALT <= 2'h0; + rMXALU <= 3'h0; + rMXDST <= 2'h0; + rMXSRC <= 2'h0; + rMXTGT <= 2'h0; + rRW <= 5'h0; + // End of automatics + end else if (gena) begin // if (grst) + //rPCLNK <= #1 xPCLNK; + rMXDST <= #1 xMXDST; + rRW <= #1 xRW; + rMXSRC <= #1 xMXSRC; + rMXTGT <= #1 xMXTGT; + rMXALT <= #1 xMXALT; + rMXALU <= #1 xMXALU; + end + + +endmodule // aeMB_ctrl diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v new file mode 100644 index 00000000..8bf4f7ca --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v @@ -0,0 +1,289 @@ +/* $Id: aeMB_edk32.v,v 1.14 2008/01/19 16:01:22 sybreon Exp $ +** +** AEMB EDK 3.2 Compatible Core +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aeMB_edk32 (/*AUTOARG*/ + // Outputs + iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, + fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, + // Inputs + sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i, + dwb_ack_i, sys_clk_i, sys_rst_i + ); + // Bus widths + parameter IW = 32; /// Instruction bus address width + parameter DW = 32; /// Data bus address width + + // Optional functions + parameter MUL = 0; // Multiplier + parameter BSF = 1; // Barrel Shifter + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v + output [31:0] dwb_dat_o; // From regf of aeMB_regf.v + output [3:0] dwb_sel_o; // From xecu of aeMB_xecu.v + output dwb_stb_o; // From ctrl of aeMB_ctrl.v + output dwb_wre_o; // From ctrl of aeMB_ctrl.v + output [6:2] fsl_adr_o; // From xecu of aeMB_xecu.v + output [31:0] fsl_dat_o; // From regf of aeMB_regf.v + output fsl_stb_o; // From ctrl of aeMB_ctrl.v + output [1:0] fsl_tag_o; // From xecu of aeMB_xecu.v + output fsl_wre_o; // From ctrl of aeMB_ctrl.v + output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v + output iwb_stb_o; // From ibuf of aeMB_ibuf.v + // End of automatics + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input dwb_ack_i; // To ctrl of aeMB_ctrl.v + input [31:0] dwb_dat_i; // To regf of aeMB_regf.v + input fsl_ack_i; // To ctrl of aeMB_ctrl.v + input [31:0] fsl_dat_i; // To regf of aeMB_regf.v + input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ... + input [31:0] iwb_dat_i; // To ibuf of aeMB_ibuf.v + input sys_int_i; // To ibuf of aeMB_ibuf.v + // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [10:0] rALT; // From ibuf of aeMB_ibuf.v + wire rBRA; // From bpcu of aeMB_bpcu.v + wire rDLY; // From bpcu of aeMB_bpcu.v + wire [31:0] rDWBDI; // From regf of aeMB_regf.v + wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v + wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v + wire rMSR_BIP; // From xecu of aeMB_xecu.v + wire rMSR_IE; // From xecu of aeMB_xecu.v + wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v + wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v + wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v + wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v + wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v + wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v + wire [31:2] rPC; // From bpcu of aeMB_bpcu.v + wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v + wire [4:0] rRA; // From ibuf of aeMB_ibuf.v + wire [4:0] rRB; // From ibuf of aeMB_ibuf.v + wire [4:0] rRD; // From ibuf of aeMB_ibuf.v + wire [31:0] rREGA; // From regf of aeMB_regf.v + wire [31:0] rREGB; // From regf of aeMB_regf.v + wire [31:0] rRESULT; // From xecu of aeMB_xecu.v + wire [4:0] rRW; // From ctrl of aeMB_ctrl.v + wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v + wire rSTALL; // From ibuf of aeMB_ibuf.v + wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v + // End of automatics + + input sys_clk_i; + input sys_rst_i; + + wire grst = sys_rst_i; + wire gclk = sys_clk_i; + wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL; + wire oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i); + + // --- INSTANTIATIONS ------------------------------------- + + aeMB_ibuf + ibuf (/*AUTOINST*/ + // Outputs + .rIMM (rIMM[15:0]), + .rRA (rRA[4:0]), + .rRD (rRD[4:0]), + .rRB (rRB[4:0]), + .rALT (rALT[10:0]), + .rOPC (rOPC[5:0]), + .rSIMM (rSIMM[31:0]), + .xIREG (xIREG[31:0]), + .rSTALL (rSTALL), + .iwb_stb_o (iwb_stb_o), + // Inputs + .rBRA (rBRA), + .rMSR_IE (rMSR_IE), + .rMSR_BIP (rMSR_BIP), + .iwb_dat_i (iwb_dat_i[31:0]), + .iwb_ack_i (iwb_ack_i), + .sys_int_i (sys_int_i), + .gclk (gclk), + .grst (grst), + .gena (gena), + .oena (oena)); + + aeMB_ctrl + ctrl (/*AUTOINST*/ + // Outputs + .rMXDST (rMXDST[1:0]), + .rMXSRC (rMXSRC[1:0]), + .rMXTGT (rMXTGT[1:0]), + .rMXALT (rMXALT[1:0]), + .rMXALU (rMXALU[2:0]), + .rRW (rRW[4:0]), + .dwb_stb_o (dwb_stb_o), + .dwb_wre_o (dwb_wre_o), + .fsl_stb_o (fsl_stb_o), + .fsl_wre_o (fsl_wre_o), + // Inputs + .rDLY (rDLY), + .rIMM (rIMM[15:0]), + .rALT (rALT[10:0]), + .rOPC (rOPC[5:0]), + .rRD (rRD[4:0]), + .rRA (rRA[4:0]), + .rRB (rRB[4:0]), + .rPC (rPC[31:2]), + .rBRA (rBRA), + .rMSR_IE (rMSR_IE), + .xIREG (xIREG[31:0]), + .dwb_ack_i (dwb_ack_i), + .iwb_ack_i (iwb_ack_i), + .fsl_ack_i (fsl_ack_i), + .gclk (gclk), + .grst (grst), + .gena (gena)); + + aeMB_bpcu #(IW) + bpcu (/*AUTOINST*/ + // Outputs + .iwb_adr_o (iwb_adr_o[IW-1:2]), + .rPC (rPC[31:2]), + .rPCLNK (rPCLNK[31:2]), + .rBRA (rBRA), + .rDLY (rDLY), + // Inputs + .rMXALT (rMXALT[1:0]), + .rOPC (rOPC[5:0]), + .rRD (rRD[4:0]), + .rRA (rRA[4:0]), + .rRESULT (rRESULT[31:0]), + .rDWBDI (rDWBDI[31:0]), + .rREGA (rREGA[31:0]), + .gclk (gclk), + .grst (grst), + .gena (gena)); + + aeMB_regf + regf (/*AUTOINST*/ + // Outputs + .rREGA (rREGA[31:0]), + .rREGB (rREGB[31:0]), + .rDWBDI (rDWBDI[31:0]), + .dwb_dat_o (dwb_dat_o[31:0]), + .fsl_dat_o (fsl_dat_o[31:0]), + // Inputs + .rOPC (rOPC[5:0]), + .rRA (rRA[4:0]), + .rRB (rRB[4:0]), + .rRW (rRW[4:0]), + .rRD (rRD[4:0]), + .rMXDST (rMXDST[1:0]), + .rPCLNK (rPCLNK[31:2]), + .rRESULT (rRESULT[31:0]), + .rDWBSEL (rDWBSEL[3:0]), + .rBRA (rBRA), + .rDLY (rDLY), + .dwb_dat_i (dwb_dat_i[31:0]), + .fsl_dat_i (fsl_dat_i[31:0]), + .gclk (gclk), + .grst (grst), + .gena (gena)); + + aeMB_xecu #(DW, MUL, BSF) + xecu (/*AUTOINST*/ + // Outputs + .dwb_adr_o (dwb_adr_o[DW-1:2]), + .dwb_sel_o (dwb_sel_o[3:0]), + .fsl_adr_o (fsl_adr_o[6:2]), + .fsl_tag_o (fsl_tag_o[1:0]), + .rRESULT (rRESULT[31:0]), + .rDWBSEL (rDWBSEL[3:0]), + .rMSR_IE (rMSR_IE), + .rMSR_BIP (rMSR_BIP), + // Inputs + .rREGA (rREGA[31:0]), + .rREGB (rREGB[31:0]), + .rMXSRC (rMXSRC[1:0]), + .rMXTGT (rMXTGT[1:0]), + .rRA (rRA[4:0]), + .rRB (rRB[4:0]), + .rMXALU (rMXALU[2:0]), + .rBRA (rBRA), + .rDLY (rDLY), + .rALT (rALT[10:0]), + .rSTALL (rSTALL), + .rSIMM (rSIMM[31:0]), + .rIMM (rIMM[15:0]), + .rOPC (rOPC[5:0]), + .rRD (rRD[4:0]), + .rDWBDI (rDWBDI[31:0]), + .rPC (rPC[31:2]), + .gclk (gclk), + .grst (grst), + .gena (gena)); + + +endmodule // aeMB_edk32 + +/* + $Log: aeMB_edk32.v,v $ + Revision 1.14 2008/01/19 16:01:22 sybreon + Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) + + Revision 1.13 2007/12/25 22:15:09 sybreon + Stalls pipeline on MUL/BSF instructions results in minor speed improvements. + + Revision 1.12 2007/12/23 20:40:44 sybreon + Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. + + Revision 1.11 2007/11/30 17:08:29 sybreon + Moved simulation kernel into code. + + Revision 1.10 2007/11/16 21:52:03 sybreon + Added fsl_tag_o to FSL bus (tag either address or data). + + Revision 1.9 2007/11/14 23:19:24 sybreon + Fixed minor typo. + + Revision 1.8 2007/11/14 22:14:34 sybreon + Changed interrupt handling system (reported by M. Ettus). + + Revision 1.7 2007/11/10 16:39:38 sybreon + Upgraded license to LGPLv3. + Significant performance optimisations. + + Revision 1.6 2007/11/09 20:51:52 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.5 2007/11/08 17:48:14 sybreon + Fixed data WISHBONE arbitration problem (reported by J Lee). + + Revision 1.4 2007/11/08 14:17:47 sybreon + Parameterised optional components. + + Revision 1.3 2007/11/03 08:34:55 sybreon + Minor code cleanup. + + Revision 1.2 2007/11/02 19:20:58 sybreon + Added better (beta) interrupt support. + Changed MSR_IE to disabled at reset as per MB docs. + + Revision 1.1 2007/11/02 03:25:40 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. +*/ \ No newline at end of file diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v new file mode 100644 index 00000000..b3e37c44 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v @@ -0,0 +1,192 @@ +/* $Id: aeMB_ibuf.v,v 1.10 2008/01/21 01:02:26 sybreon Exp $ +** +** AEMB INSTRUCTION BUFFER +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aeMB_ibuf (/*AUTOARG*/ + // Outputs + rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o, + // Inputs + rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk, + grst, gena, oena + ); + // INTERNAL + output [15:0] rIMM; + output [4:0] rRA, rRD, rRB; + output [10:0] rALT; + output [5:0] rOPC; + output [31:0] rSIMM; + output [31:0] xIREG; + output rSTALL; + + input rBRA; + //input [1:0] rXCE; + input rMSR_IE; + input rMSR_BIP; + + // INST WISHBONE + output iwb_stb_o; + input [31:0] iwb_dat_i; + input iwb_ack_i; + + // SYSTEM + input sys_int_i; + + // SYSTEM + input gclk, grst, gena, oena; + + reg [15:0] rIMM; + reg [4:0] rRA, rRD; + reg [5:0] rOPC; + + // FIXME: Endian + wire [31:0] wIDAT = iwb_dat_i; + assign {rRB, rALT} = rIMM; + + // TODO: Assign to FIFO not full. + assign iwb_stb_o = 1'b1; + + reg [31:0] rSIMM, xSIMM; + reg rSTALL; + + wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08 + wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10 + wire [31:0] wBRKOP = 32'hBA0C0018; // Vector 0x18 + wire [31:0] wBRAOP = 32'h88000000; // NOP for branches + + wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT}; + reg [31:0] xIREG; + + + // --- INTERRUPT LATCH -------------------------------------- + // Debounce and latch onto the positive level. This is independent + // of the pipeline so that stalls do not affect it. + + reg rFINT; + reg [1:0] rDINT; + wire wSHOT = rDINT[0]; + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rDINT <= 2'h0; + rFINT <= 1'h0; + // End of automatics + end else begin + if (rMSR_IE) + rDINT <= #1 + {rDINT[0], sys_int_i}; + + rFINT <= #1 + //(wIREG == wINTOP) ? 1'b0 : + (rFINT | wSHOT) & rMSR_IE; + end + + wire fIMM = (rOPC == 6'o54); + wire fRTD = (rOPC == 6'o55); + wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)); + wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57)); + + // --- DELAY SLOT ------------------------------------------- + + always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT + or wBRAOP or wIDAT or wINTOP) begin + xIREG <= (rBRA) ? wBRAOP : + (!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP : + wIDAT; + end + + always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin + xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} : + {rIMM, wIDAT[15:0]}; + end + + // --- PIPELINE -------------------------------------------- + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rIMM <= 16'h0; + rOPC <= 6'h0; + rRA <= 5'h0; + rRD <= 5'h0; + rSIMM <= 32'h0; + // End of automatics + end else if (gena) begin + {rOPC, rRD, rRA, rIMM} <= #1 xIREG; + rSIMM <= #1 xSIMM; + end + + // --- STALL FOR MUL/BSF ----------------------------------- + + wire [5:0] wOPC = xIREG[31:26]; + + wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30); + wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31); + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rSTALL <= 1'h0; + // End of automatics + end else begin + rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL); + end + +endmodule // aeMB_ibuf + +/* + $Log: aeMB_ibuf.v,v $ + Revision 1.10 2008/01/21 01:02:26 sybreon + Patch interrupt bug. + + Revision 1.9 2008/01/19 16:01:22 sybreon + Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) + + Revision 1.8 2007/12/25 22:15:09 sybreon + Stalls pipeline on MUL/BSF instructions results in minor speed improvements. + + Revision 1.7 2007/11/22 15:11:15 sybreon + Change interrupt to positive level triggered interrupts. + + Revision 1.6 2007/11/14 23:39:51 sybreon + Fixed interrupt signal synchronisation. + + Revision 1.5 2007/11/14 22:14:34 sybreon + Changed interrupt handling system (reported by M. Ettus). + + Revision 1.4 2007/11/10 16:39:38 sybreon + Upgraded license to LGPLv3. + Significant performance optimisations. + + Revision 1.3 2007/11/03 08:34:55 sybreon + Minor code cleanup. + + Revision 1.2 2007/11/02 19:20:58 sybreon + Added better (beta) interrupt support. + Changed MSR_IE to disabled at reset as per MB docs. + + Revision 1.1 2007/11/02 03:25:40 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. +*/ \ No newline at end of file diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_regf.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_regf.v new file mode 100644 index 00000000..9ac45299 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_regf.v @@ -0,0 +1,241 @@ +// $Id: aeMB_regf.v,v 1.3 2007/11/10 16:39:38 sybreon Exp $ +// +// AEMB REGISTER FILE +// +// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +// +// This file is part of AEMB. +// +// AEMB is free software: you can redistribute it and/or modify it +// under the terms of the GNU Lesser General Public License as +// published by the Free Software Foundation, either version 3 of the +// License, or (at your option) any later version. +// +// AEMB is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +// Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with AEMB. If not, see . +// +// $Log: aeMB_regf.v,v $ +// Revision 1.3 2007/11/10 16:39:38 sybreon +// Upgraded license to LGPLv3. +// Significant performance optimisations. +// +// Revision 1.2 2007/11/09 20:51:52 sybreon +// Added GET/PUT support through a FSL bus. +// +// Revision 1.1 2007/11/02 03:25:41 sybreon +// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. +// Fixed various minor data hazard bugs. +// Code compatible with -O0/1/2/3/s generated code. +// + +module aeMB_regf (/*AUTOARG*/ + // Outputs + rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o, + // Inputs + rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA, + rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena + ); + // INTERNAL + output [31:0] rREGA, rREGB; + output [31:0] rDWBDI; + input [5:0] rOPC; + input [4:0] rRA, rRB, rRW, rRD; + input [1:0] rMXDST; + input [31:2] rPCLNK; + input [31:0] rRESULT; + input [3:0] rDWBSEL; + input rBRA, rDLY; + + // DATA WISHBONE + output [31:0] dwb_dat_o; + input [31:0] dwb_dat_i; + + // FSL WISHBONE + output [31:0] fsl_dat_o; + input [31:0] fsl_dat_i; + + // SYSTEM + input gclk, grst, gena; + + // --- LOAD SIZER ---------------------------------------------- + // Moves the data bytes around depending on the size of the + // operation. + + wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian + wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian + + reg [31:0] rDWBDI; + reg [1:0] rSIZ; + + always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin + /* 51.2 + case (rSIZ) + // FSL + 2'o3: rDWBDI <= wFSLDI; + // 32'bit + 2'o2: rDWBDI <= wDWBDI; + // 16'bit + 2'o1: case (rRESULT[1]) + 1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]}; + 1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]}; + endcase // case (rRESULT[1]) + // 8'bit + 2'o0: case (rRESULT[1:0]) + 2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]}; + 2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]}; + 2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]}; + 2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]}; + endcase // case (rRESULT[1:0]) + endcase // case (rSIZ) + */ + + /* 50.6 + case ({rSIZ, rRESULT[1:0]}) + // FSL + 4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI; + // 32'bit + 4'h8: rDWBDI <= wDWBDI; + // 16'bit + 4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]}; + 4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]}; + // 8'bit + 4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]}; + 4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]}; + 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]}; + 4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]}; + default: rDWBDI <= 32'hX; + endcase // case (rSIZ) + */ + + // 52.0 + case (rDWBSEL) + // 8'bit + 4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]}; + 4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]}; + 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]}; + 4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]}; + // 16'bit + 4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]}; + 4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]}; + // 32'bit + 4'hF: rDWBDI <= wDWBDI; + // FSL + 4'h0: rDWBDI <= wFSLDI; + // Undefined + default: rDWBDI <= 32'hX; + endcase + + end + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rSIZ <= 2'h0; + // End of automatics + end else if (gena) begin + rSIZ <= rOPC[1:0]; + end + + // --- GENERAL PURPOSE REGISTERS (R0-R31) ----------------------- + // LUT RAM implementation is smaller and faster. R0 gets written + // during reset with 0x00 and doesn't change after. + + reg [31:0] mARAM[0:31], + mBRAM[0:31], + mDRAM[0:31]; + + wire [31:0] rREGW = mDRAM[rRW]; + wire [31:0] rREGD = mDRAM[rRD]; + assign rREGA = mARAM[rRA]; + assign rREGB = mBRAM[rRB]; + + wire fRDWE = |rRW; + + reg [31:0] xWDAT; + + always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW + or rRESULT) + case (rMXDST) + 2'o2: xWDAT <= rDWBDI; + 2'o1: xWDAT <= {rPCLNK, 2'o0}; + 2'o0: xWDAT <= rRESULT; + 2'o3: xWDAT <= rREGW; // No change + endcase // case (rMXDST) + + always @(posedge gclk) + if (grst | fRDWE) begin + mARAM[rRW] <= xWDAT; + mBRAM[rRW] <= xWDAT; + mDRAM[rRW] <= xWDAT; + end + + // --- STORE SIZER --------------------------------------------- + // Replicates the data bytes across depending on the size of the + // operation. + + reg [31:0] rDWBDO, xDWBDO; + + wire [31:0] xFSL; + wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE; + wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE; + + assign fsl_dat_o = rDWBDO; + assign xFSL = (fFFWD_M) ? rDWBDI : + (fFFWD_R) ? rRESULT : + rREGA; + + wire [31:0] xDST; + wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE; + wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE; + + assign dwb_dat_o = rDWBDO; + assign xDST = (fDFWD_M) ? rDWBDI : + (fDFWD_R) ? rRESULT : + rREGD; + + always @(/*AUTOSENSE*/rOPC or xDST or xFSL) + case (rOPC[1:0]) + // 8'bit + 2'h0: xDWBDO <= {(4){xDST[7:0]}}; + // 16'bit + 2'h1: xDWBDO <= {(2){xDST[15:0]}}; + // 32'bit + 2'h2: xDWBDO <= xDST; + // FSL + 2'h3: xDWBDO <= xFSL; + //default: xDWBDO <= 32'hX; + endcase // case (rOPC[1:0]) + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rDWBDO <= 32'h0; + // End of automatics + end else if (gena) begin + rDWBDO <= #1 xDWBDO; + end + + // --- SIMULATION ONLY ------------------------------------------ + // Randomise memory to simulate real-world memory + // synopsys translate_off + + integer i; + initial begin + for (i=0; i<32; i=i+1) begin + mARAM[i] <= $random; + mBRAM[i] <= $random; + mDRAM[i] <= $random; + end + end + + // synopsys translate_on + + +endmodule // aeMB_regf diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v new file mode 100644 index 00000000..1e70a631 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v @@ -0,0 +1,306 @@ +/* $Id: aeMB_sim.v,v 1.1 2007/12/23 20:40:45 sybreon Exp $ +** +** AEMB EDK 3.2 Compatible Core +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aeMB_sim (/*AUTOARG*/ + // Outputs + iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o, + fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o, + // Inputs + sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, + fsl_ack_i, dwb_dat_i, dwb_ack_i + ); + // Bus widths + parameter IW = 32; /// Instruction bus address width + parameter DW = 32; /// Data bus address width + + // Optional functions + parameter MUL = 1; // Multiplier + parameter BSF = 1; // Barrel Shifter + + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [DW-1:2] dwb_adr_o; // From cpu of aeMB_edk32.v + output [31:0] dwb_dat_o; // From cpu of aeMB_edk32.v + output [3:0] dwb_sel_o; // From cpu of aeMB_edk32.v + output dwb_stb_o; // From cpu of aeMB_edk32.v + output dwb_wre_o; // From cpu of aeMB_edk32.v + output [6:2] fsl_adr_o; // From cpu of aeMB_edk32.v + output [31:0] fsl_dat_o; // From cpu of aeMB_edk32.v + output fsl_stb_o; // From cpu of aeMB_edk32.v + output [1:0] fsl_tag_o; // From cpu of aeMB_edk32.v + output fsl_wre_o; // From cpu of aeMB_edk32.v + output [IW-1:2] iwb_adr_o; // From cpu of aeMB_edk32.v + output iwb_stb_o; // From cpu of aeMB_edk32.v + // End of automatics + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input dwb_ack_i; // To cpu of aeMB_edk32.v + input [31:0] dwb_dat_i; // To cpu of aeMB_edk32.v + input fsl_ack_i; // To cpu of aeMB_edk32.v + input [31:0] fsl_dat_i; // To cpu of aeMB_edk32.v + input iwb_ack_i; // To cpu of aeMB_edk32.v + input [31:0] iwb_dat_i; // To cpu of aeMB_edk32.v + input sys_clk_i; // To cpu of aeMB_edk32.v + input sys_int_i; // To cpu of aeMB_edk32.v + input sys_rst_i; // To cpu of aeMB_edk32.v + // End of automatics + /*AUTOWIRE*/ + + aeMB_edk32 + #(/*AUTOINSTPARAM*/ + // Parameters + .IW (IW), + .DW (DW), + .MUL (MUL), + .BSF (BSF)) + cpu + (/*AUTOINST*/ + // Outputs + .dwb_adr_o (dwb_adr_o[DW-1:2]), + .dwb_dat_o (dwb_dat_o[31:0]), + .dwb_sel_o (dwb_sel_o[3:0]), + .dwb_stb_o (dwb_stb_o), + .dwb_wre_o (dwb_wre_o), + .fsl_adr_o (fsl_adr_o[6:2]), + .fsl_dat_o (fsl_dat_o[31:0]), + .fsl_stb_o (fsl_stb_o), + .fsl_tag_o (fsl_tag_o[1:0]), + .fsl_wre_o (fsl_wre_o), + .iwb_adr_o (iwb_adr_o[IW-1:2]), + .iwb_stb_o (iwb_stb_o), + // Inputs + .dwb_ack_i (dwb_ack_i), + .dwb_dat_i (dwb_dat_i[31:0]), + .fsl_ack_i (fsl_ack_i), + .fsl_dat_i (fsl_dat_i[31:0]), + .iwb_ack_i (iwb_ack_i), + .iwb_dat_i (iwb_dat_i[31:0]), + .sys_int_i (sys_int_i), + .sys_clk_i (sys_clk_i), + .sys_rst_i (sys_rst_i)); + + // --- SIMULATION KERNEL ---------------------------------- + // synopsys translate_off + + wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0}; + wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0}; + wire [1:0] wBRA = {cpu.rBRA, cpu.rDLY}; + wire [3:0] wMSR = {cpu.xecu.rMSR_BIP, cpu.xecu.rMSR_C, cpu.xecu.rMSR_IE, cpu.xecu.rMSR_BE}; + + always @(posedge cpu.gclk) begin + if (cpu.gena) begin + + $write ("\n", ($stime/10)); + $writeh (" PC=", iwb_adr ); + $writeh ("\t"); + + case (wBRA) + 2'b00: $write(" "); + 2'b01: $write("."); + 2'b10: $write("-"); + 2'b11: $write("+"); + endcase // case (cpu.wBRA) + + case (cpu.rOPC) + 6'o00: if (cpu.rRD == 0) $write(" "); else $write("ADD"); + 6'o01: $write("RSUB"); + 6'o02: $write("ADDC"); + 6'o03: $write("RSUBC"); + 6'o04: $write("ADDK"); + 6'o05: case (cpu.rIMM[1:0]) + 2'o0: $write("RSUBK"); + 2'o1: $write("CMP"); + 2'o3: $write("CMPU"); + default: $write("XXX"); + endcase // case (cpu.rIMM[1:0]) + 6'o06: $write("ADDKC"); + 6'o07: $write("RSUBKC"); + + 6'o10: $write("ADDI"); + 6'o11: $write("RSUBI"); + 6'o12: $write("ADDIC"); + 6'o13: $write("RSUBIC"); + 6'o14: $write("ADDIK"); + 6'o15: $write("RSUBIK"); + 6'o16: $write("ADDIKC"); + 6'o17: $write("RSUBIKC"); + + 6'o20: $write("MUL"); + 6'o21: case (cpu.rALT[10:9]) + 2'o0: $write("BSRL"); + 2'o1: $write("BSRA"); + 2'o2: $write("BSLL"); + default: $write("XXX"); + endcase // case (cpu.rALT[10:9]) + 6'o22: $write("IDIV"); + + 6'o30: $write("MULI"); + 6'o31: case (cpu.rALT[10:9]) + 2'o0: $write("BSRLI"); + 2'o1: $write("BSRAI"); + 2'o2: $write("BSLLI"); + default: $write("XXX"); + endcase // case (cpu.rALT[10:9]) + 6'o33: case (cpu.rRB[4:2]) + 3'o0: $write("GET"); + 3'o4: $write("PUT"); + 3'o2: $write("NGET"); + 3'o6: $write("NPUT"); + 3'o1: $write("CGET"); + 3'o5: $write("CPUT"); + 3'o3: $write("NCGET"); + 3'o7: $write("NCPUT"); + endcase // case (cpu.rRB[4:2]) + + 6'o40: $write("OR"); + 6'o41: $write("AND"); + 6'o42: if (cpu.rRD == 0) $write(" "); else $write("XOR"); + 6'o43: $write("ANDN"); + 6'o44: case (cpu.rIMM[6:5]) + 2'o0: $write("SRA"); + 2'o1: $write("SRC"); + 2'o2: $write("SRL"); + 2'o3: if (cpu.rIMM[0]) $write("SEXT16"); else $write("SEXT8"); + endcase // case (cpu.rIMM[6:5]) + + 6'o45: $write("MOV"); + 6'o46: case (cpu.rRA[3:2]) + 3'o0: $write("BR"); + 3'o1: $write("BRL"); + 3'o2: $write("BRA"); + 3'o3: $write("BRAL"); + endcase // case (cpu.rRA[3:2]) + + 6'o47: case (cpu.rRD[2:0]) + 3'o0: $write("BEQ"); + 3'o1: $write("BNE"); + 3'o2: $write("BLT"); + 3'o3: $write("BLE"); + 3'o4: $write("BGT"); + 3'o5: $write("BGE"); + default: $write("XXX"); + endcase // case (cpu.rRD[2:0]) + + 6'o50: $write("ORI"); + 6'o51: $write("ANDI"); + 6'o52: $write("XORI"); + 6'o53: $write("ANDNI"); + 6'o54: $write("IMMI"); + 6'o55: case (cpu.rRD[1:0]) + 2'o0: $write("RTSD"); + 2'o1: $write("RTID"); + 2'o2: $write("RTBD"); + default: $write("XXX"); + endcase // case (cpu.rRD[1:0]) + 6'o56: case (cpu.rRA[3:2]) + 3'o0: $write("BRI"); + 3'o1: $write("BRLI"); + 3'o2: $write("BRAI"); + 3'o3: $write("BRALI"); + endcase // case (cpu.rRA[3:2]) + 6'o57: case (cpu.rRD[2:0]) + 3'o0: $write("BEQI"); + 3'o1: $write("BNEI"); + 3'o2: $write("BLTI"); + 3'o3: $write("BLEI"); + 3'o4: $write("BGTI"); + 3'o5: $write("BGEI"); + default: $write("XXX"); + endcase // case (cpu.rRD[2:0]) + + 6'o60: $write("LBU"); + 6'o61: $write("LHU"); + 6'o62: $write("LW"); + 6'o64: $write("SB"); + 6'o65: $write("SH"); + 6'o66: $write("SW"); + + 6'o70: $write("LBUI"); + 6'o71: $write("LHUI"); + 6'o72: $write("LWI"); + 6'o74: $write("SBI"); + 6'o75: $write("SHI"); + 6'o76: $write("SWI"); + + default: $write("XXX"); + endcase // case (cpu.rOPC) + + case (cpu.rOPC[3]) + 1'b1: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM); + 1'b0: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB," "); + endcase // case (cpu.rOPC[3]) + + + // ALU + $write("\t"); + $writeh(" A=",cpu.xecu.rOPA); + $writeh(" B=",cpu.xecu.rOPB); + + case (cpu.rMXALU) + 3'o0: $write(" ADD"); + 3'o1: $write(" LOG"); + 3'o2: $write(" SFT"); + 3'o3: $write(" MOV"); + 3'o4: $write(" MUL"); + 3'o5: $write(" BSF"); + default: $write(" XXX"); + endcase // case (cpu.rMXALU) + $writeh("=h",cpu.xecu.xRESULT); + + // WRITEBACK + $writeh("\tSR=", wMSR," "); + + if (cpu.regf.fRDWE) begin + case (cpu.rMXDST) + 2'o2: begin + if (dwb_stb_o) $writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")"); + if (fsl_stb_o) $writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")"); + end + 2'o1: $writeh("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")"); + 2'o0: $writeh("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")"); + endcase // case (cpu.rMXDST) + end + + // STORE + if (dwb_stb_o & dwb_wre_o) begin + $writeh("RAM(", dwb_adr ,")=", dwb_dat_o); + case (dwb_sel_o) + 4'hF: $write(":L"); + 4'h3,4'hC: $write(":W"); + 4'h1,4'h2,4'h4,4'h8: $write(":B"); + endcase // case (dwb_sel_o) + + end + + end // if (cpu.gena) + + end // always @ (posedge cpu.gclk) + + // synopsys translate_on + +endmodule // aeMB_sim + +/* + $Log: aeMB_sim.v,v $ + Revision 1.1 2007/12/23 20:40:45 sybreon + Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. + + */ \ No newline at end of file diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v new file mode 100644 index 00000000..5de2ea61 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v @@ -0,0 +1,412 @@ +/* $Id: aeMB_xecu.v,v 1.12 2008/05/11 13:48:46 sybreon Exp $ +** +** AEMB MAIN EXECUTION ALU +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aeMB_xecu (/*AUTOARG*/ + // Outputs + dwb_adr_o, dwb_sel_o, fsl_adr_o, fsl_tag_o, rRESULT, rDWBSEL, + rMSR_IE, rMSR_BIP, + // Inputs + rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT, + rSTALL, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena + ); + parameter DW=32; + + parameter MUL=0; + parameter BSF=0; + + // DATA WISHBONE + output [DW-1:2] dwb_adr_o; + output [3:0] dwb_sel_o; + + // FSL WISHBONE + output [6:2] fsl_adr_o; + output [1:0] fsl_tag_o; + + // INTERNAL + output [31:0] rRESULT; + output [3:0] rDWBSEL; + output rMSR_IE; + output rMSR_BIP; + input [31:0] rREGA, rREGB; + input [1:0] rMXSRC, rMXTGT; + input [4:0] rRA, rRB; + input [2:0] rMXALU; + input rBRA, rDLY; + input [10:0] rALT; + + input rSTALL; + input [31:0] rSIMM; + input [15:0] rIMM; + input [5:0] rOPC; + input [4:0] rRD; + input [31:0] rDWBDI; + input [31:2] rPC; + + // SYSTEM + input gclk, grst, gena; + + reg rMSR_C, xMSR_C; + reg rMSR_IE, xMSR_IE; + reg rMSR_BE, xMSR_BE; + reg rMSR_BIP, xMSR_BIP; + + wire fSKIP = rBRA & !rDLY; + + // --- OPERAND SELECT + + reg [31:0] rOPA, rOPB; + always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT) + case (rMXSRC) + 2'o0: rOPA <= rREGA; + 2'o1: rOPA <= rRESULT; + 2'o2: rOPA <= rDWBDI; + 2'o3: rOPA <= {rPC, 2'o0}; + endcase // case (rMXSRC) + + always @(/*AUTOSENSE*/rDWBDI or rMXTGT or rREGB or rRESULT or rSIMM) + case (rMXTGT) + 2'o0: rOPB <= rREGB; + 2'o1: rOPB <= rRESULT; + 2'o2: rOPB <= rDWBDI; + 2'o3: rOPB <= rSIMM; + endcase // case (rMXTGT) + + // --- ADD/SUB SELECTOR ---- + + reg rRES_ADDC; + reg [31:0] rRES_ADD; + + wire [31:0] wADD; + wire wADC; + + wire fCCC = !rOPC[5] & rOPC[1]; // & !rOPC[4] + wire fSUB = !rOPC[5] & rOPC[0]; // & !rOPC[4] + wire fCMP = !rOPC[3] & rIMM[1]; // unsigned only + wire wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust + + wire [31:0] wOPA = (fSUB) ? ~rOPA : rOPA; + wire wOPC = (fCCC) ? rMSR_C : fSUB; + + assign {wADC, wADD} = (rOPB + wOPA) + wOPC; // add carry + + always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin + {rRES_ADDC, rRES_ADD} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry + end + + // --- LOGIC SELECTOR -------------------------------------- + + reg [31:0] rRES_LOG; + always @(/*AUTOSENSE*/rOPA or rOPB or rOPC) + case (rOPC[1:0]) + 2'o0: rRES_LOG <= #1 rOPA | rOPB; + 2'o1: rRES_LOG <= #1 rOPA & rOPB; + 2'o2: rRES_LOG <= #1 rOPA ^ rOPB; + 2'o3: rRES_LOG <= #1 rOPA & ~rOPB; + endcase // case (rOPC[1:0]) + + // --- SHIFTER SELECTOR ------------------------------------ + + reg [31:0] rRES_SFT; + reg rRES_SFTC; + + always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA) + case (rIMM[6:5]) + 2'o0: {rRES_SFT, rRES_SFTC} <= #1 {rOPA[31],rOPA[31:0]}; + 2'o1: {rRES_SFT, rRES_SFTC} <= #1 {rMSR_C,rOPA[31:0]}; + 2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]}; + 2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} : + { {(24){rOPA[7]}}, rOPA[7:0], rMSR_C}; + endcase // case (rIMM[6:5]) + + // --- MOVE SELECTOR --------------------------------------- + + wire [31:0] wMSR = {rMSR_C, 3'o0, + 20'h0ED32, + 4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE}; + wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0]; + wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0]; + reg [31:0] rRES_MOV; + always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA + or wMSR) + rRES_MOV <= (fMFSR) ? wMSR : + (fMFPC) ? rPC : + (rRA[3]) ? rOPB : + rOPA; + + // --- MULTIPLIER ------------------------------------------ + // TODO: 2 stage multiplier + + reg [31:0] rRES_MUL, rRES_MUL0, xRES_MUL; + always @(/*AUTOSENSE*/rOPA or rOPB) begin + xRES_MUL <= (rOPA * rOPB); + end + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rRES_MUL <= 32'h0; + // End of automatics + end else if (rSTALL) begin + rRES_MUL <= #1 xRES_MUL; + end + + + // --- BARREL SHIFTER -------------------------------------- + + reg [31:0] rRES_BSF; + reg [31:0] xBSRL, xBSRA, xBSLL; + + // Infer a logical left barrel shifter. + always @(/*AUTOSENSE*/rOPA or rOPB) + xBSLL <= rOPA << rOPB[4:0]; + + // Infer a logical right barrel shifter. + always @(/*AUTOSENSE*/rOPA or rOPB) + xBSRL <= rOPA >> rOPB[4:0]; + + // Infer a arithmetic right barrel shifter. + always @(/*AUTOSENSE*/rOPA or rOPB) + case (rOPB[4:0]) + 5'd00: xBSRA <= rOPA; + 5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]}; + 5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]}; + 5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]}; + 5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]}; + 5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]}; + 5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]}; + 5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]}; + 5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]}; + 5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]}; + 5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]}; + 5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]}; + 5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]}; + 5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]}; + 5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]}; + 5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]}; + 5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]}; + 5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]}; + 5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]}; + 5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]}; + 5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]}; + 5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]}; + 5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]}; + 5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]}; + 5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]}; + 5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]}; + 5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]}; + 5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]}; + 5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]}; + 5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]}; + 5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]}; + 5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]}; + endcase // case (rOPB[4:0]) + + reg [31:0] rBSRL, rBSRA, rBSLL; + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rBSLL <= 32'h0; + rBSRA <= 32'h0; + rBSRL <= 32'h0; + // End of automatics + end else if (rSTALL) begin + rBSRL <= #1 xBSRL; + rBSRA <= #1 xBSRA; + rBSLL <= #1 xBSLL; + end + + always @(/*AUTOSENSE*/rALT or rBSLL or rBSRA or rBSRL) + case (rALT[10:9]) + 2'd0: rRES_BSF <= rBSRL; + 2'd1: rRES_BSF <= rBSRA; + 2'd2: rRES_BSF <= rBSLL; + default: rRES_BSF <= 32'hX; + endcase // case (rALT[10:9]) + + + // --- MSR REGISTER ----------------- + + // C + wire fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP; + wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0); + + always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU + or rOPA or rRES_ADDC or rRES_SFTC) + //if (fSKIP | |rXCE) begin + if (fSKIP) begin + xMSR_C <= rMSR_C; + end else + case (rMXALU) + 3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; + 3'o1: xMSR_C <= rMSR_C; // LOGIC + 3'o2: xMSR_C <= rRES_SFTC; // SHIFT + 3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C; + 3'o4: xMSR_C <= rMSR_C; + 3'o5: xMSR_C <= rMSR_C; + default: xMSR_C <= 1'hX; + endcase // case (rMXALU) + + // IE/BIP/BE + wire fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP; + wire fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP; + wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC); + wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE); + + always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA) + xMSR_IE <= (fINT) ? 1'b0 : + (fRTID) ? 1'b1 : + (fMTS) ? rOPA[1] : + rMSR_IE; + + always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA) + xMSR_BIP <= (fBRK) ? 1'b1 : + (fRTBD) ? 1'b0 : + (fMTS) ? rOPA[3] : + rMSR_BIP; + + always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA) + xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE; + + // --- RESULT SELECTOR ------------------------------------------- + // Selects results from functional units. + reg [31:0] rRESULT, xRESULT; + + // RESULT + always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF + or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT) + if (fSKIP) + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + xRESULT <= 32'h0; + // End of automatics + else + case (rMXALU) + 3'o0: xRESULT <= rRES_ADD; + 3'o1: xRESULT <= rRES_LOG; + 3'o2: xRESULT <= rRES_SFT; + 3'o3: xRESULT <= rRES_MOV; + 3'o4: xRESULT <= (MUL) ? rRES_MUL : 32'hX; + 3'o5: xRESULT <= (BSF) ? rRES_BSF : 32'hX; + default: xRESULT <= 32'hX; + endcase // case (rMXALU) + + // --- DATA WISHBONE ----- + + reg [3:0] rDWBSEL, xDWBSEL; + assign dwb_adr_o = rRESULT[DW-1:2]; + assign dwb_sel_o = rDWBSEL; + + always @(/*AUTOSENSE*/rOPC or wADD) + case (rOPC[1:0]) + 2'o0: case (wADD[1:0]) // 8'bit + 2'o0: xDWBSEL <= 4'h8; + 2'o1: xDWBSEL <= 4'h4; + 2'o2: xDWBSEL <= 4'h2; + 2'o3: xDWBSEL <= 4'h1; + endcase // case (wADD[1:0]) + 2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit + 2'o2: xDWBSEL <= 4'hF; // 32'bit + 2'o3: xDWBSEL <= 4'h0; // FSL + endcase // case (rOPC[1:0]) + + // --- FSL WISHBONE -------------------- + + reg [14:2] rFSLADR, xFSLADR; + + assign {fsl_adr_o, fsl_tag_o} = rFSLADR[8:2]; + + always @(/*AUTOSENSE*/rALT or rRB) begin + xFSLADR <= {rALT, rRB[3:2]}; + end + + // --- SYNC --- + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rDWBSEL <= 4'h0; + rFSLADR <= 13'h0; + rMSR_BE <= 1'h0; + rMSR_BIP <= 1'h0; + rMSR_C <= 1'h0; + rMSR_IE <= 1'h0; + rRESULT <= 32'h0; + // End of automatics + end else if (gena) begin // if (grst) + rRESULT <= #1 xRESULT; + rDWBSEL <= #1 xDWBSEL; + rMSR_C <= #1 xMSR_C; + rMSR_IE <= #1 xMSR_IE; + rMSR_BE <= #1 xMSR_BE; + rMSR_BIP <= #1 xMSR_BIP; + rFSLADR <= #1 xFSLADR; + end + +endmodule // aeMB_xecu + +/* + $Log: aeMB_xecu.v,v $ + Revision 1.12 2008/05/11 13:48:46 sybreon + Backported Adder from AEMB2_EDK62. + Fixes 64-bit math problem reported by M. Ettus. + + Revision 1.11 2008/01/19 15:57:36 sybreon + Fix MTS during interrupt vectoring bug (reported by M. Ettus). + + Revision 1.10 2007/12/25 22:15:09 sybreon + Stalls pipeline on MUL/BSF instructions results in minor speed improvements. + + Revision 1.9 2007/11/30 16:42:51 sybreon + Minor code cleanup. + + Revision 1.8 2007/11/16 21:52:03 sybreon + Added fsl_tag_o to FSL bus (tag either address or data). + + Revision 1.7 2007/11/14 22:14:34 sybreon + Changed interrupt handling system (reported by M. Ettus). + + Revision 1.6 2007/11/10 16:39:38 sybreon + Upgraded license to LGPLv3. + Significant performance optimisations. + + Revision 1.5 2007/11/09 20:51:52 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.4 2007/11/08 14:17:47 sybreon + Parameterised optional components. + + Revision 1.3 2007/11/03 08:34:55 sybreon + Minor code cleanup. + + Revision 1.2 2007/11/02 19:20:58 sybreon + Added better (beta) interrupt support. + Changed MSR_IE to disabled at reset as per MB docs. + + Revision 1.1 2007/11/02 03:25:41 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. + +*/ \ No newline at end of file diff --git a/usrp2/fpga/opencores/aemb/sim/CODE_DEBUG.sav b/usrp2/fpga/opencores/aemb/sim/CODE_DEBUG.sav new file mode 100644 index 00000000..f777173c --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/CODE_DEBUG.sav @@ -0,0 +1,16 @@ +[size] 1400 971 +[pos] -1 -1 +*-5.188574 2727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +testbench.dut.dwb_we_o +@22 +testbench.dut.dwb_sel_o[3:0] +testbench.dut.dwb_adr_o[15:0] +@28 +testbench.dut.sys_clk_i +@22 +testbench.dut.dwb_dat_o[31:0] +@821 +testbench.dut.dwb_dat_i[31:0] +@22 +testbench.dut.dwb_dat_i[31:0] diff --git a/usrp2/fpga/opencores/aemb/sim/CVS/Entries b/usrp2/fpga/opencores/aemb/sim/CVS/Entries new file mode 100644 index 00000000..bf457ae6 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/CVS/Entries @@ -0,0 +1,3 @@ +D/verilog//// +/cversim/1.5/Tue Jan 15 18:38:57 2008// +/iversim/1.5/Tue Jan 15 18:38:57 2008// diff --git a/usrp2/fpga/opencores/aemb/sim/CVS/Repository b/usrp2/fpga/opencores/aemb/sim/CVS/Repository new file mode 100644 index 00000000..c6bd1aa8 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/CVS/Repository @@ -0,0 +1 @@ +aemb/sim diff --git a/usrp2/fpga/opencores/aemb/sim/CVS/Root b/usrp2/fpga/opencores/aemb/sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/aemb/sim/CVS/Template b/usrp2/fpga/opencores/aemb/sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/aemb/sim/cversim b/usrp2/fpga/opencores/aemb/sim/cversim new file mode 100755 index 00000000..0dbb7aea --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/cversim @@ -0,0 +1,22 @@ +#!/bin/sh +# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $ +# $Log: cversim,v $ +# Revision 1.5 2007/12/11 00:44:30 sybreon +# Modified for AEMB2 +# +# Revision 1.4 2007/11/30 17:08:30 sybreon +# Moved simulation kernel into code. +# +# Revision 1.3 2007/11/05 10:59:31 sybreon +# Added random seed for simulation. +# +# Revision 1.2 2007/04/12 20:21:33 sybreon +# Moved testbench into /sim/verilog. +# Simulation cleanups. +# +# Revision 1.1 2007/03/09 17:41:55 sybreon +# initial import +# +RANDOM=$(date +%s) +echo "parameter randseed = $RANDOM;" > random.v +cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v diff --git a/usrp2/fpga/opencores/aemb/sim/iversim b/usrp2/fpga/opencores/aemb/sim/iversim new file mode 100755 index 00000000..9d2384b5 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/iversim @@ -0,0 +1,21 @@ +#!/bin/sh +# $Id: iversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $ +# $Log: iversim,v $ +# Revision 1.5 2007/12/11 00:44:30 sybreon +# Modified for AEMB2 +# +# Revision 1.4 2007/11/30 17:08:30 sybreon +# Moved simulation kernel into code. +# +# Revision 1.3 2007/11/09 20:50:51 sybreon +# Added log output to iverilog.log +# +# Revision 1.2 2007/11/05 10:59:31 sybreon +# Added random seed for simulation. +# +# Revision 1.1 2007/03/09 17:41:55 sybreon +# initial import +# +RANDOM=$(date +%s) +echo "parameter randseed = $RANDOM;" > random.v +iverilog $@ -DAEMBX_SIMULATION_KERNEL ../rtl/verilog/*.v && vvp -l iverilog.log a.out && rm a.out diff --git a/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Entries b/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Entries new file mode 100644 index 00000000..34e896e8 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Entries @@ -0,0 +1,3 @@ +/aemb2.v/1.3/Tue Jan 15 18:38:57 2008// +/edk32.v/1.12/Tue Jan 15 18:38:57 2008// +D diff --git a/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Repository b/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Repository new file mode 100644 index 00000000..ff3eabf2 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Repository @@ -0,0 +1 @@ +aemb/sim/verilog diff --git a/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Root b/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Template b/usrp2/fpga/opencores/aemb/sim/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/aemb/sim/verilog/aemb2.v b/usrp2/fpga/opencores/aemb/sim/verilog/aemb2.v new file mode 100644 index 00000000..bda1704e --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/verilog/aemb2.v @@ -0,0 +1,242 @@ +/* $Id: aemb2.v,v 1.3 2007/12/28 21:44:50 sybreon Exp $ +** +** AEMB2 TEST BENCH +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +module aemb2 (); + parameter IWB=16; + parameter DWB=16; + + parameter TXE = 0; ///< thread execution enable + + parameter MUL = 1; ///< enable hardware multiplier + parameter BSF = 1; ///< enable barrel shifter + parameter FSL = 1; ///< enable FSL bus + parameter DIV = 0; ///< enable hardware divider + +`include "random.v" + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [6:2] cwb_adr_o; // From dut of aeMB2_sim.v + wire [31:0] cwb_dat_o; // From dut of aeMB2_sim.v + wire [3:0] cwb_sel_o; // From dut of aeMB2_sim.v + wire cwb_stb_o; // From dut of aeMB2_sim.v + wire [1:0] cwb_tga_o; // From dut of aeMB2_sim.v + wire cwb_wre_o; // From dut of aeMB2_sim.v + wire [DWB-1:2] dwb_adr_o; // From dut of aeMB2_sim.v + wire dwb_cyc_o; // From dut of aeMB2_sim.v + wire [31:0] dwb_dat_o; // From dut of aeMB2_sim.v + wire [3:0] dwb_sel_o; // From dut of aeMB2_sim.v + wire dwb_stb_o; // From dut of aeMB2_sim.v + wire dwb_tga_o; // From dut of aeMB2_sim.v + wire dwb_wre_o; // From dut of aeMB2_sim.v + wire [IWB-1:2] iwb_adr_o; // From dut of aeMB2_sim.v + wire iwb_stb_o; // From dut of aeMB2_sim.v + wire iwb_tga_o; // From dut of aeMB2_sim.v + wire iwb_wre_o; // From dut of aeMB2_sim.v + // End of automatics + /*AUTOREGINPUT*/ + // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) + reg cwb_ack_i; // To dut of aeMB2_sim.v + reg dwb_ack_i; // To dut of aeMB2_sim.v + reg iwb_ack_i; // To dut of aeMB2_sim.v + reg sys_clk_i; // To dut of aeMB2_sim.v + reg sys_int_i; // To dut of aeMB2_sim.v + reg sys_rst_i; // To dut of aeMB2_sim.v + // End of automatics + + // INITIAL SETUP ////////////////////////////////////////////////////// + + //reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i; + reg svc; + integer inttime; + integer seed; + integer theend; + + always #5 sys_clk_i = ~sys_clk_i; + + initial begin + //$dumpfile("dump.vcd"); + //$dumpvars(1,dut, dut.bpcu); + end + + initial begin + seed = randseed; + theend = 0; + svc = 0; + sys_clk_i = $random(seed); + sys_rst_i = 1; + sys_int_i = 0; + #50 sys_rst_i = 0; + #3500000 $finish; + end + + // FAKE MEMORY //////////////////////////////////////////////////////// + + reg [31:0] rom [0:65535]; + reg [31:0] ram[0:65535]; + reg [31:0] dwblat; + reg [15:2] dadr, iadr; + + wire [31:0] dwb_dat_t = ram[dwb_adr_o]; + wire [31:0] iwb_dat_i = rom[iadr]; + wire [31:0] dwb_dat_i = ram[dadr]; + wire [31:0] cwb_dat_i = cwb_adr_o; + +`ifdef POSEDGE +`else // !`ifdef POSEDGE + + always @(negedge sys_clk_i) + if (sys_rst_i) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + cwb_ack_i <= 1'h0; + dwb_ack_i <= 1'h0; + iwb_ack_i <= 1'h0; + // End of automatics + end else begin + iwb_ack_i <= #1 iwb_stb_o; + dwb_ack_i <= #1 dwb_stb_o; + cwb_ack_i <= #1 cwb_stb_o; + end // else: !if(sys_rst_i) + + always @(negedge sys_clk_i) begin + iadr <= #1 iwb_adr_o; + dadr <= #1 dwb_adr_o; + + if (dwb_wre_o & dwb_stb_o) begin + case (dwb_sel_o) + 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; + 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; + 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; + 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; + 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; + 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; + 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; + endcase // case (dwb_sel_o) + end // if (dwb_we_o & dwb_stb_o) + end // always @ (negedge sys_clk_i) + +`endif // !`ifdef POSEDGE + + + integer i; + initial begin + for (i=0;i<65535;i=i+1) begin + ram[i] <= $random; + end + #1 $readmemh("dump.vmem",rom); + #1 $readmemh("dump.vmem",ram); + end + + // DISPLAY OUTPUTS /////////////////////////////////////////////////// + + integer rnd; + + always @(posedge sys_clk_i) begin + + // Interrupt Monitors + if (!dut.sim.rMSR_IE) begin + rnd = $random % 30; + inttime = $stime + 1000 + (rnd*rnd * 10); + end + if ($stime > inttime) begin + sys_int_i = 1; + svc = 0; + end + if (($stime > inttime + 500) && !svc) begin + $display("\n\t*** INTERRUPT TIMEOUT ***", inttime); + $finish; + end + if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0; + /* + if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin + svc = 1; + //$display("\nLATENCY: ", ($stime - inttime)/10); + end + */ + + // Pass/Fail Monitors + if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin + $display("\n\tFAIL"); + $finish; + end + + if (iwb_dat_i == 32'hb8000000) begin + theend = theend + 1; + end + + if (theend == 5) begin + $display("\n\t*** PASSED ALL TESTS ***"); + $finish; + end + + end // always @ (posedge sys_clk_i) + + // INTERNAL WIRING //////////////////////////////////////////////////// + + aeMB2_sim + #(/*AUTOINSTPARAM*/ + // Parameters + .IWB (IWB), + .DWB (DWB), + .TXE (TXE), + .MUL (MUL), + .BSF (BSF), + .FSL (FSL), + .DIV (DIV)) + dut (/*AUTOINST*/ + // Outputs + .cwb_adr_o (cwb_adr_o[6:2]), + .cwb_dat_o (cwb_dat_o[31:0]), + .cwb_sel_o (cwb_sel_o[3:0]), + .cwb_stb_o (cwb_stb_o), + .cwb_tga_o (cwb_tga_o[1:0]), + .cwb_wre_o (cwb_wre_o), + .dwb_adr_o (dwb_adr_o[DWB-1:2]), + .dwb_cyc_o (dwb_cyc_o), + .dwb_dat_o (dwb_dat_o[31:0]), + .dwb_sel_o (dwb_sel_o[3:0]), + .dwb_stb_o (dwb_stb_o), + .dwb_tga_o (dwb_tga_o), + .dwb_wre_o (dwb_wre_o), + .iwb_adr_o (iwb_adr_o[IWB-1:2]), + .iwb_stb_o (iwb_stb_o), + .iwb_tga_o (iwb_tga_o), + .iwb_wre_o (iwb_wre_o), + // Inputs + .cwb_ack_i (cwb_ack_i), + .cwb_dat_i (cwb_dat_i[31:0]), + .dwb_ack_i (dwb_ack_i), + .dwb_dat_i (dwb_dat_i[31:0]), + .iwb_ack_i (iwb_ack_i), + .iwb_dat_i (iwb_dat_i[31:0]), + .sys_clk_i (sys_clk_i), + .sys_int_i (sys_int_i), + .sys_rst_i (sys_rst_i)); + +endmodule // edk32 + +/* $Log $ */ + +// Local Variables: +// verilog-library-directories:("." "../../rtl/verilog/") +// verilog-library-files:("") +// End: diff --git a/usrp2/fpga/opencores/aemb/sim/verilog/edk32.v b/usrp2/fpga/opencores/aemb/sim/verilog/edk32.v new file mode 100644 index 00000000..68465e9e --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sim/verilog/edk32.v @@ -0,0 +1,288 @@ +/* $Id: edk32.v,v 1.12 2007/12/23 20:40:51 sybreon Exp $ +** +** AEMB EDK 3.2 Compatible Core TEST +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +`define AEMB_SIMULATION_KERNEL + +module edk32 (); + +`include "random.v" + + // INITIAL SETUP ////////////////////////////////////////////////////// + + reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i; + reg svc; + integer inttime; + integer seed; + integer theend; + + always #5 sys_clk_i = ~sys_clk_i; + + initial begin + //$dumpfile("dump.vcd"); + //$dumpvars(1,dut); + end + + initial begin + seed = randseed; + theend = 0; + svc = 0; + sys_clk_i = $random(seed); + sys_rst_i = 1; + sys_int_i = 0; + sys_exc_i = 0; + #50 sys_rst_i = 0; + end + + initial fork + //inttime $display("FSADFASDFSDAF"); + //#10000 sys_int_i = 1; + //#1100 sys_int_i = 0; + //#100000 $displayh("\nTest Completed."); + //#4000 $finish; + join + + + // FAKE MEMORY //////////////////////////////////////////////////////// + + wire fsl_stb_o; + wire fsl_wre_o; + wire [31:0] fsl_dat_o; + wire [31:0] fsl_dat_i; + wire [6:2] fsl_adr_o; + + wire [15:2] iwb_adr_o; + wire iwb_stb_o; + wire dwb_stb_o; + reg [31:0] rom [0:65535]; + wire [31:0] iwb_dat_i; + reg iwb_ack_i, dwb_ack_i, fsl_ack_i; + + reg [31:0] ram[0:65535]; + wire [31:0] dwb_dat_i; + reg [31:0] dwblat; + wire dwb_we_o; + reg [15:2] dadr,iadr; + wire [3:0] dwb_sel_o; + wire [31:0] dwb_dat_o; + wire [15:2] dwb_adr_o; + wire [31:0] dwb_dat_t; + + initial begin + dwb_ack_i = 0; + iwb_ack_i = 0; + fsl_ack_i = 0; + end + + assign dwb_dat_t = ram[dwb_adr_o]; + assign iwb_dat_i = ram[iadr]; + assign dwb_dat_i = ram[dadr]; + assign fsl_dat_i = fsl_adr_o; + +`ifdef POSEDGE + + always @(posedge sys_clk_i) + if (sys_rst_i) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + dwb_ack_i <= 1'h0; + fsl_ack_i <= 1'h0; + iwb_ack_i <= 1'h0; + // End of automatics + end else begin + iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i; + dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i; + fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i; + end // else: !if(sys_rst_i) + + always @(posedge sys_clk_i) begin + iadr <= #1 iwb_adr_o; + dadr <= #1 dwb_adr_o; + + if (dwb_we_o & dwb_stb_o) begin + case (dwb_sel_o) + 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; + 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; + 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; + 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; + 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; + 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; + 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; + endcase // case (dwb_sel_o) + end // if (dwb_we_o & dwb_stb_o) + end // always @ (posedge sys_clk_i) + +`else // !`ifdef POSEDGE + + always @(negedge sys_clk_i) + if (sys_rst_i) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + dwb_ack_i <= 1'h0; + fsl_ack_i <= 1'h0; + iwb_ack_i <= 1'h0; + // End of automatics + end else begin + iwb_ack_i <= #1 iwb_stb_o; + dwb_ack_i <= #1 dwb_stb_o; + fsl_ack_i <= #1 fsl_stb_o; + end // else: !if(sys_rst_i) + + always @(negedge sys_clk_i) begin + iadr <= #1 iwb_adr_o; + dadr <= #1 dwb_adr_o; + + if (dwb_we_o & dwb_stb_o) begin + case (dwb_sel_o) + 4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]}; + 4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]}; + 4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]}; + 4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]}; + 4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]}; + 4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]}; + 4'hF: ram[dwb_adr_o] <= {dwb_dat_o}; + endcase // case (dwb_sel_o) + end // if (dwb_we_o & dwb_stb_o) + end // always @ (negedge sys_clk_i) + +`endif // !`ifdef POSEDGE + + + integer i; + initial begin + for (i=0;i<65535;i=i+1) begin + ram[i] <= $random; + end + #1 $readmemh("dump.vmem",ram); + end + + // DISPLAY OUTPUTS /////////////////////////////////////////////////// + + integer rnd; + + always @(posedge sys_clk_i) begin + + // Interrupt Monitors + if (!dut.cpu.rMSR_IE) begin + rnd = $random % 30; + inttime = $stime + 1000 + (rnd*rnd * 10); + end + if ($stime > inttime) begin + sys_int_i = 1; + svc = 0; + end + if (($stime > inttime + 500) && !svc) begin + $display("\n\t*** INTERRUPT TIMEOUT ***", inttime); + $finish; + end + if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0; + if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin + svc = 1; + //$display("\nLATENCY: ", ($stime - inttime)/10); + end + + // Pass/Fail Monitors + if (dwb_we_o & (dwb_dat_o == "FAIL")) begin + $display("\n\tFAIL"); + $finish; + end + + if (iwb_dat_i == 32'hb8000000) begin + theend = theend + 1; + end + + if (theend == 5) begin + $display("\n\t*** PASSED ALL TESTS ***"); + $finish; + end + end // always @ (posedge sys_clk_i) + + // INTERNAL WIRING //////////////////////////////////////////////////// + + aeMB_sim #(16,16) + dut ( + .sys_int_i(sys_int_i), + .dwb_ack_i(dwb_ack_i), + .dwb_stb_o(dwb_stb_o), + .dwb_adr_o(dwb_adr_o), + .dwb_dat_o(dwb_dat_o), + .dwb_dat_i(dwb_dat_i), + .dwb_wre_o(dwb_we_o), + .dwb_sel_o(dwb_sel_o), + + .fsl_ack_i(fsl_ack_i), + .fsl_stb_o(fsl_stb_o), + .fsl_adr_o(fsl_adr_o), + .fsl_dat_o(fsl_dat_o), + .fsl_dat_i(fsl_dat_i), + .fsl_wre_o(fsl_we_o), + + .iwb_adr_o(iwb_adr_o), + .iwb_dat_i(iwb_dat_i), + .iwb_stb_o(iwb_stb_o), + .iwb_ack_i(iwb_ack_i), + .sys_clk_i(sys_clk_i), + .sys_rst_i(sys_rst_i) + ); + +endmodule // edk32 + +/* + $Log: edk32.v,v $ + Revision 1.12 2007/12/23 20:40:51 sybreon + Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. + + Revision 1.11 2007/12/11 00:44:31 sybreon + Modified for AEMB2 + + Revision 1.10 2007/11/30 17:08:30 sybreon + Moved simulation kernel into code. + + Revision 1.9 2007/11/20 18:36:00 sybreon + Removed unnecessary byte acrobatics with VMEM data. + + Revision 1.8 2007/11/18 19:41:45 sybreon + Minor simulation fixes. + + Revision 1.7 2007/11/14 22:11:41 sybreon + Added posedge/negedge bus interface. + Modified interrupt test system. + + Revision 1.6 2007/11/13 23:37:28 sybreon + Updated simulation to also check BRI 0x00 instruction. + + Revision 1.5 2007/11/09 20:51:53 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.4 2007/11/08 14:18:00 sybreon + Parameterised optional components. + + Revision 1.3 2007/11/05 10:59:31 sybreon + Added random seed for simulation. + + Revision 1.2 2007/11/02 19:16:10 sybreon + Added interrupt simulation. + Changed "human readable" simulation output. + + Revision 1.1 2007/11/02 03:25:45 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. + */ \ No newline at end of file diff --git a/usrp2/fpga/opencores/aemb/sw/CVS/Entries b/usrp2/fpga/opencores/aemb/sw/CVS/Entries new file mode 100644 index 00000000..45725bed --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/CVS/Entries @@ -0,0 +1,2 @@ +D/c//// +/gccrom/1.13/Sun Jan 20 19:47:57 2008// diff --git a/usrp2/fpga/opencores/aemb/sw/CVS/Repository b/usrp2/fpga/opencores/aemb/sw/CVS/Repository new file mode 100644 index 00000000..6de31b8b --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/CVS/Repository @@ -0,0 +1 @@ +aemb/sw diff --git a/usrp2/fpga/opencores/aemb/sw/CVS/Root b/usrp2/fpga/opencores/aemb/sw/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/aemb/sw/CVS/Template b/usrp2/fpga/opencores/aemb/sw/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/aemb/sw/c/CVS/Entries b/usrp2/fpga/opencores/aemb/sw/c/CVS/Entries new file mode 100644 index 00000000..4867b631 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/c/CVS/Entries @@ -0,0 +1,3 @@ +/aeMB_testbench.c/1.14/Tue Jan 15 18:38:57 2008// +/libaemb.h/1.3/Tue Jan 15 18:38:57 2008// +D diff --git a/usrp2/fpga/opencores/aemb/sw/c/CVS/Repository b/usrp2/fpga/opencores/aemb/sw/c/CVS/Repository new file mode 100644 index 00000000..86c411d0 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/c/CVS/Repository @@ -0,0 +1 @@ +aemb/sw/c diff --git a/usrp2/fpga/opencores/aemb/sw/c/CVS/Root b/usrp2/fpga/opencores/aemb/sw/c/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/c/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/aemb/sw/c/CVS/Template b/usrp2/fpga/opencores/aemb/sw/c/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/aemb/sw/c/aeMB_testbench.c b/usrp2/fpga/opencores/aemb/sw/c/aeMB_testbench.c new file mode 100644 index 00000000..c3402e0e --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/c/aeMB_testbench.c @@ -0,0 +1,385 @@ +/* $Id: aeMB_testbench.c,v 1.14 2007/12/28 21:44:04 sybreon Exp $ +** +** AEMB Function Verification C Testbench +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU General Public License as published by +** the Free Software Foundation, either version 3 of the License, or +** (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +** License for more details. +** +** You should have received a copy of the GNU General Public License +** along with AEMB. If not, see . +*/ + +#include +#include +#include + +#include "libaemb.h" + +/** + INTERRUPT TEST + + This tests for the following: + - Pointer addressing + - Interrupt handling + */ + +void __attribute__ ((interrupt_handler)) int_handler(); +volatile int service = 0xDEADDEAD; + +void int_service() +{ + int* pio = (int*)0xFFFFFFFC; + *pio = 0x52544E49; // "INTR" + service = 0; +} + +void int_handler() +{ + int_service(); +} + +/** + INTERRUPT TEST ROUTINE +*/ +int int_test () +{ + // Delay loop until hardware interrupt triggers + volatile int i; + for (i=0; i < 999; i++) { + if (service == 0) return 0; + }; + + return -1; +} + +/** + FIBONACCI TEST + http://en.literateprograms.org/Fibonacci_numbers_(C) + + This tests for the following: + - Recursion & Iteration + - 32/16/8-bit data handling +*/ + +unsigned int fib_slow(unsigned int n) +{ + return n < 2 ? n : fib_slow(n-1) + fib_slow(n-2); +} + +unsigned int fib_fast(unsigned int n) +{ + unsigned int a[3]; + unsigned int *p=a; + unsigned int i; + + for(i=0; i<=n; ++i) { + if(i<2) *p=i; + else { + if(p==a) *p=*(a+1)+*(a+2); + else if(p==a+1) *p=*a+*(a+2); + else *p=*a+*(a+1); + } + if(++p>a+2) p=a; + } + + return p==a?*(p+2):*(p-1); +} + +int fib_test(int max) { + unsigned int n; + unsigned int fast, slow; + // 32-bit LUT + unsigned int fib_lut32[] = { + 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 + }; + // 16-bit LUT + unsigned short fib_lut16[] = { + 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 + }; + // 8-bit LUT + unsigned char fib_lut8[] = { + 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 + }; + + for (n=0;n a) goto b_larger; + while (1) { + a = a % b; + if (a == 0) return b; + b_larger: + b = b % a; + if (b == 0) return a; + } +} + +int euclid_test(int max) +{ + int n; + int euclid; + // Random Numbers + int euclid_a[] = { + 1804289383, 1681692777, 1957747793, 719885386, 596516649, + 1025202362, 783368690, 2044897763, 1365180540, 304089172, + 35005211, 294702567, 336465782, 278722862 + }; + int euclid_b[] = { + 846930886, 1714636915, 424238335, 1649760492, 1189641421, + 1350490027, 1102520059, 1967513926, 1540383426, 1303455736, + 521595368, 1726956429, 861021530, 233665123 + }; + + // GCD + int euclid_lut[] = { + 1, 1, 1, 2, 1, 1, 1, 1, 6, 4, 1, 3, 2, 1 + }; + + for (n=0;n 0.0) + { + xn = (i+(i-1))/2.0; + break; + } + } + while (!(iters++ >= 100 + || x == xn)) + { + x = xn; + xn = x - (x * x - n) / (2 * x); + } + return xn; +} + +int newton_test (int max) { + int n; + float newt; + // 32-bit LUT + float newt_lut[] = { + 0.000000000000000000000000, + 1.000000000000000000000000, + 1.414213538169860839843750, + 1.732050776481628417968750, + 2.000000000000000000000000, + 2.236068010330200195312500, + 2.449489831924438476562500, + 2.645751237869262695312500, + 2.828427076339721679687500, + 3.000000000000000000000000, + 3.162277698516845703125000, + 3.316624879837036132812500, + 3.464101552963256835937500, + 3.605551242828369140625000, + 3.741657495498657226562500 + }; + + for (n=0;n_errno; + // return &errnum; +} +*/ + +int malloc_test() +{ + void *alloc; + + alloc = (void *)malloc(256); // allocate 32 bytes + + if (alloc == NULL) + return -1; + else + return (int) alloc; +} + +/** + MAIN TEST PROGRAMME + + This is the main test procedure. It will output signals onto the + MPI port that is checked by the testbench. + */ + +int main () +{ + // Message Passing Port + int* mpi = (int*)0xFFFFFFFF; + + // Number of each test to run + int max = 10; + + // lock T0 if it's multi-threaded + /* + if ((aemb_isthreaded() == 0) && (aemb_isthread1() != 0)) { + while (1) { + asm volatile ("nop;"); + } + } + */ + + // Enable Global Interrupts + aemb_enable_interrupt(); + + // INT TEST + //if (int_test() == -1) { *mpi = 0x4641494C; } + + // TEST MALLOC + if (malloc_test() == -1) { *mpi = 0x4641494C; } + + // FSL TEST + //if (fsl_test() == -1) { *mpi = 0x4641494C; } + + // Fibonacci Test + if (fib_test(max) == -1) { *mpi = 0x4641494C; } + + // Euclid Test + if (euclid_test(max) == -1) { *mpi = 0x4641494C; } + + // Newton-Rhapson Test + if (newton_test(max) == -1) { *mpi = 0x4641494C; } + + // Disable Global Interrupts + aemb_disable_interrupt(); + + // ALL PASSED + return 0; +} + +/* + HISTORY + $Log: aeMB_testbench.c,v $ + Revision 1.14 2007/12/28 21:44:04 sybreon + Added malloc() test + + Revision 1.13 2007/12/11 00:44:31 sybreon + Modified for AEMB2 + + Revision 1.12 2007/11/18 19:41:45 sybreon + Minor simulation fixes. + + Revision 1.11 2007/11/14 23:41:06 sybreon + Fixed minor interrupt test typo. + + Revision 1.10 2007/11/14 22:12:02 sybreon + Added interrupt test routine. + + Revision 1.9 2007/11/09 20:51:53 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.8 2007/11/03 08:40:18 sybreon + Minor code cleanup. + + Revision 1.7 2007/11/02 18:32:19 sybreon + Enable MSR_IE with software. + + Revision 1.6 2007/04/30 15:57:10 sybreon + Removed byte acrobatics. + + Revision 1.5 2007/04/27 15:17:59 sybreon + Added code documentation. + Added new tests that test floating point, modulo arithmetic and multiplication/division. + + Revision 1.4 2007/04/25 22:15:05 sybreon + Added support for 8-bit and 16-bit data types. + + Revision 1.3 2007/04/04 14:09:04 sybreon + Added initial interrupt/exception support. + + Revision 1.2 2007/04/04 06:07:45 sybreon + Fixed C code bug which passes the test + + Revision 1.1 2007/03/09 17:41:57 sybreon + initial import +*/ diff --git a/usrp2/fpga/opencores/aemb/sw/c/endian-test.c b/usrp2/fpga/opencores/aemb/sw/c/endian-test.c new file mode 100644 index 00000000..b585f7a3 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/c/endian-test.c @@ -0,0 +1,86 @@ + +#include "memory_map.h" + +int main() { + char *p = (char *)0x4000; + short *q = (short *)0x5000; + int *r= (int *)0x6000; + + int *output = (int *)0x7000; + + char s; + short t; + int u; + + // Write + // Bytes + *p = (char)1; + p++; + *p = (char)2; + p++; + *p = (char)3; + p++; + *p = (char)4; + p++; + *p = (char)5; + + // Words + *q = (short) 0x1112; + q++; + *q = (short) 0x1314; + q++; + *q = (short) 0x1516; + + // Double Words + *r = 0x21222324; + r++; + *r = 0x25262728; + r++; + *r = 0x292a2b2c; + + + // Read + p = (char *)0x6000; + s = *p; + if(s == 0x21) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + p = (char *)0x6001; + s = *p; + if(s == 0x22) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + p = (char *)0x6002; + s = *p; + if(s == 0x23) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + + p = (char *)0x6003; + s = *p; + if(s == 0x24) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + q = (short *)0x4000; + t = *q; + if(t == 0x0102) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + + r = (int *)0x4000; + u = *r; + if(u == 0x01020304) + *output = 0x53534150; // PASS + else + *output = 0x4C494146; // FAIL + +} diff --git a/usrp2/fpga/opencores/aemb/sw/c/libaemb.h b/usrp2/fpga/opencores/aemb/sw/c/libaemb.h new file mode 100644 index 00000000..329a327a --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/c/libaemb.h @@ -0,0 +1,218 @@ +/* $Id: libaemb.h,v 1.3 2007/12/16 03:26:37 sybreon Exp $ +** +** AEMB2 CUSTOM LIBRARY +** +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see . +*/ + +#ifndef LIBAEMB_H +#define LIBAEMB_H + +#define AEMB_TXE 0x0100 +#define AEMB_TXP 0x0400 +#define AEMB_TX0 0x0300 +#define AEMB_TX1 0x0700 +#define AEMB_MSK 0x0F00 + +#define AEMB_BIP 0x0008 +#define AEMB_CCC 0x0004 +#define AEMB_ITE 0x0002 +#define AEMB_BLE 0x0001 + + +// Linker symbols +extern void* _STACK_SIZE; +extern void* _stack_end; + + +void aemb_hook_init () asm ("_program_init"); +void aemb_hook_clean () asm ("_program_clean"); + +inline void aemb_enable_interrupt (); +inline void aemb_disable_interrupt (); +inline int aemb_isthread1(); +inline int aemb_isthread0(); +inline int aemb_isthreaded(); + +/*! +* Assembly macro to enable MSR_IE +*/ +void aemb_enable_interrupt () +{ + int msr, tmp; + asm volatile ("mfs %0, rmsr;" + "ori %1, %0, 0x02;" + "mts rmsr, %1;" + : "=r"(msr) + : "r" (tmp) + ); +} + +/*! +* Assembly macro to disable MSR_IE +*/ +void aemb_disable_interrupt () +{ + int msr, tmp; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, 0xFD;" + "mts rmsr, %1;" + : "=r"(msr) + : "r" (tmp) + ); +} + +/*! +* Bootstrap Hook Override +*/ + +void aemb_hook_init () +{ + int msr, tmp; + int stk_end, stk_siz; + + /* + // Check to see if hardware threads are enabled + if (((msr & AEMB_TXE) != AEMB_TXE) || + // Check to see if second thread is started + ((msr & AEMB_TX1) == AEMB_TX1)) return; + */ + //return; + asm volatile ("mfs %0, rmsr;" + // Check for BIP + "andi %1, %0, %5;" + "xori %1, %1, %5;" + "beqi %1, 44;" + + // Check for TXE + "andi %1, %0, %2;" + "xori %1, %1, %2;" + "bnei %1, 36;" + + // Check for TX1 + "andi %1, %0, %3;" + "xori %1, %1, %3;" + "beqi %1, 20;" + + // reallocate stack pointer for T0 + "ori %1, r0, %4;" + "sra %1, %1;" + "rsubk r1, %1, r1;" + + // reboot the machine + //"brki r0, _crtinit;" + "brid 0;" + "nop;" + + // clear BIP + "andni %1, %0, %5;" + "mts rmsr, %1;" + + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE), "i"(AEMB_BIP) + ); + +} + +/*! + Undo the changes made by programme init +*/ + +void aemb_hook_clean () +{ + int msr, tmp; + int stk_end, stk_siz; + + /* + // Check to see if hardware threads are enabled + if (((msr & AEMB_TXE) != AEMB_TXE) || + // Check to see if second thread is started + ((msr & AEMB_TX1) == AEMB_TX1)) return; + */ + return; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, %2;" + "xori %1, %1, %2;" + "bnei %1, 28;" + "andi %1, %0, %3;" + "xori %1, %1, %3;" + "beqi %1, 16;" + + // reallocate stack pointer for T0 + "ori %1, r0, %4;" + "sra %1, %1;" + "addk r1, %1, r1;" + + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE) + ); + + +} + +/* Checks if it's T1, and returns 0 if true */ + +int aemb_isthread1 () +{ + int msr, tmp, res; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, %3;" + "xori %1, %1, %3;" + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXE), "i"(AEMB_TXP) + ); + return tmp; +} + +/* Checks if it's T0, and returns 0 if true */ + +int aemb_isthread0 () +{ + int msr, tmp, res; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, %3;" + "xori %1, %1, %2;" + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXP), "i"(AEMB_MSK) + ); + return tmp; +} + +/* Checks if TXE is available, and returns 0 if true */ + +int aemb_isthreaded () +{ + int msr, tmp, res; + asm volatile ("mfs %0, rmsr;" + "andi %1, %0, %2;" + "xori %1, %1, %2;" + :"=r"(msr), "=r"(tmp) + :"i"(AEMB_TXE), "i"(AEMB_MSK) + ); + return tmp; +} + +#endif + +/* $Log: libaemb.h,v $ +/* Revision 1.3 2007/12/16 03:26:37 sybreon +/* Made T0 loop. +/* +/* Revision 1.1 2007/12/11 00:44:04 sybreon +/* initial import +/* */ diff --git a/usrp2/fpga/opencores/aemb/sw/gccrom b/usrp2/fpga/opencores/aemb/sw/gccrom new file mode 100755 index 00000000..f6e581f1 --- /dev/null +++ b/usrp2/fpga/opencores/aemb/sw/gccrom @@ -0,0 +1,62 @@ +#!/bin/sh +# $Id: gccrom,v 1.13 2008/01/19 16:42:54 sybreon Exp $ + +# Compile using C++ pre-processor +mb-g++ -g -Wl,-defsym -Wl,_HEAP_SIZE=0x800 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul -mno-clearbss $@ -o rom.elf -lc_m_bs -lm_m_bs && \ + +# Create a text listing of the compiled code +mb-objdump -DSC rom.elf > rom.dump && \ + +# Convert the ELF file to an SREC file +mb-objcopy -O srec rom.elf rom.srec && \ + +# Generate a Verilog VMEM file from the SREC file +srec_cat rom.srec -o ../sim/dump.vmem -vmem 32 && \ + +# Cleanup code +rm rom.srec && \ + +# Say Cheeze! +echo "ROM generated" + +# $Log: gccrom,v $ +# Revision 1.13 2008/01/19 16:42:54 sybreon +# Uses multiplier + barrel shifter as default. +# +# Revision 1.12 2007/12/11 00:44:32 sybreon +# Modified for AEMB2 +# +# Revision 1.11 2007/11/30 17:09:27 sybreon +# Minor code cleanup. +# +# Revision 1.10 2007/11/20 18:35:34 sybreon +# Generate VMEM instead of HEX dumps of programme. +# +# Revision 1.9 2007/11/18 19:41:46 sybreon +# Minor simulation fixes. +# +# Revision 1.8 2007/11/09 20:52:37 sybreon +# Added some compilation optimisations. +# +# Revision 1.7 2007/11/04 05:16:25 sybreon +# Added -msoft-float and -mxl-soft-div compiler flags. +# +# Revision 1.6 2007/11/02 03:25:46 sybreon +# New EDK 3.2 compatible design with optional barrel-shifter and multiplier. +# Fixed various minor data hazard bugs. +# Code compatible with -O0/1/2/3/s generated code. +# +# Revision 1.5 2007/10/22 19:14:38 sybreon +# Recommended to compile code with -O2/3/s +# +# Revision 1.4 2007/04/30 15:57:31 sybreon +# Modified compilation sequence. +# +# Revision 1.3 2007/04/25 22:15:06 sybreon +# Added support for 8-bit and 16-bit data types. +# +# Revision 1.2 2007/04/04 06:14:39 sybreon +# Minor changes +# +# Revision 1.1 2007/03/09 17:41:56 sybreon +# initial import diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Entries new file mode 100644 index 00000000..c8bbf235 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Entries @@ -0,0 +1,6 @@ +/start.tcl/1.3/Sun May 28 05:00:17 2006// +D/bench//// +D/doc//// +D/rtl//// +D/sim//// +D/syn//// diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Repository new file mode 100644 index 00000000..7c0a8c1d --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Entries new file mode 100644 index 00000000..428c5622 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Repository new file mode 100644 index 00000000..f7aa7ea6 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/bench diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Entries new file mode 100644 index 00000000..21ad451b --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Entries @@ -0,0 +1,7 @@ +/Phy_sim.v/1.3/Fri Nov 17 17:53:07 2006// +/User_int_sim.v/1.3/Fri Nov 17 17:53:07 2006// +/altera_mf.v/1.1/Thu Jan 19 14:07:50 2006// +/host_sim.v/1.1/Thu Jan 19 14:07:51 2006// +/reg_int_sim.v/1.1/Tue Dec 13 12:54:38 2005// +/tb_top.v/1.3/Thu Jan 19 14:07:51 2006// +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Repository new file mode 100644 index 00000000..614471f3 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/bench/verilog diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/Phy_sim.v b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/Phy_sim.v new file mode 100644 index 00000000..37bf364f --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/Phy_sim.v @@ -0,0 +1,102 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Phy_sim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: Phy_sim.v,v $ +// Revision 1.3 2006/11/17 17:53:07 maverickist +// no message +// +// Revision 1.2 2006/01/19 14:07:50 maverickist +// verification is complete. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +`timescale 1ns/100ps + +module Phy_sim (input Gtx_clk ,//used only in GMII mode + output Rx_clk , + output Tx_clk ,//used only in MII mode + input Tx_er , + input Tx_en , + input [7:0] Txd , + output Rx_er , + output Rx_dv , + output [7:0] Rxd , + output Crs , + output Col , + input [2:0] Speed + ); + + // //////////////////////////////////////////////////////////////////// + // this file used to simulate Phy. + // generate clk and loop the Tx data to Rx data + // full duplex mode can be verified on loop mode. + // //////////////////////////////////////////////////////////////////// + // //////////////////////////////////////////////////////////////////// + // internal signals + // //////////////////////////////////////////////////////////////////// + reg Clk_25m ;//used for 100 Mbps mode + reg Clk_2_5m ;//used for 10 Mbps mode + //wire Rx_clk ; + //wire Tx_clk ;//used only in MII mode + // //////////////////////////////////////////////////////////////////// + always + begin + #20 Clk_25m=0; + #20 Clk_25m=1; + end + + always + begin + #200 Clk_2_5m=0; + #200 Clk_2_5m=1; + end + + assign Rx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0; + assign Tx_clk=Speed[2]?Gtx_clk:Speed[1]?Clk_25m:Speed[0]?Clk_2_5m:0; + + assign Rx_dv =Tx_en ; + assign Rxd =Txd ; + assign Rx_er =0 ; + assign Crs =Tx_en ; + assign Col =0 ; + +endmodule // Phy_sim diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/User_int_sim.v b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/User_int_sim.v new file mode 100644 index 00000000..90c79b3d --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/User_int_sim.v @@ -0,0 +1,148 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// User_input_sim.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: User_int_sim.v,v $ +// Revision 1.3 2006/11/17 17:53:07 maverickist +// no message +// +// Revision 1.2 2006/01/19 14:07:50 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/13 12:15:35 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module User_int_sim (Reset , + Clk_user , + CPU_init_end , + //user inputerface , + Rx_mac_ra , + Rx_mac_rd , + Rx_mac_data , + Rx_mac_BE , + Rx_mac_pa , + Rx_mac_sop , + Rx_mac_eop , + //user inputerface , + Tx_mac_wa , + Tx_mac_wr , + Tx_mac_data , + Tx_mac_BE , + Tx_mac_sop , + Tx_mac_eop + ); + + input Reset ; + input Clk_user ; + input CPU_init_end ; + //user inputerface + input Rx_mac_ra ; + output Rx_mac_rd ; + input [31:0] Rx_mac_data ; + input [1:0] Rx_mac_BE ; + input Rx_mac_pa ; + input Rx_mac_sop ; + input Rx_mac_eop ; + //user inputerface + input Tx_mac_wa ; + output Tx_mac_wr ; + output [31:0] Tx_mac_data ; + output [1:0] Tx_mac_BE ;//big endian + output Tx_mac_sop ; + output Tx_mac_eop ; + + // //////////////////////////////////////////////////////////////////// + // inputernal signals + // //////////////////////////////////////////////////////////////////// + reg [4:0] operation; + reg [31:0] data; + reg Rx_mac_rd; + reg Start_tran; + // //////////////////////////////////////////////////////////////////// + //generate Tx user data + // //////////////////////////////////////////////////////////////////// + initial + begin + operation =0; + data =0; + end + + always @ (posedge Clk_user or posedge Reset) + if (Reset) + Start_tran <=0; + else if (Tx_mac_eop&&!Tx_mac_wa) + Start_tran <=0; + else if (Tx_mac_wa) + Start_tran <=1; + + always @ (posedge Clk_user) + if (Tx_mac_wa&&CPU_init_end) + $ip_32W_gen("../data/config.ini",operation,data); + else + begin + operation <=0; + data <=0; + end + + assign Tx_mac_data =data; + assign Tx_mac_wr =operation[4]; + assign Tx_mac_sop =operation[3]; + assign Tx_mac_eop =operation[2]; + assign Tx_mac_BE =operation[1:0]; + ////////////////////////////////////////////////////////////////////// + //verify Rx user data + ////////////////////////////////////////////////////////////////////// + always @ (posedge Clk_user or posedge Reset) + if (Reset) + Rx_mac_rd <=0; + else if(Rx_mac_ra) + Rx_mac_rd <=1; + else + Rx_mac_rd <=0; + + always @ (posedge Clk_user ) + if (Rx_mac_pa) + $ip_32W_check( Rx_mac_data, + {Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0}); + +endmodule // User_int_sim diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/altera_mf.v b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/altera_mf.v new file mode 100644 index 00000000..fffc46ff --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/altera_mf.v @@ -0,0 +1,34538 @@ +// Copyright (C) 1991-2005 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// Quartus II 5.1 Build 176 10/26/2005 + + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : ALTERA_MF_MEMORY_INITIALIZATION +// +// Description : Common function to read intel-hex format data file with +// extension .hex and creates the equivalent verilog format +// data file with extension .ver. +// +// Limitation : Supports only record type '00'(data record), '01'(end of +// file record) and '02'(extended segment address record). +// +// Results expected: Creates the verilog format data file with extension .ver +// and return the name of the file. +// +//END_MODULE_NAME-------------------------------------------------------------- + + +`timescale 1 ps / 1 ps +module lcell (in, out); + input in; + output out; + + assign out = in; +endmodule + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +`define TRUE 1 +`define FALSE 0 +`define NULL 0 +`define EOF -1 +`define MAX_BUFFER_SZ 2048 +`define MAX_NAME_SZ 128 +`define COLON ":" +`define NEWLINE "\n" +`define CARRIAGE_RETURN 8'h0D +`define SPACE " " +`define OFFSET 9 +`define H10 8'h10 +`define AWORD 8 +`define MASK15 32'h000000FF +`define EXT_STR "ver" + +// MODULE DECLARATION +module ALTERA_MF_MEMORY_INITIALIZATION; + + +/****************************************************************/ +/* Read in Intel-hex format data to verilog format data. */ +/* Intel-hex format :nnaaaaattddddcc */ +/****************************************************************/ +task convert_hex2ver; + input[`MAX_NAME_SZ*8 : 1] in_file; + input width; + output [`MAX_NAME_SZ*8 : 1] out_file; + reg [`MAX_NAME_SZ*8 : 1] in_file; + reg [`MAX_NAME_SZ*8 : 1] out_file; + reg [8:1] c; + reg [3:0] hex, tmp_char; + + integer width; + integer ifp, ofp, r, r2; + integer i, j, k, m, n; + integer done; + integer error_status; + integer first_rec; + integer last_rec; + + integer off_addr, nn, aaaa, tt, cc, aah, aal, dd, sum ; + integer line_no; + +begin +`ifdef NO_PLI +`else + `ifdef USE_RIF + `else + done = `FALSE; + error_status = `FALSE; + first_rec = `FALSE; + last_rec = `FALSE; + + off_addr= 0; + nn= 0; + aaaa= 0; + tt= 0; + cc= 0; + aah= 0; + aal= 0; + dd= 0; + sum = 0; + line_no = 1; + c = 0; + hex = 0; + + if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT")) + out_file = in_file; + else + begin + ifp = $fopen(in_file, "r"); + if (ifp == `NULL) + begin + $display("ERROR: cannot read %0s.", in_file); + done = `TRUE; + end + + out_file = in_file; + + if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX")) + out_file[3*8 : 1] = `EXT_STR; + else + begin + $display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file); + done = `TRUE; + end + + ofp = $fopen(out_file, "w"); + if (ofp == `NULL) + begin + $display("ERROR : cannot write %0s.", out_file); + done = `TRUE; + end + + while((!done) && (!error_status)) + begin : READER + + r = $fgetc(ifp); + + if (r == `EOF) + begin + if(!first_rec) + begin + error_status = `TRUE; + $display("WARNING: %0s, Intel-hex data file is empty.", in_file); + end + else if(!last_rec) + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no); + end + end + else if (r == `COLON) + begin + first_rec = `TRUE; + nn= 0; + aaaa= 0; + tt= 0; + cc= 0; + aah= 0; + aal= 0; + dd= 0; + sum = 0; + + // get record length bytes + for (i = 0; i < 2; i = i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + nn = (nn * 16) + (r - 'h30); + else if ((r >= "A") && (r <= "F")) + nn = (nn * 16) + 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + nn = (nn * 16) + 10 + (r - 'h61); + else + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + done = `TRUE; + disable READER; + end + end + + // get address bytes + for (i = 0; i < 4; i = i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + hex = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + hex = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + hex = 10 + (r - 'h61); + else + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + done = `TRUE; + disable READER; + end + + aaaa = (aaaa * 16) + hex; + + if (i < 2) + aal = (aal * 16) + hex; + else + aah = (aah * 16) + hex; + end + + // get record type bytes + for (i = 0; i < 2; i = i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + tt = (tt * 16) + (r - 'h30); + else if ((r >= "A") && (r <= "F")) + tt = (tt * 16) + 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + tt = (tt * 16) + 10 + (r - 'h61); + else + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + done = `TRUE; + disable READER; + end + end + + if((tt == 2) && (nn != 2) ) + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no); + end + else + begin + + // get the sum of all the bytes for record length, address and record types + sum = nn + aah + aal + tt ; + + // check the record type + case(tt) + // normal_record + 8'h00 : + begin + first_rec = `TRUE; + i = 0; + k = width / `AWORD; + if ((width % `AWORD) != 0) + k = k + 1; + + // k = no. of bytes per entry. + while (i < nn) + begin + $fdisplay(ofp,"@%0h", (aaaa + off_addr)); + for (j = 1; j <= k; j = j +1) + begin + if ((k - j +1) > nn) + begin + for(m = 1; m <= 2; m= m+1) + begin + if((((k-j)*8) + ((3-m)*4) - width) < 4) + $fwrite(ofp, "0"); + end + end + else + begin + // get the data bytes + for(m = 1; m <= 2; m= m+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + hex = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + hex = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + hex = 10 + (r - 'h61); + else + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + done = `TRUE; + disable READER; + end + + if((((k-j)*8) + ((3-m)*4) - width) < 4) + $fwrite(ofp, "%h", hex); + dd = (dd * 16) + hex; + + if(m % 2 == 0) + begin + sum = sum + dd; + dd = 0; + end + end + end + end + $fwrite(ofp, "\n"); + + i = i + k; + aaaa = aaaa + 1; + end // end of while (i < nn) + end + // last record + 8'h01: + begin + last_rec = `TRUE; + done = `TRUE; + end + // address base record + 8'h02: + begin + off_addr= 0; + + // get the extended segment address record + for(i = 1; i <= (nn*2); i= i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + hex = (r - 'h30); + else if ((r >= "A") && (r <= "F")) + hex = 10 + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + hex = 10 + (r - 'h61); + else + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + done = `TRUE; + disable READER; + end + + off_addr = (off_addr * `H10) + hex; + dd = (dd * 16) + hex; + + if(i % 2 == 0) + begin + sum = sum + dd; + dd = 0; + end + end + + off_addr = off_addr * `H10; + end + default: + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no); + end + endcase + + // get the checksum bytes + for (i = 0; i < 2; i = i+1) + begin + r = $fgetc(ifp); + + if ((r >= "0") && (r <= "9")) + cc = (cc * 16) + (r - 'h30); + else if ((r >= "A") && (r <= "F")) + cc = 10 + (cc * 16) + (r - 'h41); + else if ((r >= "a") && (r <= "f")) + cc = 10 + (cc * 16) + (r - 'h61); + else + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + done = `TRUE; + disable READER; + end + end + + // Perform check sum. + if(((~sum+1)& `MASK15) != cc) + begin + error_status = `TRUE; + $display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no); + end + end + end + else if ((r == `NEWLINE) || (r == `CARRIAGE_RETURN)) + begin + line_no = line_no +1; + end + else if (r == `SPACE) + begin + // continue to next character; + end + else + begin + error_status = `TRUE; + $display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no); + done = `TRUE; + end + end + $fclose(ifp); + $fclose(ofp); + end + `endif +`endif +end +endtask // convert_hex2ver + +endmodule // ALTERA_MF_MEMORY_INITIALIZATION + + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : ALTERA_DEVICE_FAMILIES +// +// Description : Common Altera device families comparison +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module ALTERA_DEVICE_FAMILIES; + +function IS_FAMILY_ACEX1K; + input[8*20:1] device; + reg is_acex1k; +begin + if ((device == "ACEX1K") || (device == "acex1k") || (device == "ACEX 1K") || (device == "acex 1k")) + is_acex1k = 1; + else + is_acex1k = 0; + + IS_FAMILY_ACEX1K = is_acex1k; +end +endfunction //IS_FAMILY_ACEX1K + +function IS_FAMILY_APEX20K; + input[8*20:1] device; + reg is_apex20k; +begin + if ((device == "APEX20K") || (device == "apex20k") || (device == "APEX 20K") || (device == "apex 20k") || (device == "RAPHAEL") || (device == "raphael")) + is_apex20k = 1; + else + is_apex20k = 0; + + IS_FAMILY_APEX20K = is_apex20k; +end +endfunction //IS_FAMILY_APEX20K + +function IS_FAMILY_APEX20KC; + input[8*20:1] device; + reg is_apex20kc; +begin + if ((device == "APEX20KC") || (device == "apex20kc") || (device == "APEX 20KC") || (device == "apex 20kc")) + is_apex20kc = 1; + else + is_apex20kc = 0; + + IS_FAMILY_APEX20KC = is_apex20kc; +end +endfunction //IS_FAMILY_APEX20KC + +function IS_FAMILY_APEX20KE; + input[8*20:1] device; + reg is_apex20ke; +begin + if ((device == "APEX20KE") || (device == "apex20ke") || (device == "APEX 20KE") || (device == "apex 20ke")) + is_apex20ke = 1; + else + is_apex20ke = 0; + + IS_FAMILY_APEX20KE = is_apex20ke; +end +endfunction //IS_FAMILY_APEX20KE + +function IS_FAMILY_APEXII; + input[8*20:1] device; + reg is_apexii; +begin + if ((device == "APEX II") || (device == "apex ii") || (device == "APEXII") || (device == "apexii") || (device == "APEX 20KF") || (device == "apex 20kf") || (device == "APEX20KF") || (device == "apex20kf")) + is_apexii = 1; + else + is_apexii = 0; + + IS_FAMILY_APEXII = is_apexii; +end +endfunction //IS_FAMILY_APEXII + +function IS_FAMILY_EXCALIBUR_ARM; + input[8*20:1] device; + reg is_excalibur_arm; +begin + if ((device == "EXCALIBUR_ARM") || (device == "excalibur_arm") || (device == "Excalibur ARM") || (device == "EXCALIBUR ARM") || (device == "excalibur arm") || (device == "ARM-BASED EXCALIBUR") || (device == "arm-based excalibur") || (device == "ARM_BASED_EXCALIBUR") || (device == "arm_based_excalibur")) + is_excalibur_arm = 1; + else + is_excalibur_arm = 0; + + IS_FAMILY_EXCALIBUR_ARM = is_excalibur_arm; +end +endfunction //IS_FAMILY_EXCALIBUR_ARM + +function IS_FAMILY_FLEX10KE; + input[8*20:1] device; + reg is_flex10ke; +begin + if ((device == "FLEX10KE") || (device == "flex10ke") || (device == "FLEX 10KE") || (device == "flex 10ke")) + is_flex10ke = 1; + else + is_flex10ke = 0; + + IS_FAMILY_FLEX10KE = is_flex10ke; +end +endfunction //IS_FAMILY_FLEX10KE + +function IS_FAMILY_MERCURY; + input[8*20:1] device; + reg is_mercury; +begin + if ((device == "Mercury") || (device == "MERCURY") || (device == "mercury") || (device == "DALI") || (device == "dali")) + is_mercury = 1; + else + is_mercury = 0; + + IS_FAMILY_MERCURY = is_mercury; +end +endfunction //IS_FAMILY_MERCURY + +function IS_FAMILY_STRATIX; + input[8*20:1] device; + reg is_stratix; +begin + if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) + is_stratix = 1; + else + is_stratix = 0; + + IS_FAMILY_STRATIX = is_stratix; +end +endfunction //IS_FAMILY_STRATIX + +function IS_FAMILY_STRATIXGX; + input[8*20:1] device; + reg is_stratixgx; +begin + if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) + is_stratixgx = 1; + else + is_stratixgx = 0; + + IS_FAMILY_STRATIXGX = is_stratixgx; +end +endfunction //IS_FAMILY_STRATIXGX + +function IS_FAMILY_CYCLONE; + input[8*20:1] device; + reg is_cyclone; +begin + if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) + is_cyclone = 1; + else + is_cyclone = 0; + + IS_FAMILY_CYCLONE = is_cyclone; +end +endfunction //IS_FAMILY_CYCLONE + +function IS_FAMILY_MAXII; + input[8*20:1] device; + reg is_maxii; +begin + if ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami")) + is_maxii = 1; + else + is_maxii = 0; + + IS_FAMILY_MAXII = is_maxii; +end +endfunction //IS_FAMILY_MAXII + +function IS_FAMILY_HARDCOPYSTRATIX; + input[8*20:1] device; + reg is_hardcopystratix; +begin + if ((device == "HardCopy Stratix") || (device == "HARDCOPY STRATIX") || (device == "hardcopy stratix") || (device == "Stratix HC") || (device == "STRATIX HC") || (device == "stratix hc") || (device == "StratixHC") || (device == "STRATIXHC") || (device == "stratixhc") || (device == "HardcopyStratix") || (device == "HARDCOPYSTRATIX") || (device == "hardcopystratix")) + is_hardcopystratix = 1; + else + is_hardcopystratix = 0; + + IS_FAMILY_HARDCOPYSTRATIX = is_hardcopystratix; +end +endfunction //IS_FAMILY_HARDCOPYSTRATIX + +function IS_FAMILY_STRATIXII; + input[8*20:1] device; + reg is_stratixii; +begin + if ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong")) + is_stratixii = 1; + else + is_stratixii = 0; + + IS_FAMILY_STRATIXII = is_stratixii; +end +endfunction //IS_FAMILY_STRATIXII + +function IS_FAMILY_STRATIXIIGX; + input[8*20:1] device; + reg is_stratixiigx; +begin + if ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx")) + is_stratixiigx = 1; + else + is_stratixiigx = 0; + + IS_FAMILY_STRATIXIIGX = is_stratixiigx; +end +endfunction //IS_FAMILY_STRATIXIIGX + +function IS_FAMILY_CYCLONEII; + input[8*20:1] device; + reg is_cycloneii; +begin + if ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan")) + is_cycloneii = 1; + else + is_cycloneii = 0; + + IS_FAMILY_CYCLONEII = is_cycloneii; +end +endfunction //IS_FAMILY_CYCLONEII + +function IS_FAMILY_HARDCOPYII; + input[8*20:1] device; + reg is_hardcopyii; +begin + if ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion")) + is_hardcopyii = 1; + else + is_hardcopyii = 0; + + IS_FAMILY_HARDCOPYII = is_hardcopyii; +end +endfunction //IS_FAMILY_HARDCOPYII + +function FEATURE_FAMILY_STRATIXGX; + input[8*20:1] device; + reg var_family_stratixgx; +begin + if (IS_FAMILY_STRATIXGX(device) ) + var_family_stratixgx = 1; + else + var_family_stratixgx = 0; + + FEATURE_FAMILY_STRATIXGX = var_family_stratixgx; +end +endfunction //FEATURE_FAMILY_STRATIXGX + +function FEATURE_FAMILY_CYCLONE; + input[8*20:1] device; + reg var_family_cyclone; +begin + if (IS_FAMILY_CYCLONE(device) ) + var_family_cyclone = 1; + else + var_family_cyclone = 0; + + FEATURE_FAMILY_CYCLONE = var_family_cyclone; +end +endfunction //FEATURE_FAMILY_CYCLONE + +function FEATURE_FAMILY_STRATIXII; + input[8*20:1] device; + reg var_family_stratixii; +begin + if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || IS_FAMILY_STRATIXIIGX(device) ) + var_family_stratixii = 1; + else + var_family_stratixii = 0; + + FEATURE_FAMILY_STRATIXII = var_family_stratixii; +end +endfunction //FEATURE_FAMILY_STRATIXII + +function FEATURE_FAMILY_STRATIX_HC; + input[8*20:1] device; + reg var_family_stratix_hc; +begin + if (IS_FAMILY_HARDCOPYSTRATIX(device) ) + var_family_stratix_hc = 1; + else + var_family_stratix_hc = 0; + + FEATURE_FAMILY_STRATIX_HC = var_family_stratix_hc; +end +endfunction //FEATURE_FAMILY_STRATIX_HC + +function FEATURE_FAMILY_STRATIX; + input[8*20:1] device; + reg var_family_stratix; +begin + if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_MAXII(device) || FEATURE_FAMILY_CYCLONEII(device) ) + var_family_stratix = 1; + else + var_family_stratix = 0; + + FEATURE_FAMILY_STRATIX = var_family_stratix; +end +endfunction //FEATURE_FAMILY_STRATIX + +function FEATURE_FAMILY_MAXII; + input[8*20:1] device; + reg var_family_maxii; +begin + if (IS_FAMILY_MAXII(device) ) + var_family_maxii = 1; + else + var_family_maxii = 0; + + FEATURE_FAMILY_MAXII = var_family_maxii; +end +endfunction //FEATURE_FAMILY_MAXII + +function FEATURE_FAMILY_CYCLONEII; + input[8*20:1] device; + reg var_family_cycloneii; +begin + if (IS_FAMILY_CYCLONEII(device) ) + var_family_cycloneii = 1; + else + var_family_cycloneii = 0; + + FEATURE_FAMILY_CYCLONEII = var_family_cycloneii; +end +endfunction //FEATURE_FAMILY_CYCLONEII + +function FEATURE_FAMILY_HAS_MEGARAM; + input[8*20:1] device; + reg var_family_has_megaram; +begin + if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_STRATIXII(device) ) + var_family_has_megaram = 1; + else + var_family_has_megaram = 0; + + FEATURE_FAMILY_HAS_MEGARAM = var_family_has_megaram; +end +endfunction //FEATURE_FAMILY_HAS_MEGARAM + +function FEATURE_FAMILY_HAS_M512; + input[8*20:1] device; + reg var_family_has_m512; +begin + if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIXGX(device) || IS_FAMILY_STRATIXII(device) || IS_FAMILY_STRATIXIIGX(device) ) + var_family_has_m512 = 1; + else + var_family_has_m512 = 0; + + FEATURE_FAMILY_HAS_M512 = var_family_has_m512; +end +endfunction //FEATURE_FAMILY_HAS_M512 + +function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM; + input[8*20:1] device; + reg var_family_has_stratixii_style_ram; +begin + if (FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_CYCLONEII(device) ) + var_family_has_stratixii_style_ram = 1; + else + var_family_has_stratixii_style_ram = 0; + + FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM = var_family_has_stratixii_style_ram; +end +endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM + +function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO; + input[8*20:1] device; + reg var_family_has_inverted_output_ddio; +begin + if (FEATURE_FAMILY_CYCLONEII(device) ) + var_family_has_inverted_output_ddio = 1; + else + var_family_has_inverted_output_ddio = 0; + + FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO = var_family_has_inverted_output_ddio; +end +endfunction //FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO + +function IS_VALID_FAMILY; + input[8*20:1] device; + reg is_valid; +begin + if (((device == "ACEX1K") || (device == "acex1k") || (device == "ACEX 1K") || (device == "acex 1k")) + || ((device == "APEX20K") || (device == "apex20k") || (device == "APEX 20K") || (device == "apex 20k") || (device == "RAPHAEL") || (device == "raphael")) + || ((device == "APEX20KC") || (device == "apex20kc") || (device == "APEX 20KC") || (device == "apex 20kc")) + || ((device == "APEX20KE") || (device == "apex20ke") || (device == "APEX 20KE") || (device == "apex 20ke")) + || ((device == "APEX II") || (device == "apex ii") || (device == "APEXII") || (device == "apexii") || (device == "APEX 20KF") || (device == "apex 20kf") || (device == "APEX20KF") || (device == "apex20kf")) + || ((device == "EXCALIBUR_ARM") || (device == "excalibur_arm") || (device == "Excalibur ARM") || (device == "EXCALIBUR ARM") || (device == "excalibur arm") || (device == "ARM-BASED EXCALIBUR") || (device == "arm-based excalibur") || (device == "ARM_BASED_EXCALIBUR") || (device == "arm_based_excalibur")) + || ((device == "FLEX10KE") || (device == "flex10ke") || (device == "FLEX 10KE") || (device == "flex 10ke")) + || ((device == "FLEX10K") || (device == "flex10k") || (device == "FLEX 10K") || (device == "flex 10k")) + || ((device == "FLEX10KA") || (device == "flex10ka") || (device == "FLEX 10KA") || (device == "flex 10ka")) + || ((device == "FLEX6000") || (device == "flex6000") || (device == "FLEX 6000") || (device == "flex 6000") || (device == "FLEX6K") || (device == "flex6k")) + || ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b")) + || ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae")) + || ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a")) + || ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s")) + || ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a")) + || ((device == "Mercury") || (device == "MERCURY") || (device == "mercury") || (device == "DALI") || (device == "dali")) + || ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) + || ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) + || ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) + || ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami")) + || ((device == "HardCopy Stratix") || (device == "HARDCOPY STRATIX") || (device == "hardcopy stratix") || (device == "Stratix HC") || (device == "STRATIX HC") || (device == "stratix hc") || (device == "StratixHC") || (device == "STRATIXHC") || (device == "stratixhc") || (device == "HardcopyStratix") || (device == "HARDCOPYSTRATIX") || (device == "hardcopystratix")) + || ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong")) + || ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx")) + || ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan")) + || ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))) + is_valid = 1; + else + is_valid = 0; + + IS_VALID_FAMILY = is_valid; +end +endfunction // IS_VALID_FAMILY + + +endmodule // ALTERA_DEVICE_FAMILIES + +/////////////////////////////////////////////////////////////////////////////// +// +// STRATIX_PLL and STRATIXII_PLL +// +/////////////////////////////////////////////////////////////////////////////// + +// DFFP +`timescale 1ps / 1ps +module dffp ( Q, CLK, ENA, D, CLRN, PRN ); + input D; + input CLK; + input CLRN; + input PRN; + input ENA; + output Q; + + + tri1 PRN, CLRN, ENA; + reg Q; + + always @ (posedge CLK or negedge CLRN or negedge PRN ) + if (PRN == 1'b0) Q = 1; + else if (CLRN == 1'b0) Q = 0; + else if ((CLK == 1) & (ENA == 1'b1)) Q = D; + endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// +// Module Name : stx_m_cntr +// +// Description : Simulation model for the M counter. This is the +// loop feedback counter for the Stratix PLL. +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +module stx_m_cntr (clk, + reset, + cout, + initial_value, + modulus, + time_delay); + + // INPUT PORTS + input clk; + input reset; + input [31:0] initial_value; + input [31:0] modulus; + input [31:0] time_delay; + + // OUTPUT PORTS + output cout; + + // INTERNAL VARIABLES AND NETS + integer count; + reg tmp_cout; + reg first_rising_edge; + reg clk_last_value; + reg cout_tmp; + + initial + begin + count = 1; + first_rising_edge = 1; + clk_last_value = 0; + end + + always @(reset or clk) + begin + if (reset) + begin + count = 1; + tmp_cout = 0; + first_rising_edge = 1; + end + else begin + if (clk == 1 && clk_last_value !== clk && first_rising_edge) + begin + first_rising_edge = 0; + tmp_cout = clk; + end + else if (first_rising_edge == 0) + begin + if (count < modulus) + count = count + 1; + else + begin + count = 1; + tmp_cout = ~tmp_cout; + end + end + end + clk_last_value = clk; + + cout_tmp <= #(time_delay) tmp_cout; + end + + and (cout, cout_tmp, 1'b1); + +endmodule // stx_m_cntr + +/////////////////////////////////////////////////////////////////////////////// +// +// Module Name : stx_n_cntr +// +// Description : Simulation model for the N counter. This is the +// input clock divide counter for the Stratix PLL. +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +module stx_n_cntr (clk, + reset, + cout, + modulus, + time_delay); + + // INPUT PORTS + input clk; + input reset; + input [31:0] modulus; + input [31:0] time_delay; + + // OUTPUT PORTS + output cout; + + // INTERNAL VARIABLES AND NETS + integer count; + reg tmp_cout; + reg first_rising_edge; + reg clk_last_value; + reg clk_last_valid_value; + reg cout_tmp; + + initial + begin + count = 1; + first_rising_edge = 1; + clk_last_value = 0; + end + + always @(reset or clk) + begin + if (reset) + begin + count = 1; + tmp_cout = 0; + first_rising_edge = 1; + end + else begin + if (clk_last_value !== clk) + begin + if (clk === 1'bx) + begin + $display("Warning : Invalid transition to 'X' detected on Stratix PLL input clk. This edge will be ignored."); + $display("Time: %0t Instance: %m", $time); + end + else if ((clk === 1'b1) && first_rising_edge) + begin + first_rising_edge = 0; + tmp_cout = clk; + end + else if ((first_rising_edge == 0) && (clk_last_valid_value !== clk)) + begin + if (count < modulus) + count = count + 1; + else + begin + count = 1; + tmp_cout = ~tmp_cout; + end + end + end + end + clk_last_value = clk; + if (clk !== 1'bx) + clk_last_valid_value = clk; + + cout_tmp <= #(time_delay) tmp_cout; + end + + and (cout, cout_tmp, 1'b1); + +endmodule // stx_n_cntr + +/////////////////////////////////////////////////////////////////////////////// +// +// Module Name : stx_scale_cntr +// +// Description : Simulation model for the output scale-down counters. +// This is a common model for the L0, L1, G0, G1, G2, G3, E0, +// E1, E2 and E3 output counters of the Stratix PLL. +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +module stx_scale_cntr (clk, + reset, + cout, + high, + low, + initial_value, + mode, + time_delay, + ph_tap); + + // INPUT PORTS + input clk; + input reset; + input [31:0] high; + input [31:0] low; + input [31:0] initial_value; + input [8*6:1] mode; + input [31:0] time_delay; + input [31:0] ph_tap; + + // OUTPUT PORTS + output cout; + + // INTERNAL VARIABLES AND NETS + reg tmp_cout; + reg first_rising_edge; + reg clk_last_value; + reg init; + integer count; + integer output_shift_count; + reg cout_tmp; + reg [31:0] high_reg; + reg [31:0] low_reg; + reg high_cnt_xfer_done; + + initial + begin + count = 1; + first_rising_edge = 0; + tmp_cout = 0; + output_shift_count = 0; + high_cnt_xfer_done = 0; + end + + always @(clk or reset) + begin + if (init !== 1'b1) + begin + high_reg = high; + low_reg = low; + clk_last_value = 0; + init = 1'b1; + end + if (reset) + begin + count = 1; + output_shift_count = 0; + tmp_cout = 0; + first_rising_edge = 0; + end + else if (clk_last_value !== clk) + begin + if (mode == "off") + tmp_cout = 0; + else if (mode == "bypass") + tmp_cout = clk; + else if (first_rising_edge == 0) + begin + if (clk == 1) + begin + output_shift_count = output_shift_count + 1; + if (output_shift_count == initial_value) + begin + tmp_cout = clk; + first_rising_edge = 1; + end + end + end + else if (output_shift_count < initial_value) + begin + if (clk == 1) + output_shift_count = output_shift_count + 1; + end + else + begin + count = count + 1; + if (mode == "even" && (count == (high_reg*2) + 1)) + begin + tmp_cout = 0; + if (high_cnt_xfer_done === 1'b1) + begin + low_reg = low; + high_cnt_xfer_done = 0; + end + end + else if (mode == "odd" && (count == (high_reg*2))) + begin + tmp_cout = 0; + if (high_cnt_xfer_done === 1'b1) + begin + low_reg = low; + high_cnt_xfer_done = 0; + end + end + else if (count == (high_reg + low_reg)*2 + 1) + begin + tmp_cout = 1; + count = 1; // reset count + if (high_reg != high) + begin + high_reg = high; + high_cnt_xfer_done = 1; + end + end + end + end + clk_last_value = clk; + cout_tmp <= #(time_delay) tmp_cout; + end + + and (cout, cout_tmp, 1'b1); + +endmodule // stx_scale_cntr + +/////////////////////////////////////////////////////////////////////////////// +// +// Module Name : MF_pll_reg +// +// Description : Simulation model for a simple DFF. +// This is required for the generation of the bit slip-signals. +// No timing, powers upto 0. +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1ps / 1ps +module MF_pll_reg (q, + clk, + ena, + d, + clrn, + prn); + + // INPUT PORTS + input d; + input clk; + input clrn; + input prn; + input ena; + + // OUTPUT PORTS + output q; + + // INTERNAL VARIABLES + reg q; + + // DEFAULT VALUES THRO' PULLUPs + tri1 prn, clrn, ena; + + initial q = 0; + + always @ (posedge clk or negedge clrn or negedge prn ) + begin + if (prn == 1'b0) + q <= 1; + else if (clrn == 1'b0) + q <= 0; + else if ((clk == 1) & (ena == 1'b1)) + q <= d; + end + +endmodule // MF_pll_reg + +////////////////////////////////////////////////////////////////////////////// +// +// Module Name : MF_stratix_pll +// +// Description : The behavioral model for Stratix PLL. +// +// Limitations : Applies to the Stratix and Stratix GX device families +// No support for spread spectrum feature in the model +// +// Outputs : Up to 10 output clocks, each defined by its own set of +// parameters. Locked output (active high) indicates when the +// PLL locks. clkbad, clkloss and activeclock are used for +// clock switchover to indicate which input clock has gone +// bad, when the clock switchover initiates and which input +// clock is being used as the reference, respectively. +// scandataout is the data output of the serial scan chain. +// +////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps +`define WORD_LENGTH 18 + +module MF_stratix_pll (inclk, + fbin, + ena, + clkswitch, + areset, + pfdena, + clkena, + extclkena, + scanclk, + scanaclr, + scandata, + clk, + extclk, + clkbad, + activeclock, + locked, + clkloss, + scandataout, + // lvds mode specific ports + comparator, + enable0, + enable1); + + parameter operation_mode = "normal"; + parameter qualify_conf_done = "off"; + parameter compensate_clock = "clk0"; + parameter pll_type = "auto"; + parameter scan_chain = "long"; + + parameter clk0_multiply_by = 1; + parameter clk0_divide_by = 1; + parameter clk0_phase_shift = 0; + parameter clk0_time_delay = 0; + parameter clk0_duty_cycle = 50; + + parameter clk1_multiply_by = 1; + parameter clk1_divide_by = 1; + parameter clk1_phase_shift = 0; + parameter clk1_time_delay = 0; + parameter clk1_duty_cycle = 50; + + parameter clk2_multiply_by = 1; + parameter clk2_divide_by = 1; + parameter clk2_phase_shift = 0; + parameter clk2_time_delay = 0; + parameter clk2_duty_cycle = 50; + + parameter clk3_multiply_by = 1; + parameter clk3_divide_by = 1; + parameter clk3_phase_shift = 0; + parameter clk3_time_delay = 0; + parameter clk3_duty_cycle = 50; + + parameter clk4_multiply_by = 1; + parameter clk4_divide_by = 1; + parameter clk4_phase_shift = 0; + parameter clk4_time_delay = 0; + parameter clk4_duty_cycle = 50; + + parameter clk5_multiply_by = 1; + parameter clk5_divide_by = 1; + parameter clk5_phase_shift = 0; + parameter clk5_time_delay = 0; + parameter clk5_duty_cycle = 50; + + parameter extclk0_multiply_by = 1; + parameter extclk0_divide_by = 1; + parameter extclk0_phase_shift = 0; + parameter extclk0_time_delay = 0; + parameter extclk0_duty_cycle = 50; + + parameter extclk1_multiply_by = 1; + parameter extclk1_divide_by = 1; + parameter extclk1_phase_shift = 0; + parameter extclk1_time_delay = 0; + parameter extclk1_duty_cycle = 50; + + parameter extclk2_multiply_by = 1; + parameter extclk2_divide_by = 1; + parameter extclk2_phase_shift = 0; + parameter extclk2_time_delay = 0; + parameter extclk2_duty_cycle = 50; + + parameter extclk3_multiply_by = 1; + parameter extclk3_divide_by = 1; + parameter extclk3_phase_shift = 0; + parameter extclk3_time_delay = 0; + parameter extclk3_duty_cycle = 50; + + parameter primary_clock = "inclk0"; + parameter inclk0_input_frequency = 10000; + parameter inclk1_input_frequency = 10000; + parameter gate_lock_signal = "no"; + parameter gate_lock_counter = 1; + parameter valid_lock_multiplier = 5; + parameter invalid_lock_multiplier = 5; + + parameter switch_over_on_lossclk = "off"; + parameter switch_over_on_gated_lock = "off"; + parameter switch_over_counter = 1; + parameter enable_switch_over_counter = "off"; + parameter feedback_source = "e0"; + parameter bandwidth = 0; + parameter bandwidth_type = "auto"; + parameter down_spread = "0.0"; + parameter spread_frequency = 0; + parameter common_rx_tx = "off"; + parameter rx_outclock_resource = "auto"; + parameter use_vco_bypass = "false"; + parameter use_dc_coupling = "false"; + + parameter pfd_min = 0; + parameter pfd_max = 0; + parameter vco_min = 0; + parameter vco_max = 0; + parameter vco_center = 0; + + // ADVANCED USE PARAMETERS + parameter m_initial = 1; + parameter m = 1; + parameter n = 1; + parameter m2 = 1; + parameter n2 = 1; + parameter ss = 0; + + parameter l0_high = 1; + parameter l0_low = 1; + parameter l0_initial = 1; + parameter l0_mode = "bypass"; + parameter l0_ph = 0; + parameter l0_time_delay = 0; + + parameter l1_high = 1; + parameter l1_low = 1; + parameter l1_initial = 1; + parameter l1_mode = "bypass"; + parameter l1_ph = 0; + parameter l1_time_delay = 0; + + parameter g0_high = 1; + parameter g0_low = 1; + parameter g0_initial = 1; + parameter g0_mode = "bypass"; + parameter g0_ph = 0; + parameter g0_time_delay = 0; + + parameter g1_high = 1; + parameter g1_low = 1; + parameter g1_initial = 1; + parameter g1_mode = "bypass"; + parameter g1_ph = 0; + parameter g1_time_delay = 0; + + parameter g2_high = 1; + parameter g2_low = 1; + parameter g2_initial = 1; + parameter g2_mode = "bypass"; + parameter g2_ph = 0; + parameter g2_time_delay = 0; + + parameter g3_high = 1; + parameter g3_low = 1; + parameter g3_initial = 1; + parameter g3_mode = "bypass"; + parameter g3_ph = 0; + parameter g3_time_delay = 0; + + parameter e0_high = 1; + parameter e0_low = 1; + parameter e0_initial = 1; + parameter e0_mode = "bypass"; + parameter e0_ph = 0; + parameter e0_time_delay = 0; + + parameter e1_high = 1; + parameter e1_low = 1; + parameter e1_initial = 1; + parameter e1_mode = "bypass"; + parameter e1_ph = 0; + parameter e1_time_delay = 0; + + parameter e2_high = 1; + parameter e2_low = 1; + parameter e2_initial = 1; + parameter e2_mode = "bypass"; + parameter e2_ph = 0; + parameter e2_time_delay = 0; + + parameter e3_high = 1; + parameter e3_low = 1; + parameter e3_initial = 1; + parameter e3_mode = "bypass"; + parameter e3_ph = 0; + parameter e3_time_delay = 0; + + parameter m_ph = 0; + parameter m_time_delay = 0; + parameter n_time_delay = 0; + + parameter extclk0_counter = "e0"; + parameter extclk1_counter = "e1"; + parameter extclk2_counter = "e2"; + parameter extclk3_counter = "e3"; + + parameter clk0_counter = "g0"; + parameter clk1_counter = "g1"; + parameter clk2_counter = "g2"; + parameter clk3_counter = "g3"; + parameter clk4_counter = "l0"; + parameter clk5_counter = "l1"; + + // LVDS mode parameters + parameter enable0_counter = "l0"; + parameter enable1_counter = "l0"; + + parameter charge_pump_current = 0; + parameter loop_filter_r = "1.0"; + parameter loop_filter_c = 1; + + parameter pll_compensation_delay = 0; + parameter simulation_type = "timing"; + + //parameter for stratix lvds + parameter clk0_phase_shift_num = 0; + parameter clk1_phase_shift_num = 0; + parameter clk2_phase_shift_num = 0; + + parameter skip_vco = "off"; + + parameter clk0_use_even_counter_mode = "off"; + parameter clk1_use_even_counter_mode = "off"; + parameter clk2_use_even_counter_mode = "off"; + parameter clk3_use_even_counter_mode = "off"; + parameter clk4_use_even_counter_mode = "off"; + parameter clk5_use_even_counter_mode = "off"; + parameter extclk0_use_even_counter_mode = "off"; + parameter extclk1_use_even_counter_mode = "off"; + parameter extclk2_use_even_counter_mode = "off"; + parameter extclk3_use_even_counter_mode = "off"; + + parameter clk0_use_even_counter_value = "off"; + parameter clk1_use_even_counter_value = "off"; + parameter clk2_use_even_counter_value = "off"; + parameter clk3_use_even_counter_value = "off"; + parameter clk4_use_even_counter_value = "off"; + parameter clk5_use_even_counter_value = "off"; + parameter extclk0_use_even_counter_value = "off"; + parameter extclk1_use_even_counter_value = "off"; + parameter extclk2_use_even_counter_value = "off"; + parameter extclk3_use_even_counter_value = "off"; + + // INPUT PORTS + input [1:0] inclk; + input fbin; + input ena; + input clkswitch; + input areset; + input pfdena; + input [5:0] clkena; + input [3:0] extclkena; + input scanclk; + input scanaclr; + input scandata; + // lvds specific input ports + input comparator; + + // OUTPUT PORTS + output [5:0] clk; + output [3:0] extclk; + output [1:0] clkbad; + output activeclock; + output locked; + output clkloss; + output scandataout; + // lvds specific output ports + output enable0; + output enable1; + + // BUFFER INPUTS + wire inclk0_ipd; + wire inclk1_ipd; + wire ena_ipd; + wire fbin_ipd; + wire areset_ipd; + wire pfdena_ipd; + wire clkena0_ipd; + wire clkena1_ipd; + wire clkena2_ipd; + wire clkena3_ipd; + wire clkena4_ipd; + wire clkena5_ipd; + wire extclkena0_ipd; + wire extclkena1_ipd; + wire extclkena2_ipd; + wire extclkena3_ipd; + wire scanclk_ipd; + wire scanaclr_ipd; + wire scandata_ipd; + wire comparator_ipd; + wire clkswitch_ipd; + + buf (inclk0_ipd, inclk[0]); + buf (inclk1_ipd, inclk[1]); + buf (ena_ipd, ena); + buf (fbin_ipd, fbin); + buf (areset_ipd, areset); + buf (pfdena_ipd, pfdena); + buf (clkena0_ipd, clkena[0]); + buf (clkena1_ipd, clkena[1]); + buf (clkena2_ipd, clkena[2]); + buf (clkena3_ipd, clkena[3]); + buf (clkena4_ipd, clkena[4]); + buf (clkena5_ipd, clkena[5]); + buf (extclkena0_ipd, extclkena[0]); + buf (extclkena1_ipd, extclkena[1]); + buf (extclkena2_ipd, extclkena[2]); + buf (extclkena3_ipd, extclkena[3]); + buf (scanclk_ipd, scanclk); + buf (scanaclr_ipd, scanaclr); + buf (scandata_ipd, scandata); + buf (comparator_ipd, comparator); + buf (clkswitch_ipd, clkswitch); + + // INTERNAL VARIABLES AND NETS + integer scan_chain_length; + integer i; + integer j; + integer k; + integer l_index; + integer gate_count; + integer egpp_offset; + integer sched_time; + integer delay_chain; + integer low; + integer high; + integer initial_delay; + integer fbk_phase; + integer fbk_delay; + integer phase_shift[0:7]; + integer last_phase_shift[0:7]; + + integer m_times_vco_period; + integer new_m_times_vco_period; + integer refclk_period; + integer fbclk_period; + integer primary_clock_frequency; + integer high_time; + integer low_time; + integer my_rem; + integer tmp_rem; + integer rem; + integer tmp_vco_per; + integer vco_per; + integer offset; + integer temp_offset; + integer cycles_to_lock; + integer cycles_to_unlock; + integer l0_count; + integer l1_count; + integer loop_xplier; + integer loop_initial; + integer loop_ph; + integer loop_time_delay; + integer cycle_to_adjust; + integer total_pull_back; + integer pull_back_M; + integer pull_back_ext_cntr; + + time fbclk_time; + time first_fbclk_time; + time refclk_time; + time scanaclr_rising_time; + time scanaclr_falling_time; + + reg got_first_refclk; + reg got_second_refclk; + reg got_first_fbclk; + reg refclk_last_value; + reg fbclk_last_value; + reg inclk_last_value; + reg pll_is_locked; + reg pll_about_to_lock; + reg locked_tmp; + reg l0_got_first_rising_edge; + reg l1_got_first_rising_edge; + reg vco_l0_last_value; + reg vco_l1_last_value; + reg areset_ipd_last_value; + reg ena_ipd_last_value; + reg pfdena_ipd_last_value; + reg inclk_out_of_range; + reg schedule_vco_last_value; + + reg gate_out; + reg vco_val; + + reg [31:0] m_initial_val; + reg [31:0] m_val; + reg [31:0] m_val_tmp; + reg [31:0] m2_val; + reg [31:0] n_val; + reg [31:0] n_val_tmp; + reg [31:0] n2_val; + reg [31:0] m_time_delay_val; + reg [31:0] n_time_delay_val; + reg [31:0] m_delay; + reg [8*6:1] m_mode_val; + reg [8*6:1] m2_mode_val; + reg [8*6:1] n_mode_val; + reg [8*6:1] n2_mode_val; + reg [31:0] l0_high_val; + reg [31:0] l0_low_val; + reg [31:0] l0_initial_val; + reg [31:0] l0_time_delay_val; + reg [8*6:1] l0_mode_val; + reg [31:0] l1_high_val; + reg [31:0] l1_low_val; + reg [31:0] l1_initial_val; + reg [31:0] l1_time_delay_val; + reg [8*6:1] l1_mode_val; + + reg [31:0] g0_high_val; + reg [31:0] g0_low_val; + reg [31:0] g0_initial_val; + reg [31:0] g0_time_delay_val; + reg [8*6:1] g0_mode_val; + + reg [31:0] g1_high_val; + reg [31:0] g1_low_val; + reg [31:0] g1_initial_val; + reg [31:0] g1_time_delay_val; + reg [8*6:1] g1_mode_val; + + reg [31:0] g2_high_val; + reg [31:0] g2_low_val; + reg [31:0] g2_initial_val; + reg [31:0] g2_time_delay_val; + reg [8*6:1] g2_mode_val; + + reg [31:0] g3_high_val; + reg [31:0] g3_low_val; + reg [31:0] g3_initial_val; + reg [31:0] g3_time_delay_val; + reg [8*6:1] g3_mode_val; + + reg [31:0] e0_high_val; + reg [31:0] e0_low_val; + reg [31:0] e0_initial_val; + reg [31:0] e0_time_delay_val; + reg [8*6:1] e0_mode_val; + + reg [31:0] e1_high_val; + reg [31:0] e1_low_val; + reg [31:0] e1_initial_val; + reg [31:0] e1_time_delay_val; + reg [8*6:1] e1_mode_val; + + reg [31:0] e2_high_val; + reg [31:0] e2_low_val; + reg [31:0] e2_initial_val; + reg [31:0] e2_time_delay_val; + reg [8*6:1] e2_mode_val; + + reg [31:0] e3_high_val; + reg [31:0] e3_low_val; + reg [31:0] e3_initial_val; + reg [31:0] e3_time_delay_val; + reg [8*6:1] e3_mode_val; + + reg scanclk_last_value; + reg scanaclr_last_value; + reg transfer; + reg transfer_enable; + reg [288:0] scan_data; + reg schedule_vco; + reg schedule_offset; + reg stop_vco; + reg inclk_n; + + reg [7:0] vco_out; + wire inclk_l0; + wire inclk_l1; + wire inclk_m; + wire clk0_tmp; + wire clk1_tmp; + wire clk2_tmp; + wire clk3_tmp; + wire clk4_tmp; + wire clk5_tmp; + wire extclk0_tmp; + wire extclk1_tmp; + wire extclk2_tmp; + wire extclk3_tmp; + wire nce_l0; + wire nce_l1; + wire nce_temp; + + reg vco_l0; + reg vco_l1; + + wire clk0; + wire clk1; + wire clk2; + wire clk3; + wire clk4; + wire clk5; + wire extclk0; + wire extclk1; + wire extclk2; + wire extclk3; + wire ena0; + wire ena1; + wire ena2; + wire ena3; + wire ena4; + wire ena5; + wire extena0; + wire extena1; + wire extena2; + wire extena3; + wire refclk; + wire fbclk; + wire l0_clk; + wire l1_clk; + wire g0_clk; + wire g1_clk; + wire g2_clk; + wire g3_clk; + wire e0_clk; + wire e1_clk; + wire e2_clk; + wire e3_clk; + wire dffa_out; + wire dffb_out; + wire dffc_out; + wire dffd_out; + wire lvds_dffb_clk; + wire lvds_dffc_clk; + wire lvds_dffd_clk; + + reg first_schedule; + + wire enable0_tmp; + wire enable1_tmp; + wire enable_0; + wire enable_1; + reg l0_tmp; + reg l1_tmp; + + reg vco_period_was_phase_adjusted; + reg phase_adjust_was_scheduled; + + // for external feedback mode + + reg [31:0] ext_fbk_cntr_high; + reg [31:0] ext_fbk_cntr_low; + reg [31:0] ext_fbk_cntr_modulus; + reg [31:0] ext_fbk_cntr_delay; + reg [8*2:1] ext_fbk_cntr; + reg [8*6:1] ext_fbk_cntr_mode; + integer ext_fbk_cntr_ph; + integer ext_fbk_cntr_initial; + + wire inclk_e0; + wire inclk_e1; + wire inclk_e2; + wire inclk_e3; + wire [31:0] cntr_e0_initial; + wire [31:0] cntr_e1_initial; + wire [31:0] cntr_e2_initial; + wire [31:0] cntr_e3_initial; + wire [31:0] cntr_e0_delay; + wire [31:0] cntr_e1_delay; + wire [31:0] cntr_e2_delay; + wire [31:0] cntr_e3_delay; + reg [31:0] ext_fbk_delay; + + // variables for clk_switch + reg clk0_is_bad; + reg clk1_is_bad; + reg inclk0_last_value; + reg inclk1_last_value; + reg other_clock_value; + reg other_clock_last_value; + reg primary_clk_is_bad; + reg current_clk_is_bad; + reg external_switch; + reg [8*6:1] current_clock; + reg active_clock; + reg clkloss_tmp; + reg got_curr_clk_falling_edge_after_clkswitch; + reg active_clk_was_switched; + + integer clk0_count; + integer clk1_count; + integer switch_over_count; + + reg scandataout_tmp; + integer quiet_time; + reg pll_in_quiet_period; + time start_quiet_time; + reg quiet_period_violation; + reg reconfig_err; + reg scanclr_violation; + reg scanclr_clk_violation; + reg got_first_scanclk_after_scanclr_inactive_edge; + reg error; + + reg no_warn; + + // internal parameters + parameter EGPP_SCAN_CHAIN = 289; + parameter GPP_SCAN_CHAIN = 193; + parameter TRST = 5000; + parameter TRSTCLK = 5000; + + // internal variables for scaling of multiply_by and divide_by values + integer i_clk0_mult_by; + integer i_clk0_div_by; + integer i_clk1_mult_by; + integer i_clk1_div_by; + integer i_clk2_mult_by; + integer i_clk2_div_by; + integer i_clk3_mult_by; + integer i_clk3_div_by; + integer i_clk4_mult_by; + integer i_clk4_div_by; + integer i_clk5_mult_by; + integer i_clk5_div_by; + integer i_extclk0_mult_by; + integer i_extclk0_div_by; + integer i_extclk1_mult_by; + integer i_extclk1_div_by; + integer i_extclk2_mult_by; + integer i_extclk2_div_by; + integer i_extclk3_mult_by; + integer i_extclk3_div_by; + integer max_d_value; + integer new_multiplier; + + // internal variables for storing the phase shift number.(used in lvds mode only) + integer i_clk0_phase_shift; + integer i_clk1_phase_shift; + integer i_clk2_phase_shift; + + // user to advanced internal signals + + integer i_m_initial; + integer i_m; + integer i_n; + integer i_m2; + integer i_n2; + integer i_ss; + integer i_l0_high; + integer i_l1_high; + integer i_g0_high; + integer i_g1_high; + integer i_g2_high; + integer i_g3_high; + integer i_e0_high; + integer i_e1_high; + integer i_e2_high; + integer i_e3_high; + integer i_l0_low; + integer i_l1_low; + integer i_g0_low; + integer i_g1_low; + integer i_g2_low; + integer i_g3_low; + integer i_e0_low; + integer i_e1_low; + integer i_e2_low; + integer i_e3_low; + integer i_l0_initial; + integer i_l1_initial; + integer i_g0_initial; + integer i_g1_initial; + integer i_g2_initial; + integer i_g3_initial; + integer i_e0_initial; + integer i_e1_initial; + integer i_e2_initial; + integer i_e3_initial; + reg [8*6:1] i_l0_mode; + reg [8*6:1] i_l1_mode; + reg [8*6:1] i_g0_mode; + reg [8*6:1] i_g1_mode; + reg [8*6:1] i_g2_mode; + reg [8*6:1] i_g3_mode; + reg [8*6:1] i_e0_mode; + reg [8*6:1] i_e1_mode; + reg [8*6:1] i_e2_mode; + reg [8*6:1] i_e3_mode; + integer i_vco_min; + integer i_vco_max; + integer i_vco_center; + integer i_pfd_min; + integer i_pfd_max; + integer i_l0_ph; + integer i_l1_ph; + integer i_g0_ph; + integer i_g1_ph; + integer i_g2_ph; + integer i_g3_ph; + integer i_e0_ph; + integer i_e1_ph; + integer i_e2_ph; + integer i_e3_ph; + integer i_m_ph; + integer m_ph_val; + integer i_l0_time_delay; + integer i_l1_time_delay; + integer i_g0_time_delay; + integer i_g1_time_delay; + integer i_g2_time_delay; + integer i_g3_time_delay; + integer i_e0_time_delay; + integer i_e1_time_delay; + integer i_e2_time_delay; + integer i_e3_time_delay; + integer i_m_time_delay; + integer i_n_time_delay; + integer i_extclk3_counter; + integer i_extclk2_counter; + integer i_extclk1_counter; + integer i_extclk0_counter; + integer i_clk5_counter; + integer i_clk4_counter; + integer i_clk3_counter; + integer i_clk2_counter; + integer i_clk1_counter; + integer i_clk0_counter; + integer i_charge_pump_current; + integer i_loop_filter_r; + integer max_neg_abs; + integer output_count; + integer new_divisor; + + // uppercase to lowercase parameter values + reg [8*`WORD_LENGTH:1] l_operation_mode; + reg [8*`WORD_LENGTH:1] l_pll_type; + reg [8*`WORD_LENGTH:1] l_qualify_conf_done; + reg [8*`WORD_LENGTH:1] l_compensate_clock; + reg [8*`WORD_LENGTH:1] l_scan_chain; + reg [8*`WORD_LENGTH:1] l_primary_clock; + reg [8*`WORD_LENGTH:1] l_gate_lock_signal; + reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk; + reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock; + reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter; + reg [8*`WORD_LENGTH:1] l_feedback_source; + reg [8*`WORD_LENGTH:1] l_bandwidth_type; + reg [8*`WORD_LENGTH:1] l_simulation_type; + reg [8*`WORD_LENGTH:1] l_enable0_counter; + reg [8*`WORD_LENGTH:1] l_enable1_counter; + + reg init; + + specify + endspecify + + // finds the closest integer fraction of a given pair of numerator and denominator. + task find_simple_integer_fraction; + input numerator; + input denominator; + input max_denom; + output fraction_num; + output fraction_div; + parameter max_iter = 20; + + integer numerator; + integer denominator; + integer max_denom; + integer fraction_num; + integer fraction_div; + + integer quotient_array[max_iter-1:0]; + integer int_loop_iter; + integer int_quot; + integer m_value; + integer d_value; + integer old_m_value; + integer swap; + + integer loop_iter; + integer num; + integer den; + integer i_max_iter; + + begin + loop_iter = 0; + num = numerator; + den = denominator; + i_max_iter = max_iter; + + while (loop_iter < i_max_iter) + begin + int_quot = num / den; + quotient_array[loop_iter] = int_quot; + num = num - (den*int_quot); + loop_iter=loop_iter+1; + + if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter)) + begin + // calculate the numerator and denominator if there is a restriction on the + // max denom value or if the loop is ending + m_value = 0; + d_value = 1; + // get the rounded value at this stage for the remaining fraction + if (den != 0) + begin + m_value = (2*num/den); + end + // calculate the fraction numerator and denominator at this stage + for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1) + begin + if (m_value == 0) + begin + m_value = quotient_array[int_loop_iter]; + d_value = 1; + end + else + begin + old_m_value = m_value; + m_value = quotient_array[int_loop_iter]*m_value + d_value; + d_value = old_m_value; + end + end + // if the denominator is less than the maximum denom_value or if there is no restriction save it + if ((d_value <= max_denom) || (max_denom == -1)) + begin + fraction_num = m_value; + fraction_div = d_value; + end + // end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round) + if (((d_value > max_denom) && (max_denom != -1)) || (num == 0)) + begin + i_max_iter = loop_iter; + end + end + // swap the numerator and denominator for the next round + swap = den; + den = num; + num = swap; + end + end + endtask // find_simple_integer_fraction + +// get the absolute value + function integer abs; + input value; + integer value; + begin + if (value < 0) + abs = value * -1; + else abs = value; + end + endfunction + + // find twice the period of the slowest clock + function integer slowest_clk; + input L0, L1, G0, G1, G2, G3, E0, E1, E2, E3, scan_chain, refclk, m_mod; + integer L0, L1, G0, G1, G2, G3, E0, E1, E2, E3; + reg [8*5:1] scan_chain; + integer refclk; + reg [31:0] m_mod; + integer max_modulus; + begin + if (L0 > L1) + max_modulus = L0; + else + max_modulus = L1; + if (G0 > max_modulus) + max_modulus = G0; + if (G1 > max_modulus) + max_modulus = G1; + if (G2 > max_modulus) + max_modulus = G2; + if (G3 > max_modulus) + max_modulus = G3; + if (scan_chain == "long") + begin + if (E0 > max_modulus) + max_modulus = E0; + if (E1 > max_modulus) + max_modulus = E1; + if (E2 > max_modulus) + max_modulus = E2; + if (E3 > max_modulus) + max_modulus = E3; + end + + slowest_clk = ((refclk/m_mod) * max_modulus *2); + end + endfunction + + // count the number of digits in the given integer + function integer count_digit; + input X; + integer X; + integer count, result; + begin + count = 0; + result = X; + while (result != 0) + begin + result = (result / 10); + count = count + 1; + end + + count_digit = count; + end + endfunction + + // reduce the given huge number(X) to Y significant digits + function integer scale_num; + input X, Y; + integer X, Y; + integer count; + integer fac_ten, lc; + begin + fac_ten = 1; + count = count_digit(X); + + for (lc = 0; lc < (count-Y); lc = lc + 1) + fac_ten = fac_ten * 10; + + scale_num = (X / fac_ten); + end + endfunction + + // find the greatest common denominator of X and Y + function integer gcd; + input X,Y; + integer X,Y; + integer L, S, R, G; + begin + if (X < Y) // find which is smaller. + begin + S = X; + L = Y; + end + else + begin + S = Y; + L = X; + end + + R = S; + while ( R > 1) + begin + S = L; + L = R; + R = S % L; // divide bigger number by smaller. + // remainder becomes smaller number. + end + if (R == 0) // if evenly divisible then L is gcd else it is 1. + G = L; + else + G = R; + gcd = G; + end + endfunction + + // find the least common multiple of A1 to A10 + function integer lcm; + input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P; + integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P; + integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R; + begin + M1 = (A1 * A2)/gcd(A1, A2); + M2 = (M1 * A3)/gcd(M1, A3); + M3 = (M2 * A4)/gcd(M2, A4); + M4 = (M3 * A5)/gcd(M3, A5); + M5 = (M4 * A6)/gcd(M4, A6); + M6 = (M5 * A7)/gcd(M5, A7); + M7 = (M6 * A8)/gcd(M6, A8); + M8 = (M7 * A9)/gcd(M7, A9); + M9 = (M8 * A10)/gcd(M8, A10); + if (M9 < 3) + R = 10; + else if ((M9 <= 10) && (M9 >= 3)) + R = 4 * M9; + else if (M9 > 1000) + R = scale_num(M9,3); + else + R = M9; + lcm = R; + end + endfunction + + // find the factor of division of the output clock frequency + // compared to the VCO + function integer output_counter_value; + input clk_divide, clk_mult, M, N; + integer clk_divide, clk_mult, M, N; + integer R; + begin + R = (clk_divide * M)/(clk_mult * N); + output_counter_value = R; + end + endfunction + + // find the mode of each of the PLL counters - bypass, even or odd + function [8*6:1] counter_mode; + input duty_cycle; + input output_counter_value; + integer duty_cycle; + integer output_counter_value; + integer half_cycle_high; + reg [8*6:1] R; + begin + half_cycle_high = (2*duty_cycle*output_counter_value)/100; + if (output_counter_value == 1) + R = "bypass"; + else if ((half_cycle_high % 2) == 0) + R = "even"; + else + R = "odd"; + counter_mode = R; + end + endfunction + + // find the number of VCO clock cycles to hold the output clock high + function integer counter_high; + input output_counter_value, duty_cycle; + integer output_counter_value, duty_cycle; + integer half_cycle_high; + integer tmp_counter_high; + integer mode; + begin + half_cycle_high = (2*duty_cycle*output_counter_value)/100; + mode = ((half_cycle_high % 2) == 0); + tmp_counter_high = half_cycle_high/2; + counter_high = tmp_counter_high + !mode; + end + endfunction + + // find the number of VCO clock cycles to hold the output clock low + function integer counter_low; + input output_counter_value, duty_cycle; + integer output_counter_value, duty_cycle, counter_h; + integer half_cycle_high; + integer mode; + integer tmp_counter_high; + begin + half_cycle_high = (2*duty_cycle*output_counter_value)/100; + mode = ((half_cycle_high % 2) == 0); + tmp_counter_high = half_cycle_high/2; + counter_h = tmp_counter_high + !mode; + counter_low = output_counter_value - counter_h; + end + endfunction + + // find the smallest time delay amongst t1 to t10 + function integer mintimedelay; + input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10; + integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10; + integer m1,m2,m3,m4,m5,m6,m7,m8,m9; + begin + if (t1 < t2) + m1 = t1; + else + m1 = t2; + if (m1 < t3) + m2 = m1; + else + m2 = t3; + if (m2 < t4) + m3 = m2; + else + m3 = t4; + if (m3 < t5) + m4 = m3; + else + m4 = t5; + if (m4 < t6) + m5 = m4; + else + m5 = t6; + if (m5 < t7) + m6 = m5; + else + m6 = t7; + if (m6 < t8) + m7 = m6; + else + m7 = t8; + if (m7 < t9) + m8 = m7; + else + m8 = t9; + if (m8 < t10) + m9 = m8; + else + m9 = t10; + if (m9 > 0) + mintimedelay = m9; + else + mintimedelay = 0; + end + endfunction + + // find the numerically largest negative number, and return its absolute value + function integer maxnegabs; + input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10; + integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10; + integer m1,m2,m3,m4,m5,m6,m7,m8,m9; + begin + if (t1 < t2) m1 = t1; else m1 = t2; + if (m1 < t3) m2 = m1; else m2 = t3; + if (m2 < t4) m3 = m2; else m3 = t4; + if (m3 < t5) m4 = m3; else m4 = t5; + if (m4 < t6) m5 = m4; else m5 = t6; + if (m5 < t7) m6 = m5; else m6 = t7; + if (m6 < t8) m7 = m6; else m7 = t8; + if (m7 < t9) m8 = m7; else m8 = t9; + if (m8 < t10) m9 = m8; else m9 = t10; + maxnegabs = (m9 < 0) ? 0 - m9 : 0; + end + endfunction + + // adjust the given tap_phase by adding the largest negative number (ph_base) + function integer ph_adjust; + input tap_phase, ph_base; + integer tap_phase, ph_base; + begin + ph_adjust = tap_phase + ph_base; + end + endfunction + + // find the actual time delay for each PLL counter + function integer counter_time_delay; + input clk_time_delay, m_time_delay, n_time_delay; + integer clk_time_delay, m_time_delay, n_time_delay; + begin + counter_time_delay = clk_time_delay + m_time_delay - n_time_delay; + end + endfunction + + // find the number of VCO clock cycles to wait initially before the first + // rising edge of the output clock + function integer counter_initial; + input tap_phase, m, n; + integer tap_phase, m, n, phase; + begin + if (tap_phase < 0) tap_phase = 0 - tap_phase; + // adding 0.5 for rounding correction (required in order to round + // to the nearest integer instead of truncating) + phase = ((tap_phase * m) / (360 * n)) + 0.5; + counter_initial = phase; + end + endfunction + + // find which VCO phase tap to align the rising edge of the output clock to + function integer counter_ph; + input tap_phase; + input m,n; + integer m,n, phase; + integer tap_phase; + begin + // adding 0.5 for rounding correction + phase = (tap_phase * m / n) + 0.5; + counter_ph = (phase % 360)/45; + end + endfunction + + // convert the given string to length 6 by padding with spaces + function [8*6:1] translate_string; + input mode; + reg [8*6:1] new_mode; + begin + if (mode == "bypass") + new_mode = "bypass"; + else if (mode == "even") + new_mode = " even"; + else if (mode == "odd") + new_mode = " odd"; + + translate_string = new_mode; + end + endfunction + + // convert string to integer with sign + function integer str2int; + input [8*16:1] s; + + reg [8*16:1] reg_s; + reg [8:1] digit; + reg [8:1] tmp; + integer m, magnitude; + integer sign; + + begin + sign = 1; + magnitude = 0; + reg_s = s; + for (m=1; m<=16; m=m+1) + begin + tmp = reg_s[128:121]; + digit = tmp & 8'b00001111; + reg_s = reg_s << 8; + // Accumulate ascii digits 0-9 only. + if ((tmp>=48) && (tmp<=57)) + magnitude = (magnitude * 10) + digit; + if (tmp == 45) + sign = -1; // Found a '-' character, i.e. number is negative. + end + str2int = sign*magnitude; + end + endfunction + + // this is for stratix lvds only + // convert phase delay to integer + function integer get_int_phase_shift; + input [8*16:1] s; + input i_phase_shift; + integer i_phase_shift; + + begin + if (i_phase_shift != 0) + begin + get_int_phase_shift = i_phase_shift; + end + else + begin + get_int_phase_shift = str2int(s); + end + end + endfunction + + // calculate the given phase shift (in ps) in terms of degrees + function integer get_phase_degree; + input phase_shift; + integer phase_shift, result; + begin + result = (phase_shift * 360) / inclk0_input_frequency; + // this is to round up the calculation result + if ( result > 0 ) + result = result + 1; + else if ( result < 0 ) + result = result - 1; + else + result = 0; + + // assign the rounded up result + get_phase_degree = result; + end + endfunction + + // convert uppercase parameter values to lowercase + // assumes that the maximum character length of a parameter is 18 + function [8*`WORD_LENGTH:1] alpha_tolower; + input [8*`WORD_LENGTH:1] given_string; + + reg [8*`WORD_LENGTH:1] return_string; + reg [8*`WORD_LENGTH:1] reg_string; + reg [8:1] tmp; + reg [8:1] conv_char; + integer byte_count; + begin + return_string = " "; // initialise strings to spaces + conv_char = " "; + reg_string = given_string; + for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1) + begin + tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)]; + reg_string = reg_string << 8; + if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 + begin + conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set + return_string = {return_string, conv_char}; + end + else + return_string = {return_string, tmp}; + end + + alpha_tolower = return_string; + end + endfunction + + initial + begin + // convert string parameter values from uppercase to lowercase, + // as expected in this model + l_operation_mode = alpha_tolower(operation_mode); + l_pll_type = alpha_tolower(pll_type); + l_qualify_conf_done = alpha_tolower(qualify_conf_done); + l_compensate_clock = alpha_tolower(compensate_clock); + l_scan_chain = alpha_tolower(scan_chain); + l_primary_clock = alpha_tolower(primary_clock); + l_gate_lock_signal = alpha_tolower(gate_lock_signal); + l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk); + l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock); + l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter); + l_feedback_source = alpha_tolower(feedback_source); + l_bandwidth_type = alpha_tolower(bandwidth_type); + l_simulation_type = alpha_tolower(simulation_type); + l_enable0_counter = alpha_tolower(enable0_counter); + l_enable1_counter = alpha_tolower(enable1_counter); + + if (m == 0) + begin + // set the limit of the divide_by value that can be returned by + // the following function. + max_d_value = 500; + + // scale down the multiply_by and divide_by values provided by the design + // before attempting to use them in the calculations below + find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, + max_d_value, i_clk0_mult_by, i_clk0_div_by); + find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, + max_d_value, i_clk1_mult_by, i_clk1_div_by); + find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, + max_d_value, i_clk2_mult_by, i_clk2_div_by); + find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, + max_d_value, i_clk3_mult_by, i_clk3_div_by); + find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, + max_d_value, i_clk4_mult_by, i_clk4_div_by); + find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by, + max_d_value, i_clk5_mult_by, i_clk5_div_by); + find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by, + max_d_value, i_extclk0_mult_by, i_extclk0_div_by); + find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by, + max_d_value, i_extclk1_mult_by, i_extclk1_div_by); + find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by, + max_d_value, i_extclk2_mult_by, i_extclk2_div_by); + find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by, + max_d_value, i_extclk3_mult_by, i_extclk3_div_by); + + // convert user parameters to advanced + i_n = 1; + if (l_pll_type == "lvds") + i_m = clk0_multiply_by; + else + i_m = lcm (i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, i_clk5_mult_by, + i_extclk0_mult_by, + i_extclk1_mult_by, i_extclk2_mult_by, + i_extclk3_mult_by, inclk0_input_frequency); + i_m_time_delay = maxnegabs (str2int(clk0_time_delay), + str2int(clk1_time_delay), + str2int(clk2_time_delay), + str2int(clk3_time_delay), + str2int(clk4_time_delay), + str2int(clk5_time_delay), + str2int(extclk0_time_delay), + str2int(extclk1_time_delay), + str2int(extclk2_time_delay), + str2int(extclk3_time_delay)); + i_n_time_delay = mintimedelay(str2int(clk0_time_delay), + str2int(clk1_time_delay), + str2int(clk2_time_delay), + str2int(clk3_time_delay), + str2int(clk4_time_delay), + str2int(clk5_time_delay), + str2int(extclk0_time_delay), + str2int(extclk1_time_delay), + str2int(extclk2_time_delay), + str2int(extclk3_time_delay)); + if (l_pll_type == "lvds") + i_g0_high = counter_high(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + else + i_g0_high = counter_high(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + + + i_g1_high = counter_high(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_g2_high = counter_high(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_g3_high = counter_high(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + if (l_pll_type == "lvds") + begin + i_l0_high = i_g0_high; + i_l1_high = i_g0_high; + end + else + begin + i_l0_high = counter_high(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_l1_high = counter_high(output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + end + i_e0_high = counter_high(output_counter_value(i_extclk0_div_by, + i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle); + i_e1_high = counter_high(output_counter_value(i_extclk1_div_by, + i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle); + i_e2_high = counter_high(output_counter_value(i_extclk2_div_by, + i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle); + i_e3_high = counter_high(output_counter_value(i_extclk3_div_by, + i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle); + if (l_pll_type == "lvds") + i_g0_low = counter_low(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + else + i_g0_low = counter_low(output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_g1_low = counter_low(output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_g2_low = counter_low(output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_g3_low = counter_low(output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + if (l_pll_type == "lvds") + begin + i_l0_low = i_g0_low; + i_l1_low = i_g0_low; + end + else + begin + i_l0_low = counter_low(output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_l1_low = counter_low(output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + end + i_e0_low = counter_low(output_counter_value(i_extclk0_div_by, + i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle); + i_e1_low = counter_low(output_counter_value(i_extclk1_div_by, + i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle); + i_e2_low = counter_low(output_counter_value(i_extclk2_div_by, + i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle); + i_e3_low = counter_low(output_counter_value(i_extclk3_div_by, + i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle); + + if (l_pll_type == "flvds") + begin + // Need to readjust phase shift values when the clock multiply value has been readjusted. + new_multiplier = clk0_multiply_by / i_clk0_mult_by; + i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier); + i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier); + i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier); + end + else + begin + i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num); + i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num); + i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num); + end + + max_neg_abs = maxnegabs(i_clk0_phase_shift, + i_clk1_phase_shift, + i_clk2_phase_shift, + str2int(clk3_phase_shift), + str2int(clk4_phase_shift), + str2int(clk5_phase_shift), + str2int(extclk0_phase_shift), + str2int(extclk1_phase_shift), + str2int(extclk2_phase_shift), + str2int(extclk3_phase_shift)); + if (l_pll_type == "lvds") + i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n); + else + i_g0_initial = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n); + + i_g1_initial = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n); + i_g2_initial = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n); + i_g3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n); + if (l_pll_type == "lvds") + begin + i_l0_initial = i_g0_initial; + i_l1_initial = i_g0_initial; + end + else + begin + i_l0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n); + i_l1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n); + end + i_e0_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs)), i_m, i_n); + i_e1_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs)), i_m, i_n); + i_e2_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs)), i_m, i_n); + i_e3_initial = counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs)), i_m, i_n); + if (l_pll_type == "lvds") + i_g0_mode = counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + else + i_g0_mode = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); + i_g1_mode = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); + i_g2_mode = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + i_g3_mode = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); + if (l_pll_type == "lvds") + begin + i_l0_mode = "bypass"; + i_l1_mode = "bypass"; + end + else + begin + i_l0_mode = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); + i_l1_mode = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n)); + end + i_e0_mode = counter_mode(extclk0_duty_cycle,output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n)); + i_e1_mode = counter_mode(extclk1_duty_cycle,output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n)); + i_e2_mode = counter_mode(extclk2_duty_cycle,output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n)); + i_e3_mode = counter_mode(extclk3_duty_cycle,output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n)); + i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n); + i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n); + if (l_pll_type == "lvds") + i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n); + else + i_g0_ph = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n); + + i_g1_ph = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n); + i_g2_ph = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n); + i_g3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n); + if (l_pll_type == "lvds") + begin + i_l0_ph = i_g0_ph; + i_l1_ph = i_g0_ph; + end + else + begin + i_l0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n); + i_l1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n); + end + i_e0_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs)), i_m, i_n); + i_e1_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs)), i_m, i_n); + i_e2_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs)), i_m, i_n); + i_e3_ph = counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs)), i_m, i_n); + + if (l_pll_type == "lvds") + i_g0_time_delay = counter_time_delay ( str2int(clk2_time_delay), + i_m_time_delay, + i_n_time_delay); + else + i_g0_time_delay = counter_time_delay ( str2int(clk0_time_delay), + i_m_time_delay, + i_n_time_delay); + i_g1_time_delay = counter_time_delay ( str2int(clk1_time_delay), + i_m_time_delay, + i_n_time_delay); + i_g2_time_delay = counter_time_delay ( str2int(clk2_time_delay), + i_m_time_delay, + i_n_time_delay); + i_g3_time_delay = counter_time_delay ( str2int(clk3_time_delay), + i_m_time_delay, + i_n_time_delay); + if (l_pll_type == "lvds") + begin + i_l0_time_delay = i_g0_time_delay; + i_l1_time_delay = i_g0_time_delay; + end + else + begin + i_l0_time_delay = counter_time_delay ( str2int(clk4_time_delay), + i_m_time_delay, + i_n_time_delay); + i_l1_time_delay = counter_time_delay ( str2int(clk5_time_delay), + i_m_time_delay, + i_n_time_delay); + end + i_e0_time_delay = counter_time_delay ( str2int( extclk0_time_delay), + i_m_time_delay, + i_n_time_delay); + i_e1_time_delay = counter_time_delay ( str2int( extclk1_time_delay), + i_m_time_delay, + i_n_time_delay); + i_e2_time_delay = counter_time_delay ( str2int( extclk2_time_delay), + i_m_time_delay, + i_n_time_delay); + i_e3_time_delay = counter_time_delay ( str2int( extclk3_time_delay), + i_m_time_delay, + i_n_time_delay); + i_extclk3_counter = "e3" ; + i_extclk2_counter = "e2" ; + i_extclk1_counter = "e1" ; + i_extclk0_counter = "e0" ; + i_clk5_counter = "l1" ; + i_clk4_counter = "l0" ; + i_clk3_counter = "g3" ; + i_clk2_counter = "g2" ; + i_clk1_counter = "g1" ; + + if (l_pll_type == "lvds") + begin + l_enable0_counter = "l0"; + l_enable1_counter = "l1"; + i_clk0_counter = "l0" ; + end + else + i_clk0_counter = "g0" ; + + // in external feedback mode, need to adjust M value to take + // into consideration the external feedback counter value + if (l_operation_mode == "external_feedback") + begin + // if there is a negative phase shift, m_initial can only be 1 + if (max_neg_abs > 0) + i_m_initial = 1; + + if (l_feedback_source == "extclk0") + begin + if (i_e0_mode == "bypass") + output_count = 1; + else + output_count = i_e0_high + i_e0_low; + end + else if (l_feedback_source == "extclk1") + begin + if (i_e1_mode == "bypass") + output_count = 1; + else + output_count = i_e1_high + i_e1_low; + end + else if (l_feedback_source == "extclk2") + begin + if (i_e2_mode == "bypass") + output_count = 1; + else + output_count = i_e2_high + i_e2_low; + end + else if (l_feedback_source == "extclk3") + begin + if (i_e3_mode == "bypass") + output_count = 1; + else + output_count = i_e3_high + i_e3_low; + end + else // default to e0 + begin + if (i_e0_mode == "bypass") + output_count = 1; + else + output_count = i_e0_high + i_e0_low; + end + + if (i_m > output_count) + i_m = i_m / output_count; + else + begin + new_divisor = gcd(i_m, output_count); + i_m = i_m / new_divisor; + i_n = output_count / new_divisor; + end + end + + end + else + begin // m != 0 + + i_n = n; + i_m = m; + i_l0_high = l0_high; + i_l1_high = l1_high; + i_g0_high = g0_high; + i_g1_high = g1_high; + i_g2_high = g2_high; + i_g3_high = g3_high; + i_e0_high = e0_high; + i_e1_high = e1_high; + i_e2_high = e2_high; + i_e3_high = e3_high; + i_l0_low = l0_low; + i_l1_low = l1_low; + i_g0_low = g0_low; + i_g1_low = g1_low; + i_g2_low = g2_low; + i_g3_low = g3_low; + i_e0_low = e0_low; + i_e1_low = e1_low; + i_e2_low = e2_low; + i_e3_low = e3_low; + i_l0_initial = l0_initial; + i_l1_initial = l1_initial; + i_g0_initial = g0_initial; + i_g1_initial = g1_initial; + i_g2_initial = g2_initial; + i_g3_initial = g3_initial; + i_e0_initial = e0_initial; + i_e1_initial = e1_initial; + i_e2_initial = e2_initial; + i_e3_initial = e3_initial; + i_l0_mode = alpha_tolower(l0_mode); + i_l1_mode = alpha_tolower(l1_mode); + i_g0_mode = alpha_tolower(g0_mode); + i_g1_mode = alpha_tolower(g1_mode); + i_g2_mode = alpha_tolower(g2_mode); + i_g3_mode = alpha_tolower(g3_mode); + i_e0_mode = alpha_tolower(e0_mode); + i_e1_mode = alpha_tolower(e1_mode); + i_e2_mode = alpha_tolower(e2_mode); + i_e3_mode = alpha_tolower(e3_mode); + i_l0_ph = l0_ph; + i_l1_ph = l1_ph; + i_g0_ph = g0_ph; + i_g1_ph = g1_ph; + i_g2_ph = g2_ph; + i_g3_ph = g3_ph; + i_e0_ph = e0_ph; + i_e1_ph = e1_ph; + i_e2_ph = e2_ph; + i_e3_ph = e3_ph; + i_m_ph = m_ph; // default + i_m_initial = m_initial; + i_l0_time_delay = l0_time_delay; + i_l1_time_delay = l1_time_delay; + i_g0_time_delay = g0_time_delay; + i_g1_time_delay = g1_time_delay; + i_g2_time_delay = g2_time_delay; + i_g3_time_delay = g3_time_delay; + i_e0_time_delay = e0_time_delay; + i_e1_time_delay = e1_time_delay; + i_e2_time_delay = e2_time_delay; + i_e3_time_delay = e3_time_delay; + i_m_time_delay = m_time_delay; + i_n_time_delay = n_time_delay; + i_extclk3_counter = alpha_tolower(extclk3_counter); + i_extclk2_counter = alpha_tolower(extclk2_counter); + i_extclk1_counter = alpha_tolower(extclk1_counter); + i_extclk0_counter = alpha_tolower(extclk0_counter); + i_clk5_counter = alpha_tolower(clk5_counter); + i_clk4_counter = alpha_tolower(clk4_counter); + i_clk3_counter = alpha_tolower(clk3_counter); + i_clk2_counter = alpha_tolower(clk2_counter); + i_clk1_counter = alpha_tolower(clk1_counter); + i_clk0_counter = alpha_tolower(clk0_counter); + + end // user to advanced conversion + + // set the scan_chain length + if (l_scan_chain == "long") + scan_chain_length = EGPP_SCAN_CHAIN; + else if (l_scan_chain == "short") + scan_chain_length = GPP_SCAN_CHAIN; + + if (l_primary_clock == "inclk0") + begin + refclk_period = inclk0_input_frequency * i_n; + primary_clock_frequency = inclk0_input_frequency; + end + else if (l_primary_clock == "inclk1") + begin + refclk_period = inclk1_input_frequency * i_n; + primary_clock_frequency = inclk1_input_frequency; + end + + m_times_vco_period = refclk_period; + new_m_times_vco_period = refclk_period; + + fbclk_period = 0; + high_time = 0; + low_time = 0; + schedule_vco = 0; + schedule_offset = 1; + vco_out[7:0] = 8'b0; + fbclk_last_value = 0; + offset = 0; + temp_offset = 0; + got_first_refclk = 0; + got_first_fbclk = 0; + fbclk_time = 0; + first_fbclk_time = 0; + refclk_time = 0; + first_schedule = 1; + sched_time = 0; + vco_val = 0; + l0_got_first_rising_edge = 0; + l1_got_first_rising_edge = 0; + vco_l0_last_value = 0; + l0_count = 1; + l1_count = 1; + l0_tmp = 0; + l1_tmp = 0; + gate_count = 0; + gate_out = 0; + initial_delay = 0; + fbk_phase = 0; + for (i = 0; i <= 7; i = i + 1) + begin + phase_shift[i] = 0; + last_phase_shift[i] = 0; + end + fbk_delay = 0; + inclk_n = 0; + cycle_to_adjust = 0; + m_delay = 0; + vco_l0 = 0; + vco_l1 = 0; + total_pull_back = 0; + pull_back_M = 0; + pull_back_ext_cntr = 0; + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 0; + ena_ipd_last_value = 0; + inclk_out_of_range = 0; + scandataout_tmp = 0; + schedule_vco_last_value = 0; + + // set initial values for counter parameters + m_initial_val = i_m_initial; + m_val = i_m; + m_time_delay_val = i_m_time_delay; + n_val = i_n; + n_time_delay_val = i_n_time_delay; + m_ph_val = i_m_ph; + + m2_val = m2; + n2_val = n2; + + if (m_val == 1) + m_mode_val = "bypass"; + if (m2_val == 1) + m2_mode_val = "bypass"; + if (n_val == 1) + n_mode_val = "bypass"; + if (n2_val == 1) + n2_mode_val = "bypass"; + + if (skip_vco == "on") + begin + m_val = 1; + m_initial_val = 1; + m_time_delay_val = 0; + m_ph_val = 0; + end + + l0_high_val = i_l0_high; + l0_low_val = i_l0_low; + l0_initial_val = i_l0_initial; + l0_mode_val = i_l0_mode; + l0_time_delay_val = i_l0_time_delay; + + l1_high_val = i_l1_high; + l1_low_val = i_l1_low; + l1_initial_val = i_l1_initial; + l1_mode_val = i_l1_mode; + l1_time_delay_val = i_l1_time_delay; + + g0_high_val = i_g0_high; + g0_low_val = i_g0_low; + g0_initial_val = i_g0_initial; + g0_mode_val = i_g0_mode; + g0_time_delay_val = i_g0_time_delay; + + g1_high_val = i_g1_high; + g1_low_val = i_g1_low; + g1_initial_val = i_g1_initial; + g1_mode_val = i_g1_mode; + g1_time_delay_val = i_g1_time_delay; + + g2_high_val = i_g2_high; + g2_low_val = i_g2_low; + g2_initial_val = i_g2_initial; + g2_mode_val = i_g2_mode; + g2_time_delay_val = i_g2_time_delay; + + g3_high_val = i_g3_high; + g3_low_val = i_g3_low; + g3_initial_val = i_g3_initial; + g3_mode_val = i_g3_mode; + g3_time_delay_val = i_g3_time_delay; + + e0_high_val = i_e0_high; + e0_low_val = i_e0_low; + e0_initial_val = i_e0_initial; + e0_mode_val = i_e0_mode; + e0_time_delay_val = i_e0_time_delay; + + e1_high_val = i_e1_high; + e1_low_val = i_e1_low; + e1_initial_val = i_e1_initial; + e1_mode_val = i_e1_mode; + e1_time_delay_val = i_e1_time_delay; + + e2_high_val = i_e2_high; + e2_low_val = i_e2_low; + e2_initial_val = i_e2_initial; + e2_mode_val = i_e2_mode; + e2_time_delay_val = i_e2_time_delay; + + e3_high_val = i_e3_high; + e3_low_val = i_e3_low; + e3_initial_val = i_e3_initial; + e3_mode_val = i_e3_mode; + e3_time_delay_val = i_e3_time_delay; + + i = 0; + j = 0; + inclk_last_value = 0; + + ext_fbk_cntr_ph = 0; + ext_fbk_cntr_initial = 1; + + // initialize clkswitch variables + + clk0_is_bad = 0; + clk1_is_bad = 0; + inclk0_last_value = 0; + inclk1_last_value = 0; + other_clock_value = 0; + other_clock_last_value = 0; + primary_clk_is_bad = 0; + current_clk_is_bad = 0; + external_switch = 0; + current_clock = l_primary_clock; + if (l_primary_clock == "inclk0") + active_clock = 0; + else + active_clock = 1; + clkloss_tmp = 0; + got_curr_clk_falling_edge_after_clkswitch = 0; + clk0_count = 0; + clk1_count = 0; + switch_over_count = 0; + active_clk_was_switched = 0; + + // initialize quiet_time + quiet_time = slowest_clk ( l0_high_val+l0_low_val, + l1_high_val+l1_low_val, + g0_high_val+g0_low_val, + g1_high_val+g1_low_val, + g2_high_val+g2_low_val, + g3_high_val+g3_low_val, + e0_high_val+e0_low_val, + e1_high_val+e1_low_val, + e2_high_val+e2_low_val, + e3_high_val+e3_low_val, + l_scan_chain, + refclk_period, m_val); + pll_in_quiet_period = 0; + start_quiet_time = 0; + quiet_period_violation = 0; + reconfig_err = 0; + scanclr_violation = 0; + scanclr_clk_violation = 0; + got_first_scanclk_after_scanclr_inactive_edge = 0; + error = 0; + scanaclr_rising_time = 0; + scanaclr_falling_time = 0; + + // VCO feedback loop settings for external feedback mode + // first find which ext counter is used for feedback + + if (l_operation_mode == "external_feedback") + begin + if (l_feedback_source == "extclk0") + begin + if (i_extclk0_counter == "e0") + ext_fbk_cntr = "e0"; + else if (i_extclk0_counter == "e1") + ext_fbk_cntr = "e1"; + else if (i_extclk0_counter == "e2") + ext_fbk_cntr = "e2"; + else if (i_extclk0_counter == "e3") + ext_fbk_cntr = "e3"; + else ext_fbk_cntr = "e0"; + end + else if (l_feedback_source == "extclk1") + begin + if (i_extclk1_counter == "e0") + ext_fbk_cntr = "e0"; + else if (i_extclk1_counter == "e1") + ext_fbk_cntr = "e1"; + else if (i_extclk1_counter == "e2") + ext_fbk_cntr = "e2"; + else if (i_extclk1_counter == "e3") + ext_fbk_cntr = "e3"; + else ext_fbk_cntr = "e0"; + end + else if (l_feedback_source == "extclk2") + begin + if (i_extclk2_counter == "e0") + ext_fbk_cntr = "e0"; + else if (i_extclk2_counter == "e1") + ext_fbk_cntr = "e1"; + else if (i_extclk2_counter == "e2") + ext_fbk_cntr = "e2"; + else if (i_extclk2_counter == "e3") + ext_fbk_cntr = "e3"; + else ext_fbk_cntr = "e0"; + end + else if (l_feedback_source == "extclk3") + begin + if (i_extclk3_counter == "e0") + ext_fbk_cntr = "e0"; + else if (i_extclk3_counter == "e1") + ext_fbk_cntr = "e1"; + else if (i_extclk3_counter == "e2") + ext_fbk_cntr = "e2"; + else if (i_extclk3_counter == "e3") + ext_fbk_cntr = "e3"; + else ext_fbk_cntr = "e0"; + end + + // now save this counter's parameters + if (ext_fbk_cntr == "e0") + begin + ext_fbk_cntr_high = e0_high_val; + ext_fbk_cntr_low = e0_low_val; + ext_fbk_cntr_ph = i_e0_ph; + ext_fbk_cntr_initial = i_e0_initial; + ext_fbk_cntr_delay = e0_time_delay_val; + ext_fbk_cntr_mode = e0_mode_val; + end + else if (ext_fbk_cntr == "e1") + begin + ext_fbk_cntr_high = e1_high_val; + ext_fbk_cntr_low = e1_low_val; + ext_fbk_cntr_ph = i_e1_ph; + ext_fbk_cntr_initial = i_e1_initial; + ext_fbk_cntr_delay = e1_time_delay_val; + ext_fbk_cntr_mode = e1_mode_val; + end + else if (ext_fbk_cntr == "e2") + begin + ext_fbk_cntr_high = e2_high_val; + ext_fbk_cntr_low = e2_low_val; + ext_fbk_cntr_ph = i_e2_ph; + ext_fbk_cntr_initial = i_e2_initial; + ext_fbk_cntr_delay = e2_time_delay_val; + ext_fbk_cntr_mode = e2_mode_val; + end + else if (ext_fbk_cntr == "e3") + begin + ext_fbk_cntr_high = e3_high_val; + ext_fbk_cntr_low = e3_low_val; + ext_fbk_cntr_ph = i_e3_ph; + ext_fbk_cntr_initial = i_e3_initial; + ext_fbk_cntr_delay = e3_time_delay_val; + ext_fbk_cntr_mode = e3_mode_val; + end + + if (ext_fbk_cntr_mode == "bypass") + ext_fbk_cntr_modulus = 1; + else + ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low; + end + + l_index = 1; + stop_vco = 0; + cycles_to_lock = 0; + cycles_to_unlock = 0; + if (l_pll_type == "fast") + locked_tmp = 1; + else + locked_tmp = 0; + pll_is_locked = 0; + pll_about_to_lock = 0; + + no_warn = 0; + m_val_tmp = m_val; + n_val_tmp = n_val; + end + + assign inclk_m = l_operation_mode == "external_feedback" ? (l_feedback_source == "extclk0" ? extclk0_tmp : + l_feedback_source == "extclk1" ? extclk1_tmp : + l_feedback_source == "extclk2" ? extclk2_tmp : + l_feedback_source == "extclk3" ? extclk3_tmp : 'b0) : + vco_out[m_ph_val]; + + stx_m_cntr m1 (.clk(inclk_m), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(fbclk), + .initial_value(m_initial_val), + .modulus(m_val), + .time_delay(m_delay)); + + always @(clkswitch_ipd) + begin + if (clkswitch_ipd == 1'b1) + external_switch = 1; + clkloss_tmp <= clkswitch_ipd; + end + + always @(inclk0_ipd or inclk1_ipd) + begin + // save the inclk event value + if (inclk0_ipd !== inclk0_last_value) + begin + if (current_clock !== "inclk0") + other_clock_value = inclk0_ipd; + end + if (inclk1_ipd !== inclk1_last_value) + begin + if (current_clock !== "inclk1") + other_clock_value = inclk1_ipd; + end + + // check if either input clk is bad + if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value) + begin + clk0_count = clk0_count + 1; + clk0_is_bad = 0; + if (current_clock == "inclk0") + current_clk_is_bad = 0; + clk1_count = 0; + if (clk0_count > 2) + begin + // no event on other clk for 2 cycles + clk1_is_bad = 1; + if (current_clock == "inclk1") + current_clk_is_bad = 1; + end + end + if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value) + begin + clk1_count = clk1_count + 1; + clk1_is_bad = 0; + if (current_clock == "inclk1") + current_clk_is_bad = 0; + clk0_count = 0; + if (clk1_count > 2) + begin + // no event on other clk for 2 cycles + clk0_is_bad = 1; + if (current_clock == "inclk0") + current_clk_is_bad = 1; + end + end + + // check if the bad clk is the primary clock + if (((l_primary_clock == "inclk0") && (clk0_is_bad == 1'b1)) || ((l_primary_clock == "inclk1") && (clk1_is_bad == 1'b1))) + primary_clk_is_bad = 1; + else + primary_clk_is_bad = 0; + + // actual switching + if ((inclk0_ipd !== inclk0_last_value) && (current_clock == "inclk0")) + begin + if (external_switch == 1'b1) + begin + if (!got_curr_clk_falling_edge_after_clkswitch) + begin + if (inclk0_ipd === 1'b0) + got_curr_clk_falling_edge_after_clkswitch = 1; + inclk_n = inclk0_ipd; + end + end + else inclk_n = inclk0_ipd; + end + if ((inclk1_ipd !== inclk1_last_value) && (current_clock == "inclk1")) + begin + if (external_switch == 1'b1) + begin + if (!got_curr_clk_falling_edge_after_clkswitch) + begin + if (inclk1_ipd === 1'b0) + got_curr_clk_falling_edge_after_clkswitch = 1; + inclk_n = inclk1_ipd; + end + end + else inclk_n = inclk1_ipd; + end + if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && (l_enable_switch_over_counter == "on") && primary_clk_is_bad) + switch_over_count = switch_over_count + 1; + if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value)) + begin + if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter)))) + begin + got_curr_clk_falling_edge_after_clkswitch = 0; + if (current_clock == "inclk0") + begin + current_clock = "inclk1"; + end + else + begin + current_clock = "inclk0"; + end + active_clock = ~active_clock; + active_clk_was_switched = 1; + switch_over_count = 0; + external_switch = 0; + current_clk_is_bad = 0; + end + end + + if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1)) + begin + if (primary_clk_is_bad) + clkloss_tmp = 1; + else + clkloss_tmp = 0; + end + + inclk0_last_value = inclk0_ipd; + inclk1_last_value = inclk1_ipd; + other_clock_last_value = other_clock_value; + + end + + and (clkbad[0], clk0_is_bad, 1'b1); + and (clkbad[1], clk1_is_bad, 1'b1); + and (activeclock, active_clock, 1'b1); + and (clkloss, clkloss_tmp, 1'b1); + + stx_n_cntr n1 ( .clk(inclk_n), + .reset(areset_ipd), + .cout(refclk), + .modulus(n_val), + .time_delay(n_time_delay_val)); + + stx_scale_cntr l0 ( .clk(vco_out[i_l0_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(l0_clk), + .high(l0_high_val), + .low(l0_low_val), + .initial_value(l0_initial_val), + .mode(l0_mode_val), + .time_delay(l0_time_delay_val), + .ph_tap(i_l0_ph)); + + stx_scale_cntr l1 ( .clk(vco_out[i_l1_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(l1_clk), + .high(l1_high_val), + .low(l1_low_val), + .initial_value(l1_initial_val), + .mode(l1_mode_val), + .time_delay(l1_time_delay_val), + .ph_tap(i_l1_ph)); + + stx_scale_cntr g0 ( .clk(vco_out[i_g0_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(g0_clk), + .high(g0_high_val), + .low(g0_low_val), + .initial_value(g0_initial_val), + .mode(g0_mode_val), + .time_delay(g0_time_delay_val), + .ph_tap(i_g0_ph)); + + MF_pll_reg lvds_dffa ( .d(comparator_ipd), + .clrn(1'b1), + .prn(1'b1), + .ena(1'b1), + .clk(g0_clk), + .q(dffa_out)); + + MF_pll_reg lvds_dffb ( .d(dffa_out), + .clrn(1'b1), + .prn(1'b1), + .ena(1'b1), + .clk(lvds_dffb_clk), + .q(dffb_out)); + + assign lvds_dffb_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0; + + MF_pll_reg lvds_dffc ( .d(dffb_out), + .clrn(1'b1), + .prn(1'b1), + .ena(1'b1), + .clk(lvds_dffc_clk), + .q(dffc_out)); + + assign lvds_dffc_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0; + + assign nce_temp = ~dffc_out && dffb_out; + + MF_pll_reg lvds_dffd ( .d(nce_temp), + .clrn(1'b1), + .prn(1'b1), + .ena(1'b1), + .clk(~lvds_dffd_clk), + .q(dffd_out)); + + assign lvds_dffd_clk = (l_enable0_counter == "l0") ? l0_clk : (l_enable0_counter == "l1") ? l1_clk : 1'b0; + + assign nce_l0 = (l_enable0_counter == "l0") ? dffd_out : 'b0; + assign nce_l1 = (l_enable0_counter == "l1") ? dffd_out : 'b0; + + stx_scale_cntr g1 ( .clk(vco_out[i_g1_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(g1_clk), + .high(g1_high_val), + .low(g1_low_val), + .initial_value(g1_initial_val), + .mode(g1_mode_val), + .time_delay(g1_time_delay_val), + .ph_tap(i_g1_ph)); + + stx_scale_cntr g2 ( .clk(vco_out[i_g2_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(g2_clk), + .high(g2_high_val), + .low(g2_low_val), + .initial_value(g2_initial_val), + .mode(g2_mode_val), + .time_delay(g2_time_delay_val), + .ph_tap(i_g2_ph)); + + stx_scale_cntr g3 ( .clk(vco_out[i_g3_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(g3_clk), + .high(g3_high_val), + .low(g3_low_val), + .initial_value(g3_initial_val), + .mode(g3_mode_val), + .time_delay(g3_time_delay_val), + .ph_tap(i_g3_ph)); + assign cntr_e0_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? 1 : e0_initial_val; + assign cntr_e0_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e0") ? ext_fbk_delay : e0_time_delay_val; + + stx_scale_cntr e0 ( .clk(vco_out[i_e0_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(e0_clk), + .high(e0_high_val), + .low(e0_low_val), + .initial_value(cntr_e0_initial), + .mode(e0_mode_val), + .time_delay(cntr_e0_delay), + .ph_tap(i_e0_ph)); + + assign cntr_e1_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? 1 : e1_initial_val; + assign cntr_e1_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e1") ? ext_fbk_delay : e1_time_delay_val; + stx_scale_cntr e1 ( .clk(vco_out[i_e1_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(e1_clk), + .high(e1_high_val), + .low(e1_low_val), + .initial_value(cntr_e1_initial), + .mode(e1_mode_val), + .time_delay(cntr_e1_delay), + .ph_tap(i_e1_ph)); + + assign cntr_e2_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? 1 : e2_initial_val; + assign cntr_e2_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e2") ? ext_fbk_delay : e2_time_delay_val; + stx_scale_cntr e2 ( .clk(vco_out[i_e2_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(e2_clk), + .high(e2_high_val), + .low(e2_low_val), + .initial_value(cntr_e2_initial), + .mode(e2_mode_val), + .time_delay(cntr_e2_delay), + .ph_tap(i_e2_ph)); + + assign cntr_e3_initial = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? 1 : e3_initial_val; + assign cntr_e3_delay = (l_operation_mode == "external_feedback" && ext_fbk_cntr == "e3") ? ext_fbk_delay : e3_time_delay_val; + stx_scale_cntr e3 ( .clk(vco_out[i_e3_ph]), + .reset(areset_ipd || (!ena_ipd) || stop_vco), + .cout(e3_clk), + .high(e3_high_val), + .low(e3_low_val), + .initial_value(cntr_e3_initial), + .mode(e3_mode_val), + .time_delay(cntr_e3_delay), + .ph_tap(i_e3_ph)); + + + always @(vco_out[i_l0_ph] or posedge areset_ipd or negedge ena_ipd or stop_vco) + begin + if ((areset_ipd == 1'b1) || (ena_ipd == 1'b0) || (stop_vco == 1'b1)) + begin + l0_count = 1; + l0_got_first_rising_edge = 0; + end + else begin + if (nce_l0 == 1'b0) + begin + if (l0_got_first_rising_edge == 1'b0) + begin + if (vco_out[i_l0_ph] == 1'b1 && vco_out[i_l0_ph] != vco_l0_last_value) + l0_got_first_rising_edge = 1; + end + else if (vco_out[i_l0_ph] != vco_l0_last_value) + begin + l0_count = l0_count + 1; + if (l0_count == (l0_high_val + l0_low_val) * 2) + l0_count = 1; + end + end + if (vco_out[i_l0_ph] == 1'b0 && vco_out[i_l0_ph] != vco_l0_last_value) + begin + if (l0_count == 1) + begin + l0_tmp = 1; + l0_got_first_rising_edge = 0; + end + else l0_tmp = 0; + end + end + vco_l0_last_value = vco_out[i_l0_ph]; + end + + always @(vco_out[i_l1_ph] or posedge areset_ipd or negedge ena_ipd or stop_vco) + begin + if (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1) + begin + l1_count = 1; + l1_got_first_rising_edge = 0; + end + else begin + if (nce_l1 == 1'b0) + begin + if (l1_got_first_rising_edge == 1'b0) + begin + if (vco_out[i_l1_ph] == 1'b1 && vco_out[i_l1_ph] != vco_l1_last_value) + l1_got_first_rising_edge = 1; + end + else if (vco_out[i_l1_ph] != vco_l1_last_value) + begin + l1_count = l1_count + 1; + if (l1_count == (l1_high_val + l1_low_val) * 2) + l1_count = 1; + end + end + if (vco_out[i_l1_ph] == 1'b0 && vco_out[i_l1_ph] != vco_l1_last_value) + begin + if (l1_count == 1) + begin + l1_tmp = 1; + l1_got_first_rising_edge = 0; + end + else l1_tmp = 0; + end + end + vco_l1_last_value = vco_out[i_l1_ph]; + end + + assign enable0_tmp = (l_enable0_counter == "l0") ? l0_tmp : l1_tmp; + assign enable1_tmp = (l_enable1_counter == "l0") ? l0_tmp : l1_tmp; + + always @ (inclk_n or ena_ipd or areset_ipd) + begin + if (areset_ipd == 'b1) + begin + gate_count = 0; + gate_out = 0; + end + else if (inclk_n == 'b1 && inclk_last_value != inclk_n) + if (ena_ipd == 'b1) + begin + gate_count = gate_count + 1; + if (gate_count == gate_lock_counter) + gate_out = 1; + end + inclk_last_value = inclk_n; + end + + assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp; + + always @ (scanclk_ipd or scanaclr_ipd) + begin + if (scanaclr_ipd === 1'b1 && scanaclr_last_value === 1'b0) + scanaclr_rising_time = $time; + else if (scanaclr_ipd === 1'b0 && scanaclr_last_value === 1'b1) + begin + scanaclr_falling_time = $time; + // check for scanaclr active pulse width + if ($time - scanaclr_rising_time < TRST) + begin + scanclr_violation = 1; + $display ("Warning : Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_rising_time); + $display ("Time: %0t Instance: %m", $time); + end + else begin + scanclr_violation = 0; + for (i = 0; i <= scan_chain_length; i = i + 1) + scan_data[i] = 0; + end + got_first_scanclk_after_scanclr_inactive_edge = 0; + end + else if ((scanclk_ipd === 'b1 && scanclk_last_value !== scanclk_ipd) && (got_first_scanclk_after_scanclr_inactive_edge === 1'b0) && ($time - scanaclr_falling_time < TRSTCLK)) + begin + scanclr_clk_violation = 1; + $display ("Warning : Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is %0t. Reconfiguration may not work.", $time - scanaclr_falling_time); + $display ("Time: %0t Instance: %m", $time); + got_first_scanclk_after_scanclr_inactive_edge = 1; + end + else if (scanclk_ipd == 'b1 && scanclk_last_value != scanclk_ipd && scanaclr_ipd === 1'b0) + begin + if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time)) + begin + $display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly."); + quiet_period_violation = 1; + end + else begin + pll_in_quiet_period = 0; + for (j = scan_chain_length-1; j >= 1; j = j - 1) + begin + scan_data[j] = scan_data[j - 1]; + end + scan_data[0] = scandata_ipd; + end + if (got_first_scanclk_after_scanclr_inactive_edge === 1'b0) + begin + got_first_scanclk_after_scanclr_inactive_edge = 1; + scanclr_clk_violation = 0; + end + end + else if (scanclk_ipd === 1'b0 && scanclk_last_value !== scanclk_ipd && scanaclr_ipd === 1'b0) + begin + if (pll_in_quiet_period && ($time - start_quiet_time < quiet_time)) + begin + $display("Time: %0t", $time, " Warning : Detected transition on SCANCLK during quiet time. PLL may not function correctly."); + quiet_period_violation = 1; + end + else if (scan_data[scan_chain_length-1] == 1'b1) + begin + pll_in_quiet_period = 1; + quiet_period_violation = 0; + reconfig_err = 0; + start_quiet_time = $time; + // initiate transfer + scandataout_tmp <= 1'b1; + quiet_time = slowest_clk ( l0_high_val+l0_low_val, + l1_high_val+l1_low_val, + g0_high_val+g0_low_val, + g1_high_val+g1_low_val, + g2_high_val+g2_low_val, + g3_high_val+g3_low_val, + e0_high_val+e0_low_val, + e1_high_val+e1_low_val, + e2_high_val+e2_low_val, + e3_high_val+e3_low_val, + l_scan_chain, + refclk_period, m_val); + transfer <= 1; + end + end + scanclk_last_value = scanclk_ipd; + scanaclr_last_value = scanaclr_ipd; + end + + always @(scandataout_tmp) + begin + if (scandataout_tmp == 1'b1) + scandataout_tmp <= #(quiet_time) 1'b0; + end + + always @(posedge transfer) + begin + if (transfer == 1'b1) + begin + $display("NOTE : Reconfiguring PLL"); + $display ("Time: %0t Instance: %m", $time); + if (l_scan_chain == "long") + begin + // cntr e3 + error = 0; + if (scan_data[273] == 1'b1) + begin + e3_mode_val = "bypass"; + if (scan_data[283] == 1'b1) + begin + e3_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[283] == 1'b1) + e3_mode_val = "odd"; + else + e3_mode_val = "even"; + // before reading delay bits, clear e3_time_delay_val + e3_time_delay_val = 32'b0; + e3_time_delay_val = scan_data[287:284]; + e3_time_delay_val = e3_time_delay_val * 250; + if (e3_time_delay_val > 3000) + e3_time_delay_val = 3000; + e3_high_val[8:0] <= scan_data[272:264]; + e3_low_val[8:0] <= scan_data[282:274]; + if (scan_data[272:264] == 9'b000000000) + e3_high_val[9:0] <= 10'b1000000000; + if (scan_data[282:274] == 9'b000000000) + e3_low_val[9:0] <= 10'b1000000000; + + if (ext_fbk_cntr == "e3") + begin + ext_fbk_cntr_high = e3_high_val; + ext_fbk_cntr_low = e3_low_val; + ext_fbk_cntr_delay = e3_time_delay_val; + ext_fbk_cntr_mode = e3_mode_val; + end + + // cntr e2 + if (scan_data[249] == 1'b1) + begin + e2_mode_val = "bypass"; + if (scan_data[259] == 1'b1) + begin + e2_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[259] == 1'b1) + e2_mode_val = "odd"; + else + e2_mode_val = "even"; + e2_time_delay_val = 32'b0; + e2_time_delay_val = scan_data[263:260]; + e2_time_delay_val = e2_time_delay_val * 250; + if (e2_time_delay_val > 3000) + e2_time_delay_val = 3000; + e2_high_val[8:0] <= scan_data[248:240]; + e2_low_val[8:0] <= scan_data[258:250]; + if (scan_data[248:240] == 9'b000000000) + e2_high_val[9:0] <= 10'b1000000000; + if (scan_data[258:250] == 9'b000000000) + e2_low_val[9:0] <= 10'b1000000000; + + if (ext_fbk_cntr == "e2") + begin + ext_fbk_cntr_high = e2_high_val; + ext_fbk_cntr_low = e2_low_val; + ext_fbk_cntr_delay = e2_time_delay_val; + ext_fbk_cntr_mode = e2_mode_val; + end + + // cntr e1 + if (scan_data[225] == 1'b1) + begin + e1_mode_val = "bypass"; + if (scan_data[235] == 1'b1) + begin + e1_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[235] == 1'b1) + e1_mode_val = "odd"; + else + e1_mode_val = "even"; + e1_time_delay_val = 32'b0; + e1_time_delay_val = scan_data[239:236]; + e1_time_delay_val = e1_time_delay_val * 250; + if (e1_time_delay_val > 3000) + e1_time_delay_val = 3000; + e1_high_val[8:0] <= scan_data[224:216]; + e1_low_val[8:0] <= scan_data[234:226]; + if (scan_data[224:216] == 9'b000000000) + e1_high_val[9:0] <= 10'b1000000000; + if (scan_data[234:226] == 9'b000000000) + e1_low_val[9:0] <= 10'b1000000000; + + if (ext_fbk_cntr == "e1") + begin + ext_fbk_cntr_high = e1_high_val; + ext_fbk_cntr_low = e1_low_val; + ext_fbk_cntr_delay = e1_time_delay_val; + ext_fbk_cntr_mode = e1_mode_val; + end + + // cntr e0 + if (scan_data[201] == 1'b1) + begin + e0_mode_val = "bypass"; + if (scan_data[211] == 1'b1) + begin + e0_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[211] == 1'b1) + e0_mode_val = "odd"; + else + e0_mode_val = "even"; + e0_time_delay_val = 32'b0; + e0_time_delay_val = scan_data[215:212]; + e0_time_delay_val = e0_time_delay_val * 250; + if (e0_time_delay_val > 3000) + e0_time_delay_val = 3000; + e0_high_val[8:0] <= scan_data[200:192]; + e0_low_val[8:0] <= scan_data[210:202]; + if (scan_data[200:192] == 9'b000000000) + e0_high_val[9:0] <= 10'b1000000000; + if (scan_data[210:202] == 9'b000000000) + e0_low_val[9:0] <= 10'b1000000000; + + if (ext_fbk_cntr == "e0") + begin + ext_fbk_cntr_high = e0_high_val; + ext_fbk_cntr_low = e0_low_val; + ext_fbk_cntr_delay = e0_time_delay_val; + ext_fbk_cntr_mode = e0_mode_val; + end + end + + // cntr l1 + if (scan_data[177] == 1'b1) + begin + l1_mode_val = "bypass"; + if (scan_data[187] == 1'b1) + begin + l1_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[187] == 1'b1) + l1_mode_val = "odd"; + else + l1_mode_val = "even"; + l1_time_delay_val = 32'b0; + l1_time_delay_val = scan_data[191:188]; + l1_time_delay_val = l1_time_delay_val * 250; + if (l1_time_delay_val > 3000) + l1_time_delay_val = 3000; + l1_high_val[8:0] <= scan_data[176:168]; + l1_low_val[8:0] <= scan_data[186:178]; + if (scan_data[176:168] == 9'b000000000) + l1_high_val[9:0] <= 10'b1000000000; + if (scan_data[186:178] == 9'b000000000) + l1_low_val[9:0] <= 10'b1000000000; + + // cntr l0 + if (scan_data[153] == 1'b1) + begin + l0_mode_val = "bypass"; + if (scan_data[163] == 1'b1) + begin + l0_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[163] == 1'b1) + l0_mode_val = "odd"; + else + l0_mode_val = "even"; + l0_time_delay_val = 32'b0; + l0_time_delay_val = scan_data[167:164]; + l0_time_delay_val = l0_time_delay_val * 250; + if (l0_time_delay_val > 3000) + l0_time_delay_val = 3000; + l0_high_val[8:0] <= scan_data[152:144]; + l0_low_val[8:0] <= scan_data[162:154]; + if (scan_data[152:144] == 9'b000000000) + l0_high_val[9:0] <= 10'b1000000000; + if (scan_data[162:154] == 9'b000000000) + l0_low_val[9:0] <= 10'b1000000000; + + // cntr g3 + if (scan_data[129] == 1'b1) + begin + g3_mode_val = "bypass"; + if (scan_data[139] == 1'b1) + begin + g3_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[139] == 1'b1) + g3_mode_val = "odd"; + else + g3_mode_val = "even"; + g3_time_delay_val = 32'b0; + g3_time_delay_val = scan_data[143:140]; + g3_time_delay_val = g3_time_delay_val * 250; + if (g3_time_delay_val > 3000) + g3_time_delay_val = 3000; + g3_high_val[8:0] <= scan_data[128:120]; + g3_low_val[8:0] <= scan_data[138:130]; + if (scan_data[128:120] == 9'b000000000) + g3_high_val[9:0] <= 10'b1000000000; + if (scan_data[138:130] == 9'b000000000) + g3_low_val[9:0] <= 10'b1000000000; + + // cntr g2 + if (scan_data[105] == 1'b1) + begin + g2_mode_val = "bypass"; + if (scan_data[115] == 1'b1) + begin + g2_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[115] == 1'b1) + g2_mode_val = "odd"; + else + g2_mode_val = "even"; + g2_time_delay_val = 32'b0; + g2_time_delay_val = scan_data[119:116]; + g2_time_delay_val = g2_time_delay_val * 250; + if (g2_time_delay_val > 3000) + g2_time_delay_val = 3000; + g2_high_val[8:0] <= scan_data[104:96]; + g2_low_val[8:0] <= scan_data[114:106]; + if (scan_data[104:96] == 9'b000000000) + g2_high_val[9:0] <= 10'b1000000000; + if (scan_data[114:106] == 9'b000000000) + g2_low_val[9:0] <= 10'b1000000000; + + // cntr g1 + if (scan_data[81] == 1'b1) + begin + g1_mode_val = "bypass"; + if (scan_data[91] == 1'b1) + begin + g1_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[91] == 1'b1) + g1_mode_val = "odd"; + else + g1_mode_val = "even"; + g1_time_delay_val = 32'b0; + g1_time_delay_val = scan_data[95:92]; + g1_time_delay_val = g1_time_delay_val * 250; + if (g1_time_delay_val > 3000) + g1_time_delay_val = 3000; + g1_high_val[8:0] <= scan_data[80:72]; + g1_low_val[8:0] <= scan_data[90:82]; + if (scan_data[80:72] == 9'b000000000) + g1_high_val[9:0] <= 10'b1000000000; + if (scan_data[90:82] == 9'b000000000) + g1_low_val[9:0] <= 10'b1000000000; + + // cntr g0 + if (scan_data[57] == 1'b1) + begin + g0_mode_val = "bypass"; + if (scan_data[67] == 1'b1) + begin + g0_mode_val = "off"; + $display("Warning : The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized."); + end + end + else if (scan_data[67] == 1'b1) + g0_mode_val = "odd"; + else + g0_mode_val = "even"; + g0_time_delay_val = 32'b0; + g0_time_delay_val = scan_data[71:68]; + g0_time_delay_val = g0_time_delay_val * 250; + if (g0_time_delay_val > 3000) + g0_time_delay_val = 3000; + g0_high_val[8:0] <= scan_data[56:48]; + g0_low_val[8:0] <= scan_data[66:58]; + if (scan_data[56:48] == 9'b000000000) + g0_high_val[9:0] <= 10'b1000000000; + if (scan_data[66:58] == 9'b000000000) + g0_low_val[9:0] <= 10'b1000000000; + + // cntr M + error = 0; + m_val_tmp[8:0] = scan_data[32:24]; + if (scan_data[33] !== 1'b1) + begin + if (m_val_tmp[8:0] == 9'b000000001) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Illegal 1 value for M counter. Instead, the M counter should be BYPASSED. Reconfiguration may not work."); + end + else if (m_val_tmp[8:0] == 9'b000000000) + m_val_tmp[9:0] = 10'b1000000000; + if (error == 1'b0) + begin + if (m_mode_val === "bypass") + $display ("Warning : M counter switched from BYPASS mode to enabled (M modulus = %d). PLL may lose lock.", m_val_tmp[9:0]); + else + $display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]); + m_mode_val = ""; + end + end + else if (scan_data[33] == 1'b1) + begin + if (scan_data[24] !== 1'b0) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Illegal value for counter M in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work."); + end + else begin + if (m_mode_val !== "bypass") + $display ("Warning : M counter switched from enabled to BYPASS mode. PLL may lose lock."); + m_val_tmp[9:0] = 10'b0000000001; + m_mode_val = "bypass"; + $display("PLL reconfigured with : M modulus = %d ", m_val_tmp[9:0]); + end + end + + if (skip_vco == "on") + m_val_tmp[9:0] = 10'b0000000001; + + // cntr M2 + if (ss > 0) + begin + error = 0; + m2_val[8:0] = scan_data[42:34]; + if (scan_data[43] !== 1'b1) + begin + if (m2_val[8:0] == 9'b000000001) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Illegal 1 value for M2 counter. Instead, the M2 counter should be BYPASSED. Reconfiguration may not work."); + end + else if (m2_val[8:0] == 9'b000000000) + m2_val[9:0] = 10'b1000000000; + if (error == 1'b0) + begin + if (m2_mode_val === "bypass") + $display ("Warning : M2 counter switched from BYPASS mode to enabled (M2 modulus = %d). Pll may lose lock.", m2_val[9:0]); + else + $display(" M2 modulus = %d ", m2_val[9:0]); + m2_mode_val = ""; + end + end + else if (scan_data[43] == 1'b1) + begin + if (scan_data[34] !== 1'b0) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Illegal value for counter M2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work."); + end + else begin + if (m2_mode_val !== "bypass") + $display ("Warning : M2 counter switched from enabled to BYPASS mode. PLL may lose lock."); + m2_val[9:0] = 10'b0000000001; + m2_mode_val = "bypass"; + $display(" M2 modulus = %d ", m2_val[9:0]); + end + end + if (m_mode_val != m2_mode_val) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Incompatible modes for M1/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work."); + end + end + + m_time_delay_val = 32'b0; + m_time_delay_val = scan_data[47:44]; + m_time_delay_val = m_time_delay_val * 250; + if (m_time_delay_val > 3000) + m_time_delay_val = 3000; + if (skip_vco == "on") + m_time_delay_val = 32'b0; + $display(" M time delay = %0d", m_time_delay_val); + + // cntr N + error = 0; + n_val_tmp[8:0] = scan_data[8:0]; + if (scan_data[9] !== 1'b1) + begin + if (n_val_tmp[8:0] == 9'b000000001) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Illegal 1 value for N counter. Instead, the N counter should be BYPASSED. Reconfiguration may not work."); + end + else if (n_val_tmp[8:0] == 9'b000000000) + n_val_tmp[9:0] = 10'b1000000000; + if (error == 1'b0) + begin + if (n_mode_val === "bypass") + $display ("Warning : N counter switched from BYPASS mode to enabled (N modulus = %d). PLL may lose lock.", n_val_tmp[9:0]); + else + $display(" N modulus = %d ", n_val_tmp[9:0]); + n_mode_val = ""; + end + end + else if (scan_data[9] == 1'b1) // bypass + begin + if (scan_data[0] !== 1'b0) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Illegal value for counter N in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work."); + end + else begin + if (n_mode_val !== "bypass") + $display ("Warning : N counter switched from enabled to BYPASS mode. PLL may lose lock."); + n_val_tmp[9:0] = 10'b0000000001; + n_mode_val = "bypass"; + $display(" N modulus = %d ", n_val_tmp[9:0]); + end + end + + // cntr N2 + if (ss > 0) + begin + error = 0; + n2_val[8:0] = scan_data[18:10]; + if (scan_data[19] !== 1'b1) + begin + if (n2_val[8:0] == 9'b000000001) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Illegal 1 value for N2 counter. Instead, the N2 counter should be BYPASSED. Reconfiguration may not work."); + end + else if (n2_val[8:0] == 9'b000000000) + n2_val = 10'b1000000000; + if (error == 1'b0) + begin + if (n2_mode_val === "bypass") + $display ("Warning : N2 counter switched from BYPASS mode to enabled (N2 modulus = %d). PLL may lose lock.", n2_val[9:0]); + else + $display(" N2 modulus = %d ", n2_val[9:0]); + n2_mode_val = ""; + end + end + else if (scan_data[19] == 1'b1) // bypass + begin + if (scan_data[10] !== 1'b0) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Illegal value for counter N2 in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work."); + end + else begin + if (n2_mode_val !== "bypass") + $display ("Warning : N2 counter switched from enabled to BYPASS mode. PLL may lose lock."); + n2_val[9:0] = 10'b0000000001; + n2_mode_val = "bypass"; + $display(" N2 modulus = %d ", n2_val[9:0]); + end + end + if (n_mode_val != n2_mode_val) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Incompatible modes for N1/N2 counters. Either both should be BYASSED or both NON-BYPASSED."); + end + end // ss > 0 + + n_time_delay_val = 32'b0; + n_time_delay_val = scan_data[23:20]; + n_time_delay_val = n_time_delay_val * 250; + if (n_time_delay_val > 3000) + n_time_delay_val = 3000; + $display(" N time delay = %0d", n_time_delay_val); + + transfer <= 0; + // clear the scan_chain + for (i = 0; i <= scan_chain_length; i = i + 1) + scan_data[i] = 0; + end + end + + always @(negedge transfer) + begin + if (l_scan_chain == "long") + begin + $display(" E3 high = %d, E3 low = %d, E3 mode = %s, E3 time delay = %0d", e3_high_val[9:0], e3_low_val[9:0], e3_mode_val, e3_time_delay_val); + $display(" E2 high = %d, E2 low = %d, E2 mode = %s, E2 time delay = %0d", e2_high_val[9:0], e2_low_val[9:0], e2_mode_val, e2_time_delay_val); + $display(" E1 high = %d, E1 low = %d, E1 mode = %s, E1 time delay = %0d", e1_high_val[9:0], e1_low_val[9:0], e1_mode_val, e1_time_delay_val); + $display(" E0 high = %d, E0 low = %d, E0 mode = %s, E0 time delay = %0d", e0_high_val[9:0], e0_low_val[9:0], e0_mode_val, e0_time_delay_val); + end + $display(" L1 high = %d, L1 low = %d, L1 mode = %s, L1 time delay = %0d", l1_high_val[9:0], l1_low_val[9:0], l1_mode_val, l1_time_delay_val); + $display(" L0 high = %d, L0 low = %d, L0 mode = %s, L0 time delay = %0d", l0_high_val[9:0], l0_low_val[9:0], l0_mode_val, l0_time_delay_val); + $display(" G3 high = %d, G3 low = %d, G3 mode = %s, G3 time delay = %0d", g3_high_val[9:0], g3_low_val[9:0], g3_mode_val, g3_time_delay_val); + $display(" G2 high = %d, G2 low = %d, G2 mode = %s, G2 time delay = %0d", g2_high_val[9:0], g2_low_val[9:0], g2_mode_val, g2_time_delay_val); + $display(" G1 high = %d, G1 low = %d, G1 mode = %s, G1 time delay = %0d", g1_high_val[9:0], g1_low_val[9:0], g1_mode_val, g1_time_delay_val); + $display(" G0 high = %d, G0 low = %d, G0 mode = %s, G0 time delay = %0d", g0_high_val[9:0], g0_low_val[9:0], g0_mode_val, g0_time_delay_val); + end + +always @(schedule_vco or areset_ipd or ena_ipd) +begin + sched_time = 0; + + for (i = 0; i <= 7; i=i+1) + last_phase_shift[i] = phase_shift[i]; + + cycle_to_adjust = 0; + l_index = 1; + m_times_vco_period = new_m_times_vco_period; + + // give appropriate messages + // if areset was asserted + if (areset_ipd == 1'b1 && areset_ipd_last_value !== areset_ipd) + begin + $display (" Note : Stratix PLL was reset"); + $display ("Time: %0t Instance: %m", $time); + end + + // if ena was deasserted + if (ena_ipd == 1'b0 && ena_ipd_last_value !== ena_ipd) + begin + $display (" Note : Stratix PLL was disabled"); + $display ("Time: %0t Instance: %m", $time); + end + + // illegal value on areset_ipd + if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1)) + begin + $display("Warning : Illegal value 'X' detected on ARESET input"); + $display ("Time: %0t Instance: %m", $time); + end + + if ((schedule_vco !== schedule_vco_last_value) && (areset_ipd == 1'b1 || ena_ipd == 1'b0 || stop_vco == 1'b1)) + begin + + // drop VCO taps to 0 + for (i = 0; i <= 7; i=i+1) + begin + for (j = 0; j <= last_phase_shift[i] + 1; j=j+1) + vco_out[i] <= #(j) 1'b0; + phase_shift[i] = 0; + last_phase_shift[i] = 0; + end + + // reset lock parameters + locked_tmp = 0; + if (l_pll_type == "fast") + locked_tmp = 1; + pll_is_locked = 0; + pll_about_to_lock = 0; + cycles_to_lock = 0; + cycles_to_unlock = 0; + + got_first_refclk = 0; + got_second_refclk = 0; + refclk_time = 0; + got_first_fbclk = 0; + fbclk_time = 0; + first_fbclk_time = 0; + fbclk_period = 0; + + first_schedule = 1; + schedule_offset = 1; + vco_val = 0; + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 0; + + // reset enable0 and enable1 counter parameters +// l0_count = 1; +// l1_count = 1; +// l0_got_first_rising_edge = 0; +// l1_got_first_rising_edge = 0; + + end else if (ena_ipd === 1'b1 && areset_ipd === 1'b0 && stop_vco === 1'b0) + begin + + // else note areset deassert time + // note it as refclk_time to prevent false triggering + // of stop_vco after areset + if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1) + begin + refclk_time = $time; + end + + // calculate loop_xplier : this will be different from m_val in ext. fbk mode + loop_xplier = m_val; + loop_initial = i_m_initial - 1; + loop_ph = i_m_ph; + loop_time_delay = m_time_delay_val; + + if (l_operation_mode == "external_feedback") + begin + if (ext_fbk_cntr_mode == "bypass") + ext_fbk_cntr_modulus = 1; + else + ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low; + + loop_xplier = m_val * (ext_fbk_cntr_modulus); + loop_ph = ext_fbk_cntr_ph; + loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * (ext_fbk_cntr_modulus)); + loop_time_delay = m_time_delay_val + ext_fbk_cntr_delay; + end + + // convert initial value to delay + initial_delay = (loop_initial * m_times_vco_period)/loop_xplier; + + // convert loop ph_tap to delay + rem = m_times_vco_period % loop_xplier; + vco_per = m_times_vco_period/loop_xplier; + if (rem != 0) + vco_per = vco_per + 1; + fbk_phase = (loop_ph * vco_per)/8; + + if (l_operation_mode == "external_feedback") + begin + pull_back_ext_cntr = ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier) + fbk_phase; + + while (pull_back_ext_cntr > refclk_period) + pull_back_ext_cntr = pull_back_ext_cntr - refclk_period; + + pull_back_M = m_time_delay_val + (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier); + + while (pull_back_M > refclk_period) + pull_back_M = pull_back_M - refclk_period; + end + else begin + pull_back_ext_cntr = 0; + pull_back_M = initial_delay + m_time_delay_val + fbk_phase; + end + + total_pull_back = pull_back_M + pull_back_ext_cntr; + if (l_simulation_type == "timing") + total_pull_back = total_pull_back + pll_compensation_delay; + + while (total_pull_back > refclk_period) + total_pull_back = total_pull_back - refclk_period; + + if (total_pull_back > 0) + offset = refclk_period - total_pull_back; + + if (l_operation_mode == "external_feedback") + begin + fbk_delay = pull_back_M; + if (l_simulation_type == "timing") + fbk_delay = fbk_delay + pll_compensation_delay; + + ext_fbk_delay = pull_back_ext_cntr - fbk_phase; + end + else begin + fbk_delay = total_pull_back - fbk_phase; + if (fbk_delay < 0) + begin + offset = offset - fbk_phase; + fbk_delay = total_pull_back; + end + end + + // assign m_delay + m_delay = fbk_delay; + + for (i = 1; i <= loop_xplier; i=i+1) + begin + // adjust cycles + tmp_vco_per = m_times_vco_period/loop_xplier; + if (rem != 0 && l_index <= rem) + begin + tmp_rem = (loop_xplier * l_index) % rem; + cycle_to_adjust = (loop_xplier * l_index) / rem; + if (tmp_rem != 0) + cycle_to_adjust = cycle_to_adjust + 1; + end + if (cycle_to_adjust == i) + begin + tmp_vco_per = tmp_vco_per + 1; + l_index = l_index + 1; + end + + // calculate high and low periods + high_time = tmp_vco_per/2; + if (tmp_vco_per % 2 != 0) + high_time = high_time + 1; + low_time = tmp_vco_per - high_time; + + // schedule the rising and falling egdes + for (j=0; j<=1; j=j+1) + begin + vco_val = ~vco_val; + if (vco_val == 1'b0) + sched_time = sched_time + high_time; + else + sched_time = sched_time + low_time; + + // add offset + if (schedule_offset == 1'b1) + begin + sched_time = sched_time + offset; + schedule_offset = 0; + end + + // schedule taps with appropriate phase shifts + for (k = 0; k <= 7; k=k+1) + begin + phase_shift[k] = (k*tmp_vco_per)/8; + if (first_schedule) + vco_out[k] <= #(sched_time + phase_shift[k]) vco_val; + else + vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val; + end + end + end + if (first_schedule) + begin + vco_val = ~vco_val; + if (vco_val == 1'b0) + sched_time = sched_time + high_time; + else + sched_time = sched_time + low_time; + for (k = 0; k <= 7; k=k+1) + begin + phase_shift[k] = (k*tmp_vco_per)/8; + vco_out[k] <= #(sched_time+phase_shift[k]) vco_val; + end + first_schedule = 0; + end + + // this may no longer be required + + schedule_vco <= #(sched_time) ~schedule_vco; + if (vco_period_was_phase_adjusted) + begin + m_times_vco_period = refclk_period; + new_m_times_vco_period = refclk_period; + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 1; + + tmp_vco_per = m_times_vco_period/loop_xplier; + for (k = 0; k <= 7; k=k+1) + phase_shift[k] = (k*tmp_vco_per)/8; + end + end + + areset_ipd_last_value = areset_ipd; + ena_ipd_last_value = ena_ipd; + schedule_vco_last_value = schedule_vco; + +end + +always @(pfdena_ipd) +begin + if (pfdena_ipd === 1'b0) + begin + locked_tmp = 1'bx; + pll_is_locked = 0; + cycles_to_lock = 0; + $display (" Note : PFDENA was deasserted"); + $display ("Time: %0t Instance: %m", $time); + end + else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0) + begin + // PFD was disabled, now enabled again + got_first_refclk = 0; + got_second_refclk = 0; + refclk_time = $time; + end + pfdena_ipd_last_value = pfdena_ipd; +end + +always @(negedge refclk) +begin + refclk_last_value = refclk; +end + +always @(negedge fbclk) +begin + fbclk_last_value = fbclk; +end + +always @(posedge refclk or posedge fbclk) +begin + if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0) + begin + n_val <= n_val_tmp; + if (! got_first_refclk) + begin + got_first_refclk = 1; + end else + begin + got_second_refclk = 1; + refclk_period = $time - refclk_time; + + // check if incoming freq. will cause VCO range to be + // exceeded + if ( (vco_max != 0 && vco_min != 0) && (skip_vco == "off") && (pfdena_ipd === 1'b1) && + ((refclk_period/loop_xplier > vco_max) || + (refclk_period/loop_xplier < vco_min)) ) + begin + if (pll_is_locked == 1'b1) + begin + $display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock"); + $display ("Time: %0t Instance: %m", $time); + if (inclk_out_of_range === 1'b1) + begin + // unlock + pll_is_locked = 0; + locked_tmp = 0; + if (l_pll_type == "fast") + locked_tmp = 1; + pll_about_to_lock = 0; + cycles_to_lock = 0; + $display ("Note : Stratix PLL lost lock"); + $display ("Time: %0t Instance: %m", $time); + first_schedule = 1; + schedule_offset = 1; + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 0; + end + end + else begin + if (no_warn == 0) + begin + $display ("Warning : Input clock freq. is not within VCO range. PLL may not lock"); + $display ("Time: %0t Instance: %m", $time); + no_warn = 1; + end + end + inclk_out_of_range = 1; + end + else if ( vco_min == 0 && vco_max == 0 && pll_type == "cdr") + begin + if (refclk_period != primary_clock_frequency) + begin + if (no_warn == 0) + begin + $display("Warning : Incoming clock period %d for Stratix PLL does not match the specified inclock period %d. ALTGXB simulation may not function correctly.", refclk_period, primary_clock_frequency); + $display ("Time: %0t Instance: %m", $time); + no_warn = 1; + end + end + end + else begin + inclk_out_of_range = 0; + end + + end + if (stop_vco == 1'b1) + begin + stop_vco = 0; + schedule_vco = ~schedule_vco; + end + refclk_time = $time; + end + + if (fbclk == 1'b1 && fbclk_last_value !== fbclk) + begin + m_val <= m_val_tmp; + if (!got_first_fbclk) + begin + got_first_fbclk = 1; + first_fbclk_time = $time; + end + else + fbclk_period = $time - fbclk_time; + + // need refclk_period here, so initialized to proper value above + if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked == 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) ) + begin + stop_vco = 1; + // reset + got_first_refclk = 0; + got_first_fbclk = 0; + got_second_refclk = 0; + if (pll_is_locked == 1'b1) + begin + pll_is_locked = 0; + locked_tmp = 0; + if (l_pll_type == "fast") + locked_tmp = 1; + $display ("Note : Stratix PLL lost lock due to loss of input clock"); + $display ("Time: %0t Instance: %m", $time); + end + pll_about_to_lock = 0; + cycles_to_lock = 0; + cycles_to_unlock = 0; + first_schedule = 1; + end + fbclk_time = $time; + end + + if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range)) + begin + // now we know actual incoming period +// if (abs(refclk_period - fbclk_period) > 2) +// begin +// new_m_times_vco_period = refclk_period; +// end +// else if (abs(fbclk_time - refclk_time) <= 2 || (refclk_period - abs(fbclk_time - refclk_time) <= 2)) + if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5)) + begin + // considered in phase + if (cycles_to_lock == valid_lock_multiplier - 1) + pll_about_to_lock <= 1; + if (cycles_to_lock == valid_lock_multiplier) + begin + if (pll_is_locked === 1'b0) + begin + $display (" Note : Stratix PLL locked to incoming clock"); + $display ("Time: %0t Instance: %m", $time); + end + pll_is_locked = 1; + locked_tmp = 1; + if (l_pll_type == "fast") + locked_tmp = 0; + end + // increment lock counter only if the second part of the above + // time check is NOT true + if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5)) + begin + cycles_to_lock = cycles_to_lock + 1; + end + + // adjust m_times_vco_period + new_m_times_vco_period = refclk_period; + + end else + begin + // if locked, begin unlock + if (pll_is_locked) + begin + cycles_to_unlock = cycles_to_unlock + 1; + if (cycles_to_unlock == invalid_lock_multiplier) + begin + pll_is_locked = 0; + locked_tmp = 0; + if (l_pll_type == "fast") + locked_tmp = 1; + pll_about_to_lock = 0; + cycles_to_lock = 0; + $display ("Note : Stratix PLL lost lock"); + $display ("Time: %0t Instance: %m", $time); + first_schedule = 1; + schedule_offset = 1; + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 0; + end + end + if (abs(refclk_period - fbclk_period) <= 2) + begin + // frequency is still good + if ($time == fbclk_time && (!phase_adjust_was_scheduled)) + begin + if (abs(fbclk_time - refclk_time) > refclk_period/2) + begin + if (abs(fbclk_time - refclk_time) > 1.5 * refclk_period) + begin + // input clock may have stopped : do nothing + end + else begin + new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); + vco_period_was_phase_adjusted = 1; + end + end else + begin + new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time); + vco_period_was_phase_adjusted = 1; + end + end + end else + begin + new_m_times_vco_period = refclk_period; + phase_adjust_was_scheduled = 0; + end + end + end + + if (quiet_period_violation == 1'b1 || reconfig_err == 1'b1 || scanclr_violation == 1'b1 || scanclr_clk_violation == 1'b1) + begin + locked_tmp = 0; + if (l_pll_type == "fast") + locked_tmp = 1; + end + + refclk_last_value = refclk; + fbclk_last_value = fbclk; +end + + assign clk0_tmp = i_clk0_counter == "l0" ? l0_clk : i_clk0_counter == "l1" ? l1_clk : i_clk0_counter == "g0" ? g0_clk : i_clk0_counter == "g1" ? g1_clk : i_clk0_counter == "g2" ? g2_clk : i_clk0_counter == "g3" ? g3_clk : 'b0; + + assign clk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk0_tmp : 'bx; + + dffp ena0_reg ( .D(clkena0_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!clk0_tmp), + .Q(ena0)); + + assign clk1_tmp = i_clk1_counter == "l0" ? l0_clk : i_clk1_counter == "l1" ? l1_clk : i_clk1_counter == "g0" ? g0_clk : i_clk1_counter == "g1" ? g1_clk : i_clk1_counter == "g2" ? g2_clk : i_clk1_counter == "g3" ? g3_clk : 'b0; + + assign clk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk1_tmp : 'bx; + + dffp ena1_reg ( .D(clkena1_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!clk1_tmp), + .Q(ena1)); + + assign clk2_tmp = i_clk2_counter == "l0" ? l0_clk : i_clk2_counter == "l1" ? l1_clk : i_clk2_counter == "g0" ? g0_clk : i_clk2_counter == "g1" ? g1_clk : i_clk2_counter == "g2" ? g2_clk : i_clk2_counter == "g3" ? g3_clk : 'b0; + + assign clk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk2_tmp : 'bx; + + dffp ena2_reg ( .D(clkena2_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!clk2_tmp), + .Q(ena2)); + + assign clk3_tmp = i_clk3_counter == "l0" ? l0_clk : i_clk3_counter == "l1" ? l1_clk : i_clk3_counter == "g0" ? g0_clk : i_clk3_counter == "g1" ? g1_clk : i_clk3_counter == "g2" ? g2_clk : i_clk3_counter == "g3" ? g3_clk : 'b0; + + assign clk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk3_tmp : 'bx; + + dffp ena3_reg ( .D(clkena3_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!clk3_tmp), + .Q(ena3)); + + assign clk4_tmp = i_clk4_counter == "l0" ? l0_clk : i_clk4_counter == "l1" ? l1_clk : i_clk4_counter == "g0" ? g0_clk : i_clk4_counter == "g1" ? g1_clk : i_clk4_counter == "g2" ? g2_clk : i_clk4_counter == "g3" ? g3_clk : 'b0; + + assign clk4 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk4_tmp : 'bx; + + dffp ena4_reg ( .D(clkena4_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!clk4_tmp), + .Q(ena4)); + + assign clk5_tmp = i_clk5_counter == "l0" ? l0_clk : i_clk5_counter == "l1" ? l1_clk : i_clk5_counter == "g0" ? g0_clk : i_clk5_counter == "g1" ? g1_clk : i_clk5_counter == "g2" ? g2_clk : i_clk5_counter == "g3" ? g3_clk : 'b0; + + assign clk5 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? clk5_tmp : 'bx; + + dffp ena5_reg ( .D(clkena5_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!clk5_tmp), + .Q(ena5)); + + assign extclk0_tmp = i_extclk0_counter == "e0" ? e0_clk : i_extclk0_counter == "e1" ? e1_clk : i_extclk0_counter == "e2" ? e2_clk : i_extclk0_counter == "e3" ? e3_clk : i_extclk0_counter == "g0" ? g0_clk : 'b0; + + assign extclk0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk0_tmp : 'bx; + + dffp extena0_reg ( .D(extclkena0_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!extclk0_tmp), + .Q(extena0)); + + assign extclk1_tmp = i_extclk1_counter == "e0" ? e0_clk : i_extclk1_counter == "e1" ? e1_clk : i_extclk1_counter == "e2" ? e2_clk : i_extclk1_counter == "e3" ? e3_clk : i_extclk1_counter == "g0" ? g0_clk : 'b0; + + assign extclk1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk1_tmp : 'bx; + + dffp extena1_reg ( .D(extclkena1_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!extclk1_tmp), + .Q(extena1)); + + assign extclk2_tmp = i_extclk2_counter == "e0" ? e0_clk : i_extclk2_counter == "e1" ? e1_clk : i_extclk2_counter == "e2" ? e2_clk : i_extclk2_counter == "e3" ? e3_clk : i_extclk2_counter == "g0" ? g0_clk : 'b0; + + assign extclk2 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk2_tmp : 'bx; + + dffp extena2_reg ( .D(extclkena2_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!extclk2_tmp), + .Q(extena2)); + + assign extclk3_tmp = i_extclk3_counter == "e0" ? e0_clk : i_extclk3_counter == "e1" ? e1_clk : i_extclk3_counter == "e2" ? e2_clk : i_extclk3_counter == "e3" ? e3_clk : i_extclk3_counter == "g0" ? g0_clk : 'b0; + + assign extclk3 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || (pll_about_to_lock == 1'b1 && !quiet_period_violation && !reconfig_err && !scanclr_violation && !scanclr_clk_violation) ? extclk3_tmp : 'bx; + + dffp extena3_reg ( .D(extclkena3_ipd), + .CLRN(1'b1), + .PRN(1'b1), + .ENA(1'b1), + .CLK(!extclk3_tmp), + .Q(extena3)); + + assign enable_0 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable0_tmp : 'bx; + assign enable_1 = (areset_ipd === 1'b1 || ena_ipd === 1'b0) || pll_about_to_lock == 1'b1 ? enable1_tmp : 'bx; + + // ACCELERATE OUTPUTS + and (clk[0], ena0, clk0); + and (clk[1], ena1, clk1); + and (clk[2], ena2, clk2); + and (clk[3], ena3, clk3); + and (clk[4], ena4, clk4); + and (clk[5], ena5, clk5); + + and (extclk[0], extena0, extclk0); + and (extclk[1], extena1, extclk1); + and (extclk[2], extena2, extclk2); + and (extclk[3], extena3, extclk3); + + and (enable0, 1'b1, enable_0); + and (enable1, 1'b1, enable_1); + + and (scandataout, 1'b1, scandataout_tmp); + +endmodule // MF_stratix_pll + +/////////////////////////////////////////////////////////////////////////////// +// +// Module Name : arm_m_cntr +// +// Description : Simulation model for the M counter. This is the +// loop feedback counter for the StratixII PLL. +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +module arm_m_cntr ( clk, + reset, + cout, + initial_value, + modulus, + time_delay); + + // INPUT PORTS + input clk; + input reset; + input [31:0] initial_value; + input [31:0] modulus; + input [31:0] time_delay; + + // OUTPUT PORTS + output cout; + + // INTERNAL VARIABLES AND NETS + integer count; + reg tmp_cout; + reg first_rising_edge; + reg clk_last_value; + reg cout_tmp; + + initial + begin + count = 1; + first_rising_edge = 1; + clk_last_value = 0; + end + + always @(reset or clk) + begin + if (reset) + begin + count = 1; + tmp_cout = 0; + first_rising_edge = 1; + cout_tmp <= tmp_cout; + end + else begin + if (clk == 1 && clk_last_value !== clk && first_rising_edge) + begin + first_rising_edge = 0; + tmp_cout = clk; + cout_tmp <= #(time_delay) tmp_cout; + end + else if (first_rising_edge == 0) + begin + if (count < modulus) + count = count + 1; + else + begin + count = 1; + tmp_cout = ~tmp_cout; + cout_tmp <= #(time_delay) tmp_cout; + end + end + end + clk_last_value = clk; + +// cout_tmp <= #(time_delay) tmp_cout; + end + + and (cout, cout_tmp, 1'b1); + +endmodule // arm_m_cntr + +/////////////////////////////////////////////////////////////////////////////// +// +// Module Name : arm_n_cntr +// +// Description : Simulation model for the N counter. This is the +// input clock divide counter for the StratixII PLL. +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +module arm_n_cntr ( clk, + reset, + cout, + modulus); + + // INPUT PORTS + input clk; + input reset; + input [31:0] modulus; + + // OUTPUT PORTS + output cout; + + // INTERNAL VARIABLES AND NETS + integer count; + reg tmp_cout; + reg first_rising_edge; + reg clk_last_value; + reg cout_tmp; + + initial + begin + count = 1; + first_rising_edge = 1; + clk_last_value = 0; + end + + always @(reset or clk) + begin + if (reset) + begin + count = 1; + tmp_cout = 0; + first_rising_edge = 1; + end + else begin + if (clk == 1 && clk_last_value !== clk && first_rising_edge) + begin + first_rising_edge = 0; + tmp_cout = clk; + end + else if (first_rising_edge == 0) + begin + if (count < modulus) + count = count + 1; + else + begin + count = 1; + tmp_cout = ~tmp_cout; + end + end + end + clk_last_value = clk; + + end + + assign cout = tmp_cout; + +endmodule // arm_n_cntr + +/////////////////////////////////////////////////////////////////////////////// +// +// Module Name : arm_scale_cntr +// +// Description : Simulation model for the output scale-down counters. +// This is a common model for the C0, C1, C2, C3, C4 and +// C5 output counters of the StratixII PLL. +// +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps +module arm_scale_cntr ( clk, + reset, + cout, + high, + low, + initial_value, + mode, + ph_tap); + + // INPUT PORTS + input clk; + input reset; + input [31:0] high; + input [31:0] low; + input [31:0] initial_value; + input [8*6:1] mode; + input [31:0] ph_tap; + + // OUTPUT PORTS + output cout; + + // INTERNAL VARIABLES AND NETS + reg tmp_cout; + reg first_rising_edge; + reg clk_last_value; + reg init; + integer count; + integer output_shift_count; + reg cout_tmp; + + initial + begin + count = 1; + first_rising_edge = 0; + tmp_cout = 0; + output_shift_count = 1; + end + + always @(clk or reset) + begin + if (init !== 1'b1) + begin + clk_last_value = 0; + init = 1'b1; + end + if (reset) + begin + count = 1; + output_shift_count = 1; + tmp_cout = 0; + first_rising_edge = 0; + end + else if (clk_last_value !== clk) + begin + if (mode == " off") + tmp_cout = 0; + else if (mode == "bypass") + begin + tmp_cout = clk; + first_rising_edge = 1; + end + else if (first_rising_edge == 0) + begin + if (clk == 1) + begin + if (output_shift_count == initial_value) + begin + tmp_cout = clk; + first_rising_edge = 1; + end + else + output_shift_count = output_shift_count + 1; + end + end + else if (output_shift_count < initial_value) + begin + if (clk == 1) + output_shift_count = output_shift_count + 1; + end + else + begin + count = count + 1; + if (mode == " even" && (count == (high*2) + 1)) + tmp_cout = 0; + else if (mode == " odd" && (count == (high*2))) + tmp_cout = 0; + else if (count == (high + low)*2 + 1) + begin + tmp_cout = 1; + count = 1; // reset count + end + end + end + clk_last_value = clk; + cout_tmp <= tmp_cout; + end + + and (cout, cout_tmp, 1'b1); + +endmodule // arm_scale_cntr + + +////////////////////////////////////////////////////////////////////////////// +// +// Module Name : MF_stratixii_pll +// +// Description : Behavioral model for StratixII pll. +// +// Limitations : Does not support Spread Spectrum and Bandwidth. +// +// Outputs : Up to 6 output clocks, each defined by its own set of +// parameters. Locked output (active high) indicates when the +// PLL locks. clkbad, clkloss and activeclock are used for +// clock switchover to indicate which input clock has gone +// bad, when the clock switchover initiates and which input +// clock is being used as the reference, respectively. +// scandataout is the data output of the serial scan chain. +// +////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps/1 ps +`define WORD_LENGTH 18 + +module MF_stratixii_pll (inclk, + fbin, + ena, + clkswitch, + areset, + pfdena, + scanclk, + scanread, + scanwrite, + scandata, + testin, + clk, + clkbad, + activeclock, + locked, + clkloss, + scandataout, + scandone, + enable0, + enable1, + testupout, + testdownout, + sclkout + ); + + parameter operation_mode = "normal"; + parameter pll_type = "auto"; + parameter compensate_clock = "clk0"; + parameter feedback_source = "clk0"; + parameter qualify_conf_done = "off"; + + parameter test_input_comp_delay_chain_bits = 0; + parameter test_feedback_comp_delay_chain_bits = 0; + + parameter inclk0_input_frequency = 10000; + parameter inclk1_input_frequency = 10000; + + parameter gate_lock_signal = "no"; + parameter gate_lock_counter = 1; + parameter self_reset_on_gated_loss_lock = "off"; + parameter valid_lock_multiplier = 1; + parameter invalid_lock_multiplier = 5; + + parameter switch_over_type = "auto"; + parameter switch_over_on_lossclk = "off"; + parameter switch_over_on_gated_lock = "off"; + parameter switch_over_counter = 1; + parameter enable_switch_over_counter = "on"; + + parameter bandwidth = 0; + parameter bandwidth_type = "auto"; + parameter down_spread = "0.0"; + parameter spread_frequency = 0; + parameter common_rx_tx = "off"; + parameter rx_outclock_resource = "auto"; + parameter use_dc_coupling = "false"; + + parameter clk0_output_frequency = 0; + parameter clk0_multiply_by = 1; + parameter clk0_divide_by = 1; + parameter clk0_phase_shift = "0"; + parameter clk0_duty_cycle = 50; + + parameter clk1_output_frequency = 0; + parameter clk1_multiply_by = 1; + parameter clk1_divide_by = 1; + parameter clk1_phase_shift = "0"; + parameter clk1_duty_cycle = 50; + + parameter clk2_output_frequency = 0; + parameter clk2_multiply_by = 1; + parameter clk2_divide_by = 1; + parameter clk2_phase_shift = "0"; + parameter clk2_duty_cycle = 50; + + parameter clk3_output_frequency = 0; + parameter clk3_multiply_by = 1; + parameter clk3_divide_by = 1; + parameter clk3_phase_shift = "0"; + parameter clk3_duty_cycle = 50; + + parameter clk4_output_frequency = 0; + parameter clk4_multiply_by = 1; + parameter clk4_divide_by = 1; + parameter clk4_phase_shift = "0"; + parameter clk4_duty_cycle = 50; + + parameter clk5_output_frequency = 0; + parameter clk5_multiply_by = 1; + parameter clk5_divide_by = 1; + parameter clk5_phase_shift = "0"; + parameter clk5_duty_cycle = 50; + + parameter pfd_min = 0; + parameter pfd_max = 0; + parameter vco_min = 0; + parameter vco_max = 0; + parameter vco_center = 0; + + // ADVANCED USE PARAMETERS + parameter m_initial = 1; + parameter m = 1; + parameter n = 1; + parameter m2 = 1; + parameter n2 = 1; + parameter ss = 0; + + parameter c0_high = 1; + parameter c0_low = 1; + parameter c0_initial = 1; + parameter c0_mode = "bypass"; + parameter c0_ph = 0; + + parameter c1_high = 1; + parameter c1_low = 1; + parameter c1_initial = 1; + parameter c1_mode = "bypass"; + parameter c1_ph = 0; + + parameter c2_high = 1; + parameter c2_low = 1; + parameter c2_initial = 1; + parameter c2_mode = "bypass"; + parameter c2_ph = 0; + + parameter c3_high = 1; + parameter c3_low = 1; + parameter c3_initial = 1; + parameter c3_mode = "bypass"; + parameter c3_ph = 0; + + parameter c4_high = 1; + parameter c4_low = 1; + parameter c4_initial = 1; + parameter c4_mode = "bypass"; + parameter c4_ph = 0; + + parameter c5_high = 1; + parameter c5_low = 1; + parameter c5_initial = 1; + parameter c5_mode = "bypass"; + parameter c5_ph = 0; + + parameter m_ph = 0; + + parameter clk0_counter = "c0"; + parameter clk1_counter = "c1"; + parameter clk2_counter = "c2"; + parameter clk3_counter = "c3"; + parameter clk4_counter = "c4"; + parameter clk5_counter = "c5"; + + parameter c1_use_casc_in = "off"; + parameter c2_use_casc_in = "off"; + parameter c3_use_casc_in = "off"; + parameter c4_use_casc_in = "off"; + parameter c5_use_casc_in = "off"; + + parameter m_test_source = 5; + parameter c0_test_source = 5; + parameter c1_test_source = 5; + parameter c2_test_source = 5; + parameter c3_test_source = 5; + parameter c4_test_source = 5; + parameter c5_test_source = 5; + + // LVDS mode parameters + parameter enable0_counter = "c0"; + parameter enable1_counter = "c1"; + parameter sclkout0_phase_shift = "0"; + parameter sclkout1_phase_shift = "0"; + + parameter vco_multiply_by = 0; + parameter vco_divide_by = 0; + parameter vco_post_scale = 1; + + parameter charge_pump_current = 0; + parameter loop_filter_r = "1.0"; + parameter loop_filter_c = 1; + + parameter pll_compensation_delay = 0; + parameter simulation_type = "functional"; + + //parameter for stratixii lvds + parameter clk0_phase_shift_num = 0; + parameter clk1_phase_shift_num = 0; + parameter clk2_phase_shift_num = 0; + + parameter clk0_use_even_counter_mode = "off"; + parameter clk1_use_even_counter_mode = "off"; + parameter clk2_use_even_counter_mode = "off"; + parameter clk3_use_even_counter_mode = "off"; + parameter clk4_use_even_counter_mode = "off"; + parameter clk5_use_even_counter_mode = "off"; + + parameter clk0_use_even_counter_value = "off"; + parameter clk1_use_even_counter_value = "off"; + parameter clk2_use_even_counter_value = "off"; + parameter clk3_use_even_counter_value = "off"; + parameter clk4_use_even_counter_value = "off"; + parameter clk5_use_even_counter_value = "off"; + + // INPUT PORTS + input [1:0] inclk; + input fbin; + input ena; + input clkswitch; + input areset; + input pfdena; + input scanclk; + input scanread; + input scanwrite; + input scandata; + input [3:0] testin; + + // OUTPUT PORTS + output [5:0] clk; + output [1:0] clkbad; + output activeclock; + output locked; + output clkloss; + output scandataout; + output scandone; + // lvds specific output ports + output enable0; + output enable1; + output [1:0] sclkout; + // test ports + output testupout; + output testdownout; + + // BUFFER INPUTS + wire inclk0_ipd; + wire inclk1_ipd; + wire ena_ipd; + wire fbin_ipd; + wire clkswitch_ipd; + wire areset_ipd; + wire pfdena_ipd; + wire scanclk_ipd; + wire scanread_ipd; + wire scanwrite_ipd; + wire scandata_ipd; + buf (inclk0_ipd, inclk[0]); + buf (inclk1_ipd, inclk[1]); + buf (ena_ipd, ena); + buf (fbin_ipd, fbin); + buf (clkswitch_ipd, clkswitch); + buf (areset_ipd, areset); + buf (pfdena_ipd, pfdena); + buf (scanclk_ipd, scanclk); + buf (scanread_ipd, scanread); + buf (scanwrite_ipd, scanwrite); + buf (scandata_ipd, scandata); + + + // INTERNAL VARIABLES AND NETS + integer scan_chain_length; + integer i; + integer j; + integer k; + integer x; + integer y; + integer l_index; + integer gate_count; + integer egpp_offset; + integer sched_time; + integer delay_chain; + integer low; + integer high; + integer initial_delay; + integer fbk_phase; + integer fbk_delay; + integer phase_shift[0:7]; + integer last_phase_shift[0:7]; + + integer m_times_vco_period; + integer new_m_times_vco_period; + integer refclk_period; + integer fbclk_period; + integer high_time; + integer low_time; + integer my_rem; + integer tmp_rem; + integer rem; + integer tmp_vco_per; + integer vco_per; + integer offset; + integer temp_offset; + integer cycles_to_lock; + integer cycles_to_unlock; + integer c0_count; + integer c0_initial_count; + integer c1_count; + integer c1_initial_count; + integer loop_xplier; + integer loop_initial; + integer loop_ph; + integer cycle_to_adjust; + integer total_pull_back; + integer pull_back_M; + + time fbclk_time; + time first_fbclk_time; + time refclk_time; + + reg got_first_refclk; + reg got_second_refclk; + reg got_first_fbclk; + reg refclk_last_value; + reg fbclk_last_value; + reg inclk_last_value; + reg pll_is_locked; + reg pll_about_to_lock; + reg locked_tmp; + reg c0_got_first_rising_edge; + reg c1_got_first_rising_edge; + reg vco_c0_last_value; + reg vco_c1_last_value; + reg areset_ipd_last_value; + reg ena_ipd_last_value; + reg pfdena_ipd_last_value; + reg inclk_out_of_range; + reg schedule_vco_last_value; + + reg gate_out; + reg vco_val; + + reg [31:0] m_initial_val; + reg [31:0] m_val[0:1]; + reg [31:0] n_val[0:1]; + reg [31:0] m_delay; + reg [8*6:1] m_mode_val[0:1]; + reg [8*6:1] n_mode_val[0:1]; + + reg [31:0] c_high_val[0:5]; + reg [31:0] c_low_val[0:5]; + reg [8*6:1] c_mode_val[0:5]; + reg [31:0] c_initial_val[0:5]; + integer c_ph_val[0:5]; + + // temporary registers for reprogramming + integer c_ph_val_tmp[0:5]; + reg [31:0] c_high_val_tmp[0:5]; + reg [31:0] c_low_val_tmp[0:5]; + reg [8*6:1] c_mode_val_tmp[0:5]; + + // hold registers for reprogramming + integer c_ph_val_hold[0:5]; + reg [31:0] c_high_val_hold[0:5]; + reg [31:0] c_low_val_hold[0:5]; + reg [8*6:1] c_mode_val_hold[0:5]; + + // old values + reg [31:0] m_val_old[0:1]; + reg [31:0] m_val_tmp[0:1]; + reg [31:0] n_val_old[0:1]; + reg [8*6:1] m_mode_val_old[0:1]; + reg [8*6:1] n_mode_val_old[0:1]; + reg [31:0] c_high_val_old[0:5]; + reg [31:0] c_low_val_old[0:5]; + reg [8*6:1] c_mode_val_old[0:5]; + integer c_ph_val_old[0:5]; + integer m_ph_val_old; + integer m_ph_val_tmp; + + integer cp_curr_old; + integer cp_curr_val; + integer lfc_old; + integer lfc_val; + reg [9*8:1] lfr_val; + reg [9*8:1] lfr_old; + + reg [31:0] m_hi; + reg [31:0] m_lo; + + // ph tap orig values (POF) + integer c_ph_val_orig[0:5]; + integer m_ph_val_orig; + + reg schedule_vco; + reg stop_vco; + reg inclk_n; + + reg [7:0] vco_out; + reg [7:0] vco_out_last_value; + wire inclk_c0; + wire inclk_c1; + wire inclk_c2; + wire inclk_c3; + wire inclk_c4; + wire inclk_c5; + reg inclk_c0_from_vco; + reg inclk_c1_from_vco; + reg inclk_c2_from_vco; + reg inclk_c3_from_vco; + reg inclk_c4_from_vco; + reg inclk_c5_from_vco; + reg inclk_m_from_vco; + reg inclk_sclkout0_from_vco; + reg inclk_sclkout1_from_vco; + + wire inclk_m; + wire clk0_tmp; + wire clk1_tmp; + wire clk2_tmp; + wire clk3_tmp; + wire clk4_tmp; + wire clk5_tmp; + wire ena_pll; + wire n_cntr_inclk; + reg sclkout0_tmp; + reg sclkout1_tmp; + + reg vco_c0; + reg vco_c1; + + wire clk0; + wire clk1; + wire clk2; + wire clk3; + wire clk4; + wire clk5; + wire sclkout0; + wire sclkout1; + + wire c0_clk; + wire c1_clk; + wire c2_clk; + wire c3_clk; + wire c4_clk; + wire c5_clk; + + reg first_schedule; + + wire enable0_tmp; + wire enable1_tmp; + wire enable_0; + wire enable_1; + reg c0_tmp; + reg c1_tmp; + + reg vco_period_was_phase_adjusted; + reg phase_adjust_was_scheduled; + + wire refclk; + wire fbclk; + + wire pllena_reg; + wire test_mode_inclk; + + // for external feedback mode + + reg [31:0] ext_fbk_cntr_high; + reg [31:0] ext_fbk_cntr_low; + reg [31:0] ext_fbk_cntr_modulus; + reg [8*2:1] ext_fbk_cntr; + reg [8*6:1] ext_fbk_cntr_mode; + integer ext_fbk_cntr_ph; + integer ext_fbk_cntr_initial; + integer ext_fbk_cntr_index; + + // variables for clk_switch + reg clk0_is_bad; + reg clk1_is_bad; + reg inclk0_last_value; + reg inclk1_last_value; + reg other_clock_value; + reg other_clock_last_value; + reg primary_clk_is_bad; + reg current_clk_is_bad; + reg external_switch; + reg [8*6:1] current_clock; + reg active_clock; + reg clkloss_tmp; + reg got_curr_clk_falling_edge_after_clkswitch; + + integer clk0_count; + integer clk1_count; + integer switch_over_count; + + wire scandataout_tmp; + reg scandone_tmp; + reg scandone_tmp_last_value; + integer quiet_time; + integer slowest_clk_old; + integer slowest_clk_new; + + reg reconfig_err; + reg error; + time scanclk_last_rising_edge; + time scanread_active_edge; + reg got_first_scanclk; + reg got_first_gated_scanclk; + reg gated_scanclk; + integer scanclk_period; + reg scanclk_last_value; + reg scanread_reg; + reg scanwrite_reg; + reg scanwrite_enabled; + reg scanwrite_last_value; + reg [173:0] scan_data; + reg [173:0] tmp_scan_data; + reg c0_rising_edge_transfer_done; + reg c1_rising_edge_transfer_done; + reg c2_rising_edge_transfer_done; + reg c3_rising_edge_transfer_done; + reg c4_rising_edge_transfer_done; + reg c5_rising_edge_transfer_done; + reg scanread_setup_violation; + integer index; + integer scanclk_cycles; + reg d_msg; + + integer num_output_cntrs; + reg no_warn; + + // INTERNAL PARAMETERS + parameter GPP_SCAN_CHAIN = 174; + parameter FAST_SCAN_CHAIN = 75; + // primary clk is always inclk0 + parameter primary_clock = "inclk0"; + + // internal variables for scaling of multiply_by and divide_by values + integer i_clk0_mult_by; + integer i_clk0_div_by; + integer i_clk1_mult_by; + integer i_clk1_div_by; + integer i_clk2_mult_by; + integer i_clk2_div_by; + integer i_clk3_mult_by; + integer i_clk3_div_by; + integer i_clk4_mult_by; + integer i_clk4_div_by; + integer i_clk5_mult_by; + integer i_clk5_div_by; + integer max_d_value; + integer new_multiplier; + + // internal variables for storing the phase shift number.(used in lvds mode only) + integer i_clk0_phase_shift; + integer i_clk1_phase_shift; + integer i_clk2_phase_shift; + + // user to advanced internal signals + + integer i_m_initial; + integer i_m; + integer i_n; + integer i_m2; + integer i_n2; + integer i_ss; + integer i_c_high[0:5]; + integer i_c_low[0:5]; + integer i_c_initial[0:5]; + integer i_c_ph[0:5]; + reg [8*6:1] i_c_mode[0:5]; + + integer i_vco_min; + integer i_vco_max; + integer i_vco_center; + integer i_pfd_min; + integer i_pfd_max; + integer i_m_ph; + integer m_ph_val; + reg [8*2:1] i_clk5_counter; + reg [8*2:1] i_clk4_counter; + reg [8*2:1] i_clk3_counter; + reg [8*2:1] i_clk2_counter; + reg [8*2:1] i_clk1_counter; + reg [8*2:1] i_clk0_counter; + integer i_charge_pump_current; + integer i_loop_filter_r; + integer max_neg_abs; + integer output_count; + integer new_divisor; + + integer loop_filter_c_arr[0:3]; + integer fpll_loop_filter_c_arr[0:3]; + integer charge_pump_curr_arr[0:15]; + reg [9*8:1] loop_filter_r_arr[0:39]; + + reg pll_in_test_mode; + reg pll_is_in_reset; + + // uppercase to lowercase parameter values + reg [8*`WORD_LENGTH:1] l_operation_mode; + reg [8*`WORD_LENGTH:1] l_pll_type; + reg [8*`WORD_LENGTH:1] l_qualify_conf_done; + reg [8*`WORD_LENGTH:1] l_compensate_clock; + reg [8*`WORD_LENGTH:1] l_scan_chain; + reg [8*`WORD_LENGTH:1] l_primary_clock; + reg [8*`WORD_LENGTH:1] l_gate_lock_signal; + reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk; + reg [8*`WORD_LENGTH:1] l_switch_over_type; + reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock; + reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter; + reg [8*`WORD_LENGTH:1] l_feedback_source; + reg [8*`WORD_LENGTH:1] l_bandwidth_type; + reg [8*`WORD_LENGTH:1] l_simulation_type; + reg [8*`WORD_LENGTH:1] l_enable0_counter; + reg [8*`WORD_LENGTH:1] l_enable1_counter; + + reg init; + + + // finds the closest integer fraction of a given pair of numerator and denominator. + task find_simple_integer_fraction; + input numerator; + input denominator; + input max_denom; + output fraction_num; + output fraction_div; + parameter max_iter = 20; + + integer numerator; + integer denominator; + integer max_denom; + integer fraction_num; + integer fraction_div; + + integer quotient_array[max_iter-1:0]; + integer int_loop_iter; + integer int_quot; + integer m_value; + integer d_value; + integer old_m_value; + integer swap; + + integer loop_iter; + integer num; + integer den; + integer i_max_iter; + + begin + loop_iter = 0; + num = numerator; + den = denominator; + i_max_iter = max_iter; + + while (loop_iter < i_max_iter) + begin + int_quot = num / den; + quotient_array[loop_iter] = int_quot; + num = num - (den*int_quot); + loop_iter=loop_iter+1; + + if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter)) + begin + // calculate the numerator and denominator if there is a restriction on the + // max denom value or if the loop is ending + m_value = 0; + d_value = 1; + // get the rounded value at this stage for the remaining fraction + if (den != 0) + begin + m_value = (2*num/den); + end + // calculate the fraction numerator and denominator at this stage + for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1) + begin + if (m_value == 0) + begin + m_value = quotient_array[int_loop_iter]; + d_value = 1; + end + else + begin + old_m_value = m_value; + m_value = quotient_array[int_loop_iter]*m_value + d_value; + d_value = old_m_value; + end + end + // if the denominator is less than the maximum denom_value or if there is no restriction save it + if ((d_value <= max_denom) || (max_denom == -1)) + begin + fraction_num = m_value; + fraction_div = d_value; + end + // end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round) + if (((d_value > max_denom) && (max_denom != -1)) || (num == 0)) + begin + i_max_iter = loop_iter; + end + end + // swap the numerator and denominator for the next round + swap = den; + den = num; + num = swap; + end + end + endtask // find_simple_integer_fraction + + // get the absolute value + function integer abs; + input value; + integer value; + begin + if (value < 0) + abs = value * -1; + else abs = value; + end + endfunction + + // find twice the period of the slowest clock + function integer slowest_clk; + input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, refclk, m_mod; + integer C0, C1, C2, C3, C4, C5; + reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode; + integer refclk; + reg [31:0] m_mod; + integer max_modulus; + begin + max_modulus = 1; + if (C0_mode != "bypass" && C0_mode != " off") + max_modulus = C0; + if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off") + max_modulus = C1; + if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off") + max_modulus = C2; + if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off") + max_modulus = C3; + if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off") + max_modulus = C4; + if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off") + max_modulus = C5; + + slowest_clk = (refclk * max_modulus *2 / m_mod); + end + endfunction + + // count the number of digits in the given integer + function integer count_digit; + input X; + integer X; + integer count, result; + begin + count = 0; + result = X; + while (result != 0) + begin + result = (result / 10); + count = count + 1; + end + + count_digit = count; + end + endfunction + + // reduce the given huge number(X) to Y significant digits + function integer scale_num; + input X, Y; + integer X, Y; + integer count; + integer fac_ten, lc; + begin + fac_ten = 1; + count = count_digit(X); + + for (lc = 0; lc < (count-Y); lc = lc + 1) + fac_ten = fac_ten * 10; + + scale_num = (X / fac_ten); + end + endfunction + + // find the greatest common denominator of X and Y + function integer gcd; + input X,Y; + integer X,Y; + integer L, S, R, G; + begin + if (X < Y) // find which is smaller. + begin + S = X; + L = Y; + end + else + begin + S = Y; + L = X; + end + + R = S; + while ( R > 1) + begin + S = L; + L = R; + R = S % L; // divide bigger number by smaller. + // remainder becomes smaller number. + end + if (R == 0) // if evenly divisible then L is gcd else it is 1. + G = L; + else + G = R; + gcd = G; + end + endfunction + + // find the least common multiple of A1 to A10 + function integer lcm; + input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P; + integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P; + integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R; + begin + M1 = (A1 * A2)/gcd(A1, A2); + M2 = (M1 * A3)/gcd(M1, A3); + M3 = (M2 * A4)/gcd(M2, A4); + M4 = (M3 * A5)/gcd(M3, A5); + M5 = (M4 * A6)/gcd(M4, A6); + M6 = (M5 * A7)/gcd(M5, A7); + M7 = (M6 * A8)/gcd(M6, A8); + M8 = (M7 * A9)/gcd(M7, A9); + M9 = (M8 * A10)/gcd(M8, A10); + if (M9 < 3) + R = 10; + else if ((M9 <= 10) && (M9 >= 3)) + R = 4 * M9; + else if (M9 > 1000) + R = scale_num(M9, 3); + else + R = M9; + lcm = R; + end + endfunction + + // find the factor of division of the output clock frequency + // compared to the VCO + function integer output_counter_value; + input clk_divide, clk_mult, M, N; + integer clk_divide, clk_mult, M, N; + integer R; + begin + R = (clk_divide * M)/(clk_mult * N); + output_counter_value = R; + end + endfunction + + // find the mode of each of the PLL counters - bypass, even or odd + function [8*6:1] counter_mode; + input duty_cycle; + input output_counter_value; + integer duty_cycle; + integer output_counter_value; + integer half_cycle_high; + reg [8*6:1] R; + begin + half_cycle_high = (2*duty_cycle*output_counter_value)/100; + if (output_counter_value == 1) + R = "bypass"; + else if ((half_cycle_high % 2) == 0) + R = " even"; + else + R = " odd"; + counter_mode = R; + end + endfunction + + // find the number of VCO clock cycles to hold the output clock high + function integer counter_high; + input output_counter_value, duty_cycle; + integer output_counter_value, duty_cycle; + integer half_cycle_high; + integer tmp_counter_high; + integer mode; + begin + half_cycle_high = (2*duty_cycle*output_counter_value)/100; + mode = ((half_cycle_high % 2) == 0); + tmp_counter_high = half_cycle_high/2; + counter_high = tmp_counter_high + !mode; + end + endfunction + + // find the number of VCO clock cycles to hold the output clock low + function integer counter_low; + input output_counter_value, duty_cycle; + integer output_counter_value, duty_cycle, counter_h; + integer half_cycle_high; + integer mode; + integer tmp_counter_high; + begin + half_cycle_high = (2*duty_cycle*output_counter_value)/100; + mode = ((half_cycle_high % 2) == 0); + tmp_counter_high = half_cycle_high/2; + counter_h = tmp_counter_high + !mode; + counter_low = output_counter_value - counter_h; + end + endfunction + + // find the smallest time delay amongst t1 to t10 + function integer mintimedelay; + input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10; + integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10; + integer m1,m2,m3,m4,m5,m6,m7,m8,m9; + begin + if (t1 < t2) + m1 = t1; + else + m1 = t2; + if (m1 < t3) + m2 = m1; + else + m2 = t3; + if (m2 < t4) + m3 = m2; + else + m3 = t4; + if (m3 < t5) + m4 = m3; + else + m4 = t5; + if (m4 < t6) + m5 = m4; + else + m5 = t6; + if (m5 < t7) + m6 = m5; + else + m6 = t7; + if (m6 < t8) + m7 = m6; + else + m7 = t8; + if (m7 < t9) + m8 = m7; + else + m8 = t9; + if (m8 < t10) + m9 = m8; + else + m9 = t10; + if (m9 > 0) + mintimedelay = m9; + else + mintimedelay = 0; + end + endfunction + + // find the numerically largest negative number, and return its absolute value + function integer maxnegabs; + input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10; + integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10; + integer m1,m2,m3,m4,m5,m6,m7,m8,m9; + begin + if (t1 < t2) m1 = t1; else m1 = t2; + if (m1 < t3) m2 = m1; else m2 = t3; + if (m2 < t4) m3 = m2; else m3 = t4; + if (m3 < t5) m4 = m3; else m4 = t5; + if (m4 < t6) m5 = m4; else m5 = t6; + if (m5 < t7) m6 = m5; else m6 = t7; + if (m6 < t8) m7 = m6; else m7 = t8; + if (m7 < t9) m8 = m7; else m8 = t9; + if (m8 < t10) m9 = m8; else m9 = t10; + maxnegabs = (m9 < 0) ? 0 - m9 : 0; + end + endfunction + + // adjust the given tap_phase by adding the largest negative number (ph_base) + function integer ph_adjust; + input tap_phase, ph_base; + integer tap_phase, ph_base; + begin + ph_adjust = tap_phase + ph_base; + end + endfunction + + // find the number of VCO clock cycles to wait initially before the first + // rising edge of the output clock + function integer counter_initial; + input tap_phase, m, n; + integer tap_phase, m, n, phase; + begin + if (tap_phase < 0) tap_phase = 0 - tap_phase; + // adding 0.5 for rounding correction (required in order to round + // to the nearest integer instead of truncating) + phase = ((tap_phase * m) / (360 * n)) + 0.5; + counter_initial = phase; + end + endfunction + + // find which VCO phase tap to align the rising edge of the output clock to + function integer counter_ph; + input tap_phase; + input m,n; + integer m,n, phase; + integer tap_phase; + begin + // adding 0.5 for rounding correction + phase = (tap_phase * m / n) + 0.5; + counter_ph = (phase % 360)/45; + end + endfunction + + // convert the given string to length 6 by padding with spaces + function [8*6:1] translate_string; + input [8*6:1] mode; + reg [8*6:1] new_mode; + begin + if (mode == "bypass") + new_mode = "bypass"; + else if (mode == "even") + new_mode = " even"; + else if (mode == "odd") + new_mode = " odd"; + + translate_string = new_mode; + end + endfunction + + // convert string to integer with sign + function integer str2int; + input [8*16:1] s; + + reg [8*16:1] reg_s; + reg [8:1] digit; + reg [8:1] tmp; + integer m, magnitude; + integer sign; + + begin + sign = 1; + magnitude = 0; + reg_s = s; + for (m=1; m<=16; m=m+1) + begin + tmp = reg_s[128:121]; + digit = tmp & 8'b00001111; + reg_s = reg_s << 8; + // Accumulate ascii digits 0-9 only. + if ((tmp>=48) && (tmp<=57)) + magnitude = (magnitude * 10) + digit; + if (tmp == 45) + sign = -1; // Found a '-' character, i.e. number is negative. + end + str2int = sign*magnitude; + end + endfunction + + // this is for stratixii lvds only + // convert phase delay to integer + function integer get_int_phase_shift; + input [8*16:1] s; + input i_phase_shift; + integer i_phase_shift; + + begin + if (i_phase_shift != 0) + begin + get_int_phase_shift = i_phase_shift; + end + else + begin + get_int_phase_shift = str2int(s); + end + end + endfunction + + // calculate the given phase shift (in ps) in terms of degrees + function integer get_phase_degree; + input phase_shift; + integer phase_shift, result; + begin + result = (phase_shift * 360) / inclk0_input_frequency; + // this is to round up the calculation result + if ( result > 0 ) + result = result + 1; + else if ( result < 0 ) + result = result - 1; + else + result = 0; + + // assign the rounded up result + get_phase_degree = result; + end + endfunction + + // convert uppercase parameter values to lowercase + // assumes that the maximum character length of a parameter is 18 + function [8*`WORD_LENGTH:1] alpha_tolower; + input [8*`WORD_LENGTH:1] given_string; + + reg [8*`WORD_LENGTH:1] return_string; + reg [8*`WORD_LENGTH:1] reg_string; + reg [8:1] tmp; + reg [8:1] conv_char; + integer byte_count; + begin + return_string = " "; // initialise strings to spaces + conv_char = " "; + reg_string = given_string; + for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1) + begin + tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)]; + reg_string = reg_string << 8; + if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90 + begin + conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set + return_string = {return_string, conv_char}; + end + else + return_string = {return_string, tmp}; + end + + alpha_tolower = return_string; + end + endfunction + + function integer display_msg; + input [8*2:1] cntr_name; + input msg_code; + integer msg_code; + begin + if (msg_code == 1) + $display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name); + else if (msg_code == 2) + $display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name); + else if (msg_code == 3) + $display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name); + else if (msg_code == 4) + $display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name); + + display_msg = 1; + end + endfunction + + initial + begin + + // convert string parameter values from uppercase to lowercase, + // as expected in this model + l_operation_mode = alpha_tolower(operation_mode); + l_pll_type = alpha_tolower(pll_type); + l_qualify_conf_done = alpha_tolower(qualify_conf_done); + l_compensate_clock = alpha_tolower(compensate_clock); + l_primary_clock = alpha_tolower(primary_clock); + l_gate_lock_signal = alpha_tolower(gate_lock_signal); + l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk); + l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock); + l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter); + l_switch_over_type = alpha_tolower(switch_over_type); + l_feedback_source = alpha_tolower(feedback_source); + l_bandwidth_type = alpha_tolower(bandwidth_type); + l_simulation_type = alpha_tolower(simulation_type); + l_enable0_counter = alpha_tolower(enable0_counter); + l_enable1_counter = alpha_tolower(enable1_counter); + + // initialize charge_pump_current, and loop_filter tables + loop_filter_c_arr[0] = 57; + loop_filter_c_arr[1] = 16; + loop_filter_c_arr[2] = 36; + loop_filter_c_arr[3] = 5; + + fpll_loop_filter_c_arr[0] = 18; + fpll_loop_filter_c_arr[1] = 13; + fpll_loop_filter_c_arr[2] = 8; + fpll_loop_filter_c_arr[3] = 2; + + charge_pump_curr_arr[0] = 6; + charge_pump_curr_arr[1] = 12; + charge_pump_curr_arr[2] = 30; + charge_pump_curr_arr[3] = 36; + charge_pump_curr_arr[4] = 52; + charge_pump_curr_arr[5] = 57; + charge_pump_curr_arr[6] = 72; + charge_pump_curr_arr[7] = 77; + charge_pump_curr_arr[8] = 92; + charge_pump_curr_arr[9] = 96; + charge_pump_curr_arr[10] = 110; + charge_pump_curr_arr[11] = 114; + charge_pump_curr_arr[12] = 127; + charge_pump_curr_arr[13] = 131; + charge_pump_curr_arr[14] = 144; + charge_pump_curr_arr[15] = 148; + + loop_filter_r_arr[0] = " 1.000000"; + loop_filter_r_arr[1] = " 1.500000"; + loop_filter_r_arr[2] = " 2.000000"; + loop_filter_r_arr[3] = " 2.500000"; + loop_filter_r_arr[4] = " 3.000000"; + loop_filter_r_arr[5] = " 3.500000"; + loop_filter_r_arr[6] = " 4.000000"; + loop_filter_r_arr[7] = " 4.500000"; + loop_filter_r_arr[8] = " 5.000000"; + loop_filter_r_arr[9] = " 5.500000"; + loop_filter_r_arr[10] = " 6.000000"; + loop_filter_r_arr[11] = " 6.500000"; + loop_filter_r_arr[12] = " 7.000000"; + loop_filter_r_arr[13] = " 7.500000"; + loop_filter_r_arr[14] = " 8.000000"; + loop_filter_r_arr[15] = " 8.500000"; + loop_filter_r_arr[16] = " 9.000000"; + loop_filter_r_arr[17] = " 9.500000"; + loop_filter_r_arr[18] = "10.000000"; + loop_filter_r_arr[19] = "10.500000"; + loop_filter_r_arr[20] = "11.000000"; + loop_filter_r_arr[21] = "11.500000"; + loop_filter_r_arr[22] = "12.000000"; + loop_filter_r_arr[23] = "12.500000"; + loop_filter_r_arr[24] = "13.000000"; + loop_filter_r_arr[25] = "13.500000"; + loop_filter_r_arr[26] = "14.000000"; + loop_filter_r_arr[27] = "14.500000"; + loop_filter_r_arr[28] = "15.000000"; + loop_filter_r_arr[29] = "15.500000"; + loop_filter_r_arr[30] = "16.000000"; + loop_filter_r_arr[31] = "16.500000"; + loop_filter_r_arr[32] = "17.000000"; + loop_filter_r_arr[33] = "17.500000"; + loop_filter_r_arr[34] = "18.000000"; + loop_filter_r_arr[35] = "18.500000"; + loop_filter_r_arr[36] = "19.000000"; + loop_filter_r_arr[37] = "19.500000"; + loop_filter_r_arr[38] = "20.000000"; + loop_filter_r_arr[39] = "20.500000"; + + if (m == 0) + begin + i_clk5_counter = "c5" ; + i_clk4_counter = "c4" ; + i_clk3_counter = "c3" ; + i_clk2_counter = "c2" ; + i_clk1_counter = "c1" ; + i_clk0_counter = "c0" ; + end + else begin + i_clk5_counter = alpha_tolower(clk5_counter); + i_clk4_counter = alpha_tolower(clk4_counter); + i_clk3_counter = alpha_tolower(clk3_counter); + i_clk2_counter = alpha_tolower(clk2_counter); + i_clk1_counter = alpha_tolower(clk1_counter); + i_clk0_counter = alpha_tolower(clk0_counter); + end + + // VCO feedback loop settings for external feedback mode + // first find which counter is used for feedback + if (l_operation_mode == "external_feedback") + begin + if (l_feedback_source == "clk0") + ext_fbk_cntr = i_clk0_counter; + else if (l_feedback_source == "clk1") + ext_fbk_cntr = i_clk1_counter; + else if (l_feedback_source == "clk2") + ext_fbk_cntr = i_clk2_counter; + else if (l_feedback_source == "clk3") + ext_fbk_cntr = i_clk3_counter; + else if (l_feedback_source == "clk4") + ext_fbk_cntr = i_clk4_counter; + else if (l_feedback_source == "clk5") + ext_fbk_cntr = i_clk5_counter; + else ext_fbk_cntr = "c0"; + + if (ext_fbk_cntr == "c0") + ext_fbk_cntr_index = 0; + else if (ext_fbk_cntr == "c1") + ext_fbk_cntr_index = 1; + else if (ext_fbk_cntr == "c2") + ext_fbk_cntr_index = 2; + else if (ext_fbk_cntr == "c3") + ext_fbk_cntr_index = 3; + else if (ext_fbk_cntr == "c4") + ext_fbk_cntr_index = 4; + else if (ext_fbk_cntr == "c5") + ext_fbk_cntr_index = 5; + end + + if (m == 0) + begin + + // set the limit of the divide_by value that can be returned by + // the following function. + max_d_value = 500; + + // scale down the multiply_by and divide_by values provided by the design + // before attempting to use them in the calculations below + find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by, + max_d_value, i_clk0_mult_by, i_clk0_div_by); + find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by, + max_d_value, i_clk1_mult_by, i_clk1_div_by); + find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by, + max_d_value, i_clk2_mult_by, i_clk2_div_by); + find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by, + max_d_value, i_clk3_mult_by, i_clk3_div_by); + find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by, + max_d_value, i_clk4_mult_by, i_clk4_div_by); + find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by, + max_d_value, i_clk5_mult_by, i_clk5_div_by); + + // convert user parameters to advanced + if (((l_pll_type == "fast") || (l_pll_type == "lvds")) && (vco_multiply_by != 0) && (vco_divide_by != 0)) + begin + i_n = vco_divide_by; + i_m = vco_multiply_by; + end + else begin + i_n = 1; + i_m = lcm (i_clk0_mult_by, i_clk1_mult_by, + i_clk2_mult_by, i_clk3_mult_by, + i_clk4_mult_by, i_clk5_mult_by, + 1, 1, 1, 1, inclk0_input_frequency); + end + + i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_c_high[5] = counter_high (output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + + i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by, + i_clk0_mult_by, i_m, i_n), clk0_duty_cycle); + i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by, + i_clk1_mult_by, i_m, i_n), clk1_duty_cycle); + i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by, + i_clk2_mult_by, i_m, i_n), clk2_duty_cycle); + i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by, + i_clk3_mult_by, i_m, i_n), clk3_duty_cycle); + i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by, + i_clk4_mult_by, i_m, i_n), clk4_duty_cycle); + i_c_low[5] = counter_low (output_counter_value(i_clk5_div_by, + i_clk5_mult_by, i_m, i_n), clk5_duty_cycle); + + if (l_pll_type == "flvds") + begin + // Need to readjust phase shift values when the clock multiply value has been readjusted. + new_multiplier = clk0_multiply_by / i_clk0_mult_by; + i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier); + i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier); + i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier); + end + else + begin + i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num); + i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num); + i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num); + end + + max_neg_abs = maxnegabs ( i_clk0_phase_shift, + i_clk1_phase_shift, + i_clk2_phase_shift, + str2int(clk3_phase_shift), + str2int(clk4_phase_shift), + str2int(clk5_phase_shift), + 0, 0, 0, 0); + + i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n); + i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n); + i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n); + i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n); + i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n); + i_c_initial[5] = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n); + + i_c_mode[0] = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n)); + i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n)); + i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n)); + i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n)); + i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n)); + i_c_mode[5] = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n)); + + i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n); + i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n); + + i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n); + i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n); + i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n); + i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n); + i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n); + i_c_ph[5] = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n); + + // in external feedback mode, need to adjust M value to take + // into consideration the external feedback counter value + if (l_operation_mode == "external_feedback") + begin + // if there is a negative phase shift, m_initial can only be 1 + if (max_neg_abs > 0) + i_m_initial = 1; + + if (i_c_mode[ext_fbk_cntr_index] == "bypass") + output_count = 1; + else + output_count = i_c_high[ext_fbk_cntr_index] + i_c_low[ext_fbk_cntr_index]; + + if (i_m > output_count) + i_m = i_m / output_count; + else + begin + new_divisor = gcd(i_m, output_count); + i_m = i_m / new_divisor; + i_n = output_count / new_divisor; + end + end + + end + else + begin // m != 0 + + i_n = n; + i_m = m; + i_c_high[0] = c0_high; + i_c_high[1] = c1_high; + i_c_high[2] = c2_high; + i_c_high[3] = c3_high; + i_c_high[4] = c4_high; + i_c_high[5] = c5_high; + i_c_low[0] = c0_low; + i_c_low[1] = c1_low; + i_c_low[2] = c2_low; + i_c_low[3] = c3_low; + i_c_low[4] = c4_low; + i_c_low[5] = c5_low; + i_c_initial[0] = c0_initial; + i_c_initial[1] = c1_initial; + i_c_initial[2] = c2_initial; + i_c_initial[3] = c3_initial; + i_c_initial[4] = c4_initial; + i_c_initial[5] = c5_initial; + i_c_mode[0] = translate_string(alpha_tolower(c0_mode)); + i_c_mode[1] = translate_string(alpha_tolower(c1_mode)); + i_c_mode[2] = translate_string(alpha_tolower(c2_mode)); + i_c_mode[3] = translate_string(alpha_tolower(c3_mode)); + i_c_mode[4] = translate_string(alpha_tolower(c4_mode)); + i_c_mode[5] = translate_string(alpha_tolower(c5_mode)); + i_c_ph[0] = c0_ph; + i_c_ph[1] = c1_ph; + i_c_ph[2] = c2_ph; + i_c_ph[3] = c3_ph; + i_c_ph[4] = c4_ph; + i_c_ph[5] = c5_ph; + i_m_ph = m_ph; // default + i_m_initial = m_initial; + + end // user to advanced conversion + + refclk_period = inclk0_input_frequency * i_n; + + m_times_vco_period = refclk_period; + new_m_times_vco_period = refclk_period; + + fbclk_period = 0; + high_time = 0; + low_time = 0; + schedule_vco = 0; + vco_out[7:0] = 8'b0; + fbclk_last_value = 0; + offset = 0; + temp_offset = 0; + got_first_refclk = 0; + got_first_fbclk = 0; + fbclk_time = 0; + first_fbclk_time = 0; + refclk_time = 0; + first_schedule = 1; + sched_time = 0; + vco_val = 0; + c0_got_first_rising_edge = 0; + c1_got_first_rising_edge = 0; + vco_c0_last_value = 0; + c0_count = 2; + c0_initial_count = 1; + c1_count = 2; + c1_initial_count = 1; + c0_tmp = 0; + c1_tmp = 0; + gate_count = 0; + gate_out = 0; + initial_delay = 0; + fbk_phase = 0; + for (i = 0; i <= 7; i = i + 1) + begin + phase_shift[i] = 0; + last_phase_shift[i] = 0; + end + fbk_delay = 0; + inclk_n = 0; + cycle_to_adjust = 0; + m_delay = 0; + vco_c0 = 0; + vco_c1 = 0; + total_pull_back = 0; + pull_back_M = 0; + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 0; + ena_ipd_last_value = 0; + inclk_out_of_range = 0; + scandone_tmp = 0; + schedule_vco_last_value = 0; + + // set initial values for counter parameters + m_initial_val = i_m_initial; + m_val[0] = i_m; + n_val[0] = i_n; + m_ph_val = i_m_ph; + m_ph_val_orig = i_m_ph; + m_ph_val_tmp = i_m_ph; + m_val_tmp[0] = i_m; + + m_val[1] = m2; + n_val[1] = n2; + + if (m_val[0] == 1) + m_mode_val[0] = "bypass"; + else m_mode_val[0] = ""; + if (m_val[1] == 1) + m_mode_val[1] = "bypass"; + if (n_val[0] == 1) + n_mode_val[0] = "bypass"; + if (n_val[1] == 1) + n_mode_val[1] = "bypass"; + + for (i = 0; i < 6; i=i+1) + begin + c_high_val[i] = i_c_high[i]; + c_low_val[i] = i_c_low[i]; + c_initial_val[i] = i_c_initial[i]; + c_mode_val[i] = i_c_mode[i]; + c_ph_val[i] = i_c_ph[i]; + c_high_val_tmp[i] = i_c_high[i]; + c_low_val_tmp[i] = i_c_low[i]; + if (c_mode_val[i] == "bypass") + begin + if (l_pll_type == "fast" || l_pll_type == "lvds") + begin + c_high_val[i] = 5'b10000; + c_low_val[i] = 5'b10000; + c_high_val_tmp[i] = 5'b10000; + c_low_val_tmp[i] = 5'b10000; + end + else begin + c_high_val[i] = 9'b100000000; + c_low_val[i] = 9'b100000000; + c_high_val_tmp[i] = 9'b100000000; + c_low_val_tmp[i] = 9'b100000000; + end + end + + c_mode_val_tmp[i] = i_c_mode[i]; + c_ph_val_tmp[i] = i_c_ph[i]; + + c_ph_val_orig[i] = i_c_ph[i]; + c_high_val_hold[i] = i_c_high[i]; + c_low_val_hold[i] = i_c_low[i]; + c_mode_val_hold[i] = i_c_mode[i]; + end + + lfc_val = loop_filter_c; + lfr_val = loop_filter_r; + cp_curr_val = charge_pump_current; + + i = 0; + j = 0; + inclk_last_value = 0; + + ext_fbk_cntr_ph = 0; + ext_fbk_cntr_initial = 1; + + // initialize clkswitch variables + + clk0_is_bad = 0; + clk1_is_bad = 0; + inclk0_last_value = 0; + inclk1_last_value = 0; + other_clock_value = 0; + other_clock_last_value = 0; + primary_clk_is_bad = 0; + current_clk_is_bad = 0; + external_switch = 0; + current_clock = l_primary_clock; + active_clock = 0; // primary_clk is always inclk0 + if (l_pll_type == "fast") + l_switch_over_type = "manual"; + + if (l_switch_over_type == "manual" && clkswitch_ipd === 1'b1) + begin + current_clock = "inclk1"; + active_clock = 1; + end + clkloss_tmp = 0; + got_curr_clk_falling_edge_after_clkswitch = 0; + clk0_count = 0; + clk1_count = 0; + switch_over_count = 0; + + // initialize reconfiguration variables + // quiet_time + quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0], + c_high_val[1]+c_low_val[1], c_mode_val[1], + c_high_val[2]+c_low_val[2], c_mode_val[2], + c_high_val[3]+c_low_val[3], c_mode_val[3], + c_high_val[4]+c_low_val[4], c_mode_val[4], + c_high_val[5]+c_low_val[5], c_mode_val[5], + refclk_period, m_val[0]); + reconfig_err = 0; + error = 0; + scanread_active_edge = 0; + if ((l_pll_type == "fast") || (l_pll_type == "lvds")) + begin + scan_chain_length = FAST_SCAN_CHAIN; + num_output_cntrs = 4; + end + else + begin + scan_chain_length = GPP_SCAN_CHAIN; + num_output_cntrs = 6; + end + scanread_reg = 0; + scanwrite_reg = 0; + scanwrite_enabled = 0; + c0_rising_edge_transfer_done = 0; + c1_rising_edge_transfer_done = 0; + c2_rising_edge_transfer_done = 0; + c3_rising_edge_transfer_done = 0; + c4_rising_edge_transfer_done = 0; + c5_rising_edge_transfer_done = 0; + got_first_scanclk = 0; + got_first_gated_scanclk = 0; + gated_scanclk = 1; + scanread_setup_violation = 0; + index = 0; + + // initialize the scan_chain contents + // CP/LF bits + scan_data[11:0] = 12'b0; + for (i = 0; i <= 3; i = i + 1) + begin + if ((l_pll_type == "fast") || (l_pll_type == "lvds")) + begin + if (fpll_loop_filter_c_arr[i] == loop_filter_c) + scan_data[11:10] = i; + end + else begin + if (loop_filter_c_arr[i] == loop_filter_c) + scan_data[11:10] = i; + end + end + for (i = 0; i <= 15; i = i + 1) + begin + if (charge_pump_curr_arr[i] == charge_pump_current) + scan_data[3:0] = i; + end + for (i = 0; i <= 39; i = i + 1) + begin + if (loop_filter_r_arr[i] == loop_filter_r) + begin + if ((i >= 16) && (i <= 23)) + scan_data[9:4] = i+8; + else if ((i >= 24) && (i <= 31)) + scan_data[9:4] = i+16; + else if (i >= 32) + scan_data[9:4] = i+24; + else + scan_data[9:4] = i; + end + end + + if (l_pll_type == "fast" || l_pll_type == "lvds") + begin + scan_data[21:12] = 10'b0; // M, C3-C0 ph + // C0-C3 high + scan_data[25:22] = c_high_val[0]; + scan_data[35:32] = c_high_val[1]; + scan_data[45:42] = c_high_val[2]; + scan_data[55:52] = c_high_val[3]; + // C0-C3 low + scan_data[30:27] = c_low_val[0]; + scan_data[40:37] = c_low_val[1]; + scan_data[50:47] = c_low_val[2]; + scan_data[60:57] = c_low_val[3]; + // C0-C3 mode + for (i = 0; i < 4; i = i + 1) + begin + if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass") + begin + scan_data[26 + (10*i)] = 1; + if (c_mode_val[i] == " off") + scan_data[31 + (10*i)] = 1; + else + scan_data[31 + (10*i)] = 0; + end + else begin + scan_data[26 + (10*i)] = 0; + if (c_mode_val[i] == " odd") + scan_data[31 + (10*i)] = 1; + else + scan_data[31 + (10*i)] = 0; + end + end + // M + if (m_mode_val[0] == "bypass") + begin + scan_data[66] = 1; + scan_data[71] = 0; + scan_data[65:62] = 4'b0; + scan_data[70:67] = 4'b0; + end + else begin + scan_data[66] = 0; // set BYPASS bit to 0 + scan_data[70:67] = m_val[0]/2; // set M low + if (m_val[0] % 2 == 0) + begin + // M is an even no. : set M high = low, + // set odd/even bit to 0 + scan_data[65:62] = scan_data[70:67]; + scan_data[71] = 0; + end + else begin // M is odd : M high = low + 1 + scan_data[65:62] = (m_val[0]/2) + 1; + scan_data[71] = 1; + end + end + // N + scan_data[73:72] = n_val[0]; + if (n_mode_val[0] == "bypass") + begin + scan_data[74] = 1; + scan_data[73:72] = 2'b0; + end + end + else begin // PLL type is enhanced/auto + scan_data[25:12] = 14'b0; + + // C5-C0 high + scan_data[33:26] = c_high_val[5]; + scan_data[51:44] = c_high_val[4]; + scan_data[69:62] = c_high_val[3]; + scan_data[87:80] = c_high_val[2]; + scan_data[105:98] = c_high_val[1]; + scan_data[123:116] = c_high_val[0]; + // C5-C0 low + scan_data[42:35] = c_low_val[5]; + scan_data[60:53] = c_low_val[4]; + scan_data[78:71] = c_low_val[3]; + scan_data[96:89] = c_low_val[2]; + scan_data[114:107] = c_low_val[1]; + scan_data[132:125] = c_low_val[0]; + + for (i = 5; i >= 0; i = i - 1) + begin + if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass") + begin + scan_data[124 - (18*i)] = 1; + if (c_mode_val[i] == " off") + scan_data[133 - (18*i)] = 1; + else + scan_data[133 - (18*i)] = 0; + end + else begin + scan_data[124 - (18*i)] = 0; + if (c_mode_val[i] == " odd") + scan_data[133 - (18*i)] = 1; + else + scan_data[133 - (18*i)] = 0; + end + end + + scan_data[142:134] = m_val[0]; + scan_data[143] = 0; + scan_data[152:144] = m_val[1]; + scan_data[153] = 0; + if (m_mode_val[0] == "bypass") + begin + scan_data[143] = 1; + scan_data[142:134] = 9'b0; + end + if (m_mode_val[1] == "bypass") + begin + scan_data[153] = 1; + scan_data[152:144] = 9'b0; + end + + scan_data[162:154] = n_val[0]; + scan_data[172:164] = n_val[1]; + if (n_mode_val[0] == "bypass") + begin + scan_data[163] = 1; + scan_data[162:154] = 9'b0; + end + if (n_mode_val[1] == "bypass") + begin + scan_data[173] = 1; + scan_data[172:164] = 9'b0; + end + end + + // now save this counter's parameters + ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index]; + ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index]; + ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index]; + ext_fbk_cntr_initial = c_initial_val[ext_fbk_cntr_index]; + ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index]; + + if (ext_fbk_cntr_mode == "bypass") + ext_fbk_cntr_modulus = 1; + else + ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low; + + l_index = 1; + stop_vco = 0; + cycles_to_lock = 0; + cycles_to_unlock = 0; + locked_tmp = 0; + pll_is_locked = 0; + pll_about_to_lock = 0; + no_warn = 1'b0; + + // check if pll is in test mode + if (m_test_source != 5 || c0_test_source != 5 || c1_test_source != 5 || c2_test_source != 5 || c3_test_source != 5 || c4_test_source != 5 || c5_test_source != 5) + pll_in_test_mode = 1'b1; + else + pll_in_test_mode = 1'b0; + + + pll_is_in_reset = 0; + end + + always @(clkswitch_ipd) + begin + if (clkswitch_ipd === 1'b1 && l_switch_over_type == "auto") + external_switch = 1; + else if (l_switch_over_type == "manual") + begin + if (clkswitch_ipd === 1'b1) + begin + current_clock = "inclk1"; + active_clock = 1; + inclk_n = inclk1_ipd; + end + else if (clkswitch_ipd === 1'b0) + begin + current_clock = "inclk0"; + active_clock = 0; + inclk_n = inclk0_ipd; + end + end + end + + always @(inclk0_ipd or inclk1_ipd) + begin + // save the inclk event value + if (inclk0_ipd !== inclk0_last_value) + begin + if (current_clock !== "inclk0") + other_clock_value = inclk0_ipd; + end + if (inclk1_ipd !== inclk1_last_value) + begin + if (current_clock !== "inclk1") + other_clock_value = inclk1_ipd; + end + + // check if either input clk is bad + if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value) + begin + clk0_count = clk0_count + 1; + clk0_is_bad = 0; + clk1_count = 0; + if (clk0_count > 2) + begin + // no event on other clk for 2 cycles + clk1_is_bad = 1; + if (current_clock == "inclk1") + current_clk_is_bad = 1; + end + end + if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value) + begin + clk1_count = clk1_count + 1; + clk1_is_bad = 0; + clk0_count = 0; + if (clk1_count > 2) + begin + // no event on other clk for 2 cycles + clk0_is_bad = 1; + if (current_clock == "inclk0") + current_clk_is_bad = 1; + end + end + + // check if the bad clk is the primary clock, which is always clk0 + if (clk0_is_bad == 1'b1) + primary_clk_is_bad = 1; + else + primary_clk_is_bad = 0; + + // actual switching -- manual switch + if ((inclk0_ipd !== inclk0_last_value) && current_clock == "inclk0") + begin + if (external_switch == 1'b1) + begin + if (!got_curr_clk_falling_edge_after_clkswitch) + begin + if (inclk0_ipd === 1'b0) + got_curr_clk_falling_edge_after_clkswitch = 1; + inclk_n = inclk0_ipd; + end + end + else inclk_n = inclk0_ipd; + end + if ((inclk1_ipd !== inclk1_last_value) && current_clock == "inclk1") + begin + if (external_switch == 1'b1) + begin + if (!got_curr_clk_falling_edge_after_clkswitch) + begin + if (inclk1_ipd === 1'b0) + got_curr_clk_falling_edge_after_clkswitch = 1; + inclk_n = inclk1_ipd; + end + end + else inclk_n = inclk1_ipd; + end + + // actual switching -- automatic switch + if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && l_enable_switch_over_counter == "on" && primary_clk_is_bad) + switch_over_count = switch_over_count + 1; + + if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value)) + begin + if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && l_pll_type !== "fast" && l_pll_type !== "lvds" && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter)))) + begin + got_curr_clk_falling_edge_after_clkswitch = 0; + if (current_clock == "inclk0") + current_clock = "inclk1"; + else + current_clock = "inclk0"; + active_clock = ~active_clock; + switch_over_count = 0; + external_switch = 0; + current_clk_is_bad = 0; + end + end + + if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1)) + begin + if (primary_clk_is_bad) + clkloss_tmp = 1; + else + clkloss_tmp = 0; + end + else clkloss_tmp = clkswitch_ipd; + + inclk0_last_value = inclk0_ipd; + inclk1_last_value = inclk1_ipd; + other_clock_last_value = other_clock_value; + + end + + and (clkbad[0], clk0_is_bad, 1'b1); + and (clkbad[1], clk1_is_bad, 1'b1); + and (activeclock, active_clock, 1'b1); + and (clkloss, clkloss_tmp, 1'b1); + + MF_pll_reg ena_reg ( .clk(!inclk_n), + .ena(1'b1), + .d(ena_ipd), + .clrn(1'b1), + .prn(1'b1), + .q(pllena_reg)); + + and (test_mode_inclk, inclk_n, pllena_reg); + assign n_cntr_inclk = (pll_in_test_mode === 1'b1) ? test_mode_inclk : inclk_n; + assign ena_pll = (pll_in_test_mode === 1'b1) ? pllena_reg : ena_ipd; + + assign inclk_m = (m_test_source == 0) ? n_cntr_inclk : l_operation_mode == "external_feedback" ? (l_feedback_source == "clk0" ? clk0_tmp : + l_feedback_source == "clk1" ? clk1_tmp : + l_feedback_source == "clk2" ? clk2_tmp : + l_feedback_source == "clk3" ? clk3_tmp : + l_feedback_source == "clk4" ? clk4_tmp : + l_feedback_source == "clk5" ? clk5_tmp : 'b0) : + inclk_m_from_vco; + + + arm_m_cntr m1 (.clk(inclk_m), + .reset(areset_ipd || (!ena_pll) || stop_vco), + .cout(fbclk), + .initial_value(m_initial_val), + .modulus(m_val[0]), + .time_delay(m_delay)); + + arm_n_cntr n1 (.clk(n_cntr_inclk), + .reset(areset_ipd), + .cout(refclk), + .modulus(n_val[0])); + + + + always @(vco_out) + begin + // check which VCO TAP has event + for (x = 0; x <= 7; x = x + 1) + begin + if (vco_out[x] !== vco_out_last_value[x]) + begin + if (c_ph_val[0] == x) + begin + inclk_c0_from_vco <= vco_out[x]; + if (enable0_counter == "c0") + inclk_sclkout0_from_vco <= vco_out[x]; + if (enable1_counter == "c0") + inclk_sclkout1_from_vco <= vco_out[x]; + end + if (c_ph_val[1] == x) + begin + inclk_c1_from_vco <= vco_out[x]; + if (enable0_counter == "c1") + inclk_sclkout0_from_vco <= vco_out[x]; + if (enable1_counter == "c1") + inclk_sclkout1_from_vco <= vco_out[x]; + end + if (c_ph_val[2] == x) + inclk_c2_from_vco <= vco_out[x]; + if (c_ph_val[3] == x) + inclk_c3_from_vco <= vco_out[x]; + if (c_ph_val[4] == x) + inclk_c4_from_vco <= vco_out[x]; + if (c_ph_val[5] == x) + inclk_c5_from_vco <= vco_out[x]; + if (m_ph_val == x) + inclk_m_from_vco <= vco_out[x]; + end + end + if (scanwrite_enabled === 1'b1) + begin + for (x = 0; x <= 7; x = x + 1) + begin + if ((vco_out[x] === 1'b0) && (vco_out[x] !== vco_out_last_value[x])) + begin + for (y = 0; y <= 5; y = y + 1) + begin + if (c_ph_val[y] == x) + c_ph_val[y] <= c_ph_val_tmp[y]; + end + if (m_ph_val == x) + m_ph_val <= m_ph_val_tmp; + end + end + end + + // reset all counter phase tap values to POF programmed values + if (areset_ipd === 1'b1) + begin + m_ph_val <= m_ph_val_orig; + m_ph_val_tmp <= m_ph_val_orig; + for (i=0; i<= 5; i=i+1) + begin + c_ph_val[i] <= c_ph_val_orig[i]; + c_ph_val_tmp[i] <= c_ph_val_orig[i]; + end + end + + vco_out_last_value = vco_out; + end + + always @(inclk_sclkout0_from_vco) + begin + sclkout0_tmp <= inclk_sclkout0_from_vco; + end + always @(inclk_sclkout1_from_vco) + begin + sclkout1_tmp <= inclk_sclkout1_from_vco; + end + + assign inclk_c0 = (c0_test_source == 0) ? n_cntr_inclk : (c0_test_source == 1) ? refclk : inclk_c0_from_vco; + + arm_scale_cntr c0 (.clk(inclk_c0), + .reset(areset_ipd || (!ena_pll) || stop_vco), + .cout(c0_clk), + .high(c_high_val[0]), + .low(c_low_val[0]), + .initial_value(c_initial_val[0]), + .mode(c_mode_val[0]), + .ph_tap(c_ph_val[0])); + + always @(posedge c0_clk) + begin + if (scanwrite_enabled == 1'b1) + begin + c_high_val_hold[0] <= c_high_val_tmp[0]; + c_mode_val_hold[0] <= c_mode_val_tmp[0]; + c_high_val[0] <= c_high_val_hold[0]; + c_mode_val[0] <= c_mode_val_hold[0]; + c0_rising_edge_transfer_done = 1; + end + end + always @(negedge c0_clk) + begin + if (c0_rising_edge_transfer_done) + begin + c_low_val_hold[0] <= c_low_val_tmp[0]; + c_low_val[0] <= c_low_val_hold[0]; + end + end + + assign inclk_c1 = (c1_test_source == 0) ? n_cntr_inclk : (c1_test_source == 2) ? fbclk : (c1_use_casc_in == "on") ? c0_clk : inclk_c1_from_vco; + + arm_scale_cntr c1 (.clk(inclk_c1), + .reset(areset_ipd || (!ena_pll) || stop_vco), + .cout(c1_clk), + .high(c_high_val[1]), + .low(c_low_val[1]), + .initial_value(c_initial_val[1]), + .mode(c_mode_val[1]), + .ph_tap(c_ph_val[1])); + + always @(posedge c1_clk) + begin + if (scanwrite_enabled == 1'b1) + begin + c_high_val_hold[1] <= c_high_val_tmp[1]; + c_mode_val_hold[1] <= c_mode_val_tmp[1]; + c_high_val[1] <= c_high_val_hold[1]; + c_mode_val[1] <= c_mode_val_hold[1]; + c1_rising_edge_transfer_done = 1; + end + end + always @(negedge c1_clk) + begin + if (c1_rising_edge_transfer_done) + begin + c_low_val_hold[1] <= c_low_val_tmp[1]; + c_low_val[1] <= c_low_val_hold[1]; + end + end + + assign inclk_c2 = (c2_test_source == 0) ? n_cntr_inclk : (c2_use_casc_in == "on") ? c1_clk : inclk_c2_from_vco; + + arm_scale_cntr c2 (.clk(inclk_c2), + .reset(areset_ipd || (!ena_pll) || stop_vco), + .cout(c2_clk), + .high(c_high_val[2]), + .low(c_low_val[2]), + .initial_value(c_initial_val[2]), + .mode(c_mode_val[2]), + .ph_tap(c_ph_val[2])); + + always @(posedge c2_clk) + begin + if (scanwrite_enabled == 1'b1) + begin + c_high_val_hold[2] <= c_high_val_tmp[2]; + c_mode_val_hold[2] <= c_mode_val_tmp[2]; + c_high_val[2] <= c_high_val_hold[2]; + c_mode_val[2] <= c_mode_val_hold[2]; + c2_rising_edge_transfer_done = 1; + end + end + always @(negedge c2_clk) + begin + if (c2_rising_edge_transfer_done) + begin + c_low_val_hold[2] <= c_low_val_tmp[2]; + c_low_val[2] <= c_low_val_hold[2]; + end + end + + assign inclk_c3 = (c3_test_source == 0) ? n_cntr_inclk : (c3_use_casc_in == "on") ? c2_clk : inclk_c3_from_vco; + arm_scale_cntr c3 (.clk(inclk_c3), + .reset(areset_ipd || (!ena_pll) || stop_vco), + .cout(c3_clk), + .high(c_high_val[3]), + .low(c_low_val[3]), + .initial_value(c_initial_val[3]), + .mode(c_mode_val[3]), + .ph_tap(c_ph_val[3])); + + always @(posedge c3_clk) + begin + if (scanwrite_enabled == 1'b1) + begin + c_high_val_hold[3] <= c_high_val_tmp[3]; + c_mode_val_hold[3] <= c_mode_val_tmp[3]; + c_high_val[3] <= c_high_val_hold[3]; + c_mode_val[3] <= c_mode_val_hold[3]; + c3_rising_edge_transfer_done = 1; + end + end + always @(negedge c3_clk) + begin + if (c3_rising_edge_transfer_done) + begin + c_low_val_hold[3] <= c_low_val_tmp[3]; + c_low_val[3] <= c_low_val_hold[3]; + end + end + + assign inclk_c4 = (c4_test_source == 0) ? n_cntr_inclk : (c4_use_casc_in == "on") ? c3_clk : inclk_c4_from_vco; + arm_scale_cntr c4 (.clk(inclk_c4), + .reset(areset_ipd || (!ena_pll) || stop_vco), + .cout(c4_clk), + .high(c_high_val[4]), + .low(c_low_val[4]), + .initial_value(c_initial_val[4]), + .mode(c_mode_val[4]), + .ph_tap(c_ph_val[4])); + + always @(posedge c4_clk) + begin + if (scanwrite_enabled == 1'b1) + begin + c_high_val_hold[4] <= c_high_val_tmp[4]; + c_mode_val_hold[4] <= c_mode_val_tmp[4]; + c_high_val[4] <= c_high_val_hold[4]; + c_mode_val[4] <= c_mode_val_hold[4]; + c4_rising_edge_transfer_done = 1; + end + end + always @(negedge c4_clk) + begin + if (c4_rising_edge_transfer_done) + begin + c_low_val_hold[4] <= c_low_val_tmp[4]; + c_low_val[4] <= c_low_val_hold[4]; + end + end + + assign inclk_c5 = (c5_test_source == 0) ? n_cntr_inclk : (c5_use_casc_in == "on") ? c4_clk : inclk_c5_from_vco; + arm_scale_cntr c5 (.clk(inclk_c5), + .reset(areset_ipd || (!ena_pll) || stop_vco), + .cout(c5_clk), + .high(c_high_val[5]), + .low(c_low_val[5]), + .initial_value(c_initial_val[5]), + .mode(c_mode_val[5]), + .ph_tap(c_ph_val[5])); + + always @(posedge c5_clk) + begin + if (scanwrite_enabled == 1'b1) + begin + c_high_val_hold[5] <= c_high_val_tmp[5]; + c_mode_val_hold[5] <= c_mode_val_tmp[5]; + c_high_val[5] <= c_high_val_hold[5]; + c_mode_val[5] <= c_mode_val_hold[5]; + c5_rising_edge_transfer_done = 1; + end + end + always @(negedge c5_clk) + begin + if (c5_rising_edge_transfer_done) + begin + c_low_val_hold[5] <= c_low_val_tmp[5]; + c_low_val[5] <= c_low_val_hold[5]; + end + end + + always @(vco_out[c_ph_val[0]] or posedge areset_ipd or negedge ena_pll or stop_vco) + begin + if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1) + begin + c0_count = 2; + c0_initial_count = 1; + c0_got_first_rising_edge = 0; + + end + else begin + if (c0_got_first_rising_edge == 1'b0) + begin + if (vco_out[c_ph_val[0]] == 1'b1 && vco_out[c_ph_val[0]] != vco_c0_last_value) + begin + if (c0_initial_count == c_initial_val[0]) + c0_got_first_rising_edge = 1; + else + c0_initial_count = c0_initial_count + 1; + end + end + else if (vco_out[c_ph_val[0]] != vco_c0_last_value) + begin + c0_count = c0_count + 1; + if (c0_count == (c_high_val[0] + c_low_val[0]) * 2) + c0_count = 1; + end + if (vco_out[c_ph_val[0]] == 1'b0 && vco_out[c_ph_val[0]] != vco_c0_last_value) + begin + if (c0_count == 1) + begin + c0_tmp = 1; + c0_got_first_rising_edge = 0; + end + else c0_tmp = 0; + end + end + vco_c0_last_value = vco_out[c_ph_val[0]]; + end + + always @(vco_out[c_ph_val[1]] or posedge areset_ipd or negedge ena_pll or stop_vco) + begin + if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1) + begin + c1_count = 2; + c1_initial_count = 1; + c1_got_first_rising_edge = 0; + end + else begin + if (c1_got_first_rising_edge == 1'b0) + begin + if (vco_out[c_ph_val[1]] == 1'b1 && vco_out[c_ph_val[1]] != vco_c1_last_value) + begin + if (c1_initial_count == c_initial_val[1]) + c1_got_first_rising_edge = 1; + else + c1_initial_count = c1_initial_count + 1; + end + end + else if (vco_out[c_ph_val[1]] != vco_c1_last_value) + begin + c1_count = c1_count + 1; + if (c1_count == (c_high_val[1] + c_low_val[1]) * 2) + c1_count = 1; + end + if (vco_out[c_ph_val[1]] == 1'b0 && vco_out[c_ph_val[1]] != vco_c1_last_value) + begin + if (c1_count == 1) + begin + c1_tmp = 1; + c1_got_first_rising_edge = 0; + end + else c1_tmp = 0; + end + end + vco_c1_last_value = vco_out[c_ph_val[1]]; + end + + assign enable0_tmp = (l_enable0_counter == "c0") ? c0_tmp : c1_tmp; + assign enable1_tmp = (l_enable1_counter == "c0") ? c0_tmp : c1_tmp; + + always @ (inclk_n or ena_pll or areset_ipd) + begin + if (areset_ipd == 1'b1 || ena_pll == 1'b0) + begin + gate_count = 0; + gate_out = 0; + end + else if (inclk_n == 'b1 && inclk_last_value != inclk_n) + begin + gate_count = gate_count + 1; + if (gate_count == gate_lock_counter) + gate_out = 1; + end + inclk_last_value = inclk_n; + end + + assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp; + + always @(posedge scanread_ipd) + begin + scanread_active_edge = $time; + end + + always @ (scanclk_ipd) + begin + if (scanclk_ipd === 1'b0 && scanclk_last_value === 1'b1) + begin + // enable scanwrite on falling edge + scanwrite_enabled <= scanwrite_reg; + end + if (scanread_reg === 1'b1) + gated_scanclk <= scanclk_ipd && scanread_reg; + else + gated_scanclk <= 1'b1; + if (scanclk_ipd === 1'b1 && scanclk_last_value === 1'b0) + begin + // register scanread and scanwrite + scanread_reg <= scanread_ipd; + scanwrite_reg <= scanwrite_ipd; + + if (got_first_scanclk) + scanclk_period = $time - scanclk_last_rising_edge; + else begin + got_first_scanclk = 1; + end + // reset got_first_scanclk on falling edge of scanread_reg + if (scanread_ipd == 1'b0 && scanread_reg == 1'b1) + begin + got_first_scanclk = 0; + got_first_gated_scanclk = 0; + end + + scanclk_last_rising_edge = $time; + end + scanclk_last_value = scanclk_ipd; + end + + always @(posedge gated_scanclk) + begin + if ($time > 0) + begin + if (!got_first_gated_scanclk) + begin + got_first_gated_scanclk = 1; +// if ($time - scanread_active_edge < scanclk_period) +// begin +// scanread_setup_violation = 1; +// $display("Warning : SCANREAD must go high at least one cycle before SCANDATA is read in."); +// $display ("Time: %0t Instance: %m", $time); +// end + end + for (j = scan_chain_length-1; j >= 1; j = j - 1) + begin + scan_data[j] = scan_data[j - 1]; + end + scan_data[0] <= scandata_ipd; + end + end + + assign scandataout_tmp = (l_pll_type == "fast" || l_pll_type == "lvds") ? scan_data[FAST_SCAN_CHAIN-1] : scan_data[GPP_SCAN_CHAIN-1]; + + always @(posedge scandone_tmp) + begin + if (reconfig_err == 1'b0) + begin + $display("NOTE : PLL Reprogramming completed with the following values (Values in parantheses are original values) : "); + $display ("Time: %0t Instance: %m", $time); + + $display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]); + $display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]); + $display(" M ph_tap = %0d (%0d) ", m_ph_val, m_ph_val_old); + if (ss > 0) + begin + $display(" M2 modulus = %0d (%0d) ", m_val[1], m_val_old[1]); + $display(" N2 modulus = %0d (%0d) ", n_val[1], n_val_old[1]); + end + + for (i = 0; i < num_output_cntrs; i=i+1) + begin + $display(" C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s), C%0d phase tap = %0d (%0d)", i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i], i, c_ph_val[i], c_ph_val_old[i]); + end + + // display Charge pump and loop filter values + $display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old); + $display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old); + $display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old); + end + else begin + $display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above."); + $display ("Time: %0t Instance: %m", $time); + end + end + + always @(scanwrite_enabled) + begin + if (scanwrite_enabled === 1'b0 && scanwrite_last_value === 1'b1) + begin + // falling edge : deassert scandone + scandone_tmp <= #(1.5*scanclk_period) 1'b0; + // reset counter transfer flags + c0_rising_edge_transfer_done = 0; + c1_rising_edge_transfer_done = 0; + c2_rising_edge_transfer_done = 0; + c3_rising_edge_transfer_done = 0; + c4_rising_edge_transfer_done = 0; + c5_rising_edge_transfer_done = 0; + end + if (scanwrite_enabled === 1'b1 && scanwrite_last_value !== scanwrite_enabled) + begin + + $display ("NOTE : PLL Reprogramming initiated ...."); + $display ("Time: %0t Instance: %m", $time); + + error = 0; + reconfig_err = 0; + scanread_setup_violation = 0; + + // make temp. copy of scan_data for processing + tmp_scan_data = scan_data; + + // save old values + cp_curr_old = cp_curr_val; + lfc_old = lfc_val; + lfr_old = lfr_val; + + // CP + // Bits 0-3 : all values are legal + cp_curr_val = charge_pump_curr_arr[scan_data[3:0]]; + + // LF Resistance : bits 4-9 + // values from 010000 - 010111, 100000 - 100111, + // 110000- 110111 are illegal + if (((tmp_scan_data[9:4] >= 6'b010000) && (tmp_scan_data[9:4] <= 6'b010111)) || + ((tmp_scan_data[9:4] >= 6'b100000) && (tmp_scan_data[9:4] <= 6'b100111)) || + ((tmp_scan_data[9:4] >= 6'b110000) && (tmp_scan_data[9:4] <= 6'b110111))) + begin + $display ("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work."); + reconfig_err = 1; + end + else begin + i = scan_data[9:4]; + if (i >= 56 ) + i = i - 24; + else if ((i >= 40) && (i <= 47)) + i = i - 16; + else if ((i >= 24) && (i <= 31)) + i = i - 8; + lfr_val = loop_filter_r_arr[i]; + end + + // LF Capacitance : bits 10,11 : all values are legal + if ((l_pll_type == "fast") || (l_pll_type == "lvds")) + lfc_val = fpll_loop_filter_c_arr[scan_data[11:10]]; + else + lfc_val = loop_filter_c_arr[scan_data[11:10]]; + + // save old values for display info. + for (i=0; i<=1; i=i+1) + begin + m_val_old[i] = m_val[i]; + n_val_old[i] = n_val[i]; + m_mode_val_old[i] = m_mode_val[i]; + n_mode_val_old[i] = n_mode_val[i]; + end + m_ph_val_old = m_ph_val; + for (i=0; i<=5; i=i+1) + begin + c_high_val_old[i] = c_high_val[i]; + c_low_val_old[i] = c_low_val[i]; + c_ph_val_old[i] = c_ph_val[i]; + c_mode_val_old[i] = c_mode_val[i]; + end + + // first the M counter phase : bit order same for fast and GPP + if (scan_data[12] == 1'b0) + begin + // do nothing + end + else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b1) + begin + m_ph_val_tmp = m_ph_val_tmp + 1; + if (m_ph_val_tmp > 7) + m_ph_val_tmp = 0; + end + else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b0) + begin + m_ph_val_tmp = m_ph_val_tmp - 1; + if (m_ph_val_tmp < 0) + m_ph_val_tmp = 7; + end + else begin + $display ("Warning : Illegal bit settings for M counter phase tap. Reconfiguration may not work."); + reconfig_err = 1; + end + + // read the fast PLL bits. + if (l_pll_type == "fast" || l_pll_type == "lvds") + begin + // C3-C0 phase bits + for (i = 3; i >= 0; i=i-1) + begin + if (tmp_scan_data[14] == 1'b0) + begin + // do nothing + end + else if (tmp_scan_data[14] === 1'b1) + begin + if (tmp_scan_data[15] === 1'b1) + begin + c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1; + if (c_ph_val_tmp[i] > 7) + c_ph_val_tmp[i] = 0; + end + else if (tmp_scan_data[15] === 1'b0) + begin + c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1; + if (c_ph_val_tmp[i] < 0) + c_ph_val_tmp[i] = 7; + end + end + tmp_scan_data = tmp_scan_data >> 2; + end + // C0-C3 counter moduli + tmp_scan_data = scan_data; + for (i = 0; i < 4; i=i+1) + begin + if (tmp_scan_data[26] == 1'b1) + begin + c_mode_val_tmp[i] = "bypass"; + if (tmp_scan_data[31] === 1'b1) + begin + c_mode_val_tmp[i] = " off"; + $display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i); + end + end + else if (tmp_scan_data[31] == 1'b1) + c_mode_val_tmp[i] = " odd"; + else + c_mode_val_tmp[i] = " even"; + if (tmp_scan_data[25:22] === 4'b0000) + c_high_val_tmp[i] = 5'b10000; + else + c_high_val_tmp[i] = tmp_scan_data[25:22]; + if (tmp_scan_data[30:27] === 4'b0000) + c_low_val_tmp[i] = 5'b10000; + else + c_low_val_tmp[i] = tmp_scan_data[30:27]; + + tmp_scan_data = tmp_scan_data >> 10; + end + // M + error = 0; + // some temporary storage + if (scan_data[65:62] == 4'b0000) + m_hi = 5'b10000; + else + m_hi = scan_data[65:62]; + + if (scan_data[70:67] == 4'b0000) + m_lo = 5'b10000; + else + m_lo = scan_data[70:67]; + + m_val_tmp[0] = m_hi + m_lo; + if (scan_data[66] === 1'b1) + begin + if (scan_data[71] === 1'b1) + begin + // this will turn off the M counter : error + reconfig_err = 1; + error = 1; + $display ("The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work."); + end + else begin + // M counter is being bypassed + if (m_mode_val[0] !== "bypass") + begin + // Mode is switched : give warning + d_msg = display_msg(" M", 4); + end + m_val_tmp[0] = 32'b1; + m_mode_val[0] = "bypass"; + end + end + else begin + if (m_mode_val[0] === "bypass") + begin + // Mode is switched : give warning + d_msg = display_msg(" M", 1); + end + m_mode_val[0] = ""; + if (scan_data[71] === 1'b1) + begin + // odd : check for duty cycle, if not 50% -- error + if (m_hi - m_lo !== 1) + begin + reconfig_err = 1; + $display ("Warning : The M counter of the StratixII Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"); + end + end + else begin // even mode + if (m_hi !== m_lo) + begin + reconfig_err = 1; + $display ("Warning : The M counter of the StratixII Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"); + end + end + end + + // N + error = 0; + n_val[0] = scan_data[73:72]; + if (scan_data[74] !== 1'b1) + begin + if (scan_data[73:72] == 2'b01) + begin + reconfig_err = 1; + error = 1; + // Cntr value is illegal : give warning + d_msg = display_msg(" N", 2); + end + else if (scan_data[73:72] == 2'b00) + n_val[0] = 3'b100; + if (error == 1'b0) + begin + if (n_mode_val[0] === "bypass") + begin + // Mode is switched : give warning + d_msg = display_msg(" N", 1); + end + n_mode_val[0] = ""; + end + end + else if (scan_data[74] == 1'b1) // bypass + begin + if (scan_data[72] !== 1'b0) + begin + reconfig_err = 1; + error = 1; + // Cntr value is illegal : give warning + d_msg = display_msg(" N", 3); + end + else begin + if (n_mode_val[0] != "bypass") + begin + // Mode is switched : give warning + d_msg = display_msg(" N", 4); + end + n_val[0] = 2'b01; + n_mode_val[0] = "bypass"; + end + end + end + else begin // pll type is auto or enhanced + for (i = 0; i < 6; i=i+1) + begin + if (tmp_scan_data[124] == 1'b1) + begin + c_mode_val_tmp[i] = "bypass"; + if (tmp_scan_data[133] === 1'b1) + begin + c_mode_val_tmp[i] = " off"; + $display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i); + end + end + else if (tmp_scan_data[133] == 1'b1) + c_mode_val_tmp[i] = " odd"; + else + c_mode_val_tmp[i] = " even"; + if (tmp_scan_data[123:116] === 8'b00000000) + c_high_val_tmp[i] = 9'b100000000; + else + c_high_val_tmp[i] = tmp_scan_data[123:116]; + if (tmp_scan_data[132:125] === 8'b00000000) + c_low_val_tmp[i] = 9'b100000000; + else + c_low_val_tmp[i] = tmp_scan_data[132:125]; + + tmp_scan_data = tmp_scan_data << 18; + end + + // the phase_taps + tmp_scan_data = scan_data; + for (i = 0; i < 6; i=i+1) + begin + if (tmp_scan_data[14] == 1'b0) + begin + // do nothing + end + else if (tmp_scan_data[14] === 1'b1) + begin + if (tmp_scan_data[15] === 1'b1) + begin + c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1; + if (c_ph_val_tmp[i] > 7) + c_ph_val_tmp[i] = 0; + end + else if (tmp_scan_data[15] === 1'b0) + begin + c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1; + if (c_ph_val_tmp[i] < 0) + c_ph_val_tmp[i] = 7; + end + end + tmp_scan_data = tmp_scan_data >> 2; + end + ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index]; + ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index]; + ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index]; + ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index]; + + // cntrs M/M2 + tmp_scan_data = scan_data; + for (i=0; i<2; i=i+1) + begin + if (i == 0 || (i == 1 && ss > 0)) + begin + error = 0; + m_val_tmp[i] = tmp_scan_data[142:134]; + if (tmp_scan_data[143] !== 1'b1) + begin + if (tmp_scan_data[142:134] == 9'b000000001) + begin + reconfig_err = 1; + error = 1; + // Cntr value is illegal : give warning + if (i == 0) + d_msg = display_msg(" M", 2); + else + d_msg = display_msg("M2", 2); + end + else if (tmp_scan_data[142:134] == 9'b000000000) + m_val_tmp[i] = 10'b1000000000; + if (error == 1'b0) + begin + if (m_mode_val[i] === "bypass") + begin + // Mode is switched : give warning + if (i == 0) + d_msg = display_msg(" M", 1); + else + d_msg = display_msg("M2", 1); + end + m_mode_val[i] = ""; + end + end + else if (tmp_scan_data[143] == 1'b1) + begin + if (tmp_scan_data[134] !== 1'b0) + begin + reconfig_err = 1; + error = 1; + // Cntr value is illegal : give warning + if (i == 0) + d_msg = display_msg(" M", 3); + else + d_msg = display_msg("M2", 3); + end + else begin + if (m_mode_val[i] !== "bypass") + begin + // Mode is switched: give warning + if (i == 0) + d_msg = display_msg(" M", 4); + else + d_msg = display_msg("M2", 4); + end + m_val_tmp[i] = 10'b0000000001; + m_mode_val[i] = "bypass"; + end + end + end + tmp_scan_data = tmp_scan_data >> 10; + end + if (ss > 0) + begin + if (m_mode_val[0] != m_mode_val[1]) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Incompatible modes for M/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work."); + end + end + + // cntrs N/N2 + tmp_scan_data = scan_data; + for (i=0; i<2; i=i+1) + begin + if (i == 0 || (i == 1 && ss > 0)) + begin + error = 0; + n_val[i] = tmp_scan_data[162:154]; + if (tmp_scan_data[163] !== 1'b1) + begin + if (tmp_scan_data[162:154] == 9'b000000001) + begin + reconfig_err = 1; + error = 1; + // Cntr value is illegal : give warning + if (i == 0) + d_msg = display_msg(" N", 2); + else + d_msg = display_msg("N2", 2); + end + else if (tmp_scan_data[162:154] == 9'b000000000) + n_val[i] = 10'b1000000000; + if (error == 1'b0) + begin + if (n_mode_val[i] === "bypass") + begin + // Mode is switched : give warning + if (i == 0) + d_msg = display_msg(" N", 1); + else + d_msg = display_msg("N2", 1); + end + n_mode_val[i] = ""; + end + end + else if (tmp_scan_data[163] == 1'b1) // bypass + begin + if (tmp_scan_data[154] !== 1'b0) + begin + reconfig_err = 1; + error = 1; + // Cntr value is illegal : give warning + if (i == 0) + d_msg = display_msg(" N", 3); + else + d_msg = display_msg("N2", 3); + end + else begin + if (n_mode_val[i] != "bypass") + begin + // Mode is switched : give warning + if (i == 0) + d_msg = display_msg(" N", 4); + else + d_msg = display_msg("N2", 4); + end + n_val[i] = 10'b0000000001; + n_mode_val[i] = "bypass"; + end + end + end + tmp_scan_data = tmp_scan_data >> 10; + end + if (ss > 0) + begin + if (n_mode_val[0] != n_mode_val[1]) + begin + reconfig_err = 1; + error = 1; + $display ("Warning : Incompatible modes for N/N2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work."); + end + end + end + + slowest_clk_old = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0], + c_high_val[1]+c_low_val[1], c_mode_val[1], + c_high_val[2]+c_low_val[2], c_mode_val[2], + c_high_val[3]+c_low_val[3], c_mode_val[3], + c_high_val[4]+c_low_val[4], c_mode_val[4], + c_high_val[5]+c_low_val[5], c_mode_val[5], + refclk_period, m_val[0]); + + slowest_clk_new = slowest_clk ( c_high_val_tmp[0]+c_low_val[0], c_mode_val_tmp[0], + c_high_val_tmp[1]+c_low_val[1], c_mode_val_tmp[1], + c_high_val_tmp[2]+c_low_val[2], c_mode_val_tmp[2], + c_high_val_tmp[3]+c_low_val[3], c_mode_val_tmp[3], + c_high_val_tmp[4]+c_low_val[4], c_mode_val_tmp[4], + c_high_val_tmp[5]+c_low_val[5], c_mode_val_tmp[5], + refclk_period, m_val[0]); + + quiet_time = (slowest_clk_new > slowest_clk_old) ? slowest_clk_new : slowest_clk_old; + + // get quiet time in terms of scanclk cycles + my_rem = quiet_time % scanclk_period; + scanclk_cycles = quiet_time/scanclk_period; + if (my_rem != 0) + scanclk_cycles = scanclk_cycles + 1; + + scandone_tmp <= #((scanclk_cycles+0.5) * scanclk_period) 1'b1; + end + + scanwrite_last_value = scanwrite_enabled; + end + + always @(schedule_vco or areset_ipd or ena_pll) + begin + sched_time = 0; + + for (i = 0; i <= 7; i=i+1) + last_phase_shift[i] = phase_shift[i]; + + cycle_to_adjust = 0; + l_index = 1; + m_times_vco_period = new_m_times_vco_period; + + // give appropriate messages + // if areset was asserted + if (areset_ipd === 1'b1 && areset_ipd_last_value !== areset_ipd) + begin + $display (" Note : PLL was reset"); + $display ("Time: %0t Instance: %m", $time); + // reset lock parameters + locked_tmp = 0; + pll_is_locked = 0; + pll_about_to_lock = 0; + cycles_to_lock = 0; + cycles_to_unlock = 0; + end + + // if ena was deasserted + if (ena_pll == 1'b0 && ena_ipd_last_value !== ena_pll) + begin + $display (" Note : PLL was disabled"); + $display ("Time: %0t Instance: %m", $time); + end + + // illegal value on areset_ipd + if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1)) + begin + $display("Warning : Illegal value 'X' detected on ARESET input"); + $display ("Time: %0t Instance: %m", $time); + end + + if ((schedule_vco !== schedule_vco_last_value) && (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1)) + begin + + if (areset_ipd === 1'b1) + pll_is_in_reset = 1; + + // drop VCO taps to 0 + for (i = 0; i <= 7; i=i+1) + begin + for (j = 0; j <= last_phase_shift[i] + 1; j=j+1) + vco_out[i] <= #(j) 1'b0; + phase_shift[i] = 0; + last_phase_shift[i] = 0; + end + + // reset lock parameters + locked_tmp = 0; + pll_is_locked = 0; + pll_about_to_lock = 0; + cycles_to_lock = 0; + cycles_to_unlock = 0; + + got_first_refclk = 0; + got_second_refclk = 0; + refclk_time = 0; + got_first_fbclk = 0; + fbclk_time = 0; + first_fbclk_time = 0; + fbclk_period = 0; + + first_schedule = 1; + vco_val = 0; + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 0; + + // reset all counter phase tap values to POF programmed values + m_ph_val = m_ph_val_orig; + for (i=0; i<= 5; i=i+1) + c_ph_val[i] = c_ph_val_orig[i]; + + end else if (ena_pll === 1'b1 && areset_ipd === 1'b0 && stop_vco === 1'b0) + begin + // else note areset deassert time + // note it as refclk_time to prevent false triggering + // of stop_vco after areset + if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1 && pll_is_in_reset === 1'b1) + begin + refclk_time = $time; + pll_is_in_reset = 0; + end + + // calculate loop_xplier : this will be different from m_val in ext. fbk mode + loop_xplier = m_val[0]; + loop_initial = i_m_initial - 1; + loop_ph = m_ph_val; + + if (l_operation_mode == "external_feedback") + begin + if (ext_fbk_cntr_mode == "bypass") + ext_fbk_cntr_modulus = 1; + else + ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low; + + loop_xplier = m_val[0] * (ext_fbk_cntr_modulus); + loop_ph = ext_fbk_cntr_ph; + loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * ext_fbk_cntr_modulus); + end + + // convert initial value to delay + initial_delay = (loop_initial * m_times_vco_period)/loop_xplier; + + // convert loop ph_tap to delay + rem = m_times_vco_period % loop_xplier; + vco_per = m_times_vco_period/loop_xplier; + if (rem != 0) + vco_per = vco_per + 1; + fbk_phase = (loop_ph * vco_per)/8; + + if (l_operation_mode == "external_feedback") + begin + pull_back_M = (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier); + + while (pull_back_M > refclk_period) + pull_back_M = pull_back_M - refclk_period; + end + else begin + pull_back_M = initial_delay + fbk_phase; + end + + total_pull_back = pull_back_M; + if (l_simulation_type == "timing") + total_pull_back = total_pull_back + pll_compensation_delay; + + while (total_pull_back > refclk_period) + total_pull_back = total_pull_back - refclk_period; + + if (total_pull_back > 0) + offset = refclk_period - total_pull_back; + else + offset = 0; + + if (l_operation_mode == "external_feedback") + begin + fbk_delay = pull_back_M; + if (l_simulation_type == "timing") + fbk_delay = fbk_delay + pll_compensation_delay; + end + else begin + fbk_delay = total_pull_back - fbk_phase; + if (fbk_delay < 0) + begin + offset = offset - fbk_phase; + fbk_delay = total_pull_back; + end + end + + // assign m_delay + m_delay = fbk_delay; + + for (i = 1; i <= loop_xplier; i=i+1) + begin + // adjust cycles + tmp_vco_per = m_times_vco_period/loop_xplier; + if (rem != 0 && l_index <= rem) + begin + tmp_rem = (loop_xplier * l_index) % rem; + cycle_to_adjust = (loop_xplier * l_index) / rem; + if (tmp_rem != 0) + cycle_to_adjust = cycle_to_adjust + 1; + end + if (cycle_to_adjust == i) + begin + tmp_vco_per = tmp_vco_per + 1; + l_index = l_index + 1; + end + + // calculate high and low periods + high_time = tmp_vco_per/2; + if (tmp_vco_per % 2 != 0) + high_time = high_time + 1; + low_time = tmp_vco_per - high_time; + + // schedule the rising and falling egdes + for (j=0; j<=1; j=j+1) + begin + vco_val = ~vco_val; + if (vco_val == 1'b0) + sched_time = sched_time + high_time; + else + sched_time = sched_time + low_time; + + // schedule taps with appropriate phase shifts + for (k = 0; k <= 7; k=k+1) + begin + phase_shift[k] = (k*tmp_vco_per)/8; + if (first_schedule) + vco_out[k] <= #(sched_time + phase_shift[k]) vco_val; + else + vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val; + end + end + end + if (first_schedule) + begin + vco_val = ~vco_val; + if (vco_val == 1'b0) + sched_time = sched_time + high_time; + else + sched_time = sched_time + low_time; + for (k = 0; k <= 7; k=k+1) + begin + phase_shift[k] = (k*tmp_vco_per)/8; + vco_out[k] <= #(sched_time+phase_shift[k]) vco_val; + end + first_schedule = 0; + end + + schedule_vco <= #(sched_time) ~schedule_vco; + if (vco_period_was_phase_adjusted) + begin + m_times_vco_period = refclk_period; + new_m_times_vco_period = refclk_period; + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 1; + + tmp_vco_per = m_times_vco_period/loop_xplier; + for (k = 0; k <= 7; k=k+1) + phase_shift[k] = (k*tmp_vco_per)/8; + end + end + + areset_ipd_last_value = areset_ipd; + ena_ipd_last_value = ena_pll; + schedule_vco_last_value = schedule_vco; + + end + + always @(pfdena_ipd) + begin + if (pfdena_ipd === 1'b0) + begin + if (pll_is_locked) + locked_tmp = 1'bx; + pll_is_locked = 0; + cycles_to_lock = 0; + $display (" Note : PFDENA was deasserted"); + $display ("Time: %0t Instance: %m", $time); + end + else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0) + begin + // PFD was disabled, now enabled again + got_first_refclk = 0; + got_second_refclk = 0; + refclk_time = $time; + end + pfdena_ipd_last_value = pfdena_ipd; + end + + always @(negedge refclk or negedge fbclk) + begin + refclk_last_value = refclk; + fbclk_last_value = fbclk; + end + + always @(posedge refclk or posedge fbclk) + begin + if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0) + begin + if (! got_first_refclk) + begin + got_first_refclk = 1; + end else + begin + got_second_refclk = 1; + refclk_period = $time - refclk_time; + + // check if incoming freq. will cause VCO range to be + // exceeded + if ((vco_max != 0 && vco_min != 0) && (pfdena_ipd === 1'b1) && + ((refclk_period/loop_xplier > vco_max) || + (refclk_period/loop_xplier < vco_min)) ) + begin + if (pll_is_locked == 1'b1) + begin + $display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock"); + $display ("Time: %0t Instance: %m", $time); + if (inclk_out_of_range === 1'b1) + begin + // unlock + pll_is_locked = 0; + locked_tmp = 0; + pll_about_to_lock = 0; + cycles_to_lock = 0; + $display ("Note : PLL lost lock"); + $display ("Time: %0t Instance: %m", $time); + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 0; + end + end + else begin + if (no_warn == 1'b0) + begin + $display ("Warning : Input clock freq. is not within VCO range. PLL may not lock"); + $display ("Time: %0t Instance: %m", $time); + no_warn = 1'b1; + end + end + inclk_out_of_range = 1; + end + else begin + inclk_out_of_range = 0; + end + + end + if (stop_vco == 1'b1) + begin + stop_vco = 0; + schedule_vco = ~schedule_vco; + end + refclk_time = $time; + end + + if (fbclk == 1'b1 && fbclk_last_value !== fbclk) + begin + if (scanwrite_enabled === 1'b1) + begin + m_val[0] <= m_val_tmp[0]; + m_val[1] <= m_val_tmp[1]; + end + if (!got_first_fbclk) + begin + got_first_fbclk = 1; + first_fbclk_time = $time; + end + else + fbclk_period = $time - fbclk_time; + + // need refclk_period here, so initialized to proper value above + if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked === 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) ) + begin + stop_vco = 1; + // reset + got_first_refclk = 0; + got_first_fbclk = 0; + got_second_refclk = 0; + if (pll_is_locked == 1'b1) + begin + pll_is_locked = 0; + locked_tmp = 0; + $display ("Note : PLL lost lock due to loss of input clock"); + $display ("Time: %0t Instance: %m", $time); + end + pll_about_to_lock = 0; + cycles_to_lock = 0; + cycles_to_unlock = 0; + first_schedule = 1; + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 0; + end + fbclk_time = $time; + end + + if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range)) + begin + // now we know actual incoming period + if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5)) + begin + // considered in phase + if (cycles_to_lock == valid_lock_multiplier - 1) + pll_about_to_lock <= 1; + if (cycles_to_lock == valid_lock_multiplier) + begin + if (pll_is_locked === 1'b0) + begin + $display (" Note : PLL locked to incoming clock"); + $display ("Time: %0t Instance: %m", $time); + end + pll_is_locked = 1; + locked_tmp = 1; + cycles_to_unlock = 0; + end + // increment lock counter only if the second part of the above + // time check is not true + if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5)) + begin + cycles_to_lock = cycles_to_lock + 1; + end + + // adjust m_times_vco_period + new_m_times_vco_period = refclk_period; + + end else + begin + // if locked, begin unlock + if (pll_is_locked) + begin + cycles_to_unlock = cycles_to_unlock + 1; + if (cycles_to_unlock == invalid_lock_multiplier) + begin + pll_is_locked = 0; + locked_tmp = 0; + pll_about_to_lock = 0; + cycles_to_lock = 0; + $display ("Note : PLL lost lock"); + $display ("Time: %0t Instance: %m", $time); + vco_period_was_phase_adjusted = 0; + phase_adjust_was_scheduled = 0; + end + end + if (abs(refclk_period - fbclk_period) <= 2) + begin + // frequency is still good + if ($time == fbclk_time && (!phase_adjust_was_scheduled)) + begin + if (abs(fbclk_time - refclk_time) > refclk_period/2) + begin + new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time)); + vco_period_was_phase_adjusted = 1; + end else + begin + new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time); + vco_period_was_phase_adjusted = 1; + end + end + end else + begin + new_m_times_vco_period = refclk_period; + phase_adjust_was_scheduled = 0; + end + end + end + + if (reconfig_err == 1'b1) + begin + locked_tmp = 0; + end + + refclk_last_value = refclk; + fbclk_last_value = fbclk; + end + + assign clk0_tmp = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : i_clk0_counter == "c5" ? c5_clk : 'b0; + + assign clk0 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk0_tmp : 'bx; + + + assign clk1_tmp = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : i_clk1_counter == "c5" ? c5_clk : 'b0; + + assign clk1 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk1_tmp : 'bx; + + + assign clk2_tmp = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : i_clk2_counter == "c5" ? c5_clk : 'b0; + + assign clk2 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk2_tmp : 'bx; + + + assign clk3_tmp = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : i_clk3_counter == "c5" ? c5_clk : 'b0; + + assign clk3 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk3_tmp : 'bx; + + + assign clk4_tmp = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : i_clk4_counter == "c5" ? c5_clk : 'b0; + + assign clk4 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk4_tmp : 'bx; + + + assign clk5_tmp = i_clk5_counter == "c0" ? c0_clk : i_clk5_counter == "c1" ? c1_clk : i_clk5_counter == "c2" ? c2_clk : i_clk5_counter == "c3" ? c3_clk : i_clk5_counter == "c4" ? c4_clk : i_clk5_counter == "c5" ? c5_clk : 'b0; + + assign clk5 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk5_tmp : 'bx; + + assign sclkout0 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? sclkout0_tmp : 1'bx; + + assign sclkout1 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? sclkout1_tmp : 1'bx; + + assign enable_0 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || pll_about_to_lock == 1'b1 ? enable0_tmp : 'bx; + assign enable_1 = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode == 1'b1) || pll_about_to_lock == 1'b1 ? enable1_tmp : 'bx; + + + // ACCELERATE OUTPUTS + and (clk[0], 1'b1, clk0); + and (clk[1], 1'b1, clk1); + and (clk[2], 1'b1, clk2); + and (clk[3], 1'b1, clk3); + and (clk[4], 1'b1, clk4); + and (clk[5], 1'b1, clk5); + + and (sclkout[0], 1'b1, sclkout0); + and (sclkout[1], 1'b1, sclkout1); + + and (enable0, 1'b1, enable_0); + and (enable1, 1'b1, enable_1); + + and (scandataout, 1'b1, scandataout_tmp); + and (scandone, 1'b1, scandone_tmp); + +endmodule // MF_stratixii_pll + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : ALTPLL +// +// Description : Phase-Locked Loop (PLL) behavioral model. Model supports basic +// PLL features such as clock division and multiplication, +// programmable duty cycle and phase shifts, various feedback modes +// and clock delays. Also supports real-time reconfiguration of +// PLL "parameters" and clock switchover between the 2 input +// reference clocks. Up to 10 clock outputs may be used. +// +// Limitations : Applicable to Stratix, Stratix-GX, Stratix II and Cyclone II device families only +// There is no support in the model for spread-spectrum feature +// +// Expected results : Up to 10 output clocks, each defined by its own set of +// parameters. Locked output (active high) indicates when the +// PLL locks. clkbad, clkloss and activeclock are used for +// clock switchover to inidicate which input clock has gone +// bad, when the clock switchover initiates and which input +// clock is being used as the reference, respectively. +// scandataout is the data output of the serial scan chain. + +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1ps + +// MODULE DECLARATION +module altpll ( + inclk, // input reference clock - up to 2 can be used + fbin, // external feedback input port + pllena, // PLL enable signal + clkswitch, // switch between inclk0 and inclk1 + areset, // asynchronous reset + pfdena, // enable the Phase Frequency Detector (PFD) + clkena, // enable clk0 to clk5 clock outputs + extclkena, // enable extclk0 to extclk3 clock outputs + scanclk, // clock for the serial scan chain + scanaclr, // asynchronous clear the serial scan chain + scanread, // determines when the scan chain can read in data from the scandata port + scanwrite, // determines when the scan chain can write out data into pll + scandata, // data for the scan chain + clk, // internal clock outputs (feeds the core) + extclk, // external clock outputs (feeds pins) + clkbad, // indicates if inclk0/inclk1 has gone bad + enable0, // load enable pulse 0 for lvds + enable1, // load enable pulse l for lvds + activeclock, // indicates which input clock is being used + clkloss, // indicates when clock switchover initiates + locked, // indicates when the PLL locks onto the input clock + scandataout, // data output of the serial scan chain + scandone, // indicates when pll reconfiguration is complete + sclkout0, // serial clock output 0 for lvds + sclkout1 // serial clock output 1 for lvds +); + +// GLOBAL PARAMETER DECLARATION +parameter intended_device_family = "Stratix" ; +parameter operation_mode = "NORMAL" ; +parameter pll_type = "AUTO" ; +parameter qualify_conf_done = "OFF" ; +parameter compensate_clock = "CLK0" ; +parameter scan_chain = "LONG"; +parameter primary_clock = "inclk0"; +parameter inclk0_input_frequency = 1000; +parameter inclk1_input_frequency = 0; +parameter gate_lock_signal = "NO"; +parameter gate_lock_counter = 0; +parameter lock_high = 1; +parameter lock_low = 5; +parameter valid_lock_multiplier = 1; +parameter invalid_lock_multiplier = 5; +parameter switch_over_type = "AUTO"; +parameter switch_over_on_lossclk = "OFF" ; +parameter switch_over_on_gated_lock = "OFF" ; +parameter enable_switch_over_counter = "OFF"; +parameter switch_over_counter = 0; +parameter feedback_source = "EXTCLK0" ; +parameter bandwidth = 0; +parameter bandwidth_type = "UNUSED"; +parameter lpm_hint = "UNUSED"; +parameter spread_frequency = 0; +parameter down_spread = "0.0"; +parameter self_reset_on_gated_loss_lock = "OFF"; + +// simulation-only parameters +parameter simulation_type = "functional"; +parameter source_is_pll = "off"; + +parameter skip_vco = "off"; + +// internal clock specifications +parameter clk5_multiply_by = 1; +parameter clk4_multiply_by = 1; +parameter clk3_multiply_by = 1; +parameter clk2_multiply_by = 1; +parameter clk1_multiply_by = 1; +parameter clk0_multiply_by = 1; +parameter clk5_divide_by = 1; +parameter clk4_divide_by = 1; +parameter clk3_divide_by = 1; +parameter clk2_divide_by = 1; +parameter clk1_divide_by = 1; +parameter clk0_divide_by = 1; +parameter clk5_phase_shift = "0"; +parameter clk4_phase_shift = "0"; +parameter clk3_phase_shift = "0"; +parameter clk2_phase_shift = "0"; +parameter clk1_phase_shift = "0"; +parameter clk0_phase_shift = "0"; + +parameter clk5_time_delay = "0"; // For stratix pll use only +parameter clk4_time_delay = "0"; // For stratix pll use only +parameter clk3_time_delay = "0"; // For stratix pll use only +parameter clk2_time_delay = "0"; // For stratix pll use only +parameter clk1_time_delay = "0"; // For stratix pll use only +parameter clk0_time_delay = "0"; // For stratix pll use only +parameter clk5_duty_cycle = 50; +parameter clk4_duty_cycle = 50; +parameter clk3_duty_cycle = 50; +parameter clk2_duty_cycle = 50; +parameter clk1_duty_cycle = 50; +parameter clk0_duty_cycle = 50; + +parameter clk2_output_frequency = 0; +parameter clk1_output_frequency = 0; +parameter clk0_output_frequency = 0; + +// external clock specifications (for stratix pll use only) +parameter extclk3_multiply_by = 1; +parameter extclk2_multiply_by = 1; +parameter extclk1_multiply_by = 1; +parameter extclk0_multiply_by = 1; +parameter extclk3_divide_by = 1; +parameter extclk2_divide_by = 1; +parameter extclk1_divide_by = 1; +parameter extclk0_divide_by = 1; +parameter extclk3_phase_shift = "0"; +parameter extclk2_phase_shift = "0"; +parameter extclk1_phase_shift = "0"; +parameter extclk0_phase_shift = "0"; +parameter extclk3_time_delay = "0"; +parameter extclk2_time_delay = "0"; +parameter extclk1_time_delay = "0"; +parameter extclk0_time_delay = "0"; +parameter extclk3_duty_cycle = 50; +parameter extclk2_duty_cycle = 50; +parameter extclk1_duty_cycle = 50; +parameter extclk0_duty_cycle = 50; + +// The following 4 parameters are for Stratix II pll in lvds mode only +parameter vco_multiply_by = 0; +parameter vco_divide_by = 0; +parameter sclkout0_phase_shift = "0"; +parameter sclkout1_phase_shift = "0"; + +// advanced user parameters +parameter vco_min = 0; +parameter vco_max = 0; +parameter vco_center = 0; +parameter pfd_min = 0; +parameter pfd_max = 0; +parameter m_initial = 1; +parameter m = 0; // m must default to 0 in order for altpll to calculate advanced parameters for itself +parameter n = 1; +parameter m2 = 1; +parameter n2 = 1; +parameter ss = 0; +parameter l0_high = 1; +parameter l1_high = 1; +parameter g0_high = 1; +parameter g1_high = 1; +parameter g2_high = 1; +parameter g3_high = 1; +parameter e0_high = 1; +parameter e1_high = 1; +parameter e2_high = 1; +parameter e3_high = 1; +parameter l0_low = 1; +parameter l1_low = 1; +parameter g0_low = 1; +parameter g1_low = 1; +parameter g2_low = 1; +parameter g3_low = 1; +parameter e0_low = 1; +parameter e1_low = 1; +parameter e2_low = 1; +parameter e3_low = 1; +parameter l0_initial = 1; +parameter l1_initial = 1; +parameter g0_initial = 1; +parameter g1_initial = 1; +parameter g2_initial = 1; +parameter g3_initial = 1; +parameter e0_initial = 1; +parameter e1_initial = 1; +parameter e2_initial = 1; +parameter e3_initial = 1; +parameter l0_mode = "bypass"; +parameter l1_mode = "bypass"; +parameter g0_mode = "bypass"; +parameter g1_mode = "bypass"; +parameter g2_mode = "bypass"; +parameter g3_mode = "bypass"; +parameter e0_mode = "bypass"; +parameter e1_mode = "bypass"; +parameter e2_mode = "bypass"; +parameter e3_mode = "bypass"; +parameter l0_ph = 0; +parameter l1_ph = 0; +parameter g0_ph = 0; +parameter g1_ph = 0; +parameter g2_ph = 0; +parameter g3_ph = 0; +parameter e0_ph = 0; +parameter e1_ph = 0; +parameter e2_ph = 0; +parameter e3_ph = 0; +parameter m_ph = 0; +parameter l0_time_delay = 0; +parameter l1_time_delay = 0; +parameter g0_time_delay = 0; +parameter g1_time_delay = 0; +parameter g2_time_delay = 0; +parameter g3_time_delay = 0; +parameter e0_time_delay = 0; +parameter e1_time_delay = 0; +parameter e2_time_delay = 0; +parameter e3_time_delay = 0; +parameter m_time_delay = 0; +parameter n_time_delay = 0; +parameter extclk3_counter = "e3" ; +parameter extclk2_counter = "e2" ; +parameter extclk1_counter = "e1" ; +parameter extclk0_counter = "e0" ; +parameter clk5_counter = "l1" ; +parameter clk4_counter = "l0" ; +parameter clk3_counter = "g3" ; +parameter clk2_counter = "g2" ; +parameter clk1_counter = "g1" ; +parameter clk0_counter = "g0" ; +parameter enable0_counter = "l0"; +parameter enable1_counter = "l0"; +parameter charge_pump_current = 2; +parameter loop_filter_r = "1.0"; +parameter loop_filter_c = 5; +parameter vco_post_scale = 0; +parameter lpm_type = "altpll"; + +// The following parameter are used to define the connectivity for some of the input +// and output ports. +parameter port_clkena0 = "PORT_CONNECTIVITY"; +parameter port_clkena1 = "PORT_CONNECTIVITY"; +parameter port_clkena2 = "PORT_CONNECTIVITY"; +parameter port_clkena3 = "PORT_CONNECTIVITY"; +parameter port_clkena4 = "PORT_CONNECTIVITY"; +parameter port_clkena5 = "PORT_CONNECTIVITY"; +parameter port_extclkena0 = "PORT_CONNECTIVITY"; +parameter port_extclkena1 = "PORT_CONNECTIVITY"; +parameter port_extclkena2 = "PORT_CONNECTIVITY"; +parameter port_extclkena3 = "PORT_CONNECTIVITY"; +parameter port_extclk0 = "PORT_CONNECTIVITY"; +parameter port_extclk1 = "PORT_CONNECTIVITY"; +parameter port_extclk2 = "PORT_CONNECTIVITY"; +parameter port_extclk3 = "PORT_CONNECTIVITY"; +parameter port_clk0 = "PORT_CONNECTIVITY"; +parameter port_clk1 = "PORT_CONNECTIVITY"; +parameter port_clk2 = "PORT_CONNECTIVITY"; +parameter port_clk3 = "PORT_CONNECTIVITY"; +parameter port_clk4 = "PORT_CONNECTIVITY"; +parameter port_clk5 = "PORT_CONNECTIVITY"; +parameter port_scandata = "PORT_CONNECTIVITY"; +parameter port_scandataout = "PORT_CONNECTIVITY"; +parameter port_scandone = "PORT_CONNECTIVITY"; +parameter port_sclkout1 = "PORT_CONNECTIVITY"; +parameter port_sclkout0 = "PORT_CONNECTIVITY"; +parameter port_clkbad0 = "PORT_CONNECTIVITY"; +parameter port_clkbad1 = "PORT_CONNECTIVITY"; +parameter port_activeclock = "PORT_CONNECTIVITY"; +parameter port_clkloss = "PORT_CONNECTIVITY"; +parameter port_inclk1 = "PORT_CONNECTIVITY"; +parameter port_inclk0 = "PORT_CONNECTIVITY"; +parameter port_fbin = "PORT_CONNECTIVITY"; +parameter port_pllena = "PORT_CONNECTIVITY"; +parameter port_clkswitch = "PORT_CONNECTIVITY"; +parameter port_areset = "PORT_CONNECTIVITY"; +parameter port_pfdena = "PORT_CONNECTIVITY"; +parameter port_scanclk = "PORT_CONNECTIVITY"; +parameter port_scanaclr = "PORT_CONNECTIVITY"; +parameter port_scanread = "PORT_CONNECTIVITY"; +parameter port_scanwrite = "PORT_CONNECTIVITY"; +parameter port_enable0 = "PORT_CONNECTIVITY"; +parameter port_enable1 = "PORT_CONNECTIVITY"; + +//For Stratixii pll use only +parameter c0_high = 1; +parameter c1_high = 1; +parameter c2_high = 1; +parameter c3_high = 1; +parameter c4_high = 1; +parameter c5_high = 1; +parameter c0_low = 1; +parameter c1_low = 1; +parameter c2_low = 1; +parameter c3_low = 1; +parameter c4_low = 1; +parameter c5_low = 1; +parameter c0_initial = 1; +parameter c1_initial = 1; +parameter c2_initial = 1; +parameter c3_initial = 1; +parameter c4_initial = 1; +parameter c5_initial = 1; +parameter c0_mode = "bypass"; +parameter c1_mode = "bypass"; +parameter c2_mode = "bypass"; +parameter c3_mode = "bypass"; +parameter c4_mode = "bypass"; +parameter c5_mode = "bypass"; +parameter c0_ph = 0; +parameter c1_ph = 0; +parameter c2_ph = 0; +parameter c3_ph = 0; +parameter c4_ph = 0; +parameter c5_ph = 0; +parameter c1_use_casc_in = "off"; +parameter c2_use_casc_in = "off"; +parameter c3_use_casc_in = "off"; +parameter c4_use_casc_in = "off"; +parameter c5_use_casc_in = "off"; +parameter m_test_source = 5; +parameter c0_test_source = 5; +parameter c1_test_source = 5; +parameter c2_test_source = 5; +parameter c3_test_source = 5; +parameter c4_test_source = 5; +parameter c5_test_source = 5; + +// INPUT PORT DECLARATION +input [1:0] inclk; +input fbin; +input pllena; +input clkswitch; +input areset; +input pfdena; +input [5:0] clkena; +input [3:0] extclkena; +input scanclk; +input scanaclr; +input scanread; +input scanwrite; +input scandata; + +// OUTPUT PORT DECLARATION +output [5:0] clk; +output [3:0] extclk; +output [1:0] clkbad; +output activeclock; +output enable0; +output enable1; +output clkloss; +output locked; +output scandataout; +output scandone; +output sclkout0; +output sclkout1; + +// pullups +tri1 fbin_pullup; +tri1 ena_pullup; +tri1 pfdena_pullup; +tri1 [5:0] clkena_pullup; +tri1 [3:0] extclkena_pullup; + +// pulldowns +tri0 [1:0] inclk_pulldown; +tri0 clkswitch_pulldown; +tri0 areset_pulldown; +tri0 scanclk_pulldown; +tri0 scanclr_pulldown; +tri0 scanread_pulldown; +tri0 scanwrite_pulldown; +tri0 scandata_pulldown; +tri0 comparator_pulldown; + +// For fast mode, the stratix pll atom model will give active low signal on locked output. +// Therefore, need to invert the lock signal for fast mode as in user view, locked signal is +// always active high. +wire locked_tmp; +wire [1:0] stratix_inclk; +wire stratix_fbin; +wire stratix_ena; +wire stratix_clkswitch; +wire stratix_areset; +wire stratix_pfdena; +wire [5:0] stratix_clkena; +wire [3:0] stratix_extclkena; +wire stratix_scanclk; +wire stratix_scanclr; +wire stratix_scandata; +wire [5:0] stratix_clk; +wire [3:0] stratix_extclk; +wire [1:0] stratix_clkbad; +wire stratix_activeclock; +wire stratix_locked; +wire stratix_clkloss; +wire stratix_scandataout; +wire stratix_enable0; +wire stratix_enable1; + +wire [1:0] stratixii_inclk; +wire stratixii_fbin; +wire stratixii_ena; +wire stratixii_clkswitch; +wire stratixii_areset; +wire stratixii_pfdena; +wire stratixii_scanread; +wire stratixii_scanwrite; +wire stratixii_scanclk; +wire stratixii_scandata; +wire stratixii_scandone; +wire [5:0] stratixii_clk; +wire [1:0] stratixii_clkbad; +wire stratixii_activeclock; +wire stratixii_locked; +wire stratixii_clkloss; +wire stratixii_scandataout; +wire stratixii_enable0; +wire stratixii_enable1; +wire stratixii_sclkout0; +wire stratixii_sclkout1; + +wire[5:0] clk_wire; +wire[1:0] clkbad_wire; +wire activeclock_wire; +wire clkloss_wire; +wire scandataout_wire; +wire scandone_wire; +wire sclkout0_wire; +wire sclkout1_wire; + +ALTERA_DEVICE_FAMILIES dev (); + +// INITIAL BLOCK +initial +begin + + // Begin of parameter checking + + if (clk5_multiply_by <= 0) + begin + $display("ERROR: The clk5_multiply_by must be greater than 0"); + $stop; + end + + if (clk4_multiply_by <= 0) + begin + $display("ERROR: The clk4_multiply_by must be greater than 0"); + $stop; + end + + if (clk3_multiply_by <= 0) + begin + $display("ERROR: The clk3_multiply_by must be greater than 0"); + $stop; + end + + + if (clk2_multiply_by <= 0) + begin + $display("ERROR: The clk2_multiply_by must be greater than 0"); + $stop; + end + + if (clk1_multiply_by <= 0) + begin + $display("ERROR: The clk1_multiply_by must be greater than 0"); + $stop; + end + + if (clk0_multiply_by <= 0) + begin + $display("ERROR: The clk0_multiply_by must be greater than 0"); + $stop; + end + + if (clk5_divide_by <= 0) + begin + $display("ERROR: The clk5_divide_by must be greater than 0"); + $stop; + end + + + if (clk4_divide_by <= 0) + begin + $display("ERROR: The clk4_divide_by must be greater than 0"); + $stop; + end + + + if (clk3_divide_by <= 0) + begin + $display("ERROR: The clk3_divide_by must be greater than 0"); + $stop; + end + + + if (clk2_divide_by <= 0) + begin + $display("ERROR: The clk2_divide_by must be greater than 0"); + $stop; + end + + + if (clk1_divide_by <= 0) + begin + $display("ERROR: The clk1_divide_by must be greater than 0"); + $stop; + end + + + if (clk0_divide_by <= 0) + begin + $display("ERROR: The clk0_divide_by must be greater than 0"); + $stop; + end + + if (extclk3_multiply_by <= 0) + begin + $display("ERROR: The extclk3_multiply_by must be greater than 0"); + $stop; + end + + if (extclk2_multiply_by <= 0) + begin + $display("ERROR: The extclk2_multiply_by must be greater than 0"); + $stop; + end + + if (extclk1_multiply_by <= 0) + begin + $display("ERROR: The extclk1_multiply_by must be greater than 0"); + $stop; + end + + if (extclk0_multiply_by <= 0) + begin + $display("ERROR: The extclk0_multiply_by must be greater than 0"); + $stop; + end + + + if (extclk3_divide_by <= 0) + begin + $display("ERROR: The extclk3_divide_by must be greater than 0"); + $stop; + end + + + if (extclk2_divide_by <= 0) + begin + $display("ERROR: The extclk2_divide_by must be greater than 0"); + $stop; + end + + + if (extclk1_divide_by <= 0) + begin + $display("ERROR: The extclk1_divide_by must be greater than 0"); + $stop; + end + + + if (extclk0_divide_by <= 0) + begin + $display("ERROR: The extclk0_divide_by must be greater than 0"); + $stop; + end + + if (!((primary_clock == "inclk0") || (primary_clock == "INCLK0") || + (primary_clock == "inclk1") || (primary_clock == "INCLK1"))) + begin + $display("ERROR: The primary clock is set to an illegal value"); + $stop; + end + + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $stop; + end + // End of parameter checking + +end + +// COMPONENT INSTANTIATION +MF_stratix_pll pll0 +( + .inclk (stratix_inclk), + .fbin (stratix_fbin), + .ena (stratix_ena), + .clkswitch (stratix_clkswitch), + .areset (stratix_areset), + .pfdena (stratix_pfdena), + .clkena (stratix_clkena), + .extclkena (stratix_extclkena), + .scanclk (stratix_scanclk), + .scanaclr (stratix_scanclr), + .scandata (stratix_scandata), + .comparator(), + .clk (stratix_clk), + .extclk (stratix_extclk), + .clkbad (stratix_clkbad), + .activeclock (stratix_activeclock), + .locked (locked_tmp), + .clkloss (stratix_clkloss), + .scandataout (stratix_scandataout), + .enable0 (stratix_enable0), + .enable1 (stratix_enable1) +); + defparam + pll0.operation_mode = operation_mode, + pll0.pll_type = pll_type, + pll0.qualify_conf_done = qualify_conf_done, + pll0.compensate_clock = compensate_clock, + pll0.scan_chain = scan_chain, + pll0.primary_clock = primary_clock, + pll0.inclk0_input_frequency = inclk0_input_frequency, + pll0.inclk1_input_frequency = inclk1_input_frequency, + pll0.gate_lock_signal = gate_lock_signal, + pll0.gate_lock_counter = gate_lock_counter, + pll0.valid_lock_multiplier = valid_lock_multiplier, + pll0.invalid_lock_multiplier = invalid_lock_multiplier, + pll0.switch_over_on_lossclk = switch_over_on_lossclk, + pll0.switch_over_on_gated_lock = switch_over_on_gated_lock, + pll0.enable_switch_over_counter = enable_switch_over_counter, + pll0.switch_over_counter = switch_over_counter, + pll0.feedback_source = feedback_source, + pll0.bandwidth = bandwidth, + pll0.bandwidth_type = bandwidth_type, + pll0.spread_frequency = spread_frequency, + pll0.down_spread = down_spread, + pll0.simulation_type = simulation_type, + pll0.skip_vco = skip_vco, + + // internal clock specifications + pll0.clk5_multiply_by = clk5_multiply_by, + pll0.clk4_multiply_by = clk4_multiply_by, + pll0.clk3_multiply_by = clk3_multiply_by, + pll0.clk2_multiply_by = clk2_multiply_by, + pll0.clk1_multiply_by = clk1_multiply_by, + pll0.clk0_multiply_by = clk0_multiply_by, + pll0.clk5_divide_by = clk5_divide_by, + pll0.clk4_divide_by = clk4_divide_by, + pll0.clk3_divide_by = clk3_divide_by, + pll0.clk2_divide_by = clk2_divide_by, + pll0.clk1_divide_by = clk1_divide_by, + pll0.clk0_divide_by = clk0_divide_by, + pll0.clk5_phase_shift = clk5_phase_shift, + pll0.clk4_phase_shift = clk4_phase_shift, + pll0.clk3_phase_shift = clk3_phase_shift, + pll0.clk2_phase_shift = clk2_phase_shift, + pll0.clk1_phase_shift = clk1_phase_shift, + pll0.clk0_phase_shift = clk0_phase_shift, + pll0.clk5_time_delay = clk5_time_delay, + pll0.clk4_time_delay = clk4_time_delay, + pll0.clk3_time_delay = clk3_time_delay, + pll0.clk2_time_delay = clk2_time_delay, + pll0.clk1_time_delay = clk1_time_delay, + pll0.clk0_time_delay = clk0_time_delay, + pll0.clk5_duty_cycle = clk5_duty_cycle, + pll0.clk4_duty_cycle = clk4_duty_cycle, + pll0.clk3_duty_cycle = clk3_duty_cycle, + pll0.clk2_duty_cycle = clk2_duty_cycle, + pll0.clk1_duty_cycle = clk1_duty_cycle, + pll0.clk0_duty_cycle = clk0_duty_cycle, + + // external clock specifications + pll0.extclk3_multiply_by = extclk3_multiply_by, + pll0.extclk2_multiply_by = extclk2_multiply_by, + pll0.extclk1_multiply_by = extclk1_multiply_by, + pll0.extclk0_multiply_by = extclk0_multiply_by, + pll0.extclk3_divide_by = extclk3_divide_by, + pll0.extclk2_divide_by = extclk2_divide_by, + pll0.extclk1_divide_by = extclk1_divide_by, + pll0.extclk0_divide_by = extclk0_divide_by, + pll0.extclk3_phase_shift = extclk3_phase_shift, + pll0.extclk2_phase_shift = extclk2_phase_shift, + pll0.extclk1_phase_shift = extclk1_phase_shift, + pll0.extclk0_phase_shift = extclk0_phase_shift, + pll0.extclk3_time_delay = extclk3_time_delay, + pll0.extclk2_time_delay = extclk2_time_delay, + pll0.extclk1_time_delay = extclk1_time_delay, + pll0.extclk0_time_delay = extclk0_time_delay, + pll0.extclk3_duty_cycle = extclk3_duty_cycle, + pll0.extclk2_duty_cycle = extclk2_duty_cycle, + pll0.extclk1_duty_cycle = extclk1_duty_cycle, + pll0.extclk0_duty_cycle = extclk0_duty_cycle, + + // advanced parameters + pll0.vco_min = vco_min, + pll0.vco_max = vco_max, + pll0.vco_center = vco_center, + pll0.pfd_min = pfd_min, + pll0.pfd_max = pfd_max, + pll0.m_initial = m_initial, + pll0.m = m, + pll0.n = n, + pll0.m2 = m2, + pll0.n2 = n2, + pll0.ss = ss, + pll0.l0_high = l0_high, + pll0.l1_high = l1_high, + pll0.g0_high = g0_high, + pll0.g1_high = g1_high, + pll0.g2_high = g2_high, + pll0.g3_high = g3_high, + pll0.e0_high = e0_high, + pll0.e1_high = e1_high, + pll0.e2_high = e2_high, + pll0.e3_high = e3_high, + pll0.l0_low = l0_low, + pll0.l1_low = l1_low, + pll0.g0_low = g0_low, + pll0.g1_low = g1_low, + pll0.g2_low = g2_low, + pll0.g3_low = g3_low, + pll0.e0_low = e0_low, + pll0.e1_low = e1_low, + pll0.e2_low = e2_low, + pll0.e3_low = e3_low, + pll0.l0_initial = l0_initial, + pll0.l1_initial = l1_initial, + pll0.g0_initial = g0_initial, + pll0.g1_initial = g1_initial, + pll0.g2_initial = g2_initial, + pll0.g3_initial = g3_initial, + pll0.e0_initial = e0_initial, + pll0.e1_initial = e1_initial, + pll0.e2_initial = e2_initial, + pll0.e3_initial = e3_initial, + pll0.l0_mode = l0_mode, + pll0.l1_mode = l1_mode, + pll0.g0_mode = g0_mode, + pll0.g1_mode = g1_mode, + pll0.g2_mode = g2_mode, + pll0.g3_mode = g3_mode, + pll0.e0_mode = e0_mode, + pll0.e1_mode = e1_mode, + pll0.e2_mode = e2_mode, + pll0.e3_mode = e3_mode, + pll0.l0_ph = l0_ph, + pll0.l1_ph = l1_ph, + pll0.g0_ph = g0_ph, + pll0.g1_ph = g1_ph, + pll0.g2_ph = g2_ph, + pll0.g3_ph = g3_ph, + pll0.e0_ph = e0_ph, + pll0.e1_ph = e1_ph, + pll0.e2_ph = e2_ph, + pll0.e3_ph = e3_ph, + pll0.m_ph = m_ph, + pll0.l0_time_delay = l0_time_delay, + pll0.l1_time_delay = l1_time_delay, + pll0.g0_time_delay = g0_time_delay, + pll0.g1_time_delay = g1_time_delay, + pll0.g2_time_delay = g2_time_delay, + pll0.g3_time_delay = g3_time_delay, + pll0.e0_time_delay = e0_time_delay, + pll0.e1_time_delay = e1_time_delay, + pll0.e2_time_delay = e2_time_delay, + pll0.e3_time_delay = e3_time_delay, + pll0.m_time_delay = m_time_delay, + pll0.n_time_delay = n_time_delay, + pll0.extclk3_counter = extclk3_counter, + pll0.extclk2_counter = extclk2_counter, + pll0.extclk1_counter = extclk1_counter, + pll0.extclk0_counter = extclk0_counter, + pll0.clk5_counter = clk5_counter, + pll0.clk4_counter = clk4_counter, + pll0.clk3_counter = clk3_counter, + pll0.clk2_counter = clk2_counter, + pll0.clk1_counter = clk1_counter, + pll0.clk0_counter = clk0_counter, + pll0.enable0_counter = enable0_counter, + pll0.enable1_counter = enable1_counter, + pll0.charge_pump_current = charge_pump_current, + pll0.loop_filter_r = loop_filter_r, + pll0.loop_filter_c = loop_filter_c; + +MF_stratixii_pll pll1 +( + .inclk (stratixii_inclk), + .fbin (stratixii_fbin), + .ena (stratixii_ena), + .clkswitch (stratixii_clkswitch), + .areset (stratixii_areset), + .pfdena (stratixii_pfdena), + .scanclk (stratixii_scanclk), + .scanread (stratixii_scanread), + .scanwrite (stratixii_scanwrite), + .scandata (stratixii_scandata), + .testin(), + .scandone (stratixii_scandone), + .clk (stratixii_clk), + .clkbad (stratixii_clkbad), + .activeclock (stratixii_activeclock), + .locked (stratixii_locked), + .clkloss (stratixii_clkloss), + .scandataout (stratixii_scandataout), + .enable0 (stratixii_enable0), + .enable1 (stratixii_enable1), + .testupout (), + .testdownout (), + .sclkout({stratixii_sclkout1, stratixii_sclkout0}) +); + defparam + pll1.operation_mode = operation_mode, + pll1.pll_type = pll_type, + pll1.qualify_conf_done = qualify_conf_done, + pll1.compensate_clock = compensate_clock, + pll1.inclk0_input_frequency = inclk0_input_frequency, + pll1.inclk1_input_frequency = inclk1_input_frequency, + pll1.gate_lock_signal = gate_lock_signal, + pll1.gate_lock_counter = gate_lock_counter, + pll1.valid_lock_multiplier = valid_lock_multiplier, + pll1.invalid_lock_multiplier = invalid_lock_multiplier, + pll1.switch_over_type = switch_over_type, + pll1.switch_over_on_lossclk = switch_over_on_lossclk, + pll1.switch_over_on_gated_lock = switch_over_on_gated_lock, + pll1.enable_switch_over_counter = enable_switch_over_counter, + pll1.switch_over_counter = switch_over_counter, + pll1.feedback_source = (feedback_source == "EXTCLK0") ? "CLK0" : feedback_source, + pll1.bandwidth = bandwidth, + pll1.bandwidth_type = bandwidth_type, + pll1.spread_frequency = spread_frequency, + pll1.down_spread = down_spread, + pll1.self_reset_on_gated_loss_lock = self_reset_on_gated_loss_lock, + pll1.simulation_type = simulation_type, + + // internal clock specifications + pll1.clk5_multiply_by = clk5_multiply_by, + pll1.clk4_multiply_by = clk4_multiply_by, + pll1.clk3_multiply_by = clk3_multiply_by, + pll1.clk2_multiply_by = clk2_multiply_by, + pll1.clk1_multiply_by = clk1_multiply_by, + pll1.clk0_multiply_by = clk0_multiply_by, + pll1.clk5_divide_by = clk5_divide_by, + pll1.clk4_divide_by = clk4_divide_by, + pll1.clk3_divide_by = clk3_divide_by, + pll1.clk2_divide_by = clk2_divide_by, + pll1.clk1_divide_by = clk1_divide_by, + pll1.clk0_divide_by = clk0_divide_by, + pll1.clk5_phase_shift = clk5_phase_shift, + pll1.clk4_phase_shift = clk4_phase_shift, + pll1.clk3_phase_shift = clk3_phase_shift, + pll1.clk2_phase_shift = clk2_phase_shift, + pll1.clk1_phase_shift = clk1_phase_shift, + pll1.clk0_phase_shift = clk0_phase_shift, + pll1.clk5_duty_cycle = clk5_duty_cycle, + pll1.clk4_duty_cycle = clk4_duty_cycle, + pll1.clk3_duty_cycle = clk3_duty_cycle, + pll1.clk2_duty_cycle = clk2_duty_cycle, + pll1.clk1_duty_cycle = clk1_duty_cycle, + pll1.clk0_duty_cycle = clk0_duty_cycle, + pll1.vco_multiply_by = vco_multiply_by, + pll1.vco_divide_by = vco_divide_by, + pll1.clk2_output_frequency = clk2_output_frequency, + pll1.clk1_output_frequency = clk1_output_frequency, + pll1.clk0_output_frequency = clk0_output_frequency, + + // advanced parameters + pll1.vco_min = vco_min, + pll1.vco_max = vco_max, + pll1.vco_center = vco_center, + pll1.pfd_min = pfd_min, + pll1.pfd_max = pfd_max, + pll1.m_initial = m_initial, + pll1.m = m, + pll1.n = n, + pll1.m2 = m2, + pll1.n2 = n2, + pll1.ss = ss, + pll1.c0_high = c0_high, + pll1.c1_high = c1_high, + pll1.c2_high = c2_high, + pll1.c3_high = c3_high, + pll1.c4_high = c4_high, + pll1.c5_high = c5_high, + pll1.c0_low = c0_low, + pll1.c1_low = c1_low, + pll1.c2_low = c2_low, + pll1.c3_low = c3_low, + pll1.c4_low = c4_low, + pll1.c5_low = c5_low, + pll1.c0_initial = c0_initial, + pll1.c1_initial = c1_initial, + pll1.c2_initial = c2_initial, + pll1.c3_initial = c3_initial, + pll1.c4_initial = c4_initial, + pll1.c5_initial = c5_initial, + pll1.c0_mode = c0_mode, + pll1.c1_mode = c1_mode, + pll1.c2_mode = c2_mode, + pll1.c3_mode = c3_mode, + pll1.c4_mode = c4_mode, + pll1.c5_mode = c5_mode, + pll1.c0_ph = c0_ph, + pll1.c1_ph = c1_ph, + pll1.c2_ph = c2_ph, + pll1.c3_ph = c3_ph, + pll1.c4_ph = c4_ph, + pll1.c5_ph = c5_ph, + pll1.m_ph = m_ph, + pll1.c1_use_casc_in = c1_use_casc_in, + pll1.c2_use_casc_in = c2_use_casc_in, + pll1.c3_use_casc_in = c3_use_casc_in, + pll1.c4_use_casc_in = c4_use_casc_in, + pll1.c5_use_casc_in = c5_use_casc_in, + pll1.clk5_counter = (clk5_counter == "l1") ? "c5" : clk5_counter, + pll1.clk4_counter = (clk4_counter == "l0") ? "c4" : clk4_counter, + pll1.clk3_counter = (clk3_counter == "g3") ? "c3" : clk3_counter, + pll1.clk2_counter = (clk2_counter == "g2") ? "c2" : clk2_counter, + pll1.clk1_counter = (clk1_counter == "g1") ? "c1" : clk1_counter, + pll1.clk0_counter = (clk0_counter == "g0") ? "c0" : clk0_counter, + pll1.enable0_counter = (enable0_counter == "l0") ? "c0" : enable0_counter, + pll1.enable1_counter = (enable1_counter == "l0") ? "c1" : enable1_counter, + pll1.charge_pump_current = charge_pump_current, + pll1.loop_filter_r = loop_filter_r, + pll1.loop_filter_c = loop_filter_c, + pll1.m_test_source = m_test_source, + pll1.c0_test_source = c0_test_source, + pll1.c1_test_source = c1_test_source, + pll1.c2_test_source = c2_test_source, + pll1.c3_test_source = c3_test_source, + pll1.c4_test_source = c4_test_source, + pll1.c5_test_source = c5_test_source; + +// CONTINOUS ASSIGNMENT +assign fbin_pullup = ((port_fbin == "PORT_CONNECTIVITY") || + (port_fbin == "PORT_USED")) ? fbin : 1'b1; +assign ena_pullup = ((port_pllena == "PORT_CONNECTIVITY") || + (port_pllena == "PORT_USED")) ? pllena : 1'b1; +assign pfdena_pullup = ((port_pfdena == "PORT_CONNECTIVITY") || + (port_pfdena == "PORT_USED")) ? pfdena : 1'b1; +assign clkena_pullup[0] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_clkena0 == "PORT_USED")) && + (port_clkena0 != "PORT_UNUSED") ? clkena[0] : 1'b1; +assign clkena_pullup[1] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_clkena1 == "PORT_USED")) && + (port_clkena1 != "PORT_UNUSED") ? clkena[1] : 1'b1; +assign clkena_pullup[2] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_clkena2 == "PORT_USED")) && + (port_clkena2 != "PORT_UNUSED") ? clkena[2] : 1'b1; +assign clkena_pullup[3] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_clkena3 == "PORT_USED")) && + (port_clkena3 != "PORT_UNUSED") ? clkena[3] : 1'b1; +assign clkena_pullup[4] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_clkena4 == "PORT_USED")) && + (port_clkena4 != "PORT_UNUSED") ? clkena[4] : 1'b1; +assign clkena_pullup[5] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_clkena5 == "PORT_USED")) && + (port_clkena5 != "PORT_UNUSED") ? clkena[5] : 1'b1; + +assign extclkena_pullup[0] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_extclkena0 == "PORT_USED")) && + (port_extclkena0 != "PORT_UNUSED") ? extclkena[0] : 1'b1; +assign extclkena_pullup[1] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_extclkena1 == "PORT_USED")) && + (port_extclkena1 != "PORT_UNUSED") ? extclkena[1] : 1'b1; +assign extclkena_pullup[2] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_extclkena2 == "PORT_USED")) && + (port_extclkena2 != "PORT_UNUSED") ? extclkena[2] : 1'b1; +assign extclkena_pullup[3] = (!((pll_type == "fast") || (pll_type == "FAST")) || + (port_extclkena3 == "PORT_USED")) && + (port_extclkena3 != "PORT_UNUSED") ? extclkena[3] : 1'b1; +assign scanclk_pulldown = scanclk; +assign scanread_pulldown = ((port_scanread == "PORT_CONNECTIVITY") || + (port_scanread == "PORT_USED")) ? scanread : 1'b0; +assign scanwrite_pulldown = ((port_scanwrite == "PORT_CONNECTIVITY") || + (port_scanwrite == "PORT_USED")) ? scanwrite : 1'b0; +assign scandata_pulldown = ((port_scandata == "PORT_CONNECTIVITY") || + (port_scandata == "PORT_USED")) ? scandata : 1'b0; +assign inclk_pulldown = inclk; +assign clkswitch_pulldown = ((port_clkswitch == "PORT_CONNECTIVITY") || + (port_clkswitch == "PORT_USED")) ? clkswitch : 1'b0; +assign areset_pulldown = ((port_areset == "PORT_CONNECTIVITY") || + (port_areset == "PORT_USED")) ? areset : 1'b0; +assign scanclr_pulldown = ((port_scanaclr == "PORT_CONNECTIVITY") || + (port_scanaclr == "PORT_USED")) ? scanaclr : 1'b0; + +assign stratix_inclk = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? inclk_pulldown : {2{1'b0}}; +assign stratix_fbin = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? fbin_pullup : 1'b0; +assign stratix_ena = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? ena_pullup : 1'b0; +assign stratix_clkswitch = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? clkswitch_pulldown : 1'b0; +assign stratix_areset = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? areset_pulldown : 1'b0; +assign stratix_pfdena = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? pfdena_pullup : 1'b1; +assign stratix_clkena = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? clkena_pullup : {5{1'b0}}; +assign stratix_extclkena = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? extclkena_pullup : {3{1'b0}}; +assign stratix_scanclk = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? scanclk_pulldown : 1'b0; +assign stratix_scanclr = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? scanclr_pulldown : 1'b0; +assign stratix_scandata = (!dev.FEATURE_FAMILY_STRATIXII(intended_device_family) && + !dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? scandata_pulldown : 1'b0; +assign stratixii_inclk = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? inclk_pulldown : {2{1'b0}}; +assign stratixii_fbin = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? fbin_pullup : 1'b0; +assign stratixii_ena = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? ena_pullup : 1'b0; +assign stratixii_clkswitch = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? clkswitch_pulldown : 1'b0; +assign stratixii_areset = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? areset_pulldown : 1'b0; +assign stratixii_pfdena = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? pfdena_pullup : 1'b1; +assign stratixii_scanread = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? scanread_pulldown : 1'b0; +assign stratixii_scanwrite = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? scanwrite_pulldown : 1'b0; +assign stratixii_scanclk = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? scanclk_pulldown : 1'b0; +assign stratixii_scandata = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? scandata_pulldown : 1'b0; +assign scandone_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_scandone : 1'b0; +assign scandone = (port_scandone != "PORT_UNUSED") ? scandone_wire : 1'b0; +assign clk_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_clk : + (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? {3'b0, stratixii_clk[2:0]} : stratix_clk; +assign clk[0] = (port_clk0 != "PORT_UNUSED") ? clk_wire[0] : 1'b0; +assign clk[1] = (port_clk1 != "PORT_UNUSED") ? clk_wire[1] : 1'b0; +assign clk[2] = (port_clk2 != "PORT_UNUSED") ? clk_wire[2] : 1'b0; +assign clk[3] = (port_clk3 != "PORT_UNUSED") ? clk_wire[3] : 1'b0; +assign clk[4] = (port_clk4 != "PORT_UNUSED") ? clk_wire[4] : 1'b0; +assign clk[5] = (port_clk5 != "PORT_UNUSED") ? clk_wire[5] : 1'b0; +assign extclk[0] = (port_extclk0 != "PORT_UNUSED") ? stratix_extclk[0] : 1'b0; +assign extclk[1] = (port_extclk1 != "PORT_UNUSED") ? stratix_extclk[1] : 1'b0; +assign extclk[2] = (port_extclk2 != "PORT_UNUSED") ? stratix_extclk[2] : 1'b0; +assign extclk[3] = (port_extclk3 != "PORT_UNUSED") ? stratix_extclk[3] : 1'b0; +assign clkbad_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_clkbad : + (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 2'b0 : stratix_clkbad; +assign clkbad[0] = (port_clkbad0 != "PORT_UNUSED") ? clkbad_wire[0] : 1'b0; +assign clkbad[1] = (port_clkbad1 != "PORT_UNUSED") ? clkbad_wire[1] : 1'b0; +assign activeclock_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_activeclock : + (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_activeclock; +assign activeclock = (port_activeclock != "PORT_UNUSED") ? activeclock_wire : 1'b0; +assign locked = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? stratixii_locked : stratix_locked; +assign stratix_locked = ((pll_type == "fast") || (pll_type == "FAST")) ? (!locked_tmp) : locked_tmp; +assign clkloss_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_clkloss : + (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_clkloss; +assign clkloss = (port_clkloss != "PORT_UNUSED") ? clkloss_wire : 1'b0; +assign scandataout_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_scandataout : + (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_scandataout; +assign scandataout = (port_scandataout != "PORT_UNUSED") ? scandataout_wire : 1'b0; +assign enable0 = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_enable0 : + (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_enable0; +assign enable1 = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_enable1 : + (dev.IS_FAMILY_CYCLONEII(intended_device_family)) ? 1'b0 : stratix_enable1; +assign sclkout0_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_sclkout0 : 1'b0; +assign sclkout0 = (port_sclkout0 != "PORT_UNUSED") ? sclkout0_wire : 1'b0; +assign sclkout1_wire = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) ? stratixii_sclkout1 : 1'b0; +assign sclkout1 = (port_sclkout1 != "PORT_UNUSED") ? sclkout1_wire : 1'b0; +endmodule //altpll + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : altaccumulate +// +// Description : Parameterized accumulator megafunction. The accumulator +// performs an add function or a subtract function based on the add_sub +// parameter. The input data can be signed or unsigned. +// +// Limitation : n/a +// +// Results expected: result - The results of add or subtract operation. Output +// port [width_out-1 .. 0] wide. +// cout - The cout port has a physical interpretation as +// the carry-out (borrow-in) of the MSB. The cout +// port is most meaningful for detecting overflow +// in unsigned operations. The cout port operates +// in the same manner for signed and unsigned +// operations. +// overflow - Indicates the accumulator is overflow. +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE + +`timescale 1 ps / 1 ps + +module altaccumulate (cin, data, add_sub, clock, sload, clken, sign_data, aclr, + result, cout, overflow); + + parameter width_in = 4; // Required + parameter width_out = 8; // Required + parameter lpm_representation = "UNSIGNED"; + parameter extra_latency = 0; + parameter use_wys = "ON"; + parameter lpm_hint = "UNUSED"; + parameter lpm_type = "altaccumulate"; + + // INPUT PORT DECLARATION + input cin; + input [width_in-1:0] data; // Required port + input add_sub; // Default = 1 + input clock; // Required port + input sload; // Default = 0 + input clken; // Default = 1 + input sign_data; // Default = 0 + input aclr; // Default = 0 + + // OUTPUT PORT DECLARATION + output [width_out-1:0] result; //Required port + output cout; + output overflow; + + // INTERNAL REGISTERS DECLARATION + reg [width_out:0] temp_sum; + reg overflow; + reg overflow_int; + reg cout_int; + reg cout_delayed; + + reg [width_out-1:0] result; + reg [width_out+1:0] result_int; + reg [(width_out - width_in) : 0] zeropad; + + reg borrow; + reg cin_int; + + reg [width_out-1:0] fb_int; + reg [width_out -1:0] data_int; + + reg [width_out+1:0] result_pipe [extra_latency:0]; + reg [width_out+1:0] result_full; + reg [width_out+1:0] result_full2; + + reg a; + + // INTERNAL WIRE DECLARATION + wire [width_out:0] temp_sum_wire; + wire cout; + wire cout_int_wire; + wire cout_delayed_wire; + wire overflow_int_wire; + wire [width_out+1:0] result_int_wire; + + // INTERNAL TRI DECLARATION + + tri0 aclr_int; + tri0 sign_data_int; + tri0 sload_int; + + tri1 clken_int; + tri1 add_sub_int; + + // LOCAL INTEGER DECLARATION + integer head; + integer i; + + // INITIAL CONSTRUCT BLOCK + initial + begin + + // Checking for invalid parameters + if( width_in <= 0 ) + begin + $display("Error! Value of width_in parameter must be greater than 0."); + $stop; + end + + if( width_out <= 0 ) + begin + $display("Error! Value of width_out parameter must be greater than 0."); + $stop; + end + + if( extra_latency > width_out ) + begin + $display("Info: Value of extra_latency parameter should be lower than width_out parameter for better performance/utilization."); + end + + if( width_in > width_out ) + begin + $display("Error! Value of width_in parameter should be lower than or equal to width_out."); + $stop; + end + + result = 0; + cout_delayed = 0; + overflow = 0; + head = 0; + result_int = 0; + for (i = 0; i <= extra_latency; i = i +1) + begin + result_pipe [i] = 0; + end + end + + // ALWAYS CONSTRUCT BLOCK + always @(posedge clock or posedge aclr_int) + begin + + if (aclr_int == 1) + begin + result_int = 0; + result = 0; + overflow = 0; + cout_delayed = 0; + for (i = 0; i <= extra_latency; i = i +1) + begin + result_pipe [i] = 0; + end + + end + else + begin + if (clken_int == 1) + begin + //get result from output register + if (extra_latency > 0) + begin + result_pipe [head] = { + result_int [width_out+1], + {cout_int_wire, result_int [width_out-1:0]} + }; + + head = (head + 1) % (extra_latency); + + result_full = result_pipe [head]; + cout_delayed = result_full [width_out]; + result = result_full [width_out-1:0]; + overflow = result_full [width_out+1]; + end + else + begin + result = temp_sum_wire; + overflow = overflow_int_wire; + end + + result_int = {overflow_int_wire, {cout_int_wire, temp_sum_wire [width_out-1:0]}}; + end + end + end + + + always @ (data or cin or add_sub_int or sign_data_int or + result_int_wire [width_out -1:0] or sload_int) + begin + + if ((lpm_representation == "SIGNED") || (sign_data_int == 1)) + begin + zeropad = (data [width_in-1] ==0) ? 0 : -1; + end + else + begin + zeropad = 0; + end + + fb_int = (sload_int == 1'b1) ? 0 : result_int_wire [width_out-1:0]; + data_int = {zeropad, data}; + + if ((add_sub_int == 1) || (sload_int == 1)) + begin + cin_int = ((sload_int == 1'b1) ? 0 : ((cin === 1'bz) ? 0 : cin)); + temp_sum = fb_int + data_int + cin_int; + cout_int = temp_sum [width_out]; + end + else + begin + cin_int = (cin === 1'bz) ? 1 : cin; + borrow = ~cin_int; + + temp_sum = fb_int - data_int - borrow; + + result_full2 = data_int + borrow; + cout_int = (fb_int >= result_full2) ? 1 : 0; + end + + if ((lpm_representation == "SIGNED") || (sign_data_int == 1)) + begin + a = (data [width_in-1] ~^ fb_int [width_out-1]) ^ (~add_sub_int); + overflow_int = a & (fb_int [width_out-1] ^ temp_sum[width_out-1]); + end + else + begin + overflow_int = (add_sub_int == 1) ? cout_int : ~cout_int; + end + + if (sload_int == 1) + begin + cout_int = !add_sub_int; + overflow_int = 0; + end + + end + + // CONTINOUS ASSIGNMENT + + // Get the input data and control signals. + assign sign_data_int = sign_data; + assign sload_int = sload; + assign add_sub_int = add_sub; + + assign clken_int = clken; + assign aclr_int = aclr; + assign result_int_wire = result_int; + assign temp_sum_wire = temp_sum; + assign cout_int_wire = cout_int; + assign overflow_int_wire = overflow_int; + assign cout = (extra_latency == 0) ? cout_int_wire : cout_delayed_wire; + assign cout_delayed_wire = cout_delayed; + +endmodule // End of altaccumulate + +// END OF MODULE + +//-------------------------------------------------------------------------- +// Module Name : altmult_accum +// +// Description : a*b + x (MAC) +// +// Limitation : Stratix DSP block +// +// Results expected : signed & unsigned, maximum of 3 pipelines(latency) each. +// +//-------------------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +module altmult_accum ( dataa, + datab, + scanina, + scaninb, + sourcea, + sourceb, + accum_sload_upper_data, + addnsub, + accum_sload, + signa, + signb, + clock0, + clock1, + clock2, + clock3, + ena0, + ena1, + ena2, + ena3, + aclr0, + aclr1, + aclr2, + aclr3, + result, + overflow, + scanouta, + scanoutb, + mult_round, + mult_saturation, + accum_round, + accum_saturation, + mult_is_saturated, + accum_is_saturated); + + // --------------------- + // PARAMETER DECLARATION + // --------------------- + parameter width_a = 2; + parameter width_b = 2; + parameter width_result = 5; + parameter input_reg_a = "CLOCK0"; + parameter input_aclr_a = "ACLR3"; + parameter input_reg_b = "CLOCK0"; + parameter input_aclr_b = "ACLR3"; + parameter port_addnsub = "PORT_CONNECTIVITY"; + parameter addnsub_reg = "CLOCK0"; + parameter addnsub_aclr = "ACLR3"; + parameter addnsub_pipeline_reg = "CLOCK0"; + parameter addnsub_pipeline_aclr = "ACLR3"; + parameter accum_direction = "ADD"; + parameter accum_sload_reg = "CLOCK0"; + parameter accum_sload_aclr = "ACLR3"; + parameter accum_sload_pipeline_reg = "CLOCK0"; + parameter accum_sload_pipeline_aclr = "ACLR3"; + parameter representation_a = "UNSIGNED"; + parameter port_signa = "PORT_CONNECTIVITY"; + parameter sign_reg_a = "CLOCK0"; + parameter sign_aclr_a = "ACLR3"; + parameter sign_pipeline_reg_a = "CLOCK0"; + parameter sign_pipeline_aclr_a = "ACLR3"; + parameter port_signb = "PORT_CONNECTIVITY"; + parameter representation_b = "UNSIGNED"; + parameter sign_reg_b = "CLOCK0"; + parameter sign_aclr_b = "ACLR3"; + parameter sign_pipeline_reg_b = "CLOCK0"; + parameter sign_pipeline_aclr_b = "ACLR3"; + parameter multiplier_reg = "CLOCK0"; + parameter multiplier_aclr = "ACLR3"; + parameter output_reg = "CLOCK0"; + parameter output_aclr = "ACLR3"; + parameter lpm_type = "altmult_accum"; + parameter lpm_hint = "UNUSED"; + + parameter extra_multiplier_latency = 0; + parameter extra_accumulator_latency = 0; + parameter dedicated_multiplier_circuitry = "AUTO"; + parameter dsp_block_balancing = "AUTO"; + parameter intended_device_family = "Stratix"; + + // StratixII related parameter + parameter accum_round_aclr = "ACLR3"; + parameter accum_round_pipeline_aclr = "ACLR3"; + parameter accum_round_pipeline_reg = "CLOCK0"; + parameter accum_round_reg = "CLOCK0"; + parameter accum_saturation_aclr = "ACLR3"; + parameter accum_saturation_pipeline_aclr = "ACLR3"; + parameter accum_saturation_pipeline_reg = "CLOCK0"; + parameter accum_saturation_reg = "CLOCK0"; + parameter accum_sload_upper_data_aclr = "ACLR3"; + parameter accum_sload_upper_data_pipeline_aclr = "ACLR3"; + parameter accum_sload_upper_data_pipeline_reg = "CLOCK0"; + parameter accum_sload_upper_data_reg = "CLOCK0"; + parameter mult_round_aclr = "ACLR3"; + parameter mult_round_reg = "CLOCK0"; + parameter mult_saturation_aclr = "ACLR3"; + parameter mult_saturation_reg = "CLOCK0"; + + parameter input_source_a = "DATAA"; + parameter input_source_b = "DATAB"; + parameter width_upper_data = 1; + parameter multiplier_rounding = "NO"; + parameter multiplier_saturation = "NO"; + parameter accumulator_rounding = "NO"; + parameter accumulator_saturation = "NO"; + parameter port_mult_is_saturated = "UNUSED"; + parameter port_accum_is_saturated = "UNUSED"; + + // ----------------------- + // Local parameters + // ----------------------- + parameter int_width_a = ((multiplier_saturation == "NO") && (multiplier_rounding == "NO") && (accumulator_saturation == "NO") && (accumulator_rounding == "NO")) ? width_a : 18; + parameter int_width_b = ((multiplier_saturation == "NO") && (multiplier_rounding == "NO") && (accumulator_saturation == "NO") && (accumulator_rounding == "NO")) ? width_b : 18; + parameter int_width_result = ((multiplier_saturation == "NO") && (multiplier_rounding == "NO") && (accumulator_saturation == "NO") && (accumulator_rounding == "NO")) ? width_result : 52; + parameter int_extra_width = ((multiplier_saturation == "NO") && (multiplier_rounding == "NO") && (accumulator_saturation == "NO") && (accumulator_rounding == "NO")) ? 0 : (int_width_a + int_width_b - width_a - width_b); + parameter diff_width_a = (int_width_a > width_a) ? int_width_a - width_a : 1; + parameter diff_width_b = (int_width_b > width_b) ? int_width_b - width_b : 1; + parameter sat_for_ini = ((multiplier_saturation == "NO") && (accumulator_saturation == "NO")) ? 0 : (int_width_a + int_width_b - 34); + parameter mult_round_for_ini = ((multiplier_rounding == "NO")? 0 : (int_width_a + int_width_b - 18)); + parameter bits_to_round = (((multiplier_rounding == "NO") && (accumulator_rounding == "NO"))? 0 : int_width_a + int_width_b - 18); + parameter sload_for_limit = (width_result < width_upper_data)? width_result + int_extra_width : width_upper_data ; + parameter accum_sat_for_limit = ((accumulator_saturation == "NO")? int_width_result - 1 : int_width_a + int_width_b - 33 ); + // ---------------- + // PORT DECLARATION + // ---------------- + + // data input ports + input [width_a -1 : 0] dataa; + input [width_b -1 : 0] datab; + input [width_a -1 : 0] scanina; + input [width_b -1 : 0] scaninb; + input sourcea; + input sourceb; + input [width_result -1 : width_result - width_upper_data] accum_sload_upper_data; + + // control signals + input addnsub; + input accum_sload; + input signa; + input signb; + + // clock ports + input clock0; + input clock1; + input clock2; + input clock3; + + // clock enable ports + input ena0; + input ena1; + input ena2; + input ena3; + + // clear ports + input aclr0; + input aclr1; + input aclr2; + input aclr3; + + // round and saturate ports + input mult_round; + input mult_saturation; + input accum_round; + input accum_saturation; + + // output ports + output [width_result -1 : 0] result; + output overflow; + output [width_a -1 : 0] scanouta; + output [width_b -1 : 0] scanoutb; + + output mult_is_saturated; + output accum_is_saturated; + + + // --------------- + // REG DECLARATION + // --------------- + reg [width_result -1 : 0] result; + + reg [int_width_result -1 : 0] mult_res_out; + reg [int_width_result : 0] temp_sum; + + + reg [width_result + 1 : 0] result_pipe [extra_accumulator_latency : 0]; + reg [width_result + 1 : 0] result_full ; + + reg [int_width_result - 1 : 0] result_int; + + reg [int_width_a - 1 : 0] mult_a_reg; + reg [int_width_a - 1 : 0] mult_a_int; + reg [int_width_a + int_width_b - 1 : 0] mult_res; + reg [int_width_a + int_width_b - 1 : 0] temp_mult_1; + reg [int_width_a + int_width_b - 1 : 0] temp_mult; + + + reg [int_width_b -1 :0] mult_b_reg; + reg [int_width_b -1 :0] mult_b_int; + + reg [5 + int_width_a + int_width_b + width_upper_data : 0] mult_pipe [extra_multiplier_latency:0]; + reg [5 + int_width_a + int_width_b + width_upper_data : 0] mult_full; + + reg [width_upper_data - 1 : 0] sload_upper_data_reg; + + reg [width_result - width_upper_data -1 + 4 : 0] lower_bits; + + reg mult_signed_out; + reg [width_upper_data - 1 : 0] sload_upper_data_pipe_reg; + + + reg zero_acc_reg; + reg zero_acc_pipe_reg; + reg sign_a_reg; + reg sign_a_pipe_reg; + reg sign_b_reg; + reg sign_b_pipe_reg; + reg addsub_reg; + reg addsub_pipe_reg; + + reg mult_signed; + reg temp_mult_signed; + reg neg_a; + reg neg_b; + + reg overflow_int; + reg cout_int; + reg overflow_tmp_int; + + reg overflow; + + reg [int_width_a + int_width_b -1 : 0] mult_round_out; + reg mult_saturate_overflow; + reg [int_width_a + int_width_b -1 : 0] mult_saturate_out; + reg [int_width_a + int_width_b -1 : 0] mult_result; + reg [int_width_a + int_width_b -1 : 0] mult_final_out; + + reg [int_width_result -1 : 0] accum_round_out; + reg accum_saturate_overflow; + reg [int_width_result -1 : 0] accum_saturate_out; + reg [int_width_result -1 : 0] accum_result; + reg [int_width_result -1 : 0] accum_final_out; + + tri0 mult_is_saturated_latent; + reg mult_is_saturated_int; + reg mult_is_saturated_reg; + + reg accum_is_saturated_latent; + reg [extra_accumulator_latency : 0] accum_saturate_pipe; + reg [extra_accumulator_latency : 0] mult_is_saturated_pipe; + + reg mult_round_tmp; + reg mult_saturation_tmp; + reg accum_round_tmp1; + reg accum_round_tmp2; + reg accum_saturation_tmp1; + reg accum_saturation_tmp2; + + reg [int_width_result - int_width_a - int_width_b + 2 - 1 : 0] accum_result_sign_bits; + + // ------------------- + // INTEGER DECLARATION + // ------------------- + integer head_result; + integer i; + integer i2; + integer i3; + integer i4; + integer head_mult; + integer flag; + + + //----------------- + // TRI DECLARATION + //----------------- + + + // Tri wire for clear signal + + tri0 input_a_wire_clr; + tri0 input_b_wire_clr; + + tri0 addsub_wire_clr; + tri0 addsub_pipe_wire_clr; + + tri0 zero_wire_clr; + tri0 zero_pipe_wire_clr; + + tri0 sign_a_wire_clr; + tri0 sign_pipe_a_wire_clr; + + tri0 sign_b_wire_clr; + tri0 sign_pipe_b_wire_clr; + + tri0 multiplier_wire_clr; + tri0 mult_pipe_wire_clr; + + tri0 output_wire_clr; + + tri0 mult_round_wire_clr; + tri0 mult_saturation_wire_clr; + + tri0 accum_round_wire_clr; + tri0 accum_round_pipe_wire_clr; + + tri0 accum_saturation_wire_clr; + tri0 accum_saturation_pipe_wire_clr; + + tri0 accum_sload_upper_data_wire_clr; + tri0 accum_sload_upper_data_pipe_wire_clr; + + + // Tri wire for enable signal + + tri1 input_a_wire_en; + tri1 input_b_wire_en; + + tri1 addsub_wire_en; + tri1 addsub_pipe_wire_en; + + tri1 zero_wire_en; + tri1 zero_pipe_wire_en; + + tri1 sign_a_wire_en; + tri1 sign_pipe_a_wire_en; + + tri1 sign_b_wire_en; + tri1 sign_pipe_b_wire_en; + + tri1 multiplier_wire_en; + tri1 mult_pipe_wire_en; + + tri1 output_wire_en; + + tri1 mult_round_wire_en; + tri1 mult_saturation_wire_en; + + tri1 accum_round_wire_en; + tri1 accum_round_pipe_wire_en; + + tri1 accum_saturation_wire_en; + tri1 accum_saturation_pipe_wire_en; + + tri1 accum_sload_upper_data_wire_en; + tri1 accum_sload_upper_data_pipe_wire_en; + + // ------------------------ + // SUPPLY WIRE DECLARATION + // ------------------------ + + supply0 [int_width_a + int_width_b - 1 : 0] temp_mult_zero; + + + // ---------------- + // WIRE DECLARATION + // ---------------- + + // Wire for Clock signals + + wire input_a_wire_clk; + wire input_b_wire_clk; + + wire addsub_wire_clk; + wire addsub_pipe_wire_clk; + + wire zero_wire_clk; + wire zero_pipe_wire_clk; + + wire sign_a_wire_clk; + wire sign_pipe_a_wire_clk; + + wire sign_b_wire_clk; + wire sign_pipe_b_wire_clk; + + wire multiplier_wire_clk; + wire mult_pipe_wire_clk; + + wire output_wire_clk; + + wire [width_a -1 : 0] scanouta; + wire [int_width_a + int_width_b -1 : 0] mult_out_latent; + wire [width_b -1 : 0] scanoutb; + + wire addsub_int; + wire sign_a_int; + wire sign_b_int; + + wire zero_acc_int; + wire sign_a_reg_int; + wire sign_b_reg_int; + + wire addsub_latent; + wire zeroacc_latent; + wire signa_latent; + wire signb_latent; + wire mult_signed_latent; + + wire [width_upper_data - 1 : 0] sload_upper_data_latent; + reg [int_width_result - 1 : 0] sload_upper_data_pipe_wire; + + wire [int_width_a -1 :0] mult_a_wire; + wire [int_width_b -1 :0] mult_b_wire; + wire [width_upper_data - 1 : 0] sload_upper_data_wire; + wire [int_width_a -1 : 0] mult_a_tmp; + wire [int_width_b -1 : 0] mult_b_tmp; + + wire zero_acc_wire; + wire zero_acc_pipe_wire; + + wire sign_a_wire; + wire sign_a_pipe_wire; + wire sign_b_wire; + wire sign_b_pipe_wire; + + wire addsub_wire; + wire addsub_pipe_wire; + + wire mult_round_int; + wire mult_round_wire_clk; + wire mult_saturation_int; + wire mult_saturation_wire_clk; + + wire accum_round_tmp1_wire; + wire accum_round_wire_clk; + wire accum_round_int; + wire accum_round_pipe_wire_clk; + + wire accum_saturation_tmp1_wire; + wire accum_saturation_wire_clk; + wire accum_saturation_int; + wire accum_saturation_pipe_wire_clk; + + wire accum_sload_upper_data_wire_clk; + wire accum_sload_upper_data_pipe_wire_clk; + wire [width_result -1 : width_result - width_upper_data] accum_sload_upper_data_int; + + tri0 mult_is_saturated_wire; + + // ------------------------ + // COMPONENT INSTANTIATIONS + // ------------------------ + ALTERA_DEVICE_FAMILIES dev (); + + + // -------------------- + // ASSIGNMENT STATEMENTS + // -------------------- + + + assign addsub_int = (port_addnsub == "PORT_USED") ? addsub_pipe_wire : + (port_addnsub == "PORT_UNUSED") ? ((accum_direction == "ADD") ? 1 : 0) : + ((addnsub ===1'bz) || + (addsub_wire_clk ===1'bz) || + (addsub_pipe_wire_clk ===1'bz)) ? + ((accum_direction == "ADD") ? 1 : 0) : addsub_pipe_wire; + + assign sign_a_int = (port_signa == "PORT_USED") ? sign_a_pipe_wire : + (port_signa == "PORT_UNUSED") ? ((representation_a == "SIGNED") ? 1 : 0) : + ((signa ===1'bz) || + (sign_a_wire_clk ===1'bz) || + (sign_pipe_a_wire_clk ===1'bz)) ? + ((representation_a == "SIGNED") ? 1 : 0) : sign_a_pipe_wire; + + assign sign_b_int = (port_signb == "PORT_USED") ? sign_b_pipe_wire : + (port_signb == "PORT_UNUSED") ? ((representation_b == "SIGNED") ? 1 : 0) : + ((signb ===1'bz) || + (sign_b_wire_clk ===1'bz) || + (sign_pipe_b_wire_clk ===1'bz)) ? + ((representation_b == "SIGNED") ? 1 : 0) : sign_b_pipe_wire; + + + + assign sign_a_reg_int = (port_signa == "PORT_USED") ? sign_a_wire : + (port_signa == "PORT_UNUSED") ? ((representation_a == "SIGNED") ? 1 : 0) : + ((signa ===1'bz) || + (sign_a_wire_clk ===1'bz) || + (sign_pipe_a_wire_clk ===1'bz)) ? + ((representation_a == "SIGNED") ? 1 : 0) : sign_a_wire; + + assign sign_b_reg_int = (port_signb == "PORT_USED") ? sign_b_wire : + (port_signb == "PORT_UNUSED") ? ((representation_b == "SIGNED") ? 1 : 0) : + ((signb ===1'bz) || + (sign_b_wire_clk ===1'bz) || + (sign_pipe_b_wire_clk ===1'bz)) ? + ((representation_b == "SIGNED") ? 1 : 0) : sign_b_wire; + + assign zero_acc_int = ((accum_sload ===1'bz) || + (zero_wire_clk===1'bz) || + (zero_pipe_wire_clk===1'bz)) ? + 0 : zero_acc_pipe_wire; + + assign accum_sload_upper_data_int = ((accum_sload_upper_data === {width_upper_data{1'bz}}) || + (accum_sload_upper_data_wire_clk === 1'bz) || + (accum_sload_upper_data_pipe_wire_clk === 1'bz)) ? + {width_upper_data{1'b0}} : accum_sload_upper_data; + + assign scanouta = mult_a_wire[int_width_a - 1 : int_width_a - width_a]; + assign scanoutb = mult_b_wire[int_width_b - 1 : int_width_b - width_b]; + + assign {addsub_latent, zeroacc_latent, signa_latent, signb_latent, mult_signed_latent, mult_out_latent, sload_upper_data_latent, mult_is_saturated_latent} = (extra_multiplier_latency > 0) ? + mult_full : {addsub_wire, zero_acc_wire, sign_a_wire, sign_b_wire, temp_mult_signed, mult_final_out, sload_upper_data_wire, mult_saturate_overflow}; + + assign mult_is_saturated = (port_mult_is_saturated != "UNUSED") ? mult_is_saturated_int : 0; + assign accum_is_saturated = (port_accum_is_saturated != "UNUSED") ? accum_is_saturated_latent : 0; + + + // --------------------------------------------------------------------------------- + // Initialization block where all the internal signals and registers are initialized + // --------------------------------------------------------------------------------- + initial + begin + + // Checking for invalid parameters, in case Wizard is bypassed (hand-modified). + + if ((dedicated_multiplier_circuitry != "AUTO") && + (dedicated_multiplier_circuitry != "YES") && + (dedicated_multiplier_circuitry != "NO")) + begin + $display("Error: The DEDICATED_MULTIPLIER_CIRCUITRY parameter is set to an illegal value."); + $stop; + end + if (width_a <= 0) + begin + $display("Error: width_a must be greater than 0."); + $stop; + end + if (width_b <= 0) + begin + $display("Error: width_b must be greater than 0."); + $stop; + end + if (width_result <= 0) + begin + $display("Error: width_result must be greater than 0."); + $stop; + end + + if (( (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && + (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) ) + && (input_source_a != "DATAA")) + begin + $display("Error: The input source for port A are limited to input dataa."); + $stop; + end + + if (( (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && + (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) ) + && (input_source_b != "DATAB")) + begin + $display("Error: The input source for port B are limited to input datab."); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (multiplier_rounding != "NO")) + begin + $display("Error: There is no rounding feature for %s device.", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (accumulator_rounding != "NO")) + begin + $display("Error: There is no rounding feature for %s device.", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (multiplier_saturation != "NO")) + begin + $display("Error: There is no saturation feature for %s device.", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (accumulator_saturation != "NO")) + begin + $display("Error: There is no saturation feature for %s device.", intended_device_family); + $stop; + end + + + temp_sum = 0; + head_result = 0; + head_mult = 0; + overflow_int = 0; + mult_a_reg = 0; + mult_b_reg = 0; + flag = 0; + + zero_acc_reg = 0; + zero_acc_pipe_reg = 0; + sload_upper_data_reg = 0; + lower_bits = 0; + sload_upper_data_pipe_reg = 0; + + sign_a_reg = (signa ===1'bz) ? ((representation_a == "SIGNED") ? 1 : 0) : 0; + sign_a_pipe_reg = (signa ===1'bz) ? ((representation_a == "SIGNED") ? 1 : 0) : 0; + sign_b_reg = (signb ===1'bz) ? ((representation_b == "SIGNED") ? 1 : 0) : 0; + sign_b_pipe_reg = (signb ===1'bz) ? ((representation_b == "SIGNED") ? 1 : 0) : 0; + addsub_reg = (addnsub ===1'bz) ? ((accum_direction == "ADD") ? 1 : 0) : 0; + addsub_pipe_reg = (addnsub ===1'bz) ? ((accum_direction == "ADD") ? 1 : 0) : 0; + + result_int = 0; + result = 0; + overflow = 0; + mult_full = 0; + mult_res_out = 0; + mult_signed_out = 0; + mult_res = 0; + + mult_is_saturated_int = 0; + mult_is_saturated_reg = 0; + mult_saturation_tmp = 0; + mult_saturate_overflow = 0; + + accum_result = 0; + accum_saturate_overflow = 0; + accum_is_saturated_latent = 0; + + for (i=0; i<=extra_accumulator_latency; i=i+1) + begin + result_pipe [i] = 0; + accum_saturate_pipe[i] = 0; + mult_is_saturated_pipe[i] = 0; + end + + for (i=0; i<= extra_multiplier_latency; i=i+1) + begin + mult_pipe [i] = 0; + end + + end + + + // --------------------------------------------------------- + // This block updates the internal clock signals accordingly + // every time the global clock signal changes state + // --------------------------------------------------------- + + assign input_a_wire_clk = (input_reg_a == "CLOCK0")? clock0: + (input_reg_a == "UNREGISTERED")? 0: + (input_reg_a == "CLOCK1")? clock1: + (input_reg_a == "CLOCK2")? clock2: + (input_reg_a == "CLOCK3")? clock3:0; + + assign input_b_wire_clk = (input_reg_b == "CLOCK0")? clock0: + (input_reg_b == "UNREGISTERED")? 0: + (input_reg_b == "CLOCK1")? clock1: + (input_reg_b == "CLOCK2")? clock2: + (input_reg_b == "CLOCK3")? clock3:0; + + + assign addsub_wire_clk = (addnsub_reg == "CLOCK0")? clock0: + (addnsub_reg == "UNREGISTERED")? 0: + (addnsub_reg == "CLOCK1")? clock1: + (addnsub_reg == "CLOCK2")? clock2: + (addnsub_reg == "CLOCK3")? clock3:0; + + + assign addsub_pipe_wire_clk = (addnsub_pipeline_reg == "CLOCK0")? clock0: + (addnsub_pipeline_reg == "UNREGISTERED")? 0: + (addnsub_pipeline_reg == "CLOCK1")? clock1: + (addnsub_pipeline_reg == "CLOCK2")? clock2: + (addnsub_pipeline_reg == "CLOCK3")? clock3:0; + + + assign zero_wire_clk = (accum_sload_reg == "CLOCK0")? clock0: + (accum_sload_reg == "UNREGISTERED")? 0: + (accum_sload_reg == "CLOCK1")? clock1: + (accum_sload_reg == "CLOCK2")? clock2: + (accum_sload_reg == "CLOCK3")? clock3:0; + + assign accum_sload_upper_data_wire_clk = (accum_sload_upper_data_reg == "CLOCK0")? clock0: + (accum_sload_upper_data_reg == "UNREGISTERED")? 0: + (accum_sload_upper_data_reg == "CLOCK1")? clock1: + (accum_sload_upper_data_reg == "CLOCK2")? clock2: + (accum_sload_upper_data_reg == "CLOCK3")? clock3:0; + + assign zero_pipe_wire_clk = (accum_sload_pipeline_reg == "CLOCK0")? clock0: + (accum_sload_pipeline_reg == "UNREGISTERED")? 0: + (accum_sload_pipeline_reg == "CLOCK1")? clock1: + (accum_sload_pipeline_reg == "CLOCK2")? clock2: + (accum_sload_pipeline_reg == "CLOCK3")? clock3:0; + + assign accum_sload_upper_data_pipe_wire_clk = (accum_sload_upper_data_pipeline_reg == "CLOCK0")? clock0: + (accum_sload_upper_data_pipeline_reg == "UNREGISTERED")? 0: + (accum_sload_upper_data_pipeline_reg == "CLOCK1")? clock1: + (accum_sload_upper_data_pipeline_reg == "CLOCK2")? clock2: + (accum_sload_upper_data_pipeline_reg == "CLOCK3")? clock3:0; + + assign sign_a_wire_clk =(sign_reg_a == "CLOCK0")? clock0: + (sign_reg_a == "UNREGISTERED")? 0: + (sign_reg_a == "CLOCK1")? clock1: + (sign_reg_a == "CLOCK2")? clock2: + (sign_reg_a == "CLOCK3")? clock3:0; + + + assign sign_b_wire_clk =(sign_reg_b == "CLOCK0")? clock0: + (sign_reg_b == "UNREGISTERED")? 0: + (sign_reg_b == "CLOCK1")? clock1: + (sign_reg_b == "CLOCK2")? clock2: + (sign_reg_b == "CLOCK3")? clock3:0; + + + + assign sign_pipe_a_wire_clk = (sign_pipeline_reg_a == "CLOCK0")? clock0: + (sign_pipeline_reg_a == "UNREGISTERED")? 0: + (sign_pipeline_reg_a == "CLOCK1")? clock1: + (sign_pipeline_reg_a == "CLOCK2")? clock2: + (sign_pipeline_reg_a == "CLOCK3")? clock3:0; + + + assign sign_pipe_b_wire_clk = (sign_pipeline_reg_b == "CLOCK0")? clock0: + (sign_pipeline_reg_b == "UNREGISTERED")? 0: + (sign_pipeline_reg_b == "CLOCK1")? clock1: + (sign_pipeline_reg_b == "CLOCK2")? clock2: + (sign_pipeline_reg_b == "CLOCK3")? clock3:0; + + + assign multiplier_wire_clk =(multiplier_reg == "CLOCK0")? clock0: + (multiplier_reg == "UNREGISTERED")? 0: + (multiplier_reg == "CLOCK1")? clock1: + (multiplier_reg == "CLOCK2")? clock2: + (multiplier_reg == "CLOCK3")? clock3:0; + + assign output_wire_clk = (output_reg == "CLOCK0")? clock0: + (output_reg == "UNREGISTERED")? 0: + (output_reg == "CLOCK1")? clock1: + (output_reg == "CLOCK2")? clock2: + (output_reg == "CLOCK3")? clock3:0; + + + assign mult_pipe_wire_clk = (multiplier_reg == "UNREGISTERED")? clock0: + multiplier_wire_clk; + + assign mult_round_wire_clk =(mult_round_reg == "CLOCK0")? clock0: + (mult_round_reg == "UNREGISTERED")? 0: + (mult_round_reg == "CLOCK1")? clock1: + (mult_round_reg == "CLOCK2")? clock2: + (mult_round_reg == "CLOCK3")? clock3:0; + + assign mult_saturation_wire_clk = (mult_saturation_reg == "CLOCK0")? clock0: + (mult_saturation_reg == "UNREGISTERED")? 0: + (mult_saturation_reg == "CLOCK1")? clock1: + (mult_saturation_reg == "CLOCK2")? clock2: + (mult_saturation_reg == "CLOCK3")? clock3:0; + + assign accum_round_wire_clk = (accum_round_reg == "CLOCK0")? clock0: + (accum_round_reg == "UNREGISTERED")? 0: + (accum_round_reg == "CLOCK1")? clock1: + (accum_round_reg == "CLOCK2")? clock2: + (accum_round_reg == "CLOCK3")? clock3:0; + + assign accum_round_pipe_wire_clk = (accum_round_pipeline_reg == "CLOCK0")? clock0: + (accum_round_pipeline_reg == "UNREGISTERED")? 0: + (accum_round_pipeline_reg == "CLOCK1")? clock1: + (accum_round_pipeline_reg == "CLOCK2")? clock2: + (accum_round_pipeline_reg == "CLOCK3")? clock3:0; + + assign accum_saturation_wire_clk = (accum_saturation_reg == "CLOCK0")? clock0: + (accum_saturation_reg == "UNREGISTERED")? 0: + (accum_saturation_reg == "CLOCK1")? clock1: + (accum_saturation_reg == "CLOCK2")? clock2: + (accum_saturation_reg == "CLOCK3")? clock3:0; + + assign accum_saturation_pipe_wire_clk = (accum_saturation_pipeline_reg == "CLOCK0")? clock0: + (accum_saturation_pipeline_reg == "UNREGISTERED")? 0: + (accum_saturation_pipeline_reg == "CLOCK1")? clock1: + (accum_saturation_pipeline_reg == "CLOCK2")? clock2: + (accum_saturation_pipeline_reg == "CLOCK3")? clock3:0; + + + // ---------------------------------------------------------------- + // This block updates the internal clock enable signals accordingly + // every time the global clock enable signal changes state + // ---------------------------------------------------------------- + + + + assign input_a_wire_en =(input_reg_a == "CLOCK0")? ena0: + (input_reg_a == "UNREGISTERED")? 1: + (input_reg_a == "CLOCK1")? ena1: + (input_reg_a == "CLOCK2")? ena2: + (input_reg_a == "CLOCK3")? ena3:1; + + assign input_b_wire_en =(input_reg_b == "CLOCK0")? ena0: + (input_reg_b == "UNREGISTERED")? 1: + (input_reg_b == "CLOCK1")? ena1: + (input_reg_b == "CLOCK2")? ena2: + (input_reg_b == "CLOCK3")? ena3:1; + + + assign addsub_wire_en = (addnsub_reg == "CLOCK0")? ena0: + (addnsub_reg == "UNREGISTERED")? 1: + (addnsub_reg == "CLOCK1")? ena1: + (addnsub_reg == "CLOCK2")? ena2: + (addnsub_reg == "CLOCK3")? ena3:1; + + + assign addsub_pipe_wire_en =(addnsub_pipeline_reg == "CLOCK0")? ena0: + (addnsub_pipeline_reg == "UNREGISTERED")? 1: + (addnsub_pipeline_reg == "CLOCK1")? ena1: + (addnsub_pipeline_reg == "CLOCK2")? ena2: + (addnsub_pipeline_reg == "CLOCK3")? ena3:1; + + + assign zero_wire_en = (accum_sload_reg == "CLOCK0")? ena0: + (accum_sload_reg == "UNREGISTERED")? 1: + (accum_sload_reg == "CLOCK1")? ena1: + (accum_sload_reg == "CLOCK2")? ena2: + (accum_sload_reg == "CLOCK3")? ena3:1; + + assign accum_sload_upper_data_wire_en = (accum_sload_upper_data_reg == "CLOCK0")? ena0: + (accum_sload_upper_data_reg == "UNREGISTERED")? 1: + (accum_sload_upper_data_reg == "CLOCK1")? ena1: + (accum_sload_upper_data_reg == "CLOCK2")? ena2: + (accum_sload_upper_data_reg == "CLOCK3")? ena3:1; + + assign zero_pipe_wire_en = (accum_sload_pipeline_reg == "CLOCK0")? ena0: + (accum_sload_pipeline_reg == "UNREGISTERED")? 1: + (accum_sload_pipeline_reg == "CLOCK1")? ena1: + (accum_sload_pipeline_reg == "CLOCK2")? ena2: + (accum_sload_pipeline_reg == "CLOCK3")? ena3:1; + + assign accum_sload_upper_data_pipe_wire_en = (accum_sload_upper_data_pipeline_reg == "CLOCK0")? ena0: + (accum_sload_upper_data_pipeline_reg == "UNREGISTERED")? 1: + (accum_sload_upper_data_pipeline_reg == "CLOCK1")? ena1: + (accum_sload_upper_data_pipeline_reg == "CLOCK2")? ena2: + (accum_sload_upper_data_pipeline_reg == "CLOCK3")? ena3:1; + + assign sign_a_wire_en = (sign_reg_a == "CLOCK0")? ena0: + (sign_reg_a == "UNREGISTERED")? 1: + (sign_reg_a == "CLOCK1")? ena1: + (sign_reg_a == "CLOCK2")? ena2: + (sign_reg_a == "CLOCK3")? ena3:1; + + + assign sign_b_wire_en = (sign_reg_b == "CLOCK0")? ena0: + (sign_reg_b == "UNREGISTERED")? 1: + (sign_reg_b == "CLOCK1")? ena1: + (sign_reg_b == "CLOCK2")? ena2: + (sign_reg_b == "CLOCK3")? ena3:1; + + + + assign sign_pipe_a_wire_en = (sign_pipeline_reg_a == "CLOCK0")? ena0: + (sign_pipeline_reg_a == "UNREGISTERED")? 1: + (sign_pipeline_reg_a == "CLOCK1")? ena1: + (sign_pipeline_reg_a == "CLOCK2")? ena2: + (sign_pipeline_reg_a == "CLOCK3")? ena3:1; + + + assign sign_pipe_b_wire_en = (sign_pipeline_reg_b == "CLOCK0")? ena0: + (sign_pipeline_reg_b == "UNREGISTERED")? 1: + (sign_pipeline_reg_b == "CLOCK1")? ena1: + (sign_pipeline_reg_b == "CLOCK2")? ena2: + (sign_pipeline_reg_b == "CLOCK3")? ena3:1; + + + assign multiplier_wire_en = (multiplier_reg == "CLOCK0")? ena0: + (multiplier_reg == "UNREGISTERED")? 1: + (multiplier_reg == "CLOCK1")? ena1: + (multiplier_reg == "CLOCK2")? ena2: + (multiplier_reg == "CLOCK3")? ena3:1; + + assign output_wire_en = (output_reg == "CLOCK0")? ena0: + (output_reg == "UNREGISTERED")? 1: + (output_reg == "CLOCK1")? ena1: + (output_reg == "CLOCK2")? ena2: + (output_reg == "CLOCK3")? ena3:1; + + + assign mult_pipe_wire_en = (multiplier_reg == "UNREGISTERED")? ena0: + multiplier_wire_en; + + + assign mult_round_wire_en = (mult_round_reg == "CLOCK0")? ena0: + (mult_round_reg == "UNREGISTERED")? 1: + (mult_round_reg == "CLOCK1")? ena1: + (mult_round_reg == "CLOCK2")? ena2: + (mult_round_reg == "CLOCK3")? ena3:1; + + + assign mult_saturation_wire_en = (mult_saturation_reg == "CLOCK0")? ena0: + (mult_saturation_reg == "UNREGISTERED")? 1: + (mult_saturation_reg == "CLOCK1")? ena1: + (mult_saturation_reg == "CLOCK2")? ena2: + (mult_saturation_reg == "CLOCK3")? ena3:1; + + assign accum_round_wire_en = (accum_round_reg == "CLOCK0")? ena0: + (accum_round_reg == "UNREGISTERED")? 1: + (accum_round_reg == "CLOCK1")? ena1: + (accum_round_reg == "CLOCK2")? ena2: + (accum_round_reg == "CLOCK3")? ena3:1; + + assign accum_round_pipe_wire_en = (accum_round_pipeline_reg == "CLOCK0")? ena0: + (accum_round_pipeline_reg == "UNREGISTERED")? 1: + (accum_round_pipeline_reg == "CLOCK1")? ena1: + (accum_round_pipeline_reg == "CLOCK2")? ena2: + (accum_round_pipeline_reg == "CLOCK3")? ena3:1; + + assign accum_saturation_wire_en = (accum_saturation_reg == "CLOCK0")? ena0: + (accum_saturation_reg == "UNREGISTERED")? 1: + (accum_saturation_reg == "CLOCK1")? ena1: + (accum_saturation_reg == "CLOCK2")? ena2: + (accum_saturation_reg == "CLOCK3")? ena3:1; + + assign accum_saturation_pipe_wire_en = (accum_saturation_pipeline_reg == "CLOCK0")? ena0: + (accum_saturation_pipeline_reg == "UNREGISTERED")? 1: + (accum_saturation_pipeline_reg == "CLOCK1")? ena1: + (accum_saturation_pipeline_reg == "CLOCK2")? ena2: + (accum_saturation_pipeline_reg == "CLOCK3")? ena3:1; + + // --------------------------------------------------------- + // This block updates the internal clear signals accordingly + // every time the global clear signal changes state + // --------------------------------------------------------- + + assign input_a_wire_clr =(input_aclr_a == "ACLR3")? aclr3: + (input_aclr_a == "UNUSED")? 0: + (input_aclr_a == "ACLR0")? aclr0: + (input_aclr_a == "ACLR1")? aclr1: + (input_aclr_a == "ACLR2")? aclr2: 0; + + assign input_b_wire_clr = (input_aclr_b == "ACLR3")? aclr3: + (input_aclr_b == "UNUSED")? 0: + (input_aclr_b == "ACLR0")? aclr0: + (input_aclr_b == "ACLR1")? aclr1: + (input_aclr_b == "ACLR2")? aclr2: 0; + + + assign addsub_wire_clr =(addnsub_aclr == "ACLR3")? aclr3: + (addnsub_aclr == "UNUSED")? 0: + (addnsub_aclr == "ACLR0")? aclr0: + (addnsub_aclr == "ACLR1")? aclr1: + (addnsub_aclr == "ACLR2")? aclr2: 0; + + + assign addsub_pipe_wire_clr = (addnsub_pipeline_aclr == "ACLR3")? aclr3: + (addnsub_pipeline_aclr == "UNUSED")? 0: + (addnsub_pipeline_aclr == "ACLR0")? aclr0: + (addnsub_pipeline_aclr == "ACLR1")? aclr1: + (addnsub_pipeline_aclr == "ACLR2")? aclr2: 0; + + + assign zero_wire_clr = (accum_sload_aclr == "ACLR3")? aclr3: + (accum_sload_aclr == "UNUSED")? 0: + (accum_sload_aclr == "ACLR0")? aclr0: + (accum_sload_aclr == "ACLR1")? aclr1: + (accum_sload_aclr == "ACLR2")? aclr2: 0; + + assign accum_sload_upper_data_wire_clr = (accum_sload_upper_data_aclr == "ACLR3")? aclr3: + (accum_sload_upper_data_aclr == "UNUSED")? 0: + (accum_sload_upper_data_aclr == "ACLR0")? aclr0: + (accum_sload_upper_data_aclr == "ACLR1")? aclr1: + (accum_sload_upper_data_aclr == "ACLR2")? aclr2: 0; + + assign zero_pipe_wire_clr = (accum_sload_pipeline_aclr == "ACLR3")? aclr3: + (accum_sload_pipeline_aclr == "UNUSED")? 0: + (accum_sload_pipeline_aclr == "ACLR0")? aclr0: + (accum_sload_pipeline_aclr == "ACLR1")? aclr1: + (accum_sload_pipeline_aclr == "ACLR2")? aclr2: 0; + + assign accum_sload_upper_data_pipe_wire_clr = (accum_sload_upper_data_pipeline_aclr == "ACLR3")? aclr3: + (accum_sload_upper_data_pipeline_aclr == "UNUSED")? 0: + (accum_sload_upper_data_pipeline_aclr == "ACLR0")? aclr0: + (accum_sload_upper_data_pipeline_aclr == "ACLR1")? aclr1: + (accum_sload_upper_data_pipeline_aclr == "ACLR2")? aclr2: 0; + + assign sign_a_wire_clr =(sign_aclr_a == "ACLR3")? aclr3: + (sign_aclr_a == "UNUSED")? 0: + (sign_aclr_a == "ACLR0")? aclr0: + (sign_aclr_a == "ACLR1")? aclr1: + (sign_aclr_a == "ACLR2")? aclr2: 0; + + + assign sign_b_wire_clr = (sign_aclr_b == "ACLR3")? aclr3: + (sign_aclr_b == "UNUSED")? 0: + (sign_aclr_b == "ACLR0")? aclr0: + (sign_aclr_b == "ACLR1")? aclr1: + (sign_aclr_b == "ACLR2")? aclr2: 0; + + + + + assign sign_pipe_a_wire_clr = (sign_pipeline_aclr_a == "ACLR3")? aclr3: + (sign_pipeline_aclr_a == "UNUSED")? 0: + (sign_pipeline_aclr_a == "ACLR0")? aclr0: + (sign_pipeline_aclr_a == "ACLR1")? aclr1: + (sign_pipeline_aclr_a == "ACLR2")? aclr2: 0; + + + assign sign_pipe_b_wire_clr = (sign_pipeline_aclr_b == "ACLR3")? aclr3: + (sign_pipeline_aclr_b == "UNUSED")? 0: + (sign_pipeline_aclr_b == "ACLR0")? aclr0: + (sign_pipeline_aclr_b == "ACLR1")? aclr1: + (sign_pipeline_aclr_b == "ACLR2")? aclr2: 0; + + + assign multiplier_wire_clr = (multiplier_aclr == "ACLR3")? aclr3: + (multiplier_aclr == "UNUSED")? 0: + (multiplier_aclr == "ACLR0")? aclr0: + (multiplier_aclr == "ACLR1")? aclr1: + (multiplier_aclr == "ACLR2")? aclr2: 0; + + assign output_wire_clr =(output_aclr == "ACLR3")? aclr3: + (output_aclr == "UNUSED")? 0: + (output_aclr == "ACLR0")? aclr0: + (output_aclr == "ACLR1")? aclr1: + (output_aclr == "ACLR2")? aclr2: 0; + + + assign mult_pipe_wire_clr = (multiplier_reg == "UNREGISTERED")? aclr0: + multiplier_wire_clr; + + assign mult_round_wire_clr = (mult_round_aclr == "ACLR3")? aclr3: + (mult_round_aclr == "UNUSED")? 0: + (mult_round_aclr == "ACLR0")? aclr0: + (mult_round_aclr == "ACLR1")? aclr1: + (mult_round_aclr == "ACLR2")? aclr2: 0; + + assign mult_saturation_wire_clr = (mult_saturation_aclr == "ACLR3")? aclr3: + (mult_saturation_aclr == "UNUSED")? 0: + (mult_saturation_aclr == "ACLR0")? aclr0: + (mult_saturation_aclr == "ACLR1")? aclr1: + (mult_saturation_aclr == "ACLR2")? aclr2: 0; + + assign accum_round_wire_clr = (accum_round_aclr == "ACLR3")? aclr3: + (accum_round_aclr == "UNUSED")? 0: + (accum_round_aclr == "ACLR0")? aclr0: + (accum_round_aclr == "ACLR1")? aclr1: + (accum_round_aclr == "ACLR2")? aclr2: 0; + + assign accum_round_pipe_wire_clr = (accum_round_pipeline_aclr == "ACLR3")? aclr3: + (accum_round_pipeline_aclr == "UNUSED")? 0: + (accum_round_pipeline_aclr == "ACLR0")? aclr0: + (accum_round_pipeline_aclr == "ACLR1")? aclr1: + (accum_round_pipeline_aclr == "ACLR2")? aclr2: 0; + + assign accum_saturation_wire_clr = (accum_saturation_aclr == "ACLR3")? aclr3: + (accum_saturation_aclr == "UNUSED")? 0: + (accum_saturation_aclr == "ACLR0")? aclr0: + (accum_saturation_aclr == "ACLR1")? aclr1: + (accum_saturation_aclr == "ACLR2")? aclr2: 0; + + assign accum_saturation_pipe_wire_clr = (accum_saturation_pipeline_aclr == "ACLR3")? aclr3: + (accum_saturation_pipeline_aclr == "UNUSED")? 0: + (accum_saturation_pipeline_aclr == "ACLR0")? aclr0: + (accum_saturation_pipeline_aclr == "ACLR1")? aclr1: + (accum_saturation_pipeline_aclr == "ACLR2")? aclr2: 0; + + // ------------------------------------------------------------------------ + // This block contains 1 register and 1 combinatorial block (to set mult_a) + // Signal Registered : dataa + // + // Register is controlled by posedge input_wire_a_clk + // Register has an asynchronous clear signal, input_reg_a_wire_clr + // NOTE : The combinatorial block will be executed if + // input_reg_a is unregistered and dataa changes value + // ------------------------------------------------------------------------ + assign mult_a_wire = (input_reg_a == "UNREGISTERED")? mult_a_tmp : mult_a_reg; + + assign mult_a_tmp = (int_width_a == width_a) ? ((input_source_a == "DATAA")? dataa : + (input_source_a == "SCANA")? scanina : + (sourcea == 1)? scanina : dataa) + : ((input_source_a == "DATAA")? {dataa, {(diff_width_a){1'b0}}} : + (input_source_a == "SCANA")? {scanina, {(diff_width_a){1'b0}}} : + (sourcea == 1)? {scanina, {(diff_width_a){1'b0}}} : {dataa, {(diff_width_a){1'b0}}}); + + always @(posedge input_a_wire_clk or posedge input_a_wire_clr) + begin + if (input_a_wire_clr == 1) + mult_a_reg <= 0; + else if ((input_a_wire_clk == 1) && (input_a_wire_en == 1)) + begin + if (input_source_a == "DATAA") + mult_a_reg <= (int_width_a == width_a) ? dataa : {dataa, {(diff_width_a){1'b0}}}; + else if (input_source_a == "SCANA") + mult_a_reg <= (int_width_a == width_a) ? scanina : {scanina,{(diff_width_a){1'b0}}}; + else if (input_source_a == "VARIABLE") + begin + if (sourcea == 1) + mult_a_reg <= (int_width_a == width_a) ? scanina : {scanina, {(diff_width_a){1'b0}}}; + else + mult_a_reg <= (int_width_a == width_a) ? dataa : {dataa, {(diff_width_a){1'b0}}}; + end + end + end + + + // ------------------------------------------------------------------------ + // This block contains 1 register and 1 combinatorial block (to set mult_b) + // Signal Registered : datab + // + // Register is controlled by posedge input_wire_b_clk + // Register has an asynchronous clear signal, input_reg_b_wire_clr + // NOTE : The combinatorial block will be executed if + // input_reg_b is unregistered and datab changes value + // ------------------------------------------------------------------------ + assign mult_b_wire = (input_reg_b == "UNREGISTERED")? mult_b_tmp : mult_b_reg; + assign mult_b_tmp = (int_width_b == width_b) ? ((input_source_b == "DATAB")? datab : + (input_source_b == "SCANB")? scaninb : + (sourceb == 1)? scaninb : datab) + : ((input_source_b == "DATAB")? {datab, {(diff_width_b){1'b0}}} : + (input_source_b == "SCANB")? {scaninb, {(diff_width_b){1'b0}}} : + (sourceb == 1)? {scaninb, {(diff_width_b){1'b0}}} : {datab, {(diff_width_b){1'b0}}}); + + always @(posedge input_b_wire_clk or posedge input_b_wire_clr ) + begin + if (input_b_wire_clr == 1) + mult_b_reg <= 0; + else if ((input_b_wire_clk == 1) && (input_b_wire_en == 1)) + begin + if (input_source_b == "DATAB") + mult_b_reg <= (int_width_b == width_b) ? datab : {datab, {(diff_width_b){1'b0}}}; + else if (input_source_b == "SCANB") + mult_b_reg <= (int_width_b == width_b) ? scaninb : {scaninb, {(diff_width_b){1'b0}}}; + else if (input_source_b == "VARIABLE") + begin + if (sourceb == 1) + mult_b_reg <= (int_width_b == width_b) ? scaninb : {scaninb, {(diff_width_b){1'b0}}}; + else + mult_b_reg <= (int_width_b == width_b) ? datab : {datab, {(diff_width_b){1'b0}}}; + end + end + end + + + // ----------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addnsub_reg) + // Signal Registered : addnsub + // + // Register is controlled by posedge addsub_wire_clk + // Register has an asynchronous clear signal, addsub_wire_clr + // NOTE : The combinatorial block will be executed if + // addnsub_reg is unregistered and addnsub changes value + // ----------------------------------------------------------------------------- + assign addsub_wire = ((addnsub_reg == "UNREGISTERED") )? addnsub : addsub_reg; + + always @(posedge addsub_wire_clk or posedge addsub_wire_clr) + begin + if (addsub_wire_clr == 1) + addsub_reg <= 0; + else if ((addsub_wire_clk == 1) && (addsub_wire_en == 1)) + addsub_reg <= addnsub; + end + + + // ----------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addsub_pipe) + // Signal Registered : addsub_latent + // + // Register is controlled by posedge addsub_pipe_wire_clk + // Register has an asynchronous clear signal, addsub_pipe_wire_clr + // NOTE : The combinatorial block will be executed if + // addsub_pipeline_reg is unregistered and addsub_latent changes value + // ----------------------------------------------------------------------------- + assign addsub_pipe_wire = (addnsub_pipeline_reg == "UNREGISTERED")?addsub_latent : addsub_pipe_reg; + + always @(posedge addsub_pipe_wire_clk or posedge addsub_pipe_wire_clr ) + begin + if (addsub_pipe_wire_clr == 1) + addsub_pipe_reg <= 0; + else if ((addsub_pipe_wire_clk == 1) && (addsub_pipe_wire_en == 1)) + addsub_pipe_reg <= addsub_latent; + + end + + + // ------------------------------------------------------------------------------ + // This block contains 1 register and 1 combinatorial block (to set zero_acc_reg) + // Signal Registered : accum_sload + // + // Register is controlled by posedge zero_wire_clk + // Register has an asynchronous clear signal, zero_wire_clr + // NOTE : The combinatorial block will be executed if + // accum_sload_reg is unregistered and accum_sload changes value + // ------------------------------------------------------------------------------ + assign zero_acc_wire = (accum_sload_reg == "UNREGISTERED")?accum_sload : zero_acc_reg; + + always @(posedge zero_wire_clk or posedge zero_wire_clr) + begin + if (zero_wire_clr == 1) + begin + zero_acc_reg <= 0; + end + else if ((zero_wire_clk == 1) && (zero_wire_en == 1)) + begin + zero_acc_reg <= accum_sload; + end + end + + assign sload_upper_data_wire = (accum_sload_upper_data_reg == "UNREGISTERED")? accum_sload_upper_data_int : sload_upper_data_reg; + + + always @(posedge accum_sload_upper_data_wire_clk or posedge accum_sload_upper_data_wire_clr) + begin + if (accum_sload_upper_data_wire_clr == 1) + begin + sload_upper_data_reg <= 0; + end + else if ((accum_sload_upper_data_wire_clk == 1) && (accum_sload_upper_data_wire_en == 1)) + begin + sload_upper_data_reg <= accum_sload_upper_data_int; + end + end + + // -------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set zero_acc_pipe) + // Signal Registered : zeroacc_latent + // + // Register is controlled by posedge zero_pipe_wire_clk + // Register has an asynchronous clear signal, zero_pipe_wire_clr + // NOTE : The combinatorial block will be executed if + // accum_sload_pipeline_reg is unregistered and zeroacc_latent changes value + // -------------------------------------------------------------------------------- + assign zero_acc_pipe_wire = (accum_sload_pipeline_reg == "UNREGISTERED")?zeroacc_latent : zero_acc_pipe_reg; + + always @(posedge zero_pipe_wire_clk or posedge zero_pipe_wire_clr) + begin + if (zero_pipe_wire_clr == 1) + begin + zero_acc_pipe_reg <= 0; + end + else if ((zero_pipe_wire_clk == 1) && (zero_pipe_wire_en == 1)) + begin + zero_acc_pipe_reg <= zeroacc_latent; + end + + end + + + always @(posedge accum_sload_upper_data_pipe_wire_clk or posedge accum_sload_upper_data_pipe_wire_clr) + begin + if (accum_sload_upper_data_pipe_wire_clr == 1) + begin + sload_upper_data_pipe_reg <= 0; + end + else if ((accum_sload_upper_data_pipe_wire_clk == 1) && (accum_sload_upper_data_pipe_wire_en == 1)) + begin + sload_upper_data_pipe_reg <= sload_upper_data_latent; + end + + end + + always @(sload_upper_data_latent or sload_upper_data_pipe_reg or sign_a_int or sign_b_int ) + begin + if (accum_sload_upper_data_pipeline_reg == "UNREGISTERED") + begin + if(int_width_result > width_result) + begin + + if(sign_a_int | sign_b_int) + begin + sload_upper_data_pipe_wire[int_width_result - 1 : 0] = {int_width_result{sload_upper_data_latent[width_upper_data-1]}}; + end + else + begin + sload_upper_data_pipe_wire[int_width_result - 1 : 0] = {int_width_result{1'b0}}; + end + + if(width_result > width_upper_data) + begin + for(i4 = 0; i4 < width_result - width_upper_data + int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : width_result - width_upper_data + int_extra_width] = sload_upper_data_latent; + end + else if(width_result == width_upper_data) + begin + for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + sload_upper_data_pipe_wire[width_result - 1 + int_extra_width: 0 + int_extra_width] = sload_upper_data_latent; + end + else + begin + for(i4 = int_extra_width; i4 < sload_for_limit; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = sload_upper_data_latent[i4]; + end + for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + end + end + else + begin + if(width_result > width_upper_data) + begin + for(i4 = 0; i4 < width_result - width_upper_data + int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : width_result - width_upper_data + int_extra_width] = sload_upper_data_latent; + end + else if(width_result == width_upper_data) + begin + for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : 0 + int_extra_width] = sload_upper_data_latent; + end + else + begin + for(i4 = int_extra_width; i4 < sload_for_limit; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = sload_upper_data_latent[i4]; + end + for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + end + end + end + else + begin + if(int_width_result > width_result) + begin + + if(sign_a_int | sign_b_int) + begin + sload_upper_data_pipe_wire[int_width_result - 1 : 0] = {int_width_result{sload_upper_data_pipe_reg[width_upper_data-1]}}; + end + else + begin + sload_upper_data_pipe_wire[int_width_result - 1 : 0] = {int_width_result{1'b0}}; + end + + if(width_result > width_upper_data) + begin + for(i4 = 0; i4 < width_result - width_upper_data + int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : width_result - width_upper_data + int_extra_width] = sload_upper_data_pipe_reg; + end + else if(width_result == width_upper_data) + begin + for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + sload_upper_data_pipe_wire[width_result - 1 + int_extra_width: 0 + int_extra_width] = sload_upper_data_pipe_reg; + end + else + begin + for(i4 = int_extra_width; i4 < sload_for_limit; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = sload_upper_data_pipe_reg[i4]; + end + for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + end + end + else + begin + if(width_result > width_upper_data) + begin + for(i4 = 0; i4 < width_result - width_upper_data + int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : width_result - width_upper_data + int_extra_width] = sload_upper_data_pipe_reg; + end + else if(width_result == width_upper_data) + begin + for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + sload_upper_data_pipe_wire[width_result - 1 + int_extra_width : 0 + int_extra_width] = sload_upper_data_pipe_reg; + end + else + begin + for(i4 = int_extra_width; i4 < sload_for_limit; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = sload_upper_data_pipe_reg[i4]; + end + for(i4 = 0; i4 < int_extra_width; i4 = i4 + 1) + begin + sload_upper_data_pipe_wire[i4] = 1'b0; + end + end + end + end + end + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set sign_a_reg) + // Signal Registered : signa + // + // Register is controlled by posedge sign_a_wire_clk + // Register has an asynchronous clear signal, sign_a_wire_clr + // NOTE : The combinatorial block will be executed if + // sign_reg_a is unregistered and signa changes value + // ---------------------------------------------------------------------------- + assign sign_a_wire = (sign_reg_a == "UNREGISTERED")? signa : sign_a_reg; + + always @(posedge sign_a_wire_clk or posedge sign_a_wire_clr) + begin + if (sign_a_wire_clr == 1) + sign_a_reg <= 0; + else if ((sign_a_wire_clk == 1) && (sign_a_wire_en == 1)) + sign_a_reg <= signa; + end + + + // ----------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set sign_a_pipe) + // Signal Registered : signa_latent + // + // Register is controlled by posedge sign_pipe_a_wire_clk + // Register has an asynchronous clear signal, sign_pipe_a_wire_clr + // NOTE : The combinatorial block will be executed if + // sign_pipeline_reg_a is unregistered and signa_latent changes value + // ----------------------------------------------------------------------------- + assign sign_a_pipe_wire = (sign_pipeline_reg_a == "UNREGISTERED")? signa_latent : sign_a_pipe_reg; + + always @(posedge sign_pipe_a_wire_clk or posedge sign_pipe_a_wire_clr) + begin + if (sign_pipe_a_wire_clr == 1) + sign_a_pipe_reg <= 0; + else if ((sign_pipe_a_wire_clk == 1) && (sign_pipe_a_wire_en == 1)) + sign_a_pipe_reg <= signa_latent; + end + + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set sign_b_reg) + // Signal Registered : signb + // + // Register is controlled by posedge sign_b_wire_clk + // Register has an asynchronous clear signal, sign_b_wire_clr + // NOTE : The combinatorial block will be executed if + // sign_reg_b is unregistered and signb changes value + // ---------------------------------------------------------------------------- + assign sign_b_wire = (sign_reg_b == "UNREGISTERED") ? signb : sign_b_reg; + + always @(posedge sign_b_wire_clk or posedge sign_b_wire_clr) + begin + if (sign_b_wire_clr == 1) + sign_b_reg <= 0; + else if ((sign_b_wire_clk == 1) && (sign_b_wire_en == 1)) + sign_b_reg <= signb; + end + + + // ----------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set sign_b_pipe) + // Signal Registered : signb_latent + // + // Register is controlled by posedge sign_pipe_b_wire_clk + // Register has an asynchronous clear signal, sign_pipe_b_wire_clr + // NOTE : The combinatorial block will be executed if + // sign_pipeline_reg_b is unregistered and signb_latent changes value + // ----------------------------------------------------------------------------- + assign sign_b_pipe_wire = (sign_pipeline_reg_b == "UNREGISTERED" )? signb_latent : sign_b_pipe_reg; + + always @(posedge sign_pipe_b_wire_clk or posedge sign_pipe_b_wire_clr ) + begin + if (sign_pipe_b_wire_clr == 1) + sign_b_pipe_reg <= 0; + else if ((sign_pipe_b_wire_clk == 1) && (sign_pipe_b_wire_en == 1)) + sign_b_pipe_reg <= signb_latent; + + end + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_round) + // Signal Registered : mult_round + // + // Register is controlled by posedge mult_round_wire_clk + // Register has an asynchronous clear signal, mult_round_wire_clr + // NOTE : The combinatorial block will be executed if + // mult_round_reg is unregistered and mult_round changes value + // ---------------------------------------------------------------------------- + + assign mult_round_int = (mult_round_reg == "UNREGISTERED")? mult_round : mult_round_tmp; + + always @(posedge mult_round_wire_clk or posedge mult_round_wire_clr) + begin + if (mult_round_wire_clr == 1) + mult_round_tmp <= 0; + else if ((mult_round_wire_clk == 1) && (mult_round_wire_en == 1)) + mult_round_tmp <= mult_round; + end + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_saturation) + // Signal Registered : mult_saturation + // + // Register is controlled by posedge mult_saturation_wire_clk + // Register has an asynchronous clear signal, mult_saturation_wire_clr + // NOTE : The combinatorial block will be executed if + // mult_saturation_reg is unregistered and mult_saturation changes value + // ---------------------------------------------------------------------------- + + assign mult_saturation_int = (mult_saturation_reg == "UNREGISTERED")? mult_saturation : mult_saturation_tmp; + + always @(posedge mult_saturation_wire_clk or posedge mult_saturation_wire_clr) + begin + if (mult_saturation_wire_clr == 1) + mult_saturation_tmp <= 0; + else if ((mult_saturation_wire_clk == 1) && (mult_saturation_wire_en == 1)) + mult_saturation_tmp <= mult_saturation; + end + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set accum_round) + // Signal Registered : accum_round + // + // Register is controlled by posedge accum_round_wire_clk + // Register has an asynchronous clear signal, accum_round_wire_clr + // NOTE : The combinatorial block will be executed if + // accum_round_reg is unregistered and accum_round changes value + // ---------------------------------------------------------------------------- + + assign accum_round_tmp1_wire = (accum_round_reg == "UNREGISTERED")? accum_round : accum_round_tmp1; + + always @(posedge accum_round_wire_clk or posedge accum_round_wire_clr) + begin + if (accum_round_wire_clr == 1) + accum_round_tmp1 <= 0; + else if ((accum_round_wire_clk == 1) && (accum_round_wire_en == 1)) + accum_round_tmp1 <= accum_round; + end + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set accum_round_tmp1) + // Signal Registered : accum_round_tmp1 + // + // Register is controlled by posedge accum_round_pipe_wire_clk + // Register has an asynchronous clear signal, accum_round_pipe_wire_clr + // NOTE : The combinatorial block will be executed if + // accum_round_pipeline_reg is unregistered and accum_round_tmp1_wire changes value + // ---------------------------------------------------------------------------- + + assign accum_round_int = (accum_round_pipeline_reg == "UNREGISTERED")? accum_round_tmp1_wire : accum_round_tmp2; + + always @(posedge accum_round_pipe_wire_clk or posedge accum_round_pipe_wire_clr) + begin + if (accum_round_pipe_wire_clr == 1) + accum_round_tmp2 <= 0; + else if ((accum_round_pipe_wire_clk == 1) && (accum_round_pipe_wire_en == 1)) + accum_round_tmp2 <= accum_round_tmp1_wire; + end + + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set accum_saturation) + // Signal Registered : accum_saturation + // + // Register is controlled by posedge accum_saturation_wire_clk + // Register has an asynchronous clear signal, accum_saturation_wire_clr + // NOTE : The combinatorial block will be executed if + // accum_saturation_reg is unregistered and accum_saturation changes value + // ---------------------------------------------------------------------------- + + assign accum_saturation_tmp1_wire = (accum_saturation_reg == "UNREGISTERED")? accum_saturation : accum_saturation_tmp1; + + always @(posedge accum_saturation_wire_clk or posedge accum_saturation_wire_clr) + begin + if (accum_saturation_wire_clr == 1) + accum_saturation_tmp1 <= 0; + else if ((accum_saturation_wire_clk == 1) && (accum_saturation_wire_en == 1)) + accum_saturation_tmp1 <= accum_saturation; + end + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set accum_saturation_tmp1) + // Signal Registered : accum_saturation_tmp1 + // + // Register is controlled by posedge accum_saturation_pipe_wire_clk + // Register has an asynchronous clear signal, accum_saturation_pipe_wire_clr + // NOTE : The combinatorial block will be executed if + // accum_saturation_pipeline_reg is unregistered and accum_saturation_tmp1_wire changes value + // ---------------------------------------------------------------------------- + + assign accum_saturation_int = (accum_saturation_pipeline_reg == "UNREGISTERED")? accum_saturation_tmp1_wire : accum_saturation_tmp2; + + always @(posedge accum_saturation_pipe_wire_clk or posedge accum_saturation_pipe_wire_clr) + begin + if (accum_saturation_pipe_wire_clr == 1) + accum_saturation_tmp2 <= 0; + else if ((accum_saturation_pipe_wire_clk == 1) && (accum_saturation_pipe_wire_en == 1)) + accum_saturation_tmp2 <= accum_saturation_tmp1_wire; + end + + + // ------------------------------------------------------------------------------------------------------ + // This block checks if the two numbers to be multiplied (mult_a/mult_b) is to be interpreted + // as a negative number or not. If so, then two's complement is performed. + // The numbers are then multipled + // The sign of the result (positive or negative) is determined based on the sign of the two input numbers + // ------------------------------------------------------------------------------------------------------ + + always @(mult_a_wire or mult_b_wire or sign_a_reg_int or sign_b_reg_int or temp_mult_zero) + begin + neg_a = mult_a_wire [int_width_a-1] & (sign_a_reg_int); + neg_b = mult_b_wire [int_width_b-1] & (sign_b_reg_int); + + mult_a_int = (neg_a == 1) ? ~mult_a_wire + 1 : mult_a_wire; + mult_b_int = (neg_b == 1) ? ~mult_b_wire + 1 : mult_b_wire; + + temp_mult_1 = mult_a_int * mult_b_int; + temp_mult_signed = sign_a_reg_int | sign_b_reg_int; + temp_mult = (neg_a ^ neg_b) ? (temp_mult_zero - temp_mult_1) : temp_mult_1; + + end + + always @(temp_mult or mult_saturation_int or mult_round_int) + begin + + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 1) + begin + // StratixII rounding support + + // This is based on both input is in Q1.15 format + + if ((multiplier_rounding == "YES") || + ((multiplier_rounding == "VARIABLE") && (mult_round_int == 1))) + begin + mult_round_out = temp_mult + ( 1 << (bits_to_round)); + + end + else + begin + mult_round_out = temp_mult; + end + + // StratixII saturation support + + if ((multiplier_saturation == "YES") || + (( multiplier_saturation == "VARIABLE") && (mult_saturation_int == 1))) + begin + mult_saturate_overflow = (mult_round_out[int_width_a + int_width_b - 1] == 0 && mult_round_out[int_width_a + int_width_b - 2] == 1); + if (mult_saturate_overflow == 0) + begin + mult_saturate_out = mult_round_out; + end + else + begin + for (i = (int_width_a + int_width_b - 1); i >= (int_width_a + int_width_b - 2); i = i - 1) + begin + mult_saturate_out[i] = mult_round_out[int_width_a + int_width_b - 1]; + end + + for (i = (int_width_a + int_width_b - 3); i >= 0; i = i - 1) + begin + mult_saturate_out[i] = ~mult_round_out[int_width_a + int_width_b - 1]; + end + + for (i= sat_for_ini; i >=0; i = i - 1) + begin + mult_saturate_out[i] = 1'b0; + end + + end + end + else + begin + mult_saturate_out = mult_round_out; + mult_saturate_overflow = 0; + end + + if ((multiplier_rounding == "YES") || + ((multiplier_rounding == "VARIABLE") && (mult_round_int == 1))) + begin + mult_result = mult_saturate_out; + + for (i = mult_round_for_ini; i >= 0; i = i - 1) + begin + mult_result[i] = 1'b0; + end + end + else + begin + mult_result = mult_saturate_out; + end + end + + mult_final_out = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) ? + temp_mult : mult_result; + + end + + + // --------------------------------------------------------------------------------------- + // This block contains 2 register (to set mult_res and mult_signed) + // Signals Registered : mult_out_latent, mult_signed_latent + // + // Both the registers are controlled by the same clock signal, posedge multiplier_wire_clk + // Both registers share the same clock enable signal multipler_wire_en + // Both registers have the same asynchronous signal, posedge multiplier_wire_clr + // --------------------------------------------------------------------------------------- + assign mult_is_saturated_wire = (multiplier_reg == "UNREGISTERED")? mult_is_saturated_latent : mult_is_saturated_reg; + + always @(posedge multiplier_wire_clk or posedge multiplier_wire_clr) + begin + if (multiplier_wire_clr == 1) + begin + mult_res <=0; + mult_signed <=0; + mult_is_saturated_reg <=0; + end + else if ((multiplier_wire_clk == 1) && (multiplier_wire_en == 1)) + begin + mult_res <= mult_out_latent; + mult_signed <= mult_signed_latent; + mult_is_saturated_reg <= mult_is_saturated_latent; + end + end + + + // -------------------------------------------------------------------- + // This block contains 1 register (to set mult_full) + // Signal Registered : mult_pipe + // + // Register is controlled by posedge mult_pipe_wire_clk + // Register also has an asynchronous clear signal posedge mult_pipe_wire_clr + // -------------------------------------------------------------------- + always @(posedge mult_pipe_wire_clk or posedge mult_pipe_wire_clr ) + begin + if (mult_pipe_wire_clr ==1) + begin + // clear the pipeline + for (i2=0; i2<=extra_multiplier_latency; i2=i2+1) + begin + mult_pipe [i2] = 0; + end + mult_full = 0; + end + else if ((mult_pipe_wire_clk == 1) && (mult_pipe_wire_en == 1)) + begin + mult_pipe [head_mult] = {addsub_wire, zero_acc_wire, sign_a_wire, sign_b_wire, temp_mult_signed, mult_final_out, sload_upper_data_wire, mult_saturate_overflow}; + head_mult = (head_mult +1) % (extra_multiplier_latency); + mult_full = mult_pipe[head_mult]; + end + end + + + // ------------------------------------------------------------- + // This is the main process block that performs the accumulation + // ------------------------------------------------------------- + always @(posedge output_wire_clk or posedge output_wire_clr) + begin + if (output_wire_clr == 1) + begin + temp_sum = 0; + accum_result = 0; + + result_int = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) ? + temp_sum[int_width_result -1 : 0] : accum_result; + + overflow_int = 0; + accum_saturate_overflow = 0; + mult_is_saturated_int = 0; + for (i3=0; i3<=extra_accumulator_latency; i3=i3+1) + begin + result_pipe [i3] = 0; + accum_saturate_pipe[i3] = 0; + mult_is_saturated_pipe[i3] = 0; + end + + flag = ~flag; + + end + else if (output_wire_clk ==1) + begin + + if (output_wire_en ==1) + begin + if (extra_accumulator_latency == 0) + begin + mult_is_saturated_int = mult_is_saturated_wire; + end + + if (multiplier_reg == "UNREGISTERED") + begin + mult_res_out = {{int_width_result - int_width_a - int_width_b {(sign_a_int | sign_b_int) & mult_out_latent [int_width_a+int_width_b -1]}}, mult_out_latent}; + mult_signed_out = (sign_a_int | sign_b_int); + end + else + begin + mult_res_out = {{int_width_result - int_width_a - int_width_b {(sign_a_int | sign_b_int) & mult_res [int_width_a+int_width_b -1]}}, mult_res}; + mult_signed_out = (sign_a_int | sign_b_int); + end + + if (addsub_int) + begin + //add + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0 && + dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) + begin + temp_sum = ( (zero_acc_int==0) ? result_int : 0) + mult_res_out; + end + else + begin + temp_sum = ( (zero_acc_int==0) ? result_int : sload_upper_data_pipe_wire) + mult_res_out; + end + + cout_int = temp_sum [int_width_result]; + end + else + begin + //subtract + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0 && + dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) + begin + temp_sum = ( (zero_acc_int==0) ? result_int : 0) - (mult_res_out); + cout_int = (( (zero_acc_int==0) ? result_int : 0) >= mult_res_out) ? 1 : 0; + end + else + begin + temp_sum = ( (zero_acc_int==0) ? result_int : sload_upper_data_pipe_wire) - mult_res_out; + cout_int = (( (zero_acc_int==0) ? result_int : sload_upper_data_pipe_wire) >= mult_res_out) ? 1 : 0; + end + end + + //compute overflow + if ((mult_signed_out==1) && (mult_res_out != 0)) + begin + if (zero_acc_int == 0) + begin + overflow_tmp_int = (mult_res_out [int_width_a+int_width_b -1] ~^ result_int [int_width_result-1]) ^ (~addsub_int); + overflow_int = overflow_tmp_int & (result_int [int_width_result -1] ^ temp_sum[int_width_result -1]); + end + else + begin + overflow_tmp_int = (mult_res_out [int_width_a+int_width_b -1] ~^ sload_upper_data_pipe_wire [int_width_result-1]) ^ (~addsub_int); + overflow_int = overflow_tmp_int & (sload_upper_data_pipe_wire [int_width_result -1] ^ temp_sum[int_width_result -1]); + end + end + else + begin + overflow_int = (addsub_int ==1)? cout_int : ~cout_int; + end + + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 1) + begin + // StratixII rounding support + + // This is based on both input is in Q1.15 format + + if ((accumulator_rounding == "YES") || + ((accumulator_rounding == "VARIABLE") && (accum_round_int == 1))) + begin + accum_round_out = temp_sum[int_width_result -1 : 0] + ( 1 << (bits_to_round)); + end + else + begin + accum_round_out = temp_sum[int_width_result - 1 : 0]; + end + + // StratixII saturation support + + if ((accumulator_saturation == "YES") || + ((accumulator_saturation == "VARIABLE") && (accum_saturation_int == 1))) + begin + accum_result_sign_bits = accum_round_out[int_width_result-1 : int_width_a + int_width_b - 2]; + + if ( (((&accum_result_sign_bits) | (|accum_result_sign_bits) | (^accum_result_sign_bits)) == 0) || + (((&accum_result_sign_bits) & (|accum_result_sign_bits) & !(^accum_result_sign_bits)) == 1)) + begin + accum_saturate_overflow = 1'b0; + end + else + begin + accum_saturate_overflow = 1'b1; + end + + if (accum_saturate_overflow == 0) + begin + accum_saturate_out = accum_round_out; + end + else + begin + + for (i = (int_width_result - 1); i >= (int_width_a + int_width_b - 2); i = i - 1) + begin + accum_saturate_out[i] = accum_round_out[int_width_result-1]; + end + + + for (i = (int_width_a + int_width_b - 3); i >= accum_sat_for_limit; i = i - 1) + begin + accum_saturate_out[i] = ~accum_round_out[int_width_result -1]; + end + + for (i = sat_for_ini; i >= 0; i = i - 1) + begin + accum_saturate_out[i] = 1'b0; + end + + end + end + else + begin + accum_saturate_out = accum_round_out; + accum_saturate_overflow = 0; + end + + if ((accumulator_rounding == "YES") || + ((accumulator_rounding == "VARIABLE") && (accum_round_int == 1))) + begin + accum_result = accum_saturate_out; + + for (i = bits_to_round; i >= 0; i = i - 1) + begin + accum_result[i] = 1'b0; + end + end + else + begin + accum_result = accum_saturate_out; + end + end + + result_int = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) ? + temp_sum[int_width_result -1 : 0] : accum_result; + + flag = ~flag; + end + + end + end + + always @ (posedge flag or negedge flag) + begin + if (extra_accumulator_latency == 0) + begin + result = result_int[width_result - 1 + int_extra_width : int_extra_width]; + overflow = overflow_int; + accum_is_saturated_latent = accum_saturate_overflow; + end + else + begin + result_pipe [head_result] = {overflow_int, result_int[width_result - 1 + int_extra_width : int_extra_width]}; + //mult_is_saturated_pipe[head_result] = mult_is_saturated_wire; + accum_saturate_pipe[head_result] = accum_saturate_overflow; + head_result = (head_result +1) % (extra_accumulator_latency + 1); + result_full = result_pipe[head_result]; + result = result_full [width_result-1:0]; + overflow = result_full [width_result]; + mult_is_saturated_int = mult_is_saturated_wire; + accum_is_saturated_latent = accum_saturate_pipe[head_result]; + end + + end + +endmodule // end of ALTMULT_ACCUM + +//-------------------------------------------------------------------------- +// Module Name : altmult_add +// +// Description : a*b + c*d +// +// Limitation : Stratix DSP block +// +// Results expected : signed & unsigned, maximum of 3 pipelines(latency) each. +// possible of zero pipeline. +// +//-------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module altmult_add ( dataa, + datab, + scanina, + scaninb, + sourcea, + sourceb, + clock3, + clock2, + clock1, + clock0, + aclr3, + aclr2, + aclr1, + aclr0, + ena3, + ena2, + ena1, + ena0, + signa, + signb, + addnsub1, + addnsub3, + result, + scanouta, + scanoutb, + mult01_round, + mult23_round, + mult01_saturation, + mult23_saturation, + addnsub1_round, + addnsub3_round, + mult0_is_saturated, + mult1_is_saturated, + mult2_is_saturated, + mult3_is_saturated); + + // --------------------- + // PARAMETER DECLARATION + // --------------------- + + parameter width_a = 1; + parameter width_b = 1; + parameter width_result = 3; + parameter number_of_multipliers = 1; + parameter lpm_type = "altmult_add"; + parameter lpm_hint = "UNUSED"; + + // A inputs + + parameter multiplier1_direction = "UNUSED"; + parameter multiplier3_direction = "UNUSED"; + + parameter input_register_a0 = "CLOCK0"; + parameter input_aclr_a0 = "ACLR3"; + parameter input_source_a0 = "DATAA"; + + parameter input_register_a1 = "CLOCK0"; + parameter input_aclr_a1 = "ACLR3"; + parameter input_source_a1 = "DATAA"; + + parameter input_register_a2 = "CLOCK0"; + parameter input_aclr_a2 = "ACLR3"; + parameter input_source_a2 = "DATAA"; + + parameter input_register_a3 = "CLOCK0"; + parameter input_aclr_a3 = "ACLR3"; + parameter input_source_a3 = "DATAA"; + + parameter port_signa = "PORT_CONNECTIVITY"; + parameter representation_a = "UNUSED"; + parameter signed_register_a = "CLOCK0"; + parameter signed_aclr_a = "ACLR3"; + parameter signed_pipeline_register_a = "CLOCK0"; + parameter signed_pipeline_aclr_a = "ACLR3"; + + // B inputs + + parameter input_register_b0 = "CLOCK0"; + parameter input_aclr_b0 = "ACLR3"; + parameter input_source_b0 = "DATAB"; + + parameter input_register_b1 = "CLOCK0"; + parameter input_aclr_b1 = "ACLR3"; + parameter input_source_b1 = "DATAB"; + + parameter input_register_b2 = "CLOCK0"; + parameter input_aclr_b2 = "ACLR3"; + parameter input_source_b2 = "DATAB"; + + parameter input_register_b3 = "CLOCK0"; + parameter input_aclr_b3 = "ACLR3"; + parameter input_source_b3 = "DATAB"; + + parameter port_signb = "PORT_CONNECTIVITY"; + parameter representation_b = "UNUSED"; + parameter signed_register_b = "CLOCK0"; + parameter signed_aclr_b = "ACLR3"; + parameter signed_pipeline_register_b = "CLOCK0"; + parameter signed_pipeline_aclr_b = "ACLR3"; + + // multiplier parameters + + parameter multiplier_register0 = "CLOCK0"; + parameter multiplier_aclr0 = "ACLR3"; + parameter multiplier_register1 = "CLOCK0"; + parameter multiplier_aclr1 = "ACLR3"; + parameter multiplier_register2 = "CLOCK0"; + parameter multiplier_aclr2 = "ACLR3"; + parameter multiplier_register3 = "CLOCK0"; + parameter multiplier_aclr3 = "ACLR3"; + + parameter port_addnsub1 = "PORT_CONNECTIVITY"; + parameter addnsub_multiplier_register1 = "CLOCK0"; + parameter addnsub_multiplier_aclr1 = "ACLR3"; + parameter addnsub_multiplier_pipeline_register1 = "CLOCK0"; + parameter addnsub_multiplier_pipeline_aclr1 = "ACLR3"; + + parameter port_addnsub3 = "PORT_CONNECTIVITY"; + parameter addnsub_multiplier_register3 = "CLOCK0"; + parameter addnsub_multiplier_aclr3 = "ACLR3"; + parameter addnsub_multiplier_pipeline_register3 = "CLOCK0"; + parameter addnsub_multiplier_pipeline_aclr3 = "ACLR3"; + + parameter addnsub1_round_aclr = "ACLR3"; + parameter addnsub1_round_pipeline_aclr = "ACLR3"; + parameter addnsub1_round_register = "CLOCK0"; + parameter addnsub1_round_pipeline_register = "CLOCK0"; + parameter addnsub3_round_aclr = "ACLR3"; + parameter addnsub3_round_pipeline_aclr = "ACLR3"; + parameter addnsub3_round_register = "CLOCK0"; + parameter addnsub3_round_pipeline_register = "CLOCK0"; + + parameter mult01_round_aclr = "ACLR3"; + parameter mult01_round_register = "CLOCK0"; + parameter mult01_saturation_register = "CLOCK0"; + parameter mult01_saturation_aclr = "ACLR3"; + parameter mult23_round_register = "CLOCK0"; + parameter mult23_round_aclr = "ACLR3"; + parameter mult23_saturation_register = "CLOCK0"; + parameter mult23_saturation_aclr = "ACLR3"; + + // StratixII parameters + parameter multiplier01_rounding = "NO"; + parameter multiplier01_saturation = "NO"; + parameter multiplier23_rounding = "NO"; + parameter multiplier23_saturation = "NO"; + parameter adder1_rounding = "NO"; + parameter adder3_rounding = "NO"; + parameter port_mult0_is_saturated = "UNUSED"; + parameter port_mult1_is_saturated = "UNUSED"; + parameter port_mult2_is_saturated = "UNUSED"; + parameter port_mult3_is_saturated = "UNUSED"; + + // output parameters + + parameter output_register = "CLOCK0"; + parameter output_aclr = "ACLR0"; + + // general setting parameters + + parameter extra_latency = 0; + parameter dedicated_multiplier_circuitry = "AUTO"; + parameter dsp_block_balancing = "AUTO"; + parameter intended_device_family = "Stratix"; + + // ---------------- + // PORT DECLARATION + // ---------------- + + // data input ports + input [number_of_multipliers * width_a -1 : 0] dataa; + input [number_of_multipliers * width_b -1 : 0] datab; + + input [width_a -1 : 0] scanina; + input [width_b -1 : 0] scaninb; + + input [number_of_multipliers -1 : 0] sourcea; + input [number_of_multipliers -1 : 0] sourceb; + + // clock ports + input clock3; + input clock2; + input clock1; + input clock0; + + // clear ports + input aclr3; + input aclr2; + input aclr1; + input aclr0; + + // clock enable ports + input ena3; + input ena2; + input ena1; + input ena0; + + // control signals + input signa; + input signb; + input addnsub1; + input addnsub3; + + // StratixII only input ports + input mult01_round; + input mult23_round; + input mult01_saturation; + input mult23_saturation; + input addnsub1_round; + input addnsub3_round; + + + // output ports + output [width_result -1 : 0] result; + output [width_a -1 : 0] scanouta; + output [width_b -1 : 0] scanoutb; + + // StratixII only output ports + output mult0_is_saturated; + output mult1_is_saturated; + output mult2_is_saturated; + output mult3_is_saturated; + + // ----------------------------------- + // Parameters internally used + // ----------------------------------- + // Represent the internal used width_a + parameter int_width_a = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") && + (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? width_a: + (width_a < 18)? 18 : width_a); + // Represent the internal used width_b + parameter int_width_b = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") && + (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? width_b: + (width_b < 18)? 18 : width_b); + + //Represent the internally used width_result + parameter int_width_result = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") && + (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? width_result: + (width_result > (int_width_a + int_width_b))? width_result + width_result - int_width_a - int_width_b: + int_width_a + int_width_b); + + // Represent the internally used width_result + parameter int_mult_diff_bit = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") && + (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? 0: + (int_width_a - width_a + int_width_b - width_b)); + + parameter sat_ini_value = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO"))? 3: + int_width_a + int_width_b - 3); + + // ----------------------------------- + // Constants internally used + // ----------------------------------- + // Represent the number of bits needed to be rounded in multiplier where the + // value 17 here refers to the 2 sign bits and the 15 wanted bits for rounding + `define MULT_ROUND_BITS (((multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? 1 : (int_width_a + int_width_b) - 17) + + // Represent the number of bits needed to be rounded in adder where the + // value 18 here refers to the 3 sign bits and the 15 wanted bits for rounding. + `define ADDER_ROUND_BITS (((multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? 1 :(int_width_a + int_width_b) - 17) + + + + // --------------- + // REG DECLARATION + // --------------- + + reg [int_width_result :0] temp_sum; + reg [int_width_result : 0] mult_res_ext; + reg [int_width_result : 0] temp_sum_reg; + + reg [4 * int_width_a -1 : 0] mult_a_reg; + reg [4 * int_width_b -1 : 0] mult_b_reg; + + + reg [(int_width_a + int_width_b) -1:0] mult_res_0; + reg [(int_width_a + int_width_b) -1:0] mult_res_1; + reg [(int_width_a + int_width_b) -1:0] mult_res_2; + reg [(int_width_a + int_width_b) -1:0] mult_res_3; + + + reg [4 * (int_width_a + int_width_b) -1:0] mult_res_reg; + reg [(int_width_a + int_width_b - 1) :0] mult_res_temp; + + + reg sign_a_pipe_reg; + reg sign_a_reg; + reg sign_b_pipe_reg; + reg sign_b_reg; + + reg addsub1_reg; + reg addsub1_pipe_reg; + + reg addsub3_reg; + reg addsub3_pipe_reg; + + + // StratixII features related internal reg type + + reg [(int_width_a + int_width_b + 3) -1 : 0] mult0_round_out; + reg [(int_width_a + int_width_b + 3) -1 : 0] mult0_saturate_out; + reg [(int_width_a + int_width_b + 3) -1 : 0] mult0_result; + reg mult0_saturate_overflow; + reg mult0_saturate_overflow_stat; + + reg [(int_width_a + int_width_b + 3) -1 : 0] mult1_round_out; + reg [(int_width_a + int_width_b + 3) -1 : 0] mult1_saturate_out; + reg [(int_width_a + int_width_b) -1 : 0] mult1_result; + reg mult1_saturate_overflow; + reg mult1_saturate_overflow_stat; + + reg [(int_width_a + int_width_b + 3) -1 : 0] mult2_round_out; + reg [(int_width_a + int_width_b + 3) -1 : 0] mult2_saturate_out; + reg [(int_width_a + int_width_b) -1 : 0] mult2_result; + reg mult2_saturate_overflow; + reg mult2_saturate_overflow_stat; + + reg [(int_width_a + int_width_b + 3) -1 : 0] mult3_round_out; + reg [(int_width_a + int_width_b + 3) -1 : 0] mult3_saturate_out; + reg [(int_width_a + int_width_b) -1 : 0] mult3_result; + reg mult3_saturate_overflow; + reg mult3_saturate_overflow_stat; + + reg mult01_round_reg; + reg mult01_saturate_reg; + reg mult23_round_reg; + reg mult23_saturate_reg; + reg [3 : 0] mult_saturate_overflow_reg; + reg [3 : 0] mult_saturate_overflow_pipe_reg; + + reg [int_width_result : 0] adder1_round_out; + reg [int_width_result : 0] adder1_result; + reg addnsub1_round_reg; + reg addnsub1_round_pipe_reg; + + reg [int_width_result : 0] adder3_round_out; + reg [int_width_result : 0] adder3_result; + reg addnsub3_round_reg; + reg addnsub3_round_pipe_reg; + + reg zero_pad; + + //----------------- + // TRI DECLARATION + //----------------- + tri0 signa_z; + tri0 signb_z; + tri1 addnsub1_z; + tri1 addnsub3_z; + tri0 [4 * int_width_a -1 : 0] dataa_int; + tri0 [4 * int_width_b -1 : 0] datab_int; + tri0 [4 * int_width_a -1 : 0] new_dataa_int; + tri0 [4 * int_width_b -1 : 0] new_datab_int; + reg [4 * int_width_a -1 : 0] dataa_reg; + reg [4 * int_width_b -1 : 0] datab_reg; + tri0 [int_width_a - 1 : 0] scanina_z; + tri0 [int_width_b - 1 : 0] scaninb_z; + + // Tri wire for clear signal + tri0 input_reg_a0_wire_clr; + tri0 input_reg_a1_wire_clr; + tri0 input_reg_a2_wire_clr; + tri0 input_reg_a3_wire_clr; + + tri0 input_reg_b0_wire_clr; + tri0 input_reg_b1_wire_clr; + tri0 input_reg_b2_wire_clr; + tri0 input_reg_b3_wire_clr; + + tri0 sign_reg_a_wire_clr; + tri0 sign_pipe_a_wire_clr; + + tri0 sign_reg_b_wire_clr; + tri0 sign_pipe_b_wire_clr; + + tri0 addsub1_reg_wire_clr; + tri0 addsub1_pipe_wire_clr; + + tri0 addsub3_reg_wire_clr; + tri0 addsub3_pipe_wire_clr; + + tri0 multiplier_reg0_wire_clr; + tri0 multiplier_reg1_wire_clr; + tri0 multiplier_reg2_wire_clr; + tri0 multiplier_reg3_wire_clr; + + tri0 addnsub1_round_wire_clr; + tri0 addnsub1_round_pipe_wire_clr; + + tri0 addnsub3_round_wire_clr; + tri0 addnsub3_round_pipe_wire_clr; + + tri0 mult01_round_wire_clr; + tri0 mult01_saturate_wire_clr; + + tri0 mult23_round_wire_clr; + tri0 mult23_saturate_wire_clr; + + tri0 output_reg_wire_clr; + + tri0 [3 : 0] sourcea_wire; + tri0 [3 : 0] sourceb_wire; + + + + // Tri wire for enable signal + + tri1 input_reg_a0_wire_en; + tri1 input_reg_a1_wire_en; + tri1 input_reg_a2_wire_en; + tri1 input_reg_a3_wire_en; + + tri1 input_reg_b0_wire_en; + tri1 input_reg_b1_wire_en; + tri1 input_reg_b2_wire_en; + tri1 input_reg_b3_wire_en; + + + tri1 sign_reg_a_wire_en; + tri1 sign_pipe_a_wire_en; + + tri1 sign_reg_b_wire_en; + tri1 sign_pipe_b_wire_en; + + tri1 addsub1_reg_wire_en; + tri1 addsub1_pipe_wire_en; + + tri1 addsub3_reg_wire_en; + tri1 addsub3_pipe_wire_en; + + tri1 multiplier_reg0_wire_en; + tri1 multiplier_reg1_wire_en; + tri1 multiplier_reg2_wire_en; + tri1 multiplier_reg3_wire_en; + + tri1 addnsub1_round_wire_en; + tri1 addnsub1_round_pipe_wire_en; + + tri1 addnsub3_round_wire_en; + tri1 addnsub3_round_pipe_wire_en; + + tri1 mult01_round_wire_en; + tri1 mult01_saturate_wire_en; + + tri1 mult23_round_wire_en; + tri1 mult23_saturate_wire_en; + + tri1 output_reg_wire_en; + + + + + + // ---------------- + // WIRE DECLARATION + // ---------------- + + // Wire for Clock signals + wire input_reg_a0_wire_clk; + wire input_reg_a1_wire_clk; + wire input_reg_a2_wire_clk; + wire input_reg_a3_wire_clk; + + wire input_reg_b0_wire_clk; + wire input_reg_b1_wire_clk; + wire input_reg_b2_wire_clk; + wire input_reg_b3_wire_clk; + + wire sign_reg_a_wire_clk; + wire sign_pipe_a_wire_clk; + + wire sign_reg_b_wire_clk; + wire sign_pipe_b_wire_clk; + + wire addsub1_reg_wire_clk; + wire addsub1_pipe_wire_clk; + + wire addsub3_reg_wire_clk; + wire addsub3_pipe_wire_clk; + + wire multiplier_reg0_wire_clk; + wire multiplier_reg1_wire_clk; + wire multiplier_reg2_wire_clk; + wire multiplier_reg3_wire_clk; + + wire output_reg_wire_clk; + + wire addnsub1_round_wire_clk; + wire addnsub1_round_pipe_wire_clk; + wire addnsub1_round_wire; + wire addnsub1_round_pipe_wire; + wire addnsub1_round_pre; + wire addnsub3_round_wire_clk; + wire addnsub3_round_pipe_wire_clk; + wire addnsub3_round_wire; + wire addnsub3_round_pipe_wire; + wire addnsub3_round_pre; + + wire mult01_round_wire_clk; + wire mult01_saturate_wire_clk; + wire mult23_round_wire_clk; + wire mult23_saturate_wire_clk; + wire mult01_round_pre; + wire mult01_saturate_pre; + wire mult01_round_wire; + wire mult01_saturate_wire; + wire mult23_round_pre; + wire mult23_saturate_pre; + wire mult23_round_wire; + wire mult23_saturate_wire; + wire [3 : 0] mult_is_saturate_vec; + wire [3 : 0] mult_saturate_overflow_vec; + + wire [4 * int_width_a -1 : 0] mult_a_pre; + wire [4 * int_width_b -1 : 0] mult_b_pre; + + wire [int_width_a -1 : 0] scanouta; + wire [int_width_b -1 : 0] scanoutb; + + wire sign_a_int; + wire sign_b_int; + + wire addsub1_int; + wire addsub3_int; + + wire [4 * int_width_a -1 : 0] mult_a_wire; + wire [4 * int_width_b -1 : 0] mult_b_wire; + wire [4 * (int_width_a + int_width_b) -1:0] mult_res_wire; + wire sign_a_pipe_wire; + wire sign_a_wire; + wire sign_b_pipe_wire; + wire sign_b_wire; + wire addsub1_wire; + wire addsub1_pipe_wire; + wire addsub3_wire; + wire addsub3_pipe_wire; + + wire [int_width_a -1 : 0] i_scanina; + wire [int_width_b -1 : 0] i_scaninb; + + wire [(int_width_result - 1): 0] output_reg_wire_result; + wire [31:0] head_result_wire; + reg [(int_width_result - 1): 0] output_laten_result; + reg [(int_width_result - 1): 0] result_pipe [extra_latency : 0]; + reg [31:0] head_result; + integer head_result_int; + + + // ------------------- + // INTEGER DECLARATION + // ------------------- + integer num_bit_mult0; + integer num_bit_mult1; + integer num_bit_mult2; + integer num_bit_mult3; + integer j; + integer num_mult; + integer num_stor; + + + + // ------------------------ + // COMPONENT INSTANTIATIONS + // ------------------------ + ALTERA_DEVICE_FAMILIES dev (); + + + // ----------------------------------------------------------------------------- + // This block checks if the two numbers to be multiplied (mult_a/mult_b) is to + // be interpreted as a negative number or not. If so, then two's complement is + // performed. + // The numbers are then multipled. The sign of the result (positive or negative) + // is determined based on the sign of the two input numbers + // ------------------------------------------------------------------------------ + + function [(int_width_a + int_width_b - 1):0] do_multiply; + input [32 : 0] multiplier; + input signa_wire; + input signb_wire; + begin:MULTIPLY + + reg [int_width_a + int_width_b -1 :0] temp_mult_zero; + reg [int_width_a + int_width_b -1 :0] temp_mult; + reg [int_width_a -1 :0] op_a; + reg [int_width_b -1 :0] op_b; + reg [int_width_a -1 :0] op_a_int; + reg [int_width_b -1 :0] op_b_int; + reg neg_a; + reg neg_b; + reg temp_mult_signed; + + temp_mult_zero = 0; + temp_mult = 0; + + op_a = mult_a_wire >> (multiplier * int_width_a); + op_b = mult_b_wire >> (multiplier * int_width_b); + + neg_a = op_a[int_width_a-1] & (signa_wire); + neg_b = op_b[int_width_b-1] & (signb_wire); + + op_a_int = (neg_a == 1) ? (~op_a + 1) : op_a; + op_b_int = (neg_b == 1) ? (~op_b + 1) : op_b; + + temp_mult = op_a_int * op_b_int; + temp_mult = (neg_a ^ neg_b) ? (temp_mult_zero - temp_mult) : temp_mult; + + do_multiply = temp_mult; + end + endfunction + + + + + // -------------------------------------------------------------- + // initialization block of all the internal signals and registers + // -------------------------------------------------------------- + initial + begin + + // Checking for invalid parameters, in case Wizard is bypassed (hand-modified). + if (number_of_multipliers > 4) + begin + $display("Altmult_add does not currently support NUMBER_OF_MULTIPLIERS > 4"); + $stop; + end + if (number_of_multipliers <= 0) + begin + $display("NUMBER_OF_MULTIPLIERS must be greater than 0."); + $stop; + end + + + if (width_a <= 0) + begin + $display("Error: width_a must be greater than 0."); + $stop; + end + if (width_b <= 0) + begin + $display("Error: width_b must be greater than 0."); + $stop; + end + if (width_result <= 0) + begin + $display("Error: width_result must be greater than 0."); + $stop; + end + + if ((input_source_a0 != "DATAA") && + (input_source_a0 != "SCANA") && + (input_source_a0 != "VARIABLE")) + begin + $display("Error: The INPUT_SOURCE_A0 parameter is set to an illegal value."); + $stop; + end + + if ((input_source_a1 != "DATAA") && + (input_source_a1 != "SCANA") && + (input_source_a1 != "VARIABLE")) + begin + $display("Error: The INPUT_SOURCE_A1 parameter is set to an illegal value."); + $stop; + end + + if ((input_source_a2 != "DATAA") && + (input_source_a2 != "SCANA") && + (input_source_a2 != "VARIABLE")) + begin + $display("Error: The INPUT_SOURCE_A2 parameter is set to an illegal value."); + $stop; + end + + if ((input_source_a3 != "DATAA") && + (input_source_a3 != "SCANA") && + (input_source_a3 != "VARIABLE")) + begin + $display("Error: The INPUT_SOURCE_A3 parameter is set to an illegal value."); + $stop; + end + + if ((input_source_b0 != "DATAB") && + (input_source_b0 != "SCANB") && + (input_source_b0 != "VARIABLE")) + begin + $display("Error: The INPUT_SOURCE_B0 parameter is set to an illegal value."); + $stop; + end + + if ((input_source_b1 != "DATAB") && + (input_source_b1 != "SCANB") && + (input_source_b1 != "VARIABLE")) + begin + $display("Error: The INPUT_SOURCE_B1 parameter is set to an illegal value."); + $stop; + end + + if ((input_source_b2 != "DATAB") && + (input_source_b2 != "SCANB") && + (input_source_b2 != "VARIABLE")) + begin + $display("Error: The INPUT_SOURCE_B2 parameter is set to an illegal value."); + $stop; + end + + if ((input_source_b3 != "DATAB") && + (input_source_b3 != "SCANB") && + (input_source_b3 != "VARIABLE")) + begin + $display("Error: The INPUT_SOURCE_B3 parameter is set to an illegal value."); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) && + (input_source_a0 == "VARIABLE")) + begin + $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) && + (input_source_a1 == "VARIABLE")) + begin + $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) && + (input_source_a2 == "VARIABLE")) + begin + $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) && + (input_source_a3 == "VARIABLE")) + begin + $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) && + (input_source_b0 == "VARIABLE")) + begin + $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) && + (input_source_b1 == "VARIABLE")) + begin + $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) && + (input_source_b2 == "VARIABLE")) + begin + $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && (dev.IS_FAMILY_CYCLONEII(intended_device_family) == 0) && + (input_source_b3 == "VARIABLE")) + begin + $display("Error: Input source as VARIABLE is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dedicated_multiplier_circuitry != "AUTO") && + (dedicated_multiplier_circuitry != "YES") && + (dedicated_multiplier_circuitry != "NO")) + begin + $display("Error: The DEDICATED_MULTIPLIER_CIRCUITRY parameter is set to an illegal value."); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && + ((multiplier01_rounding == "YES") || (multiplier23_rounding == "YES") || + (multiplier01_rounding == "VARIABLE") || (multiplier23_rounding == "VARIABLE"))) + begin + $display("Error: Rounding for multiplier is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && + ((adder1_rounding == "YES") || (adder3_rounding == "YES") || + (adder1_rounding == "VARIABLE") || (adder3_rounding == "VARIABLE"))) + begin + $display("Error: Rounding for adder is not supported in %s device family", intended_device_family); + $stop; + end + + if ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) && + ((multiplier01_saturation == "YES") || (multiplier23_saturation == "YES") || + (multiplier01_saturation == "VARIABLE") || (multiplier23_saturation == "VARIABLE"))) + begin + $display("Error: Saturation for multiplier is not supported in %s device family", intended_device_family); + $stop; + end + + if ((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") && + (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO")) + begin + if (int_width_result != width_result) + begin + $display ("Error: Internal parameter setting of int_width_result is illegal"); + $stop; + end + + if (int_mult_diff_bit != 0) + begin + $display ("Error: Internal parameter setting of int_mult_diff_bit is illegal"); + $stop; + end + + end + else + begin + if (((width_a < 18) && (int_width_a != 18)) || + ((width_a >= 18) && (int_width_a != width_a))) + begin + $display ("Error: Internal parameter setting of int_width_a is illegal"); + $stop; + end + + + if (((width_b < 18) && (int_width_b != 18)) || + ((width_b >= 18) && (int_width_b != width_b))) + begin + $display ("Error: Internal parameter setting of int_width_b is illegal"); + $stop; + end + + + if (int_width_result > (int_width_a + int_width_b)) + begin + if (int_width_result != (width_result + width_result - int_width_a - int_width_b)) + begin + $display ("Error: Internal parameter setting for int_width_result is illegal"); + $stop; + end + end + else + if (int_width_result != (int_width_a + int_width_b)) + begin + $display ("Error: Internal parameter setting for int_width_result is illegal"); + $stop; + end + + if (int_mult_diff_bit != (int_width_a - width_a + int_width_b - width_b)) + begin + $display ("Error: Internal parameter setting of int_mult_diff_bit is illegal"); + $stop; + end + end + + + + temp_sum_reg = 0; + + mult_a_reg = 0; + mult_b_reg = 0; + mult_res_reg = 0; + + sign_a_reg = ((port_signa == "PORT_CONNECTIVITY")? + (representation_a != "UNUSED" ? (representation_a == "SIGNED" ? 1 : 0) : 0) : + (port_signa == "PORT_USED")? 0 : + (port_signa == "PORT_UNUSED")? (representation_a == "SIGNED" ? 1 : 0) : 0); + + sign_a_pipe_reg = ((port_signa == "PORT_CONNECTIVITY")? + (representation_a != "UNUSED" ? (representation_a == "SIGNED" ? 1 : 0) : 0) : + (port_signa == "PORT_USED")? 0 : + (port_signa == "PORT_UNUSED")? (representation_a == "SIGNED" ? 1 : 0) : 0); + + sign_b_reg = ((port_signb == "PORT_CONNECTIVITY")? + (representation_b != "UNUSED" ? (representation_b == "SIGNED" ? 1 : 0) : 0) : + (port_signb == "PORT_USED")? 0 : + (port_signb == "PORT_UNUSED")? (representation_b == "SIGNED" ? 1 : 0) : 0); + + sign_b_pipe_reg = ((port_signb == "PORT_CONNECTIVITY")? + (representation_b != "UNUSED" ? (representation_b == "SIGNED" ? 1 : 0) : 0) : + (port_signb == "PORT_USED")? 0 : + (port_signb == "PORT_UNUSED")? (representation_b == "SIGNED" ? 1 : 0) : 0); + + addsub1_reg = ((port_addnsub1 == "PORT_CONNECTIVITY")? + (multiplier1_direction != "UNUSED" ? (multiplier1_direction == "ADD" ? 1 : 0) : 0) : + (port_addnsub1 == "PORT_USED")? 0 : + (port_addnsub1 == "PORT_UNUSED")? (multiplier1_direction == "ADD" ? 1 : 0) : 0); + + addsub1_pipe_reg = addsub1_reg; + + addsub3_reg = ((port_addnsub3 == "PORT_CONNECTIVITY")? + (multiplier3_direction != "UNUSED" ? (multiplier3_direction == "ADD" ? 1 : 0) : 0) : + (port_addnsub3 == "PORT_USED")? 0 : + (port_addnsub3 == "PORT_UNUSED")? (multiplier3_direction == "ADD" ? 1 : 0) : 0); + + addsub3_pipe_reg = addsub3_reg; + + // StratixII related reg type initialization + + mult0_round_out = 0; + mult0_saturate_out = 0; + mult0_result = 0; + mult0_saturate_overflow = 0; + + mult1_round_out = 0; + mult1_saturate_out = 0; + mult1_result = 0; + mult1_saturate_overflow = 0; + + mult_saturate_overflow_reg [3] = 0; + mult_saturate_overflow_reg [2] = 0; + mult_saturate_overflow_reg [1] = 0; + mult_saturate_overflow_reg [0] = 0; + + mult_saturate_overflow_pipe_reg [3] = 0; + mult_saturate_overflow_pipe_reg [2] = 0; + mult_saturate_overflow_pipe_reg [1] = 0; + mult_saturate_overflow_pipe_reg [0] = 0; + zero_pad = 0; + head_result = 0; + + for ( num_stor = extra_latency; num_stor >= 0; num_stor = num_stor - 1 ) + begin + result_pipe[num_stor] = {int_width_result{1'b0}}; + end + + end // end initialization block + + assign signa_z = signa; + assign signb_z = signb; + assign addnsub1_z = addnsub1; + assign addnsub3_z = addnsub3; + assign scanina_z[width_a - 1 : 0] = scanina[width_a - 1 : 0]; + assign scaninb_z[width_b - 1 : 0] = scaninb[width_b - 1 : 0]; + + always @(dataa or datab) + begin + dataa_reg[(number_of_multipliers * width_a) - 1:0] = dataa[(number_of_multipliers* width_a) -1:0]; + datab_reg[(number_of_multipliers * width_b) - 1: 0] = datab[(number_of_multipliers * width_b) - 1:0]; + end + + assign new_dataa_int[int_width_a - 1:int_width_a - width_a] = (number_of_multipliers >= 1) ? dataa_reg[width_a - 1:0]: {width_a{1'b0}}; + + assign new_dataa_int[(2 * int_width_a) - 1: (2 * int_width_a) - width_a] = (number_of_multipliers >= 2)? dataa_reg[(2 * width_a) - 1: width_a] : {width_a{1'b0}}; + + assign new_dataa_int[(3 * int_width_a) - 1: (3 * int_width_a) - width_a] = (number_of_multipliers >= 3)? dataa_reg[(3 * width_a) - 1:(2 * width_a)] : {width_a{1'b0}}; + + assign new_dataa_int[(4 * int_width_a) - 1: (4 * int_width_a) - width_a] = (number_of_multipliers >= 4) ? dataa_reg[(4 * width_a) - 1:(3 * width_a)] : {width_a{1'b0}}; + + assign new_datab_int[int_width_b - 1:int_width_b - width_b] = (number_of_multipliers >= 1) ? datab_reg[width_b - 1:0]: {width_b{1'b0}}; + + assign new_datab_int[(2 * int_width_b) - 1: (2 * int_width_b) - width_b] = (number_of_multipliers >= 2)? datab_reg[(2 * width_b) - 1:width_b]:{width_b{1'b0}}; + + assign new_datab_int[(3 * int_width_b) - 1: (3 * int_width_b) - width_b] = (number_of_multipliers >= 3)? datab_reg[(3 * width_b) - 1:(2 * width_b)] : {width_b{1'b0}}; + + assign new_datab_int[(4 * int_width_b) - 1: (4 * int_width_b) - width_b] = (number_of_multipliers >= 4) ? datab_reg[(4 * width_b) - 1:(3 * width_b)] : {width_b{1'b0}}; + + + + assign dataa_int[number_of_multipliers * int_width_a-1:0] = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") && + (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? dataa[number_of_multipliers * width_a - 1:0]: + (width_a < 18)? new_dataa_int[number_of_multipliers * int_width_a-1:0] : dataa[number_of_multipliers * width_a - 1:0]); + + assign datab_int[number_of_multipliers * int_width_b-1:0] = (((multiplier01_saturation == "NO") && (multiplier23_saturation == "NO") && + (multiplier01_rounding == "NO") && (multiplier23_rounding == "NO"))? datab[number_of_multipliers * width_b - 1:0]: + (width_b < 18)? new_datab_int[number_of_multipliers * int_width_b - 1:0] : datab[number_of_multipliers * width_b - 1:0]); + + + assign addnsub1_round_pre = addnsub1_round; + assign addnsub3_round_pre = addnsub3_round; + assign mult01_round_pre = mult01_round; + assign mult01_saturate_pre = mult01_saturation; + assign mult23_round_pre = mult23_round; + assign mult23_saturate_pre = mult23_saturation; + + // --------------------------------------------------------- + // This block updates the output port for each multiplier's + // saturation port only if port_mult0_is_saturated is set to used + // --------------------------------------------------------- + + + assign mult0_is_saturated = (port_mult0_is_saturated == "UNUSED")? 1'bz: + (port_mult0_is_saturated == "USED")? mult_is_saturate_vec[0]: 1'bz; + + assign mult1_is_saturated = (port_mult1_is_saturated == "UNUSED")? 1'bz: + (port_mult1_is_saturated == "USED")? mult_is_saturate_vec[1]: 1'bz; + + assign mult2_is_saturated = (port_mult2_is_saturated == "UNUSED")? 1'bz: + (port_mult2_is_saturated == "USED")? mult_is_saturate_vec[2]: 1'bz; + + assign mult3_is_saturated = (port_mult3_is_saturated == "UNUSED")? 1'bz: + (port_mult3_is_saturated == "USED")? mult_is_saturate_vec[3]: 1'bz; + + assign sourcea_wire[number_of_multipliers - 1 : 0] = sourcea[number_of_multipliers - 1 : 0]; + + assign sourceb_wire[number_of_multipliers - 1 : 0] = sourceb[number_of_multipliers - 1 : 0]; + + + + // --------------------------------------------------------- + // This block updates the internal clock signals accordingly + // every time the global clock signal changes state + // --------------------------------------------------------- + + assign input_reg_a0_wire_clk = (input_register_a0 == "CLOCK0")? clock0: + (input_register_a0 == "UNREGISTERED")? 0: + (input_register_a0 == "CLOCK1")? clock1: + (input_register_a0 == "CLOCK2")? clock2: + (input_register_a0 == "CLOCK3")? clock3: 0; + + + assign input_reg_a1_wire_clk = (input_register_a1 == "CLOCK0")? clock0: + (input_register_a1 == "UNREGISTERED")? 0: + (input_register_a1 == "CLOCK1")? clock1: + (input_register_a1 == "CLOCK2")? clock2: + (input_register_a1 == "CLOCK3")? clock3: 0; + + + assign input_reg_a2_wire_clk = (input_register_a2 == "CLOCK0")? clock0: + (input_register_a2 == "UNREGISTERED")? 0: + (input_register_a2 == "CLOCK1")? clock1: + (input_register_a2 == "CLOCK2")? clock2: + (input_register_a2 == "CLOCK3")? clock3: 0; + + + + assign input_reg_a3_wire_clk = (input_register_a3 == "CLOCK0")? clock0: + (input_register_a3 == "UNREGISTERED")? 0: + (input_register_a3 == "CLOCK1")? clock1: + (input_register_a3 == "CLOCK2")? clock2: + (input_register_a3 == "CLOCK3")? clock3: 0; + + + assign input_reg_b0_wire_clk = (input_register_b0 == "CLOCK0")? clock0: + (input_register_b0 == "UNREGISTERED")? 0: + (input_register_b0 == "CLOCK1")? clock1: + (input_register_b0 == "CLOCK2")? clock2: + (input_register_b0 == "CLOCK3")? clock3: 0; + + + assign input_reg_b1_wire_clk = (input_register_b1 == "CLOCK0")? clock0: + (input_register_b1 == "UNREGISTERED")? 0: + (input_register_b1 == "CLOCK1")? clock1: + (input_register_b1 == "CLOCK2")? clock2: + (input_register_b1 == "CLOCK3")? clock3: 0; + + + assign input_reg_b2_wire_clk = (input_register_b2 == "CLOCK0")? clock0: + (input_register_b2 == "UNREGISTERED")? 0: + (input_register_b2 == "CLOCK1")? clock1: + (input_register_b2 == "CLOCK2")? clock2: + (input_register_b2 == "CLOCK3")? clock3: 0; + + + assign input_reg_b3_wire_clk = (input_register_b3 == "CLOCK0")? clock0: + (input_register_b3 == "UNREGISTERED")? 0: + (input_register_b3 == "CLOCK1")? clock1: + (input_register_b3 == "CLOCK2")? clock2: + (input_register_b3 == "CLOCK3")? clock3: 0; + + + assign addsub1_reg_wire_clk = (addnsub_multiplier_register1 == "CLOCK0")? clock0: + (addnsub_multiplier_register1 == "UNREGISTERED")? 0: + (addnsub_multiplier_register1 == "CLOCK1")? clock1: + (addnsub_multiplier_register1 == "CLOCK2")? clock2: + (addnsub_multiplier_register1 == "CLOCK3")? clock3: 0; + + + assign addsub1_pipe_wire_clk = (addnsub_multiplier_pipeline_register1 == "CLOCK0")? clock0: + (addnsub_multiplier_pipeline_register1 == "UNREGISTERED")? 0: + (addnsub_multiplier_pipeline_register1 == "CLOCK1")? clock1: + (addnsub_multiplier_pipeline_register1 == "CLOCK2")? clock2: + (addnsub_multiplier_pipeline_register1 == "CLOCK3")? clock3: 0; + + + + assign addsub3_reg_wire_clk = (addnsub_multiplier_register3 == "CLOCK0")? clock0: + (addnsub_multiplier_register3 == "UNREGISTERED")? 0: + (addnsub_multiplier_register3 == "CLOCK1")? clock1: + (addnsub_multiplier_register3 == "CLOCK2")? clock2: + (addnsub_multiplier_register3 == "CLOCK3")? clock3: 0; + + + + assign addsub3_pipe_wire_clk = (addnsub_multiplier_pipeline_register3 == "CLOCK0")? clock0: + (addnsub_multiplier_pipeline_register3 == "UNREGISTERED")? 0: + (addnsub_multiplier_pipeline_register3 == "CLOCK1")? clock1: + (addnsub_multiplier_pipeline_register3 == "CLOCK2")? clock2: + (addnsub_multiplier_pipeline_register3 == "CLOCK3")? clock3: 0; + + + + + assign sign_reg_a_wire_clk = (signed_register_a == "CLOCK0")? clock0: + (signed_register_a == "UNREGISTERED")? 0: + (signed_register_a == "CLOCK1")? clock1: + (signed_register_a == "CLOCK2")? clock2: + (signed_register_a == "CLOCK3")? clock3: 0; + + + + assign sign_pipe_a_wire_clk = (signed_pipeline_register_a == "CLOCK0")? clock0: + (signed_pipeline_register_a == "UNREGISTERED")? 0: + (signed_pipeline_register_a == "CLOCK1")? clock1: + (signed_pipeline_register_a == "CLOCK2")? clock2: + (signed_pipeline_register_a == "CLOCK3")? clock3: 0; + + + + assign sign_reg_b_wire_clk = (signed_register_b == "CLOCK0")? clock0: + (signed_register_b == "UNREGISTERED")? 0: + (signed_register_b == "CLOCK1")? clock1: + (signed_register_b == "CLOCK2")? clock2: + (signed_register_b == "CLOCK3")? clock3: 0; + + + + assign sign_pipe_b_wire_clk = (signed_pipeline_register_b == "CLOCK0")? clock0: + (signed_pipeline_register_b == "UNREGISTERED")? 0: + (signed_pipeline_register_b == "CLOCK1")? clock1: + (signed_pipeline_register_b == "CLOCK2")? clock2: + (signed_pipeline_register_b == "CLOCK3")? clock3: 0; + + + + assign multiplier_reg0_wire_clk = (multiplier_register0 == "CLOCK0")? clock0: + (multiplier_register0 == "UNREGISTERED")? 0: + (multiplier_register0 == "CLOCK1")? clock1: + (multiplier_register0 == "CLOCK2")? clock2: + (multiplier_register0 == "CLOCK3")? clock3: 0; + + + + assign multiplier_reg1_wire_clk = (multiplier_register1 == "CLOCK0")? clock0: + (multiplier_register1 == "UNREGISTERED")? 0: + (multiplier_register1 == "CLOCK1")? clock1: + (multiplier_register1 == "CLOCK2")? clock2: + (multiplier_register1 == "CLOCK3")? clock3: 0; + + + assign multiplier_reg2_wire_clk = (multiplier_register2 == "CLOCK0")? clock0: + (multiplier_register2 == "UNREGISTERED")? 0: + (multiplier_register2 == "CLOCK1")? clock1: + (multiplier_register2 == "CLOCK2")? clock2: + (multiplier_register2 == "CLOCK3")? clock3: 0; + + + + assign multiplier_reg3_wire_clk = (multiplier_register3 == "CLOCK0")? clock0: + (multiplier_register3 == "UNREGISTERED")? 0: + (multiplier_register3 == "CLOCK1")? clock1: + (multiplier_register3 == "CLOCK2")? clock2: + (multiplier_register3 == "CLOCK3")? clock3: 0; + + + + assign output_reg_wire_clk = (output_register == "CLOCK0")? clock0: + (output_register == "UNREGISTERED")? 0: + (output_register == "CLOCK1")? clock1: + (output_register == "CLOCK2")? clock2: + (output_register == "CLOCK3")? clock3: 0; + + + assign addnsub1_round_wire_clk = (addnsub1_round_register == "CLOCK0")? clock0: + (addnsub1_round_register == "UNREGISTERED")? 0: + (addnsub1_round_register == "CLOCK1")? clock1: + (addnsub1_round_register == "CLOCK2")? clock2: + (addnsub1_round_register == "CLOCK3")? clock3: 0; + + + assign addnsub1_round_pipe_wire_clk = (addnsub1_round_pipeline_register == "CLOCK0")? clock0: + (addnsub1_round_pipeline_register == "UNREGISTERED")? 0: + (addnsub1_round_pipeline_register == "CLOCK1")? clock1: + (addnsub1_round_pipeline_register == "CLOCK2")? clock2: + (addnsub1_round_pipeline_register == "CLOCK3")? clock3: 0; + + + assign addnsub3_round_wire_clk = (addnsub3_round_register == "CLOCK0")? clock0: + (addnsub3_round_register == "UNREGISTERED")? 0: + (addnsub3_round_register == "CLOCK1")? clock1: + (addnsub3_round_register == "CLOCK2")? clock2: + (addnsub3_round_register == "CLOCK3")? clock3: 0; + + assign addnsub3_round_pipe_wire_clk = (addnsub3_round_pipeline_register == "CLOCK0")? clock0: + (addnsub3_round_pipeline_register == "UNREGISTERED")? 0: + (addnsub3_round_pipeline_register == "CLOCK1")? clock1: + (addnsub3_round_pipeline_register == "CLOCK2")? clock2: + (addnsub3_round_pipeline_register == "CLOCK3")? clock3: 0; + + assign mult01_round_wire_clk = (mult01_round_register == "CLOCK0")? clock0: + (mult01_round_register == "UNREGISTERED")? 0: + (mult01_round_register == "CLOCK1")? clock1: + (mult01_round_register == "CLOCK2")? clock2: + (mult01_round_register == "CLOCK3")? clock3: 0; + + + assign mult01_saturate_wire_clk = (mult01_saturation_register == "CLOCK0")? clock0: + (mult01_saturation_register == "UNREGISTERED")? 0: + (mult01_saturation_register == "CLOCK1")? clock1: + (mult01_saturation_register == "CLOCK2")? clock2: + (mult01_saturation_register == "CLOCK3")? clock3: 0; + + + assign mult23_round_wire_clk = (mult23_round_register == "CLOCK0")? clock0: + (mult23_round_register == "UNREGISTERED")? 0: + (mult23_round_register == "CLOCK1")? clock1: + (mult23_round_register == "CLOCK2")? clock2: + (mult23_round_register == "CLOCK3")? clock3: 0; + + assign mult23_saturate_wire_clk = (mult23_saturation_register == "CLOCK0")? clock0: + (mult23_saturation_register == "UNREGISTERED")? 0: + (mult23_saturation_register == "CLOCK1")? clock1: + (mult23_saturation_register == "CLOCK2")? clock2: + (mult23_saturation_register == "CLOCK3")? clock3: 0; + + + + // ---------------------------------------------------------------- + // This block updates the internal clock enable signals accordingly + // every time the global clock enable signal changes state + // ---------------------------------------------------------------- + + + assign input_reg_a0_wire_en = (input_register_a0 == "CLOCK0")? ena0: + (input_register_a0 == "UNREGISTERED")? 1: + (input_register_a0 == "CLOCK1")? ena1: + (input_register_a0 == "CLOCK2")? ena2: + (input_register_a0 == "CLOCK3")? ena3: 1; + + + + assign input_reg_a1_wire_en = (input_register_a1 == "CLOCK0")? ena0: + (input_register_a1 == "UNREGISTERED")? 1: + (input_register_a1 == "CLOCK1")? ena1: + (input_register_a1 == "CLOCK2")? ena2: + (input_register_a1 == "CLOCK3")? ena3: 1; + + + assign input_reg_a2_wire_en = (input_register_a2 == "CLOCK0")? ena0: + (input_register_a2 == "UNREGISTERED")? 1: + (input_register_a2 == "CLOCK1")? ena1: + (input_register_a2 == "CLOCK2")? ena2: + (input_register_a2 == "CLOCK3")? ena3: 1; + + + assign input_reg_a3_wire_en = (input_register_a3 == "CLOCK0")? ena0: + (input_register_a3 == "UNREGISTERED")? 1: + (input_register_a3 == "CLOCK1")? ena1: + (input_register_a3 == "CLOCK2")? ena2: + (input_register_a3 == "CLOCK3")? ena3: 1; + + + assign input_reg_b0_wire_en = (input_register_b0 == "CLOCK0")? ena0: + (input_register_b0 == "UNREGISTERED")? 1: + (input_register_b0 == "CLOCK1")? ena1: + (input_register_b0 == "CLOCK2")? ena2: + (input_register_b0 == "CLOCK3")? ena3: 1; + + + + assign input_reg_b1_wire_en = (input_register_b1 == "CLOCK0")? ena0: + (input_register_b1 == "UNREGISTERED")? 1: + (input_register_b1 == "CLOCK1")? ena1: + (input_register_b1 == "CLOCK2")? ena2: + (input_register_b1 == "CLOCK3")? ena3: 1; + + + assign input_reg_b2_wire_en = (input_register_b2 == "CLOCK0")? ena0: + (input_register_b2 == "UNREGISTERED")? 1: + (input_register_b2 == "CLOCK1")? ena1: + (input_register_b2 == "CLOCK2")? ena2: + (input_register_b2 == "CLOCK3")? ena3: 1; + + assign input_reg_b3_wire_en = (input_register_b3 == "CLOCK0")? ena0: + (input_register_b3 == "UNREGISTERED")? 1: + (input_register_b3 == "CLOCK1")? ena1: + (input_register_b3 == "CLOCK2")? ena2: + (input_register_b3 == "CLOCK3")? ena3: 1; + + + assign addsub1_reg_wire_en = (addnsub_multiplier_register1 == "CLOCK0")? ena0: + (addnsub_multiplier_register1 == "UNREGISTERED")? 1: + (addnsub_multiplier_register1 == "CLOCK1")? ena1: + (addnsub_multiplier_register1 == "CLOCK2")? ena2: + (addnsub_multiplier_register1 == "CLOCK3")? ena3: 1; + + + + assign addsub1_pipe_wire_en = (addnsub_multiplier_pipeline_register1 == "CLOCK0")? ena0: + (addnsub_multiplier_pipeline_register1 == "UNREGISTERED")? 1: + (addnsub_multiplier_pipeline_register1 == "CLOCK1")? ena1: + (addnsub_multiplier_pipeline_register1 == "CLOCK2")? ena2: + (addnsub_multiplier_pipeline_register1 == "CLOCK3")? ena3: 1; + + + assign addsub3_reg_wire_en = (addnsub_multiplier_register3 == "CLOCK0")? ena0: + (addnsub_multiplier_register3 == "UNREGISTERED")? 1: + (addnsub_multiplier_register3 == "CLOCK1")? ena1: + (addnsub_multiplier_register3 == "CLOCK2")? ena2: + (addnsub_multiplier_register3 == "CLOCK3")? ena3: 1; + + + + assign addsub3_pipe_wire_en = (addnsub_multiplier_pipeline_register3 == "CLOCK0")? ena0: + (addnsub_multiplier_pipeline_register3 == "UNREGISTERED")? 1: + (addnsub_multiplier_pipeline_register3 == "CLOCK1")? ena1: + (addnsub_multiplier_pipeline_register3 == "CLOCK2")? ena2: + (addnsub_multiplier_pipeline_register3 == "CLOCK3")? ena3: 1; + + + + assign sign_reg_a_wire_en = (signed_register_a == "CLOCK0")? ena0: + (signed_register_a == "UNREGISTERED")? 1: + (signed_register_a == "CLOCK1")? ena1: + (signed_register_a == "CLOCK2")? ena2: + (signed_register_a == "CLOCK3")? ena3: 1; + + + + assign sign_pipe_a_wire_en = (signed_pipeline_register_a == "CLOCK0")? ena0: + (signed_pipeline_register_a == "UNREGISTERED")? 1: + (signed_pipeline_register_a == "CLOCK1")? ena1: + (signed_pipeline_register_a == "CLOCK2")? ena2: + (signed_pipeline_register_a == "CLOCK3")? ena3: 1; + + + + assign sign_reg_b_wire_en = (signed_register_b == "CLOCK0")? ena0: + (signed_register_b == "UNREGISTERED")? 1: + (signed_register_b == "CLOCK1")? ena1: + (signed_register_b == "CLOCK2")? ena2: + (signed_register_b == "CLOCK3")? ena3: 1; + + + + assign sign_pipe_b_wire_en = (signed_pipeline_register_b == "CLOCK0")? ena0: + (signed_pipeline_register_b == "UNREGISTERED")? 1: + (signed_pipeline_register_b == "CLOCK1")? ena1: + (signed_pipeline_register_b == "CLOCK2")? ena2: + (signed_pipeline_register_b == "CLOCK3")? ena3: 1; + + + + assign multiplier_reg0_wire_en = (multiplier_register0 == "CLOCK0")? ena0: + (multiplier_register0 == "UNREGISTERED")? 1: + (multiplier_register0 == "CLOCK1")? ena1: + (multiplier_register0 == "CLOCK2")? ena2: + (multiplier_register0 == "CLOCK3")? ena3: 1; + + + + assign multiplier_reg1_wire_en = (multiplier_register1 == "CLOCK0")? ena0: + (multiplier_register1 == "UNREGISTERED")? 1: + (multiplier_register1 == "CLOCK1")? ena1: + (multiplier_register1 == "CLOCK2")? ena2: + (multiplier_register1 == "CLOCK3")? ena3: 1; + + + assign multiplier_reg2_wire_en = (multiplier_register2 == "CLOCK0")? ena0: + (multiplier_register2 == "UNREGISTERED")? 1: + (multiplier_register2 == "CLOCK1")? ena1: + (multiplier_register2 == "CLOCK2")? ena2: + (multiplier_register2 == "CLOCK3")? ena3: 1; + + + + assign multiplier_reg3_wire_en = (multiplier_register3 == "CLOCK0")? ena0: + (multiplier_register3 == "UNREGISTERED")? 1: + (multiplier_register3 == "CLOCK1")? ena1: + (multiplier_register3 == "CLOCK2")? ena2: + (multiplier_register3 == "CLOCK3")? ena3: 1; + + + + assign output_reg_wire_en = (output_register == "CLOCK0")? ena0: + (output_register == "UNREGISTERED")? 1: + (output_register == "CLOCK1")? ena1: + (output_register == "CLOCK2")? ena2: + (output_register == "CLOCK3")? ena3: 1; + + + assign addnsub1_round_wire_en = (addnsub1_round_register == "CLOCK0")? ena0: + (addnsub1_round_register == "UNREGISTERED")? 1: + (addnsub1_round_register == "CLOCK1")? ena1: + (addnsub1_round_register == "CLOCK2")? ena2: + (addnsub1_round_register == "CLOCK3")? ena3: 1; + + + assign addnsub1_round_pipe_wire_en = (addnsub1_round_pipeline_register == "CLOCK0")? ena0: + (addnsub1_round_pipeline_register == "UNREGISTERED")? 1: + (addnsub1_round_pipeline_register == "CLOCK1")? ena1: + (addnsub1_round_pipeline_register == "CLOCK2")? ena2: + (addnsub1_round_pipeline_register == "CLOCK3")? ena3: 1; + + + assign addnsub3_round_wire_en = (addnsub3_round_register == "CLOCK0")? ena0: + (addnsub3_round_register == "UNREGISTERED")? 1: + (addnsub3_round_register == "CLOCK1")? ena1: + (addnsub3_round_register == "CLOCK2")? ena2: + (addnsub3_round_register == "CLOCK3")? ena3: 1; + + + assign addnsub3_round_pipe_wire_en = (addnsub3_round_pipeline_register == "CLOCK0")? ena0: + (addnsub3_round_pipeline_register == "UNREGISTERED")? 1: + (addnsub3_round_pipeline_register == "CLOCK1")? ena1: + (addnsub3_round_pipeline_register == "CLOCK2")? ena2: + (addnsub3_round_pipeline_register == "CLOCK3")? ena3: 1; + + + assign mult01_round_wire_en = (mult01_round_register == "CLOCK0")? ena0: + (mult01_round_register == "UNREGISTERED")? 1: + (mult01_round_register == "CLOCK1")? ena1: + (mult01_round_register == "CLOCK2")? ena2: + (mult01_round_register == "CLOCK3")? ena3: 1; + + + assign mult01_saturate_wire_en = (mult01_saturation_register == "CLOCK0")? ena0: + (mult01_saturation_register == "UNREGISTERED")? 1: + (mult01_saturation_register == "CLOCK1")? ena1: + (mult01_saturation_register == "CLOCK2")? ena2: + (mult01_saturation_register == "CLOCK3")? ena3: 1; + + + assign mult23_round_wire_en = (mult23_round_register == "CLOCK0")? ena0: + (mult23_round_register == "UNREGISTERED")? 1: + (mult23_round_register == "CLOCK1")? ena1: + (mult23_round_register == "CLOCK2")? ena2: + (mult23_round_register == "CLOCK3")? ena3: 1; + + + assign mult23_saturate_wire_en = (mult23_saturation_register == "CLOCK0")? ena0: + (mult23_saturation_register == "UNREGISTERED")? 1: + (mult23_saturation_register == "CLOCK1")? ena1: + (mult23_saturation_register == "CLOCK2")? ena2: + (mult23_saturation_register == "CLOCK3")? ena3: 1; + + + // --------------------------------------------------------- + // This block updates the internal clear signals accordingly + // every time the global clear signal changes state + // --------------------------------------------------------- + + assign input_reg_a0_wire_clr = (input_aclr_a0 == "ACLR3")? aclr3: + (input_aclr_a0 == "UNREGISTERED")? 0: + (input_aclr_a0 == "ACLR0")? aclr0: + (input_aclr_a0 == "ACLR1")? aclr1: + (input_aclr_a0 == "ACLR2")? aclr2: 0; + + + + assign input_reg_a1_wire_clr = (input_aclr_a1 == "ACLR3")? aclr3: + (input_aclr_a1 == "UNREGISTERED")? 0: + (input_aclr_a1 == "ACLR0")? aclr0: + (input_aclr_a1 == "ACLR1")? aclr1: + (input_aclr_a1 == "ACLR2")? aclr2: 0; + + + assign input_reg_a2_wire_clr = (input_aclr_a2 == "ACLR3")? aclr3: + (input_aclr_a2 == "UNREGISTERED")? 0: + (input_aclr_a2 == "ACLR0")? aclr0: + (input_aclr_a2 == "ACLR1")? aclr1: + (input_aclr_a2 == "ACLR2")? aclr2: 0; + + + + assign input_reg_a3_wire_clr = (input_aclr_a3 == "ACLR3")? aclr3: + (input_aclr_a3 == "UNREGISTERED")? 0: + (input_aclr_a3 == "ACLR0")? aclr0: + (input_aclr_a3 == "ACLR1")? aclr1: + (input_aclr_a3 == "ACLR2")? aclr2: 0; + + + assign input_reg_b0_wire_clr = (input_aclr_b0 == "ACLR3")? aclr3: + (input_aclr_b0 == "UNREGISTERED")? 0: + (input_aclr_b0 == "ACLR0")? aclr0: + (input_aclr_b0 == "ACLR1")? aclr1: + (input_aclr_b0 == "ACLR2")? aclr2: 0; + + + assign input_reg_b1_wire_clr = (input_aclr_b1 == "ACLR3")? aclr3: + (input_aclr_b1 == "UNREGISTERED")? 0: + (input_aclr_b1 == "ACLR0")? aclr0: + (input_aclr_b1 == "ACLR1")? aclr1: + (input_aclr_b1 == "ACLR2")? aclr2: 0; + + + assign input_reg_b2_wire_clr = (input_aclr_b2 == "ACLR3")? aclr3: + (input_aclr_b2 == "UNREGISTERED")? 0: + (input_aclr_b2 == "ACLR0")? aclr0: + (input_aclr_b2 == "ACLR1")? aclr1: + (input_aclr_b2 == "ACLR2")? aclr2: 0; + + + + assign input_reg_b3_wire_clr = (input_aclr_b3 == "ACLR3")? aclr3: + (input_aclr_b3 == "UNREGISTERED")? 0: + (input_aclr_b3 == "ACLR0")? aclr0: + (input_aclr_b3 == "ACLR1")? aclr1: + (input_aclr_b3 == "ACLR2")? aclr2: 0; + + + + + assign addsub1_reg_wire_clr = (addnsub_multiplier_aclr1 == "ACLR3")? aclr3: + (addnsub_multiplier_aclr1 == "UNREGISTERED")? 0: + (addnsub_multiplier_aclr1 == "ACLR0")? aclr0: + (addnsub_multiplier_aclr1 == "ACLR1")? aclr1: + (addnsub_multiplier_aclr1 == "ACLR2")? aclr2: 0; + + + + assign addsub1_pipe_wire_clr = (addnsub_multiplier_pipeline_aclr1 == "ACLR3")? aclr3: + (addnsub_multiplier_pipeline_aclr1 == "UNREGISTERED")? 0: + (addnsub_multiplier_pipeline_aclr1 == "ACLR0")? aclr0: + (addnsub_multiplier_pipeline_aclr1 == "ACLR1")? aclr1: + (addnsub_multiplier_pipeline_aclr1 == "ACLR2")? aclr2: 0; + + + + + assign addsub3_reg_wire_clr = (addnsub_multiplier_aclr3 == "ACLR3")? aclr3: + (addnsub_multiplier_aclr3 == "UNREGISTERED")? 0: + (addnsub_multiplier_aclr3 == "ACLR0")? aclr0: + (addnsub_multiplier_aclr3 == "ACLR1")? aclr1: + (addnsub_multiplier_aclr3 == "ACLR2")? aclr2: 0; + + + + assign addsub3_pipe_wire_clr = (addnsub_multiplier_pipeline_aclr3 == "ACLR3")? aclr3: + (addnsub_multiplier_pipeline_aclr3 == "UNREGISTERED")? 0: + (addnsub_multiplier_pipeline_aclr3 == "ACLR0")? aclr0: + (addnsub_multiplier_pipeline_aclr3 == "ACLR1")? aclr1: + (addnsub_multiplier_pipeline_aclr3 == "ACLR2")? aclr2: 0; + + + + + assign sign_reg_a_wire_clr = (signed_aclr_a == "ACLR3")? aclr3: + (signed_aclr_a == "UNREGISTERED")? 0: + (signed_aclr_a == "ACLR0")? aclr0: + (signed_aclr_a == "ACLR1")? aclr1: + (signed_aclr_a == "ACLR2")? aclr2: 0; + + + + assign sign_pipe_a_wire_clr = (signed_pipeline_aclr_a == "ACLR3")? aclr3: + (signed_pipeline_aclr_a == "UNREGISTERED")? 0: + (signed_pipeline_aclr_a == "ACLR0")? aclr0: + (signed_pipeline_aclr_a == "ACLR1")? aclr1: + (signed_pipeline_aclr_a == "ACLR2")? aclr2: 0; + + + + assign sign_reg_b_wire_clr = (signed_aclr_b == "ACLR3")? aclr3: + (signed_aclr_b == "UNREGISTERED")? 0: + (signed_aclr_b == "ACLR0")? aclr0: + (signed_aclr_b == "ACLR1")? aclr1: + (signed_aclr_b == "ACLR2")? aclr2: 0; + + + + assign sign_pipe_b_wire_clr = (signed_pipeline_aclr_b == "ACLR3")? aclr3: + (signed_pipeline_aclr_b == "UNREGISTERED")? 0: + (signed_pipeline_aclr_b == "ACLR0")? aclr0: + (signed_pipeline_aclr_b == "ACLR1")? aclr1: + (signed_pipeline_aclr_b == "ACLR2")? aclr2: 0; + + + + + assign multiplier_reg0_wire_clr = (multiplier_aclr0 == "ACLR3")? aclr3: + (multiplier_aclr0 == "UNREGISTERED")? 0: + (multiplier_aclr0 == "ACLR0")? aclr0: + (multiplier_aclr0 == "ACLR1")? aclr1: + (multiplier_aclr0 == "ACLR2")? aclr2: 0; + + + + assign multiplier_reg1_wire_clr = (multiplier_aclr1 == "ACLR3")? aclr3: + (multiplier_aclr1 == "UNREGISTERED")? 0: + (multiplier_aclr1 == "ACLR0")? aclr0: + (multiplier_aclr1 == "ACLR1")? aclr1: + (multiplier_aclr1 == "ACLR2")? aclr2: 0; + + + + assign multiplier_reg2_wire_clr = (multiplier_aclr2 == "ACLR3")? aclr3: + (multiplier_aclr2 == "UNREGISTERED")? 0: + (multiplier_aclr2 == "ACLR0")? aclr0: + (multiplier_aclr2 == "ACLR1")? aclr1: + (multiplier_aclr2 == "ACLR2")? aclr2: 0; + + + + + assign multiplier_reg3_wire_clr = (multiplier_aclr3 == "ACLR3")? aclr3: + (multiplier_aclr3 == "UNREGISTERED")? 0: + (multiplier_aclr3 == "ACLR0")? aclr0: + (multiplier_aclr3 == "ACLR1")? aclr1: + (multiplier_aclr3 == "ACLR2")? aclr2: 0; + + + + + assign output_reg_wire_clr = (output_aclr == "ACLR3")? aclr3: + (output_aclr == "UNREGISTERED")? 0: + (output_aclr == "ACLR0")? aclr0: + (output_aclr == "ACLR1")? aclr1: + (output_aclr == "ACLR2")? aclr2: 0; + + + + assign addnsub1_round_wire_clr = (addnsub1_round_aclr == "ACLR3")? aclr3: + (addnsub1_round_register == "UNREGISTERED")? 0: + (addnsub1_round_aclr == "ACLR0")? aclr0: + (addnsub1_round_aclr == "ACLR1")? aclr1: + (addnsub1_round_aclr == "ACLR2")? aclr2: 0; + + + + assign addnsub1_round_pipe_wire_clr = (addnsub1_round_pipeline_aclr == "ACLR3")? aclr3: + (addnsub1_round_pipeline_register == "UNREGISTERED")? 0: + (addnsub1_round_pipeline_aclr == "ACLR0")? aclr0: + (addnsub1_round_pipeline_aclr == "ACLR1")? aclr1: + (addnsub1_round_pipeline_aclr == "ACLR2")? aclr2: 0; + + + + assign addnsub3_round_wire_clr = (addnsub3_round_aclr == "ACLR3")? aclr3: + (addnsub3_round_register == "UNREGISTERED")? 0: + (addnsub3_round_aclr == "ACLR0")? aclr0: + (addnsub3_round_aclr == "ACLR1")? aclr1: + (addnsub3_round_aclr == "ACLR2")? aclr2: 0; + + + + assign addnsub3_round_pipe_wire_clr = (addnsub3_round_pipeline_aclr == "ACLR3")? aclr3: + (addnsub3_round_pipeline_register == "UNREGISTERED")? 0: + (addnsub3_round_pipeline_aclr == "ACLR0")? aclr0: + (addnsub3_round_pipeline_aclr == "ACLR1")? aclr1: + (addnsub3_round_pipeline_aclr == "ACLR2")? aclr2: 0; + + + + assign mult01_round_wire_clr = (mult01_round_aclr == "ACLR3")? aclr3: + (mult01_round_register == "UNREGISTERED")? 0: + (mult01_round_aclr == "ACLR0")? aclr0: + (mult01_round_aclr == "ACLR1")? aclr1: + (mult01_round_aclr == "ACLR2")? aclr2: 0; + + + + assign mult01_saturate_wire_clr = (mult01_saturation_aclr == "ACLR3")? aclr3: + (mult01_saturation_register == "UNREGISTERED")? 0: + (mult01_saturation_aclr == "ACLR0")? aclr0: + (mult01_saturation_aclr == "ACLR1")? aclr1: + (mult01_saturation_aclr == "ACLR2")? aclr2: 0; + + + + assign mult23_round_wire_clr = (mult23_round_aclr == "ACLR3")? aclr3: + (mult23_round_register == "UNREGISTERED")? 0: + (mult23_round_aclr == "ACLR0")? aclr0: + (mult23_round_aclr == "ACLR1")? aclr1: + (mult23_round_aclr == "ACLR2")? aclr2: 0; + + + + assign mult23_saturate_wire_clr = (mult23_saturation_aclr == "ACLR3")? aclr3: + (mult23_saturation_register == "UNREGISTERED")? 0: + (mult23_saturation_aclr == "ACLR0")? aclr0: + (mult23_saturation_aclr == "ACLR1")? aclr1: + (mult23_saturation_aclr == "ACLR2")? aclr2: 0; + + + + // ------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_a[int_width_a-1:0]) + // Signal Registered : mult_a_pre[int_width_a-1:0] + // + // Register is controlled by posedge input_reg_a0_wire_clk + // Register has a clock enable input_reg_a0_wire_en + // Register has an asynchronous clear signal, input_reg_a0_wire_clr + // NOTE : The combinatorial block will be executed if + // input_register_a0 is unregistered and mult_a_pre[int_width_a-1:0] changes value + // ------------------------------------------------------------------------------------- + assign mult_a_wire[int_width_a-1:0] = (input_register_a0 == "UNREGISTERED")? + mult_a_pre[int_width_a-1:0]: mult_a_reg[int_width_a-1:0]; + always @(posedge input_reg_a0_wire_clk or posedge input_reg_a0_wire_clr) + begin + if (input_reg_a0_wire_clr == 1) + mult_a_reg[int_width_a-1:0] <= 0; + else if ((input_reg_a0_wire_clk === 1'b1) && (input_reg_a0_wire_en == 1)) + mult_a_reg[int_width_a-1:0] <= mult_a_pre[int_width_a-1:0]; + end + + + // ----------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_a[(2*int_width_a)-1:int_width_a]) + // Signal Registered : mult_a_pre[(2*int_width_a)-1:int_width_a] + // + // Register is controlled by posedge input_reg_a1_wire_clk + // Register has a clock enable input_reg_a1_wire_en + // Register has an asynchronous clear signal, input_reg_a1_wire_clr + // NOTE : The combinatorial block will be executed if + // input_register_a1 is unregistered and mult_a_pre[(2*int_width_a)-1:int_width_a] changes value + // ----------------------------------------------------------------------------------------------- + + assign mult_a_wire[(2*int_width_a)-1:int_width_a] = (input_register_a1 == "UNREGISTERED")? + mult_a_pre[(2*int_width_a)-1:int_width_a]: mult_a_reg[(2*int_width_a)-1:int_width_a]; + + always @(posedge input_reg_a1_wire_clk or posedge input_reg_a1_wire_clr) + + begin + if (input_reg_a1_wire_clr == 1) + mult_a_reg[(2*int_width_a)-1:int_width_a] <= 0; + else if ((input_reg_a1_wire_clk == 1) && (input_reg_a1_wire_en == 1)) + mult_a_reg[(2*int_width_a)-1:int_width_a] <= mult_a_pre[(2*int_width_a)-1:int_width_a]; + end + + + // ------------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_a[(3*int_width_a)-1:2*int_width_a]) + // Signal Registered : mult_a_pre[(3*int_width_a)-1:2*int_width_a] + // + // Register is controlled by posedge input_reg_a2_wire_clk + // Register has a clock enable input_reg_a2_wire_en + // Register has an asynchronous clear signal, input_reg_a2_wire_clr + // NOTE : The combinatorial block will be executed if + // input_register_a2 is unregistered and mult_a_pre[(3*int_width_a)-1:2*int_width_a] changes value + // ------------------------------------------------------------------------------------------------- + assign mult_a_wire[(3*int_width_a)-1 : 2*int_width_a ] = (input_register_a2 == "UNREGISTERED")? + mult_a_pre[(3*int_width_a)-1 : 2*int_width_a]: mult_a_reg[(3*int_width_a)-1 : 2*int_width_a ]; + + + always @(posedge input_reg_a2_wire_clk or posedge input_reg_a2_wire_clr) + begin + if (input_reg_a2_wire_clr == 1) + mult_a_reg[(3*int_width_a)-1 : 2*int_width_a ] <= 0; + else if ((input_reg_a2_wire_clk == 1) && (input_reg_a2_wire_en == 1)) + mult_a_reg[(3*int_width_a)-1 : 2*int_width_a ] <= mult_a_pre[(3*int_width_a)-1 : 2*int_width_a]; + end + + + // ------------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_a[(4*int_width_a)-1:3*int_width_a]) + // Signal Registered : mult_a_pre[(4*int_width_a)-1:3*int_width_a] + // + // Register is controlled by posedge input_reg_a3_wire_clk + // Register has a clock enable input_reg_a3_wire_en + // Register has an asynchronous clear signal, input_reg_a3_wire_clr + // NOTE : The combinatorial block will be executed if + // input_register_a3 is unregistered and mult_a_pre[(4*int_width_a)-1:3*int_width_a] changes value + // ------------------------------------------------------------------------------------------------- + assign mult_a_wire[(4*int_width_a)-1 : 3*int_width_a ] = (input_register_a3 == "UNREGISTERED")? + mult_a_pre[(4*int_width_a)-1:3*int_width_a]: mult_a_reg[(4*int_width_a)-1:3*int_width_a]; + + always @(posedge input_reg_a3_wire_clk or posedge input_reg_a3_wire_clr) + begin + if (input_reg_a3_wire_clr == 1) + mult_a_reg[(4*int_width_a)-1 : 3*int_width_a ] <= 0; + else if ((input_reg_a3_wire_clk == 1) && (input_reg_a3_wire_en == 1)) + mult_a_reg[(4*int_width_a)-1 : 3*int_width_a ] <= mult_a_pre[(4*int_width_a)-1:3*int_width_a]; + + end + + + // ------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_b[int_width_b-1:0]) + // Signal Registered : mult_b_pre[int_width_b-1:0] + // + // Register is controlled by posedge input_reg_b0_wire_clk + // Register has a clock enable input_reg_b0_wire_en + // Register has an asynchronous clear signal, input_reg_b0_wire_clr + // NOTE : The combinatorial block will be executed if + // input_register_b0 is unregistered and mult_b_pre[int_width_b-1:0] changes value + // ------------------------------------------------------------------------------------- + + assign mult_b_wire[int_width_b-1:0] = (input_register_b0 == "UNREGISTERED")? + mult_b_pre[int_width_b-1:0]: mult_b_reg[int_width_b-1:0]; + + always @(posedge input_reg_b0_wire_clk or posedge input_reg_b0_wire_clr) + begin + if (input_reg_b0_wire_clr == 1) + mult_b_reg[int_width_b-1:0] <= 0; + else if ((input_reg_b0_wire_clk == 1) && (input_reg_b0_wire_en == 1)) + mult_b_reg[int_width_b-1:0] <= mult_b_pre[int_width_b-1:0]; + end + + + // ----------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_b[(2*int_width_b)-1:int_width_b]) + // Signal Registered : mult_b_pre[(2*int_width_b)-1:int_width_b] + // + // Register is controlled by posedge input_reg_a1_wire_clk + // Register has a clock enable input_reg_b1_wire_en + // Register has an asynchronous clear signal, input_reg_b1_wire_clr + // NOTE : The combinatorial block will be executed if + // input_register_b1 is unregistered and mult_b_pre[(2*int_width_b)-1:int_width_b] changes value + // ----------------------------------------------------------------------------------------------- + assign mult_b_wire[(2*int_width_b)-1:int_width_b] = (input_register_b1 == "UNREGISTERED")? + mult_b_pre[(2*int_width_b)-1:int_width_b]: mult_b_reg[(2*int_width_b)-1:int_width_b]; + + + + always @(posedge input_reg_b1_wire_clk or posedge input_reg_b1_wire_clr) + begin + if (input_reg_b1_wire_clr == 1) + mult_b_reg[(2*int_width_b)-1:int_width_b] <= 0; + else if ((input_reg_b1_wire_clk == 1) && (input_reg_b1_wire_en == 1)) + mult_b_reg[(2*int_width_b)-1:int_width_b] <= mult_b_pre[(2*int_width_b)-1:int_width_b]; + + end + + + // ------------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_b[(3*int_width_b)-1:2*int_width_b]) + // Signal Registered : mult_b_pre[(3*int_width_b)-1:2*int_width_b] + // + // Register is controlled by posedge input_reg_b2_wire_clk + // Register has a clock enable input_reg_b2_wire_en + // Register has an asynchronous clear signal, input_reg_b2_wire_clr + // NOTE : The combinatorial block will be executed if + // input_register_b2 is unregistered and mult_b_pre[(3*int_width_b)-1:2*int_width_b] changes value + // ------------------------------------------------------------------------------------------------- + assign mult_b_wire[(3*int_width_b)-1:2*int_width_b] = (input_register_b2 == "UNREGISTERED")? + mult_b_pre[(3*int_width_b)-1:2*int_width_b]: mult_b_reg[(3*int_width_b)-1:2*int_width_b]; + + + always @(posedge input_reg_b2_wire_clk or posedge input_reg_b2_wire_clr) + begin + if (input_reg_b2_wire_clr == 1) + mult_b_reg[(3*int_width_b)-1:2*int_width_b] <= 0; + else if ((input_reg_b2_wire_clk == 1) && (input_reg_b2_wire_en == 1)) + mult_b_reg[(3*int_width_b)-1:2*int_width_b] <= mult_b_pre[(3*int_width_b)-1:2*int_width_b]; + + end + + + // ------------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult_b[(4*int_width_b)-1:3*int_width_b]) + // Signal Registered : mult_b_pre[(4*int_width_b)-1:3*int_width_b] + // + // Register is controlled by posedge input_reg_b3_wire_clk + // Register has a clock enable input_reg_b3_wire_en + // Register has an asynchronous clear signal, input_reg_b3_wire_clr + // NOTE : The combinatorial block will be executed if + // input_register_b3 is unregistered and mult_b_pre[(4*int_width_b)-1:3*int_width_b] changes value + // ------------------------------------------------------------------------------------------------- + assign mult_b_wire[(4*int_width_b)-1:3*int_width_b] = (input_register_b3 == "UNREGISTERED")? + mult_b_pre[(4*int_width_b)-1:3*int_width_b]: mult_b_reg[(4*int_width_b)-1:3*int_width_b]; + + + always @(posedge input_reg_b3_wire_clk or posedge input_reg_b3_wire_clr) + begin + if (input_reg_b3_wire_clr == 1) + mult_b_reg[(4*int_width_b)-1 : 3*int_width_b ] <= 0; + else if ((input_reg_b3_wire_clk == 1) && (input_reg_b3_wire_en == 1)) + mult_b_reg[(4*int_width_b)-1:3*int_width_b] <= mult_b_pre[(4*int_width_b)-1:3*int_width_b]; + + end + + // ------------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult01_round_wire) + // Signal Registered : mult01_round_pre + // + // Register is controlled by posedge mult01_round_wire_clk + // Register has a clock enable mult01_round_wire_en + // Register has an asynchronous clear signal, mult01_round_wire_clr + // NOTE : The combinatorial block will be executed if + // mult01_round_register is unregistered and mult01_round changes value + // ------------------------------------------------------------------------------------------------- + assign mult01_round_wire = (mult01_round_register == "UNREGISTERED")? + mult01_round_pre : mult01_round_reg; + + always @(posedge mult01_round_wire_clk or posedge mult01_round_wire_clr) + begin + if (mult01_round_wire_clr == 1) + mult01_round_reg <= 0; + else if ((mult01_round_wire_clk == 1) && (mult01_round_wire_en == 1)) + mult01_round_reg <= mult01_round_pre; + + end + + // ------------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult01_saturate_wire) + // Signal Registered : mult01_saturation_pre + // + // Register is controlled by posedge mult01_saturate_wire_clk + // Register has a clock enable mult01_saturate_wire_en + // Register has an asynchronous clear signal, mult01_saturate_wire_clr + // NOTE : The combinatorial block will be executed if + // mult01_saturation_register is unregistered and mult01_saturate_pre changes value + // ------------------------------------------------------------------------------------------------- + assign mult01_saturate_wire = (mult01_saturation_register == "UNREGISTERED")? + mult01_saturate_pre : mult01_saturate_reg; + + always @(posedge mult01_saturate_wire_clk or posedge mult01_saturate_wire_clr) + begin + if (mult01_saturate_wire_clr == 1) + mult01_saturate_reg <= 0; + else if ((mult01_saturate_wire_clk == 1) && (mult01_saturate_wire_en == 1)) + mult01_saturate_reg <= mult01_saturate_pre; + + end + + // ------------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult23_round_wire) + // Signal Registered : mult23_round_pre + // + // Register is controlled by posedge mult23_round_wire_clk + // Register has a clock enable mult23_round_wire_en + // Register has an asynchronous clear signal, mult23_round_wire_clr + // NOTE : The combinatorial block will be executed if + // mult23_round_register is unregistered and mult23_round_pre changes value + // ------------------------------------------------------------------------------------------------- + assign mult23_round_wire = (mult23_round_register == "UNREGISTERED")? + mult23_round_pre : mult23_round_reg; + + always @(posedge mult23_round_wire_clk or posedge mult23_round_wire_clr) + begin + if (mult23_round_wire_clr == 1) + mult23_round_reg <= 0; + else if ((mult23_round_wire_clk == 1) && (mult23_round_wire_en == 1)) + mult23_round_reg <= mult23_round_pre; + + end + + // ------------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set mult23_saturate_wire) + // Signal Registered : mult23_round_pre + // + // Register is controlled by posedge mult23_saturate_wire_clk + // Register has a clock enable mult23_saturate_wire_en + // Register has an asynchronous clear signal, mult23_saturate_wire_clr + // NOTE : The combinatorial block will be executed if + // mult23_saturation_register is unregistered and mult23_saturation_pre changes value + // ------------------------------------------------------------------------------------------------- + assign mult23_saturate_wire = (mult23_saturation_register == "UNREGISTERED")? + mult23_saturate_pre : mult23_saturate_reg; + + always @(posedge mult23_saturate_wire_clk or posedge mult23_saturate_wire_clr) + begin + if (mult23_saturate_wire_clr == 1) + mult23_saturate_reg <= 0; + else if ((mult23_saturate_wire_clk == 1) && (mult23_saturate_wire_en == 1)) + mult23_saturate_reg <= mult23_saturate_pre; + + end + + // --------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addnsub1_round_wire) + // Signal Registered : addnsub1_round_pre + // + // Register is controlled by posedge addnsub1_round_wire_clk + // Register has a clock enable addnsub1_round_wire_en + // Register has an asynchronous clear signal, addnsub1_round_wire_clr + // NOTE : The combinatorial block will be executed if + // addnsub1_round_register is unregistered and addnsub1_round_pre changes value + // --------------------------------------------------------------------------------- + assign addnsub1_round_wire = (addnsub1_round_register=="UNREGISTERED")? + addnsub1_round_pre : addnsub1_round_reg; + + always @(posedge addnsub1_round_wire_clk or posedge addnsub1_round_wire_clr) + begin + if (addnsub1_round_wire_clr == 1) + addnsub1_round_reg <= 0; + else if ((addnsub1_round_wire_clk == 1) && (addnsub1_round_wire_en == 1)) + addnsub1_round_reg <= addnsub1_round_pre; + end + + // --------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addnsub1_round_pipe_wire) + // Signal Registered : addnsub1_round_wire + // + // Register is controlled by posedge addnsub1_round_pipe_wire_clk + // Register has a clock enable addnsub1_round_pipe_wire_en + // Register has an asynchronous clear signal, addnsub1_round_wire_clr + // NOTE : The combinatorial block will be executed if + // addnsub1_round_pipeline_register is unregistered and addnsub1_round_wire changes value + // --------------------------------------------------------------------------------- + assign addnsub1_round_pipe_wire = (addnsub1_round_pipeline_register=="UNREGISTERED")? + addnsub1_round_wire : addnsub1_round_pipe_reg; + + always @(posedge addnsub1_round_pipe_wire_clk or posedge addnsub1_round_pipe_wire_clr) + begin + if (addnsub1_round_pipe_wire_clr == 1) + addnsub1_round_pipe_reg <= 0; + else if ((addnsub1_round_pipe_wire_clk == 1) && (addnsub1_round_pipe_wire_en == 1)) + addnsub1_round_pipe_reg <= addnsub1_round_wire; + end + + // --------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addnsub3_round_wire) + // Signal Registered : addnsub3_round_pre + // + // Register is controlled by posedge addnsub3_round_wire_clk + // Register has a clock enable addnsub3_round_wire_en + // Register has an asynchronous clear signal, addnsub3_round_wire_clr + // NOTE : The combinatorial block will be executed if + // addnsub3_round_register is unregistered and addnsub3_round_pre changes value + // --------------------------------------------------------------------------------- + assign addnsub3_round_wire = (addnsub3_round_register=="UNREGISTERED")? + addnsub3_round_pre : addnsub3_round_reg; + + always @(posedge addnsub3_round_wire_clk or posedge addnsub3_round_wire_clr) + begin + if (addnsub3_round_wire_clr == 1) + addnsub3_round_reg <= 0; + else if ((addnsub3_round_wire_clk == 1) && (addnsub3_round_wire_en == 1)) + addnsub3_round_reg <= addnsub3_round_pre; + end + + // --------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addnsub3_round_pipe_wire) + // Signal Registered : addnsub3_round_wire + // + // Register is controlled by posedge addnsub3_round_pipe_wire_clk + // Register has a clock enable addnsub3_round_pipe_wire_en + // Register has an asynchronous clear signal, addnsub3_round_wire_clr + // NOTE : The combinatorial block will be executed if + // addnsub3_round_pipeline_register is unregistered and addnsub3_round_wire changes value + // --------------------------------------------------------------------------------- + assign addnsub3_round_pipe_wire = (addnsub3_round_pipeline_register=="UNREGISTERED")? + addnsub3_round_wire : addnsub3_round_pipe_reg; + + always @(posedge addnsub3_round_pipe_wire_clk or posedge addnsub3_round_pipe_wire_clr) + begin + if (addnsub3_round_pipe_wire_clr == 1) + addnsub3_round_pipe_reg <= 0; + else if ((addnsub3_round_pipe_wire_clk == 1) && (addnsub3_round_pipe_wire_en == 1)) + addnsub3_round_pipe_reg <= addnsub3_round_wire; + end + + + // --------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addsub1_reg) + // Signal Registered : addsub1_int + // + // Register is controlled by posedge addsub1_reg_wire_clk + // Register has a clock enable addsub1_reg_wire_en + // Register has an asynchronous clear signal, addsub1_reg_wire_clr + // NOTE : The combinatorial block will be executed if + // addnsub_multiplier_register1 is unregistered and addsub1_int changes value + // --------------------------------------------------------------------------------- + assign addsub1_wire = (addnsub_multiplier_register1=="UNREGISTERED")? addsub1_int : addsub1_reg; + + always @(posedge addsub1_reg_wire_clk or posedge addsub1_reg_wire_clr) + begin + if ((addsub1_reg_wire_clr == 1) && (multiplier1_direction == "UNUSED")) + addsub1_reg <= 0; + else if ((addsub1_reg_wire_clk == 1) && (addsub1_reg_wire_en == 1)) + addsub1_reg <= addsub1_int; + end + + + // ------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addsub1_pipe) + // Signal Registered : addsub1_reg + // + // Register is controlled by posedge addsub1_pipe_wire_clk + // Register has a clock enable addsub1_pipe_wire_en + // Register has an asynchronous clear signal, addsub1_pipe_wire_clr + // NOTE : The combinatorial block will be executed if + // addnsub_multiplier_pipeline_register1 is unregistered and addsub1_reg changes value + // ------------------------------------------------------------------------------------------ + + assign addsub1_pipe_wire = (addnsub_multiplier_pipeline_register1 == "UNREGISTERED")? + addsub1_wire : addsub1_pipe_reg; + always @(posedge addsub1_pipe_wire_clk or posedge addsub1_pipe_wire_clr) + begin + if ((addsub1_pipe_wire_clr == 1) && (multiplier1_direction == "UNUSED")) + addsub1_pipe_reg <= 0; + else if ((addsub1_pipe_wire_clk == 1) && (addsub1_pipe_wire_en == 1)) + addsub1_pipe_reg <= addsub1_wire; + end + + + // --------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addsub3_reg) + // Signal Registered : addsub3_int + // + // Register is controlled by posedge addsub3_reg_wire_clk + // Register has a clock enable addsub3_reg_wire_en + // Register has an asynchronous clear signal, addsub3_reg_wire_clr + // NOTE : The combinatorial block will be executed if + // addnsub_multiplier_register3 is unregistered and addsub3_int changes value + // --------------------------------------------------------------------------------- + assign addsub3_wire = (addnsub_multiplier_register3=="UNREGISTERED")? + addsub3_int : addsub3_reg; + + + always @(posedge addsub3_reg_wire_clk or posedge addsub3_reg_wire_clr) + begin + if ((addsub3_reg_wire_clr == 1) && (multiplier3_direction == "UNUSED")) + addsub3_reg <= 0; + else if ((addsub3_reg_wire_clk == 1) && (addsub3_reg_wire_en == 1)) + addsub3_reg <= addsub3_int; + end + + + // ------------------------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set addsub3_pipe) + // Signal Registered : addsub3_reg + // + // Register is controlled by posedge addsub3_pipe_wire_clk + // Register has a clock enable addsub3_pipe_wire_en + // Register has an asynchronous clear signal, addsub3_pipe_wire_clr + // NOTE : The combinatorial block will be executed if + // addnsub_multiplier_pipeline_register3 is unregistered and addsub3_reg changes value + // ------------------------------------------------------------------------------------------ + assign addsub3_pipe_wire = (addnsub_multiplier_pipeline_register3 == "UNREGISTERED")? + addsub3_wire : addsub3_pipe_reg; + + always @(posedge addsub3_pipe_wire_clk or posedge addsub3_pipe_wire_clr) + begin + if ((addsub3_pipe_wire_clr == 1) && (multiplier3_direction == "UNUSED")) + addsub3_pipe_reg <= 0; + else if ((addsub3_pipe_wire_clk == 1) && (addsub3_pipe_wire_en == 1)) + addsub3_pipe_reg <= addsub3_wire; + end + + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set sign_a_reg) + // Signal Registered : sign_a_int + // + // Register is controlled by posedge sign_reg_a_wire_clk + // Register has a clock enable sign_reg_a_wire_en + // Register has an asynchronous clear signal, sign_reg_a_wire_clr + // NOTE : The combinatorial block will be executed if + // signed_register_a is unregistered and sign_a_int changes value + // ---------------------------------------------------------------------------- + + assign sign_a_wire = (signed_register_a == "UNREGISTERED")? sign_a_int : sign_a_reg; + always @(posedge sign_reg_a_wire_clk or posedge sign_reg_a_wire_clr) + begin + if ((sign_reg_a_wire_clr == 1) && (representation_a == "UNUSED")) + sign_a_reg <= 0; + else if ((sign_reg_a_wire_clk == 1) && (sign_reg_a_wire_en == 1)) + sign_a_reg <= sign_a_int; + end + + + // ------------------------------------------------------------------------------ + // This block contains 1 register and 1 combinatorial block (to set sign_a_pipe) + // Signal Registered : sign_a_reg + // + // Register is controlled by posedge sign_pipe_a_wire_clk + // Register has a clock enable sign_pipe_a_wire_en + // Register has an asynchronous clear signal, sign_pipe_a_wire_clr + // NOTE : The combinatorial block will be executed if + // signed_pipeline_register_a is unregistered and sign_a_reg changes value + // ------------------------------------------------------------------------------ + + assign sign_a_pipe_wire = (signed_pipeline_register_a == "UNREGISTERED")? sign_a_wire : sign_a_pipe_reg; + always @(posedge sign_pipe_a_wire_clk or posedge sign_pipe_a_wire_clr) + begin + if ((sign_pipe_a_wire_clr == 1) && (representation_a == "UNUSED")) + sign_a_pipe_reg <= 0; + else if ((sign_pipe_a_wire_clk == 1) && (sign_pipe_a_wire_en == 1)) + sign_a_pipe_reg <= sign_a_wire; + end + + + // ---------------------------------------------------------------------------- + // This block contains 1 register and 1 combinatorial block (to set sign_b_reg) + // Signal Registered : sign_b_int + // + // Register is controlled by posedge sign_reg_b_wire_clk + // Register has a clock enable sign_reg_b_wire_en + // Register has an asynchronous clear signal, sign_reg_b_wire_clr + // NOTE : The combinatorial block will be executed if + // signed_register_b is unregistered and sign_b_int changes value + // ---------------------------------------------------------------------------- + + assign sign_b_wire = (signed_register_b == "UNREGISTERED")? sign_b_int : sign_b_reg; + + always @(posedge sign_reg_b_wire_clk or posedge sign_reg_b_wire_clr) + begin + if ((sign_reg_b_wire_clr == 1) && (representation_b == "UNUSED")) + sign_b_reg <= 0; + else if ((sign_reg_b_wire_clk == 1) && (sign_reg_b_wire_en == 1)) + sign_b_reg <= sign_b_int; + + end + + + // ------------------------------------------------------------------------------ + // This block contains 1 register and 1 combinatorial block (to set sign_b_pipe) + // Signal Registered : sign_b_reg + // + // Register is controlled by posedge sign_pipe_b_wire_clk + // Register has a clock enable sign_pipe_b_wire_en + // Register has an asynchronous clear signal, sign_pipe_b_wire_clr + // NOTE : The combinatorial block will be executed if + // signed_pipeline_register_b is unregistered and sign_b_reg changes value + // ------------------------------------------------------------------------------ + assign sign_b_pipe_wire = (signed_pipeline_register_b == "UNREGISTERED")? sign_b_wire : sign_b_pipe_reg; + always @(posedge sign_pipe_b_wire_clk or posedge sign_pipe_b_wire_clr) + + begin + if ((sign_pipe_b_wire_clr == 1) && (representation_b == "UNUSED")) + sign_b_pipe_reg <= 0; + else if ((sign_pipe_b_wire_clk == 1) && (sign_pipe_b_wire_en == 1)) + sign_b_pipe_reg <= sign_b_wire; + + end + + + // -------------------------------------------------------- + // This block basically calls the task do_multiply() to set + // the value of mult_res_0[(int_width_a + int_width_b) -1 :0] + // + // If multiplier_register0 is registered, the call of the task + // will be triggered by a posedge multiplier_reg0_wire_clk. + // It also has an asynchronous clear signal multiplier_reg0_wire_clr + // + // If multiplier_register0 is unregistered, a change of value + // in either mult_a[int_width_a-1:0], mult_b[int_width_a-1:0], + // sign_a_reg or sign_b_reg will trigger the task call. + // -------------------------------------------------------- + assign mult_res_wire[(int_width_a + int_width_b - 1) :0] = (multiplier_register0 == "UNREGISTERED")? + mult0_result[(int_width_a + int_width_b - 1) :0] : + mult_res_reg[(int_width_a + int_width_b - 1) :0]; + + assign mult_saturate_overflow_vec[0] = (multiplier_register0 == "UNREGISTERED")? + mult0_saturate_overflow : mult_saturate_overflow_reg[0]; + + + // This always block is to perform the rounding and saturation operations (StratixII only) + always @(mult_res_0 or mult01_round_wire or mult01_saturate_wire) + begin + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + // ------------------------------------------------------- + // Stratix II Rounding support + // This block basically carries out the rounding for the + // mult_res_0. The equation to get the mult0_round_out is + // obtained from the Stratix II Mac FFD which is below: + // round_adder_constant = (1 << (wfraction - wfraction_round - 1)) + // roundout[] = datain[] + round_adder_constant + // For Stratix II rounding, we round up the bits to 15 bits + // or in another word wfraction_round = 15. + // -------------------------------------------------------- + + if ((multiplier01_rounding == "YES") || + ((multiplier01_rounding == "VARIABLE") && (mult01_round_wire == 1))) + begin + mult0_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_0[(int_width_a + int_width_b) -1 :0] + ( 1 << (`MULT_ROUND_BITS - 1)); + end + else + begin + mult0_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_0[(int_width_a + int_width_b) -1 :0]; + end + + mult0_round_out[((int_width_a + int_width_b) + 2) : (int_width_a + int_width_b)] = {2{1'b0}}; + + // ------------------------------------------------------- + // Stratix II Saturation support + // This carries out the saturation for mult0_round_out. + // The equation to get the saturated result is obtained + // from Stratix II MAC FFD which is below: + // satoverflow = 1 if sign bit is different + // satvalue[wtotal-1 : wfraction] = roundout[wtotal-1] + // satvalue[wfraction-1 : 0] = !roundout[wtotal-1] + // ------------------------------------------------------- + + if ((multiplier01_saturation == "YES") || + (( multiplier01_saturation == "VARIABLE") && (mult01_saturate_wire == 1))) + begin + + mult0_saturate_overflow_stat = (~mult0_round_out[int_width_a + int_width_b - 1]) && mult0_round_out[int_width_a + int_width_b - 2]; + + if (mult0_saturate_overflow_stat == 0) + begin + mult0_saturate_out = mult0_round_out; + mult0_saturate_overflow = mult0_round_out[0]; + end + else + begin + + // We are doing Q2.31 saturation + for (num_bit_mult0 = (int_width_a + int_width_b - 1); num_bit_mult0 >= (int_width_a + int_width_b - 2); num_bit_mult0 = num_bit_mult0 - 1) + begin + mult0_saturate_out[num_bit_mult0] = mult0_round_out[int_width_a + int_width_b - 1]; + end + + for (num_bit_mult0 = sat_ini_value; num_bit_mult0 >= 3; num_bit_mult0 = num_bit_mult0 - 1) + begin + mult0_saturate_out[num_bit_mult0] = ~mult0_round_out[int_width_a + int_width_b - 1]; + end + + mult0_saturate_out[2 : 0] = mult0_round_out[2:0]; + + mult0_saturate_overflow = mult0_saturate_overflow_stat; + end + end + else + begin + mult0_saturate_out = mult0_round_out; + mult0_saturate_overflow = 1'b0; + end + + if ((multiplier01_rounding == "YES") || + ((multiplier01_rounding == "VARIABLE") && (mult01_round_wire == 1))) + begin + + for (num_bit_mult0 = (`MULT_ROUND_BITS - 1); num_bit_mult0 >= 0; num_bit_mult0 = num_bit_mult0 - 1) + begin + mult0_saturate_out[num_bit_mult0] = 1'b0; + end + + end + end + end + + always @(mult0_saturate_out or mult_res_0) + begin + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + mult0_result <= mult0_saturate_out[(int_width_a + int_width_b) -1 :0]; + end + else + begin + mult0_result <= mult_res_0; + end + + end + + + + always @(posedge multiplier_reg0_wire_clk or posedge multiplier_reg0_wire_clr) + begin + if (multiplier_reg0_wire_clr == 1) + begin + mult_res_reg[(int_width_a + int_width_b) -1 :0] <= 0; + mult_saturate_overflow_reg[0] <= 0; + end + else if ((multiplier_reg0_wire_clk == 1) && (multiplier_reg0_wire_en == 1)) + begin + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) + mult_res_reg[(int_width_a + int_width_b) - 1 : 0] <= mult_res_0[(int_width_a + int_width_b) -1 :0]; + else + begin + mult_res_reg[(int_width_a + int_width_b - 1) : 0] <= mult0_result; + mult_saturate_overflow_reg[0] <= mult0_saturate_overflow; + end + end + end + + + + always @(mult_a_wire[(int_width_a *1) -1 : (int_width_a*0)] or mult_b_wire[(int_width_b *1) -1 : (int_width_b *0)] or + sign_a_wire or sign_b_wire) + begin + mult_res_0 = do_multiply (0, sign_a_wire, sign_b_wire); + end + + + + + // ------------------------------------------------------------------------ + // This block basically calls the task do_multiply() to set the value of + // mult_res_1[(int_width_a + int_width_b) -1 :0] + // + // If multiplier_register1 is registered, the call of the task + // will be triggered by a posedge multiplier_reg1_wire_clk. + // It also has an asynchronous clear signal multiplier_reg1_wire_clr + // + // If multiplier_register1 is unregistered, a change of value + // in either mult_a[(2*int_width_a)-1:int_width_a], mult_b[(2*int_width_a)-1:int_width_a], + // sign_a_reg or sign_b_reg will trigger the task call. + // ----------------------------------------------------------------------- + + assign mult_res_wire[(((int_width_a + int_width_b) *2) - 1) : (int_width_a + int_width_b)] = (multiplier_register1 == "UNREGISTERED")? + mult1_result[(int_width_a + int_width_b - 1) : 0]: + mult_res_reg[((int_width_a + int_width_b) *2) - 1: (int_width_a + int_width_b)]; + + assign mult_saturate_overflow_vec[1] = (multiplier_register1 == "UNREGISTERED")? + mult1_saturate_overflow : mult_saturate_overflow_reg[1]; + + + // This always block is to perform the rounding and saturation operations (StratixII only) + always @(mult_res_1 or mult01_round_wire or mult01_saturate_wire) + begin + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + // ------------------------------------------------------- + // Stratix II Rounding support + // This block basically carries out the rounding for the + // mult_res_1. The equation to get the mult1_round_out is + // obtained from the Stratix II Mac FFD which is below: + // round_adder_constant = (1 << (wfraction - wfraction_round - 1)) + // roundout[] = datain[] + round_adder_constant + // For Stratix II rounding, we round up the bits to 15 bits + // or in another word wfraction_round = 15. + // -------------------------------------------------------- + + if ((multiplier01_rounding == "YES") || + ((multiplier01_rounding == "VARIABLE") && (mult01_round_wire == 1))) + begin + mult1_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_1[(int_width_a + int_width_b) -1 :0] + ( 1 << (`MULT_ROUND_BITS - 1)); + end + else + begin + mult1_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_1[(int_width_a + int_width_b) -1 :0]; + end + + mult1_round_out[((int_width_a + int_width_b) + 2) : (int_width_a + int_width_b)] = {2{1'b0}}; + + + // ------------------------------------------------------- + // Stratix II Saturation support + // This carries out the saturation for mult1_round_out. + // The equation to get the saturated result is obtained + // from Stratix II MAC FFD which is below: + // satoverflow = 1 if sign bit is different + // satvalue[wtotal-1 : wfraction] = roundout[wtotal-1] + // satvalue[wfraction-1 : 0] = !roundout[wtotal-1] + // ------------------------------------------------------- + + + if ((multiplier01_saturation == "YES") || + (( multiplier01_saturation == "VARIABLE") && (mult01_saturate_wire == 1))) + begin + mult1_saturate_overflow_stat = (~mult1_round_out[int_width_a + int_width_b - 1]) && mult1_round_out[int_width_a + int_width_b - 2]; + + if (mult1_saturate_overflow_stat == 0) + begin + mult1_saturate_out = mult1_round_out; + mult1_saturate_overflow = mult1_round_out[0]; + end + else + begin + // We are doing Q2.31 saturation. Thus we would insert additional bit + // for the LSB + for (num_bit_mult1 = (int_width_a + int_width_b - 1); num_bit_mult1 >= (int_width_a + int_width_b - 2); num_bit_mult1 = num_bit_mult1 - 1) + begin + mult1_saturate_out[num_bit_mult1] = mult1_round_out[int_width_a + int_width_b - 1]; + end + + for (num_bit_mult1 = sat_ini_value; num_bit_mult1 >= 3; num_bit_mult1 = num_bit_mult1 - 1) + begin + mult1_saturate_out[num_bit_mult1] = ~mult1_round_out[int_width_a + int_width_b - 1]; + end + + mult1_saturate_out[2:0] = mult1_round_out[2:0]; + mult1_saturate_overflow = mult1_saturate_overflow_stat; + end + end + else + begin + mult1_saturate_out = mult1_round_out; + mult1_saturate_overflow = 1'b0; + end + + if ((multiplier01_rounding == "YES") || + ((multiplier01_rounding == "VARIABLE") && (mult01_round_wire == 1))) + begin + + for (num_bit_mult1 = (`MULT_ROUND_BITS - 1); num_bit_mult1 >= 0; num_bit_mult1 = num_bit_mult1 - 1) + begin + mult1_saturate_out[num_bit_mult1] = 1'b0; + end + + end + end + end + + always @(mult1_saturate_out or mult_res_1) + begin + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + mult1_result <= mult1_saturate_out[(int_width_a + int_width_b) -1 :0]; + end + else + begin + mult1_result <= mult_res_1; + end + end + + + always @(posedge multiplier_reg1_wire_clk or posedge multiplier_reg1_wire_clr) + begin + if (multiplier_reg1_wire_clr == 1) + begin + mult_res_reg[((int_width_a + int_width_b) *2) -1 : (int_width_a + int_width_b)] <= 0; + mult_saturate_overflow_reg[1] <= 0; + end + else if ((multiplier_reg1_wire_clk == 1) && (multiplier_reg1_wire_en == 1)) + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) + mult_res_reg[((int_width_a + int_width_b) *2) -1 : (int_width_a + int_width_b)] <= + mult_res_1[(int_width_a + int_width_b) -1 :0]; + else + begin + mult_res_reg[((int_width_a + int_width_b) *2) -1 : (int_width_a + int_width_b)] <= mult1_result; + mult_saturate_overflow_reg[1] <= mult1_saturate_overflow; + end + end + + + always @(mult_a_wire[(int_width_a *2) -1 : (int_width_a*1)] or mult_b_wire[(int_width_b *2) -1 : (int_width_b *1)] or + sign_a_wire or sign_b_wire) + begin + + mult_res_1 = do_multiply (1, sign_a_wire, sign_b_wire); + end + + + + + + // ---------------------------------------------------------------------------- + // This block basically calls the task do_multiply() to set the value of + // mult_res_2[(int_width_a + int_width_b) -1 :0] + // + // If multiplier_register2 is registered, the call of the task + // will be triggered by a posedge multiplier_reg2_wire_clk. + // It also has an asynchronous clear signal multiplier_reg2_wire_clr + // + // If multiplier_register2 is unregistered, a change of value + // in either mult_a[(3*int_width_a)-1:2*int_width_a], mult_b[(3*int_width_a)-1:2*int_width_a], + // sign_a_reg or sign_b_reg will trigger the task call. + // --------------------------------------------------------------------------- + + assign mult_res_wire[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))] = (multiplier_register2 == "UNREGISTERED")? + mult2_result[(int_width_a + int_width_b) -1 :0] : + mult_res_reg[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))]; + + assign mult_saturate_overflow_vec[2] = (multiplier_register2 == "UNREGISTERED")? + mult2_saturate_overflow : mult_saturate_overflow_reg[2]; + + // This always block is to perform the rounding and saturation operations (StratixII only) + always @(mult_res_2 or mult23_round_wire or mult23_saturate_wire) + begin + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + // ------------------------------------------------------- + // Stratix II Rounding support + // This block basically carries out the rounding for the + // mult_res_2. The equation to get the mult2_round_out is + // obtained from the Stratix II Mac FFD which is below: + // round_adder_constant = (1 << (wfraction - wfraction_round - 1)) + // roundout[] = datain[] + round_adder_constant + // For Stratix II rounding, we round up the bits to 15 bits + // or in another word wfraction_round = 15. + // -------------------------------------------------------- + + if ((multiplier23_rounding == "YES") || + ((multiplier23_rounding == "VARIABLE") && (mult23_round_wire == 1))) + begin + mult2_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_2[(int_width_a + int_width_b) -1 :0] + ( 1 << (`MULT_ROUND_BITS - 1)); + end + else + begin + mult2_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_2[(int_width_a + int_width_b) -1 :0]; + end + + mult2_round_out[((int_width_a + int_width_b) + 2) : (int_width_a + int_width_b)] = {2{1'b0}}; + + // ------------------------------------------------------- + // Stratix II Saturation support + // This carries out the saturation for mult2_round_out. + // The equation to get the saturated result is obtained + // from Stratix II MAC FFD which is below: + // satoverflow = 1 if sign bit is different + // satvalue[wtotal-1 : wfraction] = roundout[wtotal-1] + // satvalue[wfraction-1 : 0] = !roundout[wtotal-1] + // ------------------------------------------------------- + + + if ((multiplier23_saturation == "YES") || + (( multiplier23_saturation == "VARIABLE") && (mult23_saturate_wire == 1))) + begin + mult2_saturate_overflow_stat = (~mult2_round_out[int_width_a + int_width_b - 1]) && mult2_round_out[int_width_a + int_width_b - 2]; + + if (mult2_saturate_overflow_stat == 0) + begin + mult2_saturate_out = mult2_round_out; + mult2_saturate_overflow = mult2_round_out[0]; + end + else + begin + // We are doing Q2.31 saturation. Thus we would insert additional bit + // for the LSB + for (num_bit_mult2 = (int_width_a + int_width_b - 1); num_bit_mult2 >= (int_width_a + int_width_b - 2); num_bit_mult2 = num_bit_mult2 - 1) + begin + mult2_saturate_out[num_bit_mult2] = mult2_round_out[int_width_a + int_width_b - 1]; + end + + for (num_bit_mult2 = sat_ini_value; num_bit_mult2 >= 3; num_bit_mult2 = num_bit_mult2 - 1) + begin + mult2_saturate_out[num_bit_mult2] = ~mult2_round_out[int_width_a + int_width_b - 1]; + end + + mult2_saturate_out[2:0] = mult2_round_out[2:0]; + mult2_saturate_overflow = mult2_saturate_overflow_stat; + end + end + else + begin + mult2_saturate_out = mult2_round_out; + mult2_saturate_overflow = 1'b0; + end + + if ((multiplier23_rounding == "YES") || + ((multiplier23_rounding == "VARIABLE") && (mult23_round_wire == 1))) + begin + + for (num_bit_mult2 = (`MULT_ROUND_BITS - 1); num_bit_mult2 >= 0; num_bit_mult2 = num_bit_mult2 - 1) + begin + mult2_saturate_out[num_bit_mult2] = 1'b0; + end + + end + end + end + + always @(mult2_saturate_out or mult_res_2) + begin + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + mult2_result <= mult2_saturate_out[(int_width_a + int_width_b) -1 :0]; + end + else + begin + mult2_result <= mult_res_2; + end + end + + + always @(posedge multiplier_reg2_wire_clk or posedge multiplier_reg2_wire_clr) + begin + if (multiplier_reg2_wire_clr == 1) + begin + mult_res_reg[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))] <= 0; + mult_saturate_overflow_reg[2] <= 0; + end + else if ((multiplier_reg2_wire_clk == 1) && (multiplier_reg2_wire_en == 1)) + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) + mult_res_reg[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))] <= + mult_res_2[(int_width_a + int_width_b) -1 :0]; + else + begin + mult_res_reg[((int_width_a + int_width_b) *3) -1 : (2*(int_width_a + int_width_b))] <= mult2_result; + mult_saturate_overflow_reg[2] <= mult2_saturate_overflow; + end + end + + always @(mult_a_wire[(int_width_a *3) -1 : (int_width_a*2)] or mult_b_wire[(int_width_b *3) -1 : (int_width_b *2)] or + sign_a_wire or sign_b_wire) + begin + mult_res_2 = do_multiply (2, sign_a_wire, sign_b_wire); + end + + + + + // ---------------------------------------------------------------------------- + // This block basically calls the task do_multiply() to set the value of + // mult_res_3[(int_width_a + int_width_b) -1 :0] + // + // If multiplier_register3 is registered, the call of the task + // will be triggered by a posedge multiplier_reg3_wire_clk. + // It also has an asynchronous clear signal multiplier_reg3_wire_clr + // + // If multiplier_register3 is unregistered, a change of value + // in either mult_a[(4*int_width_a)-1:3*int_width_a], mult_b[(4*int_width_a)-1:3*int_width_a], + // sign_a_reg or sign_b_reg will trigger the task call. + // --------------------------------------------------------------------------- + + assign mult_res_wire[((int_width_a + int_width_b) *4) -1 : 3*(int_width_a + int_width_b)] = (multiplier_register3 == "UNREGISTERED")? + mult3_result[(int_width_a + int_width_b) -1 :0] : + mult_res_reg[((int_width_a + int_width_b) *4) -1 : 3*(int_width_a + int_width_b)]; + + assign mult_saturate_overflow_vec[3] = (multiplier_register3 == "UNREGISTERED")? + mult3_saturate_overflow : mult_saturate_overflow_reg[3]; + + // This always block is to perform the rounding and saturation operations (StratixII only) + always @(mult_res_3 or mult23_round_wire or mult23_saturate_wire) + begin + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + // ------------------------------------------------------- + // Stratix II Rounding support + // This block basically carries out the rounding for the + // mult_res_3. The equation to get the mult3_round_out is + // obtained from the Stratix II Mac FFD which is below: + // round_adder_constant = (1 << (wfraction - wfraction_round - 1)) + // roundout[] = datain[] + round_adder_constant + // For Stratix II rounding, we round up the bits to 15 bits + // or in another word wfraction_round = 15. + // -------------------------------------------------------- + + if ((multiplier23_rounding == "YES") || + ((multiplier23_rounding == "VARIABLE") && (mult23_round_wire == 1))) + begin + mult3_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_3[(int_width_a + int_width_b) -1 :0] + ( 1 << (`MULT_ROUND_BITS - 1)); + end + else + begin + mult3_round_out[(int_width_a + int_width_b) -1 :0] = mult_res_3[(int_width_a + int_width_b) -1 :0]; + end + + mult3_round_out[((int_width_a + int_width_b) + 2) : (int_width_a + int_width_b)] = {2{1'b0}}; + + // ------------------------------------------------------- + // Stratix II Saturation support + // This carries out the saturation for mult3_round_out. + // The equation to get the saturated result is obtained + // from Stratix II MAC FFD which is below: + // satoverflow = 1 if sign bit is different + // satvalue[wtotal-1 : wfraction] = roundout[wtotal-1] + // satvalue[wfraction-1 : 0] = !roundout[wtotal-1] + // ------------------------------------------------------- + + + if ((multiplier23_saturation == "YES") || + (( multiplier23_saturation == "VARIABLE") && (mult23_saturate_wire == 1))) + begin + mult3_saturate_overflow_stat = (~mult3_round_out[int_width_a + int_width_b - 1]) && mult3_round_out[int_width_a + int_width_b - 2]; + + if (mult3_saturate_overflow_stat == 0) + begin + mult3_saturate_out = mult3_round_out; + mult3_saturate_overflow = mult3_round_out[0]; + end + else + begin + // We are doing Q2.31 saturation. Thus we would make sure the 3 LSB bits isn't reset + for (num_bit_mult3 = (int_width_a + int_width_b -1); num_bit_mult3 >= (int_width_a + int_width_b - 2); num_bit_mult3 = num_bit_mult3 - 1) + begin + mult3_saturate_out[num_bit_mult3] = mult3_round_out[int_width_a + int_width_b - 1]; + end + + for (num_bit_mult3 = sat_ini_value; num_bit_mult3 >= 3; num_bit_mult3 = num_bit_mult3 - 1) + begin + mult3_saturate_out[num_bit_mult3] = ~mult3_round_out[int_width_a + int_width_b - 1]; + end + + mult3_saturate_out[2:0] = mult3_round_out[2:0]; + mult3_saturate_overflow = mult3_saturate_overflow_stat; + end + end + else + begin + mult3_saturate_out = mult3_round_out; + mult3_saturate_overflow = 1'b0; + end + + if ((multiplier23_rounding == "YES") || + ((multiplier23_rounding == "VARIABLE") && (mult23_round_wire == 1))) + begin + + for (num_bit_mult3 = (`MULT_ROUND_BITS - 1); num_bit_mult3 >= 0; num_bit_mult3 = num_bit_mult3 - 1) + begin + mult3_saturate_out[num_bit_mult3] = 1'b0; + end + + end + end + end + + always @(mult3_saturate_out or mult_res_3) + begin + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + mult3_result <= mult3_saturate_out[(int_width_a + int_width_b) -1 :0]; + end + else + begin + mult3_result <= mult_res_3; + end + end + + + always @(posedge multiplier_reg3_wire_clk or posedge multiplier_reg3_wire_clr) + begin + if (multiplier_reg3_wire_clr == 1) + begin + mult_res_reg[((int_width_a + int_width_b) *4) -1 : (3*(int_width_a + int_width_b))] <= 0; + mult_saturate_overflow_reg[3] <= 0; + end + else if ((multiplier_reg3_wire_clk == 1) && (multiplier_reg3_wire_en == 1)) + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0) + mult_res_reg[((int_width_a + int_width_b) *4) -1 : (3*(int_width_a + int_width_b))] <= + mult_res_3[(int_width_a + int_width_b) -1 :0]; + else + begin + mult_res_reg[((int_width_a + int_width_b) *4) -1: 3*(int_width_a + int_width_b)] <= mult3_result; + mult_saturate_overflow_reg[3] <= mult3_saturate_overflow; + end + + end + + + + + always @(mult_a_wire[(int_width_a *4) -1 : (int_width_a*3)] or mult_b_wire[(int_width_b *4) -1 : (int_width_b *3)] or + sign_a_wire or sign_b_wire) + begin + mult_res_3 = do_multiply (3, sign_a_wire, sign_b_wire); + end + + + //------------------------------ + // Continuous assign statements + //------------------------------ + + // Clock in all the A input registers + assign i_scanina = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0)? + dataa_int[int_width_a-1:0] : scanina_z; + + assign mult_a_pre[int_width_a-1:0] = (input_source_a0 == "DATAA")? dataa_int[int_width_a-1:0] : + (input_source_a0 == "SCANA")? i_scanina : + (sourcea_wire[0] == 1)? scanina_z : dataa_int[int_width_a-1:0]; + + assign mult_a_pre[(2*int_width_a)-1:int_width_a] = (input_source_a1 == "DATAA") ? dataa_int[(2*int_width_a)-1:int_width_a] : + (input_source_a1 == "SCANA")? mult_a_wire[int_width_a-1:0] : + (sourcea_wire[1] == 1)? mult_a_wire[int_width_a-1:0] : dataa_int[(2*int_width_a)-1:int_width_a]; + + assign mult_a_pre[(3*int_width_a)-1:2*int_width_a] = (input_source_a2 == "DATAA") ? dataa_int[(3*int_width_a)-1:2*int_width_a] : + (input_source_a2 == "SCANA")? mult_a_wire[(2*int_width_a)-1:int_width_a] : + (sourcea_wire[2] == 1)? mult_a_wire[(2*int_width_a)-1:int_width_a] : dataa_int[(3*int_width_a)-1:2*int_width_a]; + + assign mult_a_pre[(4*int_width_a)-1:3*int_width_a] = (input_source_a3 == "DATAA") ? dataa_int[(4*int_width_a)-1:3*int_width_a] : + (input_source_a3 == "SCANA")? mult_a_wire[(3*int_width_a)-1:2*int_width_a] : + (sourcea_wire[3] == 1)? mult_a_wire[(3*int_width_a)-1:2*int_width_a] : dataa_int[(4*int_width_a)-1:3*int_width_a]; + + assign scanouta = mult_a_wire[(number_of_multipliers * int_width_a)-1 : ((number_of_multipliers-1) * int_width_a) + (int_width_a - width_a)]; + assign scanoutb = mult_b_wire[(number_of_multipliers * int_width_b)-1 : ((number_of_multipliers-1) * int_width_b) + (int_width_b - width_b)]; + + // Clock in all the B input registers + assign i_scaninb = (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 0)? + datab_int[int_width_b-1:0] : scaninb_z; + + assign mult_b_pre[int_width_b-1:0] = (input_source_b0 == "DATAB")? datab_int[int_width_b-1:0] : + (input_source_b0 == "SCANB")? i_scaninb : + (sourceb_wire[0] == 1)? scaninb_z : datab_int[int_width_b-1:0]; + + assign mult_b_pre[(2*int_width_b)-1:int_width_b] = (input_source_b1 == "DATAB") ? datab_int[(2*int_width_b)-1 : int_width_b ]: + (input_source_b1 == "SCANB")? mult_b_wire[int_width_b -1 : 0] : + (sourceb_wire[1] == 1)? mult_b_wire[int_width_b -1 : 0] : datab_int[(2*int_width_b)-1 : int_width_b ]; + + assign mult_b_pre[(3*int_width_b)-1:2*int_width_b] = (input_source_b2 == "DATAB") ? datab_int[(3*int_width_b)-1:2*int_width_b] : + (input_source_b2 == "SCANB")? mult_b_wire[(2*int_width_b)-1:int_width_b] : + (sourceb_wire[2] == 1)? mult_b_wire[(2*int_width_b)-1:int_width_b] : datab_int[(3*int_width_b)-1:2*int_width_b]; + + assign mult_b_pre[(4*int_width_b)-1:3*int_width_b] = (input_source_b3 == "DATAB") ? datab_int[(4*int_width_b)-1:3*int_width_b] : + (input_source_b3 == "SCANB")? mult_b_wire[(3*int_width_b)-1:2*int_width_b] : + (sourceb_wire[3] == 1)? mult_b_wire[(3*int_width_b)-1:2*int_width_b] : datab_int[(4*int_width_b)-1:3*int_width_b]; + + // clock in all the control signals + assign addsub1_int = ((port_addnsub1 == "PORT_CONNECTIVITY")? + ((multiplier1_direction != "UNUSED")? (multiplier1_direction == "ADD" ? 1 : 0) : addnsub1_z) : + ((port_addnsub1 == "PORT_USED")? addnsub1_z : + (port_addnsub1 == "PORT_UNUSED")? (multiplier1_direction == "ADD" ? 1 : 0) : addnsub1_z)); + + assign addsub3_int = ((port_addnsub3 == "PORT_CONNECTIVITY")? + ((multiplier3_direction != "UNUSED") ? (multiplier3_direction == "ADD" ? 1 : 0) : addnsub3_z) : + ((port_addnsub3 == "PORT_USED")? addnsub3_z : + (port_addnsub3 == "PORT_UNUSED")? (multiplier3_direction == "ADD" ? 1 : 0) : addnsub3_z)); + + assign sign_a_int = ((port_signa == "PORT_CONNECTIVITY")? + ((representation_a != "UNUSED") ? (representation_a == "SIGNED" ? 1 : 0) : signa_z) : + (port_signa == "PORT_USED")? signa_z : + (port_signa == "PORT_UNUSED")? (representation_a == "SIGNED" ? 1 : 0) : signa_z); + + assign sign_b_int = ((port_signb == "PORT_CONNECTIVITY")? + ((representation_b != "UNUSED") ? (representation_b == "SIGNED" ? 1 : 0) : signb_z) : + (port_signb == "PORT_USED")? signb_z : + (port_signb == "PORT_UNUSED")? (representation_b == "SIGNED" ? 1 : 0) : signb_z); + + + + // ----------------------------------------------------------------- + // This is the main block that performs the addition and subtraction + // ----------------------------------------------------------------- + + assign result = (output_register == "UNREGISTERED")? + temp_sum[width_result - 1 + int_mult_diff_bit : int_mult_diff_bit]: temp_sum_reg[width_result - 1 + int_mult_diff_bit:int_mult_diff_bit]; + + assign mult_is_saturate_vec = (output_register == "UNREGISTERED")? + mult_saturate_overflow_vec: mult_saturate_overflow_pipe_reg; + + always @(posedge output_reg_wire_clk or posedge output_reg_wire_clr) + begin + if (output_reg_wire_clr == 1) + begin + temp_sum_reg <= {(int_width_result + 1){1'b0}}; + + for ( num_stor = extra_latency; num_stor >= 0; num_stor = num_stor - 1 ) + begin + result_pipe[num_stor] <= {int_width_result{1'b0}}; + end + + mult_saturate_overflow_pipe_reg <= {4{1'b0}}; + + head_result <= 0; + end + else if ((output_reg_wire_clk ==1) && (output_reg_wire_en ==1)) + begin + + if (extra_latency == 0) + begin + temp_sum_reg[int_width_result-1 :0] <= temp_sum[int_width_result-1 :0]; + end + else + begin + result_pipe [head_result] <= temp_sum[int_width_result-1 :0]; + head_result <= (head_result +1) % (extra_latency + 1); + end + mult_saturate_overflow_pipe_reg <= mult_saturate_overflow_vec; + end + + end + + assign head_result_wire = head_result[31:0]; + + always @(head_result_wire or result_pipe[head_result_wire]) + begin + if (extra_latency != 0) + temp_sum_reg[int_width_result-1 :0] <= result_pipe[head_result_wire]; + end + + always @(mult_res_wire [4 * (int_width_a + int_width_b) -1:0] or + addsub1_pipe_wire or addsub3_pipe_wire or + sign_a_pipe_wire or sign_b_pipe_wire or addnsub1_round_pipe_wire or + addnsub3_round_pipe_wire) + begin + temp_sum =0; + for (num_mult = 0; num_mult < number_of_multipliers; num_mult = num_mult +1) + begin + + mult_res_temp = mult_res_wire >> (num_mult * (int_width_a + int_width_b)); + mult_res_ext = ((int_width_result > (int_width_a + int_width_b))? + {{(int_width_result - int_width_a - int_width_b) + {mult_res_temp [int_width_a + int_width_b - 1] & + (sign_a_pipe_wire | sign_b_pipe_wire)}}, mult_res_temp}:mult_res_temp); + + if (num_mult == 1) + begin + if (addsub1_pipe_wire) + temp_sum = temp_sum + mult_res_ext; + else + temp_sum = temp_sum - mult_res_ext; + + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 1) + begin + // ------------------------------------------------------- + // Stratix II Rounding support + // This block basically carries out the rounding for the + // temp_sum. The equation to get the roundout for adder1 and + // adder3 is obtained from the Stratix II Mac FFD which is below: + // round_adder_constant = (1 << (wfraction - wfraction_round - 1)) + // roundout[] = datain[] + round_adder_constant + // For Stratix II rounding, we round up the bits to 15 bits + // or in another word wfraction_round = 15. + // -------------------------------------------------------- + + if ((adder1_rounding == "YES") || + ((adder1_rounding == "VARIABLE") && (addnsub1_round_pipe_wire == 1))) + begin + adder1_round_out = temp_sum + ( 1 << (`ADDER_ROUND_BITS - 1)); + + for (j = (`ADDER_ROUND_BITS - 1); j >= 0; j = j - 1) + begin + adder1_round_out[j] = 1'b0; + end + + end + else + begin + adder1_round_out = temp_sum; + end + + adder1_result = adder1_round_out; + end + + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + temp_sum = adder1_result; + end + + end + else if (num_mult == 3) + begin + if (addsub3_pipe_wire) + temp_sum = temp_sum + mult_res_ext; + else + temp_sum = temp_sum - mult_res_ext; + + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family) == 1) + begin + // StratixII rounding support + // Please see the description for rounding support in adder1 + + if ((adder3_rounding == "YES") || + ((adder3_rounding == "VARIABLE") && (addnsub3_round_pipe_wire == 1))) + begin + + adder3_round_out = temp_sum + ( 1 << (`ADDER_ROUND_BITS - 1)); + + for (j = (`ADDER_ROUND_BITS - 1); j >= 0; j = j - 1) + begin + adder3_round_out[j] = 1'b0; + end + + end + else + begin + adder3_round_out = temp_sum; + end + + adder3_result = adder3_round_out; + end + + if (dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) + begin + temp_sum = adder3_result; + end + + end + else + begin + temp_sum = temp_sum + mult_res_ext; + end + end + + end + + +endmodule // end of ALTMULT_ADD + + +//START_MODULE_NAME------------------------------------------------------------- +// +// Module Name : altfp_mult +// +// Description : Parameterized floating point multiplier megafunction. +// This module implements IEEE-754 Compliant Floating Poing +// Multiplier.It supports Single Precision, Single Extended +// Precision and Double Precision floating point +// multiplication. +// +// Limitation : Fixed clock latency with 4 clock cycle delay. +// +// Results expected: result of multiplication and the result's status bits +// +//END_MODULE_NAME--------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +module altfp_mult ( + clock, // Clock input to the multiplier.(Required) + clk_en, // Clock enable for the multiplier. + aclr, // Asynchronous clear for the multiplier. + dataa, // Data input to the multiplier.(Required) + datab, // Data input to the multiplier.(Required) + result, // Multiplier output port.(Required) + overflow, // Overflow port for the multiplier. + underflow, // Underflow port for the multiplier. + zero, // Zero port for the multiplier. + denormal, // Denormal port for the multiplier. + indefinite, // Indefinite port for the multiplier. + nan // Nan port for the multiplier. +); + +// GLOBAL PARAMETER DECLARATION + // Specifies the value of the exponent, Minimum = 8, Maximum = 31 + parameter width_exp = 8; + // Specifies the value of the mantissa, Minimum = 23, Maximum = 52 + parameter width_man = 23; + // Specifies whether to use dedicated multiplier circuitry. + parameter dedicated_multiplier_circuitry = "AUTO"; + parameter reduced_functionality = "NO"; + parameter pipeline = 5; + parameter lpm_hint = "UNUSED"; + parameter lpm_type = "altfp_mult"; + +// LOCAL PARAMETER DECLARATION + //clock latency + parameter LATENCY = pipeline -1; + // Sum of mantissa's width and exponent's width + parameter WIDTH_MAN_EXP = width_exp + width_man; + +// INPUT PORT DECLARATION + input [WIDTH_MAN_EXP : 0] dataa; + input [WIDTH_MAN_EXP : 0] datab; + input clock; + input clk_en; + input aclr; + +// OUTPUT PORT DECLARATION + output [WIDTH_MAN_EXP : 0] result; + output overflow; + output underflow; + output zero; + output denormal; + output indefinite; + output nan; + +// INTERNAL REGISTERS DECLARATION + reg[width_man : 0] mant_dataa; + reg[width_man : 0] mant_datab; + reg[(2 * width_man) + 1 : 0] mant_result; + reg cout; + reg zero_mant_dataa; + reg zero_mant_datab; + reg zero_dataa; + reg zero_datab; + reg inf_dataa; + reg inf_datab; + reg nan_dataa; + reg nan_datab; + reg den_dataa; + reg den_datab; + reg no_multiply; + reg mant_result_msb; + reg no_rounding; + reg sticky_bit; + reg round_bit; + reg guard_bit; + reg carry; + reg[WIDTH_MAN_EXP : 0] result_pipe[LATENCY : 0]; + reg[LATENCY : 0] overflow_pipe; + reg[LATENCY : 0] underflow_pipe; + reg[LATENCY : 0] zero_pipe; + reg[LATENCY : 0] denormal_pipe; + reg[LATENCY : 0] indefinite_pipe; + reg[LATENCY : 0] nan_pipe; + reg[WIDTH_MAN_EXP : 0] temp_result; + reg overflow_bit; + reg underflow_bit; + reg zero_bit; + reg denormal_bit; + reg indefinite_bit; + reg nan_bit; + +// INTERNAL TRI DECLARATION + tri1 clk_en; + tri0 aclr; + +// LOCAL INTEGER DECLARATION + integer exp_dataa; + integer exp_datab; + integer exp_result; + + // loop counter + integer i0; + integer i1; + integer i2; + integer i3; + integer i4; + integer i5; + +// TASK DECLARATION + + // Add up two bits to get the result( + ) + //Also output the carry bit. + task add_bits; + // Value to be added to the temporary result of mantissa's multiplication. + input [width_man : 0] val1; + // temporary result of mantissa's multiplication. + inout [(2 * width_man) + 1 : 0] temp_mant_result; + output cout; // carry out bit + + reg co; // temporary storage to store the carry out bit + + begin + co = 1'b0; + for(i0 = 0; i0 <= width_man; i0 = i0 + 1) + begin + // if the carry out bit from the previous bit addition is 1'b0 + if (co == 1'b0) + begin + if (val1[i0] != temp_mant_result[i0 + width_man + 1]) + begin + temp_mant_result[i0 + width_man + 1] = 1'b1; + end + else + begin + co = val1[i0] & temp_mant_result[i0 + width_man + 1]; + temp_mant_result[i0 + width_man + 1] = 1'b0; + end + end + else // if (co == 1'b1) + begin + co = val1[i0] | temp_mant_result[i0 + width_man + 1]; + if (val1[i0] != temp_mant_result[i0 + width_man + 1]) + begin + temp_mant_result[i0 + width_man + 1] = 1'b0; + end + else + begin + temp_mant_result[i0 + width_man + 1] = 1'b1; + end + end + end // end of for loop + cout = co; + end + endtask // add_bits + +// FUNCTON DECLARATION + + // Check whether the all the bits from index to is 1'b1 + // Return 1'b1 if true, otherwise return 1'b0 + function bit_all_0; + input [(2 * width_man) + 1: 0] val; + input index1; + integer index1; + input index2; + integer index2; + + reg all_0; //temporary storage to indicate whether all the currently + // checked bits are 1'b0 + begin + begin : LOOP_1 + all_0 = 1'b1; + for (i1 = index1; i1 <= index2; i1 = i1 + 1) + begin + if ((val[i1]) == 1'b1) + begin + all_0 = 1'b0; + disable LOOP_1; //break the loop to stop checking + end + end + end + bit_all_0 = all_0; + end + endfunction // bit_all_0 + + // Calculate the exponential value ( power of ) + function integer exponential_value; + input base_number; + input exponent_number; + integer base_number; + integer exponent_number; + integer value; // temporary storage to store the exponential value + + begin + value = 1; + for (i2 = 0; i2 < exponent_number; i2 = i2 + 1) + begin + value = base_number * value; + end + exponential_value = value; + end + endfunction // exponential_value + +// INITIAL CONSTRUCT BLOCK + initial + begin : INITIALIZATION + for(i3 = LATENCY; i3 >= 0; i3 = i3 - 1) + begin + result_pipe[i3] = 0; + overflow_pipe[i3] = 1'b0; + underflow_pipe[i3] = 1'b0; + zero_pipe[i3] = 1'b0; + denormal_pipe[i3] = 1'b0; + indefinite_pipe[i3] = 1'b0; + nan_pipe[i3] = 1'b0; + end + // Check for illegal mode setting + if (WIDTH_MAN_EXP >= 64) + begin + $display("ERROR: The sum of width_exp(%d) and width_man(%d) must be less 64!", width_exp, width_man); + $finish; + end + if (width_exp < 8) + begin + $display("ERROR: width_exp(%d) must be at least 8!", width_exp); + $finish; + end + if (width_man < 23) + begin + $display("ERROR: width_man(%d) must be at least 23!", width_man); + $finish; + end + if (~((width_exp >= 11) || ((width_exp == 8) && (width_man == 23)))) + begin + $display("ERROR: Found width_exp(%d) inside the range of Single Precision. width_exp must be 8 and width_man must be 23 for Single Presicion!", width_exp); + $finish; + end + if (~((width_man >= 31) || ((width_exp == 8) && (width_man == 23)))) + begin + $display("ERROR: Found width_man(%d) inside the range of Single Precision. width_exp must be 8 and width_man must be 23 for Single Presicion!", width_man); + $finish; + end + if (width_exp >= width_man) + begin + $display("ERROR: width_exp(%d) must be less than width_man(%d)!", width_exp, width_man); + $finish; + end + if ((pipeline != 5) && (pipeline != 6)) + begin + $display("ERROR: The legal value for PIPELINE is 5 or 6!"); + $finish; + end + + if ((reduced_functionality != "NO") && (reduced_functionality != "YES")) + begin + $display("ERROR: reduced_functionality value must be \"YES\" or \"NO\"!"); + $finish; + end + + if (reduced_functionality != "NO") + begin + $display("Info: The Clearbox support is available for reduced functionality Floating Point Multiplier."); + end + end // INITIALIZATION + +// ALWAYS CONSTRUCT BLOCK + + // multiplication + always @(dataa or datab) + begin : MULTIPLY_FP + temp_result = {(WIDTH_MAN_EXP + 1){1'b0}}; + overflow_bit = 1'b0; + underflow_bit = 1'b0; + zero_bit = 1'b0; + denormal_bit = 1'b0; + indefinite_bit = 1'b0; + nan_bit = 1'b0; + mant_result = {((2 * width_man) + 2){1'b0}}; + exp_dataa = 0; + exp_datab = 0; + // Set the exponential value + exp_dataa = dataa[width_exp + width_man -1:width_man]; + exp_datab = datab[width_exp + width_man -1:width_man]; + + zero_mant_dataa = 1'b1; + // Check whether the mantissa for dataa is zero + begin : LOOP_3 + for (i4 = 0; i4 <= width_man - 1; i4 = i4 + 1) + begin + if ((dataa[i4]) == 1'b1) + begin + zero_mant_dataa = 1'b0; + disable LOOP_3; + end + end + end // LOOP_3 + zero_mant_datab = 1'b1; + // Check whether the mantissa for datab is zero + begin : LOOP_4 + for (i4 = 0; i4 <= width_man -1; i4 = i4 + 1) + begin + if ((datab[i4]) == 1'b1) + begin + zero_mant_datab = 1'b0; + disable LOOP_4; + end + end + end // LOOP_4 + zero_dataa = 1'b0; + den_dataa = 1'b0; + inf_dataa = 1'b0; + nan_dataa = 1'b0; + // Check whether dataa is special input + if (exp_dataa == 0) + begin + if ((zero_mant_dataa == 1'b1) + || (reduced_functionality != "NO")) + begin + zero_dataa = 1'b1; // dataa is zero + end + else + begin + den_dataa = 1'b1; // dataa is denormalized + end + end + else if (exp_dataa == (exponential_value(2, width_exp) - 1)) + begin + if (zero_mant_dataa == 1'b1) + begin + inf_dataa = 1'b1; // dataa is infinity + end + else + begin + nan_dataa = 1'b1; // dataa is Nan + end + end + zero_datab = 1'b0; + den_datab = 1'b0; + inf_datab = 1'b0; + nan_datab = 1'b0; + // Check whether datab is special input + if (exp_datab == 0) + begin + if ((zero_mant_datab == 1'b1) + || (reduced_functionality != "NO")) + begin + zero_datab = 1'b1; // datab is zero + end + else + begin + den_datab = 1'b1; // datab is denormalized + end + end + else if (exp_datab == (exponential_value(2, width_exp) - 1)) + begin + if (zero_mant_datab == 1'b1) + begin + inf_datab = 1'b1; // datab is infinity + end + else + begin + nan_datab = 1'b1; // datab is Nan + end + end + no_multiply = 1'b0; + // Set status flag if special input exists + if (nan_dataa || nan_datab || (inf_dataa && zero_datab) || + (inf_datab && zero_dataa)) + begin + nan_bit = 1'b1; // NaN + for (i4 = width_man - 1; i4 <= WIDTH_MAN_EXP - 1; i4 = i4 + 1) + begin + temp_result[i4] = 1'b1; + end + no_multiply = 1'b1; // no multiplication is needed. + end + else if (zero_dataa) + begin + zero_bit = 1'b1; // Zero + temp_result[WIDTH_MAN_EXP : 0] = 0; + no_multiply = 1'b1; + end + else if (zero_datab) + begin + zero_bit = 1'b1; // Zero + temp_result[WIDTH_MAN_EXP : 0] = 0; + no_multiply = 1'b1; + end + else if (inf_dataa) + begin + overflow_bit = 1'b1; // Overflow + temp_result[WIDTH_MAN_EXP : 0] = dataa; + no_multiply = 1'b1; + end + else if (inf_datab) + begin + overflow_bit = 1'b1; // Overflow + temp_result[WIDTH_MAN_EXP : 0] = datab; + no_multiply = 1'b1; + end + // if multiplication needed + if (no_multiply == 1'b0) + begin + // Perform exponent operation + exp_result = exp_dataa + exp_datab - (exponential_value(2, width_exp -1) -1); + // First operand for multiplication + mant_dataa[width_man : 0] = {1'b1, dataa[width_man -1 : 0]}; + // Second operand for multiplication + mant_datab[width_man : 0] = {1'b1, datab[width_man -1 : 0]}; + // Multiply the mantissas using add and shift algorithm + for (i4 = 0; i4 <= width_man; i4 = i4 + 1) + begin + cout = 1'b0; + if ((mant_dataa[i4]) == 1'b1) + begin + add_bits(mant_datab, mant_result, cout); + end + mant_result = mant_result >> 1; + mant_result[2*width_man + 1] = cout; + end + sticky_bit = 1'b0; + mant_result_msb = mant_result[2*width_man + 1]; + // Normalize the Result + if (mant_result_msb == 1'b1) + begin + sticky_bit = mant_result[0]; // Needed for rounding operation. + mant_result = mant_result >> 1; + exp_result = exp_result + 1; + end + round_bit = mant_result[width_man - 1]; + guard_bit = mant_result[width_man]; + no_rounding = 1'b0; + // Check whether should perform rounding or not + if (round_bit == 1'b0) + begin + no_rounding = 1'b1; // No rounding is needed + end + else + begin + if (reduced_functionality == "NO") + begin + for(i4 = 0; i4 <= width_man - 2; i4 = i4 + 1) + begin + sticky_bit = sticky_bit | mant_result[i4]; + end + end + else + begin + sticky_bit = (mant_result[width_man - 2] & + mant_result_msb); + end + if ((sticky_bit == 1'b0) && (guard_bit == 1'b0)) + begin + no_rounding = 1'b1; + end + end + // Perform rounding + if (no_rounding == 1'b0) + begin + carry = 1'b1; + for(i4 = width_man; i4 <= 2 * width_man + 1; i4 = i4 + 1) + begin + if (carry == 1'b1) + begin + if (mant_result[i4] == 1'b0) + begin + mant_result[i4] = 1'b1; + carry = 1'b0; + end + else + begin + mant_result[i4] = 1'b0; + end + end + end + // If the mantissa of the result is 10.00.. after rounding, right shift the + // mantissa of the result by 1 bit and increase the exponent of the result by 1. + if (mant_result[(2 * width_man) + 1] == 1'b1) + begin + mant_result = mant_result >> 1; + exp_result = exp_result + 1; + end + end + // Normalize the Result + if ((!bit_all_0(mant_result, 0, (2 * width_man) + 1)) && + (mant_result[2 * width_man] == 1'b0)) + begin + while ((mant_result[2 * width_man] == 1'b0) && + (exp_result != 0)) + begin + mant_result = mant_result << 1; + exp_result = exp_result - 1; + end + end + else if ((exp_result < 0) && (exp_result >= -(2*width_man))) + begin + while(exp_result != 0) + begin + mant_result = mant_result >> 1; + exp_result = exp_result + 1; + end + end + // Set status flag "indefinite" if normal * denormal + // (ignore other status port since we dont care the output + if (den_dataa || den_datab) + begin + indefinite_bit = 1'b1; // Indefinite + end + else if (exp_result >= (exponential_value(2, width_exp) -1)) + begin + overflow_bit = 1'b1; // Overflow + end + else if (exp_result < 0) + begin + underflow_bit = 1'b1; // Underflow + zero_bit = 1'b1; // Zero + end + else if (exp_result == 0) + begin + underflow_bit = 1'b1; // Underflow + + if (bit_all_0(mant_result, width_man + 1, 2 * width_man)) + begin + zero_bit = 1'b1; // Zero + end + else + begin + denormal_bit = 1'b1; // Denormal + end + end + // Get result's mantissa + if (exp_result < 0) // Result underflow + begin + for(i4 = 0; i4 <= width_man - 1; i4 = i4 + 1) + begin + temp_result[i4] = 1'b0; + end + end + else if (exp_result == 0) // Denormalized result + begin + if (reduced_functionality == "NO") + begin + temp_result[width_man - 1 : 0] = mant_result[2 * width_man : width_man + 1]; + end + else + begin + temp_result[width_man - 1 : 0] = 0; + end + end + // Result overflow + else if (exp_result >= exponential_value(2, width_exp) -1) + begin + temp_result[width_man - 1 : 0] = {width_man{1'b0}}; + end + else // Normalized result + begin + temp_result[width_man - 1 : 0] = mant_result[(2 * width_man - 1) : width_man]; + end + // Get result's exponent + if (exp_result == 0) + begin + for(i4 = width_man; i4 <= WIDTH_MAN_EXP - 1; i4 = i4 + 1) + begin + temp_result[i4] = 1'b0; + end + end + else if (exp_result >= (exponential_value(2, width_exp) -1)) + begin + for(i4 = width_man; i4 <= WIDTH_MAN_EXP - 1; i4 = i4 + 1) + begin + temp_result[i4] = 1'b1; + end + end + else + begin + // Convert integer to binary bits + for(i4 = width_man; i4 <= WIDTH_MAN_EXP - 1; i4 = i4 + 1) + begin + if ((exp_result % 2) == 1) + begin + temp_result[i4] = 1'b1; + end + else + begin + temp_result[i4] = 1'b0; + end + exp_result = exp_result / 2; + end + end + end // end of if (no_multiply == 1'b0) + // Get result's sign bit + temp_result[WIDTH_MAN_EXP] = dataa[WIDTH_MAN_EXP] ^ datab[WIDTH_MAN_EXP]; + + end // MULTIPLY_FP + + // Pipelining registers. + always @(posedge clock or posedge aclr) + begin : PIPELINE_REGS + if (aclr == 1'b1) + begin + for (i5 = LATENCY; i5 >= 0; i5 = i5 - 1) + begin + result_pipe[i5] <= {WIDTH_MAN_EXP{1'b0}}; + overflow_pipe[i5] <= 1'b0; + underflow_pipe[i5] <= 1'b0; + zero_pipe[i5] <= 1'b1; + denormal_pipe[i5] <= 1'b0; + indefinite_pipe[i5] <= 1'b0; + nan_pipe[i5] <= 1'b0; + end + // clear all the output ports to 1'b0 + end + else if (clk_en == 1'b1) + begin + result_pipe[0] <= temp_result; + overflow_pipe[0] <= overflow_bit; + underflow_pipe[0] <= underflow_bit; + zero_pipe[0] <= zero_bit; + denormal_pipe[0] <= denormal_bit; + indefinite_pipe[0] <= indefinite_bit; + nan_pipe[0] <= nan_bit; + + // Create latency for the output result + for(i5=LATENCY; i5 >= 1; i5 = i5 - 1) + begin + result_pipe[i5] <= result_pipe[i5 - 1]; + overflow_pipe[i5] <= overflow_pipe[i5 - 1]; + underflow_pipe[i5] <= underflow_pipe[i5 - 1]; + zero_pipe[i5] <= zero_pipe[i5 - 1]; + denormal_pipe[i5] <= denormal_pipe[i5 - 1]; + indefinite_pipe[i5] <= indefinite_pipe[i5 - 1]; + nan_pipe[i5] <= nan_pipe[i5 - 1]; + end + end + end // PIPELINE_REGS + +assign result = result_pipe[LATENCY]; +assign overflow = overflow_pipe[LATENCY]; +assign underflow = underflow_pipe[LATENCY]; +assign zero = (reduced_functionality == "NO") ? zero_pipe[LATENCY] : 1'b0; +assign denormal = (reduced_functionality == "NO") ? denormal_pipe[LATENCY] : 1'b0; +assign indefinite = (reduced_functionality == "NO") ? indefinite_pipe[LATENCY] : 1'b0; +assign nan = nan_pipe[LATENCY]; + +endmodule //altfp_mult + +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------- +// +// Module Name : altsqrt +// +// Description : Parameterized integer square root megafunction. +// This module computes q[] and remainder so that +// q[]^2 + remainder[] == radical[] (remainder <= 2 * q[]) +// It can support the sequential mode(pipeline > 0) or +// combinational mode (pipeline = 0). +// +// Limitation : The radical is assumed to be unsigned integer. +// +// Results expected: Square root of the radical and the remainder. +// +//END_MODULE_NAME--------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +module altsqrt ( + radical, // Input port for the radical + clk, // Clock port + ena, // Clock enable port + aclr, // Asynchronous clear port + q, // Output port for returning the square root of the radical. + remainder // Output port for returning the remainder of the square root. +); + +// GLOBAL PARAMETER DECLARATION + parameter q_port_width = 1; // The width of the q port + parameter r_port_width = 1; // The width of the remainder port + parameter width = 1; // The width of the radical + parameter pipeline = 0; // The latency for the output + parameter lpm_hint= "UNUSED"; + parameter lpm_type = "altsqrt"; + +// INPUT PORT DECLARATION + input [width - 1 : 0] radical; + input clk; + input ena; + input aclr; + +// OUTPUT PORT DECLARATION + output [q_port_width - 1 : 0] q; + output [r_port_width - 1 : 0] remainder; + +// INTERNAL REGISTERS DECLARATION + reg[q_port_width - 1 : 0] q_temp; + reg[q_port_width - 1 : 0] q_pipeline[(pipeline +1) : 0]; + reg[r_port_width - 1 : 0] r_temp; + reg[r_port_width - 1 : 0] remainder_pipeline[(pipeline +1) : 0]; + +// INTERNAL TRI DECLARATION + tri1 clk; + tri1 ena; + tri0 aclr; + +// LOCAL INTEGER DECLARATION + integer value1; + integer value2; + integer index; + integer q_index; + integer q_value_temp; + integer r_value_temp; + integer i1; + integer pipe_ptr; + + +// INITIAL CONSTRUCT BLOCK + initial + begin : INITIALIZE + // Check for illegal mode + if(width < 1) + begin + $display("width (%d) must be greater than 0.(ERROR)", width); + $finish; + end + pipe_ptr = 0; + end // INITIALIZE + +// ALWAYS CONSTRUCT BLOCK + + // Perform square root calculation. + // In general, below are the steps to calculate the square root and the + // remainder. + // + // Start of with q = 0 and remainder= 0 + // For every iteration, do the same thing: + // 1) Shift in the next 2 bits of the radical into the remainder + // Eg. if the radical is b"101100". For the first iteration, + // the remainder will be equal to b"10". + // 2) Compare it to the 4* q + 1 + // 3) if the remainder is greater than or equal to 4*q + 1 + // remainder = remainder - (4*q + 1) + // q = 2*q + 1 + // otherwise + // q = 2*q + always @(radical) + begin : SQUARE_ROOT + // Reset variables + value1 = 0; + value2 = 0; + q_index = (width - 1) / 2; + q_value_temp = 0; + r_value_temp = 0; + q_temp = {q_port_width{1'b0}}; + r_temp = {r_port_width{1'b0}}; + + // If the number of the bits of the radical is an odd number, + // Then for the first iteration, only the 1st bit will be shifted + // into the remainder. + // Eg. if the radical is b"11111", then the remainder is b"01". + if((width % 2) == 1) + begin + index = width + 1; + value1 = 0; + value2 = (radical[index - 2] === 1'b1) ? 1'b1 : 1'b0; + end + else if (width > 1) + begin + // Otherwise, for the first iteration, the first two bits will be shifted + // into the remainder. + // Eg. if the radical is b"101111", then the remainder is b"10". + index = width; + value1 = (radical[index - 1] === 1'b1) ? 1'b1 : 1'b0; + value2 = (radical[index - 2] === 1'b1) ? 1'b1 : 1'b0; + end + + // For every iteration + for(index = index - 2; index >= 0; index = index - 2) + begin + // Get the remainder value by shifting in the next 2 bits + // of the radical into the remainder + r_value_temp = (r_value_temp * 4) + (2 * value1) + value2; + + // if remainder >= (4*q + 1) + if (r_value_temp >= ((4 * q_value_temp) + 1)) + begin + // remainder = remainder - (4*q + 1) + r_value_temp = r_value_temp - (4 * q_value_temp) - 1; + // q = 2*q + 1 + q_value_temp = (2 * q_value_temp) + 1; + // set the q[q_index] = 1 + q_temp[q_index] = 1'b1; + end + else // if remainder < (4*q + 1) + begin + // q = 2*q + q_value_temp = 2 * q_value_temp; + // set the q[q_index] = 0 + q_temp[q_index] = 1'b0; + end + + // if not the last iteration, get the next 2 bits of the radical + if(index >= 2) + begin + value1 = (radical[index - 1] === 1'b1)? 1: 0; + value2 = (radical[index - 2] === 1'b1)? 1: 0; + end + + // Reduce the current index of q by 1 + q_index = q_index - 1; + + end + + // Get the binary bits of the remainder by converting integer to + // binary bits + r_temp = r_value_temp; + end + + // store the result to a pipeline(to create the latency) + always @(posedge clk or posedge aclr) + begin + if (aclr) // clear the pipeline for result to 0 + begin + for (i1 = 0; i1 < (pipeline + 1); i1 = i1 + 1) + begin + q_pipeline[i1] <= 0; + remainder_pipeline[i1] <= 0; + end + end + else if (ena == 1) + begin + remainder_pipeline[pipe_ptr] <= r_temp; + q_pipeline[pipe_ptr] <= q_temp; + + if (pipeline > 1) + pipe_ptr <= (pipe_ptr + 1) % pipeline; + end + end + +// CONTINOUS ASSIGNMENT + assign q = (pipeline > 0) ? q_pipeline[pipe_ptr] : q_temp; + assign remainder = (pipeline > 0) ? remainder_pipeline[pipe_ptr] : r_temp; + +endmodule //altsqrt +// END OF MODULE + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : ALTCLKLOCK +// +// Description : Phase-Locked Loop (PLL) behavioral model. Supports basic +// PLL features such as multiplication and division of input +// clock frequency and phase shift. +// +// Limitations : Model supports NORMAL operation mode only. External +// feedback mode and zero-delay-buffer mode are not simulated. +// Applicable to APEX, Mercury and FLEX10KE device families +// only. +// +// Expected results : Up to 4 clock outputs (clock0, clock1, clock2, clock_ext). +// clock2 and clock_ext are for Mercury devices only. +// locked output indicates when PLL locks. +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module altclklock ( + inclock, // input reference clock + inclocken, // PLL enable signal + fbin, // feedback input for the PLL + clock0, // output clock 0 + clock1, // output clock 1 + clock2, // output clock 2 (for Mercury only) + clock_ext, // external output clock (for Mercury only) + locked // PLL lock signal +); + +// GLOBAL PARAMETER DECLARATION +parameter inclock_period = 10000; // units in ps +parameter inclock_settings = "UNUSED"; +parameter valid_lock_cycles = 5; +parameter invalid_lock_cycles = 5; +parameter valid_lock_multiplier = 5; +parameter invalid_lock_multiplier = 5; +parameter operation_mode = "NORMAL"; +parameter clock0_boost = 1; +parameter clock0_divide = 1; +parameter clock0_settings = "UNUSED"; +parameter clock0_time_delay = "0"; +parameter clock1_boost = 1; +parameter clock1_divide = 1; +parameter clock1_settings = "UNUSED"; +parameter clock1_time_delay = "0"; +parameter clock2_boost = 1; +parameter clock2_divide = 1; +parameter clock2_settings = "UNUSED"; +parameter clock2_time_delay = "0"; +parameter clock_ext_boost = 1; +parameter clock_ext_divide = 1; +parameter clock_ext_settings = "UNUSED"; +parameter clock_ext_time_delay = "0"; +parameter outclock_phase_shift = 0; // units in ps +parameter intended_device_family = "APEX20KE"; +parameter lpm_type = "altclklock"; +parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION +input inclock; +input inclocken; +input fbin; + +// OUTPUT PORT DECLARATION +output clock0; +output clock1; +output clock2; +output clock_ext; +output locked; + +// INTERNAL VARIABLE/REGISTER DECLARATION +reg clock0; +reg clock1; +reg clock2; +reg clock_ext; + +reg start_outclk; +reg clk0_tmp; +reg clk1_tmp; +reg clk2_tmp; +reg extclk_tmp; +reg pll_lock; +reg clk_last_value; +reg violation; +reg clk_check; +reg [1:0] next_clk_check; + +reg init; + +real pll_last_rising_edge; +real pll_last_falling_edge; +real actual_clk_cycle; +real expected_clk_cycle; +real pll_duty_cycle; +real inclk_period; +real expected_next_clk_edge; +integer pll_rising_edge_count; +integer stop_lock_count; +integer start_lock_count; +integer clk_per_tolerance; + +time clk0_phase_delay; +time clk1_phase_delay; +time clk2_phase_delay; +time extclk_phase_delay; + +ALTERA_DEVICE_FAMILIES dev (); + +// variables for clock synchronizing +time last_synchronizing_rising_edge_for_clk0; +time last_synchronizing_rising_edge_for_clk1; +time last_synchronizing_rising_edge_for_clk2; +time last_synchronizing_rising_edge_for_extclk; +time clk0_synchronizing_period; +time clk1_synchronizing_period; +time clk2_synchronizing_period; +time extclk_synchronizing_period; +integer input_cycles_per_clk0; +integer input_cycles_per_clk1; +integer input_cycles_per_clk2; +integer input_cycles_per_extclk; +integer clk0_cycles_per_sync_period; +integer clk1_cycles_per_sync_period; +integer clk2_cycles_per_sync_period; +integer extclk_cycles_per_sync_period; +integer input_cycle_count_to_sync0; +integer input_cycle_count_to_sync1; +integer input_cycle_count_to_sync2; +integer input_cycle_count_to_sync_extclk; + +// variables for shedule_clk0-2, clk_ext +reg schedule_clk0; +reg schedule_clk1; +reg schedule_clk2; +reg schedule_extclk; +reg output_value0; +reg output_value1; +reg output_value2; +reg output_value_ext; +time sched_time0; +time sched_time1; +time sched_time2; +time sched_time_ext; +integer rem0; +integer rem1; +integer rem2; +integer rem_ext; +integer tmp_rem0; +integer tmp_rem1; +integer tmp_rem2; +integer tmp_rem_ext; +integer clk_cnt0; +integer clk_cnt1; +integer clk_cnt2; +integer clk_cnt_ext; +integer cyc0; +integer cyc1; +integer cyc2; +integer cyc_ext; +integer inc0; +integer inc1; +integer inc2; +integer inc_ext; +integer cycle_to_adjust0; +integer cycle_to_adjust1; +integer cycle_to_adjust2; +integer cycle_to_adjust_ext; +time tmp_per0; +time tmp_per1; +time tmp_per2; +time tmp_per_ext; +time ori_per0; +time ori_per1; +time ori_per2; +time ori_per_ext; +time high_time0; +time high_time1; +time high_time2; +time high_time_ext; +time low_time0; +time low_time1; +time low_time2; +time low_time_ext; + +// Default inclocken and fbin ports to 1 if unused +tri1 inclocken_int; +tri1 fbin_int; + +assign inclocken_int = inclocken; +assign fbin_int = fbin; + +// +// function time_delay - converts time_delay in string format to integer, and +// add result to outclock_phase_shift +// +function time time_delay; +input [8*16:1] s; + +reg [8*16:1] reg_s; +reg [8:1] digit; +reg [8:1] tmp; +integer m; +integer outclock_phase_shift_adj; +integer sign; + +begin + // initialize variables + sign = 1; + outclock_phase_shift_adj = 0; + reg_s = s; + + for (m = 1; m <= 16; m = m + 1) + begin + tmp = reg_s[128:121]; + digit = tmp & 8'b00001111; + reg_s = reg_s << 8; + // Accumulate ascii digits 0-9 only. + if ((tmp >= 48) && (tmp <= 57)) + outclock_phase_shift_adj = outclock_phase_shift_adj * 10 + digit; + if (tmp == 45) + sign = -1; // Found a '-' character, i.e. number is negative. + end + + // add outclock_phase_shift to time delay + outclock_phase_shift_adj = (sign*outclock_phase_shift_adj) + outclock_phase_shift; + + // adjust phase shift so that its value is between 0 and 1 full + // inclock_period + while (outclock_phase_shift_adj < 0) + outclock_phase_shift_adj = outclock_phase_shift_adj + inclock_period; + while (outclock_phase_shift_adj >= inclock_period) + outclock_phase_shift_adj = outclock_phase_shift_adj - inclock_period; + + // assign result + time_delay = outclock_phase_shift_adj; +end +endfunction + +// INITIAL BLOCK +initial +begin + + // check for invalid parameters + if (inclock_period <= 0) + begin + $display("ERROR: The period of the input clock (inclock_period) must be greater than 0"); + $stop; + end + + if ((clock0_boost <= 0) || (clock0_divide <= 0) + || (clock1_boost <= 0) || (clock1_divide <= 0) + || (clock2_boost <= 0) || (clock2_divide <= 0) + || (clock_ext_boost <= 0) || (clock_ext_divide <= 0)) + begin + if ((clock0_boost <= 0) || (clock0_divide <= 0)) + begin + $display("ERROR: The multiplication and division factors for clock0 must be greater than 0."); + end + + if ((clock1_boost <= 0) || (clock1_divide <= 0)) + begin + $display("ERROR: The multiplication and division factors for clock1 must be greater than 0."); + end + + if ((clock2_boost <= 0) || (clock2_divide <= 0)) + begin + $display("ERROR: The multiplication and division factors for clock2 must be greater than 0."); + end + + if ((clock_ext_boost <= 0) || (clock_ext_divide <= 0)) + begin + $display("ERROR: The multiplication and division factors for clock_ext must be greater than 0."); + end + $stop; + end + + if ((!dev.IS_FAMILY_FLEX10KE(intended_device_family)) + && (!dev.IS_FAMILY_ACEX1K(intended_device_family)) + && (!dev.IS_FAMILY_APEX20K(intended_device_family)) + && (!dev.IS_FAMILY_APEX20KE(intended_device_family)) + && (!dev.IS_FAMILY_APEX20KC(intended_device_family)) + && (!dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family)) + && (!dev.IS_FAMILY_APEXII(intended_device_family)) + && (!dev.IS_FAMILY_MERCURY(intended_device_family))) + begin + $display("WARNING: Device family specified by the intended_device_family parameter, %s, may not be supported by altclklock", intended_device_family); + end + + stop_lock_count = 0; + violation = 0; + + // clock synchronizing variables + last_synchronizing_rising_edge_for_clk0 = 0; + last_synchronizing_rising_edge_for_clk1 = 0; + last_synchronizing_rising_edge_for_clk2 = 0; + last_synchronizing_rising_edge_for_extclk = 0; + clk0_synchronizing_period = 0; + clk1_synchronizing_period = 0; + clk2_synchronizing_period = 0; + extclk_synchronizing_period = 0; + input_cycles_per_clk0 = clock0_divide; + input_cycles_per_clk1 = clock1_divide; + input_cycles_per_clk2 = clock2_divide; + input_cycles_per_extclk = clock_ext_divide; + clk0_cycles_per_sync_period = clock0_boost; + clk1_cycles_per_sync_period = clock1_boost; + clk2_cycles_per_sync_period = clock2_boost; + extclk_cycles_per_sync_period = clock_ext_boost; + input_cycle_count_to_sync0 = 0; + input_cycle_count_to_sync1 = 0; + input_cycle_count_to_sync2 = 0; + input_cycle_count_to_sync_extclk = 0; + inc0 = 1; + inc1 = 1; + inc2 = 1; + inc_ext = 1; + cycle_to_adjust0 = 0; + cycle_to_adjust1 = 0; + cycle_to_adjust2 = 0; + cycle_to_adjust_ext = 0; + + if ((clock0_boost % clock0_divide) == 0) + begin + clk0_cycles_per_sync_period = clock0_boost / clock0_divide; + input_cycles_per_clk0 = 1; + end + + if ((clock1_boost % clock1_divide) == 0) + begin + clk1_cycles_per_sync_period = clock1_boost / clock1_divide; + input_cycles_per_clk1 = 1; + end + + if ((clock2_boost % clock2_divide) == 0) + begin + clk2_cycles_per_sync_period = clock2_boost / clock2_divide; + input_cycles_per_clk2 = 1; + end + + if ((clock_ext_boost % clock_ext_divide) == 0) + begin + extclk_cycles_per_sync_period = clock_ext_boost / clock_ext_divide; + input_cycles_per_extclk = 1; + end + + // convert time delays from string to integer + clk0_phase_delay = time_delay(clock0_time_delay); + clk1_phase_delay = time_delay(clock1_time_delay); + clk2_phase_delay = time_delay(clock2_time_delay); + extclk_phase_delay = time_delay(clock_ext_time_delay); + + // 2.5% tolerance of input clock period variation + if(dev.IS_FAMILY_MERCURY(intended_device_family)) + clk_per_tolerance = 0.025 * inclock_period; + else + clk_per_tolerance = 0.1 * inclock_period; +end + +always @(next_clk_check) +begin + if (next_clk_check == 1) + begin + if ((clk_check === 1'b1) || (clk_check === 1'b0)) + #((inclk_period+clk_per_tolerance)/2) clk_check = ~clk_check; + else + #((inclk_period+clk_per_tolerance)/2) clk_check = 1'b1; + end + else if (next_clk_check == 2) + begin + if ((clk_check === 1'b1) || (clk_check === 1'b0)) + #(expected_next_clk_edge - $realtime) clk_check = ~clk_check; + else + #(expected_next_clk_edge - $realtime) clk_check = 1'b1; + end + next_clk_check = 0; +end + +always @(inclock or inclocken_int or clk_check) +begin + + if(init !== 1'b1) + begin + start_lock_count = 0; + pll_rising_edge_count = 0; + pll_last_rising_edge = 0; + pll_last_falling_edge = 0; + pll_lock = 0; + init = 1'b1; + end + + if (inclocken_int == 1'b0) + begin + pll_lock = 0; + pll_rising_edge_count = 0; + end + else if ((inclock == 1'b1) && (clk_last_value !== inclock)) + begin + if (pll_lock === 1) + next_clk_check = 1; + + if (pll_rising_edge_count == 0) // this is first rising edge + begin + inclk_period = inclock_period; + pll_duty_cycle = inclk_period/2; + start_outclk = 0; + end + else if (pll_rising_edge_count == 1) // this is second rising edge + begin + expected_clk_cycle = inclk_period; + actual_clk_cycle = $realtime - pll_last_rising_edge; + if (actual_clk_cycle < (expected_clk_cycle - clk_per_tolerance) || + actual_clk_cycle > (expected_clk_cycle + clk_per_tolerance)) + begin + $display($realtime, "ps Warning: Inclock_Period Violation"); + violation = 1; + if (locked == 1'b1) + begin + stop_lock_count = stop_lock_count + 1; + if ((locked == 1'b1) && (stop_lock_count == invalid_lock_cycles)) + begin + pll_lock = 0; + $display ($realtime, "ps Warning: altclklock out of lock."); + + if(dev.IS_FAMILY_APEX20KE(intended_device_family) || dev.IS_FAMILY_APEX20KC(intended_device_family) || dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family)) + start_lock_count = 0; + else + start_lock_count = 1; + + stop_lock_count = 0; + clk0_tmp = 1'bx; + clk1_tmp = 1'bx; + clk2_tmp = 1'bx; + extclk_tmp = 1'bx; + end + end + else begin + start_lock_count = 1; + end + end + else + begin + if (($realtime - pll_last_falling_edge) < (pll_duty_cycle - clk_per_tolerance/2) || + ($realtime - pll_last_falling_edge) > (pll_duty_cycle + clk_per_tolerance/2)) + begin + $display($realtime, "ps Warning: Duty Cycle Violation"); + violation = 1; + end + else + violation = 0; + end + end + else if (($realtime - pll_last_rising_edge) < (expected_clk_cycle - clk_per_tolerance) || + ($realtime - pll_last_rising_edge) > (expected_clk_cycle + clk_per_tolerance)) + begin + $display($realtime, "ps Warning: Cycle Violation"); + violation = 1; + if (locked == 1'b1) + begin + stop_lock_count = stop_lock_count + 1; + if (stop_lock_count == invalid_lock_cycles) + begin + pll_lock = 0; + $display ($realtime, "ps Warning: altclklock out of lock."); + + if(dev.IS_FAMILY_APEX20KE(intended_device_family) || dev.IS_FAMILY_APEX20KC(intended_device_family) || dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family)) + start_lock_count = 0; + else + start_lock_count = 1; + + stop_lock_count = 0; + clk0_tmp = 1'bx; + clk1_tmp = 1'bx; + clk2_tmp = 1'bx; + extclk_tmp = 1'bx; + end + end + else + begin + start_lock_count = 1; + end + end + else + begin + violation = 0; + actual_clk_cycle = $realtime - pll_last_rising_edge; + end + pll_last_rising_edge = $realtime; + pll_rising_edge_count = pll_rising_edge_count + 1; + if (!violation) + begin + if (pll_lock == 1'b1) + begin + input_cycle_count_to_sync0 = input_cycle_count_to_sync0 + 1; + if (input_cycle_count_to_sync0 == input_cycles_per_clk0) + begin + clk0_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk0; + last_synchronizing_rising_edge_for_clk0 = $realtime; + schedule_clk0 = 1; + input_cycle_count_to_sync0 = 0; + end + input_cycle_count_to_sync1 = input_cycle_count_to_sync1 + 1; + if (input_cycle_count_to_sync1 == input_cycles_per_clk1) + begin + clk1_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk1; + last_synchronizing_rising_edge_for_clk1 = $realtime; + schedule_clk1 = 1; + input_cycle_count_to_sync1 = 0; + end + input_cycle_count_to_sync2 = input_cycle_count_to_sync2 + 1; + if (input_cycle_count_to_sync2 == input_cycles_per_clk2) + begin + clk2_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk2; + last_synchronizing_rising_edge_for_clk2 = $realtime; + schedule_clk2 = 1; + input_cycle_count_to_sync2 = 0; + end + input_cycle_count_to_sync_extclk = input_cycle_count_to_sync_extclk + 1; + if (input_cycle_count_to_sync_extclk == input_cycles_per_extclk) + begin + extclk_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_extclk; + last_synchronizing_rising_edge_for_extclk = $realtime; + schedule_extclk = 1; + input_cycle_count_to_sync_extclk = 0; + end + end + else + begin + if (!dev.IS_FAMILY_APEXII(intended_device_family) || (pll_rising_edge_count-1 > 0)) + begin + start_lock_count = start_lock_count + 1; + if (start_lock_count >= valid_lock_cycles) + begin + pll_lock = 1; + input_cycle_count_to_sync0 = 0; + input_cycle_count_to_sync1 = 0; + input_cycle_count_to_sync2 = 0; + input_cycle_count_to_sync_extclk = 0; + clk0_synchronizing_period = actual_clk_cycle * input_cycles_per_clk0; + clk1_synchronizing_period = actual_clk_cycle * input_cycles_per_clk1; + clk2_synchronizing_period = actual_clk_cycle * input_cycles_per_clk2; + extclk_synchronizing_period = actual_clk_cycle * input_cycles_per_extclk; + last_synchronizing_rising_edge_for_clk0 = $realtime; + last_synchronizing_rising_edge_for_clk1 = $realtime; + last_synchronizing_rising_edge_for_clk2 = $realtime; + last_synchronizing_rising_edge_for_extclk = $realtime; + schedule_clk0 = 1; + schedule_clk1 = 1; + schedule_clk2 = 1; + schedule_extclk = 1; + end + end + end + end + else + if(dev.IS_FAMILY_APEXII(intended_device_family)) + start_lock_count = 0; + else + start_lock_count = 1; + end + else if ((inclock == 1'b0) && (clk_last_value !== inclock)) + begin + if (pll_lock == 1) + begin + next_clk_check = 1; + if (($realtime - pll_last_rising_edge) < (pll_duty_cycle - clk_per_tolerance/2) || + ($realtime - pll_last_rising_edge) > (pll_duty_cycle + clk_per_tolerance/2)) + begin + $display($realtime, "ps Warning: Duty Cycle Violation"); + violation = 1; + if (locked == 1'b1) + begin + stop_lock_count = stop_lock_count + 1; + if (stop_lock_count == invalid_lock_cycles) + begin + pll_lock = 0; + $display ($realtime, "ps Warning: altclklock out of lock."); + + if(dev.IS_FAMILY_APEX20KE(intended_device_family) || dev.IS_FAMILY_APEX20KC(intended_device_family) || dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family)) + start_lock_count = 0; + else + start_lock_count = 1; + + stop_lock_count = 0; + clk0_tmp = 1'bx; + clk1_tmp = 1'bx; + clk2_tmp = 1'bx; + extclk_tmp = 1'bx; + end + end + end + else + violation = 0; + end + else if (!dev.IS_FAMILY_APEXII(intended_device_family) || (pll_rising_edge_count > 0)) + start_lock_count = start_lock_count + 1; + pll_last_falling_edge = $realtime; + end + else if (pll_lock == 1) + begin + if (inclock == 1'b1) + expected_next_clk_edge = pll_last_rising_edge + (inclk_period+clk_per_tolerance)/2; + else if (inclock == 'b0) + expected_next_clk_edge = pll_last_falling_edge + (inclk_period+clk_per_tolerance)/2; + else + expected_next_clk_edge = 0; + violation = 0; + if ($realtime < expected_next_clk_edge) + next_clk_check = 2; + else if ($realtime == expected_next_clk_edge) + next_clk_check = 1; + else + begin + $display($realtime, "ps Warning: Inclock_Period Violation"); + violation = 1; + + if (locked == 1'b1) + begin + stop_lock_count = stop_lock_count + 1; + expected_next_clk_edge = $realtime + (inclk_period/2); + if (stop_lock_count == invalid_lock_cycles) + begin + pll_lock = 0; + $display ($realtime, "ps Warning: altclklock out of lock."); + + if(dev.IS_FAMILY_APEX20KE(intended_device_family) || dev.IS_FAMILY_APEX20KC(intended_device_family) || dev.IS_FAMILY_EXCALIBUR_ARM(intended_device_family)) + start_lock_count = 0; + else + start_lock_count = 1; + + stop_lock_count = 0; + clk0_tmp = 1'bx; + clk1_tmp = 1'bx; + clk2_tmp = 1'bx; + extclk_tmp = 1'bx; + end + else + next_clk_check = 2; + end + end + end + clk_last_value = inclock; +end + +// clock0 output +always @(posedge schedule_clk0) +begin + // initialise variables + inc0 = 1; + cycle_to_adjust0 = 0; + output_value0 = 1'b1; + sched_time0 = 0; + rem0 = clk0_synchronizing_period % clk0_cycles_per_sync_period; + ori_per0 = clk0_synchronizing_period / clk0_cycles_per_sync_period; + + // schedule number of clock0 cycles in this + // loop - in order to synchronize the output clock always to the input clock + // to get rid of clock drift for cases where the input clock period is + // not evenly divisible + for (clk_cnt0 = 1; clk_cnt0 <= clk0_cycles_per_sync_period; + clk_cnt0 = clk_cnt0 + 1) + begin + tmp_per0 = ori_per0; + if ((rem0 != 0) && (inc0 <= rem0)) + begin + tmp_rem0 = (clk0_cycles_per_sync_period * inc0) % rem0; + cycle_to_adjust0 = (clk0_cycles_per_sync_period * inc0) / rem0; + if (tmp_rem0 != 0) + cycle_to_adjust0 = cycle_to_adjust0 + 1; + end + + // if this cycle is the one to adjust the output clock period, then + // increment the period by 1 unit + if (cycle_to_adjust0 == clk_cnt0) + begin + tmp_per0 = tmp_per0 + 1; + inc0 = inc0 + 1; + end + + // adjust the high and low cycle period + high_time0 = tmp_per0 / 2; + if ((tmp_per0 % 2) != 0) + high_time0 = high_time0 + 1; + + low_time0 = tmp_per0 - high_time0; + + // schedule the high and low cycle of 1 output clock period + for (cyc0 = 0; cyc0 <= 1; cyc0 = cyc0 + 1) + begin + // Avoid glitch in vcs when high_time0 and low_time0 is 0 + // (due to clk0_synchronizing_period is 0) + if (clk0_synchronizing_period != 0) + clk0_tmp = #(sched_time0) output_value0; + else + clk0_tmp = #(sched_time0) 1'b0; + output_value0 = ~output_value0; + if (output_value0 == 1'b0) + begin + sched_time0 = high_time0; + end + else if (output_value0 == 1'b1) + begin + sched_time0 = low_time0; + end + end + end + + // drop the schedule_clk0 to 0 so that the "always@(inclock)" block can + // trigger this block again when the correct time comes + schedule_clk0 = #1 1'b0; +end + +always @(clk0_tmp) +begin + if (clk0_phase_delay == 0) + clock0 <= clk0_tmp; + else + clock0 <= #(clk0_phase_delay) clk0_tmp; +end + +// clock1 output +always @(posedge schedule_clk1) +begin + // initialize variables + inc1 = 1; + cycle_to_adjust1 = 0; + output_value1 = 1'b1; + sched_time1 = 0; + rem1 = clk1_synchronizing_period % clk1_cycles_per_sync_period; + ori_per1 = clk1_synchronizing_period / clk1_cycles_per_sync_period; + + // schedule number of clock1 cycles in this + // loop - in order to synchronize the output clock always to the input clock, + // to get rid of clock drift for cases where the input clock period is + // not evenly divisible + for (clk_cnt1 = 1; clk_cnt1 <= clk1_cycles_per_sync_period; + clk_cnt1 = clk_cnt1 + 1) + begin + tmp_per1 = ori_per1; + if ((rem1 != 0) && (inc1 <= rem1)) + begin + tmp_rem1 = (clk1_cycles_per_sync_period * inc1) % rem1; + cycle_to_adjust1 = (clk1_cycles_per_sync_period * inc1) / rem1; + if (tmp_rem1 != 0) + cycle_to_adjust1 = cycle_to_adjust1 + 1; + end + + // if this cycle is the one to adjust the output clock period, then + // increment the period by 1 unit + if (cycle_to_adjust1 == clk_cnt1) + begin + tmp_per1 = tmp_per1 + 1; + inc1 = inc1 + 1; + end + + // adjust the high and low cycle period + high_time1 = tmp_per1 / 2; + if ((tmp_per1 % 2) != 0) + high_time1 = high_time1 + 1; + + low_time1 = tmp_per1 - high_time1; + + // schedule the high and low cycle of 1 output clock period + for (cyc1 = 0; cyc1 <= 1; cyc1 = cyc1 + 1) + begin + // Avoid glitch in vcs when high_time1 and low_time1 is 0 + // (due to clk1_synchronizing_period is 0) + if (clk1_synchronizing_period != 0) + clk1_tmp = #(sched_time1) output_value1; + else + clk1_tmp = #(sched_time1) 1'b0; + output_value1 = ~output_value1; + if (output_value1 == 1'b0) + sched_time1 = high_time1; + else if (output_value1 == 1'b1) + sched_time1 = low_time1; + end + end + // drop the schedule_clk1 to 0 so that the "always@(inclock)" block can + // trigger this block again when the correct time comes + schedule_clk1 = #1 1'b0; +end + +always @(clk1_tmp) +begin + if (clk1_phase_delay == 0) + clock1 <= clk1_tmp; + else + clock1 <= #(clk1_phase_delay) clk1_tmp; +end + +// clock2 output +always @(posedge schedule_clk2) +begin + // clock2 is only available for Mercury + if (dev.IS_FAMILY_MERCURY(intended_device_family)) + begin + // initialize variables + inc2 = 1; + cycle_to_adjust2 = 0; + output_value2 = 1'b1; + sched_time2 = 0; + rem2 = clk2_synchronizing_period % clk2_cycles_per_sync_period; + ori_per2 = clk2_synchronizing_period / clk2_cycles_per_sync_period; + + // schedule number of clock2 cycles in this + // loop - in order to synchronize the output clock always to the input clock, + // to get rid of clock drift for cases where the input clock period is + // not evenly divisible + for (clk_cnt2 = 1; clk_cnt2 <= clk2_cycles_per_sync_period; + clk_cnt2 = clk_cnt2 + 1) + begin + tmp_per2 = ori_per2; + if ((rem2 != 0) && (inc2 <= rem2)) + begin + tmp_rem2 = (clk2_cycles_per_sync_period * inc2) % rem2; + cycle_to_adjust2 = (clk2_cycles_per_sync_period * inc2) / rem2; + if (tmp_rem2 != 0) + cycle_to_adjust2 = cycle_to_adjust2 + 1; + end + + // if this cycle is the one to adjust the output clock period, then + // increment the period by 1 unit + if (cycle_to_adjust2 == clk_cnt2) + begin + tmp_per2 = tmp_per2 + 1; + inc2 = inc2 + 1; + end + + // adjust the high and low cycle period + high_time2 = tmp_per2 / 2; + if ((tmp_per2 % 2) != 0) + high_time2 = high_time2 + 1; + + low_time2 = tmp_per2 - high_time2; + + // schedule the high and low cycle of 1 output clock period + for (cyc2 = 0; cyc2 <= 1; cyc2 = cyc2 + 1) + begin + // Avoid glitch in vcs when high_time2 and low_time2 is 0 + // (due to clk2_synchronizing_period is 0) + if (clk2_synchronizing_period != 0) + clk2_tmp = #(sched_time2) output_value2; + else + clk2_tmp = #(sched_time2) 1'b0; + output_value2 = ~output_value2; + if (output_value2 == 1'b0) + sched_time2 = high_time2; + else if (output_value2 == 1'b1) + sched_time2 = low_time2; + end + end + // drop the schedule_clk2 to 0 so that the "always@(inclock)" block can + // trigger this block again when the correct time comes + schedule_clk2 = #1 1'b0; + end +end + +always @(clk2_tmp) +begin + if (clk2_phase_delay == 0) + clock2 <= clk2_tmp; + else + clock2 <= #(clk2_phase_delay) clk2_tmp; +end + +// clock_ext output +always @(posedge schedule_extclk) +begin + // clock_ext is only available for Mercury + if (dev.IS_FAMILY_MERCURY(intended_device_family)) + begin + // initialize variables + inc_ext = 1; + cycle_to_adjust_ext = 0; + output_value_ext = 1'b1; + sched_time_ext = 0; + rem_ext = extclk_synchronizing_period % extclk_cycles_per_sync_period; + ori_per_ext = extclk_synchronizing_period/extclk_cycles_per_sync_period; + + // schedule number of clock_ext cycles in this + // loop - in order to synchronize the output clock always to the input clock, + // to get rid of clock drift for cases where the input clock period is + // not evenly divisible + for (clk_cnt_ext = 1; clk_cnt_ext <= extclk_cycles_per_sync_period; + clk_cnt_ext = clk_cnt_ext + 1) + begin + tmp_per_ext = ori_per_ext; + if ((rem_ext != 0) && (inc_ext <= rem_ext)) + begin + tmp_rem_ext = (extclk_cycles_per_sync_period * inc_ext) % rem_ext; + cycle_to_adjust_ext = (extclk_cycles_per_sync_period * inc_ext) / rem_ext; + if (tmp_rem_ext != 0) + cycle_to_adjust_ext = cycle_to_adjust_ext + 1; + end + + // if this cycle is the one to adjust the output clock period, then + // increment the period by 1 unit + if (cycle_to_adjust_ext == clk_cnt_ext) + begin + tmp_per_ext = tmp_per_ext + 1; + inc_ext = inc_ext + 1; + end + + // adjust the high and low cycle period + high_time_ext = tmp_per_ext/2; + if ((tmp_per_ext % 2) != 0) + high_time_ext = high_time_ext + 1; + + low_time_ext = tmp_per_ext - high_time_ext; + + // schedule the high and low cycle of 1 output clock period + for (cyc_ext = 0; cyc_ext <= 1; cyc_ext = cyc_ext + 1) + begin + // Avoid glitch in vcs when high_time_ext and low_time_ext is 0 + // (due to extclk_synchronizing_period is 0) + if (extclk_synchronizing_period != 0) + extclk_tmp = #(sched_time_ext) output_value_ext; + else + extclk_tmp = #(sched_time_ext) 1'b0; + output_value_ext = ~output_value_ext; + if (output_value_ext == 1'b0) + sched_time_ext = high_time_ext; + else if (output_value_ext == 1'b1) + sched_time_ext = low_time_ext; + end + end + // drop the schedule_extclk to 0 so that the "always@(inclock)" block + // can trigger this block again when the correct time comes + schedule_extclk = #1 1'b0; + end +end + +always @(extclk_tmp) +begin + if (extclk_phase_delay == 0) + clock_ext <= extclk_tmp; + else + clock_ext <= #(extclk_phase_delay) extclk_tmp; +end + +// ACCELERATE OUTPUTS +buf (locked, pll_lock); + +endmodule // altclklock +// END OF MODULE ALTCLKLOCK + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : ALTDDIO_IN +// +// Description : Double Data Rate (DDR) input behavioural model. Receives +// data on both edges of the reference clock. +// +// Limitations : Not available for FLEX, MAX, APEX20K and APEX20KE device +// families. +// +// Expected results : Data sampled from the datain port at the rising edge of +// the reference clock (dataout_h) and at the falling edge of +// the reference clock (dataout_l). +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module altddio_in ( + datain, // required port, DDR input data + inclock, // required port, input reference clock to sample data by + inclocken, // enable data clock + aset, // asynchronous set + aclr, // asynchronous clear + dataout_h, // data sampled at the rising edge of inclock + dataout_l // data sampled at the falling edge of inclock +); + +// GLOBAL PARAMETER DECLARATION +parameter width = 1; // required parameter +parameter power_up_high = "OFF"; +parameter invert_input_clocks = "OFF"; +parameter intended_device_family = "MERCURY"; +parameter lpm_type = "altddio_in"; +parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION +input [width-1:0] datain; +input inclock; +input inclocken; +input aset; +input aclr; + +// OUTPUT PORT DECLARATION +output [width-1:0] dataout_h; +output [width-1:0] dataout_l; + +// REGISTER AND VARIABLE DECLARATION +reg [width-1:0] dataout_h_tmp; +reg [width-1:0] dataout_l_tmp; +reg [width-1:0] datain_latched; + +ALTERA_DEVICE_FAMILIES dev (); + +// pulldown/pullup +tri0 aset; // default aset to 0 +tri0 aclr; // default aclr to 0 +tri1 inclocken; // default inclocken to 1 + +// INITIAL BLOCK +initial +begin + + // Begin of parameter checking + if (width <= 0) + begin + $display("ERROR: The width parameter must be greater than 0"); + $stop; + end + + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $stop; + end + + if (!(dev.IS_FAMILY_MERCURY(intended_device_family) || + dev.IS_FAMILY_APEXII(intended_device_family) || + dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family) || + dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family))) + begin + $display("ERROR: Megafunction altddio_out is not supported in %s.", intended_device_family); + $stop; + end + // End of parameter checking + + // if power_up_high parameter is turned on, registers power up + // to '1', otherwise '0' + dataout_h_tmp = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}}; + dataout_l_tmp = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}}; + datain_latched = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}}; +end + +// input reference clock, sample data +always @ (posedge inclock or posedge aclr or posedge aset) +begin + if (aclr) + begin + dataout_h_tmp <= {width{1'b0}}; + dataout_l_tmp <= {width{1'b0}}; + end + else if (aset) + begin + dataout_h_tmp <= {width{1'b1}}; + dataout_l_tmp <= {width{1'b1}}; + end + // if not being set or cleared + else if (inclocken == 1'b1) + begin + if (invert_input_clocks == "ON") + datain_latched <= datain; + else + begin + dataout_h_tmp <= datain; + dataout_l_tmp <= datain_latched; + end + end +end + +always @ (negedge inclock or posedge aclr or posedge aset) +begin + if (aclr) + begin + datain_latched <= {width{1'b0}}; + end + else if (aset) + begin + datain_latched <= {width{1'b1}}; + end + // if not being set or cleared + else + begin + if (dev.IS_FAMILY_APEXII(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family) || + dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family)) + begin + if (inclocken == 1'b1) + if (invert_input_clocks == "ON") + begin + dataout_h_tmp <= datain; + dataout_l_tmp <= datain_latched; + end + else + datain_latched <= datain; + + end + else if (dev.IS_FAMILY_MERCURY(intended_device_family)) + begin + if (invert_input_clocks == "ON") + begin + dataout_h_tmp <= datain; + dataout_l_tmp <= datain_latched; + end + else + datain_latched <= datain; + end + else + begin + if (invert_input_clocks == "ON") + begin + dataout_h_tmp <= datain; + dataout_l_tmp <= datain_latched; + end + else + datain_latched <= datain; + end + end +end + +// assign registers to output ports +assign dataout_l = dataout_l_tmp; +assign dataout_h = dataout_h_tmp; + +endmodule // altddio_in +// END MODULE ALTDDIO_IN + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : ALTDDIO_OUT +// +// Description : Double Data Rate (DDR) output behavioural model. +// Transmits data on both edges of the reference clock. +// +// Limitations : Not available for FLEX, MAX, APEX20K and APEX20KE device +// families. +// +// Expected results : Double data rate output on dataout. +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module altddio_out ( + datain_h, // required port, data input for the rising edge of outclock + datain_l, // required port, data input for the falling edge of outclock + outclock, // required port, input reference clock to output data by + outclocken, // clock enable signal for outclock + aset, // asynchronous set + aclr, // asynchronous clear + oe, // output enable for dataout + dataout // DDR data output +); + +// GLOBAL PARAMETER DECLARATION +parameter width = 1; // required parameter +parameter power_up_high = "OFF"; +parameter oe_reg = "UNUSED"; +parameter extend_oe_disable = "UNUSED"; +parameter intended_device_family = "MERCURY"; +parameter invert_output = "OFF"; +parameter lpm_type = "altddio_out"; +parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION +input [width-1:0] datain_h; +input [width-1:0] datain_l; +input outclock; +input outclocken; +input aset; +input aclr; +input oe; + +// OUTPUT PORT DECLARATION +output [width-1:0] dataout; + +// REGISTER, NET AND VARIABLE DECLARATION +wire apexii_oe; +wire output_enable; +reg oe_rgd; +reg oe_reg_ext; +reg [width-1:0] dataout; +reg [width-1:0] dataout_h; +reg [width-1:0] dataout_l; +reg [width-1:0] dataout_tmp; + +ALTERA_DEVICE_FAMILIES dev (); + +// pulldown/pullup +tri0 aset; // default aset to 0 +tri0 aclr; // default aclr to 0 +tri1 outclocken; // default outclocken to 1 +tri1 oe; // default oe to 1 + +// INITIAL BLOCK +initial +begin + // Begin of parameter checking + if (width <= 0) + begin + $display("ERROR: The width parameter must be greater than 0"); + $stop; + end + + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $stop; + end + + if (!(dev.IS_FAMILY_MERCURY(intended_device_family) || + dev.IS_FAMILY_APEXII(intended_device_family) || + dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family) || + dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family))) + begin + $display("ERROR: Megafunction altddio_out is not supported in %s.", intended_device_family); + $stop; + end + // End of parameter checking + + // if power_up_high parameter is turned on, registers power up to '1' + // else to '0' + dataout_h = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}}; + dataout_l = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}}; + dataout_tmp = (power_up_high == "ON") ? {width{1'b1}} : {width{1'b0}}; + + if (power_up_high == "ON") + begin + oe_rgd = 1'b1; + oe_reg_ext = 1'b1; + end + else + begin + oe_rgd = 1'b0; + oe_reg_ext = 1'b0; + end +end + + +// input reference clock +always @ (posedge outclock or posedge aclr or posedge aset) +begin + if (aclr) + begin + dataout_h <= {width{1'b0}}; + dataout_l <= {width{1'b0}}; + dataout_tmp <= {width{1'b0}}; + + oe_rgd <= 1'b0; + end + else if (aset) + begin + dataout_h <= {width{1'b1}}; + dataout_l <= {width{1'b1}}; + dataout_tmp <= {width{1'b1}}; + + oe_rgd <= 1'b1; + end + // if clock is enabled + else if (outclocken == 1'b1) + begin + dataout_h <= datain_h; + dataout_l <= datain_l; + dataout_tmp <= datain_h; + + // register the output enable signal + oe_rgd <= oe; + end + else + dataout_tmp <= dataout_h; + +end + +// input reference clock +always @ (negedge outclock or posedge aclr or posedge aset) +begin + if (aclr) + begin + oe_reg_ext <= 1'b0; + end + else if (aset) + begin + oe_reg_ext <= 1'b1; + end + // if not being set or cleared + else + begin + // if clock is enabled + if (outclocken == 1'b1) + begin + // additional register for output enable signal + oe_reg_ext <= oe_rgd; + end + + dataout_tmp <= dataout_l; + end +end + +// data output +always @(dataout_tmp or output_enable) +begin + // if output is enabled + if (output_enable == 1'b1) + begin + if (dev.FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO(intended_device_family) && + (invert_output == "ON")) + dataout = ~dataout_tmp; + else + dataout = dataout_tmp; + end + else // output is disabled + dataout = {width{1'bZ}}; +end + +// output enable signal +// Mercury does not support extend_oe_disable and oe_reg parameters +assign output_enable = (dev.IS_FAMILY_APEXII(intended_device_family) || + dev.IS_FAMILY_STRATIX(intended_device_family)|| + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family) || + dev.FEATURE_FAMILY_STRATIXII(intended_device_family) || + dev.IS_FAMILY_HARDCOPYSTRATIX(intended_device_family) || + dev.IS_FAMILY_CYCLONEII(intended_device_family)) + ? apexii_oe + : oe; + +assign apexii_oe = (extend_oe_disable == "ON") + ? (oe_reg_ext & oe_rgd) + : ((oe_reg == "REGISTERED") && (extend_oe_disable != "ON")) + ? oe_rgd + : oe; + +endmodule // altddio_out +// END MODULE ALTDDIO_OUT + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : ALTDDIO_BIDIR +// +// Description : Double Data Rate (DDR) bi-directional behavioural model. +// Transmits and receives data on both edges of the reference +// clock. +// +// Limitations : Not available for FLEX, MAX, APEX20K and APEX20KE device +// families. +// +// Expected results : Data output sampled from padio port on rising edge of +// inclock signal (dataout_h) and falling edge of inclock +// signal (dataout_l). Combinatorial output fed by padio +// directly (combout). +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module altddio_bidir ( + datain_h, // required port, input data to be output of padio port at the + // rising edge of outclock + datain_l, // required port, input data to be output of padio port at the + // falling edge of outclock + inclock, // required port, input reference clock to sample data by + inclocken, // inclock enable + outclock, // required port, input reference clock to register data output + outclocken, // outclock enable + aset, // asynchronour set + aclr, // asynchronous clear + oe, // output enable for padio port + dataout_h, // data sampled from the padio port at the rising edge of inclock + dataout_l, // data sampled from the padio port at the falling edge of + // inclock + combout, // combinatorial output directly fed by padio + dqsundelayedout, // undelayed DQS signal to the PLD core + padio // bidirectional DDR port +); + +// GLOBAL PARAMETER DECLARATION +parameter width = 1; // required parameter +parameter power_up_high = "OFF"; +parameter oe_reg = "UNUSED"; +parameter extend_oe_disable = "UNUSED"; +parameter implement_input_in_lcell = "UNUSED"; +parameter invert_output = "OFF"; +parameter intended_device_family = "MERCURY"; +parameter lpm_type = "altddio_bidir"; +parameter lpm_hint = "UNUSED"; + +// INPUT PORT DECLARATION +input [width-1:0] datain_h; +input [width-1:0] datain_l; +input inclock; +input inclocken; +input outclock; +input outclocken; +input aset; +input aclr; +input oe; + +// OUTPUT PORT DECLARATION +output [width-1:0] dataout_h; +output [width-1:0] dataout_l; +output [width-1:0] combout; +output [width-1:0] dqsundelayedout; +// BIDIRECTIONAL PORT DECLARATION +inout [width-1:0] padio; + +// pulldown/pullup +tri0 inclock; +tri0 aset; +tri0 aclr; +tri1 outclocken; +tri1 inclocken; +tri1 oe; + +// INITIAL BLOCK +initial +begin + + // Begin of parameter checking + if (width <= 0) + begin + $display("ERROR: The width parameter must be greater than 0"); + $stop; + end + // End of parameter checking + +end + +// COMPONENT INSTANTIATION +// ALTDDIO_IN +altddio_in u1 ( + .datain(padio), + .inclock(inclock), + .inclocken(inclocken), + .aset(aset), + .aclr(aclr), + .dataout_h(dataout_h), + .dataout_l(dataout_l) +); +defparam u1.width = width, + u1.intended_device_family = intended_device_family, + u1.power_up_high = power_up_high; + +// ALTDDIO_OUT +altddio_out u2 ( + .datain_h(datain_h), + .datain_l(datain_l), + .outclock(outclock), + .oe(oe), + .outclocken(outclocken), + .aset(aset), + .aclr(aclr), + .dataout(padio) +); +defparam u2.width = width, + u2.power_up_high = power_up_high, + u2.intended_device_family = intended_device_family, + u2.oe_reg = oe_reg, + u2.extend_oe_disable = extend_oe_disable, + u2.invert_output = invert_output; + +// padio feeds combout port directly +assign combout = padio; +assign dqsundelayedout = padio; +endmodule // altddio_bidir +// END MODULE ALTDDIO_BIDIR + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : HSSI_PLL +// +// Description : This is the Phase Locked Loop (PLL) model used by altcdr_rx +// and altcdr_tx. Simple PLL model with 1 clock input (clk) and +// 2 clock outputs (clk0 & clk1). +// +// Limitations : Only capable of multiplying and dividing the input clock +// frequency. There is no support for phase shifts, uneven duty +// cycles or other fancy PLL features, since the Mercury CDR +// does not need these features. +// +// Expected results : 2 output clocks - clk0 and clk1. Locked output indicates +// when the PLL locks. +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module hssi_pll ( + clk, // input clock + areset, // asynchronous reset + clk0, // output clock0 + clk1, // output clock1 + locked // PLL lock signal +); + +// GLOBAL PARAMETER DECLARATION +parameter clk0_multiply_by = 1; +parameter clk1_divide_by = 1; +parameter input_frequency = 1000; // period in ps + +// INPUT PORT DECLARATION +input clk; +input areset; + +// OUTPUT PORT DECLARATION +output clk0; +output clk1; +output locked; + +// INTERNAL SIGNAL/REGISTER DECLARATION +reg start_outclk; +reg clk0_tmp; +reg clk1_tmp; +reg clk0; +reg clk1; +reg pll_lock; +reg clk_last_value; +reg violation; +reg clk_check; +reg [1:0] next_clk_check; +wire clk_in; + +// INTERNAL VARIABLE DECLARATION +real pll_last_rising_edge; +real pll_last_falling_edge; +real actual_clk_cycle; +real expected_clk_cycle; +real pll_duty_cycle; +real inclk_period; +real clk0_period; +real clk1_period; +real expected_next_clk_edge; + +integer pll_rising_edge_count; +integer stop_lock_count; +integer start_lock_count; +integer first_clk0_cycle; +integer first_clk1_cycle; +integer lock_on_rise; +integer lock_on_fall; +integer clk_per_tolerance; +integer lock_low; +integer lock_high; + +// variables for clock synchronizing +integer last_synchronizing_rising_edge_for_clk0; +integer last_synchronizing_rising_edge_for_clk1; +integer clk0_synchronizing_period; +integer clk1_synchronizing_period; +reg schedule_clk0; +reg schedule_clk1; +reg output_value0; +reg output_value1; + +integer input_cycles_per_clk0; +integer input_cycles_per_clk1; +integer clk0_cycles_per_sync_period; +integer clk1_cycles_per_sync_period; +integer input_cycle_count_to_sync0; +integer input_cycle_count_to_sync1; + +integer sched_time0; +integer sched_time1; +integer rem0; +integer rem1; +integer tmp_rem0; +integer tmp_rem1; +integer i0; +integer i1; +integer j0; +integer j1; +integer l0; +integer l1; +integer cycle_to_adjust0; +integer cycle_to_adjust1; +integer tmp_per0; +integer tmp_per1; +integer high_time0; +integer high_time1; +integer low_time0; +integer low_time1; + +buf (clk_in, clk); + +initial +begin + pll_rising_edge_count = 0; + pll_lock = 1'b0; + stop_lock_count = 0; + start_lock_count = 0; + clk_last_value = clk_in; + first_clk0_cycle = 1; + first_clk1_cycle = 1; + violation = 0; + lock_on_rise = 0; + lock_on_fall = 0; + pll_last_rising_edge = 0; + pll_last_falling_edge = 0; + lock_low = 2; + lock_high = 2; + clk_check = 0; + + last_synchronizing_rising_edge_for_clk0 = 0; + last_synchronizing_rising_edge_for_clk1 = 0; + clk0_synchronizing_period = 0; + clk1_synchronizing_period = 0; + schedule_clk0 = 0; + schedule_clk1 = 0; + input_cycles_per_clk0 = 1; + input_cycles_per_clk1 = clk1_divide_by; + clk0_cycles_per_sync_period = clk0_multiply_by; + clk1_cycles_per_sync_period = clk0_multiply_by; + input_cycle_count_to_sync0 = 0; + input_cycle_count_to_sync1 = 0; + l0 = 1; + l1 = 1; + cycle_to_adjust0 = 0; + cycle_to_adjust1 = 0; +end + +// trigger input clock checking for the purpose of detecting an input clock that +// has flatlined or that violates the specified input frequency or 50% duty +// cycle - with tolerance +always @(next_clk_check) +begin + if (next_clk_check == 1) + begin + #((inclk_period+clk_per_tolerance)/2) clk_check = ~clk_check; + end + else if (next_clk_check == 2) + begin + #(expected_next_clk_edge - $realtime) clk_check = ~clk_check; + end + next_clk_check = 0; +end + +// same as initial block +// reset all variables, registers and signals on positive edge of areset +always @(posedge areset) +begin + pll_rising_edge_count = 0; + pll_lock = 1'b0; + stop_lock_count = 0; + start_lock_count = 1; + clk_last_value = 0; + first_clk0_cycle = 1; + first_clk1_cycle = 1; + clk0_tmp = 1'bx; + clk1_tmp = 1'bx; + violation = 0; + lock_on_rise = 0; + lock_on_fall = 0; + pll_last_rising_edge = 0; + pll_last_falling_edge = 0; + lock_low = 1; + lock_high = 2; +end + +// on change of input clock or clock check trigger, +// monitor for duty cycle/input frequency violation +// schedule clk0 and clk1 output, handles the PLL locking +always @(clk_in or clk_check) +begin + if (areset !== 1'b1) + begin + // rising edge of the clock + if ((clk_in === 1'b1) && (clk_last_value !== clk_in)) + begin + if (pll_lock === 1'b1) + next_clk_check = 1; + if (pll_rising_edge_count == 0) // this is first rising edge + begin + inclk_period = input_frequency; + pll_duty_cycle = inclk_period/2; + clk_per_tolerance = 0.025 * inclk_period; + + clk0_period = inclk_period / clk0_multiply_by; + clk1_period = inclk_period / clk0_multiply_by * clk1_divide_by; + start_outclk = 0; + pll_last_rising_edge = $realtime; + end + else if (pll_rising_edge_count == 1) // this is second rising edge + begin + expected_clk_cycle = inclk_period; + actual_clk_cycle = $realtime - pll_last_rising_edge; + + // input frequency violation check + if (actual_clk_cycle < (expected_clk_cycle - clk_per_tolerance) || + actual_clk_cycle > (expected_clk_cycle + clk_per_tolerance)) + begin + $display($realtime, "Warning: Input frequency Violation"); + violation = 1; + if (locked === 1'b1) + begin + stop_lock_count = stop_lock_count + 1; + // PLL breaks its lock + if ((locked === 1'b1) && (stop_lock_count == lock_low)) + begin + pll_lock = 1'b0; + start_lock_count = 1; + stop_lock_count = 0; + clk0_tmp = 1'bx; + clk1_tmp = 1'bx; + end + end + end + else + begin + // Duty cycle violation check + if (($realtime - pll_last_falling_edge) < (pll_duty_cycle - (clk_per_tolerance/2)) || + ($realtime - pll_last_falling_edge) > (pll_duty_cycle + (clk_per_tolerance/2))) + begin + $display($realtime, "Warning: Duty Cycle Violation"); + violation = 1; + end + else + violation = 0; + end + end + // input frequency violation check + else if (($realtime - pll_last_rising_edge) < (expected_clk_cycle - clk_per_tolerance) || + ($realtime - pll_last_rising_edge) > (expected_clk_cycle + clk_per_tolerance)) + begin + $display($realtime, "Warning: Cycle Violation"); + violation = 1; + if (locked === 1'b1) + begin + stop_lock_count = stop_lock_count + 1; + // PLL breaks its lock + if (stop_lock_count == lock_low) + begin + pll_lock = 1'b0; + start_lock_count = 1; + stop_lock_count = 0; + clk0_tmp = 1'bx; + clk1_tmp = 1'bx; + end + end + end + else begin + violation = 0; + actual_clk_cycle = $realtime - pll_last_rising_edge; + end + pll_last_rising_edge = $realtime; + pll_rising_edge_count = pll_rising_edge_count + 1; + + // if no violation is detected, schedule clk0 and clk1 + if (!violation) + begin + if (pll_lock === 1'b1) + begin + input_cycle_count_to_sync0 = input_cycle_count_to_sync0 + 1; + if (input_cycle_count_to_sync0 == input_cycles_per_clk0) + begin + clk0_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk0; + last_synchronizing_rising_edge_for_clk0 = $realtime; + schedule_clk0 = 1; + input_cycle_count_to_sync0 = 0; + end + + input_cycle_count_to_sync1 = input_cycle_count_to_sync1 + 1; + if (input_cycle_count_to_sync1 == input_cycles_per_clk1) + begin + clk1_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk1; + last_synchronizing_rising_edge_for_clk1 = $realtime; + schedule_clk1 = 1; + input_cycle_count_to_sync1 = 0; + end + end + else begin + start_lock_count = start_lock_count + 1; + if (start_lock_count >= (lock_high + 1)) + begin + pll_lock = 1'b1; + input_cycle_count_to_sync0 = 0; + input_cycle_count_to_sync1 = 0; + lock_on_rise = 1; + if (last_synchronizing_rising_edge_for_clk0 == 0) + begin + clk0_synchronizing_period = actual_clk_cycle; + end + else + clk0_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk0; + + if (last_synchronizing_rising_edge_for_clk1 == 0) + clk1_synchronizing_period = actual_clk_cycle * clk1_divide_by; + else + clk1_synchronizing_period = $realtime - last_synchronizing_rising_edge_for_clk1; + + last_synchronizing_rising_edge_for_clk0 = $realtime; + last_synchronizing_rising_edge_for_clk1 = $realtime; + schedule_clk0 = 1; + schedule_clk1 = 1; + end + end + end + else + start_lock_count = 1; + end + // falling edge of input clock + else if ((clk_in === 1'b0) && (clk_last_value !== clk_in)) + begin + if (pll_lock === 1'b1) + begin + next_clk_check = 1; + if (($realtime - pll_last_rising_edge) < (pll_duty_cycle - (clk_per_tolerance/2)) || + ($realtime - pll_last_rising_edge) > (pll_duty_cycle + (clk_per_tolerance/2))) + begin + $display($realtime, "Warning: Duty Cycle Violation"); + violation = 1; + if (locked === 1'b1) + begin + stop_lock_count = stop_lock_count + 1; + if (stop_lock_count == lock_low) + begin + pll_lock = 1'b0; + start_lock_count = 1; + stop_lock_count = 0; + clk0_tmp = 1'bx; + clk1_tmp = 1'bx; + end + end + end + else + violation = 0; + end + else + start_lock_count = start_lock_count + 1; + + pll_last_falling_edge = $realtime; + end + else if (pll_lock === 1'b1) // perform clock check + begin + if (clk_in === 1'b1) + expected_next_clk_edge = pll_last_rising_edge + ((inclk_period+clk_per_tolerance)/2); + else if (clk_in === 1'b0) + expected_next_clk_edge = pll_last_falling_edge + ((inclk_period+clk_per_tolerance)/2); + else + expected_next_clk_edge = 0; + + violation = 0; + if ($realtime < expected_next_clk_edge) + next_clk_check = 2; + else if ($realtime == expected_next_clk_edge) + next_clk_check = 1; + else + begin + $display($realtime, "Warning: Input frequency Violation"); + violation = 1; + if (locked === 1'b1) + begin + stop_lock_count = stop_lock_count + 1; + expected_next_clk_edge = $realtime + (inclk_period/2); + // PLL breaks its lock + if (stop_lock_count == lock_low) + begin + pll_lock = 1'b0; + start_lock_count = 1; + stop_lock_count = 0; + clk0_tmp = 1'bx; + clk1_tmp = 1'bx; + end + else + next_clk_check = 2; + end + end + end + clk_last_value = clk_in; + end +end + +// schedule clk0 output +always @(posedge schedule_clk0) +begin + l0 = 1; + cycle_to_adjust0 = 0; + output_value0 = 1'b1; + sched_time0 = 0; + rem0 = clk0_synchronizing_period % clk0_cycles_per_sync_period; + for (i0 = 1; i0 <= clk0_cycles_per_sync_period; i0 = i0 + 1) + begin + tmp_per0 = clk0_synchronizing_period/clk0_cycles_per_sync_period; + if (rem0 != 0 && l0 <= rem0) + begin + tmp_rem0 = (clk0_cycles_per_sync_period * l0) % rem0; + cycle_to_adjust0 = (clk0_cycles_per_sync_period * l0) / rem0; + if (tmp_rem0 != 0) + cycle_to_adjust0 = cycle_to_adjust0 + 1; + end + if (cycle_to_adjust0 == i0) + begin + tmp_per0 = tmp_per0 + 1; + l0 = l0 + 1; + end + high_time0 = tmp_per0/2; + if (tmp_per0 % 2 != 0) + high_time0 = high_time0 + 1; + low_time0 = tmp_per0 - high_time0; + for (j0 = 0; j0 <= 1; j0 = j0 + 1) + begin + clk0_tmp = #(sched_time0) output_value0; + output_value0 = ~output_value0; + if (output_value0 === 1'b0) + sched_time0 = high_time0; + else if (output_value0 === 1'b1) + sched_time0 = low_time0; + end + end + schedule_clk0 = #1 1'b0; +end + +always @(clk0_tmp) +begin + clk0 <= clk0_tmp; +end + +// schedule clk1 output +always @(posedge schedule_clk1) +begin + l1 = 1; + cycle_to_adjust1 = 0; + output_value1 = 1'b1; + sched_time1 = 0; + rem1 = clk1_synchronizing_period % clk1_cycles_per_sync_period; + for (i1 = 1; i1 <= clk1_cycles_per_sync_period; i1 = i1 + 1) + begin + tmp_per1 = clk1_synchronizing_period/clk1_cycles_per_sync_period; + if (rem1 != 0 && l1 <= rem1) + begin + tmp_rem1 = (clk1_cycles_per_sync_period * l1) % rem1; + cycle_to_adjust1 = (clk1_cycles_per_sync_period * l1) / rem1; + if (tmp_rem1 != 0) + cycle_to_adjust1 = cycle_to_adjust1 + 1; + end + if (cycle_to_adjust1 == i1) + begin + tmp_per1 = tmp_per1 + 1; + l1 = l1 + 1; + end + high_time1 = tmp_per1/2; + if (tmp_per1 % 2 != 0) + high_time1 = high_time1 + 1; + low_time1 = tmp_per1 - high_time1; + for (j1 = 0; j1 <= 1; j1 = j1 + 1) + begin + clk1_tmp = #(sched_time1) output_value1; + output_value1 = ~output_value1; + if (output_value1 === 1'b0) + sched_time1 = high_time1; + else if (output_value1 === 1'b1) + sched_time1 = low_time1; + end + end + schedule_clk1 <= #1 1'b0; +end + +always @(clk1_tmp) +begin + clk1 <= clk1_tmp; +end + +buf (locked, pll_lock); + +endmodule // hssi_pll + + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : MF_RAM7X20_SYN +// +// Description : This is the RAM model used by HSSI_FIFO for writing and reading +// into the FIFO +// +// Limitations : Reading from the RAM is address-triggered, +// writing is clock-triggered +// RAM depth is fixed to 7, maximum width is 20 +// +// Expected results : data output from the RAM +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1ps / 1ps + +module MF_ram7x20_syn ( + wclk, // write clock + rst_l, // active low asynchronous reset + addr_wr, // write address + addr_rd, // read address + data_in, // data input to the RAM + we, // write enable + re, // read enable + data_out // data output from the RAM +); + +// GLOBAL PARAMETER DECLARATION +parameter ram_width = 20; + +// INPUT PORT DECLARATION +input wclk; +input rst_l; // active low +input [2:0] addr_wr; +input [2:0] addr_rd; +input [19:0] data_in; +input we; +input re; + +// OUTPUT PORT DECLARATION +output [19:0] data_out; + +// INTERNAL REGISTER/SIGNAL DECLARATION +reg [ram_width-1:0] data_out_i; +reg [ram_width-1:0] ram_array_d_0, ram_array_d_1, ram_array_d_2, + ram_array_d_3, ram_array_d_4, ram_array_d_5, + ram_array_d_6, + ram_array_q_0, ram_array_q_1, ram_array_q_2, + ram_array_q_3, ram_array_q_4, ram_array_q_5, + ram_array_q_6; +wire [ram_width-1:0] data_reg_0, data_reg_1, data_reg_2, + data_reg_3, data_reg_4, data_reg_5, data_reg_6; + +// Modelling the read port +// Assuming address triggered operation only +assign + data_reg_0 = ( addr_wr == 3'b000 ) ? data_in : ram_array_q_0, + data_reg_1 = ( addr_wr == 3'b001 ) ? data_in : ram_array_q_1, + data_reg_2 = ( addr_wr == 3'b010 ) ? data_in : ram_array_q_2, + data_reg_3 = ( addr_wr == 3'b011 ) ? data_in : ram_array_q_3, + data_reg_4 = ( addr_wr == 3'b100 ) ? data_in : ram_array_q_4, + data_reg_5 = ( addr_wr == 3'b101 ) ? data_in : ram_array_q_5, + data_reg_6 = ( addr_wr == 3'b110 ) ? data_in : ram_array_q_6; + +assign data_out = re ? data_out_i : 20'b0; + +always @(ram_array_q_0 or ram_array_q_1 or + ram_array_q_2 or ram_array_q_3 or + ram_array_q_4 or ram_array_q_5 or + ram_array_q_6 or addr_rd or we or addr_wr) +begin + case ( addr_rd ) + 3'b000 : data_out_i = ram_array_q_0; + 3'b001 : data_out_i = ram_array_q_1; + 3'b010 : data_out_i = ram_array_q_2; + 3'b011 : data_out_i = ram_array_q_3; + 3'b100 : data_out_i = ram_array_q_4; + 3'b101 : data_out_i = ram_array_q_5; + 3'b110 : data_out_i = ram_array_q_6; + default: data_out_i = data_out_i; + endcase +end + +// Modelling the write port +always @(posedge wclk or negedge rst_l) +begin + if(~rst_l) // reset + begin + ram_array_q_0 <= 0; + ram_array_q_1 <= 0; + ram_array_q_2 <= 0; + ram_array_q_3 <= 0; + ram_array_q_4 <= 0; + ram_array_q_5 <= 0; + ram_array_q_6 <= 0; + end + else + begin + ram_array_q_0 <= ram_array_d_0; + ram_array_q_1 <= ram_array_d_1; + ram_array_q_2 <= ram_array_d_2; + ram_array_q_3 <= ram_array_d_3; + ram_array_q_4 <= ram_array_d_4; + ram_array_q_5 <= ram_array_d_5; + ram_array_q_6 <= ram_array_d_6; + end +end + +always @(we or + data_reg_0 or data_reg_1 or + data_reg_2 or data_reg_3 or + data_reg_4 or data_reg_5 or + data_reg_6 or + ram_array_q_0 or ram_array_q_1 or + ram_array_q_2 or ram_array_q_3 or + ram_array_q_4 or ram_array_q_5 or + ram_array_q_6) + begin + if (we) // write enabled + begin + ram_array_d_0 <= data_reg_0; + ram_array_d_1 <= data_reg_1; + ram_array_d_2 <= data_reg_2; + ram_array_d_3 <= data_reg_3; + ram_array_d_4 <= data_reg_4; + ram_array_d_5 <= data_reg_5; + ram_array_d_6 <= data_reg_6; + end + else + begin + ram_array_d_0 <= ram_array_q_0; + ram_array_d_1 <= ram_array_q_1; + ram_array_d_2 <= ram_array_q_2; + ram_array_d_3 <= ram_array_q_3; + ram_array_d_4 <= ram_array_q_4; + ram_array_d_5 <= ram_array_q_5; + ram_array_d_6 <= ram_array_q_6; + end +end + +endmodule // MF_ram7x20_syn + + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : HSSI_FIFO +// +// Description : The FIFO model used by altcdr_rx and altcdr_tx to synchronize +// data between 2 clock domains +// +// Limitations : FIFO depth is limited to 7 words only, +// the overflow and empty signals are active low in this model +// +// Expected results : data read from the FIFO, empty and overflow signals +// (active low) to indicate when FIFO is empty or full +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps +`define CNTBIT 3 // 3 bit counter for FIFO read/write addresses + +module hssi_fifo ( + datain, // data input to the FIFO + clk0, // FIFO write clock + clk1, // FIFO read clock + we, // FIFO write enable + re, // FIFO read enable + reset, // FIFO asynchronous reset + dataout, // data output from the FIFO + empty, // active low FIFO empty signal + overflow // active low FIFO full signal +); + +// GLOBAL PARAMETER DECLARATION +parameter channel_width = 1; + +// INPUT PORT DECLARATION +input [channel_width-1:0] datain; +input clk0; +input clk1; +input we; +input re; +input reset; + +// OUTPUT PORT DECLARATION +output [channel_width-1:0] dataout; +output empty; +output overflow; + +// INTERNAL REGISTER/SIGNAL DECLARATION +wire [19:0] ram_dataout; +wire [19:0] data_out; +reg [19:0] ram_datain; +reg [19:0] dataout_tmp; +wire clk0_in; +wire clk1_in; +wire we_in; +wire re_in; +wire reset_in; + +// The following are for asynchronous fifo use +reg [`CNTBIT-1:0] wrPtr0; // write pointer synchronizer +reg [`CNTBIT-1:0] wrPtr1; // write pointer synchronizer +reg [`CNTBIT-1:0] wrPtr2; // write pointer synchronizer +reg [`CNTBIT-1:0] wrPtr,rdPtr; // writer pointer, read pointer +reg [`CNTBIT-1:0] wrAddr; // writer address +reg [`CNTBIT-1:0] preRdPtr,preRdPtr1,preRdPtr2; +wire [`CNTBIT-1:0] rdAddr = rdPtr; // read address +reg ram_we; // we for ram + +// Empty/Full checking +wire fullFlag = (wrPtr0 == preRdPtr2)? 1 : 0; +wire emptyFlag = (rdPtr == wrPtr2 && fullFlag == 'b0)? 1: 0; +wire overflow_tmp_b; +wire empty_tmp_b = !emptyFlag; + +// pullup/pulldown +tri1 we, re; +tri0 reset; + +integer i; + +buf (clk0_in, clk0); +buf (clk1_in, clk1); +buf (we_in, we); +buf (re_in, re); +buf (reset_in, reset); + +assign overflow_tmp_b = (reset_in)? 1'b0 : !fullFlag; + +// instantiate the 7x20 RAM for reading and writing data +MF_ram7x20_syn ram_7x20_syn( + .wclk (clk0_in), + .rst_l (!reset_in), + .addr_wr (wrAddr), + .addr_rd (rdAddr), + .data_in (ram_datain), + .we (ram_we), + .re (re && empty_tmp_b), + .data_out (ram_dataout) +); +defparam ram_7x20_syn.ram_width = channel_width; + +// initialize the FIFO read and write pointers +initial +begin + dataout_tmp = 20'b0; + for (i = 0; i < `CNTBIT; i = i + 1) + begin + wrPtr0[i] = 1'b0; + wrPtr1[i] = 1'b0; + wrPtr2[i] = 1'b0; + wrPtr[i] = 1'b0; + rdPtr[i] = 1'b0; + preRdPtr[i] = 1'b0; + preRdPtr1[i] = 1'b0; + preRdPtr2[i] = 1'b0; + end + preRdPtr1 = 6; + preRdPtr2 = 6; +end + +// output data on postive edge of read clock (clk1) +always @(posedge clk1_in or posedge reset_in ) +begin + if (reset_in === 1'b1) + dataout_tmp <= 0; + else if ((re_in === 1'b1) && (empty_tmp_b === 1'b1)) + dataout_tmp <= ram_dataout; // memory output latch + else + dataout_tmp <= dataout_tmp; +end + +// Update the write pointer and send input data to the RAM +// Delay the write pointer update until we have given the RAM the +// write strobe. This prevents the not empty flag from going true +// before the data actually makes it safely into the RAM +always @(posedge clk0_in or posedge reset_in) +begin + if(reset_in === 1'b1) // reset + begin + wrAddr <= 0; + ram_datain <= 20'b0; + wrPtr0 <= 0; + end + else if ((we_in === 1'b1) && (overflow_tmp_b === 1'b1)) + begin + ram_datain <= datain; + wrAddr <= wrPtr0; // wrLow for memory + wrPtr0 <= wrPtr0 + 1; + if (wrPtr0 == 6) + wrPtr0 <= 0; + end + else + begin + wrAddr <= wrAddr; + ram_datain <= ram_datain; + wrPtr0 <= wrPtr0; + end +end + +// write pointer +always @(posedge clk0_in or posedge reset_in) +begin + if(reset_in === 1'b1) + wrPtr <= 0; + else + wrPtr <= wrPtr0; +end + +// write enable +always @(posedge clk0_in or posedge reset_in) +begin + if (reset_in === 1'b1) + ram_we <= 1'b0; + else if ((we_in === 1'b1) && (overflow_tmp_b === 1'b1)) + ram_we <= 1'b1; + else + ram_we <= 1'b0; +end + +// update read pointer +always @(posedge clk1_in or posedge reset_in) +begin + if(reset_in === 1'b1) + begin + rdPtr <= 0; + preRdPtr <= 0; + end + else if ((re_in === 1'b1) && (empty_tmp_b === 1'b1)) + begin + rdPtr <= rdPtr + 1; + if (rdPtr == 6) + rdPtr <= 0; + preRdPtr <= rdPtr; + end +end + +// the following lines are for async. fifo. +always @(posedge clk1_in or posedge reset_in) +begin + if (reset_in === 1'b1) + begin + wrPtr1 <= 0; + wrPtr2 <= 0; + end + else + begin + wrPtr1 <= wrPtr; // sync. wrPtr to read clock + wrPtr2 <= wrPtr1; + end +end + +always @(posedge clk0_in or posedge reset_in) +begin + if (reset_in === 1'b1) + begin + preRdPtr1 <= 6; + preRdPtr2 <= 6; + end + else + begin + preRdPtr1 <= preRdPtr; // sync. RdPtr to write clock + preRdPtr2 <= preRdPtr1; + end +end + +assign dataout = dataout_tmp; + +and (empty, empty_tmp_b, 1'b1); +and (overflow, overflow_tmp_b, 1'b1); + +endmodule // hssi_fifo + + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : HSSI_RX +// +// Description : This is the receiver model used by altcdr_rx. Performs +// deserialization of input data. +// +// Limitations : Assumes that the clock is already perfectly synchronized to the +// incoming data +// +// Expected results: data output from the deserializer, slow clock (clkout) +// generated by the RX, run length violation flag (rlv), and +// locked output to indicate when the RX has failed to lock +// onto the input data signal (not simulated) +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +module hssi_rx ( + clk, // fast clock + coreclk, // slow (core) clock + datain, // data input to the RX + areset, // asynchronous reset + feedback,// data feedback port + fbkcntl, // feedback control port + dataout, // data output from the RX + clkout, // slow clock generated by the RX + rlv, // run length violation flag + locked // RX lost of lock indicator +); + +// GLOBAL PARAMETER DECLARATION +parameter channel_width = 1; +parameter operation_mode = "CDR"; +parameter run_length = 1; + +// INPUT PORT DECLARATION +input clk; +input coreclk; +input datain; +input areset; +input feedback; +input fbkcntl; + +// OUTPUT PORT DECLARATION +output [channel_width-1:0] dataout; +output clkout; +output rlv; +output locked; + +// INTERNAL VARIABLE/SIGNAL/REGISTER DECLARATION +integer i; +integer clk_count; +integer rlv_count; +reg clk_last_value; +reg coreclk_last_value; +reg clkout_last_value; +reg [channel_width-1:0] deser_data_arr; +reg clkout_tmp; +reg rlv_tmp; +reg locked_tmp; +reg rlv_flag; +reg rlv_set; +reg [19:0] dataout_tmp; +reg datain_in; +reg last_datain; +reg data_changed; +wire [19:0] data_out; +wire clk_in; +wire coreclk_in; +wire datain_buf; +wire fbin_in; +wire fbena_in; +wire areset_in; + +// pulldown +tri0 areset, feedback, fbkcntl; + +buf (clk_in, clk); +buf (coreclk_in, coreclk); +buf (datain_buf, datain); +buf (fbin_in, feedback); +buf (fbena_in, fbkcntl); +buf (areset_in, areset); + +initial +begin + i = 0; + rlv_count = 0; + clk_count = channel_width; + clk_last_value = 0; + coreclk_last_value = 0; + clkout_tmp = 1'b0; + rlv_tmp = 1'b0; + rlv_flag = 1'b0; + rlv_set = 1'b0; + locked_tmp = 1'b0; + dataout_tmp = 20'b0; + last_datain = 1'bx; + data_changed = 1'b0; +end + +// deserialize incoming data, generate clkout and check for run length violation +always @(clk_in or coreclk_in or areset_in or fbena_in) +begin + if (areset_in === 1'b1) // reset + begin + rlv_set = 1'b0; + dataout_tmp = 20'b0; + clkout_tmp = 1'b0; + rlv_tmp = 1'b0; + rlv_flag = 1'b0; + last_datain = 1'bx; + rlv_count = 0; + data_changed = 1'b0; + clk_count = channel_width; + for (i = channel_width - 1; i >= 0; i = i - 1) + deser_data_arr[i] = 1'b0; + end + else + begin + if (fbena_in === 1'b1) + datain_in = fbin_in; + else + datain_in = datain_buf; + if ((clk_in === 1'b1) && (clk_last_value !== clk_in)) + begin + if (clk_count == channel_width) + begin + clk_count = 0; + clkout_tmp = !clkout_last_value; + end + else if (clk_count == (channel_width+1)/2) + clkout_tmp = !clkout_last_value; + else if (clk_count < channel_width) + clkout_tmp = clkout_last_value; + clk_count = clk_count + 1; + + //rlv (run length violation) checking + if (operation_mode == "CDR") + begin + if (last_datain !== datain_in) + begin + data_changed = 1'b1; + last_datain = datain_in; + end + else // data not changed - increment rlv_count + begin + rlv_count = rlv_count + 1; + data_changed = 1'b0; + end + + if (rlv_count > run_length) + begin + rlv_flag = 1'b1; + rlv_set = 1'b1; + end + else + rlv_set = 1'b0; + + if (data_changed) + rlv_count = 1; + end + end + if ((coreclk_in === 1'b1) && (coreclk_last_value !== coreclk_in)) + begin + // output the rlv status with the rising edge of the coreclk + if (operation_mode == "CDR") + begin + if (rlv_flag === 1'b1) + begin + rlv_tmp = 1'b1; + if (rlv_set === 1'b0) + rlv_flag = 1'b0; + end + else + rlv_tmp = 1'b0; + end + end + + // deserialize the data + if ((clk_in === 1'b0) && (clk_last_value !== clk_in)) + begin + if ((clk_count == 3)) + dataout_tmp[channel_width-1:0] = deser_data_arr; + + for (i = channel_width - 1; i >= 1; i = i - 1) + deser_data_arr[i] = deser_data_arr[i-1]; + + deser_data_arr[0] = datain_in; + end + end + clk_last_value = clk_in; + coreclk_last_value = coreclk_in; + clkout_last_value = clkout_tmp; +end + +assign dataout = dataout_tmp; + +and (rlv, rlv_tmp, 1'b1); +and (locked, locked_tmp, 1'b1); +and (clkout, clkout_tmp, 1'b1); + +endmodule // hssi_rx + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : HSSI_TX +// +// Description : The transmitter module used by altcdr_tx. Performs +// serialization of output data. +// +// Limitations : +// +// Expected results : Serial data output (dataout) and generated slow clock +// (clkout) +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module hssi_tx ( + clk, // fast clock + datain, // parallel input data + areset, // asynchronous reset + dataout, // serial data output + clkout // generated clock +); + +// GLOBAL PARAMETER DECLARATION +parameter channel_width = 1; + +// INPUT PORT DECLARATION +input clk; +input [channel_width-1:0] datain; +input areset; + +// OUTPUT PORT DECLARATION +output dataout; +output clkout; + +// INTERNAL VARIABLE/REGISTER DECLARATION +integer i; +integer fast_clk_count; +reg clk_in_last_value; +reg dataout_tmp; +reg clkout_last_value; +reg clkout_tmp; +reg [19:0] indata; +reg [19:0] regdata; +wire clk_in; +wire areset_in; + +buf (clk_in, clk); +buf (areset_in, areset); + +initial +begin + i = 0; + fast_clk_count = channel_width; + clk_in_last_value = 0; + dataout_tmp = 1'b0; + clkout_last_value = 0; + clkout_tmp = 0; +end + +always @(clk_in or areset_in) +begin + // reset logic + if (areset_in == 1'b1) + begin + dataout_tmp = 1'b0; + clkout_tmp = 1'b0; + fast_clk_count = channel_width; + for (i = channel_width-1; i >= 0; i = i - 1) // resets register + indata[i] = 1'b0; + for (i = channel_width-1; i >= 0; i = i - 1) // resets register + regdata[i] = 1'b0; + end + else // serialize incoming parallel data and generate slow clock + begin + // rising edge of fast clock + if ((clk_in === 1'b1) && (clk_in_last_value !== clk_in)) + begin + // slow clock generation + if (fast_clk_count == channel_width) + begin + fast_clk_count = 0; + clkout_tmp = !clkout_last_value; + end + else if (fast_clk_count == (channel_width+1)/2) + clkout_tmp = !clkout_last_value; + else if (fast_clk_count < channel_width) + clkout_tmp = clkout_last_value; + + fast_clk_count = fast_clk_count + 1; + + // 3rd rising edge, start to shift out + if (fast_clk_count == 3) + begin + for (i = channel_width-1; i >= 0; i = i - 1) + regdata[i] = indata[i]; + end + + // send the MSB of regdata out + dataout_tmp = regdata[channel_width-1]; + // shift data up + for (i = channel_width-1; i > 0; i = i - 1) + regdata[i] = regdata[i-1]; + end + // falling edge of fast clock + if ((clk_in === 1'b0) && (clk_in_last_value !== clk_in)) + begin + if (fast_clk_count == 3) // loading at the 3rd falling edge + begin + indata = datain; + end + end + end + clk_in_last_value = clk_in; + clkout_last_value = clkout_tmp; +end + +and (dataout, dataout_tmp, 1'b1); +and (clkout, clkout_tmp, 1'b1); + +endmodule // hssi_tx + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : ALTCDR_RX +// +// Description : Clock Data Recovery (CDR) Receiver behavioral model. Consists +// of CDR receiver for deserialization, a Phase Locked Loop (PLL) +// and FIFO. +// +// Limitations : Available for the Mercury device family only +// +// Expected results : Deserialized data output (rx_out), recovered global data +// clock (rx_outclock), PLL lock signal, RX lost of lock signal, +// RX run length violation signal, RX FIFO full and empty +// signals (active high), recovered clock per channel +// (rx_rec_clk) +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module altcdr_rx ( + rx_in, // required port, data input + rx_inclock, // required port, input reference clock + rx_coreclock, // required port, core clock + rx_aclr, // asynchronous reset for the RX and FIFO + rx_pll_aclr, // asynchronous reset for the PLL + rx_fifo_rden, // FIFO read enable + rx_out, // data output + rx_outclock, // global clock recovered from channel 0 + rx_pll_locked,// PLL lock signal + rx_locklost, // RX lock of lost wrt input data + rx_rlv, // data run length violation flag + rx_full, // FIFO full signal + rx_empty, // FIFO empty signal + rx_rec_clk // recovered clock from each channel +); + +// GLOBAL PARAMETER DECLARATION +parameter number_of_channels = 1; +parameter deserialization_factor = 3; // Valid deserialization_factor +parameter inclock_period = 20000; // 20000ps = 50MHz +parameter inclock_boost = 1; +parameter run_length = 62; // default based on SONET requirements +parameter bypass_fifo = "OFF"; +parameter intended_device_family = "MERCURY"; +parameter lpm_type = "altcdr_rx"; +parameter lpm_hint = "UNUSED"; + +// Constant Declaration + +parameter RUN_LENGTH_MAX = 62; // Mercury Max.Run Length + + +// INPUT PORT DECLARATION +input [number_of_channels-1:0] rx_in; +input rx_inclock; +input rx_coreclock; +input rx_aclr; +input rx_pll_aclr; +input [number_of_channels-1:0] rx_fifo_rden; + +// OUTPUT PORT DECLARATION +output [deserialization_factor*number_of_channels-1:0] rx_out; +output rx_outclock; +output rx_pll_locked; +output [number_of_channels-1:0] rx_locklost; +output [number_of_channels-1:0] rx_rlv; +output [number_of_channels-1:0] rx_full; +output [number_of_channels-1:0] rx_empty; +output [number_of_channels-1:0] rx_rec_clk; + +// INTERNAL SIGNAL/VARIABLE DECLARATION +wire w_rx_inclk0; +wire [17:0] i_rx_full; +wire [17:0] i_rx_empty; +wire [17:0] i_rx_locked; +wire [17:0] w_rx_clkout; +wire [17:0] i_rx_rlv; +wire i_pll_locked; +wire [deserialization_factor-1:0] w_rx_out00; +wire [deserialization_factor-1:0] w_rx_out01; +wire [deserialization_factor-1:0] w_rx_out02; +wire [deserialization_factor-1:0] w_rx_out03; +wire [deserialization_factor-1:0] w_rx_out04; +wire [deserialization_factor-1:0] w_rx_out05; +wire [deserialization_factor-1:0] w_rx_out06; +wire [deserialization_factor-1:0] w_rx_out07; +wire [deserialization_factor-1:0] w_rx_out08; +wire [deserialization_factor-1:0] w_rx_out09; +wire [deserialization_factor-1:0] w_rx_out10; +wire [deserialization_factor-1:0] w_rx_out11; +wire [deserialization_factor-1:0] w_rx_out12; +wire [deserialization_factor-1:0] w_rx_out13; +wire [deserialization_factor-1:0] w_rx_out14; +wire [deserialization_factor-1:0] w_rx_out15; +wire [deserialization_factor-1:0] w_rx_out16; +wire [deserialization_factor-1:0] w_rx_out17; +wire [deserialization_factor-1:0] i_fifo_out00; +wire [deserialization_factor-1:0] i_fifo_out01; +wire [deserialization_factor-1:0] i_fifo_out02; +wire [deserialization_factor-1:0] i_fifo_out03; +wire [deserialization_factor-1:0] i_fifo_out04; +wire [deserialization_factor-1:0] i_fifo_out05; +wire [deserialization_factor-1:0] i_fifo_out06; +wire [deserialization_factor-1:0] i_fifo_out07; +wire [deserialization_factor-1:0] i_fifo_out08; +wire [deserialization_factor-1:0] i_fifo_out09; +wire [deserialization_factor-1:0] i_fifo_out10; +wire [deserialization_factor-1:0] i_fifo_out11; +wire [deserialization_factor-1:0] i_fifo_out12; +wire [deserialization_factor-1:0] i_fifo_out13; +wire [deserialization_factor-1:0] i_fifo_out14; +wire [deserialization_factor-1:0] i_fifo_out15; +wire [deserialization_factor-1:0] i_fifo_out16; +wire [deserialization_factor-1:0] i_fifo_out17; + +tri0 [17:0] i_rx_in; +wire [deserialization_factor*18-1:0] i_rx_out; +wire [deserialization_factor*18-1:0] i_w_rx_out; + +supply0 gnd; +supply1 vcc; + +integer i; + +// pullup/pulldown +// Default values for inputs +tri0 rx_aclr_pulldown, rx_aclr; +tri0 rx_pll_aclr_pulldown, rx_pll_aclr; +tri1 [17:0] rx_fifo_rden_pullup; + +// INITIAL BLOCK +initial +begin + + // Begin of parameter checking + if (number_of_channels <= 0) + begin + $display("ERROR: The number_of_channels parameter must be greater than 0"); + $stop; + end + + if (run_length > RUN_LENGTH_MAX) + begin + $display("ERROR: The run_length parameter must be greater than %d", RUN_LENGTH_MAX); + $stop; + end + + if (!(((deserialization_factor >= 3 ) && (deserialization_factor <= 12)) || + (deserialization_factor == 14) || (deserialization_factor == 16) || + (deserialization_factor == 18) || (deserialization_factor == 20))) + begin + $display("ERROR: Illegal value for deserialization_factor parameter (%d) -- value ", deserialization_factor); + $display(" must be in the range 3 to 12, inclusive, or must be one of 14, 16, 18, or 20"); + $stop; + end + + + // End of parameter checking + +end + + +assign rx_aclr_pulldown = rx_aclr; +assign rx_pll_aclr_pulldown = rx_pll_aclr; +assign rx_fifo_rden_pullup = rx_fifo_rden; + + //----------------------------------------------------------------------- + // Instantiate the HSSI_RX to deserialize data - maximum of 18 channels + hssi_rx rx00 ( + .datain (i_rx_in[00]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[00]), + .dataout (w_rx_out00), .clkout (w_rx_clkout[00]), .rlv (i_rx_rlv[00]) ); + defparam + rx00.channel_width = deserialization_factor, + rx00.operation_mode = "CDR", + rx00.run_length = run_length; + + hssi_rx rx01 ( + .datain (i_rx_in[01]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[01]), + .dataout (w_rx_out01), .clkout (w_rx_clkout[01]), .rlv (i_rx_rlv[01]) ); + defparam + rx01.channel_width = deserialization_factor, + rx01.operation_mode = "CDR", + rx01.run_length = run_length; + + hssi_rx rx02 ( + .datain (i_rx_in[02]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[02]), + .dataout (w_rx_out02), .clkout (w_rx_clkout[02]), .rlv (i_rx_rlv[02]) ); + defparam + rx02.channel_width = deserialization_factor, + rx02.operation_mode = "CDR", + rx02.run_length = run_length; + + hssi_rx rx03 ( + .datain (i_rx_in[03]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[03]), + .dataout (w_rx_out03), .clkout (w_rx_clkout[03]), .rlv (i_rx_rlv[03]) ); + defparam + rx03.channel_width = deserialization_factor, + rx03.operation_mode = "CDR", + rx03.run_length = run_length; + + hssi_rx rx04 ( + .datain (i_rx_in[04]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[04]), + .dataout (w_rx_out04), .clkout (w_rx_clkout[04]), .rlv (i_rx_rlv[04]) ); + defparam + rx04.channel_width = deserialization_factor, + rx04.operation_mode = "CDR", + rx04.run_length = run_length; + + hssi_rx rx05 ( + .datain (i_rx_in[05]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[05]), + .dataout (w_rx_out05), .clkout (w_rx_clkout[05]), .rlv (i_rx_rlv[05]) ); + defparam + rx05.channel_width = deserialization_factor, + rx05.operation_mode = "CDR", + rx05.run_length = run_length; + + hssi_rx rx06 ( + .datain (i_rx_in[06]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[06]), + .dataout (w_rx_out06), .clkout (w_rx_clkout[06]), .rlv (i_rx_rlv[06]) ); + defparam + rx06.channel_width = deserialization_factor, + rx06.operation_mode = "CDR", + rx06.run_length = run_length; + + hssi_rx rx07 ( + .datain (i_rx_in[07]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[07]), + .dataout (w_rx_out07), .clkout (w_rx_clkout[07]), .rlv (i_rx_rlv[07]) ); + defparam + rx07.channel_width = deserialization_factor, + rx07.operation_mode = "CDR", + rx07.run_length = run_length; + + hssi_rx rx08 ( + .datain (i_rx_in[08]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[08]), + .dataout (w_rx_out08), .clkout (w_rx_clkout[08]), .rlv (i_rx_rlv[08]) ); + defparam + rx08.channel_width = deserialization_factor, + rx08.operation_mode = "CDR", + rx08.run_length = run_length; + + hssi_rx rx09 ( + .datain (i_rx_in[09]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[09]), + .dataout (w_rx_out09), .clkout (w_rx_clkout[09]), .rlv (i_rx_rlv[09]) ); + defparam + rx09.channel_width = deserialization_factor, + rx09.operation_mode = "CDR", + rx09.run_length = run_length; + + hssi_rx rx10 ( + .datain (i_rx_in[10]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[10]), + .dataout (w_rx_out10), .clkout (w_rx_clkout[10]), .rlv (i_rx_rlv[10]) ); + defparam + rx10.channel_width = deserialization_factor, + rx10.operation_mode = "CDR", + rx10.run_length = run_length; + + hssi_rx rx11 ( + .datain (i_rx_in[11]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[11]), + .dataout (w_rx_out11), .clkout (w_rx_clkout[11]), .rlv (i_rx_rlv[11]) ); + defparam + rx11.channel_width = deserialization_factor, + rx11.operation_mode = "CDR", + rx11.run_length = run_length; + + hssi_rx rx12 ( + .datain (i_rx_in[12]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[12]), + .dataout (w_rx_out12), .clkout (w_rx_clkout[12]), .rlv (i_rx_rlv[12]) ); + defparam + rx12.channel_width = deserialization_factor, + rx12.operation_mode = "CDR", + rx12.run_length = run_length; + + hssi_rx rx13 ( + .datain (i_rx_in[13]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[13]), + .dataout (w_rx_out13), .clkout (w_rx_clkout[13]), .rlv (i_rx_rlv[13]) ); + defparam + rx13.channel_width = deserialization_factor, + rx13.operation_mode = "CDR", + rx13.run_length = run_length; + + hssi_rx rx14 ( + .datain (i_rx_in[14]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[14]), + .dataout (w_rx_out14), .clkout (w_rx_clkout[14]), .rlv (i_rx_rlv[14]) ); + defparam + rx14.channel_width = deserialization_factor, + rx14.operation_mode = "CDR", + rx14.run_length = run_length; + + hssi_rx rx15 ( + .datain (i_rx_in[15]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[15]), + .dataout (w_rx_out15), .clkout (w_rx_clkout[15]), .rlv (i_rx_rlv[15]) ); + defparam + rx15.channel_width = deserialization_factor, + rx15.operation_mode = "CDR", + rx15.run_length = run_length; + + hssi_rx rx16 ( + .datain (i_rx_in[16]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[16]), + .dataout (w_rx_out16), .clkout (w_rx_clkout[16]), .rlv (i_rx_rlv[16]) ); + defparam + rx16.channel_width = deserialization_factor, + rx16.operation_mode = "CDR", + rx16.run_length = run_length; + + hssi_rx rx17 ( + .datain (i_rx_in[17]), .clk (w_rx_inclk0), .areset (rx_aclr_pulldown), + .feedback (gnd), .fbkcntl (gnd), .coreclk (rx_coreclock), + .locked (i_rx_locked[17]), + .dataout (w_rx_out17), .clkout (w_rx_clkout[17]), .rlv (i_rx_rlv[17]) ); + defparam + rx17.channel_width = deserialization_factor, + rx17.operation_mode = "CDR", + rx17.run_length = run_length; + + + //---------------------------------------------------------- + // Instantiate HSSI_PLL - use the same PLL for all channels + + hssi_pll pll ( + .clk (rx_inclock), .areset (rx_pll_aclr_pulldown), + .clk0 (w_rx_inclk0), .clk1 (), .locked (i_pll_locked) ); + defparam + pll.clk0_multiply_by = inclock_boost, + pll.input_frequency = inclock_period; + + //---------------------------------------------------------- + // Instantiate HSSI_FIFOs + + hssi_fifo fifo00 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[00]), + .clk0 (w_rx_clkout[00]), .datain (w_rx_out00), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[00]), .empty (i_rx_empty[00]), + .dataout (i_fifo_out00) ); + defparam + fifo00.channel_width = deserialization_factor; + + hssi_fifo fifo01 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[01]), + .clk0 (w_rx_clkout[01]), .datain (w_rx_out01), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[01]), .empty (i_rx_empty[01]), + .dataout (i_fifo_out01) ); + defparam + fifo01.channel_width = deserialization_factor; + + hssi_fifo fifo02 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[02]), + .clk0 (w_rx_clkout[02]), .datain (w_rx_out02), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[02]), .empty (i_rx_empty[02]), + .dataout (i_fifo_out02) ); + defparam + fifo02.channel_width = deserialization_factor; + + hssi_fifo fifo03 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[03]), + .clk0 (w_rx_clkout[03]), .datain (w_rx_out03), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[03]), .empty (i_rx_empty[03]), + .dataout (i_fifo_out03) ); + defparam + fifo03.channel_width = deserialization_factor; + + hssi_fifo fifo04 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[04]), + .clk0 (w_rx_clkout[04]), .datain (w_rx_out04), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[04]), .empty (i_rx_empty[04]), + .dataout (i_fifo_out04) ); + defparam + fifo04.channel_width = deserialization_factor; + + hssi_fifo fifo05 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[05]), + .clk0 (w_rx_clkout[05]), .datain (w_rx_out05), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[05]), .empty (i_rx_empty[05]), + .dataout (i_fifo_out05) ); + defparam + fifo05.channel_width = deserialization_factor; + + hssi_fifo fifo06 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[06]), + .clk0 (w_rx_clkout[06]), .datain (w_rx_out06), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[06]), .empty (i_rx_empty[06]), + .dataout (i_fifo_out06) ); + defparam + fifo06.channel_width = deserialization_factor; + + hssi_fifo fifo07 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[07]), + .clk0 (w_rx_clkout[07]), .datain (w_rx_out07), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[07]), .empty (i_rx_empty[07]), + .dataout (i_fifo_out07) ); + defparam + fifo07.channel_width = deserialization_factor; + + hssi_fifo fifo08 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[08]), + .clk0 (w_rx_clkout[08]), .datain (w_rx_out08), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[08]), .empty (i_rx_empty[08]), + .dataout (i_fifo_out08) ); + defparam + fifo08.channel_width = deserialization_factor; + + hssi_fifo fifo09 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[09]), + .clk0 (w_rx_clkout[09]), .datain (w_rx_out09), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[09]), .empty (i_rx_empty[09]), + .dataout (i_fifo_out09) ); + defparam + fifo09.channel_width = deserialization_factor; + + hssi_fifo fifo10 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[10]), + .clk0 (w_rx_clkout[10]), .datain (w_rx_out10), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[10]), .empty (i_rx_empty[10]), + .dataout (i_fifo_out10) ); + defparam + fifo10.channel_width = deserialization_factor; + + hssi_fifo fifo11 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[11]), + .clk0 (w_rx_clkout[11]), .datain (w_rx_out11), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[11]), .empty (i_rx_empty[11]), + .dataout (i_fifo_out11) ); + defparam + fifo11.channel_width = deserialization_factor; + + hssi_fifo fifo12 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[12]), + .clk0 (w_rx_clkout[12]), .datain (w_rx_out12), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[12]), .empty (i_rx_empty[12]), + .dataout (i_fifo_out12) ); + defparam + fifo12.channel_width = deserialization_factor; + + hssi_fifo fifo13 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[13]), + .clk0 (w_rx_clkout[13]), .datain (w_rx_out13), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[13]), .empty (i_rx_empty[13]), + .dataout (i_fifo_out13) ); + defparam + fifo13.channel_width = deserialization_factor; + + hssi_fifo fifo14 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[14]), + .clk0 (w_rx_clkout[14]), .datain (w_rx_out14), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[14]), .empty (i_rx_empty[14]), + .dataout (i_fifo_out14) ); + defparam + fifo14.channel_width = deserialization_factor; + + hssi_fifo fifo15 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[15]), + .clk0 (w_rx_clkout[15]), .datain (w_rx_out15), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[15]), .empty (i_rx_empty[15]), + .dataout (i_fifo_out15) ); + defparam + fifo15.channel_width = deserialization_factor; + + hssi_fifo fifo16 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[16]), + .clk0 (w_rx_clkout[16]), .datain (w_rx_out16), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[16]), .empty (i_rx_empty[16]), + .dataout (i_fifo_out16) ); + defparam + fifo16.channel_width = deserialization_factor; + + hssi_fifo fifo17 ( + .clk1 (rx_coreclock), .re (rx_fifo_rden_pullup[17]), + .clk0 (w_rx_clkout[17]), .datain (w_rx_out17), + .we (vcc), .reset (rx_aclr_pulldown), + .overflow (i_rx_full[17]), .empty (i_rx_empty[17]), + .dataout (i_fifo_out17) ); + defparam + fifo17.channel_width = deserialization_factor; + + +//-------------------------- +// Inputs +assign i_rx_in[number_of_channels - 1 : 0] = rx_in[number_of_channels - 1 : 0]; + +//-------------------------- +// Outputs +// assign FIFO outputs to i_rx_out wire - for the case when FIFO is not bypassed +assign i_rx_out[01*deserialization_factor-1:00*deserialization_factor] + = i_fifo_out00; +assign i_rx_out[02*deserialization_factor-1:01*deserialization_factor] + = i_fifo_out01; +assign i_rx_out[03*deserialization_factor-1:02*deserialization_factor] + = i_fifo_out02; +assign i_rx_out[04*deserialization_factor-1:03*deserialization_factor] + = i_fifo_out03; +assign i_rx_out[05*deserialization_factor-1:04*deserialization_factor] + = i_fifo_out04; +assign i_rx_out[06*deserialization_factor-1:05*deserialization_factor] + = i_fifo_out05; +assign i_rx_out[07*deserialization_factor-1:06*deserialization_factor] + = i_fifo_out06; +assign i_rx_out[08*deserialization_factor-1:07*deserialization_factor] + = i_fifo_out07; +assign i_rx_out[09*deserialization_factor-1:08*deserialization_factor] + = i_fifo_out08; +assign i_rx_out[10*deserialization_factor-1:09*deserialization_factor] + = i_fifo_out09; +assign i_rx_out[11*deserialization_factor-1:10*deserialization_factor] + = i_fifo_out10; +assign i_rx_out[12*deserialization_factor-1:11*deserialization_factor] + = i_fifo_out11; +assign i_rx_out[13*deserialization_factor-1:12*deserialization_factor] + = i_fifo_out12; +assign i_rx_out[14*deserialization_factor-1:13*deserialization_factor] + = i_fifo_out13; +assign i_rx_out[15*deserialization_factor-1:14*deserialization_factor] + = i_fifo_out14; +assign i_rx_out[16*deserialization_factor-1:15*deserialization_factor] + = i_fifo_out15; +assign i_rx_out[17*deserialization_factor-1:16*deserialization_factor] + = i_fifo_out16; +assign i_rx_out[18*deserialization_factor-1:17*deserialization_factor] + = i_fifo_out17; + +// assign RX outputs to i_w_rx_out wire - for the case when FIFO is bypassed +assign i_w_rx_out[01*deserialization_factor-1:00*deserialization_factor] + = w_rx_out00; +assign i_w_rx_out[02*deserialization_factor-1:01*deserialization_factor] + = w_rx_out01; +assign i_w_rx_out[03*deserialization_factor-1:02*deserialization_factor] + = w_rx_out02; +assign i_w_rx_out[04*deserialization_factor-1:03*deserialization_factor] + = w_rx_out03; +assign i_w_rx_out[05*deserialization_factor-1:04*deserialization_factor] + = w_rx_out04; +assign i_w_rx_out[06*deserialization_factor-1:05*deserialization_factor] + = w_rx_out05; +assign i_w_rx_out[07*deserialization_factor-1:06*deserialization_factor] + = w_rx_out06; +assign i_w_rx_out[08*deserialization_factor-1:07*deserialization_factor] + = w_rx_out07; +assign i_w_rx_out[09*deserialization_factor-1:08*deserialization_factor] + = w_rx_out08; +assign i_w_rx_out[10*deserialization_factor-1:09*deserialization_factor] + = w_rx_out09; +assign i_w_rx_out[11*deserialization_factor-1:10*deserialization_factor] + = w_rx_out10; +assign i_w_rx_out[12*deserialization_factor-1:11*deserialization_factor] + = w_rx_out11; +assign i_w_rx_out[13*deserialization_factor-1:12*deserialization_factor] + = w_rx_out12; +assign i_w_rx_out[14*deserialization_factor-1:13*deserialization_factor] + = w_rx_out13; +assign i_w_rx_out[15*deserialization_factor-1:14*deserialization_factor] + = w_rx_out14; +assign i_w_rx_out[16*deserialization_factor-1:15*deserialization_factor] + = w_rx_out15; +assign i_w_rx_out[17*deserialization_factor-1:16*deserialization_factor] + = w_rx_out16; +assign i_w_rx_out[18*deserialization_factor-1:17*deserialization_factor] + = w_rx_out17; + +// assign the correct signals to the output ports +assign rx_out = (deserialization_factor == 1) ? rx_in : + (bypass_fifo == "OFF") ? i_rx_out[deserialization_factor*number_of_channels-1:0] : i_w_rx_out; +assign rx_outclock = (deserialization_factor > 1) ? w_rx_clkout[00] : rx_inclock; +assign rx_locklost = (deserialization_factor > 1) ? i_rx_locked[number_of_channels-1:0] : {(number_of_channels){1'b1}}; +assign rx_full = (deserialization_factor == 1) ? 0 : + (bypass_fifo == "OFF") ? ~ i_rx_full[number_of_channels-1:0] : {number_of_channels{1'bX}}; +assign rx_empty = (deserialization_factor == 1) ? 0 : + (bypass_fifo == "OFF") ? ~ i_rx_empty[number_of_channels-1:0] : {number_of_channels{1'bX}}; +assign rx_rlv = (deserialization_factor > 1) ? i_rx_rlv : 0; +assign rx_pll_locked = i_pll_locked; +assign rx_rec_clk = w_rx_clkout; + +endmodule // altcdr_rx + +// START MODULE NAME ----------------------------------------------------------- +// +// Module Name : ALTCDR_TX +// +// Description : The Clock Data Recovery (CDR) transmitter behavioral +// model. Consists of CDR transmitter for serialization, +// a PLL and FIFO. +// +// Limitations : Available for the Mercury device family only +// +// Expected results : Serial data output (tx_out), generated slow clock +// (tx_clkout), FIFO full signal (tx_full), FIFO empty signal +// (tx_empty), PLL lock signal (tx_pll_locked) +// +//END MODULE NAME -------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module altcdr_tx ( + tx_in, // required port, parallel data input + tx_inclock, // required port, input reference clock + tx_coreclock, // required port, input core clock + tx_aclr, // asynchronous clear for TX and FIFO + tx_pll_aclr, // asynchronous clear for the PLL + tx_fifo_wren, // write enable for the FIFO + tx_out, // serial data output + tx_outclock, // generated slow clock + tx_pll_locked, // PLL lock signal + tx_full, // FIFO full indicator + tx_empty // FIFO empty indicator +); + +// GLOBAL PARAMETER DECLARATION +parameter number_of_channels = 1; +parameter deserialization_factor = 3; // Valid deserialization_factor +parameter inclock_period = 0; // units in ps +parameter inclock_boost = 1; +parameter bypass_fifo = "OFF"; +parameter intended_device_family = "MERCURY"; +parameter lpm_type = "altcdr_tx"; +parameter lpm_hint = "UNUSED"; + +// LOCAL PARAMETER DECLARATION +parameter MAX_DATA_WIDTH = deserialization_factor - 1; + +// INPUT PORT DECLARATION +input [deserialization_factor*number_of_channels-1:0] tx_in; +input tx_inclock; +input tx_coreclock; +input tx_aclr; +input tx_pll_aclr; +input [number_of_channels-1:0] tx_fifo_wren; + +// OUTPUT PORT DECLARATION +output [number_of_channels-1:0] tx_out; +output tx_outclock; +output tx_pll_locked; +output [number_of_channels-1:0] tx_full; +output [number_of_channels-1:0] tx_empty; + +// Default values for inputs -- pullup/pulldown +tri0 tx_aclr_pulldown; +tri0 tx_pll_aclr_pulldown; +tri1 [17:0] tx_fifo_wren_pullup; + +// INTERNAL VARIABLE/REGISTER DECLARATION +wire w_tx_clk; +wire w_tx_clk1; +wire i_tx_pll_locked; +wire [17:0] i_tx_full; +wire [17:0] i_tx_empty; +wire [17:0] w_tx_out; +wire [17:0] w_tx_clkout; +wire [MAX_DATA_WIDTH:0] txin00; +wire [MAX_DATA_WIDTH:0] txin01; +wire [MAX_DATA_WIDTH:0] txin02; +wire [MAX_DATA_WIDTH:0] txin03; +wire [MAX_DATA_WIDTH:0] txin04; +wire [MAX_DATA_WIDTH:0] txin05; +wire [MAX_DATA_WIDTH:0] txin06; +wire [MAX_DATA_WIDTH:0] txin07; +wire [MAX_DATA_WIDTH:0] txin08; +wire [MAX_DATA_WIDTH:0] txin09; +wire [MAX_DATA_WIDTH:0] txin10; +wire [MAX_DATA_WIDTH:0] txin11; +wire [MAX_DATA_WIDTH:0] txin12; +wire [MAX_DATA_WIDTH:0] txin13; +wire [MAX_DATA_WIDTH:0] txin14; +wire [MAX_DATA_WIDTH:0] txin15; +wire [MAX_DATA_WIDTH:0] txin16; +wire [MAX_DATA_WIDTH:0] txin17; +wire [MAX_DATA_WIDTH:0] i_fifo_out00; +wire [MAX_DATA_WIDTH:0] i_fifo_out01; +wire [MAX_DATA_WIDTH:0] i_fifo_out02; +wire [MAX_DATA_WIDTH:0] i_fifo_out03; +wire [MAX_DATA_WIDTH:0] i_fifo_out04; +wire [MAX_DATA_WIDTH:0] i_fifo_out05; +wire [MAX_DATA_WIDTH:0] i_fifo_out06; +wire [MAX_DATA_WIDTH:0] i_fifo_out07; +wire [MAX_DATA_WIDTH:0] i_fifo_out08; +wire [MAX_DATA_WIDTH:0] i_fifo_out09; +wire [MAX_DATA_WIDTH:0] i_fifo_out10; +wire [MAX_DATA_WIDTH:0] i_fifo_out11; +wire [MAX_DATA_WIDTH:0] i_fifo_out12; +wire [MAX_DATA_WIDTH:0] i_fifo_out13; +wire [MAX_DATA_WIDTH:0] i_fifo_out14; +wire [MAX_DATA_WIDTH:0] i_fifo_out15; +wire [MAX_DATA_WIDTH:0] i_fifo_out16; +wire [MAX_DATA_WIDTH:0] i_fifo_out17; +wire [MAX_DATA_WIDTH:0] i_tx_in00; +wire [MAX_DATA_WIDTH:0] i_tx_in01; +wire [MAX_DATA_WIDTH:0] i_tx_in02; +wire [MAX_DATA_WIDTH:0] i_tx_in03; +wire [MAX_DATA_WIDTH:0] i_tx_in04; +wire [MAX_DATA_WIDTH:0] i_tx_in05; +wire [MAX_DATA_WIDTH:0] i_tx_in06; +wire [MAX_DATA_WIDTH:0] i_tx_in07; +wire [MAX_DATA_WIDTH:0] i_tx_in08; +wire [MAX_DATA_WIDTH:0] i_tx_in09; +wire [MAX_DATA_WIDTH:0] i_tx_in10; +wire [MAX_DATA_WIDTH:0] i_tx_in11; +wire [MAX_DATA_WIDTH:0] i_tx_in12; +wire [MAX_DATA_WIDTH:0] i_tx_in13; +wire [MAX_DATA_WIDTH:0] i_tx_in14; +wire [MAX_DATA_WIDTH:0] i_tx_in15; +wire [MAX_DATA_WIDTH:0] i_tx_in16; +wire [MAX_DATA_WIDTH:0] i_tx_in17; +wire [359:0] tx_in_int; // 360 = 18 channels * 20 bits (18=maximum number of channels, 20=maximum channel width) + +// INITIAL BLOCK +initial +begin + + // Begin of parameter checking + if (number_of_channels <= 0) + begin + $display("ERROR: The number_of_channels parameter must be greater than 0"); + $stop; + end + + if (!(((deserialization_factor >= 3 ) && (deserialization_factor <= 12)) || + (deserialization_factor == 14) || (deserialization_factor == 16) || + (deserialization_factor == 18) || (deserialization_factor == 20))) + begin + $display("ERROR: Illegal value for deserialization_factor parameter (%d) -- value ", deserialization_factor); + $display(" must be in the range 3 to 12, inclusive, or must be one of 14, 16, 18, or 20"); + $stop; + end + + + // End of parameter checking + +end + + + +assign tx_aclr_pulldown = tx_aclr; +assign tx_pll_aclr_pulldown = tx_pll_aclr; +assign tx_fifo_wren_pullup = tx_fifo_wren; + +// COMPONENT INSTANTIATION + + //------------------------------------------------------------- + // Instantiate HSSI_TX - maximum of 18 channels + hssi_tx tx00 ( + .datain (txin00), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[00]), .clkout (w_tx_clkout[00]) ); + defparam + tx00.channel_width = deserialization_factor; + + hssi_tx tx01 ( + .datain (txin01), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[01]), .clkout (w_tx_clkout[01]) ); + defparam + tx01.channel_width = deserialization_factor; + + hssi_tx tx02 ( + .datain (txin02), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[02]), .clkout (w_tx_clkout[02]) ); + defparam + tx02.channel_width = deserialization_factor; + + hssi_tx tx03 ( + .datain (txin03), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[03]), .clkout (w_tx_clkout[03]) ); + defparam + tx03.channel_width = deserialization_factor; + + hssi_tx tx04 ( + .datain (txin04), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[04]), .clkout (w_tx_clkout[04]) ); + defparam + tx04.channel_width = deserialization_factor; + + hssi_tx tx05 ( + .datain (txin05), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[05]), .clkout (w_tx_clkout[05]) ); + defparam + tx05.channel_width = deserialization_factor; + + hssi_tx tx06 ( + .datain (txin06), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[06]), .clkout (w_tx_clkout[06]) ); + defparam + tx06.channel_width = deserialization_factor; + + hssi_tx tx07 ( + .datain (txin07), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[07]), .clkout (w_tx_clkout[07]) ); + defparam + tx07.channel_width = deserialization_factor; + + hssi_tx tx08 ( + .datain (txin08), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[08]), .clkout (w_tx_clkout[08]) ); + defparam + tx08.channel_width = deserialization_factor; + + hssi_tx tx09 ( + .datain (txin09), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[09]), .clkout (w_tx_clkout[09]) ); + defparam + tx09.channel_width = deserialization_factor; + + hssi_tx tx10 ( + .datain (txin10), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[10]), .clkout (w_tx_clkout[10]) ); + defparam + tx10.channel_width = deserialization_factor; + + hssi_tx tx11 ( + .datain (txin11), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[11]), .clkout (w_tx_clkout[11]) ); + defparam + tx11.channel_width = deserialization_factor; + + hssi_tx tx12 ( + .datain (txin12), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[12]), .clkout (w_tx_clkout[12]) ); + defparam + tx12.channel_width = deserialization_factor; + + hssi_tx tx13 ( + .datain (txin13), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[13]), .clkout (w_tx_clkout[13]) ); + defparam + tx13.channel_width = deserialization_factor; + + hssi_tx tx14 ( + .datain (txin14), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[14]), .clkout (w_tx_clkout[14]) ); + defparam + tx14.channel_width = deserialization_factor; + + hssi_tx tx15 ( + .datain (txin15), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[15]), .clkout (w_tx_clkout[15]) ); + defparam + tx15.channel_width = deserialization_factor; + + hssi_tx tx16 ( + .datain (txin16), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[16]), .clkout (w_tx_clkout[16]) ); + defparam + tx16.channel_width = deserialization_factor; + + hssi_tx tx17 ( + .datain (txin17), .clk (w_tx_clk), .areset (tx_aclr_pulldown), + .dataout (w_tx_out[17]), .clkout (w_tx_clkout[17]) ); + defparam + tx17.channel_width = deserialization_factor; + + + //--------------------------------------------------------- + // Instantiate HSSI_PLL - use the same PLL for all channels + + hssi_pll pll0 ( + .clk (tx_inclock), .areset (tx_pll_aclr_pulldown), + .clk0 (w_tx_clk), .clk1 (w_tx_clk1), .locked (i_tx_pll_locked) ); + defparam + pll0.clk0_multiply_by = inclock_boost, + pll0.input_frequency = inclock_period; + + + //-------------------------------------------------------- + // Instantiate HSSI_FIFO - maximum of 18 channels + + hssi_fifo fifo00 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[00]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[00]), .datain (i_tx_in00), + .overflow (i_tx_full[00]), .empty (i_tx_empty[00]), + .dataout (i_fifo_out00) ); + defparam + fifo00.channel_width = deserialization_factor; + + hssi_fifo fifo01 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[01]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[01]), .datain (i_tx_in01), + .overflow (i_tx_full[01]), .empty (i_tx_empty[01]), + .dataout (i_fifo_out01) ); + defparam + fifo01.channel_width = deserialization_factor; + + hssi_fifo fifo02 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[02]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[02]), .datain (i_tx_in02), + .overflow (i_tx_full[02]), .empty (i_tx_empty[02]), + .dataout (i_fifo_out02) ); + defparam + fifo02.channel_width = deserialization_factor; + + hssi_fifo fifo03 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[03]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[03]), .datain (i_tx_in03), + .overflow (i_tx_full[03]), .empty (i_tx_empty[03]), + .dataout (i_fifo_out03) ); + defparam + fifo03.channel_width = deserialization_factor; + + hssi_fifo fifo04 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[04]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[04]), .datain (i_tx_in04), + .overflow (i_tx_full[04]), .empty (i_tx_empty[04]), + .dataout (i_fifo_out04) ); + defparam + fifo04.channel_width = deserialization_factor; + + hssi_fifo fifo05 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[05]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[05]), .datain (i_tx_in05), + .overflow (i_tx_full[05]), .empty (i_tx_empty[05]), + .dataout (i_fifo_out05) ); + defparam + fifo05.channel_width = deserialization_factor; + + hssi_fifo fifo06 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[06]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[06]), .datain (i_tx_in06), + .overflow (i_tx_full[06]), .empty (i_tx_empty[06]), + .dataout (i_fifo_out06) ); + defparam + fifo06.channel_width = deserialization_factor; + + hssi_fifo fifo07 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[07]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[07]), .datain (i_tx_in07), + .overflow (i_tx_full[07]), .empty (i_tx_empty[07]), + .dataout (i_fifo_out07) ); + defparam + fifo07.channel_width = deserialization_factor; + + hssi_fifo fifo08 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[08]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[08]), .datain (i_tx_in08), + .overflow (i_tx_full[08]), .empty (i_tx_empty[08]), + .dataout (i_fifo_out08) ); + defparam + fifo08.channel_width = deserialization_factor; + + hssi_fifo fifo09 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[09]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[09]), .datain (i_tx_in09), + .overflow (i_tx_full[09]), .empty (i_tx_empty[09]), + .dataout (i_fifo_out09) ); + defparam + fifo09.channel_width = deserialization_factor; + + hssi_fifo fifo10 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[10]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[10]), .datain (i_tx_in10), + .overflow (i_tx_full[10]), .empty (i_tx_empty[10]), + .dataout (i_fifo_out10) ); + defparam + fifo10.channel_width = deserialization_factor; + + hssi_fifo fifo11 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[11]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[11]), .datain (i_tx_in11), + .overflow (i_tx_full[11]), .empty (i_tx_empty[11]), + .dataout (i_fifo_out11) ); + defparam + fifo11.channel_width = deserialization_factor; + + hssi_fifo fifo12 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[12]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[12]), .datain (i_tx_in12), + .overflow (i_tx_full[12]), .empty (i_tx_empty[12]), + .dataout (i_fifo_out12) ); + defparam + fifo12.channel_width = deserialization_factor; + + hssi_fifo fifo13 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[13]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[13]), .datain (i_tx_in13), + .overflow (i_tx_full[13]), .empty (i_tx_empty[13]), + .dataout (i_fifo_out13) ); + defparam + fifo13.channel_width = deserialization_factor; + + hssi_fifo fifo14 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[14]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[14]), .datain (i_tx_in14), + .overflow (i_tx_full[14]), .empty (i_tx_empty[14]), + .dataout (i_fifo_out14) ); + defparam + fifo14.channel_width = deserialization_factor; + + hssi_fifo fifo15 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[15]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[15]), .datain (i_tx_in15), + .overflow (i_tx_full[15]), .empty (i_tx_empty[15]), + .dataout (i_fifo_out15) ); + defparam + fifo15.channel_width = deserialization_factor; + + hssi_fifo fifo16 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[16]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[16]), .datain (i_tx_in16), + .overflow (i_tx_full[16]), .empty (i_tx_empty[16]), + .dataout (i_fifo_out16) ); + defparam + fifo16.channel_width = deserialization_factor; + + hssi_fifo fifo17 ( + .clk0 (tx_coreclock), .we (tx_fifo_wren_pullup[17]), + .reset (tx_aclr_pulldown), .re (1'b1), + .clk1 (w_tx_clkout[17]), .datain (i_tx_in17), + .overflow (i_tx_full[17]), .empty (i_tx_empty[17]), + .dataout (i_fifo_out17) ); + defparam + fifo17.channel_width = deserialization_factor; + + + //-------------------------- + // Inputs + + assign tx_in_int[deserialization_factor*number_of_channels-1: 0] = + tx_in[deserialization_factor*number_of_channels-1:0]; + + assign i_tx_in00 = + tx_in_int[(01*deserialization_factor)-1:00*deserialization_factor]; + assign i_tx_in01 = + tx_in_int[(02*deserialization_factor)-1:01*deserialization_factor]; + assign i_tx_in02 = + tx_in_int[(03*deserialization_factor)-1:02*deserialization_factor]; + assign i_tx_in03 = + tx_in_int[(04*deserialization_factor)-1:03*deserialization_factor]; + assign i_tx_in04 = + tx_in_int[(05*deserialization_factor)-1:04*deserialization_factor]; + assign i_tx_in05 = + tx_in_int[(06*deserialization_factor)-1:05*deserialization_factor]; + assign i_tx_in06 = + tx_in_int[(07*deserialization_factor)-1:06*deserialization_factor]; + assign i_tx_in07 = + tx_in_int[(08*deserialization_factor)-1:07*deserialization_factor]; + assign i_tx_in08 = + tx_in_int[(09*deserialization_factor)-1:08*deserialization_factor]; + assign i_tx_in09 = + tx_in_int[(10*deserialization_factor)-1:09*deserialization_factor]; + assign i_tx_in10 = + tx_in_int[(11*deserialization_factor)-1:10*deserialization_factor]; + assign i_tx_in11 = + tx_in_int[(12*deserialization_factor)-1:11*deserialization_factor]; + assign i_tx_in12 = + tx_in_int[(13*deserialization_factor)-1:12*deserialization_factor]; + assign i_tx_in13 = + tx_in_int[(14*deserialization_factor)-1:13*deserialization_factor]; + assign i_tx_in14 = + tx_in_int[(15*deserialization_factor)-1:14*deserialization_factor]; + assign i_tx_in15 = + tx_in_int[(16*deserialization_factor)-1:15*deserialization_factor]; + assign i_tx_in16 = + tx_in_int[(17*deserialization_factor)-1:16*deserialization_factor]; + assign i_tx_in17 = + tx_in_int[(18*deserialization_factor)-1:17*deserialization_factor]; + + +//------------------------------------------------------------------ +// select the input for hssi_tx - from FIFO or from data input directly +assign txin00 = (bypass_fifo == "OFF") ? i_fifo_out00 : i_tx_in00; +assign txin01 = (bypass_fifo == "OFF") ? i_fifo_out01 : i_tx_in01; +assign txin02 = (bypass_fifo == "OFF") ? i_fifo_out02 : i_tx_in02; +assign txin03 = (bypass_fifo == "OFF") ? i_fifo_out03 : i_tx_in03; +assign txin04 = (bypass_fifo == "OFF") ? i_fifo_out04 : i_tx_in04; +assign txin05 = (bypass_fifo == "OFF") ? i_fifo_out05 : i_tx_in05; +assign txin06 = (bypass_fifo == "OFF") ? i_fifo_out06 : i_tx_in06; +assign txin07 = (bypass_fifo == "OFF") ? i_fifo_out07 : i_tx_in07; +assign txin08 = (bypass_fifo == "OFF") ? i_fifo_out08 : i_tx_in08; +assign txin09 = (bypass_fifo == "OFF") ? i_fifo_out09 : i_tx_in09; +assign txin10 = (bypass_fifo == "OFF") ? i_fifo_out10 : i_tx_in10; +assign txin11 = (bypass_fifo == "OFF") ? i_fifo_out11 : i_tx_in11; +assign txin12 = (bypass_fifo == "OFF") ? i_fifo_out12 : i_tx_in12; +assign txin13 = (bypass_fifo == "OFF") ? i_fifo_out13 : i_tx_in13; +assign txin14 = (bypass_fifo == "OFF") ? i_fifo_out14 : i_tx_in14; +assign txin15 = (bypass_fifo == "OFF") ? i_fifo_out15 : i_tx_in15; +assign txin16 = (bypass_fifo == "OFF") ? i_fifo_out16 : i_tx_in16; +assign txin17 = (bypass_fifo == "OFF") ? i_fifo_out17 : i_tx_in17; + +//----------------------------------------------- +// assign the correct signals to the output ports + +assign tx_out = (deserialization_factor > 1) ? + w_tx_out[number_of_channels-1:0] + : tx_in; + +assign tx_outclock = (deserialization_factor > 1) ? + w_tx_clkout[00] + : tx_inclock; + +assign tx_full = (deserialization_factor == 1) ? + 0 + : (bypass_fifo == "OFF") ? + ~i_tx_full[number_of_channels-1:0] + : {number_of_channels{1'bX}}; + +assign tx_empty = (deserialization_factor == 1) ? + 0 + : (bypass_fifo == "OFF") ? + ~i_tx_empty[number_of_channels-1:0] + : {number_of_channels{1'bX}}; + +assign tx_pll_locked = i_tx_pll_locked; + +endmodule // altcdr_tx + +//START_MODULE_NAME---------------------------------------------------- +// +// Module Name : altlvds_rx +// +// Description : Low Voltage Differential Signaling (LVDS) receiver +// megafunction. The altlvds_rx megafunction implements a +// deserialization receiver. LVDS is a high speed IO interface +// that uses inputs without a reference voltage. LVDS uses +// two wires carrying differential values to create a single +// channel. These wires are connected to two pins on +// supported device to create a single LVDS channel +// +// Limitation : Only available for APEX20KE, APEXII, MERCURY, STRATIX, +// STRATIX GX, Stratix II, Cyclone and Cyclone II families. +// +// Results expected: output clock, deserialized output data and pll locked +// signal. +// +//END_MODULE_NAME---------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module altlvds_rx ( + rx_in, + rx_inclock, + rx_enable, + rx_deskew, + rx_pll_enable, + rx_data_align, + rx_reset, + rx_dpll_reset, + rx_dpll_hold, + rx_dpll_enable, + rx_fifo_reset, + rx_channel_data_align, + rx_cda_reset, + rx_coreclk, + pll_areset, + rx_out, + rx_outclock, + rx_locked, + rx_dpa_locked, + rx_cda_max +); + +// GLOBAL PARAMETER DECLARATION + parameter number_of_channels = 1; + parameter deserialization_factor = 4; + parameter registered_output = "ON"; + parameter inclock_period = 10000; + parameter inclock_boost = deserialization_factor; + parameter cds_mode = "UNUSED"; + parameter intended_device_family = "APEX20KE"; + parameter input_data_rate =0; + parameter inclock_data_alignment = "EDGE_ALIGNED"; + parameter registered_data_align_input = "ON"; + parameter common_rx_tx_pll = "ON"; + parameter enable_dpa_mode = "OFF"; + parameter enable_dpa_fifo = "ON"; + parameter use_dpll_rawperror = "OFF"; + parameter use_coreclock_input = "OFF"; + parameter dpll_lock_count = 0; + parameter dpll_lock_window = 0; + parameter outclock_resource = "AUTO"; + parameter data_align_rollover = deserialization_factor; + parameter lose_lock_on_one_change ="OFF" ; + parameter reset_fifo_at_first_lock ="ON" ; + parameter use_external_pll = "OFF"; + parameter implement_in_les = "OFF"; + parameter port_rx_data_align = "PORT_CONNECTIVITY"; + parameter lpm_hint = "UNUSED"; + parameter lpm_type = "altlvds_rx"; + + // Specifies whether the source of the input clock is from a PLL + parameter clk_src_is_pll = "off"; + +// LOCAL PARAMETER DECLARATION + + // A APEX20KE type of LVDS? + parameter APEX20KE_RX_STYLE = ((intended_device_family == "APEX20KE") || + (intended_device_family == "APEX20KC") || + (intended_device_family == "EXCALIBUR_ARM") || + (intended_device_family == "EXCALIBUR_MIPS")) + ? 1 : 0; + + // A APEXII type of LVDS? + parameter APEXII_RX_STYLE = ((intended_device_family == "APEXII") || + (intended_device_family == "APEX II")) + ? 1 : 0; + + // A MERCURY type of LVDS? + parameter MERCURY_RX_STYLE = ((intended_device_family == "MERCURY") || + (intended_device_family == "Mercury")) + ? 1 : 0; + + // A STRATIX type of LVDS? + parameter STRATIX_RX_STYLE = (((intended_device_family == "Stratix") || + (intended_device_family == "STRATIX") || + (intended_device_family == "HardCopy Stratix") || + (intended_device_family == "HARDCOPY STRATIX") || + (intended_device_family == "hardcopy stratix") || + (intended_device_family == "HardcopyStratix") || + (intended_device_family == "HARDCOPYSTRATIX") || + (intended_device_family == "hardcopystratix")) || + (((intended_device_family == "STRATIXGX") || + (intended_device_family == "STRATIX-GX") || + (intended_device_family == "Stratix GX")) && + (enable_dpa_mode == "OFF"))) + ? 1 : 0; + + // A STRATIXGX DPA type of LVDS? + parameter STRATIXGX_DPA_RX_STYLE = + (((intended_device_family == "STRATIXGX") || + (intended_device_family == "STRATIX-GX") || + (intended_device_family == "Stratix GX")) && + (enable_dpa_mode == "ON")) + ? 1 : 0; + + // A STRATIX II type of LVDS? + parameter STRATIXII_RX_STYLE = ((intended_device_family == "Stratix II") || + (intended_device_family == "StratixII") || + (intended_device_family == "HardCopy II") || + (intended_device_family == "HardCopyII") || + (intended_device_family == "HARDCOPY II") || + (intended_device_family == "HARDCOPYII") || + (intended_device_family == "hardcopy ii") || + (intended_device_family == "hardcopyii") || + (intended_device_family == "Stratix II GX") || + (intended_device_family == "STRATIX II GX") || + (intended_device_family == "stratix ii gx") || + (intended_device_family == "StratixIIGX") || + (intended_device_family == "STRATIXIIGX") || + (intended_device_family == "stratixiigx")) + ? 1 : 0; + + // A Cyclone type of LVDS? + parameter CYCLONE_RX_STYLE = ((intended_device_family == "Cyclone") || + (intended_device_family == "CYCLONE") || + (intended_device_family == "cyclone")) + ? 1 : 0; + + // A Cyclone II type of LVDS? + parameter CYCLONEII_RX_STYLE = ((intended_device_family == "Cyclone II") || + (intended_device_family == "CYCLONE II") || + (intended_device_family == "cyclone ii") || + (intended_device_family == "Cycloneii") || + (intended_device_family == "CYCLONEII") || + (intended_device_family == "cycloneii")) + ? 1 : 0; + + // Is the device family has flexible LVDS? + parameter FAMILY_HAS_FLEXIBLE_LVDS = ((CYCLONE_RX_STYLE == 1) || + (CYCLONEII_RX_STYLE == 1) || + (((STRATIX_RX_STYLE == 1) || + (STRATIXII_RX_STYLE == 1)) && + (implement_in_les == "ON"))) + ? 1 : 0; + + // Is the family has Stratix style PLL + parameter FAMILY_HAS_STRATIX_STYLE_PLL = ((STRATIX_RX_STYLE == 1) || + (STRATIXGX_DPA_RX_STYLE == 1) || + (CYCLONE_RX_STYLE == 1)) + ? 1 : 0; + + // Is the family has Stratix style PLL + parameter FAMILY_HAS_STRATIXII_STYLE_PLL = ((STRATIXII_RX_STYLE == 1) || + (CYCLONEII_RX_STYLE == 1)) + ? 1 : 0; + + // Parameter to check whether the selected lvds trasmitter use hold register + // or not + parameter RX_NEED_HOLD_REG = (((APEX20KE_RX_STYLE == 1) && + (deserialization_factor == 4 )) || + ((APEXII_RX_STYLE == 1) && + (deserialization_factor == 4)) || + ((MERCURY_RX_STYLE == 1) && + (deserialization_factor > 2) && + (deserialization_factor < 7))) + ? 1 : 0; + + // calculate clock boost for device family other than STRATIX, STRATIX GX + // and STRATIX II + parameter INT_CLOCK_BOOST = (APEX20KE_RX_STYLE == 1) + ? deserialization_factor : + ( (inclock_boost == 0) + ? deserialization_factor + : inclock_boost); + + // M value for stratix/stratix II/Cyclone/Cyclone II PLL + parameter PLL_M_VALUE = (((input_data_rate * inclock_period) + + (5 * 100000)) / 1000000); + + // D value for Stratix/Stratix II/Cyclone/Cyclone II PLL + parameter PLL_D_VALUE = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? ((input_data_rate !=0) && (inclock_period !=0) + ? 2 + : 1) + : 1; + + // calculate clock boost for STRATIX, STRATIX GX and STRATIX II + parameter STRATIX_INCLOCK_BOOST = ((input_data_rate !=0) && + (inclock_period !=0)) + ? PLL_M_VALUE : + ((inclock_boost == 0) + ? deserialization_factor + : inclock_boost); + + // phase_shift delay. Add 0.5 to the calculated result to round up result to + // the nearest integer. + parameter PHASE_SHIFT = + (inclock_data_alignment == "EDGE_ALIGNED") + ? 0 : + (inclock_data_alignment == "CENTER_ALIGNED") + ? (0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 : + (inclock_data_alignment == "45_DEGREES") + ? (0.125 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 : + (inclock_data_alignment == "90_DEGREES") + ? (0.25 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 : + (inclock_data_alignment == "135_DEGREES") + ? (0.375 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 : + (inclock_data_alignment == "180_DEGREES") + ? (0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 : + (inclock_data_alignment == "225_DEGREES") + ? (0.625 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 : + (inclock_data_alignment == "270_DEGREES") + ? (0.75 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 : + (inclock_data_alignment == "315_DEGREES") + ? (0.875 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5 + : 0; + + // parameter for Stratix II inclock phase shift. + parameter STXII_PHASE_SHIFT = PHASE_SHIFT - + (0.5 * inclock_period / STRATIX_INCLOCK_BOOST); + + parameter REGISTER_WIDTH = deserialization_factor * number_of_channels; + + // input clock period for PLL. + parameter CLOCK_PERIOD = (deserialization_factor > 2) + ? inclock_period + : 10000; + +// INPUT PORT DECLARATION + input [number_of_channels -1 :0] rx_in; + input rx_inclock; + input rx_enable; + input rx_deskew; + input rx_pll_enable; + input rx_data_align; + input [number_of_channels -1 :0] rx_reset; + input [number_of_channels -1 :0] rx_dpll_reset; + input [number_of_channels -1 :0] rx_dpll_hold; + input [number_of_channels -1 :0] rx_dpll_enable; + input [number_of_channels -1 :0] rx_fifo_reset; + input [number_of_channels -1 :0] rx_channel_data_align; + input [number_of_channels -1 :0] rx_cda_reset; + input [number_of_channels -1 :0] rx_coreclk; + input pll_areset; + +// OUTPUT PORT DECLARATION + output [REGISTER_WIDTH -1: 0] rx_out; + output rx_outclock; + output rx_locked; + output [number_of_channels -1: 0] rx_dpa_locked; + output [number_of_channels -1: 0] rx_cda_max; + + +// INTERNAL REGISTERS DECLARATION + reg [REGISTER_WIDTH -1 : 0] pattern; + reg [REGISTER_WIDTH -1 : 0] rx_shift_reg; + reg [REGISTER_WIDTH -1 : 0] rx_parallel_load_reg; + reg [REGISTER_WIDTH -1 : 0] rx_out_reg; + reg [REGISTER_WIDTH -1 : 0] rx_out_hold; + reg [number_of_channels-1 : 0] deskew_done; + reg calibrate; + reg fb; + reg rx_mercury_slow_clock; + reg [deserialization_factor-1 : 0] temp; + reg [9 : 0] deskew_pattern; + reg [number_of_channels -1 : 0] rx_reg_clk_pre; + reg rx_data_align_reg; + + // for x2 mode (deserialization_factor = 2) + reg [REGISTER_WIDTH -1 : 0] rx_ddio_in; + reg [number_of_channels -1 : 0] rx_in_latched; + +// INTERNAL WIRE DECLARATION + wire [REGISTER_WIDTH -1 : 0] rx_out_int; + wire [REGISTER_WIDTH -1 : 0] stratix_dataout; + wire [REGISTER_WIDTH -1 : 0] stratixgx_dataout; + wire [REGISTER_WIDTH -1 : 0] stratixii_dataout; + wire [REGISTER_WIDTH -1 : 0] flvds_dataout; + wire [number_of_channels -1 : 0] stratixgx_dpa_locked; + wire [number_of_channels -1 : 0] stratixii_dpa_locked; + wire rx_fastclk; + wire rx_slowclk; + wire rx_locked_int; + wire rx_outclk_int; + wire rx_hold_clk; + wire rx_data_align_clk; + wire [number_of_channels -1 : 0] rx_reg_clk; + wire altclklock_inclock; + wire altclklock_fastclk; + wire altclklock_slowclk; + wire altclklock_locked; + wire[1:0] stratix_pll_inclock; + wire[1:0] stratixii_pll_inclock; + wire[5:0] stratix_pll_outclock; + wire[5:0] stratixii_pll_outclock; + wire stratix_pll_enable; + wire stratixii_pll_enable; + wire stratix_pll_areset; + wire stratixii_pll_areset; + wire stratixii_sclkout0; + wire stratixii_sclkout1; + wire stratix_locked; + wire stratixii_locked; + wire stratix_enable0; + wire stratix_enable1; + wire stratixii_enable0; + wire stratixii_enable1; + wire unused_clk2; + wire unused_clk_ext; + wire stratix_fastclk; + wire stratix_slowclk; + wire stratixgx_fastclk; + wire stratixgx_slowclk; + wire[number_of_channels -1 :0] stratixgx_coreclk; + wire stratixii_fastclk; + wire stratixii_enable; + wire flvds_fastclk; + wire flvds_slowclk; + wire flvds_syncclk; + wire rx_data_align_int; + wire rx_data_align_pulldown; + wire[number_of_channels -1 :0] rx_channel_data_align_int; + +// INTERNAL TRI DECLARATION + tri0 rx_deskew; + tri1 rx_pll_enable; + tri0[number_of_channels -1 :0] rx_reset; + tri0[number_of_channels -1 :0] rx_dpll_reset; + tri0[number_of_channels -1 :0] rx_dpll_hold; + tri1[number_of_channels -1 :0] rx_dpll_enable; + tri0[number_of_channels -1 :0] rx_fifo_reset; + tri0[number_of_channels -1 :0] rx_cda_reset; + tri0[number_of_channels -1 :0] rx_coreclk; + tri0 pll_areset; + +// LOCAL INTEGER DECLARATION + integer count [number_of_channels-1 : 0]; + integer sample; + integer i; + integer i1; + integer i2; + integer i3; + integer i4; + integer i5; + integer j; + integer j1; + integer x; + integer posedge_count; + integer negedge_count; + integer rxin_cnt; + integer start_data; + integer check_deskew_pattern; + +// COMPONENT INSTANTIATIONS + ALTERA_DEVICE_FAMILIES dev (); + +// FUNCTION DECLARATIONS + + // check whether the same pattern is found in the given input data + // for a particular channel. + function pattern_match; + input input_data, deskrew_pattern, dfactor, channel_num; + integer dfactor, channel_num; + reg[(20*10)-1 : 0] input_data; + reg[9 : 0] deskrew_pattern; + reg[9 : 0] input_pattern; + integer i; + begin + + pattern_match = 1; + + for (i = 0; i < deserialization_factor; i = i + 1) + begin + if(input_data[dfactor*channel_num +i] !== deskrew_pattern[i]) + begin + pattern_match = 0; + end + end + end + endfunction // pattern_match + +// INITIAL CONSTRUCT BLOCK + initial + begin : INITIALIZATION + fb = 1'b1; + rxin_cnt = 0; + negedge_count = 0; + posedge_count = 0; + start_data = 0; + rx_data_align_reg = 1'b0; + rx_mercury_slow_clock = 1'b0; + calibrate = 0; + deskew_done = {number_of_channels{1'b1}}; + rx_in_latched = {number_of_channels{1'b0}}; + + for (i = 0; i < number_of_channels; i = i + 1) + count[i] = 0; + + rx_out_reg = {REGISTER_WIDTH{1'b0}}; + rx_out_hold = {REGISTER_WIDTH{1'b0}}; + rx_shift_reg = {REGISTER_WIDTH{1'b0}}; + rx_parallel_load_reg = {REGISTER_WIDTH{1'b0}}; + rx_ddio_in = {REGISTER_WIDTH{1'b0}}; + + // Check for illegal mode settings + if ((APEX20KE_RX_STYLE == 1) && (deserialization_factor != 1) && + (deserialization_factor != 4) && (deserialization_factor != 7) && + (deserialization_factor != 8)) + begin + $display ($time, "ps Error: APEX20KE does not support the specified deserialization factor!"); + $finish; + end + else if ((MERCURY_RX_STYLE == 1) && + (deserialization_factor != 1) && (deserialization_factor != 2) && + (((deserialization_factor > 12) && (deserialization_factor != 14) && + (deserialization_factor != 16) && (deserialization_factor != 18) && + (deserialization_factor != 20)) || (deserialization_factor<3))) + begin + $display ($time, "ps Error: MERCURY does not support the specified deserialization factor!"); + $finish; + end + else if ((APEXII_RX_STYLE == 1) && + ((deserialization_factor > 10) || (deserialization_factor < 4)) && + (deserialization_factor != 1) && (deserialization_factor != 2)) + begin + $display ($time, "ps Error: APEXII does not support the specified deserialization factor!"); + $finish; + end + else if ((STRATIX_RX_STYLE == 1) && + (deserialization_factor != 1) && (deserialization_factor != 2) && + ((deserialization_factor > 10) || (deserialization_factor < 4))) + begin + $display ($time, "ps Error: STRATIX or STRATIXGX in non DPA mode does not support the specified deserialization factor!"); + $finish; + end + else if ((STRATIXGX_DPA_RX_STYLE == 1) && (deserialization_factor != 8) && (deserialization_factor != 10)) + begin + $display ($time, "ps Error: STRATIXGX in DPA mode does not support the specified deserialization factor!"); + $finish; + end + + if ((STRATIXII_RX_STYLE == 1) && + (deserialization_factor > 10)) + begin + $display ($time, "ps Error: STRATIX II does not support the specified deserialization factor!"); + $finish; + end + + if ((STRATIXII_RX_STYLE == 1) && + (data_align_rollover > 11)) + begin + $display ($time, "ps Error: STRATIX II does not support data align rollover values > 11 !"); + $finish; + end + + if (CYCLONE_RX_STYLE == 1) + begin + if ((use_external_pll == "ON") && + (deserialization_factor != 1) && (deserialization_factor != 2) && + (deserialization_factor != 4) && (deserialization_factor != 6) && + (deserialization_factor != 8) && (deserialization_factor != 10)) + begin + $display ($time, "ps Error: Cyclone does not support the specified deserialization factor when use_external_pll is 'ON'!"); + $finish; + end + else if ((deserialization_factor > 10) || (deserialization_factor == 3)) + begin + $display ($time, "ps Error: Cyclone does not support the specified deserialization factor when use_external_pll is 'OFF'!"); + $finish; + end + end + + if (CYCLONEII_RX_STYLE == 1) + begin + if ((use_external_pll == "ON") && + (deserialization_factor != 1) && (deserialization_factor != 2) && + (deserialization_factor != 4) && (deserialization_factor != 6) && + (deserialization_factor != 8) && (deserialization_factor != 10)) + begin + $display ($time, "ps Error: Cyclone II does not support the specified deserialization factor when use_external_pll is 'ON'!"); + $finish; + end + else if ((deserialization_factor > 10) || (deserialization_factor == 3)) + begin + $display ($time, "ps Error: Cyclone II does not support the specified deserialization factor when use_external_pll is 'OFF'!"); + $finish; + end + end + + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $finish; + end + + // Initialise calibration pattern variables. Only for APEX20KE and APEXII + if ((APEX20KE_RX_STYLE == 1) && + ((deserialization_factor == 4) || (deserialization_factor == 7) || + (deserialization_factor == 8))) + begin + check_deskew_pattern = 1; + case (deserialization_factor) + 8: deskew_pattern[7:0] = 8'b00111100; + 7: deskew_pattern[6:0] = 7'b0011100; + 4: deskew_pattern[3:0] = 4'b1100; + default ; + endcase + end + else + if (((APEXII_RX_STYLE == 1)) && (deserialization_factor <= 10) && + (deserialization_factor >= 4)) + begin + check_deskew_pattern = 1; + if (cds_mode == "SINGLE_BIT") + begin + case (deserialization_factor) + 10: deskew_pattern[9:0] = 10'b0000011111; + 9: deskew_pattern[8:0] = 9'b000001111; + 8: deskew_pattern[7:0] = 8'b00001111; + 7: deskew_pattern[6:0] = 7'b0000111; + 6: deskew_pattern[5:0] = 6'b000111; + 5: deskew_pattern[4:0] = 5'b00011; + 4: deskew_pattern[3:0] = 4'b0011; + default ; + endcase + end + else + begin + case (deserialization_factor) + 10: deskew_pattern[9:0] = 10'b0101010101; + 9: deskew_pattern[8:0] = 9'b010101010; + 8: deskew_pattern[7:0] = 8'b01010101; + 7: deskew_pattern[6:0] = 7'b0101010; + 6: deskew_pattern[5:0] = 6'b010101; + 5: deskew_pattern[4:0] = 5'b01010; + 4: deskew_pattern[3:0] = 4'b0101; + default ; + endcase + end + end + else check_deskew_pattern = 0; + + end //INITIALIZATION + + // NCSIM will only assigns 1'bZ to unconnected port at time 0fs + 1 + initial #0 + begin + if ((STRATIXII_RX_STYLE == 1) && + (rx_channel_data_align === {number_of_channels{1'bZ}}) && + (rx_data_align !== 1'bZ)) + begin + $display("Warning : Data alignment on Stratix II devices introduces one bit of latency for each assertion of the data alignment signal. In comparison, Stratix and Stratix GX devices remove one bit of latency for each assertion."); + end + end + +// COMPONENT INSTANTIATIONS + + // pll for device families other than Stratix, Stratix GX and Stratix II + altclklock u0 ( + .inclock(altclklock_inclock), + .inclocken(rx_pll_enable), + .fbin(fb), + .clock0(altclklock_fastclk), + .clock1(altclklock_slowclk), + .clock2(unused_clk2), + .clock_ext(unused_clk_ext), + .locked(altclklock_locked)); + + defparam + u0.inclock_period = CLOCK_PERIOD, + u0.clock0_boost = INT_CLOCK_BOOST, + u0.clock1_boost = INT_CLOCK_BOOST, + u0.clock1_divide = deserialization_factor, + u0.valid_lock_cycles = (APEXII_RX_STYLE == 1) ? 1 : + (MERCURY_RX_STYLE == 1) ? 3 : 5, + u0.intended_device_family = ((APEX20KE_RX_STYLE == 1 ) || + (APEXII_RX_STYLE == 1 ) || + (MERCURY_RX_STYLE == 1 )) + ? intended_device_family + : "APEX20KE"; + + // pll for Stratix and Stratix GX + MF_stratix_pll u1 ( + .inclk(stratix_pll_inclock), // Required + .ena(stratix_pll_enable), + .areset(stratix_pll_areset), + .clkena(6'b111111), + .clk (stratix_pll_outclock), + .locked(stratix_locked), + .fbin(1'b1), + .clkswitch(1'b0), + .pfdena(1'b1), + .extclkena(4'b0), + .scanclk(1'b0), + .scanaclr(1'b0), + .scandata(1'b0), + .comparator(rx_data_align_int), + .extclk(), + .clkbad(), + .enable0(stratix_enable0), + .enable1(stratix_enable1), + .activeclock(), + .clkloss(), + .scandataout()); + + defparam + u1.pll_type = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? "flvds" + : "lvds", + u1.inclk0_input_frequency = CLOCK_PERIOD, + u1.inclk1_input_frequency = CLOCK_PERIOD, + u1.valid_lock_multiplier = 1, + u1.clk0_multiply_by = STRATIX_INCLOCK_BOOST, + u1.clk0_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PLL_D_VALUE + : 1, + u1.clk1_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (deserialization_factor%2 == 1) + ? STRATIX_INCLOCK_BOOST + : 1, + u1.clk1_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (deserialization_factor%2 == 1) + ? PLL_D_VALUE*deserialization_factor + : 1, + u1.clk2_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (deserialization_factor%2 == 1) + ? STRATIX_INCLOCK_BOOST *2 + : STRATIX_INCLOCK_BOOST, + u1.clk2_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? ((deserialization_factor%2 == 0) + ? PLL_D_VALUE*deserialization_factor/2 + : PLL_D_VALUE*deserialization_factor) + : deserialization_factor, + u1.clk0_phase_shift_num = PHASE_SHIFT, + u1.clk1_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (deserialization_factor%2 == 1) + ? PHASE_SHIFT + : 1, + u1.clk2_phase_shift_num = PHASE_SHIFT, + u1.simulation_type = "functional", + u1.m = 0; + + + // pll for Stratix II + MF_stratixii_pll u2 ( + .inclk(stratixii_pll_inclock), // Required + .ena(stratixii_pll_enable), + .areset(stratixii_pll_areset), + .clk (stratixii_pll_outclock ), + .locked(stratixii_locked), + .fbin(1'b1), + .clkswitch(1'b0), + .pfdena(1'b1), + .scanclk(1'b0), + .scanread(1'b0), + .scanwrite(1'b0), + .scandata(1'b0), + .testin(4'b0), + .clkbad(), + .enable0(stratixii_enable0), + .enable1(stratixii_enable1), + .activeclock(), + .clkloss(), + .scandataout(), + .scandone(), + .sclkout({stratixii_sclkout1, stratixii_sclkout0}), + .testupout(), + .testdownout()); + + defparam + u2.pll_type = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? "flvds" + : "lvds", + u2.vco_multiply_by = STRATIX_INCLOCK_BOOST, + u2.vco_divide_by = 1, + u2.inclk0_input_frequency = CLOCK_PERIOD, + u2.inclk1_input_frequency = CLOCK_PERIOD, + u2.clk0_multiply_by = STRATIX_INCLOCK_BOOST, + u2.clk0_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PLL_D_VALUE + : deserialization_factor, + u2.clk1_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (deserialization_factor%2 == 1) + ? STRATIX_INCLOCK_BOOST + : 1, + u2.clk1_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (deserialization_factor%2 == 1) + ? PLL_D_VALUE*deserialization_factor + : 1, + u2.clk2_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (deserialization_factor%2 == 1) + ? STRATIX_INCLOCK_BOOST *2 + : STRATIX_INCLOCK_BOOST, + u2.clk2_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? ((deserialization_factor%2 == 0) + ? PLL_D_VALUE*deserialization_factor/2 + : PLL_D_VALUE*deserialization_factor) + : deserialization_factor, + u2.clk0_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PHASE_SHIFT + : STXII_PHASE_SHIFT, + u2.clk1_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (deserialization_factor%2 == 1) + ? PHASE_SHIFT + : 1, + u2.clk2_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PHASE_SHIFT + : STXII_PHASE_SHIFT, + u2.sclkout0_phase_shift = STXII_PHASE_SHIFT, + u2.simulation_type = "functional", + u2.m = 0; + + + // Stratix lvds receiver + stratix_lvds_rx u3 ( + .rx_in(rx_in), + .rx_fastclk(stratix_fastclk), + .rx_enable0(stratix_enable0), + .rx_enable1(stratix_enable1), + .rx_out(stratix_dataout)); + + defparam + u3.number_of_channels = number_of_channels, + u3.deserialization_factor = deserialization_factor; + + // Stratixgx lvds receiver with DPA mode + stratixgx_dpa_lvds_rx u4 ( + .rx_in(rx_in), + .rx_fastclk(stratixgx_fastclk), + .rx_slowclk(stratixgx_slowclk), + .rx_coreclk(stratixgx_coreclk), + .rx_locked(stratix_locked), + .rx_reset(rx_reset), + .rx_dpll_reset(rx_dpll_reset), + .rx_channel_data_align(rx_channel_data_align_int), + .rx_out(stratixgx_dataout), + .rx_dpa_locked(stratixgx_dpa_locked)); + + defparam + u4.number_of_channels = number_of_channels, + u4.deserialization_factor = deserialization_factor, + u4.use_coreclock_input = use_coreclock_input, + u4.enable_dpa_fifo = enable_dpa_fifo, + u4.registered_output = registered_output; + + + // Stratix II lvds receiver + stratixii_lvds_rx u5 ( + .rx_in(rx_in), + .rx_reset(rx_reset), + .rx_fastclk(stratixii_fastclk), + .rx_enable(stratixii_enable), + .rx_locked(stratixii_locked), + .rx_dpll_reset(rx_dpll_reset), + .rx_dpll_hold(rx_dpll_hold), + .rx_dpll_enable(rx_dpll_enable), + .rx_fifo_reset(rx_fifo_reset), + .rx_channel_data_align(rx_channel_data_align_int), + .rx_cda_reset(rx_cda_reset), + .rx_out(stratixii_dataout), + .rx_dpa_locked(stratixii_dpa_locked), + .rx_cda_max(rx_cda_max)); + + defparam + u5.number_of_channels = number_of_channels, + u5.deserialization_factor = deserialization_factor, + u5.enable_dpa_mode = enable_dpa_mode, + u5.data_align_rollover = data_align_rollover, + u5.lose_lock_on_one_change = lose_lock_on_one_change, + u5.reset_fifo_at_first_lock = reset_fifo_at_first_lock; + + // flexible lvds receiver + flexible_lvds_rx u6 ( + .rx_in(rx_in), + .rx_fastclk(flvds_fastclk), + .rx_slowclk(flvds_slowclk), + .rx_syncclk(flvds_syncclk), + .rx_locked(rx_locked_int), + .rx_out(flvds_dataout)); + + defparam + u6.number_of_channels = number_of_channels, + u6.deserialization_factor = deserialization_factor, + u6.use_extra_ddio_register = (CYCLONE_RX_STYLE == 1) || + (CYCLONEII_RX_STYLE == 1) ? "YES" : "NO", + u6.use_extra_pll_clk = (CYCLONE_RX_STYLE == 1) || + (CYCLONEII_RX_STYLE == 1) ? "NO" : "YES"; + + + +// ALWAYS CONSTRUCT BLOCK + + // For x2 mode. Data input is sampled in both the rising edge and falling + // edge of input clock. + always @(posedge rx_inclock) + begin : DDIO_IN + if (deserialization_factor == 2) + begin + for (i1 = 0; i1 <= number_of_channels-1; i1 = i1+1) + begin + rx_ddio_in[(i1*2)+1] <= rx_in[i1]; + rx_ddio_in[(i1*2)] <= rx_in_latched[i1]; + end + end + end // DDIO_IN + + always @(negedge rx_inclock) + begin : DDIO_IN_LATCH + if ((deserialization_factor == 2) && ($time > 0)) + begin + rx_in_latched <= rx_in; + end + end // DDIO_IN_LATCH + + // Activate calibration mode + always @ (posedge rx_deskew) + begin : CALIBRATION + deskew_done <= {number_of_channels{1'b0}}; + calibrate <= 1'b1; + end // CALIBRATION + + // slow clock + always @ (posedge rx_slowclk) + begin : SLOW_CLOCK + negedge_count <= 0; + + // In order to assure that the circuit is capturing data accurately + // the user must calibrate the LVDS data channels by asserting a + // deskew signal and applying the appropriate calibration value for + // 3 clock cycles to deskew the channel after 3 clock cycles. + if (check_deskew_pattern == 1) + begin + if (calibrate == 1'b1) + begin + for (j = 0; j <= number_of_channels-1; j = j+1) + begin + if (pattern_match(pattern, deskew_pattern[deserialization_factor-1:0], deserialization_factor, j) || + (pattern_match(pattern, ~deskew_pattern[deserialization_factor-1:0], deserialization_factor, j) && + (APEXII_RX_STYLE == 1) && + (cds_mode == "MULTIPLE_BIT"))) + begin + count[j] <= count[j] + 1; + + if (count[j] >= 2) + deskew_done[j] <= 1'b1; + + end + else + count[j] <= 0; + + end + end + end + + if (rx_deskew == 0) + calibrate <= 1'b0; + + end // SLOW_CLOCK + + // Fast clock (on falling edge) + always @ (negedge rx_fastclk) + begin : FAST_CLOCK_NEGEDGE + if(rx_locked_int == 1) + begin + + negedge_count <= negedge_count + 1; + + // For APEX and Mercury families, load data on the + // 3rd negative edge of the fast clock + if (negedge_count == 2) + begin + + if (rx_deskew == 0) + rx_parallel_load_reg <= rx_shift_reg; + + sample <= 1; + + for (i4= 0; i4 < number_of_channels; i4 = i4+1) + begin + if (deskew_done[i4] == 1) + begin + if(APEXII_RX_STYLE == 1) + begin + for (x=deserialization_factor-1; x >0; x=x-1) + rx_shift_reg[x + (i4 * deserialization_factor)] <= rx_shift_reg [x-1 + (i4 * deserialization_factor)]; + rx_shift_reg[i4 * deserialization_factor] <= rx_in[i4]; + end + else + // Data gets shifted into MSB first + rx_shift_reg[(i4+1)*deserialization_factor-1] <= rx_in[i4]; + end + else + begin + if(APEXII_RX_STYLE == 1) + begin + for (x=deserialization_factor-1; x >0; x=x-1) + pattern[x + (i4 * deserialization_factor)] <= pattern [x-1 + (i4 * deserialization_factor)]; + pattern[i4 * deserialization_factor] <= rx_in[i4]; + end + else + pattern[(i4+1)*deserialization_factor-1] <= rx_in[i4]; + rx_shift_reg[(i4+1)*deserialization_factor-1] <= 'bx; + end + end + + end + else + begin + // Loading input data to shift register + sample <= (sample + 1) % deserialization_factor; + + for (i4= 0; i4 < number_of_channels; i4 = i4+1) + begin + if (deskew_done[i4] == 1) + begin + if(APEXII_RX_STYLE == 1) + begin + for (x=deserialization_factor-1; x >0; x=x-1) + rx_shift_reg[x + (i4 * deserialization_factor)] <= rx_shift_reg [x-1 + (i4 * deserialization_factor)]; + rx_shift_reg[i4 * deserialization_factor] <= rx_in[i4]; + end + else + // Data gets shifted into MSB first + rx_shift_reg[(i4+1)*deserialization_factor-sample-1] <= rx_in[i4]; + end + else + begin + if(APEXII_RX_STYLE == 1) + begin + for (x=deserialization_factor-1; x >0; x=x-1) + pattern[x + (i4 * deserialization_factor)] <= pattern [x-1 + (i4 * deserialization_factor)]; + pattern[i4 * deserialization_factor] <= rx_in[i4]; + end + else + pattern[(i4+1)*deserialization_factor-sample-1] <= rx_in[i4]; + rx_shift_reg[(i4+1)*deserialization_factor-sample-1] <= 'bx; + end + end + end + end + end + + // Fast clock (on rising edge) + always @ (posedge rx_fastclk) + begin : FAST_CLOCK_POSEDGE + if(rx_locked_int == 1) + begin + if (deserialization_factor > 2) + begin + posedge_count <= (posedge_count+1) % deserialization_factor; + + // Generating slow clock for MERCURY + if (posedge_count % ((deserialization_factor+1)/2) == 0) + begin + rx_mercury_slow_clock <= ~rx_mercury_slow_clock; + end + end + end + end // FAST_CLOCK + + // synchronization register + always @ (posedge rx_reg_clk) + begin : SYNC_REGISTER + rx_out_reg <= rx_out_int; + end // SYNC_REGISTER + + // hold register + always @ (negedge rx_hold_clk) + begin : HOLD_REGISTER + if (deserialization_factor > 1) + begin + rx_out_hold <= rx_parallel_load_reg; + end + end // HOLD_REGISTER + + // Registering rx_data_align signal for stratix II lvds_rx. + always @ (posedge rx_data_align_clk) + begin + rx_data_align_reg <= rx_data_align_pulldown; + end + +// CONTINOUS ASSIGNMENT + assign rx_out = (STRATIXGX_DPA_RX_STYLE == 1) + ? stratixgx_dataout : + (registered_output == "ON") + ? rx_out_reg + : rx_out_int; + + assign rx_out_int = (deserialization_factor == 1) + ? rx_in : + (deserialization_factor == 2) + ? rx_ddio_in : + (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? flvds_dataout : + (STRATIX_RX_STYLE == 1) + ? stratix_dataout : + (STRATIXII_RX_STYLE == 1) + ? stratixii_dataout : + (RX_NEED_HOLD_REG == 1) + ? rx_out_hold + : rx_parallel_load_reg; + + assign rx_reg_clk = (use_external_pll == "ON") + ? rx_inclock + : {number_of_channels{rx_outclk_int}}; + + assign rx_hold_clk = rx_outclk_int; + + assign rx_outclock = rx_outclk_int; + + assign rx_outclk_int = (deserialization_factor <= 2) + ? rx_inclock : + (MERCURY_RX_STYLE == 1) + ? rx_mercury_slow_clock + : rx_slowclk; + + assign rx_slowclk = ((STRATIX_RX_STYLE == 1) || + (STRATIXGX_DPA_RX_STYLE == 1) || + (CYCLONE_RX_STYLE == 1)) + ? stratix_pll_outclock[2] : + ((STRATIXII_RX_STYLE == 1) || + (CYCLONEII_RX_STYLE == 1)) + ? stratixii_pll_outclock[2] + : altclklock_slowclk; + + assign rx_fastclk = altclklock_fastclk; + + assign rx_locked = (deserialization_factor > 2) + ? rx_locked_int + : 1'b1; + + assign rx_locked_int = ((STRATIX_RX_STYLE == 1) || + (STRATIXGX_DPA_RX_STYLE == 1) || + (CYCLONE_RX_STYLE == 1)) + ? stratix_locked : + ((STRATIXII_RX_STYLE == 1) || + (CYCLONEII_RX_STYLE == 1)) + ? stratixii_locked + : altclklock_locked; + + assign rx_dpa_locked = (STRATIXGX_DPA_RX_STYLE == 1) + ? stratixgx_dpa_locked : + (STRATIXII_RX_STYLE == 1) + ? stratixii_dpa_locked + : {number_of_channels{1'b1}}; + + assign rx_data_align_pulldown = (port_rx_data_align == "PORT_USED") + ? rx_data_align : + (port_rx_data_align == "PORT_UNUSED") + ? 1'b0 : + (rx_data_align !== 1'bz) + ? rx_data_align : + 1'b0; + + assign rx_data_align_int = (registered_data_align_input == "ON") + ? rx_data_align_reg + : rx_data_align_pulldown; + + assign rx_channel_data_align_int = + (rx_channel_data_align !== {number_of_channels{1'bZ}}) + ? rx_channel_data_align : + (STRATIXII_RX_STYLE == 1) + ? {number_of_channels{rx_data_align_int}} + : {number_of_channels{1'b0}}; + + assign rx_data_align_clk = ((STRATIX_RX_STYLE == 1) || + (STRATIXGX_DPA_RX_STYLE == 1)) + ? stratix_pll_outclock[2] : + (STRATIXII_RX_STYLE == 1) + ? stratixii_pll_outclock[2] + : 1'b0; + + assign altclklock_inclock = (APEX20KE_RX_STYLE == 1) || + (APEXII_RX_STYLE == 1) || + (MERCURY_RX_STYLE == 1) + ? rx_inclock + : 1'b0; + + assign stratix_pll_inclock[1:0] = (FAMILY_HAS_STRATIX_STYLE_PLL == 1) + ? {1'b0, rx_inclock} + : {2{1'b0}}; + + assign stratix_pll_enable = (FAMILY_HAS_STRATIX_STYLE_PLL == 1) + ? rx_pll_enable + : 1'b0; + + assign stratix_pll_areset = (FAMILY_HAS_STRATIX_STYLE_PLL == 1) + ? pll_areset + : 1'b0; + + assign stratix_fastclk = (STRATIX_RX_STYLE == 1) && (implement_in_les == "OFF") + ? stratix_pll_outclock[0] + : 1'b0; + + assign stratix_slowclk = (STRATIX_RX_STYLE == 1) && (implement_in_les == "OFF") + ? stratix_pll_outclock[2] + : 1'b0; + + assign stratixgx_fastclk = (STRATIXGX_DPA_RX_STYLE == 1) && (implement_in_les == "OFF") + ? stratix_pll_outclock[0] + : 1'b0; + + assign stratixgx_slowclk = (STRATIXGX_DPA_RX_STYLE == 1) && (implement_in_les == "OFF") + ? stratix_pll_outclock[2] + : 1'b0; + + assign stratixgx_coreclk = (STRATIXGX_DPA_RX_STYLE == 1) && (implement_in_les == "OFF") + ? rx_coreclk + : {number_of_channels{1'b0}}; + + assign stratixii_pll_inclock[1:0] = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1) + ? {1'b0, rx_inclock} + : {2{1'b0}}; + + assign stratixii_pll_enable = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1) + ? rx_pll_enable + : 1'b0; + + assign stratixii_pll_areset = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1) + ? pll_areset + : 1'b0; + assign stratixii_fastclk = (STRATIXII_RX_STYLE == 0) && (implement_in_les == "OFF") + ? 1'b0 : + (use_external_pll == "ON") + ? rx_inclock + : stratixii_sclkout0; + + assign stratixii_enable = (STRATIXII_RX_STYLE == 0) && (implement_in_les == "OFF") + ? 1'b0 : + (use_external_pll == "ON") + ? rx_enable + : stratixii_enable0; + + assign flvds_fastclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIX_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? rx_inclock + : stratix_pll_outclock[0]) : + ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? rx_inclock + : stratixii_pll_outclock[0]) + : 1'b0; + + assign flvds_slowclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIX_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? 1'b0 + : stratix_pll_outclock[2]) : + ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? 1'b0 + : stratixii_pll_outclock[2]) + : 1'b0; + + assign flvds_syncclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIX_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? 1'b0 + : stratix_pll_outclock[1]) : + ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? 1'b0 + : stratixii_pll_outclock[1]) + : 1'b0; + +endmodule // altlvds_rx +// END OF MODULE + +//START_MODULE_NAME---------------------------------------------------- +// +// Module Name : stratix_lvds_rx +// +// Description : Stratix lvds receiver +// +// Limitation : Only available to Stratix and stratix GX (NON DPA mode) +// families. +// +// Results expected: Deserialized output data. +// +//END_MODULE_NAME---------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module stratix_lvds_rx ( + rx_in, // input serial data + rx_fastclk, // fast clock from pll + rx_enable0, + rx_enable1, + rx_out // deserialized output data +); + +// GLOBAL PARAMETER DECLARATION + parameter number_of_channels = 1; + parameter deserialization_factor = 4; + +// LOCAL PARAMETER DECLARATION + parameter REGISTER_WIDTH = deserialization_factor*number_of_channels; + +// INPUT PORT DECLARATION + input [number_of_channels -1 :0] rx_in; + input rx_fastclk; + input rx_enable0; + input rx_enable1; + +// OUTPUT PORT DECLARATION + output [REGISTER_WIDTH -1: 0] rx_out; + +// INTERNAL REGISTERS DECLARATION + reg [REGISTER_WIDTH -1 : 0] rx_shift_reg; + reg [REGISTER_WIDTH -1 : 0] rx_parallel_load_reg; + reg [REGISTER_WIDTH -1 : 0] rx_out_hold; + reg enable0_reg; + reg enable0_reg1; + reg enable0_neg; + reg enable1_reg; + +// INTERNAL WIRE DECLARATION + wire rx_hold_clk; + +// LOCAL INTEGER DECLARATION + integer i1; + integer x; + +// INITIAL CONSTRUCT BLOCK + initial + begin : INITIALIZATION + rx_shift_reg = {REGISTER_WIDTH{1'b0}}; + rx_parallel_load_reg = {REGISTER_WIDTH{1'b0}}; + rx_out_hold = {REGISTER_WIDTH{1'b0}}; + end //INITIALIZATION + +// ALWAYS CONSTRUCT BLOCK + + // registering load enable signal + always @ (posedge rx_fastclk) + begin : LOAD_ENABLE + enable0_reg1 <= enable0_reg; + enable0_reg <= rx_enable0; + enable1_reg <= rx_enable1; + end // LOAD_ENABLE + + // Fast clock (on falling edge) + always @ (negedge rx_fastclk) + begin : NEGEDGE_FAST_CLOCK + + // load data when the registered load enable signal is high + if (enable0_neg == 1) + rx_parallel_load_reg <= rx_shift_reg; + + // Loading input data to shift register + for (i1= 0; i1 < number_of_channels; i1 = i1+1) + begin + for (x=deserialization_factor-1; x >0; x=x-1) + rx_shift_reg[x + (i1 * deserialization_factor)] <= rx_shift_reg [x-1 + (i1 * deserialization_factor)]; + rx_shift_reg[i1 * deserialization_factor] <= rx_in[i1]; + end + + enable0_neg <= enable0_reg1; + + end // NEGEDGE_FAST_CLOCK + + // Holding register + always @ (posedge rx_hold_clk) + begin : HOLD_REGISTER + rx_out_hold <= rx_parallel_load_reg; + end // HOLD_REGISTER + +// CONTINOUS ASSIGNMENT + assign rx_out = rx_out_hold; + assign rx_hold_clk = enable1_reg; + + +endmodule // stratix_lvds_rx +// END OF MODULE + +//START_MODULE_NAME---------------------------------------------------- +// +// Module Name : stratixgx_dpa_lvds_rx +// +// Description : Stratix GX lvds receiver. +// +// Limitation : Only available in Stratix GX families. +// +// Results expected: Deserialized output data and dpa locked signal. +// +//END_MODULE_NAME---------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module stratixgx_dpa_lvds_rx ( + rx_in, + rx_fastclk, + rx_slowclk, + rx_locked, + rx_coreclk, + rx_reset, + rx_dpll_reset, + rx_channel_data_align, + rx_out, + rx_dpa_locked +); + +// GLOBAL PARAMETER DECLARATION + parameter number_of_channels = 1; + parameter deserialization_factor = 4; + parameter use_coreclock_input = "OFF"; + parameter enable_dpa_fifo = "ON"; + parameter registered_output = "ON"; + +// LOCAL PARAMETER DECLARATION + parameter REGISTER_WIDTH = deserialization_factor*number_of_channels; + +// INPUT PORT DECLARATION + input [number_of_channels -1 :0] rx_in; + input rx_fastclk; + input rx_slowclk; + input rx_locked; + input [number_of_channels -1 :0] rx_coreclk; + input [number_of_channels -1 :0] rx_reset; + input [number_of_channels -1 :0] rx_dpll_reset; + input [number_of_channels -1 :0] rx_channel_data_align; + +// OUTPUT PORT DECLARATION + output [REGISTER_WIDTH -1: 0] rx_out; + output [number_of_channels -1: 0] rx_dpa_locked; + +// INTERNAL REGISTERS DECLARATION + + reg [REGISTER_WIDTH -1 : 0] rx_shift_reg; + reg [REGISTER_WIDTH -1 : 0] rx_parallel_load_reg; + reg [number_of_channels -1 : 0] rx_in_reg; + reg [number_of_channels -1 : 0] dpa_in; + reg [number_of_channels -1 : 0] retime_data; + + reg [REGISTER_WIDTH -1 : 0] ram_array0; + reg [REGISTER_WIDTH -1 : 0] ram_array1; + reg [REGISTER_WIDTH -1 : 0] ram_array2; + reg [REGISTER_WIDTH -1 : 0] ram_array3; + reg [2 : 0] wrPtr [number_of_channels -1 : 0]; + reg [2 : 0] rdPtr [number_of_channels -1 : 0]; + reg [3 : 0] bitslip_count [number_of_channels -1 : 0]; + reg [3 : 0] bitslip_count_pre [number_of_channels -1 : 0]; + + reg [REGISTER_WIDTH -1 : 0] rxpdat2; + reg [REGISTER_WIDTH -1 : 0] rxpdat3; + reg [REGISTER_WIDTH -1 : 0] rxpdatout; + reg [REGISTER_WIDTH -1 : 0] fifo_data_out; + reg [REGISTER_WIDTH -1 : 0] rx_out_reg; + reg [number_of_channels -1 : 0] dpagclk_pre; + reg [number_of_channels -1 : 0] rx_channel_data_align_pre; + reg [number_of_channels -1 : 0] fifo_write_clk_pre; + reg [number_of_channels -1 : 0] clkout_tmp; + reg [number_of_channels -1 : 0] sync_reset; + +// INTERNAL WIRE DECLARATION + wire [number_of_channels -1:0] dpagclk; + wire[number_of_channels -1:0] fifo_write_clk; + wire [REGISTER_WIDTH -1 : 0] rx_out_int; + wire [REGISTER_WIDTH -1 : 0] serdes_data_out; + wire [REGISTER_WIDTH -1 : 0] fifo_data_in; + wire [REGISTER_WIDTH -1 : 0] rxpdat1; + +// INTERNAL TRI DECLARATION + tri0[number_of_channels -1 :0] rx_reset; + tri0[number_of_channels -1 :0] rx_dpll_reset; + tri0[number_of_channels -1 :0] rx_channel_data_align; + tri0[number_of_channels -1 :0] rx_coreclk; + +// LOCAL INTEGER DECLARATION + integer i; + integer i0; + integer i1; + integer i2; + integer i3; + integer i4; + integer i5; + integer i6; + integer i7; + integer i8; + integer j; + integer j1; + integer j2; + integer j3; + integer k; + integer x; + integer negedge_count; + + integer fastclk_posedge_count [number_of_channels -1: 0]; + integer fastclk_negedge_count [number_of_channels - 1 : 0]; + integer bitslip_count_reg [number_of_channels -1: 0]; + + +// COMPONENT INSTANTIATIONS +// ALTERA_DEVICE_FAMILIES dev (); + +// INITIAL CONSTRUCT BLOCK + initial + begin : INITIALIZATION + rxpdat2 = {REGISTER_WIDTH{1'b0}}; + rxpdat3 = {REGISTER_WIDTH{1'b0}}; + rxpdatout = {REGISTER_WIDTH{1'b0}}; + rx_out_reg = {REGISTER_WIDTH{1'b0}}; + + ram_array0 = {REGISTER_WIDTH{1'b0}}; + ram_array1 = {REGISTER_WIDTH{1'b0}}; + ram_array2 = {REGISTER_WIDTH{1'b0}}; + ram_array3 = {REGISTER_WIDTH{1'b0}}; + + rx_in_reg = {number_of_channels{1'b0}}; + dpa_in = {number_of_channels{1'b0}}; + retime_data = {number_of_channels{1'b0}}; + + rx_channel_data_align_pre = {number_of_channels{1'b0}}; + clkout_tmp = {number_of_channels{1'b0}}; + sync_reset = {number_of_channels{1'b0}}; + + rx_shift_reg = {REGISTER_WIDTH{1'b0}}; + rx_parallel_load_reg = {REGISTER_WIDTH{1'b0}}; + fifo_data_out = {REGISTER_WIDTH{1'b0}}; + + for (i = 0; i < number_of_channels; i = i + 1) + begin + wrPtr[i] = 0; + rdPtr[i] = 2; + bitslip_count[i] = 0; + bitslip_count_reg[i] = 0; + fastclk_posedge_count[i] = 0; + fastclk_negedge_count[i] = 0; + end + + end //INITIALIZATION + + +// ALWAYS CONSTRUCT BLOCK + + //deserializer logic + always @ (posedge dpagclk) + begin : DPA_SERDES_SLOWCLK + + for(i0 = 0; i0 <=number_of_channels -1; i0=i0+1) + begin + if ((dpagclk[i0] == 1'b1) && (dpagclk_pre[i0] == 1'b0)) + begin + + if ((rx_reset[i0] == 1'b1) || (rx_dpll_reset[i0] == 1'b1)) + sync_reset[i0] <= 1'b1; + else + sync_reset[i0] <= 1'b0; + + // add 1 ps delay to ensure that when the rising edge of + // global clock(core clock) happens at the same time of falling + // edge of fast clock, the count for the next falling edge of + // fast clock is start at 1. + fastclk_negedge_count[i0] <= #1 0; + end + end + end // DPA_SERDES_SLOW_CLOCK + + + always @ (posedge rx_fastclk) + begin : DPA_SERDES_POSEDGE_FASTCLK + for(i1 = 0; i1 <=number_of_channels -1; i1=i1+1) + begin + if (fastclk_negedge_count[i1] == 2) + rx_parallel_load_reg <= rx_shift_reg; + + if (sync_reset[i1] == 1'b1) + begin + fastclk_posedge_count[i1] <= 0; + clkout_tmp[i1] <= 1'b0; + end + else + begin + if (fastclk_posedge_count[i1] % (deserialization_factor / 2) == 0) + begin + fastclk_posedge_count[i1] <= 1; + clkout_tmp[i1] <= !clkout_tmp[i1]; + end + + fastclk_posedge_count[i1] <= (fastclk_posedge_count[i1] + 1) % deserialization_factor; + end + end + end // DPA_SERDES_POSEDGE_FAST_CLOCK + + always @ (negedge rx_fastclk) + begin : DPA_SERDES_NEGEDGE_FAST_CLOCK + if (rx_fastclk == 1'b0) + begin + for (i2 = 0; i2 <= number_of_channels -1; i2 = i2+1) + begin + // Data gets shifted into MSB first. + for (x=deserialization_factor-1; x > 0; x=x-1) + rx_shift_reg[x + (i2 * deserialization_factor)] <= rx_shift_reg [x-1 + (i2 * deserialization_factor)]; + + rx_shift_reg[i2 * deserialization_factor] <= retime_data[i2]; + retime_data <= rx_in; + + fastclk_negedge_count[i2] <= (fastclk_negedge_count[i2] + 1) ; + end + end + end // DPA_SERDES_NEGEDGE_FAST_CLOCK + + //phase compensation FIFO + always @ (posedge fifo_write_clk) + begin : DPA_FIFO_WRITE_CLOCK + if ((enable_dpa_fifo == "ON") && (rx_locked == 1'b1)) + begin + for (i3 = 0; i3 <= number_of_channels-1; i3 = i3+1) + begin + if(sync_reset[i3] == 1'b1) + wrPtr[i3] <= 0; + else if ((fifo_write_clk[i3] == 1'b1) && (fifo_write_clk_pre[i3] == 1'b0)) + begin + case (wrPtr[i3]) + 3'b000: + for (j = i3*deserialization_factor; j <= (i3+1)*deserialization_factor -1; j=j+1) + ram_array0[j] <= fifo_data_in[j]; + + 3'b001: + for (j = i3*deserialization_factor; j <= (i3+1)*deserialization_factor -1; j=j+1) + ram_array1[j] <= fifo_data_in[j]; + 3'b010: + for (j = i3*deserialization_factor; j <= (i3+1)*deserialization_factor -1; j=j+1) + ram_array2[j] <= fifo_data_in[j]; + 3'b011: + for (j = i3*deserialization_factor; j <= (i3+1)*deserialization_factor -1; j=j+1) + ram_array3[j] <= fifo_data_in[j]; + default: + $display ("Error! Invalid wrPtr value."); + endcase + wrPtr[i3] <= (wrPtr[i3] + 1) % 4; + end + end + end + end // DPA_FIFO_WRITE_CLOCK + + always @ (negedge fifo_write_clk) + begin + for (i6 = 0; i6 <= number_of_channels-1; i6 = i6+1) + begin + if (fifo_write_clk[i6] == 1'b0) + fifo_write_clk_pre[i6] <= fifo_write_clk[i6]; + end + end + + always @ (posedge dpagclk) + begin : DPA_FIFO_SLOW_CLOCK + + if((enable_dpa_fifo == "ON") ) + begin + for (i4 = 0; i4 <= number_of_channels-1; i4 = i4+1) + begin + if ((dpagclk[i4] == 1'b1) && (dpagclk_pre[i4] == 1'b0)) + begin + if ((rx_reset[i4] == 1'b1) || (rx_dpll_reset[i4] == 1'b1) || (sync_reset[i4] == 1'b1)) + begin + for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1) + begin + fifo_data_out[j1] <= 1'b0; + ram_array0[j1] <= 1'b0; + ram_array1[j1] <= 1'b0; + ram_array2[j1] <= 1'b0; + ram_array3[j1] <= 1'b0; + end + + wrPtr[i4] <= 0; + rdPtr[i4] <= 2; + end + else + begin + case (rdPtr[i4]) + 3'b000: + for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1) + fifo_data_out[j1] <= ram_array0[j1]; + 3'b001: + for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1) + fifo_data_out[j1] <= ram_array1[j1]; + 3'b010: + for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1) + fifo_data_out[j1] <= ram_array2[j1]; + 3'b011: + for (j1 = i4*deserialization_factor; j1 <= (i4+1)*deserialization_factor -1; j1=j1+1) + fifo_data_out[j1] <= ram_array3[j1]; + default: + $display ("Error! Invalid rdPtr value."); + endcase + + rdPtr[i4] <= (rdPtr[i4] + 1) % 4; + end + end + end + end + end // DPA_FIFO_SLOW_CLOCK + + + //bit-slipping logic + always @ (posedge dpagclk) + begin : DPA_BIT_SLIP + + for (i5 = 0; i5 <= number_of_channels-1; i5 = i5 + 1) + begin + if ((dpagclk[i5] == 1'b1) && (dpagclk_pre[i5] == 1'b0)) + begin + if ((sync_reset[i5] == 1'b1) || (rx_reset[i5] == 1'b1) || + (rx_dpll_reset[i5] == 1'b1)) + begin + for(j2 = deserialization_factor*i5; j2 <= deserialization_factor*(i5+1) -1; j2=j2+1) + begin + rxpdat2[j2] <= 1'b0; + rxpdat3[j2] <= 1'b0; + rxpdatout[j2] <= 1'b0; + end + bitslip_count[i5] <= 0; + bitslip_count_reg[i5] <= 0; + end + else + begin + if ((rx_channel_data_align[i5] == 1'b1) && (rx_channel_data_align_pre[i5] == 1'b0)) + bitslip_count[i5] <= (bitslip_count[i5] + 1) % deserialization_factor; + + bitslip_count_reg[i5] <= bitslip_count[i5]; + + rxpdat2 <= rxpdat1; + rxpdat3 <= rxpdat2; + + for(j2 = deserialization_factor*i5 + bitslip_count_reg[i5]; j2 <= deserialization_factor*(i5+1) -1; j2=j2+1) + rxpdatout[j2] <= rxpdat3[j2-bitslip_count_reg[i5]]; + + for(j2 = deserialization_factor*i5 ; j2 <= deserialization_factor*i5 + bitslip_count_reg[i5] -1; j2=j2+1) + rxpdatout[j2] <= rxpdat2[j2+ deserialization_factor -bitslip_count_reg[i5]]; + end + rx_channel_data_align_pre[i5] <= rx_channel_data_align[i5]; + end + end + end // DPA_BIT_SLIP + + // synchronization register + always @ (posedge dpagclk) + begin : SYNC_REGISTER + for (i8 = 0; i8 < number_of_channels; i8 = i8+1) + begin + if ((dpagclk[i8] == 1'b1) && (dpagclk_pre[i8] == 1'b0)) + begin + for (j3 = 0; j3 < deserialization_factor; j3 = j3+1) + rx_out_reg[i8*deserialization_factor + j3] <= rxpdatout[i8*deserialization_factor + j3]; + end + end + end // SYNC_REGISTER + + // store previous value of the global clocks + always @ (dpagclk) + begin + dpagclk_pre <= dpagclk; + end + + // CONTINOUS ASSIGNMENT + assign dpagclk = (use_coreclock_input == "ON") ? rx_coreclk : {number_of_channels{rx_slowclk}}; + assign rxpdat1 = (enable_dpa_fifo == "ON") ? fifo_data_out : serdes_data_out; + assign serdes_data_out = rx_parallel_load_reg; + assign fifo_data_in = serdes_data_out; + assign fifo_write_clk = clkout_tmp; + assign rx_dpa_locked = {number_of_channels {1'b1}}; + assign rx_out = (registered_output == "ON") ? rx_out_reg : rxpdatout; + + +endmodule // stratixgx_dpa_lvds_rx +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------- +// +// Module Name : stratixii_lvds_rx +// +// Description : Stratix II lvds receiver. Support both the dpa and non-dpa +// mode. +// +// Limitation : Only available to Stratix II. +// +// Results expected: Deserialized output data, dpa lock signal and status bit +// indicating whether maximum bitslip has been reached. +// +//END_MODULE_NAME--------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module stratixii_lvds_rx ( + rx_in, + rx_reset, + rx_fastclk, + rx_enable, + rx_locked, + rx_dpll_reset, + rx_dpll_hold, + rx_dpll_enable, + rx_fifo_reset, + rx_channel_data_align, + rx_cda_reset, + rx_out, + rx_dpa_locked, + rx_cda_max +); + +// GLOBAL PARAMETER DECLARATION + parameter number_of_channels = 1; + parameter deserialization_factor = 4; + parameter enable_dpa_mode = "OFF"; + parameter data_align_rollover = deserialization_factor; + parameter lose_lock_on_one_change = "OFF"; + parameter reset_fifo_at_first_lock = "ON"; + +// LOCAL PARAMETER DECLARATION + parameter REGISTER_WIDTH = deserialization_factor*number_of_channels; + parameter MUX_WIDTH = 12; + parameter RAM_WIDTH = 6; + +// INPUT PORT DECLARATION + input [number_of_channels -1 :0] rx_in; + input rx_fastclk; + input rx_enable; + input rx_locked; + input [number_of_channels -1 :0] rx_reset; + input [number_of_channels -1 :0] rx_dpll_reset; + input [number_of_channels -1 :0] rx_dpll_hold; + input [number_of_channels -1 :0] rx_dpll_enable; + input [number_of_channels -1 :0] rx_fifo_reset; + input [number_of_channels -1 :0] rx_channel_data_align; + input [number_of_channels -1 :0] rx_cda_reset; + +// OUTPUT PORT DECLARATION + output [REGISTER_WIDTH -1: 0] rx_out; + output [number_of_channels -1: 0] rx_dpa_locked; + output [number_of_channels -1: 0] rx_cda_max; + + +// INTERNAL REGISTERS DECLARATION + + reg [REGISTER_WIDTH -1 : 0] rx_shift_reg; + reg [REGISTER_WIDTH -1 : 0] rx_parallel_load_reg; + reg [number_of_channels -1 : 0] rx_in_reg; + reg [number_of_channels -1 : 0] fifo_in_sync_reg; + reg [number_of_channels -1 : 0] fifo_out_sync_reg; + reg [number_of_channels -1 : 0] bitslip_mux_out; + reg [number_of_channels -1 : 0] dpa_in; + reg [number_of_channels -1 : 0] retime_data; + reg [number_of_channels -1 : 0] dpll_lock; + reg [number_of_channels -1 : 0] dpll_first_lock; + reg [number_of_channels -1 : 0] rx_channel_data_align_pre; + reg [number_of_channels -1 : 0] write_side_sync_reset; + reg [number_of_channels -1 : 0] read_side_sync_reset; + + reg ram_array [(RAM_WIDTH*number_of_channels) -1 : 0]; + reg [2 : 0] wrPtr [number_of_channels -1 : 0]; + reg [2 : 0] rdPtr [number_of_channels -1 : 0]; + reg [3 : 0] bitslip_count [number_of_channels -1 : 0]; + reg [number_of_channels -1 : 0] start_corrupt_bits; + reg [1 : 0] num_corrupt_bits [number_of_channels -1 : 0]; + reg [number_of_channels -1 : 0] rx_cda_max; + reg [(MUX_WIDTH*number_of_channels) -1 : 0] shift_reg_chain; + reg enable0_reg; + +// INTERNAL WIRE DECLARATION + wire fifo_write_clk; + wire fifo_read_clk; + wire [number_of_channels -1 : 0] dpa_fifo_in; + wire [number_of_channels -1 : 0] dpa_fifo_out; + wire rx_in_reg_clk; + wire rx_bload; + +// INTERNAL TRI DECLARATION + tri0[number_of_channels -1 :0] rx_reset; + tri0[number_of_channels -1 :0] rx_dpll_reset; + tri0[number_of_channels -1 :0] rx_dpll_hold; + tri1[number_of_channels -1 :0] rx_dpll_enable; + tri0[number_of_channels -1 :0] rx_fifo_reset; + tri0[number_of_channels -1 :0] rx_channel_data_align; + tri0[number_of_channels -1 :0] rx_cda_reset; + +// LOCAL INTEGER DECLARATION + integer i; + integer i1; + integer i2; + integer i3; + integer i4; + integer i5; + integer i6; + integer i7; + integer i8; + integer j; + integer j1; + integer j2; + integer j3; + integer j4; + integer x; + integer dpll_clk_count[number_of_channels -1: 0]; + +// INITIAL CONSTRUCT BLOCK + initial + begin : INITIALIZATION + enable0_reg=0; + + for (i = 0; i < number_of_channels; i = i + 1) + begin + rx_in_reg[i] = 1'b0; + rx_cda_max[i] = 1'b0; + fifo_in_sync_reg[i] = 1'b0; + fifo_out_sync_reg[i] = 1'b0; + bitslip_mux_out[i] = 1'b0; + dpa_in[i] = 1'b0; + retime_data[i] = 1'b0; + wrPtr[i] = 0; + rdPtr[i] = 3; + bitslip_count[i] = 0; + dpll_clk_count[i] = 0; + dpll_lock[i] = 1'b0; + dpll_first_lock[i] = 1'b0; + start_corrupt_bits[i] = 0; + num_corrupt_bits[i] = 0; + + for (j = 0; j < RAM_WIDTH; j = j + 1) + ram_array[(i*RAM_WIDTH) + j] = 1'b0; + + for (j = 0; j < MUX_WIDTH; j = j + 1) + shift_reg_chain[(i*MUX_WIDTH) + j] = 1'b0; + end + + for (i = 0; i < REGISTER_WIDTH; i = i + 1) + begin + rx_shift_reg[i] = 0; + rx_parallel_load_reg[i] = 0; + end + + + end //INITIALIZATION + +// ALWAYS CONSTRUCT BLOCK + + // Fast clock (on rising edge) + always @ (posedge rx_fastclk) + begin : STRATIXII_DESER + if (rx_bload == 1) + rx_parallel_load_reg <= rx_shift_reg; + + for (i1 = 0; i1 < number_of_channels; i1 = i1+1) + begin + for (x=deserialization_factor-1; x >0; x=x-1) + rx_shift_reg[x + (i1 * deserialization_factor)] <= rx_shift_reg [x-1 + (i1 * deserialization_factor)]; + + rx_shift_reg[i1 * deserialization_factor] <= bitslip_mux_out[i1]; + end + + // Registering enable0 signal + enable0_reg <= rx_enable; + end // STRATIXII_DESER + + // input synchronization register + always @ (posedge rx_in_reg_clk) + begin : IN_SYNC_REGISTER + rx_in_reg <= rx_in; + end // IN_SYNC_REGISTER + + // Stratix II bitslip logic + always @ (posedge rx_cda_reset) + begin + for (i2 = 0; i2 <= number_of_channels-1; i2 = i2 + 1) + begin + if (rx_cda_reset[i2] == 1'b1) + begin + // reset the bitslipping circuitry. + bitslip_count[i2] <= 0; + rx_cda_max[i2] <= 1'b0; + end + end + end + + always @ (posedge rx_fastclk) + begin : STRATIXII_BITSLIP + for (i3 = 0; i3 <= number_of_channels-1; i3 = i3 + 1) + begin + if (rx_cda_reset[i3] !== 1'b1) + begin + if ((rx_channel_data_align[i3] === 1'b1) && + (rx_channel_data_align_pre[i3] === 1'b0)) + begin + // slipped data byte is corrupted. + start_corrupt_bits[i3] <= 1; + num_corrupt_bits[i3] <= 1; + + // Rollover has occurred. Serial data stream is reset back to 0 latency. + if (bitslip_count[i3] == data_align_rollover) + begin + bitslip_count[i3] <= 0; + rx_cda_max[i3] <= 1'b0; + end + else + begin + // increase the bit slip count. + bitslip_count[i3] <= bitslip_count[i3] + 1; + + // if maximum of bitslip limit has been reach, set rx_cda_max to high. + // Rollover will occur on the next bit slip. + if (bitslip_count[i3] == data_align_rollover - 1) + rx_cda_max[i3] <= 1'b1; + end + end + else if ((rx_channel_data_align[i3] === 1'b0) && + (rx_channel_data_align_pre[i3] === 1'b1)) + begin + start_corrupt_bits[i3] <= 0; + num_corrupt_bits[i3] <= 0; + end + end + + if (start_corrupt_bits[i3] == 1'b1) + begin + if (num_corrupt_bits[i3]+1 == 3) + start_corrupt_bits[i3] <= 0; + else + num_corrupt_bits[i3] <= num_corrupt_bits[i3] + 1; + end + + // load serial data stream into the shift register chain. + if ((enable_dpa_mode == "ON") && (rx_dpll_enable[i3] == 1'b1)) + shift_reg_chain[(i3*MUX_WIDTH) + 0] <= dpa_fifo_out[i3]; + else + shift_reg_chain[(i3*MUX_WIDTH) + 0] <= rx_in_reg[i3]; + + // propagate the serial data stream through the bitslip register chain. + for (j1 = 0; j1 < data_align_rollover; j1 = j1 + 1) + shift_reg_chain[(i3*MUX_WIDTH) + j1 + 1] <= shift_reg_chain[(i3*MUX_WIDTH) + j1]; + + // set the output to 'X' for 3 fast clock cycles after receiving the bitslip signal. + if (((rx_channel_data_align[i3] === 1'b1) && (rx_channel_data_align_pre[i3] === 1'b0)) || + ((start_corrupt_bits[i3] == 1'b1) && (num_corrupt_bits[i3] < 3) && + (rx_channel_data_align[i3] === 1'b1))) + bitslip_mux_out[i3] <= 1'bx; + else + bitslip_mux_out[i3] <= shift_reg_chain[(i3*MUX_WIDTH) + bitslip_count[i3]]; + + rx_channel_data_align_pre[i3] <= rx_channel_data_align[i3]; + end + end //STRATIXII_BITSLIP + + // Stratix II Phase Compensation FIFO + always @ (posedge fifo_write_clk or posedge rx_reset or posedge rx_fifo_reset) + begin : STRATIXII_DPA_FIFO_WRITE + for (i4 = 0; i4 <= number_of_channels-1; i4 = i4 + 1) + begin + if ((rx_reset[i4] == 1'b1) || (rx_fifo_reset[i4] == 1'b1) || + ((reset_fifo_at_first_lock == "ON") && + (dpll_first_lock[i4] == 1'b0))) + begin + wrPtr[i4] <= 0; + for (j2 = 0; j2 < RAM_WIDTH; j2 = j2 + 1) + ram_array[(i4*RAM_WIDTH) + j2] <= 1'b0; + fifo_in_sync_reg[i4] <= 1'b0; + write_side_sync_reset[i4] <= 1'b1; + end + else + begin + if (write_side_sync_reset[i4] <= 1'b0) + begin + wrPtr[i4] <= wrPtr[i4] + 1; + fifo_in_sync_reg[i4] <= dpa_fifo_in[i4]; + ram_array[(i4*RAM_WIDTH) + wrPtr[i4]] <= fifo_in_sync_reg[i4]; + if (wrPtr[i4] == 5) + wrPtr[i4] <= 0; + end + write_side_sync_reset[i4] <= 1'b0; + end + end + end //STRATIXII_DPA_FIFO_WRITE + + // Stratix II Phase Compensation FIFO + always @ (posedge fifo_read_clk or posedge rx_reset or posedge rx_fifo_reset) + begin : STRATIXII_DPA_FIFO_READ + for (i5 = 0; i5 <= number_of_channels-1; i5 = i5 + 1) + begin + if ((rx_reset[i5] == 1'b1) || (rx_fifo_reset[i5] == 1'b1) || + ((reset_fifo_at_first_lock == "ON") && + (dpll_first_lock[i5] == 1'b0))) + begin + rdPtr[i5] <= 3; + fifo_out_sync_reg[i5] <= 1'b0; + read_side_sync_reset[i5] <= 1'b1; + end + else + begin + if (read_side_sync_reset[i5] == 1'b0) + begin + rdPtr[i5] <= rdPtr[i5] + 1; + fifo_out_sync_reg[i5] <= ram_array[(i5*RAM_WIDTH) + rdPtr[i5]]; + if (rdPtr[i5] == 5) + rdPtr[i5] <= 0; + end + read_side_sync_reset[i5] <= 1'b0; + end + end + end //STRATIXII_DPA_FIFO_READ + + // Stratix II DPA Block + always @ (posedge rx_fastclk or posedge rx_reset) + begin : STRATIXII_DPA_BLOCK + for (i6 = 0; i6 <= number_of_channels-1; i6 = i6 + 1) + begin + if (rx_reset[i6] == 1'b1) + begin + dpll_clk_count[i6] <= 0; + dpll_lock[i6] <= 1'b0; + end + else + begin + dpll_clk_count[i6] <= dpll_clk_count[i6] + 1; + + if (dpll_clk_count[i6] == 2) + begin + dpll_lock[i6] <= 1'b1; + dpll_first_lock[i6] <= 1'b1; + end + end + end + end //STRATIXII_DPA_BLOCK + + always @ (posedge rx_fastclk) + begin + dpa_in <= rx_in; + retime_data <= dpa_in; + end + + + // CONTINOUS ASSIGNMENT + assign rx_out = rx_parallel_load_reg; + assign dpa_fifo_in = retime_data; + assign dpa_fifo_out = fifo_out_sync_reg; + assign fifo_write_clk = rx_fastclk; + assign fifo_read_clk = rx_fastclk; + assign rx_in_reg_clk = rx_fastclk; + assign rx_dpa_locked = dpll_lock; + assign rx_bload = enable0_reg; + +endmodule // stratixii_lvds_rx +// END OF MODULE + +//START_MODULE_NAME---------------------------------------------------- +// +// Module Name : flexible_lvds_rx +// +// Description : flexible lvds receiver +// +// Limitation : Only available to Cyclone and Cyclone II +// families. +// +// Results expected: Deserialized output data. +// +//END_MODULE_NAME---------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module flexible_lvds_rx ( + rx_in, // input serial data + rx_fastclk, // fast clock from PLL + rx_slowclk, // slow clock from PLL + rx_syncclk, // sync clock from PLL + rx_locked, // lock signal from PLL + rx_out // deserialized output data +); + +// GLOBAL PARAMETER DECLARATION + parameter number_of_channels = 1; + parameter deserialization_factor = 4; + parameter use_extra_ddio_register = "YES"; + parameter use_extra_pll_clk = "NO"; + +// LOCAL PARAMETER DECLARATION + parameter REGISTER_WIDTH = deserialization_factor*number_of_channels; + +// INPUT PORT DECLARATION + input [number_of_channels -1 :0] rx_in; + input rx_fastclk; + input rx_slowclk; + input rx_syncclk; + input rx_locked; + +// OUTPUT PORT DECLARATION + output [REGISTER_WIDTH -1: 0] rx_out; + +// INTERNAL REGISTERS DECLARATION + reg [REGISTER_WIDTH -1 : 0] rx_shift_reg; + reg [REGISTER_WIDTH -1 : 0] rx_shift_reg1; + reg [REGISTER_WIDTH -1 : 0] rx_shift_reg2; + reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1; + reg [REGISTER_WIDTH -1 : 0] rx_sync_reg2; + reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1_buf1; + reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1_buf1_pipe; + reg [REGISTER_WIDTH -1 : 0] rx_sync_reg2_buf1; + reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1_buf2; + reg [REGISTER_WIDTH -1 : 0] rx_sync_reg1_buf2_pipe; + reg [REGISTER_WIDTH -1 : 0] rx_sync_reg2_buf2; + reg [REGISTER_WIDTH -1 : 0] rx_out_odd; + reg [REGISTER_WIDTH -1 : 0] rx_out_odd_mode; + reg [number_of_channels -1 :0] ddio_h_reg; + reg [number_of_channels -1 :0] ddio_l_reg; + reg [number_of_channels -1 :0] datain_h_reg; + reg [number_of_channels -1 :0] datain_l_reg; + reg [number_of_channels -1 :0] datain_l_latch; + reg select_bit; + reg sync_clock; + +// INTERNAL WIRE DECLARATION + wire [REGISTER_WIDTH -1 : 0] rx_out; + +// LOCAL INTEGER DECLARATION + integer i; + integer x; + +// INITIAL CONSTRUCT BLOCK + initial + begin : INITIALIZATION + + rx_shift_reg = {REGISTER_WIDTH{1'b0}}; + rx_shift_reg1 = {REGISTER_WIDTH{1'b0}}; + rx_shift_reg2 = {REGISTER_WIDTH{1'b0}}; + rx_sync_reg1 = {REGISTER_WIDTH{1'b0}}; + rx_sync_reg2 = {REGISTER_WIDTH{1'b0}}; + rx_sync_reg1_buf1 = {REGISTER_WIDTH{1'b0}}; + rx_sync_reg1_buf1_pipe = {REGISTER_WIDTH{1'b0}}; + rx_sync_reg2_buf1 = {REGISTER_WIDTH{1'b0}}; + rx_sync_reg1_buf2 = {REGISTER_WIDTH{1'b0}}; + rx_sync_reg1_buf2_pipe = {REGISTER_WIDTH{1'b0}}; + rx_sync_reg2_buf2 = {REGISTER_WIDTH{1'b0}}; + rx_out_odd = {REGISTER_WIDTH{1'b0}}; + rx_out_odd_mode = {REGISTER_WIDTH{1'b0}}; + ddio_h_reg = {number_of_channels{1'b0}}; + ddio_l_reg = {number_of_channels{1'b0}}; + datain_h_reg = {number_of_channels{1'b0}}; + datain_l_reg = {number_of_channels{1'b0}}; + datain_l_latch = {number_of_channels{1'b0}}; + + select_bit = 1'b0; + sync_clock = 1'b0; + end //INITIALIZATION + + +// ALWAYS CONSTRUCT BLOCK + + // This always block implements the altddio_in that takes in the input serial + // data of each channel and deserialized it into two parallel data stream + // (ddio_h_reg and ddio_l_reg). Each parallel data stream will be registered + // before send to shift registers. + always @(posedge rx_fastclk) + begin : DDIO_IN + if (use_extra_ddio_register == "YES") + begin + ddio_h_reg <= rx_in; + datain_h_reg <= ddio_h_reg; + end + else + datain_h_reg <= rx_in; + + datain_l_reg <= datain_l_latch; + end // DDIO_IN + + always @(negedge rx_fastclk) + begin : DDIO_IN_LATCH + if (use_extra_ddio_register == "YES") + begin + ddio_l_reg <= rx_in; + datain_l_latch <= ddio_l_reg; + end + else + datain_l_latch <= rx_in; + end // DDIO_IN_LATCH + + // Loading input data to shift register + always @ (posedge rx_fastclk) + begin : SHIFTREG + + // Implementation for even deserialization factor. + if ((deserialization_factor % 2) == 0) + begin + for (i= 0; i < number_of_channels; i = i+1) + begin + for (x=deserialization_factor-1; x >1; x=x-1) + rx_shift_reg[x + (i * deserialization_factor)] <= + rx_shift_reg [x-2 + (i * deserialization_factor)]; + + rx_shift_reg[i * deserialization_factor] <= datain_h_reg[i]; + rx_shift_reg[(i * deserialization_factor)+1] <= datain_l_reg[i]; + end + end + else // Implementation for odd deserialization factor. + begin + for (i= 0; i < number_of_channels; i = i+1) + begin + for (x=deserialization_factor-1; x >1; x=x-1) + begin + rx_shift_reg1[x + (i * deserialization_factor)] <= + rx_shift_reg1[x-2 + (i * deserialization_factor)]; + + rx_shift_reg2[x + (i * deserialization_factor)] <= + rx_shift_reg2[x-2 + (i * deserialization_factor)]; + end + rx_shift_reg1[i * deserialization_factor] <= datain_h_reg[i]; + rx_shift_reg1[(i * deserialization_factor)+1] <= datain_l_reg[i]; + rx_shift_reg2[i * deserialization_factor] <= rx_shift_reg1[((i+1)* deserialization_factor)-2]; + rx_shift_reg2[(i * deserialization_factor)+1] <= rx_shift_reg1[((i+1)* deserialization_factor)-1]; + end + end + end // SHIFTREG + + always @ (posedge rx_slowclk) + begin : BIT_SELECT + rx_sync_reg1 <= rx_shift_reg1; + rx_sync_reg2 <= rx_shift_reg2; + rx_sync_reg1_buf2_pipe <= rx_sync_reg1_buf2; + + if (rx_locked == 1'b1) + begin + sync_clock <= ~sync_clock; + select_bit <= ~select_bit; + end + + if(use_extra_pll_clk == "NO") + begin + if (select_bit) + rx_out_odd_mode <= rx_sync_reg1_buf1_pipe; + else + rx_out_odd_mode <= rx_sync_reg2_buf1; + end + else + begin + if (select_bit) + rx_out_odd_mode <= rx_sync_reg1_buf2_pipe; + else + rx_out_odd_mode <= rx_sync_reg2_buf2; + end + + rx_out_odd <= rx_out_odd_mode; + end // BIT_SELECT + + always @ (posedge sync_clock) + begin : SYNC_REG + rx_sync_reg1_buf1 <= rx_sync_reg1; + rx_sync_reg2_buf1 <= rx_sync_reg2; + rx_sync_reg1_buf1_pipe <= rx_sync_reg1_buf1; + end // SYNC_REG + + always @ (posedge rx_syncclk) + begin : SYNC_REG2 + rx_sync_reg1_buf2 <= rx_sync_reg1; + rx_sync_reg2_buf2 <= rx_sync_reg2; + end // SYNC_REG2 + +// CONTINOUS ASSIGNMENT + assign rx_out = ((deserialization_factor % 2) == 0) ? rx_shift_reg : + rx_out_odd; +endmodule // flexible_lvds_rx +// END OF MODULE + + +//START_MODULE_NAME-------------------------------------------------------------- +// +// Module Name : altlvds_tx + +// Description : Low Voltage Differential Signaling (LVDS) transmitter +// megafunction. The altlvds_tx megafunction implements a +// serialization transmitter. LVDS is a high speed IO +// interface that uses inputs without a reference voltage. +// LVDS uses two wires carrying differential values to +// create a single channel. These wires are connected to two +// pins on supported device to create a single LVDS channel + +// Limitation : Only available for APEX20KE, APEXII, MERCURY, STRATIX, +// STRATIX GX, STRATIX II, CYCLONE and CYCLONEII families. +// +// Results expected: Output clock, serialized output data and pll locked signal. +// +//END_MODULE_NAME---------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +module altlvds_tx ( + tx_in, + tx_inclock, + tx_enable, + sync_inclock, + tx_pll_enable, + pll_areset, + + tx_out, + tx_outclock, + tx_coreclock, + tx_locked +); + + +// GLOBAL PARAMETER DECLARATION + + // No. of LVDS channels (required) + parameter number_of_channels = 1; + + // No. of bits per channel (required) + parameter deserialization_factor = 4; + + // Indicates whether the tx_in[] and tx_outclock ports should be registered. + parameter registered_input = "ON"; + + // "ON" means that sync_inclock is also used + // (not used for Stratix and Stratix GX devices.) + parameter multi_clock = "OFF"; + + // The period of the input clock in ps (Required) + parameter inclock_period = 10000; + + // Specifies the period of the tx_outclock port as + // [INCLOCK_PERIOD * OUTCLOCK_DIVIDE_BY] + parameter outclock_divide_by = deserialization_factor; + + // The effective clock period to sample output data + parameter inclock_boost = deserialization_factor; + + // Aligns the Most Significant Bit(MSB) to the falling edge of the clock + // instead of the rising edge. (only for APEX II devices) + parameter center_align_msb = "OFF"; + + // The device family to be used. + parameter intended_device_family = "APEX20KE"; + + // Data rate out of the PLL. (required and only for Stratix and + // Stratix GX devices) + parameter output_data_rate = 0; + + // The alignment of the input data with respect to the tx_inclock port. + // (required and only for Stratix and Stratix GX devices) + parameter inclock_data_alignment = "EDGE_ALIGNED"; + + // The alignment of the output data with respect to the tx_outclock port. + // (required and only for Stratix and Stratix GX devices) + parameter outclock_alignment = "EDGE_ALIGNED"; + + // Specifies whether the compiler uses the same PLL for both the LVDS + // receiver and the LVDS transmitter + parameter common_rx_tx_pll = "ON"; + + parameter outclock_resource = "AUTO"; + parameter use_external_pll = "OFF"; + parameter implement_in_les = "OFF"; + parameter preemphasis_setting = 0; + parameter vod_setting = 0; + parameter differential_drive = 0; + + parameter lpm_type = "altlvds_tx"; + parameter lpm_hint = "UNUSED"; + + // Specifies whether the source of the input clock is from a PLL + parameter clk_src_is_pll = "off"; + + +// LOCAL PARAMETER DECLARATION + + // A APEX20KE type of LVDS? + parameter APEX20KE_TX_STYLE = (intended_device_family == "APEX20KE") || + (intended_device_family == "EXCALIBUR_ARM") || + (intended_device_family == "EXCALIBUR_MIPS") || + (intended_device_family == "APEX20KC") + ? 1 : 0; + + // A APEXII type of LVDS? + parameter APEXII_TX_STYLE = (intended_device_family == "APEXII") || + (intended_device_family == "APEX II") + ? 1 : 0; + + // A MERCURY type of LVDS? + parameter MERCURY_TX_STYLE = (intended_device_family == "MERCURY") || + (intended_device_family == "Mercury") + ? 1 : 0; + + // A STRATIX type of LVDS? + parameter STRATIX_TX_STYLE = (intended_device_family == "Stratix") || + (intended_device_family == "STRATIX") || + (intended_device_family == "STRATIXGX") || + (intended_device_family == "STRATIX-GX") || + (intended_device_family == "Stratix GX") || + (intended_device_family == "HardCopy Stratix") || + (intended_device_family == "HARDCOPY STRATIX") || + (intended_device_family == "hardcopy stratix") || + (intended_device_family == "HardcopyStratix") || + (intended_device_family == "HARDCOPYSTRATIX") || + (intended_device_family == "hardcopystratix") + ? 1 : 0; + + // A STRATIXII type of LVDS? + parameter STRATIXII_TX_STYLE = ((intended_device_family == "Stratix II") || + (intended_device_family == "StratixII") || + (intended_device_family == "HardCopy II") || + (intended_device_family == "HardCopyII") || + (intended_device_family == "HARDCOPY II") || + (intended_device_family == "HARDCOPYII") || + (intended_device_family == "hardcopy ii") || + (intended_device_family == "hardcopyii") || + (intended_device_family == "Stratix II GX") || + (intended_device_family == "STRATIX II GX") || + (intended_device_family == "stratix ii gx") || + (intended_device_family == "StratixIIGX") || + (intended_device_family == "STRATIXIIGX") || + (intended_device_family == "stratixiigx")) + ? 1 : 0; + + // A Cyclone type of LVDS? + parameter CYCLONE_TX_STYLE = ((intended_device_family == "Cyclone") || + (intended_device_family == "CYCLONE") || + (intended_device_family == "cyclone")) + ? 1 : 0; + + // A Cyclone II type of LVDS? + parameter CYCLONEII_TX_STYLE = ((intended_device_family == "Cyclone II") || + (intended_device_family == "CYCLONE II") || + (intended_device_family == "cyclone ii") || + (intended_device_family == "Cycloneii") || + (intended_device_family == "CYCLONEII") || + (intended_device_family == "cycloneii")) + ? 1 : 0; + + // Is the device family has flexible LVDS? +parameter FAMILY_HAS_FLEXIBLE_LVDS = ((CYCLONE_TX_STYLE == 1) || + (CYCLONEII_TX_STYLE == 1) || + (((STRATIX_TX_STYLE == 1) || (STRATIXII_TX_STYLE == 1)) && + (implement_in_les == "ON"))) + ? 1 : 0; + + // Is the family has Stratix style PLL + parameter FAMILY_HAS_STRATIX_STYLE_PLL = ((STRATIX_TX_STYLE == 1) || + (CYCLONE_TX_STYLE == 1)) + ? 1 : 0; + + // Is the family has Stratix style PLL + parameter FAMILY_HAS_STRATIXII_STYLE_PLL = ((STRATIXII_TX_STYLE == 1) || + (CYCLONEII_TX_STYLE == 1)) + ? 1 : 0; + + // Parameter to check whether the selected lvds trasmitter use + // holding register or not. + parameter TX_NEED_HOLD = (((APEX20KE_TX_STYLE == 1) && + (deserialization_factor >= 7)) || + ((APEXII_TX_STYLE == 1) && + (deserialization_factor >= 5)) || + ((MERCURY_TX_STYLE == 1) && + (deserialization_factor >= 7))) + ? 1 : 0; + + // calculate clock boost for device family other than STRATIX and STRATIX GX + parameter INT_CLOCK_BOOST = (APEX20KE_TX_STYLE == 1) + ? deserialization_factor : + ((inclock_boost == 0) + ? deserialization_factor + : inclock_boost); + + // M value for Stratix/Stratix II/Cyclone/Cyclone II PLL + parameter PLL_M_VALUE = (((output_data_rate * inclock_period) + + (5 * 100000)) / 1000000); + + // D value for Stratix/Stratix II/Cyclone/Cyclone II PLL + parameter PLL_D_VALUE = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? ((output_data_rate !=0) && (inclock_period !=0) + ? 2 + : 1) + : 1; + + // calculate clock boost for STRATIX, STRATIX GX and STRATIX II + parameter STRATIX_INCLOCK_BOOST = + ((output_data_rate !=0) && (inclock_period !=0)) + ? PLL_M_VALUE : + ((inclock_boost == 0) + ? deserialization_factor + : inclock_boost); + + // parameter for inclock phase shift. Add 0.5 to the calculated result to + // round up result to the nearest integer. + // CENTER_ALIGNED means 180 degrees + parameter PHASE_INCLOCK = (inclock_data_alignment == "EDGE_ALIGNED")? + 0 : + (inclock_data_alignment == "CENTER_ALIGNED") ? + (0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5: + (inclock_data_alignment == "45_DEGREES") ? + (0.125 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5: + (inclock_data_alignment == "90_DEGREES") ? + (0.25 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5: + (inclock_data_alignment == "135_DEGREES") ? + (0.375 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5: + (inclock_data_alignment == "180_DEGREES") ? + (0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5: + (inclock_data_alignment == "225_DEGREES") ? + (0.625 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5: + (inclock_data_alignment == "270_DEGREES") ? + (0.75 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5: + (inclock_data_alignment == "315_DEGREES") ? + (0.875 * inclock_period / STRATIX_INCLOCK_BOOST) + 0.5: 0; + + // parameter for Stratix II inclock phase shift. + parameter STXII_PHASE_INCLOCK = PHASE_INCLOCK - (0.5 * inclock_period / STRATIX_INCLOCK_BOOST); + + // parameter for outclock phase shift. Add 0.5 to the calculated result to + // round up result to the nearest integer. + parameter PHASE_OUTCLOCK = (outclock_alignment == "EDGE_ALIGNED") ? + 0: + (outclock_alignment == "CENTER_ALIGNED") ? + ((0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5): + (outclock_alignment == "45_DEGREES") ? + ((0.125 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5): + (outclock_alignment == "90_DEGREES") ? + ((0.25 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5): + (outclock_alignment == "135_DEGREES") ? + ((0.375 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5): + (outclock_alignment == "180_DEGREES") ? + ((0.5 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5): + (outclock_alignment == "225_DEGREES") ? + ((0.625 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5): + (outclock_alignment == "270_DEGREES") ? + ((0.75 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5): + (outclock_alignment == "315_DEGREES") ? + ((0.875 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5): 0; + + // parameter for Stratix and Stratix GX outclock phase shift. + // Add 0.5 to the calculated result to round up result to the nearest integer. + parameter STX_PHASE_OUTCLOCK = ((outclock_divide_by == 1) || + (outclock_alignment == "45_DEGREES") || + (outclock_alignment == "90_DEGREES") || + (outclock_alignment == "135_DEGREES")) ? + PHASE_OUTCLOCK + PHASE_INCLOCK: + ((outclock_alignment == "180_DEGREES") || + (outclock_alignment == "CENTER_ALIGNED")) ? + PHASE_INCLOCK : + (outclock_alignment == "225_DEGREES") ? + ((0.125 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5 + PHASE_INCLOCK): + (outclock_alignment == "270_DEGREES") ? + ((0.25 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5 + PHASE_INCLOCK): + (outclock_alignment == "315_DEGREES") ? + ((0.375 * inclock_period / STRATIX_INCLOCK_BOOST) + + 0.5 + PHASE_INCLOCK): PHASE_INCLOCK; + + // parameter for Stratix II outclock phase shift. + parameter STXII_PHASE_OUTCLOCK = STX_PHASE_OUTCLOCK - (0.5 * inclock_period / STRATIX_INCLOCK_BOOST); + + parameter REGISTER_WIDTH = deserialization_factor * number_of_channels; + + // input clock period for PLL. + parameter CLOCK_PERIOD = (deserialization_factor > 2) ? inclock_period : 10000; + + +// INPUT PORT DECLARATION + + // Input data (required) + input [REGISTER_WIDTH -1 : 0] tx_in; + + // Input clock (required) + input tx_inclock; + + input tx_enable; + + // Optional clock for input registers (Required if "multi_clock" parameters + // is turned on) + input sync_inclock; + + // Enable control for the LVDS PLL + input tx_pll_enable; + + // Asynchronously resets all counters to initial values (only for Stratix + // and Stratix GX devices) + input pll_areset; + + + +// OUTPUT PORT DECLARATION + + // Serialized data signal(required) + output [number_of_channels-1 :0] tx_out; + + // External reference clock + output tx_outclock; + + // Output clock used to feed non-peripheral logic. + // Only available for Mercury, Stratix, and Stratix GX devices only. + output tx_coreclock; + + // Gives the status of the LVDS PLL + // (when the PLL is locked, this signal is VCC. GND otherwise) + output tx_locked; + + +// INTERNAL REGISTERS DECLARATION + + reg [REGISTER_WIDTH -1 : 0] tx_hold_reg; + reg [REGISTER_WIDTH -1 : 0] tx_in_reg; + reg [REGISTER_WIDTH -1 : 0] tx_shift_reg; + reg [REGISTER_WIDTH -1 : 0] tx_parallel_load_reg; + reg tx_mercury_core_clock; + reg fb; + reg [number_of_channels-1 :0] tx_out_apex; + reg [number_of_channels-1 :0] tx_out_stratix; + reg [number_of_channels-1 :0] tx_ddio_out; + reg [number_of_channels-1 :0] dataout_l; + reg [number_of_channels-1 :0] dataout_h; + reg enable0_reg1; + reg enable0_reg2; + reg enable0_neg; + reg tx_fastclk_pre; + reg [9 : 0] stx_phase_shift_txdata; + reg [9 : 0] phase_shift_txdata; + + +// INTERNAL WIRE DECLARATION + + wire [REGISTER_WIDTH -1 : 0] tx_in_int; + wire tx_fastclk; + wire tx_slowclk; + wire tx_reg_clk; + wire tx_hold_clk; + wire tx_coreclock_int; + wire tx_locked_int; + wire unused_clk_ext; + wire [2:0] altclklock_clk; + wire altclklock_locked; + wire altclklock_inclock; + wire altclklock_clkena; + wire [1:0] stratix_pll_inclock; + wire [1:0] stratixii_pll_inclock; + wire [5:0] stratix_pll_outclock; + wire [5:0] stratixii_pll_outclock; + wire stratix_pll_enable; + wire stratixii_pll_enable; + wire stratix_pll_areset; + wire stratixii_pll_areset; + wire stratix_locked; + wire stratixii_locked; + wire stratix_enable0; + wire stratixii_enable0; + wire stratix_enable1; + wire stratixii_enable1; + wire stratix_outclock; + wire stratixii_outclock; + wire stratixii_sclkout0; + wire stratixii_sclkout1; + wire stratix_inclock; + wire stratix_enable; + wire stratixii_inclock; + wire stratixii_enable; + wire flvds_fastclk; + wire flvds_slowclk; + wire flvds_regclk; + wire[number_of_channels-1 :0] flvds_dataout; + +// INTERNAL TRI DECLARATION + + tri1 tx_enable; + tri0 sync_inclock; + tri1 tx_pll_enable; + tri0 pll_areset; + +// LOCAL INTEGER DECLARATION + + integer count; + integer i; + integer i1; + integer i2; + integer posedge_count; + integer negedge_count; + integer shift_data; + +// LOCAL TIME DECLARATION + + time tx_out_delay; + +// COMPONENT INSTANTIATIONS + ALTERA_DEVICE_FAMILIES dev (); + +// INITIAL CONSTRUCT BLOCK + + initial + begin : INITIALIZATION + tx_in_reg = {REGISTER_WIDTH{1'b0}}; + tx_hold_reg = {REGISTER_WIDTH{1'b0}}; + tx_parallel_load_reg = {REGISTER_WIDTH{1'b0}}; + tx_shift_reg = {REGISTER_WIDTH{1'b0}}; + + tx_out_apex = {number_of_channels{1'b0}}; + tx_out_stratix = {number_of_channels{1'b0}}; + tx_ddio_out = {number_of_channels{1'b0}}; + dataout_l = {number_of_channels{1'b0}}; + dataout_h = {number_of_channels{1'b0}}; + + fb = 'b1; + count = 0; + shift_data = 0; + negedge_count = 0; + posedge_count = 0; + + tx_out_delay = inclock_period/(deserialization_factor*2); + + // Input data needed by stratix_tx_outclk in order to generate the tx_outclock. + stx_phase_shift_txdata = 0; + if (outclock_divide_by > 1) + begin + if (deserialization_factor == 4) + begin + if ( outclock_divide_by == 2) + stx_phase_shift_txdata[3:0] = 4'b1010; + else if (outclock_divide_by == 4) + stx_phase_shift_txdata[3:0] = 4'b0011; + end + else if (deserialization_factor == 8) + begin + if (outclock_divide_by == 2) + stx_phase_shift_txdata[7:0] = 8'b10101010; + else if (outclock_divide_by == 4) + stx_phase_shift_txdata[7:0] = 8'b00110011; + else if (outclock_divide_by == 8) + stx_phase_shift_txdata[7:0] = 8'b11000011; + end + else if (deserialization_factor == 10) + begin + if (outclock_divide_by == 2) + stx_phase_shift_txdata[9:0] = 10'b1010101010; + else if (outclock_divide_by == 10) + stx_phase_shift_txdata[9:0] = 10'b1110000011; + end + else if (deserialization_factor == 7) + if (outclock_divide_by == 7) + stx_phase_shift_txdata[6:0] = 7'b1100011; + end + + // Input data needed by stratixii_tx_outclk in order to generate the tx_outclock. + phase_shift_txdata = 0; + if (outclock_divide_by > 1) + begin + if (deserialization_factor == 4) + begin + if ( outclock_divide_by == 2) + phase_shift_txdata[3:0] = 4'b1010; + else if (outclock_divide_by == 4) + phase_shift_txdata[3:0] = 4'b1100; + end + else if (deserialization_factor == 6) + begin + if (outclock_divide_by == 2) + phase_shift_txdata[5:0] = 6'b101010; + else if (outclock_divide_by == 6) + phase_shift_txdata[5:0] = 6'b111000; + end + else if (deserialization_factor == 8) + begin + if (outclock_divide_by == 2) + phase_shift_txdata[7:0] = 8'b10101010; + else if (outclock_divide_by == 4) + phase_shift_txdata[7:0] = 8'b11001100; + else if (outclock_divide_by == 8) + phase_shift_txdata[7:0] = 8'b11110000; + end + else if (deserialization_factor == 10) + begin + if (outclock_divide_by == 2) + phase_shift_txdata[9:0] = 10'b1010101010; + else if (outclock_divide_by == 10) + phase_shift_txdata[9:0] = 10'b1111100000; + end + else if (deserialization_factor == 7) + if (outclock_divide_by == 7) + phase_shift_txdata[6:0] = 7'b1111000; + end + + // Check for illegal mode settings + if ((APEX20KE_TX_STYLE == 1) && (deserialization_factor != 1) && + (deserialization_factor != 4) && (deserialization_factor != 7) && + (deserialization_factor != 8)) + begin + $display ($time, "ps Error: APEX20KE does not support the specified deserialization factor!"); + $finish; + end + else if ((MERCURY_TX_STYLE == 1) && + (deserialization_factor != 1) && (deserialization_factor != 2) && + (((deserialization_factor > 12) && + (deserialization_factor != 14) && + (deserialization_factor != 16) && + (deserialization_factor != 18) && + (deserialization_factor != 20)) ||(deserialization_factor < 3))) + begin + $display ($time, "ps Error: MERCURY does not support the specified deserialization factor!"); + $finish; + end + else if (((APEXII_TX_STYLE == 1)) && + ((deserialization_factor > 10) || (deserialization_factor < 4)) && + (deserialization_factor != 1) && (deserialization_factor != 2)) + begin + $display ($time, "ps Error: APEXII does not support the specified deserialization factor!"); + $finish; + end + else if ((STRATIX_TX_STYLE == 1) && + (deserialization_factor != 1) && (deserialization_factor != 2) && + ((deserialization_factor > 10) || (deserialization_factor < 4))) + begin + $display ($time, "ps Error: STRATIX does not support the specified deserialization factor!"); + $finish; + end + else if ((STRATIXII_TX_STYLE == 1) && + (deserialization_factor > 10)) + begin + $display ($time, "ps Error: STRATIX II does not support the specified deserialization factor!"); + $finish; + end + + if (CYCLONE_TX_STYLE == 1) + begin + if ((use_external_pll == "ON") && + (deserialization_factor != 1) && (deserialization_factor != 2) && + (deserialization_factor != 4) && (deserialization_factor != 6) && + (deserialization_factor != 8) && (deserialization_factor != 10)) + begin + $display ($time, "ps Error: Cyclone does not support the specified deserialization factor when use_external_pll is 'ON'!"); + $finish; + end + else if ((deserialization_factor > 10) || (deserialization_factor == 3)) + begin + $display ($time, "ps Error: Cyclone does not support the specified deserialization factor when use_external_pll is 'OFF'!"); + $finish; + end + end + + if (CYCLONEII_TX_STYLE == 1) + begin + if ((use_external_pll == "ON") && + (deserialization_factor != 1) && (deserialization_factor != 2) && + (deserialization_factor != 4) && (deserialization_factor != 6) && + (deserialization_factor != 8) && (deserialization_factor != 10)) + begin + $display ($time, "ps Error: Cyclone II does not support the specified deserialization factor when use_external_pll is 'ON'!"); + $finish; + end + else if ((deserialization_factor > 10) || (deserialization_factor == 3)) + begin + $display ($time, "ps Error: Cyclone II does not support the specified deserialization factor when use_external_pll is 'OFF'!"); + $finish; + end + end + + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $finish; + end + + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $finish; + end + + end // INITIALIZATION + + +// COMPONENT INSTANTIATIONS + + // PLL for device family other than Stratix, Stratix GX and Stratix II + altclklock u0 ( + .inclock(altclklock_inclock), // Required + .inclocken(altclklock_clkena), + .fbin(fb), + .clock0(altclklock_clk[0]), + .clock1(altclklock_clk[1]), + .clock2(altclklock_clk[2]), + .clock_ext(unused_clk_ext), + .locked(altclklock_locked)); + + defparam + u0.inclock_period = CLOCK_PERIOD, + u0.clock0_boost = INT_CLOCK_BOOST, + u0.clock1_boost = INT_CLOCK_BOOST, + u0.clock1_divide = deserialization_factor, + u0.clock2_boost = (MERCURY_TX_STYLE == 1) ? + INT_CLOCK_BOOST : 1, + u0.clock2_divide = (MERCURY_TX_STYLE == 1) ? + outclock_divide_by : 1, + u0.valid_lock_cycles = (APEXII_TX_STYLE == 1) ? 1 : + (MERCURY_TX_STYLE == 1) ? 3 : 5, + u0.intended_device_family = ((APEX20KE_TX_STYLE == 1 ) || + (APEXII_TX_STYLE == 1 ) || + (MERCURY_TX_STYLE == 1 )) + ? intended_device_family + : "APEX20KE"; + + + // PLL for Stratix and Stratix GX + MF_stratix_pll u1 ( + .inclk(stratix_pll_inclock), // Required + .ena(stratix_pll_enable), + .areset(stratix_pll_areset), + .clkena(6'b111111), + .clk (stratix_pll_outclock), + .locked(stratix_locked), + .fbin(1'b1), + .clkswitch(1'b0), + .pfdena(1'b1), + .extclkena(4'b0), + .scanclk(1'b0), + .scanaclr(1'b0), + .scandata(1'b0), + .comparator(1'b0), + .extclk(), + .clkbad(), + .enable0(stratix_enable0), + .enable1(stratix_enable1), + .activeclock(), + .clkloss(), + .scandataout() ); + + defparam + u1.primary_clock = "inclk0", + u1.pll_type = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? "flvds" + : "lvds", + u1.inclk0_input_frequency = CLOCK_PERIOD, + u1.valid_lock_multiplier = 1, + u1.clk0_multiply_by = STRATIX_INCLOCK_BOOST, + u1.clk0_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PLL_D_VALUE + : 1, + u1.clk0_phase_shift_num = PHASE_INCLOCK, + u1.clk1_multiply_by = STRATIX_INCLOCK_BOOST, + u1.clk1_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PLL_D_VALUE*outclock_divide_by + : 1, + u1.clk1_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PHASE_OUTCLOCK + : STX_PHASE_OUTCLOCK, + u1.clk2_multiply_by = STRATIX_INCLOCK_BOOST, + u1.clk2_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? ((deserialization_factor%2 == 0) + ? PLL_D_VALUE*deserialization_factor/2 + : PLL_D_VALUE*deserialization_factor) + : deserialization_factor, + u1.clk2_phase_shift_num = PHASE_INCLOCK, + u1.simulation_type = "functional", + u1.m = 0; + + // PLL for Stratix II + MF_stratixii_pll u2 ( + .inclk(stratixii_pll_inclock), // Required + .ena(stratixii_pll_enable), + .areset(stratixii_pll_areset), + .clk (stratixii_pll_outclock ), + .locked(stratixii_locked), + .fbin(1'b1), + .clkswitch(1'b0), + .pfdena(1'b1), + .scanclk(1'b0), + .scanread(1'b0), + .scanwrite(1'b0), + .scandata(1'b0), + .testin(4'b0), + .clkbad(), + .enable0(stratixii_enable0), + .enable1(stratixii_enable1), + .activeclock(), + .clkloss(), + .scandataout(), + .scandone(), + .sclkout({stratixii_sclkout1, stratixii_sclkout0}), + .testupout(), + .testdownout()); + + defparam + u2.primary_clock = "inclk0", + u2.pll_type = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? "flvds" + : "lvds", + u2.vco_multiply_by = STRATIX_INCLOCK_BOOST, + u2.vco_divide_by = 1, + u2.inclk0_input_frequency = CLOCK_PERIOD, + u2.clk0_multiply_by = STRATIX_INCLOCK_BOOST, + u2.clk0_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PLL_D_VALUE + : deserialization_factor, + u2.clk0_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PHASE_INCLOCK + : STXII_PHASE_INCLOCK, + u2.clk1_multiply_by = STRATIX_INCLOCK_BOOST, + u2.clk1_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PLL_D_VALUE*outclock_divide_by + : deserialization_factor, + u2.clk1_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PHASE_OUTCLOCK + : STXII_PHASE_OUTCLOCK, + u2.clk2_multiply_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? STRATIX_INCLOCK_BOOST + : 1, + u2.clk2_divide_by = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? ((deserialization_factor%2 == 0) + ? PLL_D_VALUE*deserialization_factor/2 + : PLL_D_VALUE*deserialization_factor) + : 1, + u2.clk2_phase_shift_num = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? PHASE_INCLOCK + : 1, + u2.sclkout0_phase_shift = STXII_PHASE_INCLOCK, + u2.sclkout1_phase_shift = STXII_PHASE_OUTCLOCK, + u2.simulation_type = "functional", + u2.m = 0; + + + // This module produces output clock for Stratix and Stratix GX. + stratix_tx_outclk u3 ( + .tx_in(stx_phase_shift_txdata), + .tx_fastclk(stratix_inclock), + .tx_enable(stratix_enable), + .tx_out(stratix_outclock)); + defparam + u3.deserialization_factor = deserialization_factor, + u3.bypass_serializer = (outclock_divide_by == 1) ? + "TRUE" : "'FALSE", + u3.use_falling_clock_edge = ((outclock_alignment == "180_DEGREES") || + (outclock_alignment == "CENTER_ALIGNED") || + (outclock_alignment == "225_DEGREES") || + (outclock_alignment == "270_DEGREES") || + (outclock_alignment == "315_DEGREES")) ? + "TRUE" : "FALSE"; + + + // This module produces output clock for StratixII. + stratixii_tx_outclk u4 ( + .tx_in(phase_shift_txdata), + .tx_fastclk(stratixii_inclock), + .tx_enable(stratixii_enable), + .tx_out(stratixii_outclock)); + + defparam + u4.deserialization_factor = deserialization_factor, + u4.bypass_serializer = (outclock_divide_by == 1) ? + "TRUE" : "'FALSE", + u4.use_falling_clock_edge = ((outclock_alignment == "180_DEGREES") || + (outclock_alignment == "CENTER_ALIGNED") || + (outclock_alignment == "225_DEGREES") || + (outclock_alignment == "270_DEGREES") || + (outclock_alignment == "315_DEGREES")) ? + "TRUE" : "FALSE"; + + // This module produces output clock for StratixII. + flexible_lvds_tx u5 ( + .tx_in(tx_in), + .tx_fastclk(flvds_fastclk), + .tx_slowclk(flvds_slowclk), + .tx_regclk(flvds_regclk), + .tx_locked(tx_locked_int), + .tx_out(flvds_dataout)); + + defparam + u5.number_of_channels = number_of_channels, + u5.deserialization_factor = deserialization_factor, + u5.registered_input = registered_input; + +// ALWAYS CONSTRUCT BLOCK + + // For x2 mode. For each data channel, input data are separated into 2 data + // stream which will be transmitted on different edge of input clock. + always @ (posedge tx_inclock) + begin : DDIO_OUT_RECEIVE + if (deserialization_factor == 2) + begin + for (i1 = 0; i1 < number_of_channels; i1 = i1 +1) + begin + dataout_l[i1] <= tx_in_int[i1*2]; + dataout_h[i1] <= tx_in_int[i1*2+1]; + end + end + end // DDIO_OUT_RECEIVE + + // Fast Clock + always @ (posedge tx_fastclk) + begin : FAST_CLOCK_POS + if (deserialization_factor > 2) + begin + + // registering load enable signal + enable0_reg2 <= enable0_reg1; + enable0_reg1 <= (use_external_pll == "ON") ? tx_enable : + (STRATIX_TX_STYLE == 1) ? stratix_enable0 : + stratixii_enable0; + + if ((STRATIX_TX_STYLE == 0) && (STRATIXII_TX_STYLE == 0)) + begin + posedge_count <= (posedge_count+1) % deserialization_factor; + if (posedge_count == 2) + begin + // register incoming data on the third edge + tx_shift_reg <= tx_parallel_load_reg; + count <= 2; + for (i = 0; i < number_of_channels; i = i +1) + // Data in MSB gets shifted out first. + // NB: This happens 1/2clk cycle later for APEXII (MSB + // only) when center_align_msb is ON. + begin + if ((i == number_of_channels-1) && + ((APEXII_TX_STYLE == 1)) && + (center_align_msb == "ON")) + begin + tx_out_apex[i] <= #tx_out_delay + tx_parallel_load_reg[(i+1)*deserialization_factor - 1]; + end + else + begin + tx_out_apex[i] <= tx_parallel_load_reg[(i+1)*deserialization_factor - 1]; + end + end + + end + else + begin + count <= count + 1; + for (i = 0; i < number_of_channels; i = i +1) + // Data in MSB gets shifted out first. + // NB: This happens 1/2clk cycle later for APEXII (MSB + // only) when center_align_msb is ON. + begin + if ((i == number_of_channels-1) && + ((APEXII_TX_STYLE == 1)) && + (center_align_msb == "ON")) + begin + tx_out_apex[i] <= #tx_out_delay + tx_shift_reg[(i+1)*deserialization_factor - count]; + end + else + begin + tx_out_apex[i] <= tx_shift_reg[(i+1)*deserialization_factor - count]; + end + end + end + + // Mercury core clock is assymmetrical for odd deserialization + // factor values. + if (posedge_count == ((deserialization_factor+1)/2+1)) + begin + tx_mercury_core_clock <= ~tx_mercury_core_clock; + end + end + else + begin + if(((STRATIX_TX_STYLE == 1) && (enable0_neg == 1)) || + ((STRATIXII_TX_STYLE == 1) && (enable0_reg1 == 1))) + begin + tx_shift_reg <= tx_parallel_load_reg; + count <= 2; + + for (i = 0; i < number_of_channels; i = i +1) + begin + tx_out_stratix[i] <= tx_parallel_load_reg[(i+1)*deserialization_factor - 1]; + end + end + else + begin + count <= (count % deserialization_factor) + 1; + for (i = 0; i < number_of_channels; i = i +1) + begin + tx_out_stratix[i] <= tx_shift_reg[(i+1)*deserialization_factor - count]; + end + end + + // Loading data to parallel load register for Stratix and + // Stratix GX + if (((STRATIX_TX_STYLE == 1) && (stratix_enable0 == 1)) || + (STRATIXII_TX_STYLE == 1)) + begin + tx_parallel_load_reg <= tx_in_int; + end + end + end + end // FAST_CLOCK_POS + + always @ (negedge tx_fastclk) + begin : FAST_CLOCK_NEG + if (deserialization_factor > 2) + begin + // registering load enable signal + enable0_neg <= enable0_reg2; + + negedge_count <= negedge_count + 1; + + // Loading data to parallel load register for non-STRATIX family + if ((negedge_count == 2) && (STRATIX_TX_STYLE == 0) && + (STRATIXII_TX_STYLE == 0) && + (tx_locked_int == 1)) + begin + if (TX_NEED_HOLD == 1) + begin + tx_parallel_load_reg <= tx_hold_reg; + end + else + begin + tx_parallel_load_reg <= tx_in_int; + end + end + end + end // FAST_CLOCK_NEG + + // Slow Clock + always @ (posedge tx_slowclk) + begin : SLOW_CLOCK + negedge_count <= 0; + tx_mercury_core_clock <= tx_slowclk; + end // SLOW_CLOCK + + // synchronization register + always @ (posedge tx_reg_clk) + begin : SYNC_REGISTER + tx_in_reg <= #5 tx_in; + end // SYNC_REGISTER + + // hold register + always @ (negedge tx_hold_clk) + begin : HOLD_REGISTER + if (deserialization_factor > 1) + begin + tx_hold_reg <= tx_in_int; + end + end // HOLD_REGISTER + + + // CONTINOUS ASSIGNMENT + assign tx_out = (deserialization_factor == 1) + ? tx_in_int : + (deserialization_factor == 2) + ? ((tx_inclock == 1) ? dataout_h : dataout_l) : + (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? flvds_dataout : + ((STRATIX_TX_STYLE == 1) || (STRATIXII_TX_STYLE == 1)) + ? tx_out_stratix + : tx_out_apex; + + assign tx_in_int = (registered_input != "OFF") + ? tx_in_reg + : tx_in; + + assign tx_reg_clk = ((STRATIX_TX_STYLE == 1) || + (((STRATIXII_TX_STYLE == 1) || + (CYCLONE_TX_STYLE == 1) || + (CYCLONEII_TX_STYLE == 1)) && + (use_external_pll == "OFF"))) + ? ((registered_input == "TX_CLKIN") + ? tx_inclock + : tx_coreclock_int) : + (((registered_input == "ON") && + (multi_clock == "ON")) + ? sync_inclock + : tx_inclock); + + assign tx_hold_clk = (multi_clock == "ON") + ? sync_inclock : + ((MERCURY_TX_STYLE == 1) + ? tx_coreclock_int + : tx_inclock); + + assign tx_outclock = (deserialization_factor < 3) + ? tx_inclock : + ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIX_STYLE_PLL == 1)) + ? stratix_pll_outclock[1] : + ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)) + ? stratixii_pll_outclock[1] : + (STRATIX_TX_STYLE == 1) + ? stratix_outclock : + (STRATIXII_TX_STYLE == 1) + ? stratixii_outclock : + (MERCURY_TX_STYLE == 1) + ? altclklock_clk[2] : + (APEXII_TX_STYLE == 1) + ? tx_inclock + : tx_slowclk; + + assign tx_coreclock = tx_coreclock_int; + + assign tx_coreclock_int = (deserialization_factor < 3) + ? 1'b0 : + (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? flvds_slowclk : + (((deserialization_factor % 2) != 0) && + (MERCURY_TX_STYLE == 1)) + ? tx_mercury_core_clock + : tx_slowclk; + + assign tx_locked = (deserialization_factor > 2) + ? tx_locked_int + : 1'b1; + + assign tx_locked_int = ((STRATIX_TX_STYLE == 1) || + (CYCLONE_TX_STYLE == 1)) + ? stratix_locked : + ((STRATIXII_TX_STYLE == 1) || + (CYCLONEII_TX_STYLE == 1)) + ? stratixii_locked + : altclklock_locked; + + assign tx_fastclk = ((deserialization_factor < 3) || + (FAMILY_HAS_FLEXIBLE_LVDS == 1)) + ? 1'b0 : + (use_external_pll == "ON") + ? tx_inclock : + (STRATIX_TX_STYLE == 1) + ? stratix_pll_outclock[0] : + (STRATIXII_TX_STYLE == 1) + ? stratixii_sclkout0 + : altclklock_clk[0]; + + assign tx_slowclk = ((use_external_pll == "ON") || + (FAMILY_HAS_FLEXIBLE_LVDS == 1)) + ? 1'b0 : + (STRATIX_TX_STYLE == 1) + ? stratix_pll_outclock[2] : + (STRATIXII_TX_STYLE == 1) + ? stratixii_pll_outclock[0] + : altclklock_clk[1]; + + assign altclklock_inclock = ((STRATIX_TX_STYLE == 1) || + (STRATIXII_TX_STYLE == 1) || + (FAMILY_HAS_FLEXIBLE_LVDS == 1)) + ? 0 + : tx_inclock; + + assign altclklock_clkena = ((FAMILY_HAS_STRATIX_STYLE_PLL == 1) || + (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)) + ? 0 + : tx_pll_enable; + + assign stratix_pll_inclock[1:0] = (FAMILY_HAS_STRATIX_STYLE_PLL == 1) + ? {1'b0, tx_inclock} + : 2'b00; + + assign stratixii_pll_inclock[1:0] = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1) + ? {1'b0, tx_inclock} + : 2'b00; + + assign stratix_pll_enable = (FAMILY_HAS_STRATIX_STYLE_PLL == 1) + ? tx_pll_enable + : 1'b0; + + assign stratixii_pll_enable = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1) + ? tx_pll_enable + : 1'b0; + + assign stratix_pll_areset = (FAMILY_HAS_STRATIX_STYLE_PLL == 1) + ? pll_areset + : 1'b0; + + assign stratixii_pll_areset = (FAMILY_HAS_STRATIXII_STYLE_PLL == 1) + ? pll_areset + : 1'b0; + + assign stratix_inclock = ((STRATIX_TX_STYLE == 1) && + (implement_in_les == "OFF")) + ? stratix_pll_outclock[1] + : 1'b0; + + assign stratix_enable = ((STRATIX_TX_STYLE == 1) && + (implement_in_les == "OFF")) + ? stratix_enable1 + : 1'b0; + + assign stratixii_inclock = ((STRATIXII_TX_STYLE == 1) && + (implement_in_les == "OFF")) + ? ((use_external_pll == "ON") + ? tx_inclock + : stratixii_sclkout1) + : 1'b0; + + assign stratixii_enable = ((STRATIXII_TX_STYLE == 1) && + (implement_in_les == "OFF")) + ? ((use_external_pll == "ON") + ? tx_enable + : stratixii_enable1) + : 1'b0; + + assign flvds_fastclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIX_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? tx_inclock + : stratix_pll_outclock[0]) : + ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? tx_inclock + : stratixii_pll_outclock[0]) + : 1'b0; + + assign flvds_slowclk = ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIX_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? 1'b0 + : stratix_pll_outclock[2]) : + ((FAMILY_HAS_FLEXIBLE_LVDS == 1) && + (FAMILY_HAS_STRATIXII_STYLE_PLL == 1)) + ? ((use_external_pll == "ON") + ? 1'b0 + : stratixii_pll_outclock[2]) + : 1'b0; + + assign flvds_regclk = (FAMILY_HAS_FLEXIBLE_LVDS == 1) + ? tx_reg_clk + : 1'b0; + +endmodule // altlvds_tx +// END OF MODULE + + +//START_MODULE_NAME-------------------------------------------------------------- +// +// Module Name : stratix_tx_outclk + +// Description : This module is used to generate the tx_outclock for Stratix +// family. + +// Limitation : Only available STRATIX family. +// +// Results expected: Output clock. +// +//END_MODULE_NAME---------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +module stratix_tx_outclk ( + tx_in, + tx_fastclk, + tx_enable, + tx_out +); + +// GLOBAL PARAMETER DECLARATION + // No. of bits per channel (required) + parameter deserialization_factor = 4; + parameter bypass_serializer = "FALSE"; + parameter use_falling_clock_edge = "FALSE"; + +// INPUT PORT DECLARATION + // Input data (required) + input [9 : 0] tx_in; + // Input clock (required) + input tx_fastclk; + input tx_enable; + +// OUTPUT PORT DECLARATION + // Serialized data signal(required) + output tx_out; + +// INTERNAL REGISTERS DECLARATION + reg [deserialization_factor -1 : 0] tx_shift_reg; + reg [deserialization_factor -1 : 0] tx_parallel_load_reg; + reg tx_out_neg; + reg enable1_reg0; + reg enable1_reg1; + reg enable1_reg2; + +// INTERNAL TRI DECLARATION + tri1 tx_enable; + +// LOCAL INTEGER DECLARATION + integer x; + +// INITIAL CONSTRUCT BLOCK + + initial + begin : INITIALIZATION + tx_parallel_load_reg = {deserialization_factor{1'b0}}; + tx_shift_reg = {deserialization_factor{1'b0}}; + end // INITIALIZATION + +// ALWAYS CONSTRUCT BLOCK + + // registering load enable signal + always @ (posedge tx_fastclk) + begin : LOAD_ENABLE_POS + if (tx_fastclk === 1'b1) + begin + enable1_reg1 <= enable1_reg0; + enable1_reg0 <= tx_enable; + end + end // LOAD_ENABLE_POS + + always @ (negedge tx_fastclk) + begin : LOAD_ENABLE_NEG + enable1_reg2 <= enable1_reg1; + end // LOAD_ENABLE_NEG + + // Fast Clock + always @ (posedge tx_fastclk) + begin : POSEDGE_FAST_CLOCK + if (enable1_reg2 == 1'b1) + tx_shift_reg <= tx_parallel_load_reg; + else// Shift data from shift register to tx_out + begin + for (x=deserialization_factor-1; x >0; x=x-1) + tx_shift_reg[x] <= tx_shift_reg [x-1]; + end + + tx_parallel_load_reg <= tx_in[deserialization_factor-1 : 0]; + end // POSEDGE_FAST_CLOCK + + always @ (negedge tx_fastclk) + begin : NEGEDGE_FAST_CLOCK + tx_out_neg <= tx_shift_reg[deserialization_factor-1]; + end // NEGEDGE_FAST_CLOCK + +// CONTINUOUS ASSIGNMENT + assign tx_out = (bypass_serializer == "TRUE") ? tx_fastclk : + (use_falling_clock_edge == "TRUE") ? tx_out_neg : + tx_shift_reg[deserialization_factor-1]; + +endmodule // stratix_tx_outclk +// END OF MODULE + +//START_MODULE_NAME-------------------------------------------------------------- +// +// Module Name : stratixii_tx_outclk + +// Description : This module is used to generate the tx_outclock for StratixII +// family. + +// Limitation : Only available STRATIX II family. +// +// Results expected: Output clock. +// +//END_MODULE_NAME---------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +module stratixii_tx_outclk ( + tx_in, + tx_fastclk, + tx_enable, + tx_out +); + +// GLOBAL PARAMETER DECLARATION + // No. of bits per channel (required) + parameter deserialization_factor = 4; + parameter bypass_serializer = "FALSE"; + parameter use_falling_clock_edge = "FALSE"; + +// INPUT PORT DECLARATION + // Input data (required) + input [9 : 0] tx_in; + // Input clock (required) + input tx_fastclk; + input tx_enable; + +// OUTPUT PORT DECLARATION + // Serialized data signal(required) + output tx_out; + +// INTERNAL REGISTERS DECLARATION + reg [deserialization_factor -1 : 0] tx_shift_reg; + reg [deserialization_factor -1 : 0] tx_parallel_load_reg; + reg tx_out_reg; + reg tx_out_neg; + reg enable1_reg; + +// INTERNAL TRI DECLARATION + tri1 tx_enable; + +// LOCAL INTEGER DECLARATION + integer i1; + integer i2; + integer x; + +// INITIAL CONSTRUCT BLOCK + + initial + begin : INITIALIZATION + tx_parallel_load_reg = {deserialization_factor{1'b0}}; + tx_shift_reg = {deserialization_factor{1'b0}}; + + enable1_reg = 0; + + end // INITIALIZATION + +// ALWAYS CONSTRUCT BLOCK + + // Fast Clock + always @ (posedge tx_fastclk) + begin : POSEDGE_FAST_CLOCK + // registering enable1 signal + enable1_reg <= tx_enable; + + if (enable1_reg == 1'b1) + tx_shift_reg <= tx_parallel_load_reg; + else// Shift data from shift register to tx_out + begin + for (x=deserialization_factor-1; x >0; x=x-1) + tx_shift_reg[x] <= tx_shift_reg [x-1]; + end + + tx_parallel_load_reg <= tx_in[deserialization_factor-1 : 0]; + end // POSEDGE_FAST_CLOCK + + always @ (negedge tx_fastclk) + begin : NEGEDGE_FAST_CLOCK + tx_out_neg <= tx_shift_reg[deserialization_factor-1]; + end // NEGEDGE_FAST_CLOCK + +// CONTINUOUS ASSIGNMENT + assign tx_out = (bypass_serializer == "TRUE") ? tx_fastclk : + (use_falling_clock_edge == "TRUE") ? tx_out_neg : + tx_shift_reg[deserialization_factor-1]; + +endmodule // stratixii_tx_outclk +// END OF MODULE + + +//START_MODULE_NAME---------------------------------------------------- +// +// Module Name : flexible_lvds_tx +// +// Description : flexible lvds transmitter +// +// Limitation : Only available to Cyclone and Cyclone II +// families. +// +// Results expected: Serialized output data. +// +//END_MODULE_NAME---------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module flexible_lvds_tx ( + tx_in, // input serial data + tx_fastclk, // fast clock from pll + tx_slowclk, // slow clock from pll + tx_regclk, // clock for registering input data + tx_locked, // locked signal from PLL + tx_out // deserialized output data +); + +// GLOBAL PARAMETER DECLARATION + parameter number_of_channels = 1; + parameter deserialization_factor = 4; + parameter registered_input = "ON"; + +// LOCAL PARAMETER DECLARATION + parameter REGISTER_WIDTH = deserialization_factor*number_of_channels; + parameter DOUBLE_DESER = deserialization_factor*2; + +// INPUT PORT DECLARATION + input [REGISTER_WIDTH -1: 0] tx_in; + input tx_fastclk; + input tx_slowclk; + input tx_regclk; + input tx_locked; + +// OUTPUT PORT DECLARATION + output [number_of_channels -1 :0] tx_out; + +// INTERNAL REGISTERS DECLARATION + reg [REGISTER_WIDTH -1 : 0] tx_reg; + reg [(REGISTER_WIDTH*2) -1 : 0] tx_reg2; + reg [REGISTER_WIDTH -1 : 0] tx_shift_reg; + reg [(REGISTER_WIDTH*2) -1 : 0] tx_shift_reg2; + reg [REGISTER_WIDTH -1 :0] h_sync_a; + reg [(REGISTER_WIDTH*2) -1 :0] sync_b_reg; + reg [number_of_channels -1 :0] dataout_h; + reg [number_of_channels -1 :0] dataout_l; + reg [number_of_channels -1 :0] dataout_tmp; + reg [number_of_channels -1 :0] tx_ddio_out; + +// INTERNAL WIRE DECLARATION + wire [REGISTER_WIDTH -1 : 0] tx_in_int; + wire [(REGISTER_WIDTH*2) -1 : 0] tx_in_int2; + + +// LOCAL INTEGER DECLARATION + integer i1; + integer i2; + integer i3; + integer x; + integer x2; + integer loadcnt; + +// INITIAL CONSTRUCT BLOCK + initial + begin : INITIALIZATION + tx_reg = {REGISTER_WIDTH{1'b0}}; + tx_reg2 = {(REGISTER_WIDTH*2){1'b0}}; + + tx_shift_reg = {REGISTER_WIDTH{1'b0}}; + tx_shift_reg2 = {(REGISTER_WIDTH*2){1'b0}}; + + dataout_h = {number_of_channels{1'b0}}; + dataout_l = {number_of_channels{1'b0}}; + dataout_tmp = {number_of_channels{1'b0}}; + tx_ddio_out = {number_of_channels{1'b0}}; + + h_sync_a = {REGISTER_WIDTH{1'b0}}; + sync_b_reg = {(REGISTER_WIDTH*2){1'b0}}; + + loadcnt = 0; + end //INITIALIZATION + + +// ALWAYS CONSTRUCT BLOCK + + // For each data channel, input data are separated into 2 data + // stream which will be transmitted on different edge of input clock. + always @ (posedge tx_fastclk) + begin : DDIO_OUT_POS + if ((deserialization_factor % 2) == 0) + begin + for (i1 = 0; i1 < number_of_channels; i1 = i1 +1) + begin + dataout_h[i1] <= tx_shift_reg[(i1+1)*deserialization_factor-1]; + dataout_l[i1] <= tx_shift_reg[(i1+1)*deserialization_factor-2]; + dataout_tmp[i1] <= tx_shift_reg[(i1+1)*deserialization_factor-1]; + end + end + else + begin + for (i1 = 0; i1 < number_of_channels; i1 = i1 +1) + begin + dataout_h[i1] <= tx_shift_reg2[(i1+1)*DOUBLE_DESER-1]; + dataout_l[i1] <= tx_shift_reg2[(i1+1)*DOUBLE_DESER-2]; + dataout_tmp[i1] <= tx_shift_reg2[(i1+1)*DOUBLE_DESER-1]; + end + end + end // DDIO_OUT_POS + + always @ (negedge tx_fastclk) + begin : DDIO_OUT_NEG + dataout_tmp <= dataout_l; + end // DDIO_OUT_NEG + + // Loading input data to shift register + always @ (posedge tx_fastclk) + begin : SHIFTREG + + // if(tx_locked == 1'b1) + begin + // Implementation for even deserialization factor. + if ((deserialization_factor % 2) == 0) + begin + loadcnt <= (loadcnt + 1) % (deserialization_factor/2); + + if(loadcnt == 0) + tx_shift_reg <= tx_in_int; + else + begin + for (i2= 0; i2 < number_of_channels; i2 = i2+1) + begin + for (x=deserialization_factor-1; x >1; x=x-1) + tx_shift_reg[x + (i2 * deserialization_factor)] <= + tx_shift_reg [x-2 + (i2 * deserialization_factor)]; + end + end + end + else // Implementation for odd deserialization factor. + begin + loadcnt <= (loadcnt + 1) % deserialization_factor; + + if(loadcnt == 0) + tx_shift_reg2 <= tx_in_int2; + else + begin + for (i2= 0; i2 < number_of_channels; i2 = i2+1) + begin + for (x=DOUBLE_DESER-1; x >1; x=x-1) + tx_shift_reg2[x + (i2 * DOUBLE_DESER)] <= + tx_shift_reg2 [x-2 + (i2 * DOUBLE_DESER)]; + end + end + end + end + end // SHIFTREG + + // loading data to synchronization register + always @ (posedge tx_slowclk) + begin : SYNC_REG_POS + h_sync_a <= tx_in; + end // SYNC_REG_POS + + always @ (negedge tx_slowclk) + begin : SYNC_REG_NEG + + for (i3= 0; i3 < number_of_channels; i3 = i3+1) + begin + for (x2=0; x2 < deserialization_factor; x2=x2+1) + begin + sync_b_reg[x2 + (((i3 * 2) + 1) * deserialization_factor)] <= + h_sync_a[x2 + (i3 * deserialization_factor)]; + sync_b_reg[x2 + (i3 * DOUBLE_DESER)] <= + tx_in[x2 + (i3 * deserialization_factor)]; + end + end + end // SYNC_REG_NEG + + // loading data to input register + always @ (posedge tx_regclk) + begin : IN_REG + if ((deserialization_factor % 2) == 0) + tx_reg <= tx_in; + else + tx_reg2 <= sync_b_reg; + end // IN_REG + +// CONTINOUS ASSIGNMENT + assign tx_in_int = (registered_input == "OFF") ? tx_in : tx_reg; + assign tx_in_int2 = (registered_input == "OFF") ? sync_b_reg : tx_reg2; + assign tx_out = dataout_tmp; + + +endmodule // flexible_lvds_tx +// END OF MODULE + + +//START_MODULE_NAME---------------------------------------------------- +// +// Module Name : altcam +// +// Description : Content-addressable memory (CAM) Megafunction. The +// data contained in a CAM is a set of patterns that can be searched in a +// single-clock cycle. The altcam megafunction allows each stored pattern +// bit to be specified as a binary "1" bit, binary "0" bit, or a don't care bit. +// Comparing a stored pattern bit that is specified as don't care with its +// corresponding input pattern bit will always result in a match. +// +// Limitation : Input patterns cannot contain don't care bits. +// +// Results expected: If the input pattern given to the CAM matches one +// of the patterns stored in the CAM, the address of the matching stored +// pattern is generated. +// +//END_MODULE_NAME---------------------------------------------------- + +`timescale 1 ps / 1 ps + + +module altcam (pattern, wrx, wrxused, wrdelete, wraddress, wren, + inclock, inclocken, inaclr, outclock, + outclocken, outaclr, mstart, mnext, maddress, mbits, mfound, mcount, + rdbusy, wrbusy); + + parameter width = 1; + parameter widthad = 1; + parameter numwords = 1; + parameter lpm_file = "UNUSED"; + parameter lpm_filex = "UNUSED"; + parameter lpm_hint = "UNUSED"; + parameter match_mode = "MULTIPLE"; + parameter output_reg = "UNREGISTERED"; + parameter output_aclr = "ON"; + parameter pattern_reg = "INCLOCK"; + parameter pattern_aclr = "ON"; + parameter wraddress_aclr = "ON"; + parameter wrx_reg = "INCLOCK"; + parameter wrx_aclr = "ON"; + parameter wrcontrol_aclr = "ON"; + parameter use_eab = "ON"; + parameter lpm_type = "altcam"; + + // Input ports + input [width-1 : 0] pattern; // Required port + input [width-1 : 0] wrx; + input wrxused; + input wrdelete; + input [widthad-1 : 0] wraddress; + input wren; + input inclock; // Required port + input inclocken; + input inaclr; + input outclock; + input outclocken; + input outaclr; + input mstart; + input mnext; + + // Output ports + output [widthad-1 : 0] maddress; + output [numwords-1 : 0] mbits; + output mfound; + output [widthad-1 : 0] mcount; + output rdbusy; + output wrbusy; + + // Nets + tri1 wrxused_pullup; + tri1 inclocken_pullup; + tri1 outclocken_pullup; + tri0 wrdelete_pulldown; + tri0 inaclr_pulldown; + wire [width-1 : 0] pattern_int; + wire [width-1 : 0] wrx_int; + wire wrxused_int; + wire outclock_int; + wire outaclr_int; + wire rdbusy_delayed; + + // Registers + reg [width-1 : 0] pattern_rgd; + reg [width-1 : 0] wrx_rgd; + reg wrxused_rgd; + reg [widthad-1 : 0] wraddress_rgd; + reg wren_rgd; + reg wrdelete_rgd; + reg [widthad-1 : 0] maddress_rgd; + reg [widthad-1 : 0] maddress_int; + reg [numwords-1 : 0] mbits_rgd; + reg [numwords-1 : 0] mbits_int; + reg mfound_rgd; + reg mfound_int; + reg [widthad-1 : 0] mcount_rgd; + reg [widthad-1 : 0] mcount_int; + reg wrbusy_int; + reg rdbusy_int; + + // CAM registers + reg [width-1 : 0] cam_array [numwords-1 : 0]; + reg [width-1 : 0] x_array [numwords-1 : 0]; + + // Read control registers + reg first_read_clock; + reg get_first_match; + reg get_next_match; + reg mstart_rgd1; + reg mstart_rgd2; + reg first_read_in_write; + + // Write control registers + reg write_start; + reg write_start_rgd; + reg write_start_1; + reg write_incomplete; + reg write0; + reg write1; + reg writex; + reg write0_done; + reg write1_done; + reg writex_done; + + // Variables + reg [8*256:1] cam_initf; + reg [8*256:1] cam_initx; + reg [width-1 : 0] word_0; + reg [width-1 : 0] word_1; + reg [widthad-1 : 0] address_0; + reg [widthad-1 : 0] address_1; + reg [numwords-1 : 0] numwords_0; + integer count; + integer index; + integer i, j, k, addr; + integer next_search; + reg restart_read; + reg reset_read; + reg mstart_used; + reg [width-1:0] ipattern; + reg [widthad-1:0] iwraddress; + reg [width-1:0] iwrx; + reg iwren; + reg iwrxused; + reg [numwords-1 : 0] mbits_tmp; + + function read_cam_array; + input [widthad-1 : 0] i; + input [width-1 : 0] j; + begin: READ_CAM + reg [width-1 : 0] tmp; + tmp = cam_array[i]; + read_cam_array = tmp[j]; + end // end READ_CAM + endfunction // end of read_cam_array + + task write_cam_array; + input [widthad-1 : 0] i; + input [width-1 : 0] j; + input value; + begin: WRITE_CAM + reg [width-1 : 0] tmp; + tmp = cam_array[i]; + tmp[j] = value; + cam_array[i] = tmp; + end // end of WRITE_CAM + endtask // end of write_cam_array + + function read_x_array; + input [widthad-1 : 0] i; + input [width-1 : 0] j; + begin: READ_X + reg [width-1 : 0] tmp; + tmp = x_array[i]; + read_x_array = tmp[j]; + end // end of READ_X + endfunction // end of read_x_array + + task write_x_array; + input [widthad-1 : 0] i; + input [width-1 : 0] j; + input value; + begin: WRITE_X + reg [width-1 : 0] tmp; + tmp = x_array[i]; + tmp[j] = value; + x_array[i] = tmp; + end // end of WRITE_X + endtask // end of write_x_array + + ALTERA_MF_MEMORY_INITIALIZATION mem (); + + initial + begin + + // Checking for invalid parameters + if( width <= 0 ) + begin + $display("Error! Value of width parameter must be greater than 0."); + $stop; + end + + if( widthad <= 0 ) + begin + $display("Error! Value of widthad parameter must be greater than 0."); + $stop; + end + + if( (match_mode != "SINGLE") && (match_mode != "MULTIPLE") && (match_mode != "FAST_MULTIPLE") ) + begin + $display("Error! Illegal value for match_mode parameter. The value must be SINGLE, MULTIPLE (the default), or FAST_MULTIPLE."); + $stop; + end + + for (i=0; i=0; i=i-1) + if ((i % 2) == 1 ) + begin + mbits_tmp[i-1] = mbits_tmp[i]; + end + else + begin + begin: WWORD_MM1 for (j=0; j "0" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + // "1" ==> "X" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "X" ==> "X" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "U" ==> "0" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + end + end else if (ipattern[i] == 1'b1) + begin + // "0" ==> "X" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + // "X" ==> "X" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "U" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + end + end + end + write0_done <= 1'b1; + write1_done <= 1'b0; + writex_done <= 1'b0; + end + //////////////// + // WRITE_ONES // + //////////////// + if (write1 == 1'b1) + begin + for (i =0; i "0" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + // "1" ==> "U" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b1); + // "X" ==> "0" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + // "U" ==> "U" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b1); + end + end + else if (ipattern[i] == 1'b1) + begin + // "0" ==> "U" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + // "X" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + // "U" ==> "U" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b1); + end + end + end + write0_done <= 1'b0; + write1_done <= 1'b1; + writex_done <= 1'b0; + end + ///////////// + // WRITE_X // + ///////////// + if (writex == 1'b1) + begin + for (i =0; i "0" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + // "1" ==> "X" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "X" ==> "X" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "U" ==> "0" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + end + end + else if ((ipattern[i] ^ wrx_int[i]) == 1'b1) + begin + // "0" ==> "X" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + // "X" ==> "X" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "U" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + end + end + end + writex_done <= 1'b1; + write0_done <= 1'b0; + write1_done <= 1'b0; + end + if (wrbusy_int == 1'b1) + begin + write_start_1 <= 1'b1; + write_start <= write_start_1; + end + else + begin + write_start_1 <= 1'b0; + write_start <= 1'b0; + end + end + else + begin // 2 Cycle write + /////////////////// + // 2 CYCLE WRITE // + /////////////////// + ///////////////// + // WRITE_ZEROS // + ///////////////// + if (write0 == 1'b1) + begin + for (i =0; i "0" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + // "1" ==> "X" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "X" ==> "X" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "U" ==> "0" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + end + end + else if (ipattern[i] == 1'b1) + begin + // "0" ==> "X" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + // "X" ==> "X" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b1); + // "U" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + end + end + end + write0_done <= 1'b1; + write1_done <= 1'b0; + writex_done <= 1'b0; + end + //////////////// + // WRITE_ONES // + //////////////// + if (write1 == 1'b1) + begin + for (i =0; i "0" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + // "1" ==> "U" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b1); + // "X" ==> "0" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b0); + write_x_array(addr,i,1'b0); + // "U" ==> "U" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b1); + end + end + else if (ipattern[i] == 1'b1) + begin + // "0" ==> "U" + if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b0)) + begin // "0" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b0)) + begin // "1" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + // "X" ==> "1" + end + else if ((read_cam_array(addr,i)==1'b0 && read_x_array(addr,i)==1'b1)) + begin // "X" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b0); + // "U" ==> "U" + end + else if ((read_cam_array(addr,i)==1'b1 && read_x_array(addr,i)==1'b1)) + begin // "U" + write_cam_array(addr,i,1'b1); + write_x_array(addr,i,1'b1); + end + end + end + write0_done <= 1'b0; + write1_done <= 1'b1; + writex_done <= 1'b0; + end + + if (wrbusy_int == 1'b1) + begin + write_start <= 1'b1; + end + else + begin + write_start <= 1'b0; + end + end // wrxused_int + end + else + begin // if (wrdelete == 1'b1) begin + //////////////////// + // 2 CYCLE DELETE // + //////////////////// + // Delete is a 2-cycle write + //////////////// + // WRITE_ONES // + //////////////// + if (write0 == 1'b1) + begin + for (i =0; i=0; i=i-1) + if ((i % 2) == 1 ) + begin + mbits_tmp[i-1] = mbits_tmp[i]; + end + else + begin + begin: WWORD_MM3 for (j=0; j 0) + begin + mfound_int <= 1'b1; + end + else + begin + mfound_int <= 1'b0; + maddress_int <= word_1; + end + end + mcount_int <= count; + mbits_int <= mbits_tmp; + end + + ///////////////////////////////// + // SINGLE: READ ON NEW PATTERN // + ///////////////////////////////// + if (match_mode == "SINGLE") + begin + mbits_tmp = numwords_0; + index = 0; + count = 0; + begin: MADDR_SM1 for (k=0; k "0" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + // "1" ==> "X" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "X" ==> "X" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "U" ==> "0" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + end + end + else if (pattern[k] == 1'b1) + begin + // "0" ==> "X" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + // "X" ==> "X" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "U" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + end + end + end + end + //////////////// + // WRITE_ONES // + //////////////// + if (write1_done == 1'b1) + begin + for (k =0; k "0" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + // "1" ==> "U" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b1); + // "X" ==> "0" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + // "U" ==> "U" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b1); + end + end + else if (pattern[k] == 1'b1) + begin + // "0" ==> "U" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + // "X" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + // "U" ==> "U" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b1); + end + end + end + end + ///////////// + // WRITE_X // + ///////////// + if (writex_done == 1'b1) + begin + for (k =0; k "0" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + // "1" ==> "X" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "X" ==> "X" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "U" ==> "0" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + end + end + else if ((pattern[k] ^ wrx_int[k]) == 1'b1) + begin + // "0" ==> "X" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + // "X" ==> "X" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "U" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + end + end + end + end + end + else + begin // 2 Cycle write + /////////////////// + // 2 CYCLE WRITE // + /////////////////// + ///////////////// + // WRITE_ZEROS // + ///////////////// + if (write0_done == 1'b1) + begin + for (k =0; k "0" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + // "1" ==> "X" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "X" ==> "X" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "U" ==> "0" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + end + end + else if (pattern[k] == 1'b1) + begin + // "0" ==> "X" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + // "X" ==> "X" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b1); + // "U" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + end + end + end + end + //////////////// + // WRITE_ONES // + //////////////// + if (write1_done == 1'b1) + begin + for (k =0; k "0" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + // "1" ==> "U" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b1); + // "X" ==> "0" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b0); + write_x_array(addr,k,1'b0); + // "U" ==> "U" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b1); + end + end + else if (pattern[k] == 1'b1) + begin + // "0" ==> "U" + if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b0)) + begin // "0" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b1); + // "1" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b0)) + begin // "1" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + // "X" ==> "1" + end + else if ((read_cam_array(addr,k)==1'b0 && read_x_array(addr,k)==1'b1)) + begin // "X" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b0); + // "U" ==> "U" + end + else if ((read_cam_array(addr,k)==1'b1 && read_x_array(addr,k)==1'b1)) + begin // "U" + write_cam_array(addr,k,1'b1); + write_x_array(addr,k,1'b1); + end + end + end + end + end // wrxused_int + end + else + begin // if (wrdelete == 1'b1) begin + //////////////////// + // 2 CYCLE DELETE // + //////////////////// + // Delete is a 2-cycle write + //////////////// + // WRITE_ONES // + //////////////// + if (write0_done == 1'b1) + begin + for (k =0; k=0; k=k-1) + if ((k % 2) == 1 ) + begin + mbits_tmp[k-1] = mbits_tmp[k]; + end + else + begin + begin: WWORD_MM_3 for (j=0; j= + add_reg_b_mult_wb) && + (add_reg_a_mult_wa <= + (add_reg_b_mult_wb_pl_wb - 1))) + + || + + (((add_reg_a_mult_wa_pl_wa - 1) >= + add_reg_b_mult_wb) && + ((add_reg_a_mult_wa_pl_wa - 1) <= + (add_reg_b_mult_wb_pl_wb - 1))) + ) + for (i3 = add_reg_a_mult_wa; + i3 < add_reg_a_mult_wa_pl_wa; + i3 = i3 + 1) + begin + if ((i3 >= add_reg_b_mult_wb) && + (i3 <= (add_reg_b_mult_wb_pl_wb - 1))) + begin + i_q_tmp2_a_idx = (i3 - add_reg_a_mult_wa); + i_q_tmp2_a[i_q_tmp2_a_idx] = 1'bx; + end + end + + end + end + end + end + end + + + // assigning the correct output values for i_q_tmp_a (non-registered output) + always @(i_q_tmp2_a or i_wren_reg_a or i_data_reg_a or + i_address_reg_a or i_byteena_mask_reg_a_out) + begin + + if (i_wren_reg_a) + begin + i_q_tmp_a <= i_data_reg_a ^ i_byteena_mask_reg_a_out; + + end + else + i_q_tmp_a <= i_q_tmp2_a; + + end + + + // Port A outdata output registered + always @(posedge i_outdata_clk_a or posedge i_outdata_aclr_a) + begin + if (i_outdata_aclr_a) + i_q_reg_a <= 0; + else if (i_outdata_clken_a) + i_q_reg_a <= i_q_tmp_a; + end + + + // Port A : assigning the correct output values for q_a + assign q_a = (operation_mode == "DUAL_PORT") ? + {width_a{1'b0}} : (((outdata_reg_a == "CLOCK0") || + (outdata_reg_a == "CLOCK1")) ? + i_q_reg_a : i_q_tmp_a); + + + // Port B reading + always @(posedge i_read_flag_b or negedge i_read_flag_b) + begin + if ((operation_mode == "BIDIR_DUAL_PORT") || + (operation_mode == "DUAL_PORT")) + begin + if (~good_to_go_b) + begin + + if (check_simultaneous_read_write) + i_q_tmp2_b = {width_b{1'bx}}; + else + i_q_tmp2_b = 0; + end + else + begin + if (i_rden_reg_b) + begin + //If width_a is equal to b, no address calculation is needed + if (width_a == width_b) + begin + if (check_simultaneous_read_write) + begin + if ((rdcontrol_reg_b == "CLOCK0") || + (wrcontrol_wraddress_reg_b == "CLOCK0")) + begin + // A write, B read + if (i_wren_reg_a & ~i_wren_reg_b) + begin + // if A write to the same Ram address B is reading from + if (i_address_reg_b == i_address_reg_a) + temp_wb = {width_b{1'bx}}; + else + temp_wb = mem_data[i_address_reg_b]; + + end + else + temp_wb = mem_data[i_address_reg_b]; + end + else + temp_wb = mem_data[i_address_reg_b]; + end + else + temp_wb = mem_data[i_address_reg_b]; + + end + else + begin + j2 = i_address_reg_b * width_b; + + if (check_simultaneous_read_write) + begin + if ((rdcontrol_reg_b == "CLOCK0") || + (wrcontrol_wraddress_reg_b == "CLOCK0")) + begin + // A write, B read + if (i_wren_reg_a & ~i_wren_reg_b) + begin + + for (i5=0; i5 i_*_lo) during falling edge. + always @(negedge i_apex_inclock) + begin + if (indata_reg == "INCLOCK") + begin + if ((aclr == 1) && (indata_aclr_int == "ON")) + i_data_lo <= 0; + else + i_data_lo <= i_data_hi; + end + + if (write_reg == "INCLOCK") + begin + if ((aclr == 1) && (write_aclr_int == "ON")) + begin + i_wraddress_lo <= 0; + i_wren_lo <= 0; + end + else + begin + i_wraddress_lo <= i_wraddress_hi; + i_wren_lo <= i_wren_hi; + end + end + end // End of always block: @(negedge inclock) + + + // At posedge of read clock: + // Read Cycle: This block is valid only if the operating mode is + // in "Seperate Clock Mode". All read data, address + // and control are clocked out from internal vars + // (i_*_reg) to output port. + always @(posedge i_apex_outclock) + begin + if (outdata_reg_a == "OUTCLOCK") + begin + if ((aclr == 1) && (outdata_aclr_a == "ON")) + i_qa_reg <= 0; + else if (outclocken == 1) + i_qa_reg <= i_qa_tmp; + end + + if (outdata_reg_b == "OUTCLOCK") + begin + if ((aclr == 1) && (outdata_aclr_b == "ON")) + i_qb_reg <= 0; + else if (outclocken == 1) + i_qb_reg <= i_qb_tmp; + end + + if (rdaddress_reg_a == "OUTCLOCK") + begin + if ((aclr == 1) && (rdaddress_aclr_a_int == "ON")) + i_rdaddress_reg_a <= 0; + else if (outclocken == 1) + i_rdaddress_reg_a <= rdaddress_a; + end + + if (rdcontrol_reg_a == "OUTCLOCK") + begin + if ((aclr == 1) && (rdcontrol_aclr_a_int == "ON")) + i_rden_reg_a <= 0; + else if (outclocken == 1) + i_rden_reg_a <= rden_a; + end + + if (rdaddress_reg_b == "OUTCLOCK") + begin + if ((aclr == 1) && (rdaddress_aclr_b_int == "ON")) + i_rdaddress_reg_b <= 0; + else if (outclocken == 1) + i_rdaddress_reg_b <= rdaddress_b; + end + + if (rdcontrol_reg_b == "OUTCLOCK") + begin + if ((aclr == 1) && (rdcontrol_aclr_b_int == "ON")) + i_rden_reg_b <= 0; + else if (outclocken == 1) + i_rden_reg_b <= rden_b; + end + end // End of always block: @(posedge outclock) + + always @(i_rdaddress_reg_a) + begin + i_rdaddress_reg_a_dly <= i_rdaddress_reg_a; + end + + always @(i_rdaddress_reg_b) + begin + i_rdaddress_reg_b_dly <= i_rdaddress_reg_b; + end + + //========= + // Memory + //========= + + always @(i_data_tmp or i_wren_tmp or i_wraddress_tmp) + begin + new_data <= 1; + end + + always @(posedge new_data or negedge new_data) + begin + if (new_data == 1) + begin + // + // This is where data is being write to the internal memory: mem_data[] + // + if (i_wren_tmp == 1) + begin + mem_data[i_wraddress_tmp] <= i_data_tmp; + end + + tmp_new_data <= ~tmp_new_data; + + end + end + + always @(tmp_new_data) + begin + + new_data <= 0; + end + + // Triple-Port Ram (alt3pram) has one write port and two read ports (a and b) + // Below is the operation to read data from internal memory (mem_data[]) + // to the output port (i_qa_tmp or i_qb_tmp) + // Note: i_q*_tmp will serve as the var directly link to the physical + // output port q* if alt3pram is operate in "Shared Clock Mode", + // else data read from i_q*_tmp will need to be latched to i_q*_reg + // through outclock before it is fed to the output port q* (qa or qb). + + always @(posedge new_data or negedge new_data or + posedge i_rden_tmp_a or negedge i_rden_tmp_a or + i_rdaddress_tmp_a) + begin + + if (i_rden_tmp_a == 1) + i_qa_tmp <= mem_data[i_rdaddress_tmp_a]; + else if (rden_low_output_0 == 1) + i_qa_tmp <= 0; + + end + + always @(posedge new_data or negedge new_data or + posedge i_rden_tmp_b or negedge i_rden_tmp_b or + i_rdaddress_tmp_b) + begin + + if (i_rden_tmp_b == 1) + i_qb_tmp <= mem_data[i_rdaddress_tmp_b]; + else if (rden_low_output_0 == 1) + i_qb_tmp <= 0; + + end + + + //======= + // Sync + //======= + + assign i_wraddress_reg = ((aclr == 1) && (write_aclr_int == "ON")) ? + 0 : (write_at_low_clock ? + i_wraddress_lo : i_wraddress_hi); + + assign i_wren_reg = ((aclr == 1) && (write_aclr_int == "ON")) ? + 0 : ((write_at_low_clock) ? + i_wren_lo : i_wren_hi); + + assign i_data_reg = ((aclr == 1) && (indata_aclr_int == "ON")) ? + 0 : ((write_at_low_clock) ? + i_data_lo : i_data_hi); + + assign i_wraddress_tmp = ((aclr == 1) && (write_aclr_int == "ON")) ? + 0 : ((write_reg == "INCLOCK") ? + i_wraddress_reg : wraddress); + + assign i_rdaddress_tmp_a = ((aclr == 1) && (rdaddress_aclr_a_int == "ON")) ? + 0 : (((rdaddress_reg_a == "INCLOCK") || + (rdaddress_reg_a == "OUTCLOCK")) ? + i_rdaddress_reg_a_dly : rdaddress_a); + + assign i_rdaddress_tmp_b = ((aclr == 1) && (rdaddress_aclr_b_int == "ON")) ? + 0 : (((rdaddress_reg_b == "INCLOCK") || + (rdaddress_reg_b == "OUTCLOCK")) ? + i_rdaddress_reg_b_dly : rdaddress_b); + + assign i_wren_tmp = ((aclr == 1) && (write_aclr_int == "ON")) ? + 0 : ((write_reg == "INCLOCK") ? + i_wren_reg : wren); + + assign i_rden_tmp_a = ((aclr == 1) && (rdcontrol_aclr_a_int == "ON")) ? + 0 : (((rdcontrol_reg_a == "INCLOCK") || + (rdcontrol_reg_a == "OUTCLOCK")) ? + i_rden_reg_a : rden_a); + + assign i_rden_tmp_b = ((aclr == 1) && (rdcontrol_aclr_b_int == "ON")) ? + 0 : (((rdcontrol_reg_b == "INCLOCK") || + (rdcontrol_reg_b == "OUTCLOCK")) ? + i_rden_reg_b : rden_b); + + assign i_data_tmp = ((aclr == 1) && (indata_aclr_int == "ON")) ? + 0 : ((indata_reg == "INCLOCK") ? + i_data_reg : data); + + assign qa = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 1) || + (dev.IS_FAMILY_STRATIXII(intended_device_family) == 1) || + (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 1) || + (dev.IS_FAMILY_CYCLONE(intended_device_family) == 1)) ? + i_qa_stratix : + (((aclr == 1) && (outdata_aclr_a == "ON")) ? + 0 : ((outdata_reg_a == "OUTCLOCK") ? + i_qa_reg : i_qa_tmp)); + + assign qb = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 1) || + (dev.IS_FAMILY_STRATIXII(intended_device_family) == 1) || + (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 1) || + (dev.IS_FAMILY_CYCLONE(intended_device_family) == 1)) ? + i_qb_stratix : + (((aclr == 1) && (outdata_aclr_b == "ON")) ? + 0 : ((outdata_reg_b == "OUTCLOCK") ? + i_qb_reg : i_qb_tmp)); + + assign i_apex_inclock = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 0) && + (dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && + (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 0) && + (dev.IS_FAMILY_CYCLONE(intended_device_family) == 0)) ? + inclock : 1'b0; + + assign i_apex_outclock = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 0) && + (dev.IS_FAMILY_STRATIXII(intended_device_family) == 0) && + (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 0) && + (dev.IS_FAMILY_CYCLONE(intended_device_family) == 0)) ? + outclock : 1'b0; + + assign i_stratix_inclock = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 1) || + (dev.IS_FAMILY_STRATIXII(intended_device_family) == 1) || + (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 1) || + (dev.IS_FAMILY_CYCLONE(intended_device_family) == 1)) ? + inclock : 1'b0; + + assign i_stratix_outclock = ((dev.IS_FAMILY_STRATIX(intended_device_family) == 1) || + (dev.IS_FAMILY_STRATIXII(intended_device_family) == 1) || + (dev.IS_FAMILY_STRATIXGX(intended_device_family) == 1) || + (dev.IS_FAMILY_CYCLONE(intended_device_family) == 1)) ? + outclock : 1'b0; + + +endmodule // end of ALT3PRAM + +// START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : ALTQPRAM +// +// Description : Asynchronous quad ports memory or memory with synchronous +// inputs and/or outputs +// +// Limitation : +// +// Results expected : [Synchronous Write to Memory (all inputs registered)] +// inclock inclocken wren Function +// X L L No change +// not H H No change +// posedge L X No change +// posedge H H Memory content updated +// +// [Synchronous Read from Memory] +// inclock inclocken rden Function +// X L L No change +// not H H No change +// posedge L X No change. +// posedge H H Memory content showed +// at the output port +// +// [Asynchronous Memory Operations] +// wren Function +// L No change +// H Memory content updated +// Memory content showed +// at the output port +// +// END_MODULE_NAME-------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +// BEGINNING OF MODULE + +// MODULE DECLARATION + +module altqpram ( + wren_a, + wren_b, + data_a, + data_b, + wraddress_a, + wraddress_b, + inclock_a, + inclock_b, + inclocken_a, + inclocken_b, + rden_a, + rden_b, + rdaddress_a, + rdaddress_b, + outclock_a, + outclock_b, + outclocken_a, + outclocken_b, + inaclr_a, + inaclr_b, + outaclr_a, + outaclr_b, + q_a, + q_b + ); + +// GLOBAL PARAMETER DECLARATION + + parameter operation_mode = "QUAD_PORT"; + + // Port A write parameters + parameter width_write_a = 1; + parameter widthad_write_a = 1; + parameter numwords_write_a = 0; + parameter indata_reg_a = "INCLOCK_A"; + parameter indata_aclr_a = "INACLR_A"; + parameter wrcontrol_wraddress_reg_a = "INCLOCK_A"; + parameter wrcontrol_aclr_a = "INACLR_A"; + parameter wraddress_aclr_a = "INACLR_A"; + + // Port B write parameters + parameter width_write_b = 1; + parameter widthad_write_b = 1; + parameter numwords_write_b = 0; + parameter indata_reg_b = "INCLOCK_B"; + parameter indata_aclr_b = "INACLR_B"; + parameter wrcontrol_wraddress_reg_b = "INCLOCK_B"; + parameter wrcontrol_aclr_b = "INACLR_B"; + parameter wraddress_aclr_b = "INACLR_B"; + + // Port A read parameters + parameter width_read_a = 1; + parameter widthad_read_a = 1; + parameter numwords_read_a = 0; + parameter rdcontrol_reg_a = "OUTCLOCK_A"; + parameter rdcontrol_aclr_a = "OUTACLR_A"; + parameter rdaddress_reg_a = "OUTCLOCK_A"; + parameter rdaddress_aclr_a = "OUTACLR_A"; + parameter outdata_reg_a = "UNREGISTERED"; + parameter outdata_aclr_a = "OUTACLR_A"; + + // Port B read parameters + parameter width_read_b = 1; + parameter widthad_read_b = 1; + parameter numwords_read_b = 0; + parameter rdcontrol_reg_b = "OUTCLOCK_B"; + parameter rdcontrol_aclr_b = "OUTACLR_B"; + parameter rdaddress_reg_b = "OUTCLOCK_B"; + parameter rdaddress_aclr_b = "OUTACLR_B"; + parameter outdata_reg_b = "UNREGISTERED"; + parameter outdata_aclr_b = "OUTACLR_B"; + + parameter init_file = "UNUSED"; + parameter lpm_hint = "UNUSED"; + parameter lpm_type = "altqpram"; + +// INPUT PORT DECLARATION + + input wren_a; + input wren_b; + input rden_a; + input rden_b; + input [width_write_a - 1 : 0] data_a; + input [width_write_b - 1 : 0] data_b; + input [widthad_write_a - 1 : 0] wraddress_a; + input [widthad_write_b - 1 : 0] wraddress_b; + input inclock_a; + input inclock_b; + input inclocken_a; + input inclocken_b; + input [widthad_read_a - 1 : 0] rdaddress_a; + input [widthad_read_b - 1 : 0] rdaddress_b; + input outclock_a; + input outclock_b; + input outclocken_a; + input outclocken_b; + input inaclr_a; + input inaclr_b; + input outaclr_a; + input outaclr_b; + +// OUTPUT PORT DECLARATION + + output [width_read_a - 1 : 0] q_a; + output [width_read_b - 1 : 0] q_b; + +// INTERNAL REGISTERS DECLARATION + + reg [width_read_a - 1 : 0] mem_data [0 : (1 << widthad_read_a) - 1]; + reg [width_write_a - 1 : 0] mem_data_w [0 : (1 << widthad_write_a) - 1]; + reg [width_write_a - 1 : 0] i_data_reg_a; + reg [width_write_a - 1 : 0] i_data_tmp_a; + reg [width_write_a - 1 : 0] i_data2_a; + reg [width_write_a - 1 : 0] temp_wa; + reg [width_write_a - 1 : 0] temp_wa2; + reg [width_write_a - 1 : 0] temp_wa3; + reg [width_write_b - 1 : 0] i_data_reg_b; + reg [width_write_b - 1 : 0] i_data_tmp_b; + reg [width_write_b - 1 : 0] i_data2_b; + reg [width_write_a - 1 : 0] i_data_hi_a; + reg [width_write_a - 1 : 0] i_data_lo_a; + reg [width_write_b - 1 : 0] i_data_hi_b; + reg [width_write_b - 1 : 0] i_data_lo_b; + reg [width_read_a - 1 : 0] i_q_reg_a; + reg [width_read_a - 1 : 0] i_q_tmp_a; + reg [width_read_a - 1 : 0] temp_ra; + reg [width_read_a - 1 : 0] temp_ra2; + reg [width_read_a - 1 : 0] temp_ra3; + reg [width_read_a - 1 : 0] temp_ra4; + reg [width_read_b - 1 : 0] i_q_reg_b; + reg [width_read_b - 1 : 0] i_q_tmp_b; + reg [widthad_write_a - 1 : 0] i_wraddress_reg_a; + reg [widthad_write_a - 1 : 0] i_wraddress_tmp_a; + reg [widthad_write_a - 1 : 0] i_wraddress2_a; + reg [widthad_write_b - 1 : 0] i_wraddress_reg_b; + reg [widthad_write_b - 1 : 0] i_wraddress_tmp_b; + reg [widthad_write_b - 1 : 0] i_wraddress2_b; + reg [widthad_write_a - 1 : 0] i_wraddress_hi_a; + reg [widthad_write_a - 1 : 0] i_wraddress_lo_a; + reg [widthad_write_b - 1 : 0] i_wraddress_hi_b; + reg [widthad_write_b - 1 : 0] i_wraddress_lo_b; + reg [widthad_read_a - 1 : 0] i_rdaddress_reg_a; + reg [widthad_read_a - 1 : 0] i_rdaddress_tmp_a; + reg [widthad_read_b - 1 : 0] i_rdaddress_reg_b; + reg [widthad_read_b - 1 : 0] i_rdaddress_tmp_b; + reg [8*256 : 1] ram_initf; + reg i_wren_reg_a; + reg i_wren_tmp_a; + reg i_wren2_a; + reg i_rden_reg_a; + reg i_rden_tmp_a; + reg i_wren_reg_b; + reg i_wren_tmp_b; + reg i_wren2_b; + reg i_rden_reg_b; + reg i_rden_tmp_b; + reg i_wren_hi_a; + reg i_wren_lo_a; + reg i_wren_hi_b; + reg i_wren_lo_b; + reg mem_updated; + reg clk_a_trigger; + reg clk_b_trigger; + reg write_at_low_clock_a; + reg write_at_low_clock_b; + + + wire i_indata_aclr_a; + wire i_wraddress_aclr_a; + wire i_wrcontrol_aclr_a; + wire i_outdata_aclr_a; + wire i_rdaddress_aclr_a; + wire i_rdcontrol_aclr_a; + wire i_indata_aclr_b; + wire i_wraddress_aclr_b; + wire i_wrcontrol_aclr_b; + wire i_outdata_aclr_b; + wire i_rdaddress_aclr_b; + wire i_rdcontrol_aclr_b; + + +// LOCAL INTEGER DECLARATION + + integer i_numwords_read_a; + integer i_numwords_read_b; + integer i_numwords_write_a; + integer i_numwords_write_b; + integer write_ratio; + integer read_ratio; + integer read_write_ratio; + integer i; + integer i2; + integer i3; + integer i4; + integer j; + integer j2; + integer j3; + integer j4; + + integer ja; + integer jb; + integer Pa; + integer Pa1; + integer Pa2; + integer Pb; + integer Pb1; + integer Pb2; + + integer simultaneous_write; + +// INTERNAL TRI DECLARATION + + tri0 wren_a; + tri0 wren_b; + tri1 rden_a; + tri1 rden_b; + tri0 inclock_a; + tri0 inclock_b; + tri0 outclock_a; + tri0 outclock_b; + tri1 inclocken_a; + tri1 inclocken_b; + tri1 outclocken_a; + tri1 outclocken_b; + tri0 inaclr_a; + tri0 inaclr_b; + tri0 outaclr_a; + tri0 outaclr_b; + +// INTERNAL WIRE + + wire i_wren_a; + wire i_wren_b; + wire i_rden_a; + wire i_rden_b; + wire i_inclock_a; + wire i_inclock_b; + wire i_inclocken_a; + wire i_inclocken_b; + wire i_outclock_a; + wire i_outclock_b; + wire i_outclocken_a; + wire i_outclocken_b; + wire i_inaclr_a; + wire i_inaclr_b; + wire i_outaclr_a; + wire i_outaclr_b; + +// INTERNAL BUF + + buf (i_wren_a, wren_a); + buf (i_wren_b, wren_b); + buf (i_rden_a, rden_a); + buf (i_rden_b, rden_b); + buf (i_inclock_a, inclock_a); + buf (i_inclock_b, inclock_b); + buf (i_inclocken_a, inclocken_a); + buf (i_inclocken_b, inclocken_b); + buf (i_outclock_a, outclock_a); + buf (i_outclock_b, outclock_b); + buf (i_outclocken_a, outclocken_a); + buf (i_outclocken_b, outclocken_b); + buf (i_inaclr_a, inaclr_a); + buf (i_inaclr_b, inaclr_b); + buf (i_outaclr_a, outaclr_a); + buf (i_outaclr_b, outaclr_b); + + +// COMPONENT INSTANTIATIONS + ALTERA_MF_MEMORY_INITIALIZATION mem (); + +// INITIAL CONSTRUCT BLOCK + + initial + begin + + // Check for invalid parameters + + if ((operation_mode != "QUAD_PORT") && (operation_mode != "BIDIR_DUAL_PORT") && + (operation_mode != "DUAL_PORT") && (operation_mode != "SINGLE_PORT") && + (operation_mode != "ROM")) + begin + $display("Error! operation_mode parameter is invalid."); + $stop; + end + + if ((width_write_a <= 0) && (operation_mode != "ROM")) + begin + $display("Error! width_write_a parameter must be greater than 0."); + $stop; + end + + if ((width_write_b <= 0) && ((operation_mode == "QUAD_PORT") || (operation_mode == "BIDIR_DUAL_PORT"))) + begin + $display("Error! width_write_b parameter must be greater than 0."); + $stop; + end + + if ((widthad_write_a <= 0) && (operation_mode != "ROM")) + begin + $display("Error! widthad_write_a parameter must be greater than 0."); + $stop; + end + + if ((widthad_write_b <= 0) && ((operation_mode == "QUAD_PORT") || (operation_mode == "BIDIR_DUAL_PORT"))) + begin + $display("Error! widthad_write_b parameter must be greater than 0."); + $stop; + end + + if ((width_read_a <= 0) && ((operation_mode == "QUAD_PORT") || (operation_mode == "DUAL_PORT"))) + begin + $display("Error! width_read_a parameter must be greater than 0."); + $stop; + end + + if ((width_read_b <= 0) && (operation_mode == "QUAD_PORT")) + begin + $display("Error! width_read_b parameter must be greater than 0."); + $stop; + end + + if ((widthad_read_a <= 0) && ((operation_mode == "QUAD_PORT") || (operation_mode == "DUAL_PORT"))) + begin + $display("Error! widthad_read_a parameter must be greater than 0."); + $stop; + end + + if ((widthad_read_b <= 0) && (operation_mode == "QUAD_PORT")) + begin + $display("Error! widthad_read_b parameter must be greater than 0."); + $stop; + end + + if (((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT")) && (width_read_a != width_write_a)) + begin + $display("Error! width_read_a must equal width_write_a."); + $stop; + end + + if ((operation_mode == "BIDIR_DUAL_PORT") && (width_read_b != width_write_b)) + begin + $display("Error! width_read_b must equal width_write_b."); + $stop; + end + + i_numwords_read_a = (numwords_read_a) ? numwords_read_a : (1 << widthad_read_a); + i_numwords_read_b = (numwords_read_b) ? numwords_read_b : (1 << widthad_read_b); + i_numwords_write_a =(numwords_write_a) ? + numwords_write_a : (1 << widthad_write_a); + i_numwords_write_b =(numwords_write_b) ? + numwords_write_b : (1 << widthad_write_b); + + if ((width_read_a*i_numwords_read_a != width_write_a*i_numwords_write_a) && + ((operation_mode == "QUAD_PORT") || (operation_mode == "DUAL_PORT"))) + begin + $display("Error! RAM size for port A is inconsistant."); + $stop; + end + + if ((operation_mode == "QUAD_PORT") || (operation_mode == "BIDIR_DUAL_PORT")) + begin + if ((width_read_b * i_numwords_read_b) != (width_write_b * i_numwords_write_b)) + begin + $display("Error! RAM size for port B is inconsistant."); + $stop; + end + + if (width_read_a*i_numwords_read_a != width_read_b*i_numwords_read_b) + begin + $display("Error! RAM size between port A and port B is inconsistant."); + $stop; + end + end + + read_ratio = (width_read_a > width_read_b) ? + (width_read_a / width_read_b) + : (width_read_b / width_read_a); + write_ratio = (width_write_a > width_write_b) ? + (width_write_a / width_write_b) + : (width_write_b / width_write_a); + read_write_ratio = (width_read_a > width_write_a) ? + (width_read_a / width_write_a) + : (width_write_a / width_read_a); + + // reset unused ratios to avoid incorrect checking + if ((operation_mode != "QUAD_PORT") || (operation_mode != "BIDIR_DUAL_MODE")) + begin + read_ratio = 1; + write_ratio = 1; + end + + if (((read_ratio != 1) && (read_ratio != 2) && (read_ratio != 4) && + (read_ratio != 8) && (read_ratio != 16)) || + ((write_ratio != 1) && (write_ratio != 2) && (write_ratio != 4) && + (write_ratio != 8) && (write_ratio != 16)) || + ((read_write_ratio != 1) && (read_write_ratio != 2) && + (read_write_ratio != 4) && (read_write_ratio != 8) && + (read_write_ratio != 16))) + begin + $display("Error! RAM size for port A and / or port B is invalid."); + $stop; + end + + // Initialize mem_data + if ((init_file == "UNUSED") || (init_file == "")) + begin + if (operation_mode == "ROM") + begin + $display("Error! altqpram needs data file for memory initialization.\n"); + $stop; + end + else if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT")) + for (i = 0; i < i_numwords_write_a; i = i + 1) + mem_data_w[i] = 0; + else // if QP or DP mode + for (i = 0; i < i_numwords_read_a; i = i + 1) + mem_data[i] = 0; + end + else + begin + if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT")) + begin +`ifdef NO_PLI + $readmemh(init_file, mem_data_w); +`else + `ifdef USE_RIF + $readmemh(init_file, mem_data_w); + `else + mem.convert_hex2ver(init_file, width_write_a, ram_initf); + $readmemh(ram_initf, mem_data_w); + `endif +`endif + end + else // if ROM, QP or DP mode + begin +`ifdef NO_PLI + $readmemh(init_file, mem_data); +`else + `ifdef USE_RIF + $readmemh(init_file, mem_data); + `else + mem.convert_hex2ver(init_file, width_read_a, ram_initf); + $readmemh(ram_initf, mem_data); + `endif +`endif + end + end + + mem_updated <= 0; + write_at_low_clock_a <= (wrcontrol_wraddress_reg_a != "UNREGISTERED") ? + 1 : 0; + write_at_low_clock_b <= (wrcontrol_wraddress_reg_b != "UNREGISTERED") ? + 1 : 0; + + // Initialize registers + i_data_reg_a <= 0; + i_data_tmp_a <= 0; + i_data_reg_b <= 0; + i_data_tmp_b <= 0; + i_data_hi_a <= 0; + i_data_lo_a <= 0; + i_data_hi_b <= 0; + i_data_lo_b <= 0; + i_wraddress_reg_a <= 0; + i_wraddress_tmp_a <= 0; + i_wraddress_reg_b <= 0; + i_wraddress_tmp_b <= 0; + i_wraddress_reg_b <= 0; + i_wraddress_tmp_b <= 0; + i_wraddress_hi_a <= 0; + i_wraddress_lo_a <= 0; + i_wraddress_hi_b <= 0; + i_wraddress_lo_b <= 0; + i_rdaddress_reg_a <= 0; + i_rdaddress_tmp_a <= 0; + i_rdaddress_reg_b <= 0; + i_rdaddress_tmp_b <= 0; + i_wren_reg_a <= 0; + i_wren_tmp_a <= 0; + i_wren_hi_a <= 0; + i_wren_lo_a <= 0; + i_rden_reg_a <= 0; + i_rden_tmp_a <= 0; + i_wren_reg_b <= 0; + i_wren_tmp_b <= 0; + i_wren_hi_b <= 0; + i_wren_lo_b <= 0; + i_rden_reg_b <= 0; + i_rden_tmp_b <= 0; + i_q_reg_a <= 0; + i_q_tmp_a <= 0; + i_q_reg_b <= 0; + i_q_tmp_b <= 0; + + i_data2_a <= 0; + i_wren2_a <= 0; + i_wraddress2_a <= 0; + i_data2_b <= 0; + i_wren2_b <= 0; + i_wraddress2_b <= 0; + clk_a_trigger <= 0; + clk_b_trigger <= 0; + end + + + assign i_indata_aclr_a = (indata_aclr_a == "INACLR_A") ? + i_inaclr_a : 0; + + assign i_wraddress_aclr_a = (wraddress_aclr_a == "INACLR_A") ? + i_inaclr_a : 0; + + assign i_wrcontrol_aclr_a = (wrcontrol_aclr_a == "INACLR_A") ? + i_inaclr_a : 0; + + assign i_outdata_aclr_a = ((outdata_aclr_a == "INACLR_A") ? i_inaclr_a : + ((outdata_aclr_a == "OUTACLR_A") ? i_outaclr_a : 0)); + + assign i_rdaddress_aclr_a = ((rdaddress_aclr_a == "INACLR_A") ? i_inaclr_a : + ((rdaddress_aclr_a == "OUTACLR_A") ? i_outaclr_a : 0)); + + assign i_rdcontrol_aclr_a = ((rdcontrol_aclr_a == "INACLR_A") ? i_inaclr_a : + ((rdcontrol_aclr_a == "OUTACLR_A") ? i_outaclr_a : 0)); + + assign i_indata_aclr_b = (indata_aclr_b == "INACLR_B") ? + i_inaclr_b : 0; + + assign i_wraddress_aclr_b = (wraddress_aclr_b == "INACLR_B") ? + i_inaclr_b : 0; + + assign i_wrcontrol_aclr_b = (wrcontrol_aclr_b == "INACLR_B") ? + i_inaclr_b : 0; + + assign i_outdata_aclr_b = ((outdata_aclr_b == "INACLR_B") ? i_inaclr_b : + ((outdata_aclr_b == "OUTACLR_B") ? i_outaclr_b : 0)); + + assign i_rdaddress_aclr_b = ((rdaddress_aclr_b == "INACLR_B") ? i_inaclr_b : + ((rdaddress_aclr_b == "OUTACLR_B") ? i_outaclr_b : 0)); + + assign i_rdcontrol_aclr_b = ((rdcontrol_aclr_b == "INACLR_B") ? i_inaclr_b : + ((rdcontrol_aclr_b == "OUTACLR_B") ? i_outaclr_b : 0)); + + + + // This always block is to handle registered inputs and output for port A + always @(posedge i_inclock_a) + begin + if (i_indata_aclr_a === 1) + i_data_hi_a <= 0; + else if (i_inclocken_a == 1) + i_data_hi_a <= data_a; + + if (i_wraddress_aclr_a === 1) + i_wraddress_hi_a <= 0; + else if (i_inclocken_a == 1) + i_wraddress_hi_a <= wraddress_a; + + if (i_wrcontrol_aclr_a === 1) + i_wren_hi_a <= 0; + else if (i_inclocken_a == 1) + i_wren_hi_a <= i_wren_a; + + if (outdata_reg_a == "INCLOCK_A") + begin + if (i_outdata_aclr_a === 1) + i_q_reg_a <= 0; + else if (i_inclocken_a == 1) + i_q_reg_a <= i_q_tmp_a; + end + + if (rdaddress_reg_a == "INCLOCK_A") + begin + if (i_rdaddress_aclr_a === 1) + i_rdaddress_reg_a <= 0; + else if (i_inclocken_a == 1) + i_rdaddress_reg_a <= rdaddress_a; + end + + if (rdcontrol_reg_a == "INCLOCK_A") + begin + if (i_rdcontrol_aclr_a === 1) + i_rden_reg_a <= 0; + else if (i_inclocken_a == 1) + i_rden_reg_a <= i_rden_a; + end + end + + // This always block is to handle registered inputs and output for port B + always @(posedge i_inclock_b) + begin + if (i_indata_aclr_b === 1) + i_data_hi_b <= 0; + else if (i_inclocken_b == 1) + i_data_hi_b <= data_b; + + if (i_wraddress_aclr_b === 1) + i_wraddress_hi_b <= 0; + else if (i_inclocken_b == 1) + i_wraddress_hi_b <= wraddress_b; + + if (i_wrcontrol_aclr_b === 1) + i_wren_hi_b <= 0; + else if (i_inclocken_b == 1) + i_wren_hi_b <= i_wren_b; + + if (outdata_reg_b == "INCLOCK_B") + begin + if (i_outdata_aclr_b === 1) + i_q_reg_b <= 0; + else if (i_inclocken_b == 1) + i_q_reg_b <= i_q_tmp_b; + end + + if (rdaddress_reg_b == "INCLOCK_B") + begin + if (i_rdaddress_aclr_b === 1) + i_rdaddress_reg_b <= 0; + else if (i_inclocken_b == 1) + i_rdaddress_reg_b <= rdaddress_b; + end + + if (rdcontrol_reg_b == "INCLOCK_B") + begin + if (i_rdcontrol_aclr_b === 1) + i_rden_reg_b <= 0; + else if (i_inclocken_b == 1) + i_rden_reg_b <= i_rden_b; + end + end + + + // This always block is to handle registered inputs for port A + // for negative clock edge + always @(negedge i_inclock_a) + begin + if (i_indata_aclr_a) + i_data_lo_a <= 0; + else + i_data_lo_a <= i_data_hi_a; + + if (i_wraddress_aclr_a) + i_wraddress_lo_a <= 0; + else + i_wraddress_lo_a <= i_wraddress_hi_a; + + if (i_wrcontrol_aclr_a) + i_wren_lo_a <= 0; + else + i_wren_lo_a <= i_wren_hi_a; + + clk_a_trigger <= 1; + end + + + // This process is to handle registered inputs for port B + // for negative clock edge + always @(negedge i_inclock_b) + begin + if (i_indata_aclr_b) + i_data_lo_b <= 0; + else + i_data_lo_b <= i_data_hi_b; + + if (i_wraddress_aclr_b) + i_wraddress_lo_b <= 0; + else + i_wraddress_lo_b <= i_wraddress_hi_b; + + if (i_wrcontrol_aclr_b) + i_wren_lo_b <= 0; + else + i_wren_lo_b <= i_wren_hi_b; + + clk_b_trigger <= 1; + end + + + // This process is to handle registered outputs for port A + always @(posedge i_outclock_a) + begin + if (outdata_reg_a == "OUTCLOCK_A") + begin + if (i_outdata_aclr_a) + i_q_reg_a <= 0; + else if (i_outclocken_a == 1) + i_q_reg_a <= i_q_tmp_a; + end + + if (rdaddress_reg_a == "OUTCLOCK_A") + begin + if (i_rdaddress_aclr_a) + i_rdaddress_reg_a <= 0; + else if (i_outclocken_a == 1) + i_rdaddress_reg_a <= rdaddress_a; + end + + if (rdcontrol_reg_a == "OUTCLOCK_A") + begin + if (i_rdcontrol_aclr_a) + i_rden_reg_a <= 0; + else if (i_outclocken_a == 1) + i_rden_reg_a <= i_rden_a; + end + end + + + // This process is to handle registered outputs for port B + always @(posedge i_outclock_b) + begin + if (outdata_reg_b == "OUTCLOCK_B") + begin + if (i_outdata_aclr_b) + i_q_reg_b <= 0; + else if (i_outclocken_b == 1) + i_q_reg_b <= i_q_tmp_b; + end + + if (rdaddress_reg_b == "OUTCLOCK_B") + begin + if (i_rdaddress_aclr_b) + i_rdaddress_reg_b <= 0; + else if (i_outclocken_b == 1) + i_rdaddress_reg_b <= rdaddress_b; + end + + if (rdcontrol_reg_b == "OUTCLOCK_B") + begin + if (i_rdcontrol_aclr_b) + i_rden_reg_b <= 0; + else if (i_outclocken_b == 1) + i_rden_reg_b <= i_rden_b; + end + end + + + // This always block is to update the memory contents with 'X' when both ports intend to + // write at the same location + always @(i_data_tmp_a or i_wren_tmp_a or i_wraddress_tmp_a or i_data_tmp_b or + i_wren_tmp_b or i_wraddress_tmp_b or write_at_low_clock_a or write_at_low_clock_b or + i_inclock_a or i_inclock_b) + begin + + if ((write_at_low_clock_a ==1) && (write_at_low_clock_b == 1)) + begin + if ((clk_a_trigger ==1) && (clk_b_trigger ==1)) + simultaneous_write = 1; + else + simultaneous_write = 0; + end + else + simultaneous_write = 1; + + if ((i_wren_tmp_a == 1) && (i_wren_tmp_b == 1 ) && + (i_inclock_a == 0 ) && (i_inclock_b == 0 ) && + (simultaneous_write == 1) && + ((operation_mode == "QUAD_PORT") || (operation_mode == "BIDIR_DUAL_PORT"))) + begin + simultaneous_write = 0; + + if (operation_mode == "BIDIR_DUAL_PORT") + begin + for (jb = 0; jb < width_write_b; jb = jb + 1) + begin + Pa = ((i_wraddress_tmp_a * width_write_a) + jb) % width_write_a; + Pb = ((i_wraddress_tmp_b * width_write_b) + jb) / width_write_a; + + if ((i_wraddress_tmp_a == Pb) && (Pa < width_write_a)) + begin + temp_wa3 = mem_data_w[i_wraddress_tmp_a]; + temp_wa3[Pa] = 1'bx; + mem_data_w[i_wraddress_tmp_a] = temp_wa3; + simultaneous_write = 1; + end + end + end + else // QP mode + begin + for (ja = 0; ja < width_write_a; ja = ja + 1) + begin + for (jb = 0; jb < width_write_b; jb = jb + 1) + begin + Pa1 = ((i_wraddress_tmp_a * width_write_a) + ja) / width_read_a; + Pa2 = ((i_wraddress_tmp_a * width_write_a) + ja) % width_read_a; + Pb1 = ((i_wraddress_tmp_b * width_write_b) + jb) / width_read_a; + Pb2 = ((i_wraddress_tmp_b * width_write_b) + jb) % width_read_a; + + if ((Pa1 == Pb1) && (Pa2 == Pb2)) + begin + temp_ra4 = mem_data[Pa1]; + temp_ra4[Pa2] = 1'b X; + mem_data[Pa1] = temp_ra4; + simultaneous_write = 1; + end + end + end + end + end + else + simultaneous_write = 0; + + if (simultaneous_write == 1) + mem_updated = ~mem_updated; + else + begin + i_data2_a = i_data_tmp_a; + i_wren2_a = i_wren_tmp_a; + i_wraddress2_a = i_wraddress_tmp_a; + i_data2_b = i_data_tmp_b; + i_wren2_b = i_wren_tmp_b; + i_wraddress2_b = i_wraddress_tmp_b; + end + + clk_a_trigger = 0; + clk_b_trigger = 0; + end + + + // This always block is to update the memory contents by port A + always @(i_data2_a or i_wren2_a or i_wraddress2_a or i_wraddress_lo_a or i_wren_lo_a or i_inclock_a) + begin + j4 = i_wraddress2_a * width_write_a; + + if ((i_wren2_a == 1) && (i_inclock_a == 0) && + (operation_mode != "ROM")) + begin + if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT")) + mem_data_w[i_wraddress2_a] = i_data2_a; + else // QP or DP mode + for (i4 = 0; i4 < width_write_a; i4 = i4 + 1) + begin + temp_ra3 = mem_data[(j4+i4)/width_read_a]; + temp_ra3[(j4+i4)%width_read_a] = i_data2_a[i4]; + mem_data[(j4+i4)/width_read_a] = temp_ra3; + end + + mem_updated = ~mem_updated; + end + end + + + // This always block is to update the memory contents by port B + always @(i_data2_b or i_wren2_b or i_wraddress2_b or i_wraddress_lo_b or i_wren_lo_b or i_inclock_b) + begin + j3 = i_wraddress2_b * width_write_b; + + if ((i_wren2_b == 1) && (i_inclock_b == 0) && + ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "QUAD_PORT"))) + begin + if (operation_mode == "BIDIR_DUAL_PORT") + for (i3 = 0; i3 < width_write_b; i3 = i3 + 1) + begin + temp_wa2 = mem_data_w[(j3+i3)/width_write_a]; + temp_wa2[(j3+i3)%width_write_a] = i_data2_b[i3]; + mem_data_w[(j3+i3)/width_write_a] = temp_wa2; + end + else // QP mode + for (i3 = 0; i3 < width_write_b; i3 = i3 + 1) + begin + temp_ra2 = mem_data[(j3+i3)/width_read_a]; + temp_ra2[(j3+i3)%width_read_a] = i_data2_b[i3]; + mem_data[(j3+i3)/width_read_a] = temp_ra2; + end + + mem_updated = ~mem_updated; + end + end + + + // This always block is to read the memory content for port A + always @(posedge i_rden_tmp_a or negedge i_rden_tmp_a or + i_rdaddress_tmp_a or + i_wraddress_tmp_a or mem_updated) + begin + if ((operation_mode == "DUAL_PORT") || (operation_mode == "QUAD_PORT")) + begin + if (i_rden_tmp_a == 1) + i_q_tmp_a = mem_data[i_rdaddress_tmp_a]; + end + else if ((operation_mode == "BIDIR_DUAL_PORT") || (operation_mode == "SINGLE_PORT")) + i_q_tmp_a = mem_data_w[i_wraddress_tmp_a]; + else if (operation_mode == "ROM") + i_q_tmp_a = mem_data[i_rdaddress_tmp_a]; + end + + // This always block is to read the memory content for port A + always @(posedge i_rden_tmp_b or negedge i_rden_tmp_b or + i_rdaddress_tmp_b or + i_wraddress_tmp_b or + mem_updated) + begin + if (operation_mode == "QUAD_PORT") + begin + j2 = i_rdaddress_tmp_b * width_read_b; + if (i_rden_tmp_b == 1) + for (i2 = 0; i2 < width_read_b; i2 = i2 + 1) + begin + temp_ra = mem_data[(j2+i2)/width_read_a]; + i_q_tmp_b[i2] = temp_ra[(j2+i2)%width_read_a]; + end + end + else if (operation_mode == "BIDIR_DUAL_PORT") + begin + j2 = i_wraddress_tmp_b * width_write_b; + for (i2=0; i2 `max_precision) + $display ("Error! WIDTHR must not exceed WIDTH+SIZE+SHIFT*(SIZE-1)."); + if (size < 2) + $display ("Error! SIZE must be greater than 1."); + + if (shift == 0) + begin + best_result_width = width; + if (size > 1) + best_result_width = best_result_width + ceil_log2(size); + end + else + best_result_width = ceil_log2( ((1<> (ni * width)); + + // If signed and negative, pad MSB with ones to sign extend the input data + if ((representation != "UNSIGNED") && (idata_word[width-1] == 1'b1)) + idata_extended = ({{(`max_precision-width-2){1'b1}}, idata_word} << (shift*ni)); + else + idata_extended = (idata_word << (shift*ni)); // zero padding is automatic + + // Add to total + if ((msw_subtract == "YES") && (ni == (size-1))) + tmp_result = tmp_result - idata_extended; + else + tmp_result = tmp_result + idata_extended; + end + end + + // Pipeline model + always @(posedge clock or posedge aclr) + begin + if (aclr == 1'b1) + begin + // Clear the pipeline array + for (ni=0; ni< (pipeline +1); ni=ni+1) + resultpipe[ni] <= 0; + pipe_ptr <= 0; + end + else if (clken_int == 1'b1) + begin + resultpipe[pipe_ptr] <= aligned_result; + if (pipeline > 1) + pipe_ptr <= (pipe_ptr + 1) % pipeline; + end + end + + // Check if output needs MSB alignment + assign aligned_result = (imsb_align == 1) + ? (tmp_result >> (best_result_width-widthr)) + : tmp_result; + assign clken_int = clken; + assign result = (pipeline > 0) ? resultpipe[pipe_ptr] : aligned_result; +endmodule // end of PARALLEL_ADD +// END OF MODULE +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : scfifo +// +// Description : Single Clock FIFO +// +// Limitation : USE_EAB=OFF is not supported +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module scfifo ( data, + clock, + wrreq, + rdreq, + aclr, + sclr, + q, + usedw, + full, + empty, + almost_full, + almost_empty); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_widthu = 1; + parameter lpm_numwords = 2; + parameter lpm_showahead = "OFF"; + parameter lpm_type = "scfifo"; + parameter lpm_hint = "USE_EAB=ON"; + parameter intended_device_family = "APEX20KE"; + parameter underflow_checking = "ON"; + parameter overflow_checking = "ON"; + parameter allow_rwcycle_when_full = "OFF"; + parameter use_eab = "ON"; + parameter add_ram_output_register = "OFF"; + parameter almost_full_value = 0; + parameter almost_empty_value = 0; + parameter maximum_depth = 0; + parameter showahead_area = ((lpm_showahead == "ON") && (add_ram_output_register == "OFF")); + parameter showahead_speed = ((lpm_showahead == "ON") && (add_ram_output_register == "ON")); + parameter legacy_speed = ((lpm_showahead == "OFF") && (add_ram_output_register == "ON")); + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input clock; + input wrreq; + input rdreq; + input aclr; + input sclr; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + output [lpm_widthu-1:0] usedw; + output full; + output empty; + output almost_full; + output almost_empty; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] mem_data [(1< (1 << lpm_widthu))) + $display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU)."); + if (lpm_numwords <= (1 << (lpm_widthu - 1))) + $display ("Error! LPM_WIDTHU is too big for the specified LPM_NUMWORDS."); + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF")) + $display ("Error! add_ram_output_register must be ON or OFF."); + + for (i = 0; i < (1< 0) + almost_full_flag <= 1'b0; + if (almost_empty_value > 0) + almost_empty_flag <= 1'b1; + + write_id <= 0; + + if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed))) + begin + write_latency1 <= 1'bx; + write_latency2 <= 1'bx; + data_shown <= {lpm_width{1'b0}}; + tmp_q <= {lpm_width{1'bX}}; + end + end + else + begin + if (sclr) + begin + tmp_q <= {lpm_width{1'bX}}; + + read_id <= 0; + count_id <= 0; + full_flag <= 1'b0; + empty_flag <= 1'b1; + empty_latency1 <= 1'b1; + empty_latency2 <= 1'b1; + set_q_to_x <= 1'b0; + wrt_count <= 0; + + if (almost_full_value > 0) + almost_full_flag <= 1'b0; + if (almost_empty_value > 0) + almost_empty_flag <= 1'b1; + + if (!stratix_family) + begin + if (valid_wreq) + begin + write_flag <= 1'b1; + end + else + write_id <= 0; + end + else + begin + write_id <= 0; + end + + if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed))) + begin + write_latency1 <= 1'bx; + write_latency2 <= 1'bx; + data_shown <= {lpm_width{1'b0}}; + tmp_q <= {lpm_width{1'bX}}; + end + end + else + begin + // WRITE operation + if (valid_wreq) + begin + if ((overflow_checking == "OFF" && full_flag && !valid_rreq) || set_q_to_x) + begin + tmp_q <= {lpm_width{1'bX}}; + set_q_to_x <= 1'b1; + end + else + begin + mem_data[write_id] <= data; + write_flag <= 1'b1; + + if (!((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area || legacy_speed))) + begin + empty_flag <= 1'b0; + end + else + begin + empty_latency1 <= 1'b0; + end + + if (!valid_rreq) + wrt_count <= wrt_count + 1; + + if (!valid_rreq) + begin + if (count_id >= (1 << lpm_widthu) - 1) + count_id <= 0; + else + count_id <= count_id + 1; + end + else + begin + if (allow_rwcycle_when_full == "OFF") + full_flag <= 1'b0; + end + + if (!(stratix_family) || (stratix_family && !(showahead_speed || showahead_area || legacy_speed))) + begin + if (!valid_rreq) + if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0)) + full_flag <= 1'b1; + end + else + begin + if (!valid_rreq) + if (count_id == lpm_numwords - 1) + full_flag <= 1'b1; + end + + if (lpm_showahead == "ON") + begin + if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area)) + begin + write_latency1 <= write_id; + data_shown[write_id] <= 1'b1; + data_ready[write_id] <= 1'bx; + end + else + begin + if ((use_eab == "OFF") && stratix_family && (count_id == 0)) + begin + tmp_q <= data; + end + else + begin + if ((!empty_flag) && (!valid_rreq)) + begin + tmp_q <= mem_data[read_id]; + end + end + end + end + else + begin + if ((use_eab == "ON") && stratix_family && legacy_speed) + begin + write_latency1 <= write_id; + data_shown[write_id] <= 1'b1; + data_ready[write_id] <= 1'bx; + end + end + end + end + //READ operation + if (valid_rreq) + begin + if (!(set_q_to_x)) + begin + if (!valid_wreq) + wrt_count <= wrt_count - 1; + + if (!valid_wreq) + begin + full_flag <= 1'b0; + + if (count_id <= 0) + count_id <= ((1 << lpm_widthu) - 1); + else + count_id <= count_id - 1; + end + + if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area || legacy_speed)) + begin + if ((wrt_count == 1 && valid_rreq && !valid_wreq) || ((wrt_count == 1 ) && valid_wreq && valid_rreq)) + begin + empty_flag <= 1'b1; + end + else + begin + if (showahead_speed) + begin + if (data_shown[write_latency2] == 1'b0) + begin + empty_flag <= 1'b1; + end + end + else if (showahead_area || legacy_speed) + begin + if (data_shown[write_latency1] == 1'b0) + begin + empty_flag <= 1'b1; + end + end + end + end + else + begin + if (!valid_wreq) + begin + if ((count_id == 1) && !(full_flag)) + empty_flag <= 1'b1; + end + end + + if (empty_flag) + begin + tmp_q <= {lpm_width{1'bX}}; + end + else if (read_id >= ((1<= ((1< almost_full_value) + begin + if (almost_full_flag) + begin + if ((count_id == almost_full_value) && !wrreq && rdreq) + almost_full_flag <= 1'b0; + end + else + begin + if ((almost_full_value == 1) && (count_id == 0) && wrreq) + almost_full_flag <= 1'b1; + else if ((almost_full_value > 1) && (count_id == almost_full_value - 1) + && wrreq && !rdreq) + almost_full_flag <= 1'b1; + end + end + + if (almost_empty_value == 0) + almost_empty_flag <= 1'b0; + else if (lpm_numwords > almost_empty_value) + begin + if (almost_empty_flag) + begin + if ((almost_empty_value == 1) && (count_id == 0) && wrreq) + almost_empty_flag <= 1'b0; + else if ((almost_empty_value > 1) && (count_id == almost_empty_value - 1) + && wrreq && !rdreq) + almost_empty_flag <= 1'b0; + end + else + begin + if ((count_id == almost_empty_value) && !wrreq && rdreq) + almost_empty_flag <= 1'b1; + end + end + end + + if ((use_eab == "ON") && stratix_family) + begin + if (showahead_speed) + begin + write_latency2 <= write_latency1; + write_latency3 <= write_latency2; + if (write_latency3 !== write_latency2) + data_ready[write_latency2] <= 1'b1; + + empty_latency2 <= empty_latency1; + + if (data_shown[write_latency2]==1'b1) + begin + if ((read_id == write_latency2) || aclr || sclr) + begin + if (!(aclr === 1'b1) && !(sclr === 1'b1)) + begin + if (write_latency2 !== 1'bx) + begin + tmp_q <= mem_data[write_latency2]; + data_shown[write_latency2] <= 1'b0; + data_ready[write_latency2] <= 1'b0; + + if (!valid_rreq) + empty_flag <= empty_latency2; + end + end + end + end + end + else if (showahead_area) + begin + write_latency2 <= write_latency1; + if (write_latency2 !== write_latency1) + data_ready[write_latency1] <= 1'b1; + + if (data_shown[write_latency1]==1'b1) + begin + if ((read_id == write_latency1) || aclr || sclr) + begin + if (!(aclr === 1'b1) && !(sclr === 1'b1)) + begin + if (write_latency1 !== 1'bx) + begin + tmp_q <= mem_data[write_latency1]; + data_shown[write_latency1] <= 1'b0; + data_ready[write_latency1] <= 1'b0; + + if (!valid_rreq) + begin + empty_flag <= empty_latency1; + end + end + end + end + end + end + else + begin + if (legacy_speed) + begin + write_latency2 <= write_latency1; + if (write_latency2 !== write_latency1) + data_ready[write_latency1] <= 1'b1; + + empty_flag <= empty_latency1; + + if ((wrt_count == 1 && !valid_wreq && valid_rreq) || aclr || sclr) + begin + empty_flag <= 1'b1; + empty_latency1 <= 1'b1; + end + else + begin + if ((wrt_count == 1) && valid_wreq && valid_rreq) + begin + empty_flag <= 1'b1; + end + end + end + end + end + end + end + + always @(negedge clock) + begin + if (write_flag) + begin + write_flag <= 1'b0; + + if (sclr || aclr || (write_id >= ((1 << lpm_widthu) - 1))) + write_id <= 0; + else + write_id <= write_id + 1; + end + + if (!(stratix_family)) + begin + if (!empty) + begin + if ((lpm_showahead == "ON") && ($time > 0)) + tmp_q <= mem_data[read_id]; + end + end + end + + always @(full_flag) + begin + if (lpm_numwords == almost_full_value) + if (full_flag) + almost_full_flag <= 1'b1; + else + almost_full_flag <= 1'b0; + + if (lpm_numwords == almost_empty_value) + if (full_flag) + almost_empty_flag <= 1'b0; + else + almost_empty_flag <= 1'b1; + end + +// CONTINOUS ASSIGNMENT + assign q = tmp_q; + assign full = full_flag; + assign empty = empty_flag; + assign usedw = count_id; + assign almost_full = almost_full_flag; + assign almost_empty = almost_empty_flag; + +endmodule // scfifo +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : dcfifo_dffpipe +// +// Description : Dual Clocks FIFO +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module dcfifo_dffpipe ( d, clock, aclr, + q); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_delay = 1; + parameter lpm_width = 64; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] d; + input clock; + input aclr; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] dffpipe [lpm_delay:0]; + reg [lpm_width-1:0] q; + +// LOCAL INTEGER DECLARATION + integer delay, i; + +// INITIAL CONSTRUCT BLOCK + initial + begin + delay <= lpm_delay - 1; + for (i = 0; i < lpm_delay; i = i + 1) + dffpipe[i] <= 0; + q <= 0; + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge clock or posedge aclr) + begin + if (aclr) + begin + for (i = 0; i < lpm_delay; i = i + 1) + dffpipe[i] <= 0; + q <= 0; + end + else + begin + if ((lpm_delay > 0) && ($time > 0)) + begin + if (delay > 0) + begin + for (i = delay; i > 0; i = i - 1) + dffpipe[i] <= dffpipe[i - 1]; + q <= dffpipe[delay - 1]; + end + else + q <= d; + + dffpipe[0] <= d; + end + end + end // @(posedge aclr or posedge clock) + + always @(d) + begin + if (lpm_delay == 0) + q <= d; + end // @(d) + +endmodule // dcfifo_dffpipe +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : dcfifo_fefifo +// +// Description : Dual Clock FIFO +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module dcfifo_fefifo ( usedw_in, wreq, rreq, clock, aclr, + empty, full); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_widthad = 1; + parameter lpm_numwords = 1; + parameter underflow_checking = "ON"; + parameter overflow_checking = "ON"; + parameter lpm_mode = "READ"; + +// INPUT PORT DECLARATION + input [lpm_widthad-1:0] usedw_in; + input wreq, rreq; + input clock; + input aclr; + +// OUTPUT PORT DECLARATION + output empty, full; + +// INTERNAL REGISTERS DECLARATION + reg [1:0] sm_empty; + reg lrreq; + reg i_empty, i_full; + +// LOCAL INTEGER DECLARATION + integer almostfull; + +// INITIAL CONSTRUCT BLOCK + initial + begin + if ((lpm_mode != "READ") && (lpm_mode != "WRITE")) + $display ("Error! LPM_MODE must be READ or WRITE."); + if ((underflow_checking != "ON") && (underflow_checking != "OFF")) + $display ("Error! UNDERFLOW_CHECKING must be ON or OFF."); + if ((overflow_checking != "ON") && (overflow_checking != "OFF")) + $display ("Error! OVERFLOW_CHECKING must be ON or OFF."); + + sm_empty <= 2'b00; + i_empty <= 1'b1; + i_full <= 1'b0; + + if (lpm_numwords >= 3) + almostfull <= lpm_numwords - 3; + else + almostfull <= 0; + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge aclr) + begin + sm_empty <= 2'b00; + i_empty <= 1'b1; + i_full <= 1'b0; + lrreq <= 1'b0; + end // @(posedge aclr) + + always @(posedge clock) + begin + if (underflow_checking == "OFF") + lrreq <= rreq; + else + lrreq <= rreq && ~i_empty; + + if (~aclr && $time > 0) + begin + if (lpm_mode == "READ") + begin + casex (sm_empty) + // state_empty + 2'b00: + if (usedw_in != 0) + sm_empty <= 2'b01; + // state_non_empty + 2'b01: + if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq))) + sm_empty <= 2'b10; + // state_emptywait + 2'b10: + if (usedw_in > 1) + sm_empty <= 2'b01; + else + sm_empty <= 2'b00; + default: + $display ("Error! Invalid sm_empty state in read mode."); + endcase + end // if (lpm_mode == "READ") + else if (lpm_mode == "WRITE") + begin + casex (sm_empty) + // state_empty + 2'b00: + if (wreq) + sm_empty <= 2'b01; + // state_one + 2'b01: + if (!wreq) + sm_empty <= 2'b11; + // state_non_empty + 2'b11: + if (wreq) + sm_empty <= 2'b01; + else if (usedw_in == 0) + sm_empty <= 2'b00; + default: + $display ("Error! Invalid sm_empty state in write mode."); + endcase + end // if (lpm_mode == "WRITE") + + if (~aclr && (usedw_in >= almostfull) && ($time > 0)) + i_full <= 1'b1; + else + i_full <= 1'b0; + end // if (~aclr && $time > 0) + end // @(posedge clock) + + always @(sm_empty) + begin + i_empty <= !sm_empty[0]; + end + // @(sm_empty) + +// CONTINOUS ASSIGNMENT + assign empty = i_empty; + assign full = i_full; +endmodule // dcfifo_fefifo +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : dcfifo_async +// +// Description : Asynchronous Dual Clocks FIFO +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module dcfifo_async (data, rdclk, wrclk, aclr, rdreq, wrreq, + rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_widthu = 1; + parameter lpm_numwords = 2; + parameter delay_rdusedw = 1; + parameter delay_wrusedw = 1; + parameter rdsync_delaypipe = 3; + parameter wrsync_delaypipe = 3; + parameter intended_device_family = "APEX20KE"; + parameter lpm_showahead = "OFF"; + parameter underflow_checking = "ON"; + parameter overflow_checking = "ON"; + parameter use_eab = "ON"; + parameter add_ram_output_register = "OFF"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input rdclk; + input wrclk; + input aclr; + input wrreq; + input rdreq; + +// OUTPUT PORT DECLARATION + output rdfull; + output wrfull; + output rdempty; + output wrempty; + output [lpm_widthu-1:0] rdusedw; + output [lpm_widthu-1:0] wrusedw; + output [lpm_width-1:0] q; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] mem_data [(1< 0)) + begin + i_data_tmp <= data; + i_wrptr_tmp <= i_wrptr; + i_wren_tmp <= i_wren; + + if (i_wren) + begin + if (~aclr && ((i_wrptr < (1< 0)) + begin + if (i_wren_tmp) + begin + mem_data[i_wrptr_tmp] <= i_data_tmp; + data_ready[i_wrptr_tmp] <= 1'b0; + end + + if ((lpm_showahead == "ON") && + (!(dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family)))) + i_showahead_flag3 <= 1'b1; + end + end // @(negedge wrclk) + + always @(posedge rdclk) + begin + + if (rdclk && ($time > 0)) + begin + if ((lpm_showahead == "ON") && (add_ram_output_register == "ON") && + (dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family))) + begin + for (k = 0; k < (1< 0)) + begin + if (~aclr && ((i_rdptr < (1< (1 << lpm_widthu)) + $display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU."); + if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF")) + $display ("Error! add_ram_output_register must be ON or OFF."); + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + + for (i = 0; i < (1 << lpm_widthu); i = i + 1) + mem_data[i] <= 0; + i_data_tmp <= 0; + i_rdptr <= 0; + i_wrptr <= 0; + i_wrptr_tmp <= 0; + i_wren_tmp <= 0; + + i_rdempty <= 1; + i_wrempty <= 1; + i_rdfull <= 0; + i_wrfull <= 0; + i_rdusedw <= 0; + i_wrusedw <= 0; + i_q_tmp <= 0; + + if (lpm_numwords == (1 << lpm_widthu)) + cnt_mod <= 1 << (lpm_widthu + 1); + else + cnt_mod <= 1 << lpm_widthu; + end + +// COMPONENT INSTANTIATIONS + dcfifo_dffpipe RDPTR_D ( + .d (i_rdptr), + .clock (wrclk), + .aclr (aclr), + .q (w_rdptr_s)); + dcfifo_dffpipe WRPTR_D ( + .d (i_wrptr), + .clock (wrclk), + .aclr (aclr), + .q (w_wrptr_r)); + dcfifo_dffpipe WRPTR_E ( + .d (w_wrptr_r), + .clock (rdclk), + .aclr (aclr), + .q (w_wrptr_s)); + defparam + RDPTR_D.lpm_delay = 1, + RDPTR_D.lpm_width = lpm_widthu + 1, + WRPTR_D.lpm_delay = 1, + WRPTR_D.lpm_width = lpm_widthu + 1, + WRPTR_E.lpm_delay = 1, + WRPTR_E.lpm_width = lpm_widthu + 1; + +// ALWAYS CONSTRUCT BLOCK + always @(posedge aclr) + begin + i_rdptr <= 0; + i_wrptr <= 0; + if (!(dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family)) || + ((add_ram_output_register == "ON") && (use_eab == "OFF"))) + if (lpm_showahead == "ON") + i_q_tmp <= mem_data[0]; + else + i_q_tmp <= 0; + end // @(posedge aclr) + + // FIFOram + always @(rdreq or i_rdempty) + begin + if (underflow_checking == "OFF") + i_rden <= rdreq; + else + i_rden <= rdreq && !i_rdempty; + end // @(rdreq or i_rdempty) + + always @(wrreq or i_wrfull) + begin + if (overflow_checking == "OFF") + i_wren <= wrreq; + else + i_wren <= wrreq && !i_wrfull; + end // @(wrreq or i_wrfull) + + always @(posedge wrclk) + begin + if (aclr && (!(dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family)) || + ((add_ram_output_register == "ON") && (use_eab == "OFF")))) + begin + i_data_tmp <= 0; + i_wrptr_tmp <= 0; + i_wren_tmp <= 0; + end + else if (wrclk && ($time > 0)) + begin + i_data_tmp <= data; + i_wrptr_tmp <= i_wrptr[lpm_widthu-1:0]; + i_wren_tmp <= i_wren; + + if (i_wren) + begin + if (~aclr && (i_wrptr < cnt_mod - 1)) + i_wrptr <= i_wrptr + 1; + else + i_wrptr <= 0; + + if (use_eab == "OFF") + begin + mem_data[i_wrptr[lpm_widthu-1:0]] <= data; + + if (lpm_showahead == "ON") + i_showahead_flag2 <= 1'b1; + end + end + end + end // @(posedge wrclk) + + always @(negedge wrclk) + begin + if ((~wrclk && (use_eab == "ON")) && ($time > 0)) + begin + if (i_wren_tmp) + begin + mem_data[i_wrptr_tmp] <= i_data_tmp; + end + + if ((lpm_showahead == "ON") && + (!( dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family)))) + i_showahead_flag2 <= 1'b1; + end + end // @(negedge wrclk) + + always @(posedge rdclk) + begin + if (aclr && (!(dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family)) || + ((add_ram_output_register == "ON") && (use_eab == "OFF")))) + begin + if (lpm_showahead == "ON") + i_q_tmp <= mem_data[0]; + else + i_q_tmp <= 0; + end + else if (rdclk && i_rden && ($time > 0)) + begin + if (~aclr && (i_rdptr < cnt_mod - 1)) + i_rdptr <= i_rdptr + 1; + else + i_rdptr <= 0; + + if ((lpm_showahead == "ON") && (!((use_eab == "ON") && + (dev.IS_FAMILY_STRATIX(intended_device_family) || + dev.IS_FAMILY_STRATIXGX(intended_device_family) || + dev.IS_FAMILY_CYCLONE(intended_device_family))))) + i_showahead_flag2 <= 1'b1; + else + i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]]; + end + end // @(rdclk) + + always @(posedge i_showahead_flag) + begin + i_q_tmp <= mem_data[i_rdptr[lpm_widthu-1:0]]; + i_showahead_flag2 <= 1'b0; + end // @(posedge i_showahead_flag) + + always @(i_showahead_flag2) + begin + i_showahead_flag <= i_showahead_flag2; + end // @(i_showahead_flag2) + + // Usedw, Empty, Full + always @(i_rdptr or w_wrptr_s or cnt_mod) + begin + if (w_wrptr_s >= i_rdptr) + i_rdusedw <= w_wrptr_s - i_rdptr; + else + i_rdusedw <= w_wrptr_s + cnt_mod - i_rdptr; + end // @(i_rdptr or w_wrptr_s) + + always @(i_wrptr or w_rdptr_s or cnt_mod) + begin + if (i_wrptr >= w_rdptr_s) + i_wrusedw <= i_wrptr - w_rdptr_s; + else + i_wrusedw <= i_wrptr + cnt_mod - w_rdptr_s; + end // @(i_wrptr or w_rdptr_s) + + always @(i_rdusedw) + begin + if (i_rdusedw == 0) + i_rdempty <= 1; + else + i_rdempty <= 0; + + if (((lpm_numwords == (1 << lpm_widthu)) && i_rdusedw[lpm_widthu]) || + ((lpm_numwords < (1 << lpm_widthu)) && (i_rdusedw == lpm_numwords))) + i_rdfull <= 1; + else + i_rdfull <= 0; + end // @(i_rdusedw) + + always @(i_wrusedw) + begin + if (i_wrusedw == 0) + i_wrempty <= 1; + else + i_wrempty <= 0; + + if (((lpm_numwords == (1 << lpm_widthu)) && i_wrusedw[lpm_widthu]) || + ((lpm_numwords < (1 << lpm_widthu)) && (i_wrusedw == lpm_numwords))) + i_wrfull <= 1; + else + i_wrfull <= 0; + end // @(i_wrusedw) + +// CONTINOUS ASSIGNMENT + assign rdempty = i_rdempty; + assign wrempty = i_wrempty; + assign rdfull = i_rdfull; + assign wrfull = i_wrfull; + assign wrusedw = i_wrusedw[lpm_widthu-1:0]; + assign rdusedw = i_rdusedw[lpm_widthu-1:0]; + assign q = i_q_tmp; + +endmodule // dcfifo_sync +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : dcfifo_low_latency +// +// Description : Dual Clocks FIFO with lowest latency. This fifo implements +// the fifo behavior for Stratix II, Cyclone II and Stratix +// showahead area mode (LPM_SHOWAHEAD=ON, ADD_RAM_OUTPUT_REGISTER=OFF) +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module dcfifo_low_latency (data, rdclk, wrclk, aclr, rdreq, wrreq, + rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_widthu = 1; + parameter lpm_numwords = 2; + parameter delay_rdusedw = 2; + parameter delay_wrusedw = 2; + parameter rdsync_delaypipe = 1; + parameter wrsync_delaypipe = 1; + parameter intended_device_family = "Stratix"; + parameter lpm_showahead = "OFF"; + parameter underflow_checking = "ON"; + parameter overflow_checking = "ON"; + +input [lpm_width-1:0] data; + input rdclk; + input wrclk; + input aclr; + input rdreq; + input wrreq; + +// OUTPUT PORT DECLARATION + output rdfull; + output wrfull; + output rdempty; + output wrempty; + output [lpm_widthu-1:0] rdusedw; + output [lpm_widthu-1:0] wrusedw; + output [lpm_width-1:0] q; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] mem_data [(1< (1 << lpm_widthu)) + $display ("Error! LPM_NUMWORDS must be less than or equal to 2**LPM_WIDTHU."); + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + + for (i = 0; i < (1 << lpm_widthu); i = i + 1) + mem_data[i] <= {lpm_width{1'bx}}; + i_data_tmp <= 0; + i_wren_tmp <= 0; + i_rdptr_g <= 0; + i_rdptr_g1p <= 1; + i_wrptr_g <= 0; + i_wrptr_g_tmp <= 0; + i_wrptr_g1 <= 1; + i_delayed_wrptr_g <= 0; + i_rdempty <= 1; + i_wrempty <= 1; + i_rdempty_rreg <= 1; + i_rdfull <= 0; + i_wrfull <= 0; + i_wrfull_wreg <= 0; + i_q <= {lpm_width{1'bx}}; + + if (lpm_numwords == (1 << lpm_widthu)) + cnt_mod <= 1 << (lpm_widthu + 1); + else + cnt_mod <= 1 << lpm_widthu; + + if ((lpm_showahead == "OFF") && + ((dev.FEATURE_FAMILY_STRATIXII(intended_device_family)) || + (dev.IS_FAMILY_CYCLONEII(intended_device_family)))) + i_q_is_registered <= 1'b1; + else + i_q_is_registered <= 1'b0; + end + +// COMPONENT INSTANTIATIONS + dcfifo_dffpipe DP_WS_DGRP ( + .d (i_rdptr_g), + .clock (wrclk), + .aclr (aclr), + .q (i_ws_dgrp)); + defparam + DP_WS_DGRP.lpm_delay = wrsync_delaypipe, + DP_WS_DGRP.lpm_width = lpm_widthu; + + dcfifo_dffpipe DP_RS_DGWP ( + .d (i_delayed_wrptr_g), + .clock (rdclk), + .aclr (aclr), + .q (i_rs_dgwp)); + defparam + DP_RS_DGWP.lpm_delay = rdsync_delaypipe, + DP_RS_DGWP.lpm_width = lpm_widthu; + + dcfifo_dffpipe DP_RDUSEDW ( + .d (i_rdusedw_tmp), + .clock (rdclk), + .aclr (aclr), + .q (i_rdusedw)); + dcfifo_dffpipe DP_WRUSEDW ( + .d (i_wrusedw_tmp), + .clock (wrclk), + .aclr (aclr), + .q (i_wrusedw)); + defparam + DP_RDUSEDW.lpm_delay = (delay_rdusedw > 2) ? 2 : delay_rdusedw, + DP_RDUSEDW.lpm_width = lpm_widthu, + DP_WRUSEDW.lpm_delay = (delay_wrusedw > 2) ? 2 : delay_wrusedw, + DP_WRUSEDW.lpm_width = lpm_widthu; + +// ALWAYS CONSTRUCT BLOCK + always @(posedge aclr) + begin + i_data_tmp <= 0; + i_wren_tmp <= 0; + i_rdptr_g <= 0; + i_rdptr_g1p <= 1; + i_wrptr_g <= 0; + i_wrptr_g_tmp <= 0; + i_wrptr_g1 <= 1; + i_delayed_wrptr_g <= 0; + i_rdempty <= 1; + i_wrempty <= 1; + i_rdempty_rreg <= 1; + i_rdfull <= 0; + i_wrfull <= 0; + i_wrfull_wreg <= 0; + if(i_q_is_registered) + i_q <= 0; + end // @(posedge aclr) + + // FIFOram + always @(rdreq or i_rdempty) + begin + if (underflow_checking == "OFF") + i_rden <= rdreq; + else + i_rden <= rdreq && !i_rdempty; + end // @(rdreq or i_rdempty) + + always @(wrreq or i_wrfull) + begin + if (overflow_checking == "OFF") + i_wren <= wrreq; + else + i_wren <= wrreq && !i_wrfull; + end // @(wrreq or i_wrfull) + + always @(posedge wrclk) + begin + i_data_tmp <= data; + i_wrptr_g_tmp <= i_wrptr_g; + i_wren_tmp <= i_wren; + + if (~aclr && ($time > 0)) + begin + if (i_wren) + begin + if (i_wrptr_g1 < cnt_mod - 1) + i_wrptr_g1 <= i_wrptr_g1 + 1; + else + i_wrptr_g1 <= 0; + + i_wrptr_g <= i_wrptr_g1; + end + i_delayed_wrptr_g <= i_wrptr_g; + end + end // @(wrclk) + + always @(negedge wrclk) + begin + if (i_wren_tmp && ($time > 0)) + mem_data[i_wrptr_g_tmp] <= i_data_tmp; + + end // @(wrclk) + + always @(posedge rdclk) + begin + if(~aclr) + begin + if (i_rden && ($time > 0)) + begin + if (i_rdptr_g1p < cnt_mod - 1) + i_rdptr_g1p <= i_rdptr_g1p + 1; + else + i_rdptr_g1p <= 0; + + i_rdptr_g <= i_rdptr_g1p; + end + end + end + + always @(posedge rdclk) + begin + if ((! i_q_is_registered) && ($time > 0)) + begin + if (i_rdempty == 1'b1) + i_q <= mem_data[i_rdptr_g]; + else if (i_rden) + i_q <= mem_data[i_rdptr_g1p]; + end + else if (~aclr && i_rden && ($time > 0)) + i_q <= mem_data[i_rdptr_g]; + end + + // Usedw, Empty, Full + always @(i_wrptr_g or i_ws_dgrp or cnt_mod) + begin + if (i_wrptr_g < i_ws_dgrp) + i_wrusedw_tmp <= cnt_mod + i_wrptr_g - i_ws_dgrp; + else + i_wrusedw_tmp <= i_wrptr_g - i_ws_dgrp; + end // @(i_wrptr_g or i_ws_dgrp) + + always @(i_rdptr_g or i_rs_dgwp or cnt_mod) + begin + if (i_rs_dgwp < i_rdptr_g) + i_rdusedw_tmp <= cnt_mod + i_rs_dgwp - i_rdptr_g; + else + i_rdusedw_tmp <= i_rs_dgwp - i_rdptr_g; + end // @(i_wrptr_g or i_rs_dgwp) + + always @(i_wrptr_g1 or i_ws_dgrp) + begin + if (i_wrptr_g1 == i_ws_dgrp) + i_wrfull <= 1; + else + i_wrfull <= 0; + end // @(i_wrptr_g1 or i_ws_dgrp) + + always @(i_rdptr_g or i_rs_dgwp) + begin + if (i_rdptr_g == i_rs_dgwp) + i_rdempty <= 1; + else + i_rdempty <= 0; + end // @(i_rdptr_g or i_rs_dgwp) + + always @(posedge rdclk) + begin + i_rdfull <= i_wrfull_wreg; + i_rdempty_rreg <= i_rdempty; + end // @(posedge rdclk) + + always @(posedge wrclk) + begin + i_wrempty <= i_rdempty_rreg; + i_wrfull_wreg <= i_wrfull; + end // @(posedge wrclk) + +// CONTINOUS ASSIGNMENT + assign rdempty = i_rdempty; + assign wrempty = i_wrempty; + assign rdfull = i_rdfull; + assign wrfull = i_wrfull; + assign wrusedw = i_wrusedw[lpm_widthu-1:0]; + assign rdusedw = i_rdusedw[lpm_widthu-1:0]; + assign q = i_q; + +endmodule // dcfifo_low_latency +// END OF MODULE + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : dcfifo +// +// Description : Dual Clocks FIFO +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module dcfifo ( data, rdclk, wrclk, aclr, rdreq, wrreq, + rdfull, wrfull, rdempty, wrempty, rdusedw, wrusedw, q); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_widthu = 1; + parameter lpm_numwords = 2; + parameter delay_rdusedw = 1; + parameter delay_wrusedw = 1; + parameter rdsync_delaypipe = 3; + parameter wrsync_delaypipe = 3; + parameter intended_device_family = "APEX20KE"; + parameter lpm_showahead = "OFF"; + parameter underflow_checking = "ON"; + parameter overflow_checking = "ON"; + parameter clocks_are_synchronized = "FALSE"; + parameter use_eab = "ON"; + parameter add_ram_output_register = "OFF"; + parameter add_width = 1; + parameter lpm_hint = "USE_EAB=ON"; + parameter lpm_type = "dcfifo"; + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input rdclk; + input wrclk; + input aclr; + input rdreq; + input wrreq; + +// OUTPUT PORT DECLARATION + output rdfull; + output wrfull; + output rdempty; + output wrempty; + output [lpm_widthu-1:0] rdusedw; + output [lpm_widthu-1:0] wrusedw; + output [lpm_width-1:0] q; + +// INTERNAL WIRE DECLARATION + wire w_rdfull_s; + wire w_wrfull_s; + wire w_rdempty_s; + wire w_wrempty_s; + wire w_rdfull_a; + wire w_wrfull_a; + wire w_rdempty_a; + wire w_wrempty_a; + wire w_rdfull_l; + wire w_wrfull_l; + wire w_rdempty_l; + wire w_wrempty_l; + wire [lpm_widthu-1:0] w_rdusedw_s; + wire [lpm_widthu-1:0] w_wrusedw_s; + wire [lpm_widthu-1:0] w_rdusedw_a; + wire [lpm_widthu-1:0] w_wrusedw_a; + wire [lpm_widthu-1:0] w_rdusedw_l; + wire [lpm_widthu-1:0] w_wrusedw_l; + wire [lpm_width-1:0] w_q_s; + wire [lpm_width-1:0] w_q_a; + wire [lpm_width-1:0] w_q_l; + +// INTERNAL TRI DECLARATION + tri0 aclr; + +// COMPONENT INSTANTIATIONS + ALTERA_DEVICE_FAMILIES dev (); + + dcfifo_sync SYNC ( + .data (data), + .rdclk (rdclk), + .wrclk (wrclk), + .aclr (aclr), + .rdreq (rdreq), + .wrreq (wrreq), + .rdfull (w_rdfull_s), + .wrfull (w_wrfull_s), + .rdempty (w_rdempty_s), + .wrempty (w_wrempty_s), + .rdusedw (w_rdusedw_s), + .wrusedw (w_wrusedw_s), + .q (w_q_s)); + defparam + SYNC.lpm_width = lpm_width, + SYNC.lpm_widthu = lpm_widthu, + SYNC.lpm_numwords = lpm_numwords, + SYNC.intended_device_family = intended_device_family, + SYNC.lpm_showahead = lpm_showahead, + SYNC.underflow_checking = underflow_checking, + SYNC.overflow_checking = overflow_checking, + SYNC.use_eab = use_eab, + SYNC.add_ram_output_register = add_ram_output_register; + + dcfifo_async ASYNC ( + .data (data), + .rdclk (rdclk), + .wrclk (wrclk), + .aclr (aclr), + .rdreq (rdreq), + .wrreq (wrreq), + .rdfull (w_rdfull_a), + .wrfull (w_wrfull_a), + .rdempty (w_rdempty_a), + .wrempty (w_wrempty_a), + .rdusedw (w_rdusedw_a), + .wrusedw (w_wrusedw_a), + .q (w_q_a) ); + defparam + ASYNC.lpm_width = lpm_width, + ASYNC.lpm_widthu = lpm_widthu, + ASYNC.lpm_numwords = lpm_numwords, + ASYNC.delay_rdusedw = delay_rdusedw, + ASYNC.delay_wrusedw = delay_wrusedw, + ASYNC.rdsync_delaypipe = rdsync_delaypipe, + ASYNC.wrsync_delaypipe = wrsync_delaypipe, + ASYNC.intended_device_family = intended_device_family, + ASYNC.lpm_showahead = lpm_showahead, + ASYNC.underflow_checking = underflow_checking, + ASYNC.overflow_checking = overflow_checking, + ASYNC.use_eab = use_eab, + ASYNC.add_ram_output_register = add_ram_output_register; + + dcfifo_low_latency LOWLATENCY ( + .data (data), + .rdclk (rdclk), + .wrclk (wrclk), + .aclr (aclr), + .rdreq (rdreq), + .wrreq (wrreq), + .rdfull (w_rdfull_l), + .wrfull (w_wrfull_l), + .rdempty (w_rdempty_l), + .wrempty (w_wrempty_l), + .rdusedw (w_rdusedw_l), + .wrusedw (w_wrusedw_l), + .q (w_q_l) ); + defparam + LOWLATENCY.lpm_width = lpm_width, + LOWLATENCY.lpm_widthu = lpm_widthu, + LOWLATENCY.lpm_numwords = lpm_numwords, + LOWLATENCY.delay_rdusedw = delay_rdusedw, + LOWLATENCY.delay_wrusedw = delay_wrusedw, + LOWLATENCY.rdsync_delaypipe = (rdsync_delaypipe > 3 ? rdsync_delaypipe - 2 : 1), + LOWLATENCY.wrsync_delaypipe = (wrsync_delaypipe > 3 ? wrsync_delaypipe - 2 : 1), + LOWLATENCY.intended_device_family = intended_device_family, + LOWLATENCY.lpm_showahead = lpm_showahead, + LOWLATENCY.underflow_checking = underflow_checking, + LOWLATENCY.overflow_checking = overflow_checking; + +// CONTINOUS ASSIGNMENT + assign rdfull = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) || + (dev.FEATURE_FAMILY_STRATIX(intended_device_family) && + (lpm_showahead == "ON") && + (add_ram_output_register == "OFF"))) && + (use_eab == "ON")) ? w_rdfull_l : + (clocks_are_synchronized == "TRUE") ? w_rdfull_s : w_rdfull_a; + + assign wrfull = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) || + (dev.FEATURE_FAMILY_STRATIX(intended_device_family) && + (lpm_showahead == "ON") && + (add_ram_output_register == "OFF"))) && + (use_eab == "ON")) ? w_wrfull_l : + (clocks_are_synchronized == "TRUE") ? w_wrfull_s : w_wrfull_a; + + assign rdempty = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) || + (dev.FEATURE_FAMILY_STRATIX(intended_device_family) && + (lpm_showahead == "ON") && + (add_ram_output_register == "OFF"))) && + (use_eab == "ON")) ? w_rdempty_l : + (clocks_are_synchronized == "TRUE") ? w_rdempty_s : w_rdempty_a; + + assign wrempty = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) || + (dev.FEATURE_FAMILY_STRATIX(intended_device_family) && + (lpm_showahead == "ON") && + (add_ram_output_register == "OFF"))) && + (use_eab == "ON")) ? w_wrempty_l : + (clocks_are_synchronized == "TRUE") ? w_wrempty_s : w_wrempty_a; + + assign rdusedw = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) || + (dev.FEATURE_FAMILY_STRATIX(intended_device_family) && + (lpm_showahead == "ON") && + (add_ram_output_register == "OFF"))) && + (use_eab == "ON")) ? w_rdusedw_l : + (clocks_are_synchronized == "TRUE") ? w_rdusedw_s : w_rdusedw_a; + + assign wrusedw = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) || + (dev.FEATURE_FAMILY_STRATIX(intended_device_family) && + (lpm_showahead == "ON") && + (add_ram_output_register == "OFF"))) && + (use_eab == "ON")) ? w_wrusedw_l : + (clocks_are_synchronized == "TRUE") ? w_wrusedw_s : w_wrusedw_a; + + assign q = ((dev.FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM(intended_device_family) || + (dev.FEATURE_FAMILY_STRATIX(intended_device_family) && + (lpm_showahead == "ON") && + (add_ram_output_register == "OFF"))) && + (use_eab == "ON")) ? w_q_l : + (clocks_are_synchronized == "TRUE") ? w_q_s : w_q_a; + +endmodule // dcfifo +// END OF MODULE + +//-------------------------------------------------------------------------- +// Module Name : altshift_taps +// +// Description : Parameterized shift register with taps megafunction. +// Implements a RAM-based shift register for efficient +// creation of very large shift registers +// +// Limitation : This megafunction is provided only for backward +// compatibility in Cyclone, Stratix, and Stratix GX +// designs. +// +// Results expected : Produce output from the end of the shift register +// and from the regularly spaced taps along the +// shift register. +// +//-------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module altshift_taps (shiftin, clock, clken, shiftout, taps); + +// PARAMETER DECLARATION + parameter number_of_taps = 4; // Specifies the number of regularly spaced + // taps along the shift register + parameter tap_distance = 3; // Specifies the distance between the + // regularly spaced taps in clock cycles + // This number translates to the number of + // memory words that will be needed + parameter width = 8; // Specifies the width of the input pattern + parameter power_up_state = "CLEARED"; + parameter lpm_type = "altshift_taps"; + parameter lpm_hint = "UNUSED"; + + // Following parameters are used as constant + parameter RAM_WIDTH = width * number_of_taps; + parameter TOTAL_TAP_DISTANCE = number_of_taps * tap_distance; + +// INPUT PORT DECLARATION + input [width-1:0] shiftin; // Data input to the shifter + input clock; // Positive-edge triggered clock + input clken; // Clock enable for the clock port + +// OUTPUT PORT DECLARATION + output [width-1:0] shiftout; // Output from the end of the shift + // register + output [RAM_WIDTH-1:0] taps; // Output from the regularly spaced taps + // along the shift register + +// INTERNAL REGISTERS DECLARATION + reg [width-1:0] shiftout; + reg [RAM_WIDTH-1:0] taps; + reg [width-1:0] shiftout_tmp; + reg [RAM_WIDTH-1:0] taps_tmp; + reg [width-1:0] contents [0:TOTAL_TAP_DISTANCE-1]; + +// LOCAL INTEGER DECLARATION + integer head; // pointer to memory + integer i; // for loop index + integer j; // for loop index + integer k; // for loop index + integer place; + +// TRI STATE DECLARATION + tri1 clken; + +// INITIAL CONSTRUCT BLOCK + initial + begin + head = 0; + if (power_up_state == "CLEARED") + begin + shiftout = 0; + shiftout_tmp = 0; + for (i = 0; i < TOTAL_TAP_DISTANCE; i = i + 1) + begin + contents [i] = 0; + end + for (j = 0; j < RAM_WIDTH; j = j + 1) + begin + taps [j] = 0; + taps_tmp [j] = 0; + end + end + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge clock) + begin + if (clken == 1'b1) + begin + contents[head] = shiftin; + head = (head + 1) % TOTAL_TAP_DISTANCE; + shiftout_tmp = contents[head]; + + taps_tmp = 0; + + for (k=0; k < number_of_taps; k=k+1) + begin + place = (((number_of_taps - k - 1) * tap_distance) + head ) % + TOTAL_TAP_DISTANCE; + taps_tmp = taps_tmp | (contents[place] << (k * width)); + end + end + end + + always @(shiftout_tmp) + begin + shiftout <= shiftout_tmp; + end + + always @(taps_tmp) + begin + taps <= taps_tmp; + end + +endmodule // altshift_taps + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : a_graycounter +// +// Description : Gray counter with Count-enable, Up/Down, aclr and sclr +// +// Limitation : Sync sigal priority: clk_en (higher),sclr,cnt_en (lower) +// +// Results expected: q is graycounter output and qbin is normal counter +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module a_graycounter (clock, cnt_en, clk_en, updown, aclr, sclr, + q, qbin); +// GLOBAL PARAMETER DECLARATION + parameter width = 3; + parameter pvalue = 0; + parameter lpm_hint = "UNUSED"; + parameter lpm_type = "a_graycounter"; + +// INPUT PORT DECLARATION + input clock; + input cnt_en; + input clk_en; + input updown; + input aclr; + input sclr; + +// OUTPUT PORT DECLARATION + output [width-1:0] q; + output [width-1:0] qbin; + +// INTERNAL REGISTERS DECLARATION + reg [width-1:0] cnt; + +// INTERNAL TRI DECLARATION + tri1 clk_en; + tri1 cnt_en; + tri1 updown; + tri0 aclr; + tri0 sclr; + +// LOCAL INTEGER DECLARATION + +// COMPONENT INSTANTIATIONS + +// INITIAL CONSTRUCT BLOCK + initial + begin + if (width <= 0) + $display ("Error! WIDTH of a_greycounter must be greater than 0."); + + cnt <= pvalue; + end + +// ALWAYS CONSTRUCT BLOCK + always @(posedge aclr or posedge clock) + begin + if (aclr) + cnt <= pvalue; + else + begin + if (clk_en) + begin + if (sclr) + cnt <= pvalue; + else if (cnt_en) + begin + if (updown == 1) + cnt <= cnt + 1; + else + cnt <= cnt - 1; + end + end + end + end + +// CONTINOUS ASSIGNMENT + assign qbin = cnt; + assign q = cnt ^ (cnt >>1); + +endmodule // a_graycounter +// END OF MODULE + + +//-------------------------------------------------------------------------- +// alt_exc_dpram +//-------------------------------------------------------------------------- +// +`timescale 1 ps / 1 ps +module alt_exc_dpram (portadatain, + portadataout, + portaaddr, + portawe, + portaena, + portaclk, + portbdatain, + portbdataout, + portbaddr, + portbwe, + portbena, + portbclk + ); + + // default parameters + parameter operation_mode = "SINGLE_PORT" ; + parameter addrwidth = 14 ; + parameter width = 32 ; + parameter depth = 16384 ; + parameter ramblock = 65535 ; + parameter output_mode = "UNREG" ; + parameter lpm_file = "NONE" ; + parameter lpm_type = "alt_exc_dpram"; + parameter lpm_hint = "UNUSED"; + + // size of memory array + + reg [width-1:0] dpram_content[depth-1:0]; + + // input/output signals + + input portawe , + portbwe , + portaena , + portbena , + portaclk , + portbclk ; + + input [width-1:0] portadatain ; + input [width-1:0] portbdatain ; + + input [addrwidth-1:0] portaaddr ; + input [addrwidth-1:0] portbaddr ; + + output [width-1:0] portadataout , + portbdataout ; + + // internal signals/registers + + reg portaclk_in_last ; + reg portbclk_in_last ; + + wire portaclk_in ; + wire portbclk_in ; + wire portawe_in ; + wire portbwe_in ; + wire portaena_in ; + wire portbena_in ; + + wire [width-1:0] portadatain_in ; + wire [width-1:0] portbdatain_in ; + wire [width-1:0] portadatain_tmp ; + wire [width-1:0] portbdatain_tmp ; + + wire [addrwidth-1:0] portaaddr_in ; + wire [addrwidth-1:0] portbaddr_in ; + + reg [width-1:0] portadataout_tmp ; + reg [width-1:0] portbdataout_tmp ; + reg [width-1:0] portadataout_reg ; + reg [width-1:0] portbdataout_reg ; + reg [width-1:0] portadataout_reg_out ; + reg [width-1:0] portbdataout_reg_out ; + wire [width-1:0] portadataout_tmp2 ; + wire [width-1:0] portbdataout_tmp2 ; + + reg portawe_latched ; + reg portbwe_latched ; + reg [addrwidth-1:0] portaaddr_latched ; + reg [addrwidth-1:0] portbaddr_latched ; + + // assign to internal signals + + assign portadatain_in = portadatain; + assign portaaddr_in = portaaddr; + assign portaena_in = portaena; + assign portaclk_in = portaclk; + assign portawe_in = portawe; + + assign portbdatain_in = portbdatain; + assign portbaddr_in = portbaddr; + assign portbena_in = portbena; + assign portbclk_in = portbclk; + assign portbwe_in = portbwe; + + + // Dual Port Contention Port A address = Port B address + // + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | Port A | Port B | A Data In | B Data In | A Data Out | B Data Out | Memory State | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | read | read | DA | DB | memory | memory | no change | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | write | read | DA | DB | unknown | unknown | memory <= DA | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | read | write | DA | DB | unknown | unknown | memory <= DB | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | write | write | DA | DB | unknown | unknown | memory <= unknown | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // + // Dual Port Contention Port A address != Port B address + // + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | Port A | Port B | A Data In | B Data In | A Data Out | B Data Out | Memory State | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | read | read | DA | DB | mem[A_addr] | mem[B_Addr] | no change | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | write | read | DA | DB | unknown | mem[B_Addr] | mem[A_Addr] <= DA | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | read | write | DA | DB | mem[A_addr] | unknown | mem[B_Addr] <= DB | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // | write | write | DA | DB | unknown | unknown | mem[A_Addr] <= DA | + // | | | | | | | mem[B_Addr] <= DB | + // +-----------+----------+-------------+-------------+--------------+--------------+---------------------+ + // + // NB: Output state is always unknown when writing. + + + initial + begin + // Initialise dpram memory contents from file (if filename specified). + if (lpm_file != "NONE" && lpm_file != "none") $readmemh(lpm_file, dpram_content); + + portaclk_in_last = 0; + portbclk_in_last = 0; + end + + always @(portaclk_in) + begin + if (portaclk_in != 0 && portaclk_in_last == 0) // rising edge port a clock + begin + + portawe_latched = portawe_in ; + portaaddr_latched = portaaddr_in ; + + if (portawe_latched == 'b0) + begin + + // reading A + + if (portaaddr_latched == portbaddr_latched && portbwe_latched != 'b0) + begin + + // B simultaneously writing to same address (effect of B write to memory handled below) + + portadataout_reg = portadataout_tmp; + portadataout_tmp = 'bx; + + end + else + begin + + // B reading from same address, or reading/writing to different address. + + portadataout_reg = portadataout_tmp; + portadataout_tmp = dpram_content[portaaddr_latched]; + + end + end + + else + + // writing to A + + begin + if (portaaddr_latched == portbaddr_latched && portawe_latched != 'b0 && portbwe_latched != 'b0) + begin + + // A and B simultaneously writing to same address + + portadataout_reg = portadataout_tmp ; + dpram_content[portaaddr_latched] = 'bx ; + portadataout_tmp = 'bx ; + + end + else + begin + + // B reading from same address or reading/writing to different address + + portadataout_reg = portadataout_tmp; + dpram_content[portaaddr_latched] = portadatain_tmp ; + portadataout_tmp = 'bx ; + + end + end // writing to A + end // rising edge port a clock + portaclk_in_last = portaclk_in; + end // portaclk_in change event + + always @(portbclk_in) + begin + if (portbclk_in != 0 && portbclk_in_last == 0 && (operation_mode == "DUAL_PORT" || operation_mode == "dual_port")) // rising edge port b clock + begin + + portbwe_latched = portbwe_in ; + portbaddr_latched = portbaddr_in ; + + if (portbwe_latched == 'b0) + begin + + // reading B + + if (portbaddr_latched == portaaddr_latched && portawe_latched != 'b0) + begin + + // A simultaneously writing to same address (effect of A write to memory handled above) + + portbdataout_reg = portbdataout_tmp; + portbdataout_tmp = 'bx; + + end + else + begin + + // A reading from same address, or reading/writing to different address. + + portbdataout_reg = portbdataout_tmp; + portbdataout_tmp = dpram_content[portbaddr_latched]; + + end + end + else + + // writing to B + + begin + if (portbaddr_latched == portaaddr_latched && portbwe_latched != 'b0 && portawe_latched != 'b0) + begin + + // B and A simultaneously writing to same address + + portbdataout_reg = portbdataout_tmp ; + dpram_content[portbaddr_latched] = 'bx ; + portbdataout_tmp = 'bx ; + + end + else + begin + + // A reading from same address or reading/writing to different address + + portbdataout_reg = portbdataout_tmp; + dpram_content[portbaddr_latched] = portbdatain_tmp ; + portbdataout_tmp = 'bx ; + + end + end // writing to B + end // rising edge port B clock + + portbclk_in_last = portbclk_in; + + end // portbclk_in change event + + // registered Port A output enabled ? + + always @(portaena_in or portadataout_reg) + begin + if (output_mode == "REG" || output_mode == "reg") + if ( portaena_in == 1'b1 ) + portadataout_reg_out = portadataout_reg ; + end + + // registered Port B output enabled ? + + always @(portbena_in or portbdataout_reg) + begin + if (output_mode == "REG" || output_mode == "reg") + if ( portbena_in == 1'b1 ) + portbdataout_reg_out = portbdataout_reg ; + end + + // Registered or Unregistered mode ? + + assign portadataout_tmp2 = (output_mode == "REG" || output_mode == "reg") ? portadataout_reg_out[width-1:0] : portadataout_tmp[width-1:0]; + assign portbdataout_tmp2 = (output_mode == "REG" || output_mode == "reg") ? portbdataout_reg_out[width-1:0] : portbdataout_tmp[width-1:0]; + + assign portadatain_tmp[width-1:0] = portadatain; + assign portbdatain_tmp[width-1:0] = portbdatain; + + assign portadataout = portadataout_tmp2; + assign portbdataout = portbdataout_tmp2; + + +endmodule // alt_exc_dpram + +//-------------------------------------------------------------------------- +// Altera UP Core +//-------------------------------------------------------------------------- +// +`timescale 1 ps / 1 ps + +module alt_exc_upcore ( + intpld, intuart, inttimer0, inttimer1, intcommtx, intcommrx, intproctimer, intprocbridge, + debugrq, debugext0, debugext1, debugiebrkpt, debugdewpt, debugextin, debugack, + debugrng0, debugrng1, debugextout, + + slavehclk, + slavehwrite, slavehreadyi, slavehselreg, slavehsel, slavehmastlock, slavehaddr, + slavehwdata, slavehtrans, slavehsize, slavehburst, slavehreadyo, slavebuserrint, + slavehrdata, slavehresp, + + masterhclk, + masterhrdata, masterhresp, masterhwrite, masterhlock, masterhbusreq, masterhaddr, + masterhwdata, masterhtrans, masterhsize, masterhready, masterhburst, masterhgrant, + + lockreqdp0, lockreqdp1, + lockgrantdp0, lockgrantdp1, + + ebiack, ebiwen, ebioen, ebiclk, ebibe, ebicsn, ebiaddr, ebidq, + + uarttxd, uartrtsn, uartdtrn, uartctsn, uartdsrn, uartrxd, uartdcdn, + uartrin, + + sdramclk, sdramclkn, sdramclke, sdramwen, sdramcasn, sdramrasn, sdramdqm, + sdramaddr, sdramdq, sdramdqs, sdramcsn, + + + intextpin, traceclk, tracesync, tracepipestat, tracepkt, clk_ref, intnmi, perreset, + npor, nreset, gpi, gpo + ); + + parameter processor = "ARM"; + parameter source = ""; + parameter sdram_width = 32; + parameter sdramdqm_width = 4; + parameter gpio_width = 4; + parameter lpm_type = "alt_exc_upcore"; + parameter lpm_hint = "UNUSED"; + +// AHB2 Master and Slave bridges +// Interupt, debug and trace ports +// DP Ram locks + + input slavehclk, masterhclk; + + input slavehwrite, slavehreadyi, slavehselreg, slavehsel, + slavehmastlock, masterhready, masterhgrant; + + input lockreqdp0, lockreqdp1, + debugrq, debugext0, debugext1, debugiebrkpt, debugdewpt; + + input [31:0] slavehaddr, slavehwdata, masterhrdata; + input [1:0] slavehtrans, slavehsize, masterhresp; + input [3:0] debugextin; + input [5:0] intpld; + input [2:0] slavehburst; + + output masterhwrite, masterhlock, masterhbusreq, slavehreadyo, slavebuserrint, + intuart, inttimer0, inttimer1, intcommtx, intcommrx, + debugack, debugrng0, debugrng1, + lockgrantdp0, lockgrantdp1; + + output [31:0] masterhaddr, masterhwdata, slavehrdata; + output [1:0] masterhtrans, masterhsize, slavehresp; + output [2:0] masterhburst; + output [3:0] debugextout; + +// Shared IO connections +// EBI Expansion bus +// SDRAM interface +// UART and trace port + + input ebiack; + output ebiwen, ebioen, ebiclk; + output [1:0] ebibe; + output [3:0] ebicsn; + output [24:0] ebiaddr; + inout [15:0] ebidq; + + input uartctsn, uartdsrn, uartrxd; + output uarttxd, uartrtsn, uartdtrn; + inout uartdcdn, uartrin; + + output sdramclk, sdramclkn, sdramclke, + sdramwen, sdramcasn, sdramrasn; + output [1:0] sdramcsn; + output [sdramdqm_width-1:0] sdramdqm; + output [14:0] sdramaddr; + + inout [sdram_width-1:0] sdramdq; + inout [sdramdqm_width-1:0] sdramdqs; + + input intextpin; + output traceclk, tracesync; + output [2:0] tracepipestat; + output [15:0] tracepkt; + + input clk_ref, npor; + inout nreset; + output intproctimer, intprocbridge; + output perreset; + input intnmi; + input [gpio_width-1:0] gpi; + output [gpio_width-1:0] gpo; + + +///////////////////////////////////////////////////////////////////////////////////////////////// +// AHB Constants +///////////////////////////////////////////////////////////////////////////////////////////////// + +// responses (HRESP) +`define H_OKAY 2'b00 +`define H_ERROR 2'b01 +`define H_RETRY 2'b10 +`define H_SPLIT 2'b11 + +// transcation types (HTRANS) +`define H_IDLE 2'b00 +`define H_BUSY 2'b01 +`define H_NONSEQ 2'b10 +`define H_SEQ 2'b11 + +// burst mode (HBURST) +`define H_SINGLE 3'b000 +`define H_INCR 3'b001 +`define H_WRAP4 3'b010 +`define H_INCR4 3'b011 +`define H_WRAP8 3'b100 +`define H_INCR8 3'b101 +`define H_WRAP16 3'b110 +`define H_INCR16 3'b111 + +// transaction sizes (HSIZE 8,16,32 bits -- larger sizes not supported) +`define H_BYTE 2'b00 +`define H_HWORD 2'b01 +`define H_WORD 2'b10 + +///////////////////////////////////////////////////////////////////////////////////////////////// +// slave port +///////////////////////////////////////////////////////////////////////////////////////////////// + + wire slavehclk_in; + wire slavehwrite_in, slavehreadyi_in, slavehselreg_in, slavehsel_in, + slavehmastlock_in; + wire [31:0] slavehaddr_in, slavehwdata_in; + wire [1:0] slavehtrans_in, slavehsize_in; + wire [2:0] slavehburst_in; + wire slavehreadyo_out, slavebuserrint_out; + wire [31:0] slavehrdata_out; + wire [1:0] slavehresp_out; + +// + assign slavehclk_in = slavehclk ; + assign slavehwrite_in = slavehwrite ; + assign slavehreadyi_in = slavehreadyi ; + assign slavehselreg_in = slavehselreg ; + assign slavehsel_in = slavehsel ; + assign slavehmastlock_in = slavehmastlock; + + assign slavehaddr_in = slavehaddr; + + assign slavehwdata_in = slavehwdata; + + assign slavehtrans_in = slavehtrans; + assign slavehsize_in = slavehsize; + assign slavehburst_in = slavehburst; + +// + assign slavehreadyo = slavehreadyo_out; + assign slavebuserrint= slavebuserrint_out; + + assign slavehrdata = slavehrdata_out; + assign slavehresp = slavehresp_out; + +///////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////// + +// outputs + reg slavehreadyo_out_r ; + reg [1:0] slavehresp_out_r ; + + assign slavehreadyo_out = slavehreadyo_out_r ; + assign slavehresp_out = slavehresp_out_r ; + + +// record of address and control information (latched on address phase) + reg [31:0] startReg; // start address for burst + reg [31:0] addrReg; + reg [1:0] transReg; + reg [1:0] sizeReg; + reg writeReg; + reg [2:0] burstReg; + reg selReg; + reg [7:0] waitReg; + +// Implement 6 banks of 256K = (1.5MB of address space) +// /////////////////////////////////////////////////////////////////// + reg [79:0] memCfg[0:5]; // slavememory.cfg.dat + reg [31:0] memStart[0:5]; + reg [31:0] memEnd[0:5]; + reg [7:0] memWaitStart[0:5]; + reg [7:0] memWait[0:5]; + reg [31:0] memMapA[0:65535]; // slavememory.0.dat + reg [31:0] memMapB[0:65535]; + reg [31:0] memMapC[0:65535]; + reg [31:0] memMapD[0:65535]; + reg [31:0] memMapE[0:65535]; + reg [31:0] memMapF[0:65535]; // slavememory.5.dat + + reg [2:0] memBank; + reg [79:0] temp; + + integer output_file ; + + initial begin + +// Open the results file + output_file = $fopen("output.dat") ; + if ( !output_file ) + $display("ERROR: Cannot open Output File") ; + + +// Initialise memory banks from config and map files +////////////////////////////////////////////////////////////////////// + temp=80'h00000000_00000000_00_00; + for (memBank=0;memBank<6;memBank=memBank+1) + begin + memCfg[memBank]=temp; + end + +// 79..48 start address +// 47..16 end address +// 15...8 wait states on first access +// 7...0 wait states per cycle + $readmemh("slavememory.cfg.dat", memCfg); + for (memBank=0;memBank<6;memBank=memBank+1) + begin + temp=memCfg[memBank]; + memStart[memBank] =temp[79:48]; + memEnd[memBank] =temp[47:16]; + memWaitStart[memBank] =temp[15:8]; + memWait[memBank] =temp[7:0]; + end + + if (memStart[0]!=memEnd[0]) $readmemh("slavememory.0.dat", memMapA); + if (memStart[1]!=memEnd[1]) $readmemh("slavememory.1.dat", memMapB); + if (memStart[2]!=memEnd[2]) $readmemh("slavememory.2.dat", memMapC); + if (memStart[3]!=memEnd[3]) $readmemh("slavememory.3.dat", memMapD); + if (memStart[4]!=memEnd[4]) $readmemh("slavememory.4.dat", memMapE); + if (memStart[5]!=memEnd[5]) $readmemh("slavememory.5.dat", memMapF); +////////////////////////////////////////////////////////////////////// + + addrReg=0; + transReg=`H_IDLE; + sizeReg=`H_WORD; + writeReg=0; + burstReg=`H_NONSEQ; + selReg=0; + + slavehresp_out_r=`H_OKAY; + end + + +// select signal + wire sel = slavehsel_in & slavehreadyi_in; + +// determine if the transaction includes an operation / a "busy" + wire doWork = selReg & ((transReg==`H_NONSEQ || transReg==`H_SEQ) ? 1'b1 : 1'b0); + wire doBusyWork = selReg & ( transReg==`H_BUSY ? 1'b1 : 1'b0); + + +// BURST MODE SUPPORT +/////////////////////////////////////////////////////////////////////////////// +// +// If we are in burst mode we'll compute our own address and control settings +// based on the spec. +// +// compute values SEQuential (burst) transfers + wire seqTrans = ( selReg & + ( doWork | doBusyWork) & + ( (slavehtrans_in==`H_SEQ || slavehtrans_in==`H_BUSY) ) ? 1'b1 : 1'b0 ); + + +// mask to determine which bits are retained from the start address + wire [31:0] wrapmask; + assign wrapmask = + ( burstReg==`H_WRAP4 ? {32{1'b1}} << 2: // all but 2 + ( burstReg==`H_WRAP8 ? {32{1'b1}} << 3: // all but 3 + ( burstReg==`H_WRAP16 ? {32{1'b1}} << 4: // all but 4 + {32{1'b0}} ) )); // none + wire [31:0] wrapmask_w; + assign wrapmask_w = // correct for word size + ( sizeReg==`H_WORD ? wrapmask<<2 : + ( sizeReg==`H_HWORD ? wrapmask<<1 : + /* H_BYTE */ wrapmask )); + + wire [31:0] seqPlusAddr; // work out the next sequential address + assign seqPlusAddr = + ( burstReg == `H_SINGLE) ? addrReg : + addrReg + ( sizeReg==`H_BYTE ? 1 : + ( sizeReg==`H_HWORD ? 2 : + ( sizeReg==`H_WORD ? 4 : 0) ) ) ; + + wire [31:0] seqAddr; // apply the mask to wrap at boundaries + assign seqAddr = (slavehtrans_in==`H_BUSY) ? addrReg : + ( (startReg&wrapmask_w) | (seqPlusAddr&~wrapmask_w)); + +// +// if this is a sequential transaction only sample HTRANS + wire [31:0] startNext; + wire [31:0] addrNext; + wire [1:0] transNext; + wire [1:0] sizeNext; + wire [2:0] burstNext; + wire writeNext; + + assign startNext = seqTrans ? startReg : slavehaddr_in; + assign addrNext = seqTrans ? seqAddr : slavehaddr_in; + assign transNext = slavehtrans_in; + assign sizeNext = seqTrans ? sizeReg : slavehsize_in; + assign burstNext = seqTrans ? burstReg : slavehburst_in; + assign writeNext = seqTrans ? writeReg : slavehwrite_in; + + +// Latch the control data if we are selected +/////////////////////////////////////////////////////////////////////////////////// + always @ (posedge slavehclk_in) + begin +// if readin is low another device is wait stating its +// data phase and hence extending our address phase + if (slavehreadyi_in) + begin + selReg <= sel; + if (sel) // latch the control data + begin + startReg <= startNext; + addrReg <= addrNext; + transReg <= transNext; + sizeReg <= sizeNext; + writeReg <= writeNext; + burstReg <= burstNext; + end + else + begin + startReg <= 0; + addrReg <= 0; + transReg <= `H_IDLE; + sizeReg <= `H_WORD; + writeReg <= 0; + burstReg <= `H_SINGLE; + end + end + end + + +// Implment memory banks +/////////////////////////////////////////////////////////////////////////////////// +// bank selects + wire bankA = ( addrReg>=memStart[0] && addrReg<=memEnd[0] && memStart[0]!=memEnd[0]) ? 1'b1 : 1'b0; + wire bankB = ( addrReg>=memStart[1] && addrReg<=memEnd[1] && memStart[1]!=memEnd[1]) ? 1'b1 : 1'b0; + wire bankC = ( addrReg>=memStart[2] && addrReg<=memEnd[2] && memStart[2]!=memEnd[2]) ? 1'b1 : 1'b0; + wire bankD = ( addrReg>=memStart[3] && addrReg<=memEnd[3] && memStart[3]!=memEnd[3]) ? 1'b1 : 1'b0; + wire bankE = ( addrReg>=memStart[4] && addrReg<=memEnd[4] && memStart[4]!=memEnd[4]) ? 1'b1 : 1'b0; + wire bankF = ( addrReg>=memStart[5] && addrReg<=memEnd[5] && memStart[5]!=memEnd[5]) ? 1'b1 : 1'b0; + +// byte offset into bank //word offset into bank + wire [31:0] offsetA = addrReg-memStart[0]; wire [15:0] wordA = offsetA[17:2]; + wire [31:0] offsetB = addrReg-memStart[1]; wire [15:0] wordB = offsetB[17:2]; + wire [31:0] offsetC = addrReg-memStart[2]; wire [15:0] wordC = offsetC[17:2]; + wire [31:0] offsetD = addrReg-memStart[3]; wire [15:0] wordD = offsetD[17:2]; + wire [31:0] offsetE = addrReg-memStart[4]; wire [15:0] wordE = offsetE[17:2]; + wire [31:0] offsetF = addrReg-memStart[5]; wire [15:0] wordF = offsetF[17:2]; + +// current data + wire [31:0] dataA = memMapA[wordA]; + wire [31:0] dataB = memMapB[wordB]; + wire [31:0] dataC = memMapC[wordC]; + wire [31:0] dataD = memMapD[wordD]; + wire [31:0] dataE = memMapE[wordE]; + wire [31:0] dataF = memMapF[wordF]; + + reg [31:0] currentVal; + always @(dataA or dataB or dataC or dataD or dataE or dataF or + bankA or bankB or bankC or bankD or bankE or bankF ) + begin + if (bankA) currentVal=dataA; + else if (bankB) currentVal=dataB; + else if (bankC) currentVal=dataC; + else if (bankD) currentVal=dataD; + else if (bankE) currentVal=dataE; + else if (bankF) currentVal=dataF; + end + + +// byte enables + wire be0 = (sizeReg==`H_WORD || + (sizeReg==`H_HWORD && addrReg[1]==1'b0) || + (sizeReg==`H_BYTE && addrReg[1:0]==2'b00) ) ? 1'b1 : 1'b0; + wire be1 = (sizeReg==`H_WORD || + (sizeReg==`H_HWORD && addrReg[1]==1'b0) || + (sizeReg==`H_BYTE && addrReg[1:0]==2'b01) ) ? 1'b1 : 1'b0; + wire be2 = (sizeReg==`H_WORD || + (sizeReg==`H_HWORD && addrReg[1]==1'b1) || + (sizeReg==`H_BYTE && addrReg[1:0]==2'b10) ) ? 1'b1 : 1'b0; + wire be3 = (sizeReg==`H_WORD || + (sizeReg==`H_HWORD && addrReg[1]==1'b1) || + (sizeReg==`H_BYTE && addrReg[1:0]==2'b11) ) ? 1'b1 : 1'b0; + + wire [31:0] readDataMask = {be3 ? 8'hFF : 8'h00, + be2 ? 8'hFF : 8'h00, + be1 ? 8'hFF : 8'h00, + be0 ? 8'hFF : 8'h00 }; + + + +// wait state generation +/////////////////////////////////////////////////////////////////////////////////// + + reg s_addr_latch; // address latched this cycle + reg [7:0] waitStart; + reg [7:0] waitSeq; + + initial begin + s_addr_latch=1'b0; + waitReg=8'h00; + end + + always @(bankA or bankB or bankC or bankD or bankE or bankF ) + begin + if (bankA) waitStart = memWaitStart[0]; + else if (bankB) waitStart = memWaitStart[1]; + else if (bankC) waitStart = memWaitStart[2]; + else if (bankD) waitStart = memWaitStart[3]; + else if (bankE) waitStart = memWaitStart[4]; + else if (bankF) waitStart = memWaitStart[5]; + end + + always @(bankA or bankB or bankC or bankD or bankE or bankF ) + begin + if (bankA) waitSeq = memWait[0]; + else if (bankB) waitSeq = memWait[1]; + else if (bankC) waitSeq = memWait[2]; + else if (bankD) waitSeq = memWait[3]; + else if (bankE) waitSeq = memWait[4]; + else if (bankF) waitSeq = memWait[5]; + end + + +// +// wait if +// first beat and memWaitStart and addr has just been latched +// or +// first beat and waitReg (more than 1 wait state) +// or +// seq beat and waitReg +// else ready +// + + always @(posedge slavehclk_in) + s_addr_latch <= slavehreadyi_in & slavehsel_in; + + always @(doWork or transReg or waitReg or waitStart or s_addr_latch) + begin + if ( doWork & (transReg==`H_NONSEQ) & (waitStart!=8'h00) & s_addr_latch ) + begin + slavehreadyo_out_r = 1'b0; + // $fdisplay(output_file, "SLAVE: wait on first" ); + end + else if ( doWork & (transReg==`H_NONSEQ) & waitReg!=8'h00 ) + begin + slavehreadyo_out_r = 1'b0; + // $fdisplay(output_file, "SLAVE: wait" ); + end + else if (doWork & (transReg==`H_SEQ) & (waitReg!=8'h00)) + begin + slavehreadyo_out_r = 1'b0; + // $fdisplay(output_file, "SLAVE: wait" ); + end + else + slavehreadyo_out_r = 1'b1; + end + + +// if we are waiting (waitReg>0) and not in a busy decrement the counter +// otherwise get the new value from memWait of memWaitStart according to +// the transaction type + + wire [7:0] waitStartNext; + assign waitStartNext = ( waitStart>8'h01 ? (waitStart-1) : 8'h00); + + always @ (posedge slavehclk_in) + waitReg<= (waitReg!=8'h00 & ~doBusyWork) ? (waitReg - 1'b1) : + ( doWork & (transReg==`H_NONSEQ) & (waitStart!=8'h00) & s_addr_latch ? waitStartNext : + ( seqTrans ? waitSeq : 8'h00 )); + + +// read data +/////////////////////////////////////////////////////////////////////////////////// + assign slavehrdata_out =(doWork & ~writeReg & slavehreadyo_out_r) ? + (readDataMask & currentVal) : {32{1'b0}}; + + + +// record writes in memory banks + report on screen +/////////////////////////////////////////////////////////////////////////////////// + reg [31:0] memWord; // the word to be updated / read + always @ (posedge slavehclk_in) + begin + if (doWork & slavehreadyo_out_r) + begin + memWord = currentVal; + if (writeReg) + begin + if (be0) memWord[7:0] =slavehwdata_in[7:0] ; + if (be1) memWord[15:8] =slavehwdata_in[15:8] ; + if (be2) memWord[23:16] =slavehwdata_in[23:16]; + if (be3) memWord[31:24] =slavehwdata_in[31:24]; + + if (bankA) memMapA[wordA] = memWord; + if (bankB) memMapB[wordB] = memWord; + if (bankC) memMapC[wordC] = memWord; + if (bankD) memMapD[wordD] = memWord; + if (bankE) memMapE[wordE] = memWord; + if (bankF) memMapF[wordF] = memWord; + end + if (output_file) + $fdisplay(output_file, + "SLAVE: addr=[%h] %s data=[%h] %s", + addrReg, + writeReg ? "WRITE" : "READ", + writeReg ? slavehwdata_in : slavehrdata_out , + sizeReg==`H_BYTE ? "BYTE" : + ( sizeReg==`H_HWORD ? "HALF WORD" : "WORD" ) ); + else + $display( + "SLAVE: addr=[%h] %s data=[%h] %s", + addrReg, + writeReg ? "WRITE" : "READ", + writeReg ? slavehwdata_in : slavehrdata_out , + sizeReg==`H_BYTE ? "BYTE" : + ( sizeReg==`H_HWORD ? "HALF WORD" : "WORD" ) ); + + end + end + +///////////////////////////////////////////////////////////////////////////////////////////////// +// Master Port transactor +///////////////////////////////////////////////////////////////////////////////////////////////// + +// timing data - setup and holds +//////////////////////////////// + wire masterhclk_in; + wire masterhready_in, masterhgrant_in; + wire [31:0] masterhrdata_in; + wire [1:0] masterhresp_in; + wire masterhwrite_out, masterhlock_out, masterhbusreq_out; + wire [31:0] masterhaddr_out, masterhwdata_out; + wire [1:0] masterhtrans_out, masterhsize_out; + wire [2:0] masterhburst_out; + +// + assign masterhclk_in = masterhclk; + assign masterhready_in = masterhready; + assign masterhgrant_in = masterhgrant; + + assign masterhrdata_in = masterhrdata; + assign masterhresp_in = masterhresp; + +// + assign masterhwrite = masterhwrite_out; + assign masterhlock = masterhlock_out; + assign masterhbusreq = masterhbusreq_out; + + assign masterhtrans = masterhtrans_out; + assign masterhsize = masterhsize_out; + assign masterhburst = masterhburst_out; + + assign masterhaddr = masterhaddr_out; + assign masterhwdata = masterhwdata_out; + + + ///////////////////////////////////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////////////////////////////////// + + // Transaction Record Format + // 255..254 spare + // 253..252 response + // 251..220 read data + // 219 go busy + // 218..217 spare + // 216..208 number of beats in sequential transaction + // 207..176 start address of transaction + // 175..144 expected data + // 143..128 transaction number + // ------------------------------------- following field read from command file + // 127..112 spare + // 111..109 spare + // 108 bus command (0 => inactive) + // 107.. 76 address + // 75.. 73 spare + // 72 write + // 71.. 40 write data / expected read data + // 39.. 37 spare + // 36 lock (not implemented) + // 35.. 33 spare + // 32 check expected data (not implemented) + // 31.. 30 spare + // 29.. 28 transaction type + // 27.. 23 spare + // 21.. 20 burst type + // 19.. 18 spare + // 17.. 16 size + // 15.. 00 repeat count + + // register outputs + reg [31:0] masterhaddr_out_r; + reg [31:0] masterhwdata_out_r; + reg [2:0] masterhburst_out_r; + reg [1:0] masterhtrans_out_r; + reg masterhwrite_out_r; + + assign masterhaddr_out = masterhaddr_out_r; + assign masterhwdata_out = masterhwdata_out_r; + assign masterhburst_out = masterhburst_out_r; + assign masterhtrans_out = masterhtrans_out_r; + assign masterhwrite_out = masterhwrite_out_r; + + reg [2:0] masterhsize_outl; // the transactor implements the full 3 bit size + assign masterhsize_out=masterhsize_outl[1:0]; // field but upCore only uses 2 + + + // //////////////////////////////////////////////////////////////////////////////////////////// + // + reg [128:0] transactions[1:65535]; // space for NUMTRANS transactions + reg [128:0] tmp_transaction; + reg [8:0] tmp_beats, tmp_num; + + // Transaction records + reg [255:0] n_trans; // next + reg [255:0] c_trans; // control / address phase + reg [255:0] d_trans; // data phase + reg [255:0] retry_trans; // retrying + reg [255:0] r_trans; // reporting + + reg [255:0] i_trans; // IDLE Transaction + + reg [15:0] trans_num; // the current control phase transaction + reg [31:0] resp_data; + +/*---------------------------------------------------------------------------- +Control signals for master transactor +----------------------------------------------------------------------------*/ + reg reset; + wire start = n_trans[108]; + wire stop = 1'b0; + wire continue_after_error = 1'b1; + wire generate_data = 1'b0; + wire [1:0] insert_busy = 2'b00; + wire go_busy = n_trans[219]; + wire [8:0] beats = n_trans[216:208]; // 511 beats max + wire [2:0] burst = n_trans[23:20]; + wire [2:0] size = n_trans[18:16]; + wire write = n_trans[72]; + wire [31:0] start_address = n_trans[207:176]; + wire [31:0] data = n_trans[71:40]; + + +/*---------------------------------------------------------------------------- +Transactor state and responses +----------------------------------------------------------------------------*/ + reg [2:0] original_burst; + reg masterhgrant_in_r; + reg [1:0] busy_states; + reg [1:0] busy_counter; + reg [9:0] init_wrap_mask, wrap_mask; + reg [7:0] masterhaddr_out_r_inc, init_wrap_boundary_bit; + reg [10:0] init_next_masterhaddr_out_r, wrap_boundary_bit; + reg [9:0] next_masterhaddr_out_r; + wire break_wrap; + + reg address_bus_owned, data_bus_owned; + reg add_go, data_go; + reg reading, writing; + reg first_beat, need_retry, wrap, replay_wrap; + reg new_grant; + wire first_masterhtrans_out_r; + wire addr_ack; + wire data_ack; + +/*---------------------------------------------------------------------------- +Initialisation +----------------------------------------------------------------------------*/ + initial + begin + i_trans ={256{1'b0}}; // set up a null transaction record + i_trans[143:128]=16'hFFFF; + i_trans[29:28] =`H_IDLE; + + d_trans=i_trans; // fill pipe with null's + c_trans=i_trans; + r_trans=i_trans; + // initialise the transactions database + tmp_transaction={128{1'b0}}; + + // we're using the bus functional language so load the commands + // from a file + for (trans_num=1;trans_num<65535;trans_num=trans_num+1) + begin + transactions[trans_num]=tmp_transaction; + end + $readmemh("mastercommands.dat", transactions); + + tmp_num = 9'b000000000; + tmp_beats = 9'b000000000; + trans_num=16'h0000; + + n_trans=i_trans; + n_trans[2]=1'b1; // repeat 4 + + reset=0; // reset the transactor on start + #10 reset=1; + #20 reset=0; + + end + + + +/*---------------------------------------------------------------------------- + Report completed transactions + + We could mask and shift the received data for HALFWORD and BYTE + transactions but we won't. + ----------------------------------------------------------------------------*/ + // received data + /**** + wire [31:0] r_r_data = r_trans[72]==1'b1 ? r_trans[71:40] : r_trans[251:220]; + wire [31:0] e_r_data = r_trans[175:144]; + wire [31:0] mr_r_data, me_r_data; // byte lane masked recovered and expected + + mr_r_data = r_trans[17:16] == `H_WORD ? r_r_data : + (r_trans[17:16] == `H_HWORD ? + { 16'h0000, (r_trans[77]==1'b1 ? r_r_data[31:16] : r_r_data[15:0]) } : + // byte + { 24'h000000, ( r_trans[77:76]==2'b00 ? r_r_data[7:0] : + r_trans[77:76]==2'b01 ? r_r_data[15:8] : + r_trans[77:76]==2'b10 ? r_r_data[23:16] : + r_r_data[31:24]) } ); + + r_rdata = r_trans[17:16] == `H_WORD ? r_e_data : + (r_trans[17:16] == `H_HWORD ? + { 16'h0000, (r_trans[77]==1'b1 ? r_e_data[31:16] : r_e_data[15:0]) } : + // byte + { 24'h000000, ( r_trans[77:76]==2'b00 ? r_e_data[7:0] : + r_trans[77:76]==2'b01 ? r_e_data[15:8] : + r_trans[77:76]==2'b10 ? r_e_data[23:16] : + r_e_data[31:24]) } ); + ****/ + always @(posedge masterhclk_in) + begin + if (r_trans[108]==1'b1) // r_trans contains a valid transaction + begin + + if (output_file) + $fdisplay(output_file, + "MASTER: trans=[%d] addr=[%h] %s data=[%h] expected=[%h] %s %s", + r_trans[143:128], + r_trans[107:76], + r_trans[72]==1'b1 ? "WRITE" : "READ", + r_trans[72]==1'b1 ? r_trans[71:40] : r_trans[251:220], + r_trans[175:144], + r_trans[17:16]==`H_BYTE ? "BYTE" : + ( r_trans[17:16]==`H_HWORD ? "HALF WORD" : "WORD" ), + r_trans[253:252]==`H_OKAY ? "OKAY" : "ERROR" ); + else + $display( + "MASTER: trans=[%d] addr=[%h] %s data=[%h] expected=[%h] %s %s", + r_trans[143:128], + r_trans[107:76], + r_trans[72]==1'b1 ? "WRITE" : "READ", + r_trans[72]==1'b1 ? r_trans[71:40] : r_trans[251:220], + r_trans[175:144], + r_trans[17:16]==`H_BYTE ? "BYTE" : + ( r_trans[17:16]==`H_HWORD ? "HALF WORD" : "WORD" ), + r_trans[253:252]==`H_OKAY ? "OKAY" : "ERROR" ); + + end + end + + + + + +/*---------------------------------------------------------------------------- +Get Next Transaction +----------------------------------------------------------------------------*/ + reg [216:208] tmp_repeats; + always + begin + + while ( trans_num<16'hFFFF) + begin + + if (n_trans[15:0]==16'h0000) + begin + // get the next record + trans_num = trans_num+1; + + tmp_transaction = transactions[trans_num]; + + n_trans[175:144]<= tmp_transaction[71:40]; // expected data + n_trans[143:128]<= trans_num; + n_trans[127:0] <= tmp_transaction; + + + // check for a BUSY + n_trans[219] <= tmp_transaction[29:28]==`H_BUSY ? 1'b1 : 1'b0; + + // update the start address + if (tmp_transaction[29:28]!=`H_SEQ&&tmp_transaction[29:28]!=`H_BUSY) + begin + n_trans[207:176] <= tmp_transaction[107:76]; // start address + end + + + // compute the number of beats in burst + if (tmp_transaction[23:20]!=`H_SINGLE && tmp_transaction[29:28]==`H_NONSEQ) + begin + tmp_beats=9'b0_0000_0001; + tmp_repeats[216:208]=9'b0_0000_0001; + + // get the transaction from the database + tmp_transaction=transactions[trans_num+tmp_beats]; + + while (tmp_transaction[29:28]==`H_SEQ||tmp_transaction[29:28]==`H_BUSY) + begin + tmp_repeats[216:208]=tmp_repeats[216:208]+tmp_transaction[15:0]+1; + tmp_beats=tmp_beats+1; + + // get the transaction from the database + tmp_transaction = transactions[trans_num+tmp_beats]; + + end + n_trans[216:208]<=tmp_repeats[216:208]; + end + + + end + else + begin + n_trans[15:0]<=n_trans[15:0]-1; + end // i + + // wait for the current transaction to be accepted + @(posedge masterhclk_in); + while (~(addr_ack|data_ack) && n_trans[108]) + @(posedge masterhclk_in); + + end // while transactions in buffer + if (output_file) $fclose(output_file) ; + $finish(2); + end + + + + + +/*---------------------------------------------------------------------------- +Compute burst length + +add_go_r prevents a newly loaded length being decremented by the last data +beat of the previous transaction. +----------------------------------------------------------------------------*/ + reg [8:0] length; + reg add_go_r; + always @(posedge masterhclk_in) + if (masterhready_in) + add_go_r <= add_go; + + always @(posedge masterhclk_in or posedge reset) + if (reset) + length <= 5'h0; + else if (add_go) + case (burst) + `H_SINGLE: length <= 9'h1; + `H_INCR: length <= beats; + `H_WRAP4, + `H_INCR4: length <= 9'h4; + `H_WRAP8, + `H_INCR8: length <= 9'h8; + `H_WRAP16, + `H_INCR16: length <= 9'h10; + endcase + else if ((reading | writing) & masterhready_in & ~add_go_r & ((masterhresp_in == `H_OKAY) | (masterhresp_in == `H_ERROR))) + length <= length - (|length); + + reg [8:0] address_length; + always @(posedge masterhclk_in or posedge reset) + if (reset) + address_length <= 5'h0; + else if (add_go) + case (burst) + `H_SINGLE: address_length <= 9'h1; + `H_INCR: address_length <= beats; + `H_WRAP4, + `H_INCR4: address_length <= 9'h4; + `H_WRAP8, + `H_INCR8: address_length <= 9'h8; + `H_WRAP16, + `H_INCR16: address_length <= 9'h10; + endcase + else if (data_bus_owned & ~masterhready_in & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT))) + address_length <= address_length + 9'h1; + else if (address_bus_owned & masterhready_in & ~(|busy_states) & (masterhtrans_out_r != `H_IDLE)) + address_length <= address_length - (|address_length); + else if (address_bus_owned & masterhready_in & (|busy_states) & (masterhtrans_out_r == `H_BUSY) & ~(|busy_counter)) + address_length <= address_length - (|address_length); + +/*---------------------------------------------------------------------------- +Bus request state machine + +Bus request machine follows the principle that the arbiter will generally +only re-assign bus grants at the end of a burst transaction. For defined +bursts masterhbusreq_out is removed as soon as we masterhave started the transaction. +Undefined (INCR) bursts will masterhold masterhbusreq_out asserted until the last beat of the +transaction. + +Locked transactions must always assert masterhlock_out for at least one cycle before +the address to be locked to allow the arbiter to see the lock. In practice, +this means inserting an idle cycle. + +Have to be careful using burst and beats from the control word. As soon as +the master address phase masterhas finished and the addr_ack is asserted the +testbench can change the control word. So don't use them after the initial +request. Use the ahb outputs instead which will tell us what sort of +transaction we're doing. +----------------------------------------------------------------------------*/ + reg [2:0] req_state; + parameter req_idle = 3'b000, + req_first = 3'b001, + req_wait = 3'b101, + req_masterhold = 3'b011, + req_using = 3'b010, + req_again = 3'b111; + assign masterhbusreq_out = start + | (req_state == req_first) + | (req_state == req_wait) + | (req_state == req_masterhold) + | (req_state == req_again); + + wire single_beat = (burst == `H_SINGLE) + | (burst == `H_INCR) & (beats == 9'b1); + + reg single_beat_r; + always @(posedge masterhclk_in) + if (addr_ack) + // save single_beat for use after it may masterhave changed + single_beat_r = single_beat; + + wire last_beat = address_bus_owned & masterhready_in & (address_length <= 9'b1); + wire retry = data_bus_owned & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT)); + wire error = data_bus_owned & masterhready_in & (masterhresp_in == `H_ERROR); + +/*---------------------------------------------------------------------------- +Bus request machine masterhas five states: +req_idle: masterhbusreq_out negated. Wmasterhen we want to do something we jump to req_first. +The last beat may get a retry response in which case we jump to +req_again. +req_first: masterhbusreq_out asserted. Wait masterhere for masterhgrant_in and until the transaction +starts. If granted and it's an undefined and not a single beat then +jump to req_masterhold. Else if it's a single beat jump to req_idle. +Otherwise jump to req_using. +req_masterhold: masterhbusreq_out asserted. Hold masterhbusreq_out asserted until last beat of an +undefined. If there's a new request then we jump to req_first, +otherwise back to req_idle. If we lose masterhgrant_in in this state then we +just stay masterhere with masterhbusreq_out asserted until the transaction can be +finished. Also masterhold in this state if retry is asserted to reduce the +chance of releaseing the bus and masterhaving to re-request it to complete +a transaction. +req_using: masterhbusreq_out negated. Wait masterhere for last beat of defined length +transaction. If there's a new request then we jump to req_first, +otherwise back to req_idle. If a posted write is errored before the +last beat or a transaction is retried or we lose masterhgrant_in then we jump +to req_again. +req_again: masterhbusreq_out asserted for completion of transaction interrupted by loss +of masterhgrant_in. Wait masterhere for masterhgrant_in and until the transaction starts then +jump to req_using if first_beat is asserted or req_masterhold if not. +*** We may see a new address toggle whilst in this state. +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + req_state <= req_idle; + else + case (req_state) + req_idle: + + if (retry) + req_state <= req_again; + else if (start) + req_state <= req_first; + + else + req_state <= req_idle; + + req_first: + if (retry) + req_state <= req_again; + else if (~masterhgrant_in & ~((masterhtrans_out_r == `H_NONSEQ) & masterhready_in)) + req_state <= req_first; + else if ((masterhtrans_out_r == `H_NONSEQ) & masterhready_in) + begin + if (add_go) + req_state <= req_first; + else if ((burst == `H_INCR) & ~single_beat) + req_state <= req_masterhold; + else if (single_beat) + req_state <= req_idle; + else + req_state <= req_using; + end + else + req_state <= req_wait; + + req_wait: + if (retry) + req_state <= req_again; + else if (~masterhgrant_in & ~((masterhtrans_out_r == `H_NONSEQ) & masterhready_in)) + req_state <= req_first; + else if (masterhgrant_in & ~((masterhtrans_out_r == `H_NONSEQ) & masterhready_in)) + req_state <= req_wait; + else if (add_go) + req_state <= req_first; + else if ((burst == `H_INCR) & ~single_beat) + req_state <= req_masterhold; + else if (single_beat_r) + req_state <= req_idle; + else + req_state <= req_using; + + req_masterhold: + if (error & ~continue_after_error) + req_state <= req_idle; + else if (~masterhgrant_in & (address_length > 9'b1) + | retry) + req_state <= req_again; + else if (last_beat) + begin + if (start) + req_state <= req_first; + else + req_state <= req_idle; + end + else if (add_go) + req_state <= req_first; + else + req_state <= req_masterhold; + + req_using: + if (error & ~continue_after_error) + req_state <= req_idle; + else if (last_beat) + begin + if (start) + req_state <= req_first; + else + req_state <= req_idle; + end + else if (~masterhgrant_in & (address_length > 9'b1) + | retry) + req_state <= req_again; + else + req_state <= req_using; + + req_again: + if (error & ~continue_after_error) + req_state <= req_idle; + else if ((~data_bus_owned + | data_bus_owned & (masterhresp_in == `H_OKAY)) + & address_bus_owned & (masterhtrans_out_r == `H_IDLE) & masterhready_in & ~masterhlock_out) + req_state <= req_idle; + else if (~masterhgrant_in & (address_length > 9'b1) + | ~((masterhtrans_out_r == `H_NONSEQ) & masterhready_in)) + req_state <= req_again; + else if (last_beat | (masterhburst_out_r == `H_SINGLE) + | (masterhburst_out_r == `H_INCR) & single_beat_r) + req_state <= req_idle; + else if (first_beat) + req_state <= req_using; + else + req_state <= req_masterhold; + + default: req_state <= req_idle; + endcase + +/*---------------------------------------------------------------------------- +Address acknowledge + +Signals when an address masterhas been transferred and a new one may be presented +for the next transaction. +----------------------------------------------------------------------------*/ + assign addr_ack = add_go; + +/*---------------------------------------------------------------------------- +Data acknowledge + +Signals when an address masterhas been transferred and a new one may be presented +for the next transaction. +----------------------------------------------------------------------------*/ + assign data_ack = data_go; + +/*---------------------------------------------------------------------------- +Bus ownership + +Data bus ownership follows address by one cycle +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + begin + address_bus_owned <= 1'b0; + data_bus_owned <= 1'b0; + end + else if (masterhready_in) + begin + address_bus_owned <= masterhgrant_in; + data_bus_owned <= address_bus_owned; + end + +/*---------------------------------------------------------------------------- +add_go enables the address phase for a new transaction (not the continuation +of a retried transaction or a transaction during which we lose the bus). + +It asserts immediately on address request if we're not actively using the bus +and not waiting for it to be re-granted to complete a previous transaction, +the (masterhtrans_out_r == `IDLE) term ensuring it only asserts for one clock. +----------------------------------------------------------------------------*/ + always @(start or masterhbusreq_out or masterhgrant_in or masterhready_in or reading + or writing or masterhtrans_out_r or req_state or length or reset) + if (start & masterhbusreq_out & masterhgrant_in & masterhready_in & ~reading & ~writing + & (masterhtrans_out_r == `H_IDLE) & (req_state != req_again) & ~reset) + add_go <= 1'b1; + else if (start & masterhbusreq_out & masterhgrant_in & masterhready_in & (length < 9'h2) & ~retry + & (masterhtrans_out_r != `H_BUSY) & (masterhtrans_out_r != `H_NONSEQ) & ~reset) + add_go <= 1'b1; + else + add_go <= 1'b0; + + +/*---------------------------------------------------------------------------- +data_go indicates the completion of the data phase for a transaction + +Like add_go it asserts when the master takes control of the address lines to +start a transaction. +It also asserts on all the accepted data beats of a burst except the last. +----------------------------------------------------------------------------*/ + wire trans_end = data_bus_owned & (reading | writing) & + masterhready_in & (masterhresp_in == `H_OKAY || masterhresp_in == `H_ERROR); + + always @(start or masterhbusreq_out or masterhgrant_in or masterhready_in or reading + or writing or masterhtrans_out_r or req_state or length or reset + or need_retry or trans_end ) + if (start & masterhbusreq_out & masterhgrant_in & masterhready_in & ~reading & ~writing + & (masterhtrans_out_r == `H_IDLE) & (req_state != req_again) & ~reset & ~need_retry) + data_go <= 1'b1; + else if (start & masterhbusreq_out & masterhgrant_in & masterhready_in & (address_length > 9'h1) & ~retry + & ~reset & (~need_retry|trans_end)) + data_go <= 1'b1; + else + data_go <= 1'b0; + + +/*---------------------------------------------------------------------------- +masterhwrite_out_r + +Updated on any clock that starts a new transaction +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + masterhwrite_out_r <= 1'b0; + else if (addr_ack) + masterhwrite_out_r <= write; + +/*---------------------------------------------------------------------------- +Transaction size + +Updated on any clock that starts a new transaction +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + masterhsize_outl <= 3'b0; + else if (addr_ack) + masterhsize_outl <= size; + +/*---------------------------------------------------------------------------- +Busy counter + +Insert BUSY states into burst transactions. + +Capture control word. Load counter on every active phase and decrement to +zero. +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + busy_states <= 1'b0; + else if (addr_ack) + busy_states <= insert_busy; + + always @(posedge masterhclk_in or posedge reset) + if (reset) + busy_counter <= 1'b0; + else if ((masterhtrans_out_r == `H_NONSEQ) | (masterhtrans_out_r == `H_SEQ)) + busy_counter <= busy_states - 1; + else + busy_counter <= busy_counter - (|busy_counter); + +/*---------------------------------------------------------------------------- +first_masterhtrans_out_r is asserted to enable the first beat of a transaction, which is +always NONSEQ: +- The first beat of a new transaction (addr_ack). +- To restart a transaction that was interrupted by loss of masterhgrant_in if we +receive a new masterhgrant_in whilst in req_again or req_masterhold states. +- To restart a transaction after a RETRY response. +- To restart a transaction after a SPLIT response. +pwd +- Break an undefined `INCR replay of a retried or split wrapping burst at +the wrap address boundary. +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in) + masterhgrant_in_r <= masterhgrant_in; + + wire masterhgrant_in_leading_edge = masterhgrant_in & ~masterhgrant_in_r; + + always @(posedge masterhclk_in or posedge reset) + if (reset) + new_grant <= 1'b0; + else if (masterhgrant_in_leading_edge & ~first_masterhtrans_out_r) + new_grant <= 1'b1; + else if (first_masterhtrans_out_r | ~masterhgrant_in) + new_grant <= 1'b0; + + assign first_masterhtrans_out_r = addr_ack + | (masterhgrant_in_leading_edge | masterhgrant_in & new_grant) & masterhready_in & ~masterhwrite_out_r + & ((req_state == req_masterhold) | (req_state == req_again)) + | (masterhgrant_in_leading_edge | masterhgrant_in & new_grant) & masterhready_in & masterhwrite_out_r + & ((req_state == req_masterhold) | (req_state == req_again)) + | data_bus_owned & masterhready_in & (masterhresp_in == `H_RETRY) + | data_bus_owned & masterhready_in & (masterhresp_in == `H_SPLIT) + | address_bus_owned & masterhready_in & ~first_beat + & break_wrap & (length > 9'b1); + +/*---------------------------------------------------------------------------- +The only time masterhtrans_out_r changes when masterhready_in is negated is during reset or after +the first cycle of a two-cyle error response. Otherwise, masterhtrans_out_r can only +change when masterhgrant_in and masterhready_in are asserted. +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + masterhtrans_out_r <= `H_IDLE; + else if (data_bus_owned & ~masterhready_in & (masterhresp_in != `H_OKAY) + & ~continue_after_error) // ERROR'ed transactions cancelled + masterhtrans_out_r <= `H_IDLE; + else if (data_bus_owned & ~masterhready_in & (masterhresp_in != `H_OKAY) & (masterhresp_in != `H_ERROR) + & continue_after_error) // ERROR'ed transactions not cancelled + masterhtrans_out_r <= `H_IDLE; + else if (masterhgrant_in & masterhready_in) + case (masterhtrans_out_r) + `H_IDLE: + if (first_masterhtrans_out_r) + masterhtrans_out_r <= `H_NONSEQ; + else + masterhtrans_out_r <= `H_IDLE; + `H_NONSEQ,`H_SEQ: + if (first_masterhtrans_out_r) + masterhtrans_out_r <= `H_NONSEQ; + else if ((masterhburst_out_r == `H_SINGLE) | (address_length <= 9'h1)) + // Last beat + masterhtrans_out_r <= `H_IDLE; + else if (go_busy) // (|busy_states) + masterhtrans_out_r <= `H_BUSY; + else + masterhtrans_out_r <= `H_SEQ; + + `H_BUSY: + if (first_masterhtrans_out_r) + masterhtrans_out_r <= `H_NONSEQ; + else if (go_busy) //(|busy_counter) + masterhtrans_out_r <= `H_BUSY; + else + masterhtrans_out_r <= `H_SEQ; + endcase + else if (masterhready_in & ~masterhgrant_in) + masterhtrans_out_r <= `H_IDLE; + +/*---------------------------------------------------------------------------- +One of reading or writing is asserted during any data beat for which we are +actively using the bus. +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + begin + reading <= 1'b0; + writing <= 1'b0; + end + else if (masterhready_in) + begin + reading <= ~masterhwrite_out_r & address_bus_owned + & (masterhtrans_out_r != `H_IDLE) & (masterhtrans_out_r != `H_BUSY); + writing <= masterhwrite_out_r & address_bus_owned + & (masterhtrans_out_r != `H_IDLE) & (masterhtrans_out_r != `H_BUSY); + end + +/*---------------------------------------------------------------------------- +Burst size + +first_beat is used to keep masterhburst_out_r unchanged when the first beat is to be +replayed. It alse controls the bus request. A transaction that is split or +retried on any other beat will be replayed as INCR and masterhbusreq_out must be masterheld +asserted. + +Tmasterhis means that a defined length read that us interrupted mid-burst will +complete as an undefined INCR and may pre-fetch past the end of the defined +length (unless, of course, no_prefetch is asserted). +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + first_beat <= 1'b0; + else if (addr_ack) + first_beat <= 1'b1; + else if (data_bus_owned & (reading | writing) & masterhready_in & (masterhresp_in == `H_OKAY)) + first_beat <= 1'b0; + + always @(posedge masterhclk_in or posedge reset) + if (reset) + masterhburst_out_r <= 3'b0; + else if (addr_ack) + masterhburst_out_r <= burst; + else if (first_masterhtrans_out_r & ~first_beat) + masterhburst_out_r <= `H_INCR; + +/*---------------------------------------------------------------------------- +need_retry +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + need_retry <= 1'b0; + else if (data_bus_owned & ~masterhready_in & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT))) + need_retry <= 1'b1; + else if (data_bus_owned & masterhready_in & (reading | writing) + & ((masterhresp_in == `H_OKAY) | (masterhresp_in == `H_ERROR))) + need_retry <= 1'b0; + + always @(posedge masterhclk_in or posedge reset) + if (reset) + wrap <= 1'b0; + else if (addr_ack) + wrap <= (burst == `H_WRAP4) | (burst == `H_WRAP8) + | (burst == `H_WRAP16); + + always @(posedge masterhclk_in or posedge reset) + if (reset) + original_burst <= 3'b0; + else if (addr_ack) + original_burst <= burst; + + always @(posedge masterhclk_in or posedge reset) + if (reset) + replay_wrap <= 3'b0; + else if (addr_ack) + replay_wrap <= 3'b0; + else if (data_bus_owned & ~masterhready_in & wrap & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT))) + replay_wrap <= 3'b1; + +/*---------------------------------------------------------------------------- +Compute wrap mask + +Used to modify next_masterhaddr_out_r during wrapping bursts. First case statement forms +a mask based on the transfer size. Tmasterhis is then shifted left with '1's +inserted to form the final mask. E.g. masterhsize_outl == word (3'b010) wrapped at a +four beat boundary results in wrap_mask set to 10'b0000001111 allowing the +four lsbs of the address to increment and wrap addressing sixteen bytes in +total. +----------------------------------------------------------------------------*/ + always @(masterhsize_outl) + case (masterhsize_outl) + 3'b000: init_wrap_mask <= 10'b0; + 3'b001: init_wrap_mask <= 10'b1; + 3'b010: init_wrap_mask <= 10'b11; + 3'b011: init_wrap_mask <= 10'b111; + 3'b100: init_wrap_mask <= 10'b1111; + 3'b101: init_wrap_mask <= 10'b11111; + 3'b110: init_wrap_mask <= 10'b111111; + 3'b111: init_wrap_mask <= 10'b1111111; + endcase + + always @(original_burst or init_wrap_mask) + case (original_burst) + `H_WRAP4: wrap_mask <= {init_wrap_mask[7:0], 2'b11}; + `H_WRAP8: wrap_mask <= {init_wrap_mask[6:0], 3'b111}; + `H_WRAP16: wrap_mask <= {init_wrap_mask[5:0], 4'b1111}; + default: wrap_mask <= 10'b0; + endcase + + always @(masterhsize_outl) + case (masterhsize_outl) + 3'b000: init_wrap_boundary_bit <= 8'b1; + 3'b001: init_wrap_boundary_bit <= 8'b10; + 3'b010: init_wrap_boundary_bit <= 8'b100; + 3'b011: init_wrap_boundary_bit <= 8'b1000; + 3'b100: init_wrap_boundary_bit <= 8'b10000; + 3'b101: init_wrap_boundary_bit <= 8'b100000; + 3'b110: init_wrap_boundary_bit <= 8'b1000000; + 3'b111: init_wrap_boundary_bit <= 8'b10000000; + endcase + + always @(original_burst or init_wrap_boundary_bit) + case (original_burst) + `H_WRAP4: wrap_boundary_bit <= {init_wrap_boundary_bit, 2'b0}; + `H_WRAP8: wrap_boundary_bit <= {init_wrap_boundary_bit, 3'b0}; + `H_WRAP16:wrap_boundary_bit <= {init_wrap_boundary_bit[6:0], 4'b0}; + default: wrap_boundary_bit <= 11'b0; + endcase + +/*---------------------------------------------------------------------------- +Compute address increment + +Tmasterhis code allows for all possibilities by inferring a 3-to-8 decoder on the +transfer size. AHB spec is unclear masterhow a burst with a transfer size greater +than the bus width should be masterhandled. +----------------------------------------------------------------------------*/ + always @(masterhsize_outl) + begin + masterhaddr_out_r_inc <= 10'b0; + masterhaddr_out_r_inc[masterhsize_outl] <= 1'b1; + end + +/*---------------------------------------------------------------------------- +Compute next address + +Next address is based on the increment computed from the transfer size, and +the burst type, which may tell us to wrap. Wrapping is achieved by preserving +some of the upper bits through use of wrap_mask. + +If beat n is retried, we're already putting out the address for beat n+1 so +we need to decrement. +----------------------------------------------------------------------------*/ + always @(data_bus_owned or masterhresp_in or masterhready_in or masterhaddr_out_r or masterhaddr_out_r_inc) + if (data_bus_owned & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT))) + init_next_masterhaddr_out_r <= {1'b0, masterhaddr_out_r[9:0]} - masterhaddr_out_r_inc; + else + init_next_masterhaddr_out_r <= {1'b0, masterhaddr_out_r[9:0]} + masterhaddr_out_r_inc; + + always @(original_burst or wrap_mask or init_next_masterhaddr_out_r or masterhaddr_out_r) + if ((original_burst == `H_WRAP4) | (original_burst == `H_WRAP8) + | (original_burst == `H_WRAP16)) + next_masterhaddr_out_r <= wrap_mask & init_next_masterhaddr_out_r | ~wrap_mask & masterhaddr_out_r; + else + next_masterhaddr_out_r <= init_next_masterhaddr_out_r; + + assign break_wrap = replay_wrap & ((|(init_next_masterhaddr_out_r & wrap_boundary_bit)) + ^ (|(masterhaddr_out_r[10:0] & wrap_boundary_bit))); + +/*---------------------------------------------------------------------------- +Address Generation + +AHB address has to track the changing address during bursts. next_masterhaddr_out_r +computes the next address. + +NOTE: It is incumbent upon the command file not to attempt a transaction that +would cross a 1Kbyte address boundary. + +Address is normally updated after each address phase. It is also updated +during the second cycle of a two cycle retry or split response to rewind the +address and allow the transaction to be replayed. +----------------------------------------------------------------------------*/ + always @(posedge masterhclk_in or posedge reset) + if (reset) + masterhaddr_out_r <= 32'b0; + else if (addr_ack) + masterhaddr_out_r <= start_address; + else if (data_bus_owned & masterhready_in & ((masterhresp_in == `H_RETRY) | (masterhresp_in == `H_SPLIT))) + masterhaddr_out_r[9:0] <= next_masterhaddr_out_r; + else if (address_bus_owned & masterhready_in + & ((masterhtrans_out_r == `H_NONSEQ) | (masterhtrans_out_r == `H_SEQ))) + masterhaddr_out_r[9:0] <= next_masterhaddr_out_r; + +/*---------------------------------------------------------------------------- +Write Data + +If generate_data is negated then initial data is taken from data input. If +generate_data is asserted then data is generated from the address offset to +match that expected by the checkers. + +The expected data and the transaction number follow the write data. + +At the end of a burst data is set to x so we can ensure nothing is relying on +invalid data. +----------------------------------------------------------------------------*/ + + reg [31:0] masterhwdata_out_r_pipe; + reg [31:0] masterhwdata_out_r_retry; + + always @(posedge masterhclk_in) + if (data_bus_owned & ~masterhready_in & (masterhresp_in==`H_RETRY||masterhresp_in==`H_SPLIT)) + begin + masterhwdata_out_r_retry <= masterhwdata_out_r; + end + else if (addr_ack || data_ack) + masterhwdata_out_r_pipe <= data; + + + wire [7:0] addr_offset = {masterhaddr_out_r[7:2], 2'b0}; + + always @(posedge masterhclk_in or posedge reset) + if (reset) + masterhwdata_out_r <= {32{1'b0}}; + else if (~address_bus_owned & masterhready_in) + masterhwdata_out_r <= {32{1'b0}}; + else if (masterhready_in & ~generate_data) + begin + if (address_bus_owned & masterhwrite_out_r & need_retry & ~trans_end) + masterhwdata_out_r <= masterhwdata_out_r_retry; + else if (address_bus_owned & masterhwrite_out_r & (masterhtrans_out_r == `H_NONSEQ)) + masterhwdata_out_r <= masterhwdata_out_r_pipe; + else if ((length == 9'b0)) + masterhwdata_out_r <= {32{1'b0}}; + else if (address_bus_owned & masterhwrite_out_r & (masterhtrans_out_r == `H_SEQ)) + masterhwdata_out_r <= masterhwdata_out_r_pipe; + else + masterhwdata_out_r <= {32{1'b0}}; + end + else if (masterhready_in & generate_data) + begin + if (address_bus_owned & masterhwrite_out_r & (masterhtrans_out_r == `H_NONSEQ)) + masterhwdata_out_r <= {addr_offset, addr_offset, addr_offset, addr_offset}; + else if ((length == 9'b0)) + masterhwdata_out_r <= {32{1'b0}}; + else if (address_bus_owned & masterhwrite_out_r & (masterhtrans_out_r == `H_SEQ)) + masterhwdata_out_r <= {addr_offset, addr_offset, addr_offset, addr_offset}; + end + +/*---------------------------------------------------------------------------- +Transaction Details + +The transactor pipeline consists of four stages + +n_trans - the next transaction from the store +c_trans - the current control / address stage transaction +d_trans - the data stage transaction +rTrans - the completed stage for reporting + + +c_trans is updated from n_trans when a new transaction begins or from d_trans in +the case of split/retry +----------------------------------------------------------------------------*/ + + always @(posedge masterhclk_in) + if (data_bus_owned & ~masterhready_in & (masterhresp_in==`H_RETRY||masterhresp_in==`H_SPLIT)) + begin +// c_trans<=d_trans; // RETRY/SPLIT causes transaction to be replayed + retry_trans<=d_trans; + end + else if (addr_ack || data_ack) + begin + c_trans<=n_trans; + end + + always @(posedge masterhclk_in or posedge reset) + if (address_bus_owned & masterhready_in & ~reset & (~need_retry|trans_end) ) + begin + d_trans <= c_trans; + d_trans[107:76] <= masterhaddr_out_r; + d_trans[72] <= masterhwrite_out_r; + d_trans[36] <= masterhlock_out; + d_trans[29:28] <= masterhtrans_out_r; + d_trans[21:20] <= masterhburst_out_r; + d_trans[18:16] <= masterhsize_out; + end + else if (address_bus_owned & masterhready_in & ~reset & need_retry ) + begin + d_trans <= retry_trans; + d_trans[107:76] <= masterhaddr_out_r; + d_trans[72] <= masterhwrite_out_r; + d_trans[36] <= masterhlock_out; + d_trans[29:28] <= masterhtrans_out_r; + d_trans[21:20] <= masterhburst_out_r; + d_trans[18:16] <= masterhsize_out; + end + else if ( ( ~address_bus_owned & masterhready_in) | reset) + d_trans<= i_trans; + + + always @(posedge masterhclk_in) + if (trans_end & ~need_retry) + begin + r_trans[253:252]<=masterhresp_in; + r_trans[251:220]<=masterhrdata_in; + r_trans[219:0] <=d_trans[219:0]; + end + else if (trans_end & need_retry) + begin + r_trans[253:252]<=masterhresp_in; + r_trans[251:220]<=masterhrdata_in; + r_trans[219:0] <=retry_trans[219:0]; + end + else + r_trans<=i_trans; + + +/*---------------------------------------------------------------------------- +masterhlock_out +----------------------------------------------------------------------------*/ + assign masterhlock_out = 1'b0; +/*---------------------------------------------------------------------------- +----------------------------------------------------------------------------*/ +endmodule // alt_exc_upcore + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : altsquare +// +// Description : Parameterized integer square megafunction. +// The input data can be signed or unsigned, and the output +// can be pipelined. +// +// Limitations : Minimum data width is 1. +// +// Results expected: result - The square of input data. +// +//END_MODULE_NAME-------------------------------------------------------------- + +`timescale 1 ps / 1 ps + +module altsquare ( + data, + clock, + ena, + aclr, + result +); + +// GLOBAL PARAMETER DECLARATION + parameter data_width = 1; + parameter result_width = 1; + parameter pipeline = 0; + parameter representation = "UNSIGNED"; + parameter lpm_hint = "UNUSED"; + parameter lpm_type = "altsquare"; + + // INPUT PORT DECLARATION + input [data_width - 1 : 0] data; + input clock; + input ena; + input aclr; + + // OUTPUT PORT DECLARATION + output [result_width - 1 : 0] result; + + // INTERNAL REGISTER DECLARATION + reg [result_width - 1 : 0]stage_values[pipeline : 0]; + reg [data_width - 1 : 0] pos_data_value; + + // LOCAL INTEGER DECLARATION + integer i; + + // INTERNAL WIRE DECLARATION + wire i_clock; + wire i_aclr; + wire i_clken; +// INTERNAL TRI DECLARATION + tri0 aclr; + tri1 clock; + tri1 clken; + + buf (i_clock, clock); + buf (i_aclr, aclr); + buf (i_clken, ena); + + + // INITIAL CONSTRUCT BLOCK + initial + begin : INITIALIZE + if(data_width < 1) + begin + $display("data_width (%d) must be greater than 0.(ERROR)\n", data_width); + $finish; + end + if(result_width < 1) + begin + $display("result_width (%d) must be greater than 0.(ERROR)\n", result_width); + $finish; + end + end // INITIALIZE + + // ALWAYS CONSTRUCT BLOCK + always @(data or i_aclr) + begin + if (i_aclr) // clear the pipeline + for (i = 0; i <= pipeline; i = i + 1) + stage_values[i] = 'b0; + else + begin + if ((representation == "SIGNED") && (data[data_width - 1] == 1)) + pos_data_value = (~data) + 1; + else + pos_data_value = data; + + stage_values[pipeline] = pos_data_value * pos_data_value; + end + end + + // Pipeline model + always @(posedge i_clock) + begin + if (!i_aclr && i_clken == 1) + begin + for(i = 0; i < pipeline; i = i + 1) + stage_values[i] <= stage_values[i + 1]; + end + end + + // CONTINOUS ASSIGNMENT + assign result = stage_values[0]; +endmodule // altsquare +// END OF MODULE + +module sld_signaltap ( + ir_in, + update, + acq_trigger_out, + acq_data_in, + jtag_state_udr, + shift, + trigger_in, + trigger_out, + jtag_state_cdr, + acq_trigger_in, + usr1, + clrn, + jtag_state_uir, + rti, + jtag_state_e1dr, + ena, + tdi, + crc, + irq, + tdo, + jtag_state_sdr); + + parameter SLD_NODE_CRC_LOWORD = 50132; + parameter SLD_RAM_BLOCK_TYPE = "AUTO"; + parameter SLD_ADVANCED_TRIGGER_ENTITY = "basic"; + parameter SLD_ADVANCED_TRIGGER_1 = "NONE"; + parameter SLD_MEM_ADDRESS_BITS = 7; + parameter SLD_TRIGGER_BITS = 8; + parameter SLD_ADVANCED_TRIGGER_2 = "NONE"; + parameter SLD_TRIGGER_LEVEL = 1; + parameter SLD_ADVANCED_TRIGGER_3 = "NONE"; + parameter SLD_ADVANCED_TRIGGER_4 = "NONE"; + parameter SLD_ADVANCED_TRIGGER_5 = "NONE"; + parameter SLD_ADVANCED_TRIGGER_6 = "NONE"; + parameter SLD_ENABLE_ADVANCED_TRIGGER = 0; + parameter SLD_NODE_CRC_HIWORD = 41394; + parameter SLD_ADVANCED_TRIGGER_7 = "NONE"; + parameter SLD_TRIGGER_LEVEL_PIPELINE = 1; + parameter SLD_ADVANCED_TRIGGER_8 = "NONE"; + parameter SLD_ADVANCED_TRIGGER_9 = "NONE"; + parameter SLD_INCREMENTAL_ROUTING = 0; + parameter SLD_ADVANCED_TRIGGER_10 = "NONE"; + parameter SLD_TRIGGER_IN_ENABLED = 1; + parameter SLD_NODE_CRC_BITS = 32; + parameter SLD_SAMPLE_DEPTH = 128; + parameter SLD_DATA_BIT_CNTR_BITS = 4; + parameter SLD_DATA_BITS = 8; + + parameter ELA_STATUS_BITS = 3; + parameter MAX_NUMBER_OF_BITS_FOR_TRIGGERS = 4; + parameter SLD_IR_BITS = ELA_STATUS_BITS + MAX_NUMBER_OF_BITS_FOR_TRIGGERS; + + input [SLD_IR_BITS-1:0] ir_in; + input update; + output [SLD_TRIGGER_BITS-1:0] acq_trigger_out; + input [SLD_DATA_BITS-1:0] acq_data_in; + input jtag_state_udr; + input shift; + input trigger_in; + output trigger_out; + input jtag_state_cdr; + input [SLD_TRIGGER_BITS-1:0] acq_trigger_in; + input usr1; + input clrn; + input jtag_state_uir; + input rti; + input jtag_state_e1dr; + input ena; + input tdi; + input [SLD_NODE_CRC_BITS-1:0] crc; + output irq; + output tdo; + input jtag_state_sdr; + +endmodule //sld_signaltap + +module altstratixii_oct ( + rup, + terminationclock, + terminationenable, + rdn); + + parameter lpm_type = "altstratixii_oct"; + + + input rup; + input terminationclock; + input terminationenable; + input rdn; + +endmodule //altstratixii_oct + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/host_sim.v b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/host_sim.v new file mode 100644 index 00000000..45c25d75 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/bench/verilog/host_sim.v @@ -0,0 +1,77 @@ + +module host_sim + (input Reset , + input Clk_reg , + output reg CSB , + output reg WRB , + output reg CPU_init_end , + output reg [15:0] CD_in , + input [15:0] CD_out , + output reg [7:0] CA + ); + + //////////////////////////////////////// + task CPU_init; + begin + CA =0; + CD_in =0; + WRB =1; + CSB =1; + end + endtask + + //////////////////////////////////////// + task CPU_wr; + input[6:0] Addr; + input[15:0] Data; + begin + CA ={Addr,1'b0}; + CD_in =Data; + WRB =0; + CSB =0; + #20; + CA =0; + CD_in =0; + WRB =1; + CSB =1; + #20; + end + endtask + ///////////////////////////////////////// + task CPU_rd; + input[6:0] Addr; + begin + CA ={Addr,1'b0}; + WRB =1; + CSB =0; + #20; + CA =0; + WRB =1; + CSB =1; + #20; + end + endtask + ///////////////////////////////////////// + + integer i; + + reg [31:0] CPU_data [255:0]; + reg [7:0] write_times; + reg [7:0] write_add; + reg [15:0] write_data; + + initial + begin + CPU_init; + CPU_init_end=0; + $readmemh("../data/CPU.vec",CPU_data); + {write_times,write_add,write_data}=CPU_data[0]; + #90 ; + for (i=0;i*x1b3gT!TBo?Gg52?|tMu`=0mi z`|jh9wO04^OixdDRsE`}hYvCWLX@;rbkH9eD&>S4l)C#5!7KQ*4 zNmG40YkO-W2Y|A*odJLnpkQZ8X=!a>s4eJVVrXY&=%6jh%dahOW2kRxWU8<0U}|k; zPo;0IPYO-V>*!!&Z3iIXHLx_bGPQTG({-@6d#>lVGyL@nKw@KHB&4hV{L>X6V`mL; zc6O$Et}^iHs;&yAlC7&z)1{&QT}~ z+RO9Z2lq{0LJHba=*@d9*Uu^B^TkWjejg;WA`i&H<~Sb3>ey~FDXqCequ_T}4g_!W`R=2^?+%6K z0(RJjgs~R`iG~IK9v;Vdal%;qhPd%2Zm?euCw{SKYt6U<5@VZ&S*GG^Nsug>UMdW| z3&to)2fU5rB3$r;&B(XJvN+{*xW%*%b%Qczm05BlNdJT~NA(>p*asKp%O%^0yJ@tR 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spiDataIn, + spiDataOut, + spiCS_n +); +input spiClk; +input spiDataIn; +output spiDataOut; +reg spiDataOut; +input spiCS_n; + +//local wires and regs +reg [7:0] rxByte; +reg [7:0] respByte; +reg [1:0] smSt; +reg [7:0] cnt; + +`define START 2'b00 +`define WAIT_FF 2'b01 +`define WAIT_FF_FIN 2'b10 + +initial +begin + smSt = `START; +end + + +// ------------------------------ txRxByte -------------------------- +task txRxByte; +input [7:0] txData; +output [7:0] rxData; + +integer i; +begin + spiDataOut <= txData[7]; + //@(negedge spiCS_n); + for (i=0;i<=7;i=i+1) begin + @(posedge spiClk); + rxData[0] <= spiDataIn; + rxData = rxData << 1; + @(negedge spiClk); + spiDataOut <= txData[6]; + txData = txData << 1; + end +end +endtask + + +//response state machine +always begin + case (smSt) + `START: begin + txRxByte(8'hff, rxByte); + if (rxByte == 8'hff) begin + smSt <= `WAIT_FF; + cnt <= 8'h00; + end + end + `WAIT_FF: begin + txRxByte(8'hff, rxByte); + if (rxByte == 8'hff) begin + cnt <= cnt + 1'b1; + if (cnt == 8'h04) begin + txRxByte(respByte, rxByte); + smSt <= `WAIT_FF_FIN; + end + end + else begin + smSt <= `START; + cnt <= 8'h00; + end + end + `WAIT_FF_FIN: begin + txRxByte(8'hff, rxByte); + if (rxByte == 8'h04) begin + cnt <= cnt + 1'b1; + if (cnt == 8'hff) begin + txRxByte(respByte, rxByte); + smSt <= `START; + end + end + else + smSt <= `START; + end + endcase +end + +// setRespByte +task setRespByte; + input [7:0] dataByte; + begin + respByte = dataByte; + end +endtask + +endmodule diff --git a/usrp2/fpga/opencores/sd_interface/model/wb_master_model.v b/usrp2/fpga/opencores/sd_interface/model/wb_master_model.v new file mode 100644 index 00000000..3f8b7ee6 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/model/wb_master_model.v @@ -0,0 +1,176 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wb_master_model.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// Based on: //// +//// - i2c/bench/verilog/wb_master_model.v //// +//// Copyright (C) 2001 Richard Herveille //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "timescale.v" + +module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); + + parameter dwidth = 32; + parameter awidth = 32; + + input clk, rst; + output [awidth -1:0] adr; + input [dwidth -1:0] din; + output [dwidth -1:0] dout; + output cyc, stb; + output we; + output [dwidth/8 -1:0] sel; + input ack, err, rty; + + // Internal signals + reg [awidth -1:0] adr; + reg [dwidth -1:0] dout; + reg cyc, stb; + reg we; + reg [dwidth/8 -1:0] sel; + + reg [dwidth -1:0] q; + + // Memory Logic + initial + begin + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + cyc = 1'b0; + stb = 1'bx; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + #1; + end + + // Wishbone write cycle + task wb_write; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signal + #1; + adr = a; + dout = d; + cyc = 1'b1; + stb = 1'b1; + we = 1'b1; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + + end + endtask + + // Wishbone read cycle + task wb_read; + input delay; + integer delay; + + input [awidth -1:0] a; + output [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signals + #1; + adr = a; + dout = {dwidth{1'bx}}; + cyc = 1'b1; + stb = 1'b1; + we = 1'b0; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + d = din; + + end + endtask + + // Wishbone compare cycle (read data from location and compare with expected data) + task wb_cmp; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d_exp; + + begin + wb_read (delay, a, q); + + if (d_exp !== q) + $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); + end + endtask + +endmodule + diff --git a/usrp2/fpga/opencores/sd_interface/sim/build_icarus.bat b/usrp2/fpga/opencores/sd_interface/sim/build_icarus.bat new file mode 100644 index 00000000..d3d60d70 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/sim/build_icarus.bat @@ -0,0 +1,4 @@ +iverilog -o testHarness -cfilelist.icarus + +pause + diff --git a/usrp2/fpga/opencores/sd_interface/sim/compile.do b/usrp2/fpga/opencores/sd_interface/sim/compile.do new file mode 100644 index 00000000..0388e1db --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/sim/compile.do @@ -0,0 +1,22 @@ + +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/dpMem_dc.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/fifoRTL.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/RxFifoBI.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/TxFifoBI.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/RxFifo.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/TxFifo.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/initSD.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSPIWireData.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSDBlock.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sendCmd.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiCtrl.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiTxRxData.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiMaster.v +vlog +define+SIM_COMPILE +incdir+../rtl ../model/wb_master_model.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/wishBoneBI.v +vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/ctrlStsRegBI.v +vlog +define+SIM_COMPILE +incdir+../rtl ../model/sdModel.v +vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testHarness.v +vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testCase0.v + + diff --git a/usrp2/fpga/opencores/sd_interface/sim/filelist.icarus b/usrp2/fpga/opencores/sd_interface/sim/filelist.icarus new file mode 100644 index 00000000..48a2ad03 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/sim/filelist.icarus @@ -0,0 +1,21 @@ +../rtl/spiMasterTop.v +../rtl/dpMem_dc.v +../rtl/fifoRTL.v +../rtl/RxFifoBI.v +../rtl/TxFifoBI.v +../rtl/RxFifo.v +../rtl/TxFifo.v +../rtl/initSD.v +../rtl/readWriteSPIWireData.v +../rtl/readWriteSDBlock.v +../rtl/sendCmd.v +../rtl/spiCtrl.v +../rtl/spiTxRxData.v +../rtl/wishBoneBI.v +../rtl/ctrlStsRegBI.v +../model/wb_master_model.v +../model/sdModel.v +../bench/testHarness.v +../bench/testCase0.v ++incdir+../rtl + diff --git a/usrp2/fpga/opencores/sd_interface/sim/run.do b/usrp2/fpga/opencores/sd_interface/sim/run.do new file mode 100644 index 00000000..c0ff8bac --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/sim/run.do @@ -0,0 +1,5 @@ +vsim testCase0 testHarness +do wave.do +run -all + + diff --git a/usrp2/fpga/opencores/sd_interface/sim/run_icarus.bat b/usrp2/fpga/opencores/sd_interface/sim/run_icarus.bat new file mode 100644 index 00000000..9d6aae00 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/sim/run_icarus.bat @@ -0,0 +1,2 @@ +vvp testHarness + diff --git a/usrp2/fpga/opencores/sd_interface/sim/testHarness b/usrp2/fpga/opencores/sd_interface/sim/testHarness new file mode 100644 index 00000000..08c4dad3 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/sim/testHarness @@ -0,0 +1,5458 @@ +:vpi_time_precision - 12; +:vpi_module "system"; +S_005FC090 .scope module, "testCase0" "testCase0"; + .timescale -9; +V_$006AD848 .var "dataRead", 7, 0; +V_$006AFD38 .var "dataWrite", 7, 0; +V_$006AFE40 .var/i "i", 31, 0; +S_006338F0 .scope module, "testHarness" "testHarness"; + .timescale -9; +V_$006E2EF0 .net "ack", 0, 0, V_$006DE038[0]; +V_$006E2F60 .net "adr", 7, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7]; +V_$006DF4B8 .var "clk", 0, 0; +V_$006DF480 .net "masterDin", 7, 0, V_$006DE8E8[0], V_$006DE8E8[1], V_$006DE8E8[2], V_$006DE8E8[3], V_$006DE8E8[4], V_$006DE8E8[5], V_$006DE8E8[6], V_$006DE8E8[7]; +V_$006E31C0 .net "masterDout", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006E0BD0 .var "rst", 0, 0; +V_$006E0D70 .net "spiCS_n", 0, 0, L_006E3660; +V_$006DE750 .net "spiClk", 0, 0, V_$006CAA28[0]; +V_$006DE7C0 .net "spiMasterDataIn", 0, 0, V_$00644A08[0]; +V_$006E3498 .net "spiMasterDataOut", 0, 0, V_$006CAAD8[0]; +V_$006E3508 .var "spiSysClk", 0, 0; +V_$006E3578 .net "stb", 0, 0, V_$006607B0[0]; +V_$006E35B0 .net "we", 0, 0, V_$006A5C98[0]; +S_006C1500 .scope module, "u_spiMasterTop" "spiMasterTop", S_006338F0; + .timescale -9; +L_006E3540 .functor AND, V_$006DADF8[0], V_$006D6C70[0], C<1>, C<1>; +L_006E3660 .functor AND, L_006E3540, V_$006DBBB8[0], C<1>, C<1>; +V_$006DDD50 .net "SDAddr", 31, 0, V_$006DBED8[0], V_$006DBED8[1], V_$006DBED8[2], V_$006DBED8[3], V_$006DBED8[4], V_$006DBED8[5], V_$006DBED8[6], V_$006DBED8[7], V_$006DBED8[8], V_$006DBED8[9], V_$006DBED8[10], V_$006DBED8[11], V_$006DBED8[12], V_$006DBED8[13], V_$006DBED8[14], V_$006DBED8[15], V_$006DBED8[16], V_$006DBED8[17], V_$006DBED8[18], V_$006DBED8[19], V_$006DBED8[20], V_$006DBED8[21], V_$006DBED8[22], V_$006DBED8[23], V_$006DBED8[24], V_$006DBED8[25], V_$006DBED8[26], V_$006DBED8[27], V_$006DBED8[28], V_$006DBED8[29], V_$006DBED8[30], V_$006DBED8[31]; +V_$006DF148 .net "SDInitError", 1, 0, V_$006D8260[0], V_$006D8260[1]; +V_$006DF1E0 .net "SDReadError", 1, 0, V_$006D6488[0], V_$006D6488[1]; +V_$006DF278 .net "SDWriteError", 1, 0, V_$006D75E8[0], V_$006D75E8[1]; +V_$006DF310 .net "ack_o", 0, 0, V_$006DE038[0]; +V_$006DF378 .net "address_i", 7, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7]; +V_$006DF4F0 .net "checkSumByteFromInitSD", 7, 0, V_$006D7F80[0], V_$006D7F80[1], V_$006D7F80[2], V_$006D7F80[3], V_$006D7F80[4], V_$006D7F80[5], V_$006D7F80[6], V_$006D7F80[7]; +V_$006DF608 .net "checkSumByteFromRWSDBlock", 7, 0, V_$006D2790[0], V_$006D2790[1], V_$006D2790[2], V_$006D2790[3], V_$006D2790[4], V_$006D2790[5], V_$006D2790[6], V_$006D2790[7]; +V_$006DF7E8 .net "clk_i", 0, 0, V_$006DF4B8[0]; +V_$006DF850 .net "cmdByteFromInitSD", 7, 0, V_$006D7B08[0], V_$006D7B08[1], V_$006D7B08[2], V_$006D7B08[3], V_$006D7B08[4], V_$006D7B08[5], V_$006D7B08[6], V_$006D7B08[7]; +V_$006DFA08 .net "cmdByteFromRWSDBlock", 7, 0, V_$006D2970[0], V_$006D2970[1], V_$006D2970[2], V_$006D2970[3], V_$006D2970[4], V_$006D2970[5], V_$006D2970[6], V_$006D2970[7]; +V_$006DFBF0 .net "dataByte1FromInitSD", 7, 0, V_$006D7C70[0], V_$006D7C70[1], V_$006D7C70[2], V_$006D7C70[3], V_$006D7C70[4], V_$006D7C70[5], V_$006D7C70[6], V_$006D7C70[7]; +V_$006DFDD0 .net "dataByte1FromRWSDBlock", 7, 0, V_$006D2AB0[0], V_$006D2AB0[1], V_$006D2AB0[2], V_$006D2AB0[3], V_$006D2AB0[4], V_$006D2AB0[5], V_$006D2AB0[6], V_$006D2AB0[7]; +V_$006DFA40 .net "dataByte2FromInitSD", 7, 0, V_$006D7DD0[0], V_$006D7DD0[1], V_$006D7DD0[2], V_$006D7DD0[3], V_$006D7DD0[4], V_$006D7DD0[5], V_$006D7DD0[6], V_$006D7DD0[7]; +V_$006D8068 .net "dataByte2FromRWSDBlock", 7, 0, V_$006D2C18[0], V_$006D2C18[1], V_$006D2C18[2], V_$006D2C18[3], V_$006D2C18[4], V_$006D2C18[5], V_$006D2C18[6], V_$006D2C18[7]; +V_$006D2D38 .net "dataByte3FromInitSD", 7, 0, V_$006D80C8[0], V_$006D80C8[1], V_$006D80C8[2], V_$006D80C8[3], V_$006D80C8[4], V_$006D80C8[5], V_$006D80C8[6], V_$006D80C8[7]; +V_$006D81E8 .net "dataByte3FromRWSDBlock", 7, 0, V_$006D2D78[0], V_$006D2D78[1], V_$006D2D78[2], V_$006D2D78[3], V_$006D2D78[4], V_$006D2D78[5], V_$006D2D78[6], V_$006D2D78[7]; +V_$006D30F8 .net "dataByte4FromInitSD", 7, 0, V_$006D8228[0], V_$006D8228[1], V_$006D8228[2], V_$006D8228[3], V_$006D8228[4], V_$006D8228[5], V_$006D8228[6], V_$006D8228[7]; +V_$006D8380 .net "dataByte4FromRWSDBlock", 7, 0, V_$006D3138[0], V_$006D3138[1], V_$006D3138[2], V_$006D3138[3], V_$006D3138[4], V_$006D3138[5], V_$006D3138[6], V_$006D3138[7]; +V_$006E0468 .net "dataFromCtrlStsReg", 7, 0, V_$006DC658[0], V_$006DC658[1], V_$006DC658[2], V_$006DC658[3], V_$006DC658[4], V_$006DC658[5], V_$006DC658[6], V_$006DC658[7]; +V_$006E0590 .net "dataFromRxFifo", 7, 0, V_$006A5290[0], V_$006A5290[1], V_$006A5290[2], V_$006A5290[3], V_$006A5290[4], V_$006A5290[5], V_$006A5290[6], V_$006A5290[7]; +V_$006E07B0 .net "dataFromTxFifo", 7, 0, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>; +V_$006E09D0 .net "data_i", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006DE808 .net "data_o", 7, 0, V_$006DE8E8[0], V_$006DE8E8[1], V_$006DE8E8[2], V_$006DE8E8[3], V_$006DE8E8[4], V_$006DE8E8[5], V_$006DE8E8[6], V_$006DE8E8[7]; +V_$006DE868 .net "readWriteSDBlockReq", 1, 0, V_$006DBA28[0], V_$006DBA28[1]; +V_$006DE8A0 .net "rstSyncToSpiClk", 0, 0, V_$006DCA00[0]; +V_$006E0D38 .net "rst_i", 0, 0, V_$006E0BD0[0]; +V_$006E0DA8 .net "rxDataFromRWSPIWireData", 7, 0, V_$006C90B8[0], V_$006C90B8[1], V_$006C90B8[2], V_$006C90B8[3], V_$006C90B8[4], V_$006C90B8[5], V_$006C90B8[6], V_$006C90B8[7]; +V_$006CB650 .net "rxDataFromSpiTxRxData", 7, 0, V_$006CB750[0], V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6], V_$006CB750[7]; +V_$006DD040 .net "rxDataRdyClrFromRWSDBlock", 0, 0, V_$006D6920[0]; +V_$006DD008 .net "rxDataRdyClrFromSendCmd", 0, 0, V_$006D1308[0]; +V_$006DCD68 .net "rxDataRdySetFromRWSPIWireData", 0, 0, V_$006CA688[0]; +V_$006DCD30 .net "rxFifoDataIn", 7, 0, V_$006D6958[0], V_$006D6958[1], V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5], V_$006D6958[6], V_$006D6958[7]; +V_$006D6B58 .net "sendCmdRespByte", 7, 0, V_$006D0B40[0], V_$006D0B40[1], V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4], V_$006D0B40[5], V_$006D0B40[6], V_$006D0B40[7]; +V_$006DCCC0 .net "spiCS_n", 0, 0, L_006E3660; +V_$006DCC88 .net "spiCS_nFromInitSD", 0, 0, V_$006DADF8[0]; +V_$006DCC50 .net "spiCS_nFromRWSDBlock", 0, 0, V_$006D6C70[0]; +V_$006E12C8 .net "spiCS_nFromSpiCtrl", 0, 0, V_$006DBBB8[0]; +V_$006E1300 .net "spiClkDelayFromCtrlStsReg", 7, 0, V_$006DCA38[0], V_$006DCA38[1], V_$006DCA38[2], V_$006DCA38[3], V_$006DCA38[4], V_$006DCA38[5], V_$006DCA38[6], V_$006DCA38[7]; +V_$006DCB70 .net "spiClkDelayFromInitSD", 7, 0, V_$006DB188[0], V_$006DB188[1], V_$006DB188[2], V_$006DB188[3], V_$006DB188[4], V_$006DB188[5], V_$006DB188[6], V_$006DB188[7]; +V_$006DB2A8 .net "spiClkOut", 0, 0, V_$006CAA28[0]; +V_$006E1450 .net "spiDataIn", 0, 0, V_$00644A08[0]; +V_$006E14B8 .net "spiDataOut", 0, 0, V_$006CAAD8[0]; +V_$006E1520 .net "spiDirectAccessTxData", 7, 0, V_$006DD220[0], V_$006DD220[1], V_$006DD220[2], V_$006DD220[3], V_$006DD220[4], V_$006DD220[5], V_$006DD220[6], V_$006DD220[7]; +V_$006DD340 .net "spiSysClk", 0, 0, V_$006E3508[0]; +V_$006E1700 .net "spiTransType", 1, 0, V_$006DDBA0[0], V_$006DDBA0[1]; +V_$006DDBD8 .net "strobe_i", 0, 0, V_$006607B0[0]; +V_$006E1798 .net "txDataFromInitSD", 7, 0, V_$006D71D0[0], V_$006D71D0[1], V_$006D71D0[2], V_$006D71D0[3], V_$006D71D0[4], V_$006D71D0[5], V_$006D71D0[6], V_$006D71D0[7]; +V_$006DB478 .net "txDataFromRWSDBlock", 7, 0, V_$006D7208[0], V_$006D7208[1], V_$006D7208[2], V_$006D7208[3], V_$006D7208[4], V_$006D7208[5], V_$006D7208[6], V_$006D7208[7]; +V_$006D7268 .net "txDataFromSendCmd", 7, 0, V_$006D1678[0], V_$006D1678[1], V_$006D1678[2], V_$006D1678[3], V_$006D1678[4], V_$006D1678[5], V_$006D1678[6], V_$006D1678[7]; +V_$006E1AE8 .net "txDataFullClrFromRWSPIWireData", 0, 0, V_$006CAC78[0]; +V_$006E1B50 .net "txDataFullFromSpiTxRxData", 0, 0, V_$006CC7A8[0]; +V_$006E1B88 .net "txDataToRWSPIWireData", 7, 0, V_$006CC858[0], V_$006CC858[1], V_$006CC858[2], V_$006CC858[3], V_$006CC858[4], V_$006CC858[5], V_$006CC858[6], V_$006CC858[7]; +V_$006CC978 .net "txDataWenFromInitSD", 0, 0, V_$006DB4B8[0]; +V_$006E1CD8 .net "txDataWenFromRWSDBlock", 0, 0, V_$006D72A8[0]; +V_$006E1D40 .net "txDataWenFromSendCmd", 0, 0, V_$006D17B8[0]; +V_$006E1DA8 .net "txFifoDataOut", 7, 0, V_$006C7CF0[0], V_$006C7CF0[1], V_$006C7CF0[2], V_$006C7CF0[3], V_$006C7CF0[4], V_$006C7CF0[5], V_$006C7CF0[6], V_$006C7CF0[7]; +V_$006E1FC8 .net "we_i", 0, 0, V_$006A5C98[0]; +V_$006E2040 .net "ctrlStsRegSel", 0, 0, V_$006DE140[0]; +V_$006E2078 .net "rxFifoSel", 0, 0, V_$006DE9B8[0]; +V_$006E20E8 .net "txFifoSel", 0, 0, V_$006DEA20[0]; +V_$006E2158 .net "spiTransCtrl", 0, 0, V_$006DDF80[0]; +V_$006E2190 .net "spiTransSts", 0, 0, V_$006DBC48[0]; +V_$006E21C8 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0]; +V_$006E2310 .net "readWriteSDBlockRdy", 0, 0, V_$006D6E38[0]; +V_$006E2348 .net "rxDataRdyFromSpiTxRxData", 0, 0, V_$006CB9B8[0]; +V_$006E2498 .net "rxDataRdyClrFromSpiCtrl", 0, 0, V_$006DAC70[0]; +V_$006E24D0 .net "SDInitRdy", 0, 0, V_$006D7E68[0]; +V_$006E2628 .net "SDInitReq", 0, 0, V_$006DB678[0]; +V_$006E2660 .net "txDataWenFromSpiCtrl", 0, 0, V_$006DBDB0[0]; +V_$006E27C0 .net "sendCmdRespTout", 0, 0, V_$006D1010[0]; +V_$006E2830 .net "rxDataRdyClrFromInitSD", 0, 0, V_$006DACA8[0]; +V_$006E2998 .net "sendCmdRdy", 0, 0, V_$006D1360[0]; +V_$006E2A08 .net "sendCmdReqFromInitSD", 0, 0, V_$006DAD18[0]; +V_$006E2B78 .net "txDataEmptyFromRWSPIWireData", 0, 0, V_$006CAB30[0]; +V_$006DB320 .net "rRxFifoWE", 0, 0, V_$006D6B90[0]; +V_$006D6BC8 .net "sendCmdReqFromRWSDBlock", 0, 0, V_$006D6C38[0]; +V_$006E2CF0 .net "txFifoRE", 0, 0, V_$006D7488[0]; +V_$006D75B0 .net "hostTxFifoEmpty", 0, 0, V_$006C7FF8[0]; +V_$006E2EB8 .net "hostRxFifoFull", 0, 0, V_$006C4260[0]; +S_006DD638 .scope module, "u_wishBoneBI" "wishBoneBI", S_006C1500; + .timescale -9; +V_$006DDE60 .var "ack_delayed", 0, 0; +V_$006DDEE0 .var "ack_immediate", 0, 0; +V_$006DE038 .var "ack_o", 0, 0; +V_$006DE0A8 .net "address", 7, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7]; +V_$006DE108 .net "clk", 0, 0, V_$006DF4B8[0]; +V_$006DE140 .var "ctrlStsRegSel", 0, 0; +V_$006DE178 .net "dataFromCtrlStsReg", 7, 0, V_$006DC658[0], V_$006DC658[1], V_$006DC658[2], V_$006DC658[3], V_$006DC658[4], V_$006DC658[5], V_$006DC658[6], V_$006DC658[7]; +V_$006DE280 .net "dataFromRxFifo", 7, 0, V_$006A5290[0], V_$006A5290[1], V_$006A5290[2], V_$006A5290[3], V_$006A5290[4], V_$006A5290[5], V_$006A5290[6], V_$006A5290[7]; +V_$006DE3A0 .net "dataFromTxFifo", 7, 0, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>; +V_$006DE5B8 .net "dataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006DE8E8 .var "dataOut", 7, 0; +V_$006DE980 .net "rst", 0, 0, V_$006E0BD0[0]; +V_$006DE9B8 .var "rxFifoSel", 0, 0; +V_$006DE920 .net "strobe_i", 0, 0, V_$006607B0[0]; +V_$006DEA20 .var "txFifoSel", 0, 0; +V_$006DEA88 .net "writeEn", 0, 0, V_$006A5C98[0]; +E_006DDDA0/0 .event edge, V_$006DDEE0[0], V_$006DDE60[0], V_$0068AE60[0], V_$0068AE60[1]; +E_006DDDA0/1 .event edge, V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5]; +E_006DDDA0/2 .event edge, V_$0068AE60[6], V_$0068AE60[7], V_$006A5C98[0]; +E_006DDDA0 .event/or E_006DDDA0/0, E_006DDDA0/1, E_006DDDA0/2; +E_006DDDF8 .event edge, V_$006607B0[0]; +E_006DDE28/0 .event edge, C<0>, C<0>, C<0>, C<0>; +E_006DDE28/1 .event edge, C<0>, C<0>, C<0>, C<0>; +E_006DDE28/2 .event edge, V_$006A5290[0], V_$006A5290[1], V_$006A5290[2], V_$006A5290[3]; +E_006DDE28/3 .event edge, V_$006A5290[4], V_$006A5290[5], V_$006A5290[6], V_$006A5290[7]; +E_006DDE28/4 .event edge, V_$006DC658[0], V_$006DC658[1], V_$006DC658[2], V_$006DC658[3]; +E_006DDE28/5 .event edge, V_$006DC658[4], V_$006DC658[5], V_$006DC658[6], V_$006DC658[7]; +E_006DDE28/6 .event edge, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3]; +E_006DDE28/7 .event edge, V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7]; +E_006DDE28 .event/or E_006DDE28/0, E_006DDE28/1, E_006DDE28/2, E_006DDE28/3, E_006DDE28/4, E_006DDE28/5, E_006DDE28/6, E_006DDE28/7; +S_006DBE08 .scope module, "u_ctrlStsRegBI" "ctrlStsRegBI", S_006C1500; + .timescale -9; +V_$006DBED8 .var "SDAddr", 31, 0; +V_$006DC3C8 .net "SDInitError", 1, 0, V_$006D8260[0], V_$006D8260[1]; +V_$006DC440 .var "SDInitErrorSTB", 1, 0; +V_$006DC478 .net "SDReadError", 1, 0, V_$006D6488[0], V_$006D6488[1]; +V_$006DC4D0 .var "SDReadErrorSTB", 1, 0; +V_$006DCE08 .net "SDWriteError", 1, 0, V_$006D75E8[0], V_$006D75E8[1]; +V_$006DCE80 .var "SDWriteErrorSTB", 1, 0; +V_$006DCEF8 .net "address", 7, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7]; +V_$006DC578 .net "busClk", 0, 0, V_$006DF4B8[0]; +V_$006DC5B0 .net "ctrlStsRegSel", 0, 0, V_$006DE140[0]; +V_$006DC5E8 .net "dataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006DC658 .var "dataOut", 7, 0; +V_$006DC6B8 .var "rstFromBus", 0, 0; +V_$006DC620 .net "rstFromWire", 0, 0, V_$006E0BD0[0]; +V_$006DC710 .var "rstShift", 5, 0; +V_$006DC940 .var "rstSyncToBusClkOut", 0, 0; +V_$006DC978 .var "rstSyncToSpiClkFirst", 0, 0; +V_$006DCA00 .var "rstSyncToSpiClkOut", 0, 0; +V_$006DCA38 .var "spiClkDelay", 7, 0; +V_$006DCBF0 .net "spiDirectAccessRxData", 7, 0, V_$006CB750[0], V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6], V_$006CB750[7]; +V_$006DD078 .var "spiDirectAccessRxDataSTB", 7, 0; +V_$006DD220 .var "spiDirectAccessTxData", 7, 0; +V_$006DD380 .var "spiDirectAccessTxDataSTB", 7, 0; +V_$006DDF48 .net "spiSysClk", 0, 0, V_$006E3508[0]; +V_$006DDF80 .var "spiTransCtrl", 0, 0; +V_$006DD6A8 .var "spiTransCtrlSTB", 0, 0; +V_$006DD6E0 .var "spiTransCtrlShift", 5, 0; +V_$006DD918 .net "spiTransStatus", 0, 0, V_$006DBC48[0]; +V_$006DD970 .var "spiTransStatusReg1", 0, 0; +V_$006DD9E0 .var "spiTransStatusReg2", 0, 0; +V_$006DDAA8 .var "spiTransStatusSTB", 0, 0; +V_$006DDBA0 .var "spiTransType", 1, 0; +V_$006DDC18 .var "spiTransTypeSTB", 1, 0; +V_$006DDCE0 .net "strobe_i", 0, 0, V_$006607B0[0]; +V_$006DDD18 .net "writeEn", 0, 0, V_$006A5C98[0]; +E_006DBE78/0 .event edge, V_$006DC710[0], V_$006DC710[1], V_$006DC710[2], V_$006DC710[3]; +E_006DBE78/1 .event edge, V_$006DC710[4], V_$006DC710[5]; +E_006DBE78 .event/or E_006DBE78/0, E_006DBE78/1; +E_006DBEB8/0 .event edge, V_$006DD078[0], V_$006DD078[1], V_$006DD078[2], V_$006DD078[3]; +E_006DBEB8/1 .event edge, V_$006DD078[4], V_$006DD078[5], V_$006DD078[6], V_$006DD078[7]; +E_006DBEB8/2 .event edge, V_$006DDAA8[0], V_$006DD6A8[0], V_$006DDC18[0], V_$006DDC18[1]; +E_006DBEB8/3 .event edge, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3]; +E_006DBEB8/4 .event edge, V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7]; +E_006DBEB8 .event/or E_006DBEB8/0, E_006DBEB8/1, E_006DBEB8/2, E_006DBEB8/3, E_006DBEB8/4; +S_006DA008 .scope module, "u_spiCtrl" "spiCtrl", S_006C1500; + .timescale -9; +V_$006DB530 .var "CurrState_spiCtrlSt", 2, 0; +V_$006DB5C8 .var "NextState_spiCtrlSt", 2, 0; +V_$006DB620 .net "SDInitRdy", 0, 0, V_$006D7E68[0]; +V_$006DB678 .var "SDInitReq", 0, 0; +V_$006DB6D0 .net "clk", 0, 0, V_$006E3508[0]; +V_$006DB728 .var "next_SDInitReq", 0, 0; +V_$006DB760 .var "next_readWriteSDBlockReq", 1, 0; +V_$006DB7C0 .var "next_rxDataRdyClr", 0, 0; +V_$006DB810 .var "next_spiCS_n", 0, 0; +V_$006DB890 .var "next_spiTransSts", 0, 0; +V_$006DB918 .var "next_txDataWen", 0, 0; +V_$006DB9D0 .net "readWriteSDBlockRdy", 0, 0, V_$006D6E38[0]; +V_$006DBA28 .var "readWriteSDBlockReq", 1, 0; +V_$006DB950 .net "rst", 0, 0, V_$006DCA00[0]; +V_$006DBB18 .net "rxDataRdy", 0, 0, V_$006CB9B8[0]; +V_$006DAC70 .var "rxDataRdyClr", 0, 0; +V_$006DBBB8 .var "spiCS_n", 0, 0; +V_$006DBC10 .net "spiTransCtrl", 0, 0, V_$006DDF80[0]; +V_$006DBC48 .var "spiTransSts", 0, 0; +V_$006DBCC8 .net "spiTransType", 1, 0, V_$006DDBA0[0], V_$006DDBA0[1]; +V_$006DBDB0 .var "txDataWen", 0, 0; +E_006DB510/0 .event edge, V_$006DB530[0], V_$006DB530[1], V_$006DB530[2], V_$006DBBB8[0]; +E_006DB510/1 .event edge, V_$006DBC48[0], V_$006DAC70[0], V_$006DB678[0], V_$006DBDB0[0]; +E_006DB510/2 .event edge, V_$006DBA28[0], V_$006DBA28[1], V_$006D6E38[0], V_$006D7E68[0]; +E_006DB510/3 .event edge, V_$006CB9B8[0], V_$006DDF80[0]; +E_006DB510 .event/or E_006DB510/0, E_006DB510/1, E_006DB510/2, E_006DB510/3; +S_006D5E10 .scope module, "u_initSD" "initSD", S_006C1500; + .timescale -9; +V_$006D7810 .var "CurrState_initSDSt", 3, 0; +V_$006D78C0 .var "NextState_initSDSt", 3, 0; +V_$006D7E68 .var "SDInitRdy", 0, 0; +V_$006D7F00 .net "SDInitReq", 0, 0, V_$006DB678[0]; +V_$006D7F80 .var "checkSumByte", 7, 0; +V_$006D7AD0 .net "clk", 0, 0, V_$006E3508[0]; +V_$006D7B08 .var "cmdByte", 7, 0; +V_$006D7C70 .var "dataByte1", 7, 0; +V_$006D7DD0 .var "dataByte2", 7, 0; +V_$006D80C8 .var "dataByte3", 7, 0; +V_$006D8228 .var "dataByte4", 7, 0; +V_$006D83C0 .var "delCnt1", 9, 0; +V_$006D83F8 .var "delCnt2", 7, 0; +V_$006D8260 .var "initError", 1, 0; +V_$006D8E20 .var "loopCnt", 7, 0; +V_$006D8560 .var "next_SDInitRdy", 0, 0; +V_$006D85E0 .var "next_checkSumByte", 7, 0; +V_$006D8900 .var "next_cmdByte", 7, 0; +V_$006D8B78 .var "next_dataByte1", 7, 0; +V_$006D90D8 .var "next_dataByte2", 7, 0; +V_$006D93B8 .var "next_dataByte3", 7, 0; +V_$006D9F90 .var "next_dataByte4", 7, 0; +V_$006D9750 .var "next_delCnt1", 9, 0; +V_$006D9AB8 .var "next_delCnt2", 7, 0; +V_$006D9D58 .var "next_initError", 1, 0; +V_$006DA0A8 .var "next_loopCnt", 7, 0; +V_$006DA348 .var "next_rxDataRdyClr", 0, 0; +V_$006DA3D0 .var "next_sendCmdReq", 0, 0; +V_$006DA450 .var "next_spiCS_n", 0, 0; +V_$006DA4D0 .var "next_spiClkDelayOut", 7, 0; +V_$006DA638 .var "next_txDataOut", 7, 0; +V_$006DA918 .var "next_txDataWen", 0, 0; +V_$006DA998 .net "respByte", 7, 0, V_$006D0B40[0], V_$006D0B40[1], V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4], V_$006D0B40[5], V_$006D0B40[6], V_$006D0B40[7]; +V_$006DAB98 .net "respTout", 0, 0, V_$006D1010[0]; +V_$006DAC00 .net "rst", 0, 0, V_$006DCA00[0]; +V_$006DAC38 .net "rxDataRdy", 0, 0, V_$006CB9B8[0]; +V_$006DACA8 .var "rxDataRdyClr", 0, 0; +V_$006DACE0 .net "sendCmdRdy", 0, 0, V_$006D1360[0]; +V_$006DAD18 .var "sendCmdReq", 0, 0; +V_$006DADF8 .var "spiCS_n", 0, 0; +V_$006DAE30 .net "spiClkDelayIn", 7, 0, V_$006DCA38[0], V_$006DCA38[1], V_$006DCA38[2], V_$006DCA38[3], V_$006DCA38[4], V_$006DCA38[5], V_$006DCA38[6], V_$006DCA38[7]; +V_$006DB188 .var "spiClkDelayOut", 7, 0; +V_$006DB2E8 .net "txDataEmpty", 0, 0, V_$006CAB30[0]; +V_$006DB358 .net "txDataFull", 0, 0, V_$006CC7A8[0]; +V_$006D71D0 .var "txDataOut", 7, 0; +V_$006DB4B8 .var "txDataWen", 0, 0; +E_006C8B28/0 .event edge, V_$006D7810[0], V_$006D7810[1], V_$006D7810[2], V_$006D7810[3]; +E_006C8B28/1 .event edge, V_$006DACA8[0], V_$006DAD18[0], V_$006D7F80[0], V_$006D7F80[1]; +E_006C8B28/2 .event edge, V_$006D7F80[2], V_$006D7F80[3], V_$006D7F80[4], V_$006D7F80[5]; +E_006C8B28/3 .event edge, V_$006D7F80[6], V_$006D7F80[7], V_$006D8228[0], V_$006D8228[1]; +E_006C8B28/4 .event edge, V_$006D8228[2], V_$006D8228[3], V_$006D8228[4], V_$006D8228[5]; +E_006C8B28/5 .event edge, V_$006D8228[6], V_$006D8228[7], V_$006D80C8[0], V_$006D80C8[1]; +E_006C8B28/6 .event edge, V_$006D80C8[2], V_$006D80C8[3], V_$006D80C8[4], V_$006D80C8[5]; +E_006C8B28/7 .event edge, V_$006D80C8[6], V_$006D80C8[7], V_$006D7DD0[0], V_$006D7DD0[1]; +E_006C8B28/8 .event edge, V_$006D7DD0[2], V_$006D7DD0[3], V_$006D7DD0[4], V_$006D7DD0[5]; +E_006C8B28/9 .event edge, V_$006D7DD0[6], V_$006D7DD0[7], V_$006D7C70[0], V_$006D7C70[1]; +E_006C8B28/10 .event edge, V_$006D7C70[2], V_$006D7C70[3], V_$006D7C70[4], V_$006D7C70[5]; +E_006C8B28/11 .event edge, V_$006D7C70[6], V_$006D7C70[7], V_$006D7B08[0], V_$006D7B08[1]; +E_006C8B28/12 .event edge, V_$006D7B08[2], V_$006D7B08[3], V_$006D7B08[4], V_$006D7B08[5]; +E_006C8B28/13 .event edge, V_$006D7B08[6], V_$006D7B08[7], V_$006DB4B8[0], V_$006D71D0[0]; +E_006C8B28/14 .event edge, V_$006D71D0[1], V_$006D71D0[2], V_$006D71D0[3], V_$006D71D0[4]; +E_006C8B28/15 .event edge, V_$006D71D0[5], V_$006D71D0[6], V_$006D71D0[7], V_$006D8260[0]; +E_006C8B28/16 .event edge, V_$006D8260[1], V_$006DADF8[0], V_$006D7E68[0], V_$006DB188[0]; +E_006C8B28/17 .event edge, V_$006DB188[1], V_$006DB188[2], V_$006DB188[3], V_$006DB188[4]; +E_006C8B28/18 .event edge, V_$006DB188[5], V_$006DB188[6], V_$006DB188[7], V_$006CAB30[0]; +E_006C8B28/19 .event edge, V_$006D83F8[0], V_$006D83F8[1], V_$006D83F8[2], V_$006D83F8[3]; +E_006C8B28/20 .event edge, V_$006D83F8[4], V_$006D83F8[5], V_$006D83F8[6], V_$006D83F8[7]; +E_006C8B28/21 .event edge, V_$006D83C0[0], V_$006D83C0[1], V_$006D83C0[2], V_$006D83C0[3]; +E_006C8B28/22 .event edge, V_$006D83C0[4], V_$006D83C0[5], V_$006D83C0[6], V_$006D83C0[7]; +E_006C8B28/23 .event edge, V_$006D83C0[8], V_$006D83C0[9], V_$006D0B40[0], V_$006D0B40[1]; +E_006C8B28/24 .event edge, V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4], V_$006D0B40[5]; +E_006C8B28/25 .event edge, V_$006D0B40[6], V_$006D0B40[7], V_$006D1010[0], V_$006D1360[0]; +E_006C8B28/26 .event edge, V_$006D8E20[0], V_$006D8E20[1], V_$006D8E20[2], V_$006D8E20[3]; +E_006C8B28/27 .event edge, V_$006D8E20[4], V_$006D8E20[5], V_$006D8E20[6], V_$006D8E20[7]; +E_006C8B28/28 .event edge, V_$006CC7A8[0], V_$006DB678[0], V_$006DCA38[0], V_$006DCA38[1]; +E_006C8B28/29 .event edge, V_$006DCA38[2], V_$006DCA38[3], V_$006DCA38[4], V_$006DCA38[5]; +E_006C8B28/30 .event edge, V_$006DCA38[6], V_$006DCA38[7]; +E_006C8B28 .event/or E_006C8B28/0, E_006C8B28/1, E_006C8B28/2, E_006C8B28/3, E_006C8B28/4, E_006C8B28/5, E_006C8B28/6, E_006C8B28/7, E_006C8B28/8, E_006C8B28/9, E_006C8B28/10, E_006C8B28/11, E_006C8B28/12, E_006C8B28/13, E_006C8B28/14, E_006C8B28/15, E_006C8B28/16, E_006C8B28/17, E_006C8B28/18, E_006C8B28/19, E_006C8B28/20, E_006C8B28/21, E_006C8B28/22, E_006C8B28/23, E_006C8B28/24, E_006C8B28/25, E_006C8B28/26, E_006C8B28/27, E_006C8B28/28, E_006C8B28/29, E_006C8B28/30; +S_006D0E50 .scope module, "u_readWriteSDBlock" "readWriteSDBlock", S_006C1500; + .timescale -9; +V_$006D1830 .var "CurrState_rwBlkSt", 5, 0; +V_$006D1C70 .var "NextState_rwBlkSt", 5, 0; +V_$006D2078 .net "blockAddr", 31, 0, V_$006DBED8[0], V_$006DBED8[1], V_$006DBED8[2], V_$006DBED8[3], V_$006DBED8[4], V_$006DBED8[5], V_$006DBED8[6], V_$006DBED8[7], V_$006DBED8[8], V_$006DBED8[9], V_$006DBED8[10], V_$006DBED8[11], V_$006DBED8[12], V_$006DBED8[13], V_$006DBED8[14], V_$006DBED8[15], V_$006DBED8[16], V_$006DBED8[17], V_$006DBED8[18], V_$006DBED8[19], V_$006DBED8[20], V_$006DBED8[21], V_$006DBED8[22], V_$006DBED8[23], V_$006DBED8[24], V_$006DBED8[25], V_$006DBED8[26], V_$006DBED8[27], V_$006DBED8[28], V_$006DBED8[29], V_$006DBED8[30], V_$006DBED8[31]; +V_$006D2790 .var "checkSumByte", 7, 0; +V_$006D28F0 .net "clk", 0, 0, V_$006E3508[0]; +V_$006D2970 .var "cmdByte", 7, 0; +V_$006D2AB0 .var "dataByte1", 7, 0; +V_$006D2C18 .var "dataByte2", 7, 0; +V_$006D2D78 .var "dataByte3", 7, 0; +V_$006D3138 .var "dataByte4", 7, 0; +V_$006D3278 .var "delCnt1", 7, 0; +V_$006D3310 .var "delCnt2", 7, 0; +V_$006D3370 .var "locRespByte", 7, 0; +V_$006D32B0 .var "loopCnt", 8, 0; +V_$006D3580 .var "next_checkSumByte", 7, 0; +V_$006D3890 .var "next_cmdByte", 7, 0; +V_$006D3B18 .var "next_dataByte1", 7, 0; +V_$006D40D8 .var "next_dataByte2", 7, 0; +V_$006D43B8 .var "next_dataByte3", 7, 0; +V_$006D4F90 .var "next_dataByte4", 7, 0; +V_$006D4750 .var "next_delCnt1", 7, 0; +V_$006D4A70 .var "next_delCnt2", 7, 0; +V_$006D4D10 .var "next_locRespByte", 7, 0; +V_$006D5200 .var "next_loopCnt", 8, 0; +V_$006D5DD8 .var "next_readError", 1, 0; +V_$006D5F20 .var "next_readWriteSDBlockRdy", 0, 0; +V_$006D5FB0 .var "next_rxDataRdyClr", 0, 0; +V_$006D5520 .var "next_rxFifoData", 7, 0; +V_$006D5800 .var "next_rxFifoWen", 0, 0; +V_$006D5880 .var "next_sendCmdReq", 0, 0; +V_$006D5948 .var "next_spiCS_n", 0, 0; +V_$006D5A20 .var "next_timeOutCnt", 9, 0; +V_$006D6008 .var "next_txDataOut", 7, 0; +V_$006D62B0 .var "next_txDataWen", 0, 0; +V_$006D6330 .var "next_txFifoRen", 0, 0; +V_$006D63B0 .var "next_writeError", 1, 0; +V_$006D6488 .var "readError", 1, 0; +V_$006D6E38 .var "readWriteSDBlockRdy", 0, 0; +V_$006D6EC0 .net "readWriteSDBlockReq", 1, 0, V_$006DBA28[0], V_$006DBA28[1]; +V_$006D6F98 .net "respByte", 7, 0, V_$006D0B40[0], V_$006D0B40[1], V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4], V_$006D0B40[5], V_$006D0B40[6], V_$006D0B40[7]; +V_$006D6648 .net "respTout", 0, 0, V_$006D1010[0]; +V_$006D66A0 .net "rst", 0, 0, V_$006DCA00[0]; +V_$006D66D8 .net "rxDataIn", 7, 0, V_$006CB750[0], V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6], V_$006CB750[7]; +V_$006D68B8 .net "rxDataRdy", 0, 0, V_$006CB9B8[0]; +V_$006D6920 .var "rxDataRdyClr", 0, 0; +V_$006D6958 .var "rxFifoData", 7, 0; +V_$006D6B90 .var "rxFifoWen", 0, 0; +V_$006D6C00 .net "sendCmdRdy", 0, 0, V_$006D1360[0]; +V_$006D6C38 .var "sendCmdReq", 0, 0; +V_$006D6C70 .var "spiCS_n", 0, 0; +V_$006D6CA8 .var "timeOutCnt", 9, 0; +V_$006D7160 .net "txDataEmpty", 0, 0, V_$006CAB30[0]; +V_$006D7198 .net "txDataFull", 0, 0, V_$006CC7A8[0]; +V_$006D7208 .var "txDataOut", 7, 0; +V_$006D72A8 .var "txDataWen", 0, 0; +V_$006D73E8 .net "txFifoData", 7, 0, V_$006C7CF0[0], V_$006C7CF0[1], V_$006C7CF0[2], V_$006C7CF0[3], V_$006C7CF0[4], V_$006C7CF0[5], V_$006C7CF0[6], V_$006C7CF0[7]; +V_$006D7488 .var "txFifoRen", 0, 0; +V_$006D75E8 .var "writeError", 1, 0; +E_006D1810/0 .event edge, V_$006D1830[0], V_$006D1830[1], V_$006D1830[2], V_$006D1830[3]; +E_006D1810/1 .event edge, V_$006D1830[4], V_$006D1830[5], V_$006D6958[0], V_$006D6958[1]; +E_006D1810/2 .event edge, V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5]; +E_006D1810/3 .event edge, V_$006D6958[6], V_$006D6958[7], V_$006D6B90[0], V_$006D7488[0]; +E_006D1810/4 .event edge, V_$006D6C38[0], V_$006D2790[0], V_$006D2790[1], V_$006D2790[2]; +E_006D1810/5 .event edge, V_$006D2790[3], V_$006D2790[4], V_$006D2790[5], V_$006D2790[6]; +E_006D1810/6 .event edge, V_$006D2790[7], V_$006D3138[0], V_$006D3138[1], V_$006D3138[2]; +E_006D1810/7 .event edge, V_$006D3138[3], V_$006D3138[4], V_$006D3138[5], V_$006D3138[6]; +E_006D1810/8 .event edge, V_$006D3138[7], V_$006D2D78[0], V_$006D2D78[1], V_$006D2D78[2]; +E_006D1810/9 .event edge, V_$006D2D78[3], V_$006D2D78[4], V_$006D2D78[5], V_$006D2D78[6]; +E_006D1810/10 .event edge, V_$006D2D78[7], V_$006D2C18[0], V_$006D2C18[1], V_$006D2C18[2]; +E_006D1810/11 .event edge, V_$006D2C18[3], V_$006D2C18[4], V_$006D2C18[5], V_$006D2C18[6]; +E_006D1810/12 .event edge, V_$006D2C18[7], V_$006D2AB0[0], V_$006D2AB0[1], V_$006D2AB0[2]; +E_006D1810/13 .event edge, V_$006D2AB0[3], V_$006D2AB0[4], V_$006D2AB0[5], V_$006D2AB0[6]; +E_006D1810/14 .event edge, V_$006D2AB0[7], V_$006D2970[0], V_$006D2970[1], V_$006D2970[2]; +E_006D1810/15 .event edge, V_$006D2970[3], V_$006D2970[4], V_$006D2970[5], V_$006D2970[6]; +E_006D1810/16 .event edge, V_$006D2970[7], V_$006D6920[0], V_$006D72A8[0], V_$006D7208[0]; +E_006D1810/17 .event edge, V_$006D7208[1], V_$006D7208[2], V_$006D7208[3], V_$006D7208[4]; +E_006D1810/18 .event edge, V_$006D7208[5], V_$006D7208[6], V_$006D7208[7], V_$006D75E8[0]; +E_006D1810/19 .event edge, V_$006D75E8[1], V_$006D6488[0], V_$006D6488[1], V_$006D6C70[0]; +E_006D1810/20 .event edge, V_$006D6E38[0], V_$006D3310[0], V_$006D3310[1], V_$006D3310[2]; +E_006D1810/21 .event edge, V_$006D3310[3], V_$006D3310[4], V_$006D3310[5], V_$006D3310[6]; +E_006D1810/22 .event edge, V_$006D3310[7], V_$006D3278[0], V_$006D3278[1], V_$006D3278[2]; +E_006D1810/23 .event edge, V_$006D3278[3], V_$006D3278[4], V_$006D3278[5], V_$006D3278[6]; +E_006D1810/24 .event edge, V_$006D3278[7], V_$006CB750[0], V_$006CB750[1], V_$006CB750[2]; +E_006D1810/25 .event edge, V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6]; +E_006D1810/26 .event edge, V_$006CB750[7], V_$006CB9B8[0], V_$006D3370[0], V_$006D3370[1]; +E_006D1810/27 .event edge, V_$006D3370[2], V_$006D3370[3], V_$006D3370[4], V_$006D3370[5]; +E_006D1810/28 .event edge, V_$006D3370[6], V_$006D3370[7], V_$006D6CA8[0], V_$006D6CA8[1]; +E_006D1810/29 .event edge, V_$006D6CA8[2], V_$006D6CA8[3], V_$006D6CA8[4], V_$006D6CA8[5]; +E_006D1810/30 .event edge, V_$006D6CA8[6], V_$006D6CA8[7], V_$006D6CA8[8], V_$006D6CA8[9]; +E_006D1810/31 .event edge, V_$006CAB30[0], V_$006C7CF0[0], V_$006C7CF0[1], V_$006C7CF0[2]; +E_006D1810/32 .event edge, V_$006C7CF0[3], V_$006C7CF0[4], V_$006C7CF0[5], V_$006C7CF0[6]; +E_006D1810/33 .event edge, V_$006C7CF0[7], V_$006D32B0[0], V_$006D32B0[1], V_$006D32B0[2]; +E_006D1810/34 .event edge, V_$006D32B0[3], V_$006D32B0[4], V_$006D32B0[5], V_$006D32B0[6]; +E_006D1810/35 .event edge, V_$006D32B0[7], V_$006D32B0[8], V_$006CC7A8[0], V_$006DBA28[0]; +E_006D1810/36 .event edge, V_$006DBA28[1], V_$006D1360[0], V_$006DBED8[0], V_$006DBED8[1]; +E_006D1810/37 .event edge, V_$006DBED8[2], V_$006DBED8[3], V_$006DBED8[4], V_$006DBED8[5]; +E_006D1810/38 .event edge, V_$006DBED8[6], V_$006DBED8[7], V_$006DBED8[8], V_$006DBED8[9]; +E_006D1810/39 .event edge, V_$006DBED8[10], V_$006DBED8[11], V_$006DBED8[12], V_$006DBED8[13]; +E_006D1810/40 .event edge, V_$006DBED8[14], V_$006DBED8[15], V_$006DBED8[16], V_$006DBED8[17]; +E_006D1810/41 .event edge, V_$006DBED8[18], V_$006DBED8[19], V_$006DBED8[20], V_$006DBED8[21]; +E_006D1810/42 .event edge, V_$006DBED8[22], V_$006DBED8[23], V_$006DBED8[24], V_$006DBED8[25]; +E_006D1810/43 .event edge, V_$006DBED8[26], V_$006DBED8[27], V_$006DBED8[28], V_$006DBED8[29]; +E_006D1810/44 .event edge, V_$006DBED8[30], V_$006DBED8[31]; +E_006D1810 .event/or E_006D1810/0, E_006D1810/1, E_006D1810/2, E_006D1810/3, E_006D1810/4, E_006D1810/5, E_006D1810/6, E_006D1810/7, E_006D1810/8, E_006D1810/9, E_006D1810/10, E_006D1810/11, E_006D1810/12, E_006D1810/13, E_006D1810/14, E_006D1810/15, E_006D1810/16, E_006D1810/17, E_006D1810/18, E_006D1810/19, E_006D1810/20, E_006D1810/21, E_006D1810/22, E_006D1810/23, E_006D1810/24, E_006D1810/25, E_006D1810/26, E_006D1810/27, E_006D1810/28, E_006D1810/29, E_006D1810/30, E_006D1810/31, E_006D1810/32, E_006D1810/33, E_006D1810/34, E_006D1810/35, E_006D1810/36, E_006D1810/37, E_006D1810/38, E_006D1810/39, E_006D1810/40, E_006D1810/41, E_006D1810/42, E_006D1810/43, E_006D1810/44; +S_006CC9E8 .scope module, "u_sendCmd" "sendCmd", S_006C1500; + .timescale -9; +V_$006CCC20 .var "CurrState_sndCmdSt", 4, 0; +V_$006CCD78 .var "NextState_sndCmdSt", 4, 0; +V_$006CD0D8 .var "checkSumByte", 7, 0; +V_$006CD390 .net "checkSumByte_1", 7, 0, V_$006D7F80[0], V_$006D7F80[1], V_$006D7F80[2], V_$006D7F80[3], V_$006D7F80[4], V_$006D7F80[5], V_$006D7F80[6], V_$006D7F80[7]; +V_$006CDF58 .net "checkSumByte_2", 7, 0, V_$006D2790[0], V_$006D2790[1], V_$006D2790[2], V_$006D2790[3], V_$006D2790[4], V_$006D2790[5], V_$006D2790[6], V_$006D2790[7]; +V_$006CD750 .net "clk", 0, 0, V_$006E3508[0]; +V_$006CD788 .var "cmdByte", 7, 0; +V_$006CDA58 .net "cmdByte_1", 7, 0, V_$006D7B08[0], V_$006D7B08[1], V_$006D7B08[2], V_$006D7B08[3], V_$006D7B08[4], V_$006D7B08[5], V_$006D7B08[6], V_$006D7B08[7]; +V_$006CDCF8 .net "cmdByte_2", 7, 0, V_$006D2970[0], V_$006D2970[1], V_$006D2970[2], V_$006D2970[3], V_$006D2970[4], V_$006D2970[5], V_$006D2970[6], V_$006D2970[7]; +V_$006CE188 .var "dataByte1", 7, 0; +V_$006CE428 .net "dataByte1_1", 7, 0, V_$006D7C70[0], V_$006D7C70[1], V_$006D7C70[2], V_$006D7C70[3], V_$006D7C70[4], V_$006D7C70[5], V_$006D7C70[6], V_$006D7C70[7]; +V_$006CE538 .net "dataByte1_2", 7, 0, V_$006D2AB0[0], V_$006D2AB0[1], V_$006D2AB0[2], V_$006D2AB0[3], V_$006D2AB0[4], V_$006D2AB0[5], V_$006D2AB0[6], V_$006D2AB0[7]; +V_$006CE7B0 .var "dataByte2", 7, 0; +V_$006CE460 .net "dataByte2_1", 7, 0, V_$006D7DD0[0], V_$006D7DD0[1], V_$006D7DD0[2], V_$006D7DD0[3], V_$006D7DD0[4], V_$006D7DD0[5], V_$006D7DD0[6], V_$006D7DD0[7]; +V_$006CECD8 .net "dataByte2_2", 7, 0, V_$006D2C18[0], V_$006D2C18[1], V_$006D2C18[2], V_$006D2C18[3], V_$006D2C18[4], V_$006D2C18[5], V_$006D2C18[6], V_$006D2C18[7]; +V_$006CF158 .var "dataByte3", 7, 0; +V_$006CF3F8 .net "dataByte3_1", 7, 0, V_$006D80C8[0], V_$006D80C8[1], V_$006D80C8[2], V_$006D80C8[3], V_$006D80C8[4], V_$006D80C8[5], V_$006D80C8[6], V_$006D80C8[7]; +V_$006CFF80 .net "dataByte3_2", 7, 0, V_$006D2D78[0], V_$006D2D78[1], V_$006D2D78[2], V_$006D2D78[3], V_$006D2D78[4], V_$006D2D78[5], V_$006D2D78[6], V_$006D2D78[7]; +V_$006CF750 .var "dataByte4", 7, 0; +V_$006CFA18 .net "dataByte4_1", 7, 0, V_$006D8228[0], V_$006D8228[1], V_$006D8228[2], V_$006D8228[3], V_$006D8228[4], V_$006D8228[5], V_$006D8228[6], V_$006D8228[7]; +V_$006CFCB8 .net "dataByte4_2", 7, 0, V_$006D3138[0], V_$006D3138[1], V_$006D3138[2], V_$006D3138[3], V_$006D3138[4], V_$006D3138[5], V_$006D3138[6], V_$006D3138[7]; +V_$006D01A8 .var "next_respByte", 7, 0; +V_$006D0488 .var "next_respTout", 0, 0; +V_$006D04F0 .var "next_rxDataRdyClr", 0, 0; +V_$006D0E18 .var "next_sendCmdRdy", 0, 0; +V_$006D0F08 .var "next_timeOutCnt", 9, 0; +V_$006D07C0 .var "next_txDataOut", 7, 0; +V_$006D0AC0 .var "next_txDataWen", 0, 0; +V_$006D0B40 .var "respByte", 7, 0; +V_$006D1010 .var "respTout", 0, 0; +V_$006D1090 .net "rst", 0, 0, V_$006DCA00[0]; +V_$006D1150 .net "rxDataIn", 7, 0, V_$006CB750[0], V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6], V_$006CB750[7]; +V_$006D12B0 .net "rxDataRdy", 0, 0, V_$006CB9B8[0]; +V_$006D1308 .var "rxDataRdyClr", 0, 0; +V_$006D1360 .var "sendCmdRdy", 0, 0; +V_$006D1398 .var "sendCmdReq", 0, 0; +V_$006D13D0 .net "sendCmdReq1", 0, 0, V_$006DAD18[0]; +V_$006D1428 .net "sendCmdReq2", 0, 0, V_$006D6C38[0]; +V_$006D14A8 .var "timeOutCnt", 9, 0; +V_$006D15B8 .net "txDataEmpty", 0, 0, V_$006CAB30[0]; +V_$006D1610 .net "txDataFull", 0, 0, V_$006CC7A8[0]; +V_$006D1678 .var "txDataOut", 7, 0; +V_$006D17B8 .var "txDataWen", 0, 0; +E_006CCA58/0 .event edge, V_$006CCC20[0], V_$006CCC20[1], V_$006CCC20[2], V_$006CCC20[3]; +E_006CCA58/1 .event edge, V_$006CCC20[4], V_$006D1360[0], V_$006D1010[0], V_$006D1308[0]; +E_006CCA58/2 .event edge, V_$006D1678[0], V_$006D1678[1], V_$006D1678[2], V_$006D1678[3]; +E_006CCA58/3 .event edge, V_$006D1678[4], V_$006D1678[5], V_$006D1678[6], V_$006D1678[7]; +E_006CCA58/4 .event edge, V_$006D17B8[0], V_$006D1398[0], V_$006CD788[0], V_$006CD788[1]; +E_006CCA58/5 .event edge, V_$006CD788[2], V_$006CD788[3], V_$006CD788[4], V_$006CD788[5]; +E_006CCA58/6 .event edge, V_$006CD788[6], V_$006CD788[7], V_$006CD0D8[0], V_$006CD0D8[1]; +E_006CCA58/7 .event edge, V_$006CD0D8[2], V_$006CD0D8[3], V_$006CD0D8[4], V_$006CD0D8[5]; +E_006CCA58/8 .event edge, V_$006CD0D8[6], V_$006CD0D8[7], V_$006CAB30[0], V_$006CF750[0]; +E_006CCA58/9 .event edge, V_$006CF750[1], V_$006CF750[2], V_$006CF750[3], V_$006CF750[4]; +E_006CCA58/10 .event edge, V_$006CF750[5], V_$006CF750[6], V_$006CF750[7], V_$006CF158[0]; +E_006CCA58/11 .event edge, V_$006CF158[1], V_$006CF158[2], V_$006CF158[3], V_$006CF158[4]; +E_006CCA58/12 .event edge, V_$006CF158[5], V_$006CF158[6], V_$006CF158[7], V_$006CE188[0]; +E_006CCA58/13 .event edge, V_$006CE188[1], V_$006CE188[2], V_$006CE188[3], V_$006CE188[4]; +E_006CCA58/14 .event edge, V_$006CE188[5], V_$006CE188[6], V_$006CE188[7], V_$006D0B40[0]; +E_006CCA58/15 .event edge, V_$006D0B40[1], V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4]; +E_006CCA58/16 .event edge, V_$006D0B40[5], V_$006D0B40[6], V_$006D0B40[7], V_$006CB750[0]; +E_006CCA58/17 .event edge, V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4]; +E_006CCA58/18 .event edge, V_$006CB750[5], V_$006CB750[6], V_$006CB750[7], V_$006CB9B8[0]; +E_006CCA58/19 .event edge, V_$006D14A8[0], V_$006D14A8[1], V_$006D14A8[2], V_$006D14A8[3]; +E_006CCA58/20 .event edge, V_$006D14A8[4], V_$006D14A8[5], V_$006D14A8[6], V_$006D14A8[7]; +E_006CCA58/21 .event edge, V_$006D14A8[8], V_$006D14A8[9], V_$006CE7B0[0], V_$006CE7B0[1]; +E_006CCA58/22 .event edge, V_$006CE7B0[2], V_$006CE7B0[3], V_$006CE7B0[4], V_$006CE7B0[5]; +E_006CCA58/23 .event edge, V_$006CE7B0[6], V_$006CE7B0[7], V_$006CC7A8[0]; +E_006CCA58 .event/or E_006CCA58/0, E_006CCA58/1, E_006CCA58/2, E_006CCA58/3, E_006CCA58/4, E_006CCA58/5, E_006CCA58/6, E_006CCA58/7, E_006CCA58/8, E_006CCA58/9, E_006CCA58/10, E_006CCA58/11, E_006CCA58/12, E_006CCA58/13, E_006CCA58/14, E_006CCA58/15, E_006CCA58/16, E_006CCA58/17, E_006CCA58/18, E_006CCA58/19, E_006CCA58/20, E_006CCA58/21, E_006CCA58/22, E_006CCA58/23; +E_006CCC00 .event edge, V_$006D6C38[0], V_$006DAD18[0]; +S_006CABC8 .scope module, "u_spiTxRxData" "spiTxRxData", S_006C1500; + .timescale -9; +V_$006CBE48 .net "clk", 0, 0, V_$006E3508[0]; +V_$006CBE80 .net "rst", 0, 0, V_$006DCA00[0]; +V_$006CBEB8 .net "rx1DataRdyClr", 0, 0, V_$006D6920[0]; +V_$006CBF60 .net "rx2DataRdyClr", 0, 0, V_$006D1308[0]; +V_$006CB4F8 .net "rx3DataRdyClr", 0, 0, V_$006DACA8[0]; +V_$006CB568 .net "rx4DataRdyClr", 0, 0, V_$006DAC70[0]; +V_$006CB5F0 .net "rxDataIn", 7, 0, V_$006C90B8[0], V_$006C90B8[1], V_$006C90B8[2], V_$006C90B8[3], V_$006C90B8[4], V_$006C90B8[5], V_$006C90B8[6], V_$006C90B8[7]; +V_$006CB750 .var "rxDataOut", 7, 0; +V_$006CB9B8 .var "rxDataRdy", 0, 0; +V_$006CBA20 .net "rxDataRdySet", 0, 0, V_$006CA688[0]; +V_$006CBA78 .net "tx1DataIn", 7, 0, V_$006D7208[0], V_$006D7208[1], V_$006D7208[2], V_$006D7208[3], V_$006D7208[4], V_$006D7208[5], V_$006D7208[6], V_$006D7208[7]; +V_$006CBD38 .net "tx1DataWEn", 0, 0, V_$006D72A8[0]; +V_$006CC038 .net "tx2DataIn", 7, 0, V_$006D1678[0], V_$006D1678[1], V_$006D1678[2], V_$006D1678[3], V_$006D1678[4], V_$006D1678[5], V_$006D1678[6], V_$006D1678[7]; +V_$006CBAB0 .net "tx2DataWEn", 0, 0, V_$006D17B8[0]; +V_$006CC2F8 .net "tx3DataIn", 7, 0, V_$006D71D0[0], V_$006D71D0[1], V_$006D71D0[2], V_$006D71D0[3], V_$006D71D0[4], V_$006D71D0[5], V_$006D71D0[6], V_$006D71D0[7]; +V_$006CCE78 .net "tx3DataWEn", 0, 0, V_$006DB4B8[0]; +V_$006CCF00 .net "tx4DataIn", 7, 0, V_$006DD220[0], V_$006DD220[1], V_$006DD220[2], V_$006DD220[3], V_$006DD220[4], V_$006DD220[5], V_$006DD220[6], V_$006DD220[7]; +V_$006CC720 .net "tx4DataWEn", 0, 0, V_$006DBDB0[0]; +V_$006CC7A8 .var "txDataFull", 0, 0; +V_$006CC800 .net "txDataFullClr", 0, 0, V_$006CAC78[0]; +V_$006CC858 .var "txDataOut", 7, 0; +S_006C9128 .scope module, "u_readWriteSPIWireData" "readWriteSPIWireData", S_006C1500; + .timescale -9; +V_$006C9298 .var "CurrState_rwSPISt", 1, 0; +V_$006C92D0 .var "NextState_rwSPISt", 1, 0; +V_$006C9BE0 .var "bitCnt", 3, 0; +V_$006C9C18 .net "clk", 0, 0, V_$006E3508[0]; +V_$006C9CC8 .net "clkDelay", 7, 0, V_$006DB188[0], V_$006DB188[1], V_$006DB188[2], V_$006DB188[3], V_$006DB188[4], V_$006DB188[5], V_$006DB188[6], V_$006DB188[7]; +V_$006C9D00 .var "clkDelayCnt", 7, 0; +V_$006C9FA0 .var "next_bitCnt", 3, 0; +V_$006C9440 .var "next_clkDelayCnt", 7, 0; +V_$006C9660 .var "next_rxDataOut", 7, 0; +V_$006C9938 .var "next_rxDataRdySet", 0, 0; +V_$006C99C0 .var "next_rxDataShiftReg", 7, 0; +V_$006CA118 .var "next_spiClkOut", 0, 0; +V_$006CA198 .var "next_spiDataOut", 0, 0; +V_$006C99F8 .var "next_txDataEmpty", 0, 0; +V_$006CA268 .var "next_txDataFullClr", 0, 0; +V_$006CA2F0 .var "next_txDataShiftReg", 7, 0; +V_$006CAEC0 .net "rst", 0, 0, V_$006DCA00[0]; +V_$006C90B8 .var "rxDataOut", 7, 0; +V_$006CA688 .var "rxDataRdySet", 0, 0; +V_$006CA718 .var "rxDataShiftReg", 7, 0; +V_$006CAA28 .var "spiClkOut", 0, 0; +V_$006CAA80 .net "spiDataIn", 0, 0, V_$00644A08[0]; +V_$006CAAD8 .var "spiDataOut", 0, 0; +V_$006CAB30 .var "txDataEmpty", 0, 0; +V_$006CAB90 .net "txDataFull", 0, 0, V_$006CC7A8[0]; +V_$006CAC78 .var "txDataFullClr", 0, 0; +V_$006CAD08 .net "txDataIn", 7, 0, V_$006CC858[0], V_$006CC858[1], V_$006CC858[2], V_$006CC858[3], V_$006CC858[4], V_$006CC858[5], V_$006CC858[6], V_$006CC858[7]; +V_$006CB278 .var "txDataShiftReg", 7, 0; +E_006C8530/0 .event edge, V_$006C9298[0], V_$006C9298[1], V_$006C90B8[0], V_$006C90B8[1]; +E_006C8530/1 .event edge, V_$006C90B8[2], V_$006C90B8[3], V_$006C90B8[4], V_$006C90B8[5]; +E_006C8530/2 .event edge, V_$006C90B8[6], V_$006C90B8[7], V_$006CAAD8[0], V_$006CAA28[0]; +E_006C8530/3 .event edge, V_$006CAC78[0], V_$006CAB30[0], V_$006CA688[0], V_$00644A08[0]; +E_006C8530/4 .event edge, V_$006CA718[0], V_$006CA718[1], V_$006CA718[2], V_$006CA718[3]; +E_006C8530/5 .event edge, V_$006CA718[4], V_$006CA718[5], V_$006CA718[6], V_$006CA718[7]; +E_006C8530/6 .event edge, V_$006C9BE0[0], V_$006C9BE0[1], V_$006C9BE0[2], V_$006C9BE0[3]; +E_006C8530/7 .event edge, V_$006CB278[0], V_$006CB278[1], V_$006CB278[2], V_$006CB278[3]; +E_006C8530/8 .event edge, V_$006CB278[4], V_$006CB278[5], V_$006CB278[6], V_$006CB278[7]; +E_006C8530/9 .event edge, V_$006DB188[0], V_$006DB188[1], V_$006DB188[2], V_$006DB188[3]; +E_006C8530/10 .event edge, V_$006DB188[4], V_$006DB188[5], V_$006DB188[6], V_$006DB188[7]; +E_006C8530/11 .event edge, V_$006C9D00[0], V_$006C9D00[1], V_$006C9D00[2], V_$006C9D00[3]; +E_006C8530/12 .event edge, V_$006C9D00[4], V_$006C9D00[5], V_$006C9D00[6], V_$006C9D00[7]; +E_006C8530/13 .event edge, V_$006CC858[0], V_$006CC858[1], V_$006CC858[2], V_$006CC858[3]; +E_006C8530/14 .event edge, V_$006CC858[4], V_$006CC858[5], V_$006CC858[6], V_$006CC858[7]; +E_006C8530/15 .event edge, V_$006CC7A8[0]; +E_006C8530 .event/or E_006C8530/0, E_006C8530/1, E_006C8530/2, E_006C8530/3, E_006C8530/4, E_006C8530/5, E_006C8530/6, E_006C8530/7, E_006C8530/8, E_006C8530/9, E_006C8530/10, E_006C8530/11, E_006C8530/12, E_006C8530/13, E_006C8530/14, E_006C8530/15; +S_006C4F78 .scope module, "u_txFifo" "TxFifo", S_006C1500; + .timescale -9; +V_$006C86B0 .net "busAddress", 2, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2]; +V_$006C5188 .net "busClk", 0, 0, V_$006DF4B8[0]; +V_$006C5150 .net "busDataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006C5118 .net "busDataOut", 7, 0, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>; +V_$006C8968 .net "busFifoSelect", 0, 0, V_$006DEA20[0]; +V_$006C89E0 .net "busStrobe_i", 0, 0, V_$006607B0[0]; +V_$006C59A8 .net "busWriteEn", 0, 0, V_$006A5C98[0]; +V_$006C5A40 .net "fifoDataOut", 7, 0, V_$006C7CF0[0], V_$006C7CF0[1], V_$006C7CF0[2], V_$006C7CF0[3], V_$006C7CF0[4], V_$006C7CF0[5], V_$006C7CF0[6], V_$006C7CF0[7]; +V_$006C8B48 .net "fifoEmpty", 0, 0, V_$006C7FF8[0]; +V_$006C8BA0 .net "fifoFull", 0, 0, V_$006C8098[0]; +V_$006C8BF8 .net "fifoREn", 0, 0, V_$006D7488[0]; +V_$006C8C68 .net "fifoWEn", 0, 0, V_$006C54B0[0]; +V_$006C8CD8 .net "forceEmptySyncToBusClk", 0, 0, V_$006C5548[0]; +V_$006C8C30 .net "forceEmptySyncToSpiClk", 0, 0, V_$006C55B8[0]; +V_$006C8D10 .net "numElementsInFifo", 15, 0, V_$006C82B8[0], V_$006C82B8[1], V_$006C82B8[2], V_$006C82B8[3], V_$006C82B8[4], V_$006C82B8[5], V_$006C82B8[6], V_$006C82B8[7], V_$006C82B8[8], V_$006C82B8[9], V_$006C82B8[10], V_$006C82B8[11], V_$006C82B8[12], V_$006C82B8[13], V_$006C82B8[14], V_$006C82B8[15]; +V_$006C9048 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0]; +V_$006C9080 .net "rstSyncToSpiClk", 0, 0, V_$006DCA00[0]; +V_$006C90F0 .net "spiSysClk", 0, 0, V_$006E3508[0]; +S_006C5A78 .scope module, "u_fifo" "fifoRTL", S_006C4F78; + .timescale -9; +V_$006C52C8 .var "bufferCnt", 9, 0; +V_$006C5290 .var "bufferInIndex", 9, 0; +V_$006C5258 .var "bufferInIndexSyncToRdClk", 9, 0; +V_$006C7270 .var "bufferInIndexToMem", 8, 0; +V_$006C73C8 .var "bufferOutIndex", 9, 0; +V_$006C7F50 .var "bufferOutIndexSyncToWrClk", 9, 0; +V_$006C77D8 .var "bufferOutIndexToMem", 8, 0; +V_$006C7978 .net "dataFromMem", 7, 0, V_$006C53E0[0], V_$006C53E0[1], V_$006C53E0[2], V_$006C53E0[3], V_$006C53E0[4], V_$006C53E0[5], V_$006C53E0[6], V_$006C53E0[7]; +V_$006C7AD8 .net "dataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006C7CF0 .var "dataOut", 7, 0; +V_$006C7FF8 .var "fifoEmpty", 0, 0; +V_$006C8098 .var "fifoFull", 0, 0; +V_$006C8118 .net "fifoREn", 0, 0, V_$006D7488[0]; +V_$006C8030 .var "fifoREnDelayed", 0, 0; +V_$006C81A0 .net "fifoWEn", 0, 0, V_$006C54B0[0]; +V_$006C81D8 .net "forceEmptySyncToRdClk", 0, 0, V_$006C55B8[0]; +V_$006C8210 .net "forceEmptySyncToWrClk", 0, 0, V_$006C5548[0]; +V_$006C82B8 .var "numElementsInFifo", 15, 0; +V_$006C8550 .net "rdClk", 0, 0, V_$006E3508[0]; +V_$006C85E0 .net "rstSyncToRdClk", 0, 0, V_$006DCA00[0]; +V_$006C8618 .net "rstSyncToWrClk", 0, 0, V_$006DC940[0]; +V_$006C5628 .net "wrClk", 0, 0, V_$006DF4B8[0]; +E_005F17F0/0 .event edge, V_$006C73C8[0], V_$006C73C8[1], V_$006C73C8[2], V_$006C73C8[3]; +E_005F17F0/1 .event edge, V_$006C73C8[4], V_$006C73C8[5], V_$006C73C8[6], V_$006C73C8[7]; +E_005F17F0/2 .event edge, V_$006C73C8[8], V_$006C73C8[9], V_$006C5290[0], V_$006C5290[1]; +E_005F17F0/3 .event edge, V_$006C5290[2], V_$006C5290[3], V_$006C5290[4], V_$006C5290[5]; +E_005F17F0/4 .event edge, V_$006C5290[6], V_$006C5290[7], V_$006C5290[8], V_$006C5290[9]; +E_005F17F0 .event/or E_005F17F0/0, E_005F17F0/1, E_005F17F0/2, E_005F17F0/3, E_005F17F0/4; +E_003DDD60/0 .event edge, V_$006C73C8[0], V_$006C73C8[1], V_$006C73C8[2], V_$006C73C8[3]; +E_003DDD60/1 .event edge, V_$006C73C8[4], V_$006C73C8[5], V_$006C73C8[6], V_$006C73C8[7]; +E_003DDD60/2 .event edge, V_$006C73C8[8], V_$006C73C8[9], V_$006C5258[0], V_$006C5258[1]; +E_003DDD60/3 .event edge, V_$006C5258[2], V_$006C5258[3], V_$006C5258[4], V_$006C5258[5]; +E_003DDD60/4 .event edge, V_$006C5258[6], V_$006C5258[7], V_$006C5258[8], V_$006C5258[9]; +E_003DDD60 .event/or E_003DDD60/0, E_003DDD60/1, E_003DDD60/2, E_003DDD60/3, E_003DDD60/4; +S_006C5C68 .scope module, "u_dpMem_dc" "dpMem_dc", S_006C5A78; + .timescale -9; +V_$006C5B38 .net "addrIn", 8, 0, V_$006C7270[0], V_$006C7270[1], V_$006C7270[2], V_$006C7270[3], V_$006C7270[4], V_$006C7270[5], V_$006C7270[6], V_$006C7270[7], V_$006C7270[8]; +V_$006C6048 .net "addrOut", 8, 0, V_$006C77D8[0], V_$006C77D8[1], V_$006C77D8[2], V_$006C77D8[3], V_$006C77D8[4], V_$006C77D8[5], V_$006C77D8[6], V_$006C77D8[7], V_$006C77D8[8]; +V_$006C6340 .net "dataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006C53E0 .var "dataOut", 7, 0; +V_$006C53A8 .net "rdClk", 0, 0, V_$006E3508[0]; +V_$006C5370 .net "readEn", 0, 0, V_$006D7488[0]; +V_$006C5338 .net "wrClk", 0, 0, V_$006DF4B8[0]; +V_$006C5300 .net "writeEn", 0, 0, V_$006C54B0[0]; +M_$006C68E0 .mem "buffer", 7,0, 0,511; +S_006C5098 .scope module, "u_TxfifoBI" "TxfifoBI", S_006C4F78; + .timescale -9; +V_$006C5060 .net "address", 2, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2]; +V_$006C51C0 .net "busClk", 0, 0, V_$006DF4B8[0]; +V_$006C51F8 .net "busDataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006C5418 .net "busDataOut", 7, 0, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>; +V_$006C5478 .net "fifoSelect", 0, 0, V_$006DEA20[0]; +V_$006C54B0 .var "fifoWEn", 0, 0; +V_$006C54E8 .var "forceEmpty", 0, 0; +V_$006C5548 .var "forceEmptyShift", 5, 0; +V_$006C5580 .net "forceEmptySyncToBusClk", 0, 0, V_$006C5548[0]; +V_$006C55B8 .var "forceEmptySyncToSpiClk", 0, 0; +V_$006C55F0 .var "forceEmptySyncToSpiClkFirst", 0, 0; +V_$006C5660 .net "numElementsInFifo", 15, 0, V_$006C82B8[0], V_$006C82B8[1], V_$006C82B8[2], V_$006C82B8[3], V_$006C82B8[4], V_$006C82B8[5], V_$006C82B8[6], V_$006C82B8[7], V_$006C82B8[8], V_$006C82B8[9], V_$006C82B8[10], V_$006C82B8[11], V_$006C82B8[12], V_$006C82B8[13], V_$006C82B8[14], V_$006C82B8[15]; +V_$006C58F0 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0]; +V_$006C5928 .net "spiSysClk", 0, 0, V_$006E3508[0]; +V_$006C4F40 .net "strobe_i", 0, 0, V_$006607B0[0]; +V_$006C5A08 .net "writeEn", 0, 0, V_$006A5C98[0]; +E_006C45B0/0 .event edge, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3]; +E_006C45B0/1 .event edge, V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +E_006C45B0/2 .event edge, V_$006DEA20[0], V_$006607B0[0], V_$006A5C98[0], V_$0068AE60[0]; +E_006C45B0/3 .event edge, V_$0068AE60[1], V_$0068AE60[2]; +E_006C45B0 .event/or E_006C45B0/0, E_006C45B0/1, E_006C45B0/2, E_006C45B0/3; +S_006C1570 .scope module, "u_rxFifo" "RxFifo", S_006C1500; + .timescale -9; +V_$006C4760 .net "busAddress", 2, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2]; +V_$006C4798 .net "busClk", 0, 0, V_$006DF4B8[0]; +V_$006C4660 .net "busDataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006C4840 .net "busDataOut", 7, 0, V_$006A5290[0], V_$006A5290[1], V_$006A5290[2], V_$006A5290[3], V_$006A5290[4], V_$006A5290[5], V_$006A5290[6], V_$006A5290[7]; +V_$006C48A0 .net "busFifoSelect", 0, 0, V_$006DE9B8[0]; +V_$006C48D8 .net "busStrobe_i", 0, 0, V_$006607B0[0]; +V_$006C4910 .net "busWriteEn", 0, 0, V_$006A5C98[0]; +V_$006C4970 .net "dataFromFifoToBus", 7, 0, V_$006C4090[0], V_$006C4090[1], V_$006C4090[2], V_$006C4090[3], V_$006C4090[4], V_$006C4090[5], V_$006C4090[6], V_$006C4090[7]; +V_$006C49D0 .net "fifoDataIn", 7, 0, V_$006D6958[0], V_$006D6958[1], V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5], V_$006D6958[6], V_$006D6958[7]; +V_$006C4A08 .net "fifoEmpty", 0, 0, V_$006C41F0[0]; +V_$006C4A40 .net "fifoFull", 0, 0, V_$006C4260[0]; +V_$006C4AB0 .net "fifoREn", 0, 0, V_$006A76F0[0]; +V_$006C4B20 .net "fifoWEn", 0, 0, V_$006D6B90[0]; +V_$006C4A78 .net "forceEmptySyncToBusClk", 0, 0, V_$00666B38[0]; +V_$006C4B58 .net "forceEmptySyncToSpiClk", 0, 0, V_$006A9EA0[0]; +V_$006C4BD8 .net "numElementsInFifo", 15, 0, V_$006C4398[0], V_$006C4398[1], V_$006C4398[2], V_$006C4398[3], V_$006C4398[4], V_$006C4398[5], V_$006C4398[6], V_$006C4398[7], V_$006C4398[8], V_$006C4398[9], V_$006C4398[10], V_$006C4398[11], V_$006C4398[12], V_$006C4398[13], V_$006C4398[14], V_$006C4398[15]; +V_$006C4E68 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0]; +V_$006C4ED0 .net "rstSyncToSpiClk", 0, 0, V_$006DCA00[0]; +V_$006C4F08 .net "spiSysClk", 0, 0, V_$006E3508[0]; +S_006C2110 .scope module, "u_fifo" "fifoRTL", S_006C1570; + .timescale -9; +V_$006C2810 .var "bufferCnt", 9, 0; +V_$006C2B10 .var "bufferInIndex", 9, 0; +V_$006C3170 .var "bufferInIndexSyncToRdClk", 9, 0; +V_$006C3508 .var "bufferInIndexToMem", 8, 0; +V_$006C3600 .var "bufferOutIndex", 9, 0; +V_$006C3D38 .var "bufferOutIndexSyncToWrClk", 9, 0; +V_$006C3740 .var "bufferOutIndexToMem", 8, 0; +V_$006C3898 .net "dataFromMem", 7, 0, V_$00639738[0], V_$00639738[1], V_$00639738[2], V_$00639738[3], V_$00639738[4], V_$00639738[5], V_$00639738[6], V_$00639738[7]; +V_$006C39F8 .net "dataIn", 7, 0, V_$006D6958[0], V_$006D6958[1], V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5], V_$006D6958[6], V_$006D6958[7]; +V_$006C4090 .var "dataOut", 7, 0; +V_$006C41F0 .var "fifoEmpty", 0, 0; +V_$006C4260 .var "fifoFull", 0, 0; +V_$006C4298 .net "fifoREn", 0, 0, V_$006A76F0[0]; +V_$006C4228 .var "fifoREnDelayed", 0, 0; +V_$006C42D0 .net "fifoWEn", 0, 0, V_$006D6B90[0]; +V_$006C4308 .net "forceEmptySyncToRdClk", 0, 0, V_$00666B38[0]; +V_$006C4360 .net "forceEmptySyncToWrClk", 0, 0, V_$006A9EA0[0]; +V_$006C4398 .var "numElementsInFifo", 15, 0; +V_$006C45D0 .net "rdClk", 0, 0, V_$006DF4B8[0]; +V_$006C4698 .net "rstSyncToRdClk", 0, 0, V_$006DC940[0]; +V_$006C46F0 .net "rstSyncToWrClk", 0, 0, V_$006DCA00[0]; +V_$006C4728 .net "wrClk", 0, 0, V_$006E3508[0]; +E_005EEF18/0 .event edge, V_$006C3600[0], V_$006C3600[1], V_$006C3600[2], V_$006C3600[3]; +E_005EEF18/1 .event edge, V_$006C3600[4], V_$006C3600[5], V_$006C3600[6], V_$006C3600[7]; +E_005EEF18/2 .event edge, V_$006C3600[8], V_$006C3600[9], V_$006C2B10[0], V_$006C2B10[1]; +E_005EEF18/3 .event edge, V_$006C2B10[2], V_$006C2B10[3], V_$006C2B10[4], V_$006C2B10[5]; +E_005EEF18/4 .event edge, V_$006C2B10[6], V_$006C2B10[7], V_$006C2B10[8], V_$006C2B10[9]; +E_005EEF18 .event/or E_005EEF18/0, E_005EEF18/1, E_005EEF18/2, E_005EEF18/3, E_005EEF18/4; +E_005EE048/0 .event edge, V_$006C3600[0], V_$006C3600[1], V_$006C3600[2], V_$006C3600[3]; +E_005EE048/1 .event edge, V_$006C3600[4], V_$006C3600[5], V_$006C3600[6], V_$006C3600[7]; +E_005EE048/2 .event edge, V_$006C3600[8], V_$006C3600[9], V_$006C3170[0], V_$006C3170[1]; +E_005EE048/3 .event edge, V_$006C3170[2], V_$006C3170[3], V_$006C3170[4], V_$006C3170[5]; +E_005EE048/4 .event edge, V_$006C3170[6], V_$006C3170[7], V_$006C3170[8], V_$006C3170[9]; +E_005EE048 .event/or E_005EE048/0, E_005EE048/1, E_005EE048/2, E_005EE048/3, E_005EE048/4; +S_006C2228 .scope module, "u_dpMem_dc" "dpMem_dc", S_006C2110; + .timescale -9; +V_$006AC480 .net "addrIn", 8, 0, V_$006C3508[0], V_$006C3508[1], V_$006C3508[2], V_$006C3508[3], V_$006C3508[4], V_$006C3508[5], V_$006C3508[6], V_$006C3508[7], V_$006C3508[8]; +V_$006AC4E0 .net "addrOut", 8, 0, V_$006C3740[0], V_$006C3740[1], V_$006C3740[2], V_$006C3740[3], V_$006C3740[4], V_$006C3740[5], V_$006C3740[6], V_$006C3740[7], V_$006C3740[8]; +V_$006AD2C8 .net "dataIn", 7, 0, V_$006D6958[0], V_$006D6958[1], V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5], V_$006D6958[6], V_$006D6958[7]; +V_$00639738 .var "dataOut", 7, 0; +V_$00615800 .net "rdClk", 0, 0, V_$006DF4B8[0]; +V_$005E3868 .net "readEn", 0, 0, V_$006A76F0[0]; +V_$006C2778 .net "wrClk", 0, 0, V_$006E3508[0]; +V_$006C27D8 .net "writeEn", 0, 0, V_$006D6B90[0]; +M_$005D1E00 .mem "buffer", 7,0, 0,511; +S_006C1658 .scope module, "u_RxfifoBI" "RxfifoBI", S_006C1570; + .timescale -9; +V_$006A4EE8 .net "address", 2, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2]; +V_$006A6E08 .net "busClk", 0, 0, V_$006DF4B8[0]; +V_$0065A890 .net "busDataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7]; +V_$006A5290 .var "busDataOut", 7, 0; +V_$00660078 .net "fifoDataIn", 7, 0, V_$006C4090[0], V_$006C4090[1], V_$006C4090[2], V_$006C4090[3], V_$006C4090[4], V_$006C4090[5], V_$006C4090[6], V_$006C4090[7]; +V_$006A76F0 .var "fifoREn", 0, 0; +V_$006A7BA8 .net "fifoSelect", 0, 0, V_$006DE9B8[0]; +V_$006A7DD8 .var "forceEmpty", 0, 0; +V_$00666B38 .var "forceEmptyShift", 5, 0; +V_$006A8D90 .net "forceEmptySyncToBusClk", 0, 0, V_$00666B38[0]; +V_$006A9EA0 .var "forceEmptySyncToSpiClk", 0, 0; +V_$006A8850 .var "forceEmptySyncToUsbClkFirst", 0, 0; +V_$00666678 .net "numElementsInFifo", 15, 0, V_$006C4398[0], V_$006C4398[1], V_$006C4398[2], V_$006C4398[3], V_$006C4398[4], V_$006C4398[5], V_$006C4398[6], V_$006C4398[7], V_$006C4398[8], V_$006C4398[9], V_$006C4398[10], V_$006C4398[11], V_$006C4398[12], V_$006C4398[13], V_$006C4398[14], V_$006C4398[15]; +V_$0065D6E8 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0]; +V_$006AACA0 .net "spiSysClk", 0, 0, V_$006E3508[0]; +V_$006AA8A8 .net "strobe_i", 0, 0, V_$006607B0[0]; +V_$006685B0 .net "writeEn", 0, 0, V_$006A5C98[0]; +E_003DDB00/0 .event edge, V_$006DE9B8[0], V_$006607B0[0], V_$006A5C98[0], V_$0068AE60[0]; +E_003DDB00/1 .event edge, V_$0068AE60[1], V_$0068AE60[2]; +E_003DDB00 .event/or E_003DDB00/0, E_003DDB00/1; +E_003DDC30/0 .event edge, V_$006C4398[0], V_$006C4398[1], V_$006C4398[2], V_$006C4398[3]; +E_003DDC30/1 .event edge, V_$006C4398[4], V_$006C4398[5], V_$006C4398[6], V_$006C4398[7]; +E_003DDC30/2 .event edge, V_$006C4398[8], V_$006C4398[9], V_$006C4398[10], V_$006C4398[11]; +E_003DDC30/3 .event edge, V_$006C4398[12], V_$006C4398[13], V_$006C4398[14], V_$006C4398[15]; +E_003DDC30/4 .event edge, V_$006C4090[0], V_$006C4090[1], V_$006C4090[2], V_$006C4090[3]; +E_003DDC30/5 .event edge, V_$006C4090[4], V_$006C4090[5], V_$006C4090[6], V_$006C4090[7]; +E_003DDC30/6 .event edge, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2]; +E_003DDC30 .event/or E_003DDC30/0, E_003DDC30/1, E_003DDC30/2, E_003DDC30/3, E_003DDC30/4, E_003DDC30/5, E_003DDC30/6; +E_003DE478 .event posedge, V_$006E3508[0]; +S_00624D88 .scope module, "u_wb_master_model" "wb_master_model", S_006338F0; + .timescale -9; +V_$00689E98 .net "ack", 0, 0, V_$006DE038[0]; +V_$0068AE60 .var "adr", 7, 0; +V_$00698EA8 .net "clk", 0, 0, V_$006DF4B8[0]; +V_$0069A858 .var "cyc", 0, 0; +V_$00657510 .net "din", 7, 0, V_$006DE8E8[0], V_$006DE8E8[1], V_$006DE8E8[2], V_$006DE8E8[3], V_$006DE8E8[4], V_$006DE8E8[5], V_$006DE8E8[6], V_$006DE8E8[7]; +V_$0069AA18 .var "dout", 7, 0; +V_$0069FC50 .net "err", 0, 0, C<0>; +V_$006A05F8 .var "q", 7, 0; +V_$006A0F58 .net "rst", 0, 0, V_$006E0BD0[0]; +V_$006A10B0 .net "rty", 0, 0, C<0>; +V_$006A4238 .var "sel", 0, 0; +V_$006607B0 .var "stb", 0, 0; +V_$006A5C98 .var "we", 0, 0; +S_005FFF10 .scope task, "wb_cmp" "testHarness.u_wb_master_model.wb_cmp", S_00624D88; + .timescale -9; +V_$0067FD60 .var "a", 7, 0; +V_$00682498 .var "d_exp", 7, 0; +V_$00682CF8 .var/i "delay", 31, 0; +TD_testHarness.u_wb_master_model.wb_cmp ; + %load/v 32, V_$00682CF8[0], 32; + %set/v V_$0067ECA0[0], 32, 32; + %load/v 32, V_$0067FD60[0], 8; + %set/v V_$0067E7C8[0], 32, 8; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006A05F8[0], 32, 8; + %load/v 32, V_$00682498[0], 8; + %load/v 40, V_$006A05F8[0], 8; + %cmp/u 32, 40, 8; + %inv 6, 1; + %mov 32, 6, 1; + %jmp/0xz T_0.0, 32; + %vpi_call "$display", "Data compare error. Received %h, expected %h at time %t", V_$006A05F8, V_$00682498, $time; +T_0.0 ; + %end; +S_003D31C0 .scope task, "wb_read" "testHarness.u_wb_master_model.wb_read", S_00624D88; + .timescale -9; +V_$0067E7C8 .var "a", 7, 0; +V_$0067EE18 .var "d", 7, 0; +V_$0067ECA0 .var/i "delay", 31, 0; +TD_testHarness.u_wb_master_model.wb_read ; + %load/v 32, V_$0067ECA0[0], 32; +T_1.2 %cmp/u 0, 32, 32; + %jmp/0xz T_1.3, 5; + %add 32, 1, 32; + %wait E_003DE0F8; + %jmp T_1.2; +T_1.3 ; + %delay 1000; + %load/v 32, V_$0067E7C8[0], 8; + %set/v V_$0068AE60[0], 32, 8; + %set/v V_$0069AA18[0], 2, 8; + %set V_$0069A858[0], 1; + %set V_$006607B0[0], 1; + %set V_$006A5C98[0], 0; + %set V_$006A4238[0], 1; + %wait E_003DE0F8; +T_1.4 ; + %load 32, V_$00689E98[0]; + %inv 32, 1; + %jmp/0xz T_1.5, 32; + %wait E_003DE0F8; + %jmp T_1.4; +T_1.5 ; + %delay 1000; + %set V_$0069A858[0], 0; + %set V_$006607B0[0], 2; + %set/v V_$0068AE60[0], 2, 8; + %set/v V_$0069AA18[0], 2, 8; + %set V_$006A5C98[0], 2; + %set V_$006A4238[0], 2; + %load 32, V_$00657510[0]; + %load 33, V_$00657510[1]; + %load 34, V_$00657510[2]; + %load 35, V_$00657510[3]; + %load 36, V_$00657510[4]; + %load 37, V_$00657510[5]; + %load 38, V_$00657510[6]; + %load 39, V_$00657510[7]; + %set/v V_$0067EE18[0], 32, 8; + %end; +S_0062CD78 .scope task, "wb_write" "testHarness.u_wb_master_model.wb_write", S_00624D88; + .timescale -9; +V_$0067C5F0 .var "a", 7, 0; +V_$0067D930 .var "d", 7, 0; +V_$0067E2E8 .var/i "delay", 31, 0; +E_003DE0F8 .event posedge, V_$006DF4B8[0]; +TD_testHarness.u_wb_master_model.wb_write ; + %load/v 32, V_$0067E2E8[0], 32; +T_2.6 %cmp/u 0, 32, 32; + %jmp/0xz T_2.7, 5; + %add 32, 1, 32; + %wait E_003DE0F8; + %jmp T_2.6; +T_2.7 ; + %delay 1000; + %load/v 32, V_$0067C5F0[0], 8; + %set/v V_$0068AE60[0], 32, 8; + %load/v 32, V_$0067D930[0], 8; + %set/v V_$0069AA18[0], 32, 8; + %set V_$0069A858[0], 1; + %set V_$006607B0[0], 1; + %set V_$006A5C98[0], 1; + %set V_$006A4238[0], 1; + %wait E_003DE0F8; +T_2.8 ; + %load 32, V_$00689E98[0]; + %inv 32, 1; + %jmp/0xz T_2.9, 32; + %wait E_003DE0F8; + %jmp T_2.8; +T_2.9 ; + %delay 1000; + %set V_$0069A858[0], 0; + %set V_$006607B0[0], 2; + %set/v V_$0068AE60[0], 2, 8; + %set/v V_$0069AA18[0], 2, 8; + %set V_$006A5C98[0], 2; + %set V_$006A4238[0], 2; + %end; +S_00633880 .scope module, "u_sdModel" "sdModel", S_006338F0; + .timescale -9; +V_$006B0438 .var "cnt", 7, 0; +V_$006B0578 .var "respByte", 7, 0; +V_$006B0718 .var "rxByte", 7, 0; +V_$006B08C8 .var "smSt", 1, 0; +V_$0066EE28 .net "spiCS_n", 0, 0, L_006E3660; +V_$0063FB48 .net "spiClk", 0, 0, V_$006CAA28[0]; +V_$0067A3E8 .net "spiDataIn", 0, 0, V_$006CAAD8[0]; +V_$00644A08 .var "spiDataOut", 0, 0; +S_005C89B8 .scope task, "setRespByte" "testHarness.u_sdModel.setRespByte", S_00633880; + .timescale -9; +V_$006B0310 .var "dataByte", 7, 0; +TD_testHarness.u_sdModel.setRespByte ; + %load/v 32, V_$006B0310[0], 8; + %set/v V_$006B0578[0], 32, 8; + %end; +S_006399E8 .scope task, "txRxByte" "testHarness.u_sdModel.txRxByte", S_00633880; + .timescale -9; +V_$006AFF68 .var/i "i", 31, 0; +V_$006B00C0 .var "rxData", 7, 0; +V_$006B01E8 .var "txData", 7, 0; +E_00639FE8 .event negedge, V_$006CAA28[0]; +E_00619EB0 .event posedge, V_$006CAA28[0]; +TD_testHarness.u_sdModel.txRxByte ; + %load/v 32, V_$006B01E8[7], 1; + %assign V_$00644A08[0], 0, 32; + %set/v V_$006AFF68[0], 0, 32; +T_4.10 ; + %load/v 32, V_$006AFF68[0], 32; + %mov 64, 1, 3; + %mov 67, 0, 29; + %cmp/s 32, 64, 32; + %or 5, 4, 1; + %jmp/0xz T_4.11, 5; + %wait E_00619EB0; + %load 32, V_$0067A3E8[0]; + %assign V_$006B00C0[0], 0, 32; + %load/v 32, V_$006B00C0[0], 8; + %ix/load 0, 1; + %shiftl/i0 32, 8; + %set/v V_$006B00C0[0], 32, 8; + %wait E_00639FE8; + %load/v 32, V_$006B01E8[6], 1; + %assign V_$00644A08[0], 0, 32; + %load/v 32, V_$006B01E8[0], 8; + %ix/load 0, 1; + %shiftl/i0 32, 8; + %set/v V_$006B01E8[0], 32, 8; + %load/v 32, V_$006AFF68[0], 32; + %addi 32, 1, 32; + %set/v V_$006AFF68[0], 32, 32; + %jmp T_4.10; +T_4.11 ; + %end; + .scope S_005FC090; +T_5 ; + %vpi_call "$write", "\n\n"; + %delay 1000000; + %vpi_call "$write", "Testing register read/write\n"; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set/v V_$0067C5F0[0], 1, 3; + %set/v V_$0067C5F0[3], 0, 5; + %set/v V_$0067D930[0], 0, 3; + %set/v V_$0067D930[3], 1, 4; + %set V_$0067D930[7], 0; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set/v V_$0067C5F0[0], 0, 3; + %set V_$0067C5F0[3], 1; + %set/v V_$0067C5F0[4], 0, 4; + %set V_$0067D930[0], 0; + %set/v V_$0067D930[1], 1, 2; + %set V_$0067D930[3], 0; + %set V_$0067D930[4], 1; + %set V_$0067D930[5], 0; + %set V_$0067D930[6], 1; + %set V_$0067D930[7], 0; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set V_$0067C5F0[0], 1; + %set/v V_$0067C5F0[1], 0, 2; + %set V_$0067C5F0[3], 1; + %set/v V_$0067C5F0[4], 0, 4; + %set/v V_$0067D930[0], 0, 2; + %set V_$0067D930[2], 1; + %set V_$0067D930[3], 0; + %set/v V_$0067D930[4], 1, 2; + %set/v V_$0067D930[6], 0, 2; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set V_$0067C5F0[0], 0; + %set V_$0067C5F0[1], 1; + %set V_$0067C5F0[2], 0; + %set V_$0067C5F0[3], 1; + %set/v V_$0067C5F0[4], 0, 4; + %set V_$0067D930[0], 0; + %set V_$0067D930[1], 1; + %set/v V_$0067D930[2], 0, 2; + %set V_$0067D930[4], 1; + %set/v V_$0067D930[5], 0, 3; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$00682CF8[0], 1; + %set V_$00682CF8[1], 0; + %set/v V_$00682CF8[2], 0, 30; + %set/v V_$0067FD60[0], 1, 3; + %set/v V_$0067FD60[3], 0, 5; + %set/v V_$00682498[0], 0, 3; + %set/v V_$00682498[3], 1, 4; + %set V_$00682498[7], 0; + %fork TD_testHarness.u_wb_master_model.wb_cmp, S_005FFF10; + %join; + %set V_$00682CF8[0], 1; + %set V_$00682CF8[1], 0; + %set/v V_$00682CF8[2], 0, 30; + %set/v V_$0067FD60[0], 0, 3; + %set V_$0067FD60[3], 1; + %set/v V_$0067FD60[4], 0, 4; + %set V_$00682498[0], 0; + %set/v V_$00682498[1], 1, 2; + %set V_$00682498[3], 0; + %set V_$00682498[4], 1; + %set V_$00682498[5], 0; + %set V_$00682498[6], 1; + %set V_$00682498[7], 0; + %fork TD_testHarness.u_wb_master_model.wb_cmp, S_005FFF10; + %join; + %set V_$00682CF8[0], 1; + %set V_$00682CF8[1], 0; + %set/v V_$00682CF8[2], 0, 30; + %set V_$0067FD60[0], 1; + %set/v V_$0067FD60[1], 0, 2; + %set V_$0067FD60[3], 1; + %set/v V_$0067FD60[4], 0, 4; + %set/v V_$00682498[0], 0, 2; + %set V_$00682498[2], 1; + %set V_$00682498[3], 0; + %set/v V_$00682498[4], 1, 2; + %set/v V_$00682498[6], 0, 2; + %fork TD_testHarness.u_wb_master_model.wb_cmp, S_005FFF10; + %join; + %set V_$00682CF8[0], 1; + %set V_$00682CF8[1], 0; + %set/v V_$00682CF8[2], 0, 30; + %set V_$0067FD60[0], 0; + %set V_$0067FD60[1], 1; + %set V_$0067FD60[2], 0; + %set V_$0067FD60[3], 1; + %set/v V_$0067FD60[4], 0, 4; + %set V_$00682498[0], 0; + %set V_$00682498[1], 1; + %set/v V_$00682498[2], 0, 2; + %set V_$00682498[4], 1; + %set/v V_$00682498[5], 0, 3; + %fork TD_testHarness.u_wb_master_model.wb_cmp, S_005FFF10; + %join; + %vpi_call "$write", "Testing SPI bus direct access\n"; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set V_$0067C5F0[0], 0; + %set V_$0067C5F0[1], 1; + %set/v V_$0067C5F0[2], 0, 6; + %set/v V_$0067D930[0], 0, 8; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set V_$0067C5F0[0], 0; + %set/v V_$0067C5F0[1], 1, 2; + %set/v V_$0067C5F0[3], 0, 5; + %set/v V_$0067D930[0], 1, 5; + %set V_$0067D930[5], 0; + %set V_$0067D930[6], 1; + %set V_$0067D930[7], 0; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set/v V_$0067C5F0[0], 1, 2; + %set/v V_$0067C5F0[2], 0, 6; + %set V_$0067D930[0], 1; + %set/v V_$0067D930[1], 0, 7; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067ECA0[0], 1; + %set V_$0067ECA0[1], 0; + %set/v V_$0067ECA0[2], 0, 30; + %set/v V_$0067E7C8[0], 0, 2; + %set V_$0067E7C8[2], 1; + %set/v V_$0067E7C8[3], 0, 5; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006AD848[0], 32, 8; +T_5.0 ; + %load/v 32, V_$006AD848[0], 1; + %jmp/0xz T_5.1, 32; + %set V_$0067ECA0[0], 1; + %set V_$0067ECA0[1], 0; + %set/v V_$0067ECA0[2], 0, 30; + %set/v V_$0067E7C8[0], 0, 2; + %set V_$0067E7C8[2], 1; + %set/v V_$0067E7C8[3], 0, 5; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006AD848[0], 32, 8; + %jmp T_5.0; +T_5.1 ; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set V_$0067C5F0[0], 0; + %set/v V_$0067C5F0[1], 1, 2; + %set/v V_$0067C5F0[3], 0, 5; + %set V_$0067D930[0], 0; + %set V_$0067D930[1], 1; + %set V_$0067D930[2], 0; + %set V_$0067D930[3], 1; + %set V_$0067D930[4], 0; + %set V_$0067D930[5], 1; + %set V_$0067D930[6], 0; + %set V_$0067D930[7], 1; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set/v V_$0067C5F0[0], 1, 2; + %set/v V_$0067C5F0[2], 0, 6; + %set V_$0067D930[0], 1; + %set/v V_$0067D930[1], 0, 7; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067ECA0[0], 1; + %set V_$0067ECA0[1], 0; + %set/v V_$0067ECA0[2], 0, 30; + %set/v V_$0067E7C8[0], 0, 2; + %set V_$0067E7C8[2], 1; + %set/v V_$0067E7C8[3], 0, 5; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006AD848[0], 32, 8; +T_5.2 ; + %load/v 32, V_$006AD848[0], 1; + %jmp/0xz T_5.3, 32; + %set V_$0067ECA0[0], 1; + %set V_$0067ECA0[1], 0; + %set/v V_$0067ECA0[2], 0, 30; + %set/v V_$0067E7C8[0], 0, 2; + %set V_$0067E7C8[2], 1; + %set/v V_$0067E7C8[3], 0, 5; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006AD848[0], 32, 8; + %jmp T_5.2; +T_5.3 ; + %vpi_call "$write", "Testing SD init\n"; + %set V_$006B0310[0], 1; + %set/v V_$006B0310[1], 0, 7; + %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set V_$0067C5F0[0], 0; + %set V_$0067C5F0[1], 1; + %set/v V_$0067C5F0[2], 0, 6; + %set V_$0067D930[0], 1; + %set/v V_$0067D930[1], 0, 7; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set/v V_$0067C5F0[0], 1, 2; + %set/v V_$0067C5F0[2], 0, 6; + %set V_$0067D930[0], 1; + %set/v V_$0067D930[1], 0, 7; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %delay 60000000; + %set/v V_$006B0310[0], 0, 8; + %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8; + %join; + %set V_$0067ECA0[0], 1; + %set V_$0067ECA0[1], 0; + %set/v V_$0067ECA0[2], 0, 30; + %set/v V_$0067E7C8[0], 0, 2; + %set V_$0067E7C8[2], 1; + %set/v V_$0067E7C8[3], 0, 5; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006AD848[0], 32, 8; +T_5.4 ; + %load/v 32, V_$006AD848[0], 1; + %jmp/0xz T_5.5, 32; + %set V_$0067ECA0[0], 1; + %set V_$0067ECA0[1], 0; + %set/v V_$0067ECA0[2], 0, 30; + %set/v V_$0067E7C8[0], 0, 2; + %set V_$0067E7C8[2], 1; + %set/v V_$0067E7C8[3], 0, 5; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006AD848[0], 32, 8; + %jmp T_5.4; +T_5.5 ; + %set V_$0067ECA0[0], 1; + %set V_$0067ECA0[1], 0; + %set/v V_$0067ECA0[2], 0, 30; + %set V_$0067E7C8[0], 1; + %set V_$0067E7C8[1], 0; + %set V_$0067E7C8[2], 1; + %set/v V_$0067E7C8[3], 0, 5; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006AD848[0], 32, 8; + %load/v 32, V_$006AD848[0], 2; + %cmpi/u 32, 0, 2; + %jmp/0xz T_5.6, 4; + %vpi_call "$write", "SD init test passed\n"; + %jmp T_5.7; +T_5.6 ; + %load/v 32, V_$006AD848[0], 2; + %vpi_call "$write", "---- ERROR: SD init test failed. Error code = 0x%01x\n", T<32,2,u>; +T_5.7 ; + %vpi_call "$write", "Testing block write\n"; + %set/v V_$006AFD38[0], 0, 8; + %set/v V_$006AFE40[0], 0, 32; +T_5.8 ; + %load/v 32, V_$006AFE40[0], 32; + %mov 64, 1, 9; + %mov 73, 0, 23; + %cmp/s 32, 64, 32; + %or 5, 4, 1; + %jmp/0xz T_5.9, 5; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set/v V_$0067C5F0[0], 0, 5; + %set V_$0067C5F0[5], 1; + %set/v V_$0067C5F0[6], 0, 2; + %load/v 32, V_$006AFD38[0], 8; + %set/v V_$0067D930[0], 32, 8; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %load/v 32, V_$006AFD38[0], 8; + %addi 32, 1, 8; + %set/v V_$006AFD38[0], 32, 8; + %load/v 32, V_$006AFE40[0], 32; + %addi 32, 1, 32; + %set/v V_$006AFE40[0], 32, 32; + %jmp T_5.8; +T_5.9 ; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set V_$0067C5F0[0], 0; + %set V_$0067C5F0[1], 1; + %set/v V_$0067C5F0[2], 0, 6; + %set/v V_$0067D930[0], 1, 2; + %set/v V_$0067D930[2], 0, 6; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set/v V_$0067C5F0[0], 1, 2; + %set/v V_$0067C5F0[2], 0, 6; + %set V_$0067D930[0], 1; + %set/v V_$0067D930[1], 0, 7; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %delay 100000000; + %set V_$006B0310[0], 1; + %set V_$006B0310[1], 0; + %set V_$006B0310[2], 1; + %set/v V_$006B0310[3], 0, 5; + %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8; + %join; + %delay 400000000; + %set V_$0067ECA0[0], 1; + %set V_$0067ECA0[1], 0; + %set/v V_$0067ECA0[2], 0, 30; + %set V_$0067E7C8[0], 1; + %set V_$0067E7C8[1], 0; + %set V_$0067E7C8[2], 1; + %set/v V_$0067E7C8[3], 0, 5; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006AD848[0], 32, 8; + %load/v 32, V_$006AD848[4], 2; + %cmpi/u 32, 0, 2; + %jmp/0xz T_5.10, 4; + %vpi_call "$write", "SD block write passed\n"; + %jmp T_5.11; +T_5.10 ; + %load/v 32, V_$006AD848[4], 2; + %vpi_call "$write", "---- ERROR: SD block write failed. Error code = 0x%01x\n", T<32,2,u>; +T_5.11 ; + %vpi_call "$write", "Testing block read\n"; + %set/v V_$006B0310[0], 0, 8; + %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set V_$0067C5F0[0], 0; + %set V_$0067C5F0[1], 1; + %set/v V_$0067C5F0[2], 0, 6; + %set V_$0067D930[0], 0; + %set V_$0067D930[1], 1; + %set/v V_$0067D930[2], 0, 6; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set/v V_$0067C5F0[0], 1, 2; + %set/v V_$0067C5F0[2], 0, 6; + %set V_$0067D930[0], 1; + %set/v V_$0067D930[1], 0, 7; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %delay 100000000; + %set V_$006B0310[0], 1; + %set V_$006B0310[1], 0; + %set V_$006B0310[2], 1; + %set/v V_$006B0310[3], 0, 5; + %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8; + %join; + %delay 400000000; + %set V_$0067ECA0[0], 1; + %set V_$0067ECA0[1], 0; + %set/v V_$0067ECA0[2], 0, 30; + %set V_$0067E7C8[0], 1; + %set V_$0067E7C8[1], 0; + %set V_$0067E7C8[2], 1; + %set/v V_$0067E7C8[3], 0, 5; + %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0; + %join; + %load/v 32, V_$0067EE18[0], 8; + %set/v V_$006AD848[0], 32, 8; + %load/v 32, V_$006AD848[2], 2; + %cmpi/u 32, 0, 2; + %jmp/0xz T_5.12, 4; + %vpi_call "$write", "SD block read passed\n"; + %jmp T_5.13; +T_5.12 ; + %load/v 32, V_$006AD848[2], 2; + %vpi_call "$write", "---- ERROR: SD block read failed. Error code = 0x%01x\n", T<32,2,u>; +T_5.13 ; + %set/v V_$006AFE40[0], 0, 32; +T_5.14 ; + %load/v 32, V_$006AFE40[0], 32; + %mov 64, 1, 9; + %mov 73, 0, 23; + %cmp/s 32, 64, 32; + %or 5, 4, 1; + %jmp/0xz T_5.15, 5; + %set V_$0067E2E8[0], 1; + %set V_$0067E2E8[1], 0; + %set/v V_$0067E2E8[2], 0, 30; + %set/v V_$0067C5F0[0], 0, 5; + %set V_$0067C5F0[5], 1; + %set/v V_$0067C5F0[6], 0, 2; + %load/v 32, V_$006AFD38[0], 8; + %set/v V_$0067D930[0], 32, 8; + %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78; + %join; + %load/v 32, V_$006AFD38[0], 8; + %addi 32, 1, 8; + %set/v V_$006AFD38[0], 32, 8; + %load/v 32, V_$006AFE40[0], 32; + %addi 32, 1, 32; + %set/v V_$006AFE40[0], 32, 32; + %jmp T_5.14; +T_5.15 ; + %vpi_call "$write", "Finished all tests\n"; + %vpi_call "$stop"; + %end; + .thread T_5; + .scope S_006DD638; +T_6 ; + %wait E_006DDE28; + %assign V_$006DE140[0], 0, 0; + %assign V_$006DE9B8[0], 0, 0; + %assign V_$006DEA20[0], 0, 0; + %load 32, V_$006DE0A8[0]; + %load 33, V_$006DE0A8[1]; + %load 34, V_$006DE0A8[2]; + %load 35, V_$006DE0A8[3]; + %load 36, V_$006DE0A8[4]; + %load 37, V_$006DE0A8[5]; + %load 38, V_$006DE0A8[6]; + %load 39, V_$006DE0A8[7]; + %mov 40, 0, 4; + %mov 44, 1, 4; + %and 32, 40, 8; + %cmpi/u 32, 0, 8; + %jmp/1 T_6.0, 6; + %cmpi/u 32, 16, 8; + %jmp/1 T_6.1, 6; + %cmpi/u 32, 32, 8; + %jmp/1 T_6.2, 6; + %ix/load 0, 8; + %assign/v0 V_$006DE8E8[0], 0, 0; + %jmp T_6.4; +T_6.0 ; + %assign V_$006DE140[0], 0, 1; + %load 32, V_$006DE178[0]; + %load 33, V_$006DE178[1]; + %load 34, V_$006DE178[2]; + %load 35, V_$006DE178[3]; + %load 36, V_$006DE178[4]; + %load 37, V_$006DE178[5]; + %load 38, V_$006DE178[6]; + %load 39, V_$006DE178[7]; + %ix/load 0, 8; + %assign/v0 V_$006DE8E8[0], 0, 32; + %jmp T_6.4; +T_6.1 ; + %assign V_$006DE9B8[0], 0, 1; + %load 32, V_$006DE280[0]; + %load 33, V_$006DE280[1]; + %load 34, V_$006DE280[2]; + %load 35, V_$006DE280[3]; + %load 36, V_$006DE280[4]; + %load 37, V_$006DE280[5]; + %load 38, V_$006DE280[6]; + %load 39, V_$006DE280[7]; + %ix/load 0, 8; + %assign/v0 V_$006DE8E8[0], 0, 32; + %jmp T_6.4; +T_6.2 ; + %assign V_$006DEA20[0], 0, 1; + %load 32, V_$006DE3A0[0]; + %load 33, V_$006DE3A0[1]; + %load 34, V_$006DE3A0[2]; + %load 35, V_$006DE3A0[3]; + %load 36, V_$006DE3A0[4]; + %load 37, V_$006DE3A0[5]; + %load 38, V_$006DE3A0[6]; + %load 39, V_$006DE3A0[7]; + %ix/load 0, 8; + %assign/v0 V_$006DE8E8[0], 0, 32; + %jmp T_6.4; +T_6.4 ; + %jmp T_6; + .thread T_6, $push; + .scope S_006DD638; +T_7 ; + %wait E_003DE0F8; + %load 32, V_$006DE920[0]; + %assign V_$006DDE60[0], 0, 32; + %jmp T_7; + .thread T_7; + .scope S_006DD638; +T_8 ; + %wait E_006DDDF8; + %load 32, V_$006DE920[0]; + %assign V_$006DDEE0[0], 0, 32; + %jmp T_8; + .thread T_8, $push; + .scope S_006DD638; +T_9 ; + %wait E_006DDDA0; + %load 32, V_$006DEA88[0]; + %cmpi/u 32, 0, 1; + %mov 32, 4, 1; + %load 33, V_$006DE0A8[0]; + %load 34, V_$006DE0A8[1]; + %load 35, V_$006DE0A8[2]; + %load 36, V_$006DE0A8[3]; + %load 37, V_$006DE0A8[4]; + %load 38, V_$006DE0A8[5]; + %load 39, V_$006DE0A8[6]; + %load 40, V_$006DE0A8[7]; + %cmpi/u 33, 16, 8; + %mov 33, 4, 1; + %load 34, V_$006DE0A8[0]; + %load 35, V_$006DE0A8[1]; + %load 36, V_$006DE0A8[2]; + %load 37, V_$006DE0A8[3]; + %load 38, V_$006DE0A8[4]; + %load 39, V_$006DE0A8[5]; + %load 40, V_$006DE0A8[6]; + %load 41, V_$006DE0A8[7]; + %cmpi/u 34, 32, 8; + %mov 34, 4, 1; + %or 33, 34, 1; + %and 32, 33, 1; + %jmp/0xz T_9.0, 32; + %load/v 32, V_$006DDE60[0], 1; + %assign V_$006DE038[0], 0, 32; + %jmp T_9.1; +T_9.0 ; + %load/v 32, V_$006DDEE0[0], 1; + %assign V_$006DE038[0], 0, 32; +T_9.1 ; + %jmp T_9; + .thread T_9, $push; + .scope S_006DBE08; +T_10 ; + %wait E_003DE0F8; + %load/v 32, V_$006DC940[0], 1; + %jmp/0xz T_10.0, 32; + %assign V_$006DDC18[0], 0, 0; + %assign V_$006DDC18[1], 0, 0; + %assign V_$006DD6A8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006DD380[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006DCA38[0], 0, 0; + %jmp T_10.1; +T_10.0 ; + %load 32, V_$006DDD18[0]; + %load 33, V_$006DC5B0[0]; + %and 32, 33, 1; + %load 33, V_$006DDCE0[0]; + %and 32, 33, 1; + %load 33, V_$006DCEF8[0]; + %load 34, V_$006DCEF8[1]; + %load 35, V_$006DCEF8[2]; + %load 36, V_$006DCEF8[3]; + %load 37, V_$006DCEF8[4]; + %load 38, V_$006DCEF8[5]; + %load 39, V_$006DCEF8[6]; + %load 40, V_$006DCEF8[7]; + %cmpi/u 33, 1, 8; + %mov 33, 4, 1; + %and 32, 33, 1; + %load 33, V_$006DC5E8[1]; + %and 32, 33, 1; + %jmp/0xz T_10.2, 32; + %assign V_$006DC6B8[0], 0, 1; + %jmp T_10.3; +T_10.2 ; + %assign V_$006DC6B8[0], 0, 0; +T_10.3 ; + %load 32, V_$006DDD18[0]; + %load 33, V_$006DC5B0[0]; + %and 32, 33, 1; + %load 33, V_$006DDCE0[0]; + %and 32, 33, 1; + %load 33, V_$006DCEF8[0]; + %load 34, V_$006DCEF8[1]; + %load 35, V_$006DCEF8[2]; + %load 36, V_$006DCEF8[3]; + %load 37, V_$006DCEF8[4]; + %load 38, V_$006DCEF8[5]; + %load 39, V_$006DCEF8[6]; + %load 40, V_$006DCEF8[7]; + %cmpi/u 33, 3, 8; + %mov 33, 4, 1; + %and 32, 33, 1; + %load 33, V_$006DC5E8[0]; + %and 32, 33, 1; + %jmp/0xz T_10.4, 32; + %assign V_$006DD6A8[0], 0, 1; + %jmp T_10.5; +T_10.4 ; + %assign V_$006DD6A8[0], 0, 0; +T_10.5 ; + %load 32, V_$006DDD18[0]; + %load 33, V_$006DC5B0[0]; + %and 32, 33, 1; + %load 33, V_$006DDCE0[0]; + %and 32, 33, 1; + %jmp/0xz T_10.6, 32; + %load 32, V_$006DCEF8[0]; + %load 33, V_$006DCEF8[1]; + %load 34, V_$006DCEF8[2]; + %load 35, V_$006DCEF8[3]; + %load 36, V_$006DCEF8[4]; + %load 37, V_$006DCEF8[5]; + %load 38, V_$006DCEF8[6]; + %load 39, V_$006DCEF8[7]; + %cmpi/u 32, 2, 8; + %jmp/1 T_10.8, 6; + %cmpi/u 32, 7, 8; + %jmp/1 T_10.9, 6; + %cmpi/u 32, 8, 8; + %jmp/1 T_10.10, 6; + %cmpi/u 32, 9, 8; + %jmp/1 T_10.11, 6; + %cmpi/u 32, 10, 8; + %jmp/1 T_10.12, 6; + %cmpi/u 32, 11, 8; + %jmp/1 T_10.13, 6; + %cmpi/u 32, 6, 8; + %jmp/1 T_10.14, 6; + %jmp T_10.15; +T_10.8 ; + %load 32, V_$006DC5E8[0]; + %load 33, V_$006DC5E8[1]; + %assign V_$006DDC18[0], 0, 32; + %assign V_$006DDC18[1], 0, 33; + %jmp T_10.15; +T_10.9 ; + %load 32, V_$006DC5E8[0]; + %load 33, V_$006DC5E8[1]; + %load 34, V_$006DC5E8[2]; + %load 35, V_$006DC5E8[3]; + %load 36, V_$006DC5E8[4]; + %load 37, V_$006DC5E8[5]; + %load 38, V_$006DC5E8[6]; + %load 39, V_$006DC5E8[7]; + %ix/load 0, 8; + %assign/v0 V_$006DBED8[0], 0, 32; + %jmp T_10.15; +T_10.10 ; + %load 32, V_$006DC5E8[0]; + %load 33, V_$006DC5E8[1]; + %load 34, V_$006DC5E8[2]; + %load 35, V_$006DC5E8[3]; + %load 36, V_$006DC5E8[4]; + %load 37, V_$006DC5E8[5]; + %load 38, V_$006DC5E8[6]; + %load 39, V_$006DC5E8[7]; + %ix/load 0, 8; + %assign/v0 V_$006DBED8[8], 0, 32; + %jmp T_10.15; +T_10.11 ; + %load 32, V_$006DC5E8[0]; + %load 33, V_$006DC5E8[1]; + %load 34, V_$006DC5E8[2]; + %load 35, V_$006DC5E8[3]; + %load 36, V_$006DC5E8[4]; + %load 37, V_$006DC5E8[5]; + %load 38, V_$006DC5E8[6]; + %load 39, V_$006DC5E8[7]; + %ix/load 0, 8; + %assign/v0 V_$006DBED8[16], 0, 32; + %jmp T_10.15; +T_10.12 ; + %load 32, V_$006DC5E8[0]; + %load 33, V_$006DC5E8[1]; + %load 34, V_$006DC5E8[2]; + %load 35, V_$006DC5E8[3]; + %load 36, V_$006DC5E8[4]; + %load 37, V_$006DC5E8[5]; + %load 38, V_$006DC5E8[6]; + %load 39, V_$006DC5E8[7]; + %ix/load 0, 8; + %assign/v0 V_$006DBED8[24], 0, 32; + %jmp T_10.15; +T_10.13 ; + %load 32, V_$006DC5E8[0]; + %load 33, V_$006DC5E8[1]; + %load 34, V_$006DC5E8[2]; + %load 35, V_$006DC5E8[3]; + %load 36, V_$006DC5E8[4]; + %load 37, V_$006DC5E8[5]; + %load 38, V_$006DC5E8[6]; + %load 39, V_$006DC5E8[7]; + %ix/load 0, 8; + %assign/v0 V_$006DCA38[0], 0, 32; + %jmp T_10.15; +T_10.14 ; + %load 32, V_$006DC5E8[0]; + %load 33, V_$006DC5E8[1]; + %load 34, V_$006DC5E8[2]; + %load 35, V_$006DC5E8[3]; + %load 36, V_$006DC5E8[4]; + %load 37, V_$006DC5E8[5]; + %load 38, V_$006DC5E8[6]; + %load 39, V_$006DC5E8[7]; + %ix/load 0, 8; + %assign/v0 V_$006DD380[0], 0, 32; + %jmp T_10.15; +T_10.15 ; +T_10.6 ; +T_10.1 ; + %jmp T_10; + .thread T_10; + .scope S_006DBE08; +T_11 ; + %wait E_006DBEB8; + %load 32, V_$006DCEF8[0]; + %load 33, V_$006DCEF8[1]; + %load 34, V_$006DCEF8[2]; + %load 35, V_$006DCEF8[3]; + %load 36, V_$006DCEF8[4]; + %load 37, V_$006DCEF8[5]; + %load 38, V_$006DCEF8[6]; + %load 39, V_$006DCEF8[7]; + %cmpi/u 32, 0, 8; + %jmp/1 T_11.0, 6; + %cmpi/u 32, 2, 8; + %jmp/1 T_11.1, 6; + %cmpi/u 32, 3, 8; + %jmp/1 T_11.2, 6; + %cmpi/u 32, 4, 8; + %jmp/1 T_11.3, 6; + %cmpi/u 32, 5, 8; + %jmp/1 T_11.4, 6; + %cmpi/u 32, 7, 8; + %jmp/1 T_11.5, 6; + %cmpi/u 32, 8, 8; + %jmp/1 T_11.6, 6; + %cmpi/u 32, 9, 8; + %jmp/1 T_11.7, 6; + %cmpi/u 32, 10, 8; + %jmp/1 T_11.8, 6; + %cmpi/u 32, 11, 8; + %jmp/1 T_11.9, 6; + %cmpi/u 32, 6, 8; + %jmp/1 T_11.10, 6; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 0; + %jmp T_11.12; +T_11.0 ; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 0; + %jmp T_11.12; +T_11.1 ; + %load/v 32, V_$006DDC18[0], 2; + %mov 34, 0, 6; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.2 ; + %load/v 32, V_$006DD6A8[0], 1; + %mov 33, 0, 7; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.3 ; + %load/v 32, V_$006DDAA8[0], 1; + %mov 33, 0, 7; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.4 ; + %load/v 32, V_$006DC440[0], 2; + %load/v 34, V_$006DC4D0[0], 2; + %load/v 36, V_$006DCE80[0], 2; + %mov 38, 0, 2; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.5 ; + %load/v 32, V_$006DBED8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.6 ; + %load/v 32, V_$006DBED8[8], 8; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.7 ; + %load/v 32, V_$006DBED8[16], 8; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.8 ; + %load/v 32, V_$006DBED8[24], 8; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.9 ; + %load/v 32, V_$006DCA38[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.10 ; + %load/v 32, V_$006DD078[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006DC658[0], 0, 32; + %jmp T_11.12; +T_11.12 ; + %jmp T_11; + .thread T_11, $push; + .scope S_006DBE08; +T_12 ; + %wait E_003DE0F8; + %load 32, V_$006DC620[0]; + %load/v 33, V_$006DC6B8[0], 1; + %or 32, 33, 1; + %jmp/0xz T_12.0, 32; + %ix/load 0, 6; + %assign/v0 V_$006DC710[0], 0, 1; + %jmp T_12.1; +T_12.0 ; + %load/v 32, V_$006DC710[1], 5; + %mov 37, 0, 1; + %ix/load 0, 6; + %assign/v0 V_$006DC710[0], 0, 32; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_006DBE08; +T_13 ; + %wait E_006DBE78; + %load/v 32, V_$006DC710[0], 1; + %assign V_$006DC940[0], 0, 32; + %jmp T_13; + .thread T_13, $push; + .scope S_006DBE08; +T_14 ; + %wait E_003DE478; + %load/v 32, V_$006DC940[0], 1; + %assign V_$006DC978[0], 0, 32; + %load/v 32, V_$006DC978[0], 1; + %assign V_$006DCA00[0], 0, 32; + %jmp T_14; + .thread T_14; + .scope S_006DBE08; +T_15 ; + %wait E_003DE0F8; + %load/v 32, V_$006DC940[0], 1; + %jmp/0xz T_15.0, 32; + %ix/load 0, 6; + %assign/v0 V_$006DD6E0[0], 0, 0; + %jmp T_15.1; +T_15.0 ; + %load/v 32, V_$006DD6A8[0], 1; + %jmp/0xz T_15.2, 32; + %ix/load 0, 6; + %assign/v0 V_$006DD6E0[0], 0, 1; + %jmp T_15.3; +T_15.2 ; + %load/v 32, V_$006DD6E0[1], 5; + %mov 37, 0, 1; + %ix/load 0, 6; + %assign/v0 V_$006DD6E0[0], 0, 32; +T_15.3 ; +T_15.1 ; + %jmp T_15; + .thread T_15; + .scope S_006DBE08; +T_16 ; + %wait E_003DE478; + %load/v 32, V_$006DD6E0[0], 1; + %assign V_$006DDF80[0], 0, 32; + %jmp T_16; + .thread T_16; + .scope S_006DBE08; +T_17 ; + %wait E_003DE478; + %load/v 32, V_$006DCA00[0], 1; + %jmp/0xz T_17.0, 32; + %assign V_$006DDBA0[0], 0, 0; + %assign V_$006DDBA0[1], 0, 0; + %assign V_$006DDF80[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006DD220[0], 0, 0; + %jmp T_17.1; +T_17.0 ; + %load/v 32, V_$006DD380[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006DD220[0], 0, 32; + %load/v 32, V_$006DDC18[0], 2; + %assign V_$006DDBA0[0], 0, 32; + %assign V_$006DDBA0[1], 0, 33; + %load/v 32, V_$006DD380[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006DD220[0], 0, 32; +T_17.1 ; + %jmp T_17; + .thread T_17; + .scope S_006DBE08; +T_18 ; + %wait E_003DE0F8; + %load/v 32, V_$006DC940[0], 1; + %jmp/0xz T_18.0, 32; + %assign V_$006DDAA8[0], 0, 0; + %assign V_$006DD970[0], 0, 0; + %assign V_$006DD9E0[0], 0, 0; + %jmp T_18.1; +T_18.0 ; + %load 32, V_$006DD918[0]; + %assign V_$006DD970[0], 0, 32; + %load/v 32, V_$006DD970[0], 1; + %assign V_$006DD9E0[0], 0, 32; + %load/v 32, V_$006DD6A8[0], 1; + %jmp/0xz T_18.2, 32; + %assign V_$006DDAA8[0], 0, 1; + %jmp T_18.3; +T_18.2 ; + %load/v 32, V_$006DD9E0[0], 1; + %load/v 33, V_$006DD970[0], 1; + %cmpi/u 33, 0, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_18.4, 32; + %assign V_$006DDAA8[0], 0, 0; +T_18.4 ; +T_18.3 ; +T_18.1 ; + %load 32, V_$006DCBF0[0]; + %load 33, V_$006DCBF0[1]; + %load 34, V_$006DCBF0[2]; + %load 35, V_$006DCBF0[3]; + %load 36, V_$006DCBF0[4]; + %load 37, V_$006DCBF0[5]; + %load 38, V_$006DCBF0[6]; + %load 39, V_$006DCBF0[7]; + %ix/load 0, 8; + %assign/v0 V_$006DD078[0], 0, 32; + %load 32, V_$006DCE08[0]; + %load 33, V_$006DCE08[1]; + %assign V_$006DCE80[0], 0, 32; + %assign V_$006DCE80[1], 0, 33; + %load 32, V_$006DC478[0]; + %load 33, V_$006DC478[1]; + %assign V_$006DC4D0[0], 0, 32; + %assign V_$006DC4D0[1], 0, 33; + %load 32, V_$006DC3C8[0]; + %load 33, V_$006DC3C8[1]; + %assign V_$006DC440[0], 0, 32; + %assign V_$006DC440[1], 0, 33; + %jmp T_18; + .thread T_18; + .scope S_006DA008; +T_19 ; + %wait E_006DB510; + %load/v 32, V_$006DB530[0], 3; + %ix/load 0, 3; + %assign/v0 V_$006DB5C8[0], 0, 32; + %load/v 32, V_$006DBA28[0], 2; + %assign V_$006DB760[0], 0, 32; + %assign V_$006DB760[1], 0, 33; + %load/v 32, V_$006DBDB0[0], 1; + %assign V_$006DB918[0], 0, 32; + %load/v 32, V_$006DB678[0], 1; + %assign V_$006DB728[0], 0, 32; + %load/v 32, V_$006DAC70[0], 1; + %assign V_$006DB7C0[0], 0, 32; + %load/v 32, V_$006DBC48[0], 1; + %assign V_$006DB890[0], 0, 32; + %load/v 32, V_$006DBBB8[0], 1; + %assign V_$006DB810[0], 0, 32; + %load/v 32, V_$006DB530[0], 3; + %cmpi/u 32, 0, 3; + %jmp/1 T_19.0, 6; + %cmpi/u 32, 1, 3; + %jmp/1 T_19.1, 6; + %cmpi/u 32, 2, 3; + %jmp/1 T_19.2, 6; + %cmpi/u 32, 3, 3; + %jmp/1 T_19.3, 6; + %cmpi/u 32, 4, 3; + %jmp/1 T_19.4, 6; + %cmpi/u 32, 5, 3; + %jmp/1 T_19.5, 6; + %cmpi/u 32, 6, 3; + %jmp/1 T_19.6, 6; + %cmpi/u 32, 7, 3; + %jmp/1 T_19.7, 6; + %jmp T_19.8; +T_19.0 ; + %assign V_$006DB760[0], 0, 0; + %assign V_$006DB760[1], 0, 0; + %assign V_$006DB918[0], 0, 0; + %assign V_$006DB728[0], 0, 0; + %assign V_$006DB7C0[0], 0, 0; + %assign V_$006DB890[0], 0, 0; + %assign V_$006DB810[0], 0, 1; + %assign V_$006DB5C8[0], 0, 1; + %assign V_$006DB5C8[1], 0, 0; + %assign V_$006DB5C8[2], 0, 0; + %jmp T_19.8; +T_19.1 ; + %assign V_$006DB7C0[0], 0, 0; + %assign V_$006DB890[0], 0, 0; + %load 32, V_$006DBC10[0]; + %load 33, V_$006DBCC8[0]; + %load 34, V_$006DBCC8[1]; + %cmpi/u 33, 1, 2; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_19.9, 32; + %assign V_$006DB5C8[0], 0, 0; + %assign V_$006DB5C8[1], 0, 0; + %assign V_$006DB5C8[2], 0, 1; + %assign V_$006DB890[0], 0, 1; + %assign V_$006DB728[0], 0, 1; + %jmp T_19.10; +T_19.9 ; + %load 32, V_$006DBC10[0]; + %load 33, V_$006DBCC8[0]; + %load 34, V_$006DBCC8[1]; + %cmpi/u 33, 3, 2; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_19.11, 32; + %assign V_$006DB5C8[0], 0, 0; + %assign V_$006DB5C8[1], 0, 1; + %assign V_$006DB5C8[2], 0, 1; + %assign V_$006DB890[0], 0, 1; + %assign V_$006DB760[0], 0, 1; + %assign V_$006DB760[1], 0, 0; + %jmp T_19.12; +T_19.11 ; + %load 32, V_$006DBC10[0]; + %load 33, V_$006DBCC8[0]; + %load 34, V_$006DBCC8[1]; + %cmpi/u 33, 2, 2; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_19.13, 32; + %assign V_$006DB5C8[0], 0, 0; + %assign V_$006DB5C8[1], 0, 1; + %assign V_$006DB5C8[2], 0, 1; + %assign V_$006DB890[0], 0, 1; + %assign V_$006DB760[0], 0, 0; + %assign V_$006DB760[1], 0, 1; + %jmp T_19.14; +T_19.13 ; + %load 32, V_$006DBC10[0]; + %load 33, V_$006DBCC8[0]; + %load 34, V_$006DBCC8[1]; + %cmpi/u 33, 0, 2; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_19.15, 32; + %assign V_$006DB5C8[0], 0, 1; + %assign V_$006DB5C8[1], 0, 1; + %assign V_$006DB5C8[2], 0, 0; + %assign V_$006DB890[0], 0, 1; + %assign V_$006DB918[0], 0, 1; + %assign V_$006DB810[0], 0, 0; +T_19.15 ; +T_19.14 ; +T_19.12 ; +T_19.10 ; + %jmp T_19.8; +T_19.2 ; + %load 32, V_$006DBB18[0]; + %jmp/0xz T_19.17, 32; + %assign V_$006DB5C8[0], 0, 1; + %assign V_$006DB5C8[1], 0, 0; + %assign V_$006DB5C8[2], 0, 0; + %assign V_$006DB7C0[0], 0, 1; + %assign V_$006DB810[0], 0, 1; +T_19.17 ; + %jmp T_19.8; +T_19.3 ; + %assign V_$006DB918[0], 0, 0; + %assign V_$006DB5C8[0], 0, 0; + %assign V_$006DB5C8[1], 0, 1; + %assign V_$006DB5C8[2], 0, 0; + %jmp T_19.8; +T_19.4 ; + %assign V_$006DB728[0], 0, 0; + %assign V_$006DB5C8[0], 0, 1; + %assign V_$006DB5C8[1], 0, 0; + %assign V_$006DB5C8[2], 0, 1; + %jmp T_19.8; +T_19.5 ; + %load 32, V_$006DB620[0]; + %jmp/0xz T_19.19, 32; + %assign V_$006DB5C8[0], 0, 1; + %assign V_$006DB5C8[1], 0, 0; + %assign V_$006DB5C8[2], 0, 0; +T_19.19 ; + %jmp T_19.8; +T_19.6 ; + %assign V_$006DB760[0], 0, 0; + %assign V_$006DB760[1], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006DB5C8[0], 0, 1; + %jmp T_19.8; +T_19.7 ; + %load 32, V_$006DB9D0[0]; + %jmp/0xz T_19.21, 32; + %assign V_$006DB5C8[0], 0, 1; + %assign V_$006DB5C8[1], 0, 0; + %assign V_$006DB5C8[2], 0, 0; +T_19.21 ; + %jmp T_19.8; +T_19.8 ; + %jmp T_19; + .thread T_19, $push; + .scope S_006DA008; +T_20 ; + %wait E_003DE478; + %load 32, V_$006DB950[0]; + %jmp/0xz T_20.0, 32; + %ix/load 0, 3; + %assign/v0 V_$006DB530[0], 0, 0; + %jmp T_20.1; +T_20.0 ; + %load/v 32, V_$006DB5C8[0], 3; + %ix/load 0, 3; + %assign/v0 V_$006DB530[0], 0, 32; +T_20.1 ; + %jmp T_20; + .thread T_20; + .scope S_006DA008; +T_21 ; + %wait E_003DE478; + %load 32, V_$006DB950[0]; + %jmp/0xz T_21.0, 32; + %assign V_$006DBA28[0], 0, 0; + %assign V_$006DBA28[1], 0, 0; + %assign V_$006DBDB0[0], 0, 0; + %assign V_$006DB678[0], 0, 0; + %assign V_$006DAC70[0], 0, 0; + %assign V_$006DBC48[0], 0, 0; + %assign V_$006DBBB8[0], 0, 1; + %jmp T_21.1; +T_21.0 ; + %load/v 32, V_$006DB760[0], 2; + %assign V_$006DBA28[0], 0, 32; + %assign V_$006DBA28[1], 0, 33; + %load/v 32, V_$006DB918[0], 1; + %assign V_$006DBDB0[0], 0, 32; + %load/v 32, V_$006DB728[0], 1; + %assign V_$006DB678[0], 0, 32; + %load/v 32, V_$006DB7C0[0], 1; + %assign V_$006DAC70[0], 0, 32; + %load/v 32, V_$006DB890[0], 1; + %assign V_$006DBC48[0], 0, 32; + %load/v 32, V_$006DB810[0], 1; + %assign V_$006DBBB8[0], 0, 32; +T_21.1 ; + %jmp T_21; + .thread T_21; + .scope S_006D5E10; +T_22 ; + %wait E_006C8B28; + %load/v 32, V_$006D7810[0], 4; + %ix/load 0, 4; + %assign/v0 V_$006D78C0[0], 0, 32; + %load/v 32, V_$006DB188[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006DA4D0[0], 0, 32; + %load/v 32, V_$006D7E68[0], 1; + %assign V_$006D8560[0], 0, 32; + %load/v 32, V_$006DADF8[0], 1; + %assign V_$006DA450[0], 0, 32; + %load/v 32, V_$006D8260[0], 2; + %assign V_$006D9D58[0], 0, 32; + %assign V_$006D9D58[1], 0, 33; + %load/v 32, V_$006D71D0[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006DA638[0], 0, 32; + %load/v 32, V_$006DB4B8[0], 1; + %assign V_$006DA918[0], 0, 32; + %load/v 32, V_$006D7B08[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D8900[0], 0, 32; + %load/v 32, V_$006D7C70[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D8B78[0], 0, 32; + %load/v 32, V_$006D7DD0[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D90D8[0], 0, 32; + %load/v 32, V_$006D80C8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D93B8[0], 0, 32; + %load/v 32, V_$006D8228[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D9F90[0], 0, 32; + %load/v 32, V_$006D7F80[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D85E0[0], 0, 32; + %load/v 32, V_$006DAD18[0], 1; + %assign V_$006DA3D0[0], 0, 32; + %load/v 32, V_$006D8E20[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006DA0A8[0], 0, 32; + %load/v 32, V_$006D83C0[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006D9750[0], 0, 32; + %load/v 32, V_$006D83F8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D9AB8[0], 0, 32; + %load/v 32, V_$006DACA8[0], 1; + %assign V_$006DA348[0], 0, 32; + %load/v 32, V_$006D7810[0], 4; + %cmpi/u 32, 0, 4; + %jmp/1 T_22.0, 6; + %cmpi/u 32, 1, 4; + %jmp/1 T_22.1, 6; + %cmpi/u 32, 2, 4; + %jmp/1 T_22.2, 6; + %cmpi/u 32, 3, 4; + %jmp/1 T_22.3, 6; + %cmpi/u 32, 13, 4; + %jmp/1 T_22.4, 6; + %cmpi/u 32, 4, 4; + %jmp/1 T_22.5, 6; + %cmpi/u 32, 5, 4; + %jmp/1 T_22.6, 6; + %cmpi/u 32, 6, 4; + %jmp/1 T_22.7, 6; + %cmpi/u 32, 7, 4; + %jmp/1 T_22.8, 6; + %cmpi/u 32, 8, 4; + %jmp/1 T_22.9, 6; + %cmpi/u 32, 9, 4; + %jmp/1 T_22.10, 6; + %cmpi/u 32, 10, 4; + %jmp/1 T_22.11, 6; + %cmpi/u 32, 11, 4; + %jmp/1 T_22.12, 6; + %cmpi/u 32, 12, 4; + %jmp/1 T_22.13, 6; + %jmp T_22.14; +T_22.0 ; + %load 32, V_$006DAE30[0]; + %load 33, V_$006DAE30[1]; + %load 34, V_$006DAE30[2]; + %load 35, V_$006DAE30[3]; + %load 36, V_$006DAE30[4]; + %load 37, V_$006DAE30[5]; + %load 38, V_$006DAE30[6]; + %load 39, V_$006DAE30[7]; + %ix/load 0, 8; + %assign/v0 V_$006DA4D0[0], 0, 32; + %assign V_$006D8560[0], 0, 0; + %assign V_$006DA450[0], 0, 1; + %assign V_$006D9D58[0], 0, 0; + %assign V_$006D9D58[1], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006DA638[0], 0, 0; + %assign V_$006DA918[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D8900[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D8B78[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D90D8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D93B8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D9F90[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D85E0[0], 0, 0; + %assign V_$006DA3D0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006DA0A8[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006D9750[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D9AB8[0], 0, 0; + %assign V_$006DA348[0], 0, 0; + %assign V_$006D78C0[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D78C0[1], 0, 0; + %jmp T_22.14; +T_22.1 ; + %assign V_$006D8560[0], 0, 1; + %load 32, V_$006DAE30[0]; + %load 33, V_$006DAE30[1]; + %load 34, V_$006DAE30[2]; + %load 35, V_$006DAE30[3]; + %load 36, V_$006DAE30[4]; + %load 37, V_$006DAE30[5]; + %load 38, V_$006DAE30[6]; + %load 39, V_$006DAE30[7]; + %ix/load 0, 8; + %assign/v0 V_$006DA4D0[0], 0, 32; + %load 32, V_$006D7F00[0]; + %jmp/0xz T_22.15, 32; + %assign V_$006D78C0[0], 0, 0; + %assign V_$006D78C0[1], 0, 1; + %assign V_$006D78C0[2], 0, 0; + %assign V_$006D78C0[3], 0, 0; + %assign V_$006D8560[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006DA0A8[0], 0, 0; + %assign V_$006DA4D0[0], 0, 1; + %assign V_$006DA4D0[1], 0, 1; + %assign V_$006DA4D0[2], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006DA4D0[3], 0, 1; + %assign V_$006DA4D0[6], 0, 0; + %assign V_$006DA4D0[7], 0, 0; + %assign V_$006D9D58[0], 0, 0; + %assign V_$006D9D58[1], 0, 0; +T_22.15 ; + %jmp T_22.14; +T_22.2 ; + %load 32, V_$006DB358[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_22.17, 4; + %assign V_$006D78C0[0], 0, 1; + %assign V_$006D78C0[1], 0, 1; + %assign V_$006D78C0[2], 0, 0; + %assign V_$006D78C0[3], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006DA638[0], 0, 1; + %assign V_$006DA918[0], 0, 1; + %load/v 32, V_$006D8E20[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006DA0A8[0], 0, 32; +T_22.17 ; + %jmp T_22.14; +T_22.3 ; + %assign V_$006DA918[0], 0, 0; + %load/v 32, V_$006D8E20[0], 8; + %cmpi/u 32, 160, 8; + %jmp/0xz T_22.19, 4; + %assign V_$006D78C0[0], 0, 1; + %assign V_$006D78C0[1], 0, 0; + %assign V_$006D78C0[2], 0, 1; + %assign V_$006D78C0[3], 0, 1; + %jmp T_22.20; +T_22.19 ; + %assign V_$006D78C0[0], 0, 0; + %assign V_$006D78C0[1], 0, 1; + %assign V_$006D78C0[2], 0, 0; + %assign V_$006D78C0[3], 0, 0; +T_22.20 ; + %jmp T_22.14; +T_22.4 ; + %load 32, V_$006DB2E8[0]; + %jmp/0xz T_22.21, 32; + %assign V_$006D78C0[0], 0, 0; + %assign V_$006D78C0[1], 0, 0; + %assign V_$006D78C0[2], 0, 1; + %assign V_$006D78C0[3], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006DA0A8[0], 0, 0; +T_22.21 ; + %jmp T_22.14; +T_22.5 ; + %ix/load 0, 6; + %assign/v0 V_$006D8900[0], 0, 0; + %assign V_$006D8900[6], 0, 1; + %assign V_$006D8900[7], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D8B78[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D90D8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D93B8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D9F90[0], 0, 0; + %assign V_$006D85E0[0], 0, 1; + %assign V_$006D85E0[1], 0, 0; + %assign V_$006D85E0[2], 0, 1; + %assign V_$006D85E0[3], 0, 0; + %assign V_$006D85E0[4], 0, 1; + %assign V_$006D85E0[5], 0, 0; + %assign V_$006D85E0[6], 0, 0; + %assign V_$006D85E0[7], 0, 1; + %assign V_$006DA3D0[0], 0, 1; + %load/v 32, V_$006D8E20[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006DA0A8[0], 0, 32; + %assign V_$006DA450[0], 0, 0; + %assign V_$006D78C0[0], 0, 1; + %assign V_$006D78C0[1], 0, 0; + %assign V_$006D78C0[2], 0, 1; + %assign V_$006D78C0[3], 0, 0; + %jmp T_22.14; +T_22.6 ; + %assign V_$006DA3D0[0], 0, 0; + %assign V_$006D78C0[0], 0, 0; + %assign V_$006D78C0[1], 0, 1; + %assign V_$006D78C0[2], 0, 1; + %assign V_$006D78C0[3], 0, 0; + %jmp T_22.14; +T_22.7 ; + %load 32, V_$006DACE0[0]; + %jmp/0xz T_22.23, 32; + %ix/load 0, 3; + %assign/v0 V_$006D78C0[0], 0, 1; + %assign V_$006D78C0[3], 0, 0; + %assign V_$006DA450[0], 0, 1; +T_22.23 ; + %jmp T_22.14; +T_22.8 ; + %load 32, V_$006DAB98[0]; + %load 33, V_$006DA998[0]; + %load 34, V_$006DA998[1]; + %load 35, V_$006DA998[2]; + %load 36, V_$006DA998[3]; + %load 37, V_$006DA998[4]; + %load 38, V_$006DA998[5]; + %load 39, V_$006DA998[6]; + %load 40, V_$006DA998[7]; + %cmpi/u 33, 1, 8; + %inv 4, 1; + %mov 33, 4, 1; + %or 32, 33, 1; + %load/v 33, V_$006D8E20[0], 8; + %cmpi/u 33, 255, 8; + %inv 4, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_22.25, 32; + %assign V_$006D78C0[0], 0, 0; + %assign V_$006D78C0[1], 0, 0; + %assign V_$006D78C0[2], 0, 1; + %assign V_$006D78C0[3], 0, 0; + %jmp T_22.26; +T_22.25 ; + %load 32, V_$006DAB98[0]; + %load 33, V_$006DA998[0]; + %load 34, V_$006DA998[1]; + %load 35, V_$006DA998[2]; + %load 36, V_$006DA998[3]; + %load 37, V_$006DA998[4]; + %load 38, V_$006DA998[5]; + %load 39, V_$006DA998[6]; + %load 40, V_$006DA998[7]; + %cmpi/u 33, 1, 8; + %inv 4, 1; + %mov 33, 4, 1; + %or 32, 33, 1; + %jmp/0xz T_22.27, 32; + %assign V_$006D78C0[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D78C0[1], 0, 0; + %assign V_$006D9D58[0], 0, 1; + %assign V_$006D9D58[1], 0, 0; + %jmp T_22.28; +T_22.27 ; + %assign V_$006D78C0[0], 0, 0; + %assign V_$006D78C0[1], 0, 1; + %assign V_$006D78C0[2], 0, 0; + %assign V_$006D78C0[3], 0, 1; +T_22.28 ; +T_22.26 ; + %jmp T_22.14; +T_22.9 ; + %load 32, V_$006DACE0[0]; + %jmp/0xz T_22.29, 32; + %assign V_$006D78C0[0], 0, 1; + %assign V_$006D78C0[1], 0, 0; + %assign V_$006D78C0[2], 0, 0; + %assign V_$006D78C0[3], 0, 1; + %assign V_$006DA450[0], 0, 1; +T_22.29 ; + %jmp T_22.14; +T_22.10 ; + %load 32, V_$006DAB98[0]; + %load 33, V_$006DA998[0]; + %load 34, V_$006DA998[1]; + %load 35, V_$006DA998[2]; + %load 36, V_$006DA998[3]; + %load 37, V_$006DA998[4]; + %load 38, V_$006DA998[5]; + %load 39, V_$006DA998[6]; + %load 40, V_$006DA998[7]; + %cmpi/u 33, 0, 8; + %inv 4, 1; + %mov 33, 4, 1; + %or 32, 33, 1; + %load/v 33, V_$006D8E20[0], 8; + %cmpi/u 33, 255, 8; + %inv 4, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_22.31, 32; + %assign V_$006D78C0[0], 0, 0; + %assign V_$006D78C0[1], 0, 1; + %assign V_$006D78C0[2], 0, 0; + %assign V_$006D78C0[3], 0, 1; + %jmp T_22.32; +T_22.31 ; + %load 32, V_$006DAB98[0]; + %load 33, V_$006DA998[0]; + %load 34, V_$006DA998[1]; + %load 35, V_$006DA998[2]; + %load 36, V_$006DA998[3]; + %load 37, V_$006DA998[4]; + %load 38, V_$006DA998[5]; + %load 39, V_$006DA998[6]; + %load 40, V_$006DA998[7]; + %cmpi/u 33, 0, 8; + %inv 4, 1; + %mov 33, 4, 1; + %or 32, 33, 1; + %jmp/0xz T_22.33, 32; + %assign V_$006D78C0[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D78C0[1], 0, 0; + %assign V_$006D9D58[0], 0, 0; + %assign V_$006D9D58[1], 0, 1; + %jmp T_22.34; +T_22.33 ; + %assign V_$006D78C0[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D78C0[1], 0, 0; +T_22.34 ; +T_22.32 ; + %jmp T_22.14; +T_22.11 ; + %assign V_$006D8900[0], 0, 1; + %ix/load 0, 5; + %assign/v0 V_$006D8900[1], 0, 0; + %assign V_$006D8900[6], 0, 1; + %assign V_$006D8900[7], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D8B78[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D90D8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D93B8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D9F90[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D85E0[0], 0, 1; + %assign V_$006DA3D0[0], 0, 1; + %load/v 32, V_$006D8E20[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006DA0A8[0], 0, 32; + %assign V_$006DA450[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006D9750[0], 0, 0; + %assign V_$006D78C0[0], 0, 1; + %assign V_$006D78C0[1], 0, 1; + %assign V_$006D78C0[2], 0, 0; + %assign V_$006D78C0[3], 0, 1; + %jmp T_22.14; +T_22.12 ; + %load/v 32, V_$006D83C0[0], 10; + %addi 32, 1, 10; + %ix/load 0, 10; + %assign/v0 V_$006D9750[0], 0, 32; + %ix/load 0, 8; + %assign/v0 V_$006D9AB8[0], 0, 0; + %assign V_$006DA3D0[0], 0, 0; + %load/v 32, V_$006D83C0[0], 10; + %cmpi/u 32, 375, 10; + %jmp/0xz T_22.35, 4; + %ix/load 0, 3; + %assign/v0 V_$006D78C0[0], 0, 0; + %assign V_$006D78C0[3], 0, 1; + %jmp T_22.36; +T_22.35 ; + %assign V_$006D78C0[0], 0, 0; + %assign V_$006D78C0[1], 0, 0; + %assign V_$006D78C0[2], 0, 1; + %assign V_$006D78C0[3], 0, 1; +T_22.36 ; + %jmp T_22.14; +T_22.13 ; + %load/v 32, V_$006D83F8[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006D9AB8[0], 0, 32; + %load/v 32, V_$006D83F8[0], 8; + %cmpi/u 32, 255, 8; + %jmp/0xz T_22.37, 4; + %assign V_$006D78C0[0], 0, 1; + %assign V_$006D78C0[1], 0, 1; + %assign V_$006D78C0[2], 0, 0; + %assign V_$006D78C0[3], 0, 1; +T_22.37 ; + %jmp T_22.14; +T_22.14 ; + %jmp T_22; + .thread T_22, $push; + .scope S_006D5E10; +T_23 ; + %wait E_003DE478; + %load 32, V_$006DAC00[0]; + %jmp/0xz T_23.0, 32; + %ix/load 0, 4; + %assign/v0 V_$006D7810[0], 0, 0; + %jmp T_23.1; +T_23.0 ; + %load/v 32, V_$006D78C0[0], 4; + %ix/load 0, 4; + %assign/v0 V_$006D7810[0], 0, 32; +T_23.1 ; + %jmp T_23; + .thread T_23; + .scope S_006D5E10; +T_24 ; + %wait E_003DE478; + %load 32, V_$006DAC00[0]; + %jmp/0xz T_24.0, 32; + %load 32, V_$006DAE30[0]; + %load 33, V_$006DAE30[1]; + %load 34, V_$006DAE30[2]; + %load 35, V_$006DAE30[3]; + %load 36, V_$006DAE30[4]; + %load 37, V_$006DAE30[5]; + %load 38, V_$006DAE30[6]; + %load 39, V_$006DAE30[7]; + %ix/load 0, 8; + %assign/v0 V_$006DB188[0], 0, 32; + %assign V_$006D7E68[0], 0, 0; + %assign V_$006DADF8[0], 0, 1; + %assign V_$006D8260[0], 0, 0; + %assign V_$006D8260[1], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D71D0[0], 0, 0; + %assign V_$006DB4B8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D7B08[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D7C70[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D7DD0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D80C8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D8228[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D7F80[0], 0, 0; + %assign V_$006DAD18[0], 0, 0; + %assign V_$006DACA8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D8E20[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006D83C0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D83F8[0], 0, 0; + %jmp T_24.1; +T_24.0 ; + %load/v 32, V_$006DA4D0[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006DB188[0], 0, 32; + %load/v 32, V_$006D8560[0], 1; + %assign V_$006D7E68[0], 0, 32; + %load/v 32, V_$006DA450[0], 1; + %assign V_$006DADF8[0], 0, 32; + %load/v 32, V_$006D9D58[0], 2; + %assign V_$006D8260[0], 0, 32; + %assign V_$006D8260[1], 0, 33; + %load/v 32, V_$006DA638[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D71D0[0], 0, 32; + %load/v 32, V_$006DA918[0], 1; + %assign V_$006DB4B8[0], 0, 32; + %load/v 32, V_$006D8900[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D7B08[0], 0, 32; + %load/v 32, V_$006D8B78[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D7C70[0], 0, 32; + %load/v 32, V_$006D90D8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D7DD0[0], 0, 32; + %load/v 32, V_$006D93B8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D80C8[0], 0, 32; + %load/v 32, V_$006D9F90[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D8228[0], 0, 32; + %load/v 32, V_$006D85E0[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D7F80[0], 0, 32; + %load/v 32, V_$006DA3D0[0], 1; + %assign V_$006DAD18[0], 0, 32; + %load/v 32, V_$006DA348[0], 1; + %assign V_$006DACA8[0], 0, 32; + %load/v 32, V_$006DA0A8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D8E20[0], 0, 32; + %load/v 32, V_$006D9750[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006D83C0[0], 0, 32; + %load/v 32, V_$006D9AB8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D83F8[0], 0, 32; +T_24.1 ; + %jmp T_24; + .thread T_24; + .scope S_006D0E50; +T_25 ; + %wait E_006D1810; + %load/v 32, V_$006D1830[0], 6; + %ix/load 0, 6; + %assign/v0 V_$006D1C70[0], 0, 32; + %load/v 32, V_$006D6E38[0], 1; + %assign V_$006D5F20[0], 0, 32; + %load/v 32, V_$006D6C70[0], 1; + %assign V_$006D5948[0], 0, 32; + %load/v 32, V_$006D6488[0], 2; + %assign V_$006D5DD8[0], 0, 32; + %assign V_$006D5DD8[1], 0, 33; + %load/v 32, V_$006D75E8[0], 2; + %assign V_$006D63B0[0], 0, 32; + %assign V_$006D63B0[1], 0, 33; + %load/v 32, V_$006D7208[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 32; + %load/v 32, V_$006D72A8[0], 1; + %assign V_$006D62B0[0], 0, 32; + %load/v 32, V_$006D6920[0], 1; + %assign V_$006D5FB0[0], 0, 32; + %load/v 32, V_$006D2970[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D3890[0], 0, 32; + %load/v 32, V_$006D2AB0[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D3B18[0], 0, 32; + %load/v 32, V_$006D2C18[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D40D8[0], 0, 32; + %load/v 32, V_$006D2D78[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D43B8[0], 0, 32; + %load/v 32, V_$006D3138[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D4F90[0], 0, 32; + %load/v 32, V_$006D2790[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D3580[0], 0, 32; + %load/v 32, V_$006D6C38[0], 1; + %assign V_$006D5880[0], 0, 32; + %load/v 32, V_$006D32B0[0], 9; + %ix/load 0, 9; + %assign/v0 V_$006D5200[0], 0, 32; + %load/v 32, V_$006D3278[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D4750[0], 0, 32; + %load/v 32, V_$006D3310[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D4A70[0], 0, 32; + %load/v 32, V_$006D7488[0], 1; + %assign V_$006D6330[0], 0, 32; + %load/v 32, V_$006D6B90[0], 1; + %assign V_$006D5800[0], 0, 32; + %load/v 32, V_$006D6958[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D5520[0], 0, 32; + %load/v 32, V_$006D6CA8[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006D5A20[0], 0, 32; + %load/v 32, V_$006D3370[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D4D10[0], 0, 32; + %load/v 32, V_$006D1830[0], 6; + %cmpi/u 32, 0, 6; + %jmp/1 T_25.0, 6; + %cmpi/u 32, 4, 6; + %jmp/1 T_25.1, 6; + %cmpi/u 32, 1, 6; + %jmp/1 T_25.2, 6; + %cmpi/u 32, 2, 6; + %jmp/1 T_25.3, 6; + %cmpi/u 32, 3, 6; + %jmp/1 T_25.4, 6; + %cmpi/u 32, 5, 6; + %jmp/1 T_25.5, 6; + %cmpi/u 32, 6, 6; + %jmp/1 T_25.6, 6; + %cmpi/u 32, 7, 6; + %jmp/1 T_25.7, 6; + %cmpi/u 32, 8, 6; + %jmp/1 T_25.8, 6; + %cmpi/u 32, 9, 6; + %jmp/1 T_25.9, 6; + %cmpi/u 32, 10, 6; + %jmp/1 T_25.10, 6; + %cmpi/u 32, 40, 6; + %jmp/1 T_25.11, 6; + %cmpi/u 32, 41, 6; + %jmp/1 T_25.12, 6; + %cmpi/u 32, 42, 6; + %jmp/1 T_25.13, 6; + %cmpi/u 32, 43, 6; + %jmp/1 T_25.14, 6; + %cmpi/u 32, 44, 6; + %jmp/1 T_25.15, 6; + %cmpi/u 32, 45, 6; + %jmp/1 T_25.16, 6; + %cmpi/u 32, 23, 6; + %jmp/1 T_25.17, 6; + %cmpi/u 32, 24, 6; + %jmp/1 T_25.18, 6; + %cmpi/u 32, 25, 6; + %jmp/1 T_25.19, 6; + %cmpi/u 32, 26, 6; + %jmp/1 T_25.20, 6; + %cmpi/u 32, 27, 6; + %jmp/1 T_25.21, 6; + %cmpi/u 32, 28, 6; + %jmp/1 T_25.22, 6; + %cmpi/u 32, 29, 6; + %jmp/1 T_25.23, 6; + %cmpi/u 32, 30, 6; + %jmp/1 T_25.24, 6; + %cmpi/u 32, 31, 6; + %jmp/1 T_25.25, 6; + %cmpi/u 32, 46, 6; + %jmp/1 T_25.26, 6; + %cmpi/u 32, 32, 6; + %jmp/1 T_25.27, 6; + %cmpi/u 32, 33, 6; + %jmp/1 T_25.28, 6; + %cmpi/u 32, 34, 6; + %jmp/1 T_25.29, 6; + %cmpi/u 32, 35, 6; + %jmp/1 T_25.30, 6; + %cmpi/u 32, 36, 6; + %jmp/1 T_25.31, 6; + %cmpi/u 32, 37, 6; + %jmp/1 T_25.32, 6; + %cmpi/u 32, 38, 6; + %jmp/1 T_25.33, 6; + %cmpi/u 32, 39, 6; + %jmp/1 T_25.34, 6; + %cmpi/u 32, 11, 6; + %jmp/1 T_25.35, 6; + %cmpi/u 32, 12, 6; + %jmp/1 T_25.36, 6; + %cmpi/u 32, 13, 6; + %jmp/1 T_25.37, 6; + %cmpi/u 32, 14, 6; + %jmp/1 T_25.38, 6; + %cmpi/u 32, 15, 6; + %jmp/1 T_25.39, 6; + %cmpi/u 32, 16, 6; + %jmp/1 T_25.40, 6; + %cmpi/u 32, 17, 6; + %jmp/1 T_25.41, 6; + %cmpi/u 32, 18, 6; + %jmp/1 T_25.42, 6; + %cmpi/u 32, 19, 6; + %jmp/1 T_25.43, 6; + %cmpi/u 32, 20, 6; + %jmp/1 T_25.44, 6; + %cmpi/u 32, 21, 6; + %jmp/1 T_25.45, 6; + %cmpi/u 32, 22, 6; + %jmp/1 T_25.46, 6; + %cmpi/u 32, 47, 6; + %jmp/1 T_25.47, 6; + %jmp T_25.48; +T_25.0 ; + %assign V_$006D5F20[0], 0, 0; + %assign V_$006D5948[0], 0, 1; + %assign V_$006D5DD8[0], 0, 0; + %assign V_$006D5DD8[1], 0, 0; + %assign V_$006D63B0[0], 0, 0; + %assign V_$006D63B0[1], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 0; + %assign V_$006D62B0[0], 0, 0; + %assign V_$006D5FB0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D3890[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D3B18[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D40D8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D43B8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D4F90[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D3580[0], 0, 0; + %assign V_$006D5880[0], 0, 0; + %ix/load 0, 9; + %assign/v0 V_$006D5200[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D4750[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D4A70[0], 0, 0; + %assign V_$006D5DD8[0], 0, 0; + %assign V_$006D5DD8[1], 0, 0; + %assign V_$006D63B0[0], 0, 0; + %assign V_$006D63B0[1], 0, 0; + %assign V_$006D6330[0], 0, 0; + %assign V_$006D5800[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D5520[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006D5A20[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D4D10[0], 0, 0; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; + %jmp T_25.48; +T_25.1 ; + %assign V_$006D5948[0], 0, 1; + %assign V_$006D5F20[0], 0, 1; + %load 32, V_$006D6EC0[0]; + %load 33, V_$006D6EC0[1]; + %cmpi/u 32, 2, 2; + %jmp/0xz T_25.49, 4; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %assign V_$006D5948[0], 0, 0; + %assign V_$006D5F20[0], 0, 0; + %assign V_$006D5DD8[0], 0, 0; + %assign V_$006D5DD8[1], 0, 0; + %jmp T_25.50; +T_25.49 ; + %load 32, V_$006D6EC0[0]; + %load 33, V_$006D6EC0[1]; + %cmpi/u 32, 1, 2; + %jmp/0xz T_25.51, 4; + %assign V_$006D1C70[0], 0, 1; + %ix/load 0, 5; + %assign/v0 V_$006D1C70[1], 0, 0; + %assign V_$006D5948[0], 0, 0; + %assign V_$006D5F20[0], 0, 0; + %assign V_$006D63B0[0], 0, 0; + %assign V_$006D63B0[1], 0, 0; +T_25.51 ; +T_25.50 ; + %jmp T_25.48; +T_25.2 ; + %ix/load 0, 3; + %assign/v0 V_$006D3890[0], 0, 0; + %assign V_$006D3890[3], 0, 1; + %assign V_$006D3890[4], 0, 1; + %assign V_$006D3890[5], 0, 0; + %assign V_$006D3890[6], 0, 1; + %assign V_$006D3890[7], 0, 0; + %load 32, V_$006D2078[24]; + %load 33, V_$006D2078[25]; + %load 34, V_$006D2078[26]; + %load 35, V_$006D2078[27]; + %load 36, V_$006D2078[28]; + %load 37, V_$006D2078[29]; + %load 38, V_$006D2078[30]; + %load 39, V_$006D2078[31]; + %ix/load 0, 8; + %assign/v0 V_$006D3B18[0], 0, 32; + %load 32, V_$006D2078[16]; + %load 33, V_$006D2078[17]; + %load 34, V_$006D2078[18]; + %load 35, V_$006D2078[19]; + %load 36, V_$006D2078[20]; + %load 37, V_$006D2078[21]; + %load 38, V_$006D2078[22]; + %load 39, V_$006D2078[23]; + %ix/load 0, 8; + %assign/v0 V_$006D40D8[0], 0, 32; + %load 32, V_$006D2078[8]; + %load 33, V_$006D2078[9]; + %load 34, V_$006D2078[10]; + %load 35, V_$006D2078[11]; + %load 36, V_$006D2078[12]; + %load 37, V_$006D2078[13]; + %load 38, V_$006D2078[14]; + %load 39, V_$006D2078[15]; + %ix/load 0, 8; + %assign/v0 V_$006D43B8[0], 0, 32; + %load 32, V_$006D2078[0]; + %load 33, V_$006D2078[1]; + %load 34, V_$006D2078[2]; + %load 35, V_$006D2078[3]; + %load 36, V_$006D2078[4]; + %load 37, V_$006D2078[5]; + %load 38, V_$006D2078[6]; + %load 39, V_$006D2078[7]; + %ix/load 0, 8; + %assign/v0 V_$006D4F90[0], 0, 32; + %ix/load 0, 8; + %assign/v0 V_$006D3580[0], 0, 1; + %assign V_$006D5880[0], 0, 1; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 1; + %ix/load 0, 4; + %assign/v0 V_$006D1C70[2], 0, 0; + %jmp T_25.48; +T_25.3 ; + %load 32, V_$006D6C00[0]; + %load 33, V_$006D6648[0]; + %load 34, V_$006D6F98[0]; + %load 35, V_$006D6F98[1]; + %load 36, V_$006D6F98[2]; + %load 37, V_$006D6F98[3]; + %load 38, V_$006D6F98[4]; + %load 39, V_$006D6F98[5]; + %load 40, V_$006D6F98[6]; + %load 41, V_$006D6F98[7]; + %cmpi/u 34, 0, 8; + %inv 4, 1; + %mov 34, 4, 1; + %or 33, 34, 1; + %and 32, 33, 1; + %jmp/0xz T_25.53, 32; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; + %assign V_$006D63B0[0], 0, 1; + %assign V_$006D63B0[1], 0, 0; + %jmp T_25.54; +T_25.53 ; + %load 32, V_$006D6C00[0]; + %jmp/0xz T_25.55, 32; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; +T_25.55 ; +T_25.54 ; + %jmp T_25.48; +T_25.4 ; + %assign V_$006D5880[0], 0, 0; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %ix/load 0, 4; + %assign/v0 V_$006D1C70[2], 0, 0; + %jmp T_25.48; +T_25.5 ; + %assign V_$006D62B0[0], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.6 ; + %load 32, V_$006D7198[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_25.57, 4; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %assign V_$006D62B0[0], 0, 1; +T_25.57 ; + %jmp T_25.48; +T_25.7 ; + %assign V_$006D62B0[0], 0, 0; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.8 ; + %load 32, V_$006D7198[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_25.59, 4; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %assign V_$006D62B0[0], 0, 1; +T_25.59 ; + %jmp T_25.48; +T_25.9 ; + %assign V_$006D62B0[0], 0, 0; + %ix/load 0, 4; + %assign/v0 V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.10 ; + %load 32, V_$006D7198[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_25.61, 4; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 0; + %assign V_$006D6008[0], 0, 0; + %ix/load 0, 7; + %assign/v0 V_$006D6008[1], 0, 1; + %assign V_$006D62B0[0], 0, 1; +T_25.61 ; + %jmp T_25.48; +T_25.11 ; + %load/v 32, V_$006D3370[0], 8; + %cmpi/u 32, 0, 8; + %mov 32, 4, 1; + %load/v 33, V_$006D6CA8[0], 10; + %cmpi/u 33, 182, 10; + %inv 4, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_25.63, 32; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %load/v 32, V_$006D6CA8[0], 10; + %addi 32, 1, 10; + %ix/load 0, 10; + %assign/v0 V_$006D5A20[0], 0, 32; + %jmp T_25.64; +T_25.63 ; + %load/v 32, V_$006D6CA8[0], 10; + %cmpi/u 32, 182, 10; + %jmp/0xz T_25.65, 4; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; + %assign V_$006D63B0[0], 0, 1; + %assign V_$006D63B0[1], 0, 1; + %jmp T_25.66; +T_25.65 ; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; +T_25.66 ; +T_25.64 ; + %jmp T_25.48; +T_25.12 ; + %load 32, V_$006D68B8[0]; + %jmp/0xz T_25.67, 32; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %load 32, V_$006D66D8[0]; + %load 33, V_$006D66D8[1]; + %load 34, V_$006D66D8[2]; + %load 35, V_$006D66D8[3]; + %load 36, V_$006D66D8[4]; + %load 37, V_$006D66D8[5]; + %load 38, V_$006D66D8[6]; + %load 39, V_$006D66D8[7]; + %ix/load 0, 8; + %assign/v0 V_$006D4D10[0], 0, 32; +T_25.67 ; + %jmp T_25.48; +T_25.13 ; + %assign V_$006D62B0[0], 0, 0; + %assign V_$006D5FB0[0], 0, 0; + %load/v 32, V_$006D3278[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006D4750[0], 0, 32; + %ix/load 0, 8; + %assign/v0 V_$006D4A70[0], 0, 0; + %load/v 32, V_$006D3278[0], 8; + %cmpi/u 32, 255, 8; + %jmp/0xz T_25.69, 4; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %jmp T_25.70; +T_25.69 ; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; +T_25.70 ; + %jmp T_25.48; +T_25.14 ; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %assign V_$006D62B0[0], 0, 1; + %assign V_$006D5FB0[0], 0, 1; + %ix/load 0, 8; + %assign/v0 V_$006D4750[0], 0, 0; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %jmp T_25.48; +T_25.15 ; + %load/v 32, V_$006D3310[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006D4A70[0], 0, 32; + %load/v 32, V_$006D3310[0], 8; + %cmpi/u 32, 255, 8; + %jmp/0xz T_25.71, 4; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; +T_25.71 ; + %jmp T_25.48; +T_25.16 ; + %ix/load 0, 10; + %assign/v0 V_$006D5A20[0], 0, 0; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %jmp T_25.48; +T_25.17 ; + %assign V_$006D3890[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D3890[1], 0, 0; + %assign V_$006D3890[4], 0, 1; + %assign V_$006D3890[5], 0, 0; + %assign V_$006D3890[6], 0, 1; + %assign V_$006D3890[7], 0, 0; + %load 32, V_$006D2078[24]; + %load 33, V_$006D2078[25]; + %load 34, V_$006D2078[26]; + %load 35, V_$006D2078[27]; + %load 36, V_$006D2078[28]; + %load 37, V_$006D2078[29]; + %load 38, V_$006D2078[30]; + %load 39, V_$006D2078[31]; + %ix/load 0, 8; + %assign/v0 V_$006D3B18[0], 0, 32; + %load 32, V_$006D2078[16]; + %load 33, V_$006D2078[17]; + %load 34, V_$006D2078[18]; + %load 35, V_$006D2078[19]; + %load 36, V_$006D2078[20]; + %load 37, V_$006D2078[21]; + %load 38, V_$006D2078[22]; + %load 39, V_$006D2078[23]; + %ix/load 0, 8; + %assign/v0 V_$006D40D8[0], 0, 32; + %load 32, V_$006D2078[8]; + %load 33, V_$006D2078[9]; + %load 34, V_$006D2078[10]; + %load 35, V_$006D2078[11]; + %load 36, V_$006D2078[12]; + %load 37, V_$006D2078[13]; + %load 38, V_$006D2078[14]; + %load 39, V_$006D2078[15]; + %ix/load 0, 8; + %assign/v0 V_$006D43B8[0], 0, 32; + %load 32, V_$006D2078[0]; + %load 33, V_$006D2078[1]; + %load 34, V_$006D2078[2]; + %load 35, V_$006D2078[3]; + %load 36, V_$006D2078[4]; + %load 37, V_$006D2078[5]; + %load 38, V_$006D2078[6]; + %load 39, V_$006D2078[7]; + %ix/load 0, 8; + %assign/v0 V_$006D4F90[0], 0, 32; + %ix/load 0, 8; + %assign/v0 V_$006D3580[0], 0, 1; + %assign V_$006D5880[0], 0, 1; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.18 ; + %load 32, V_$006D6C00[0]; + %load 33, V_$006D6648[0]; + %load 34, V_$006D6F98[0]; + %load 35, V_$006D6F98[1]; + %load 36, V_$006D6F98[2]; + %load 37, V_$006D6F98[3]; + %load 38, V_$006D6F98[4]; + %load 39, V_$006D6F98[5]; + %load 40, V_$006D6F98[6]; + %load 41, V_$006D6F98[7]; + %cmpi/u 34, 0, 8; + %inv 4, 1; + %mov 34, 4, 1; + %or 33, 34, 1; + %and 32, 33, 1; + %jmp/0xz T_25.73, 32; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; + %assign V_$006D5DD8[0], 0, 1; + %assign V_$006D5DD8[1], 0, 0; + %jmp T_25.74; +T_25.73 ; + %load 32, V_$006D6C00[0]; + %jmp/0xz T_25.75, 32; + %assign V_$006D1C70[0], 0, 0; + %ix/load 0, 4; + %assign/v0 V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[5], 0, 0; +T_25.75 ; +T_25.74 ; + %jmp T_25.48; +T_25.19 ; + %assign V_$006D5880[0], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.20 ; + %load/v 32, V_$006D3370[0], 8; + %cmpi/u 32, 254, 8; + %inv 4, 1; + %mov 32, 4, 1; + %load/v 33, V_$006D6CA8[0], 10; + %cmpi/u 33, 72, 10; + %inv 4, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_25.77, 32; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %load/v 32, V_$006D6CA8[0], 10; + %addi 32, 1, 10; + %ix/load 0, 10; + %assign/v0 V_$006D5A20[0], 0, 32; + %ix/load 0, 8; + %assign/v0 V_$006D4750[0], 0, 0; + %jmp T_25.78; +T_25.77 ; + %load/v 32, V_$006D6CA8[0], 10; + %cmpi/u 32, 72, 10; + %jmp/0xz T_25.79, 4; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; + %assign V_$006D5DD8[0], 0, 0; + %assign V_$006D5DD8[1], 0, 1; + %jmp T_25.80; +T_25.79 ; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %assign V_$006D5FB0[0], 0, 1; +T_25.80 ; +T_25.78 ; + %jmp T_25.48; +T_25.21 ; + %load 32, V_$006D68B8[0]; + %jmp/0xz T_25.81, 32; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %load 32, V_$006D66D8[0]; + %load 33, V_$006D66D8[1]; + %load 34, V_$006D66D8[2]; + %load 35, V_$006D66D8[3]; + %load 36, V_$006D66D8[4]; + %load 37, V_$006D66D8[5]; + %load 38, V_$006D66D8[6]; + %load 39, V_$006D66D8[7]; + %ix/load 0, 8; + %assign/v0 V_$006D4D10[0], 0, 32; +T_25.81 ; + %jmp T_25.48; +T_25.22 ; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %assign V_$006D62B0[0], 0, 1; + %assign V_$006D5FB0[0], 0, 1; + %ix/load 0, 5; + %assign/v0 V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.23 ; + %load/v 32, V_$006D3278[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006D4750[0], 0, 32; + %ix/load 0, 8; + %assign/v0 V_$006D4A70[0], 0, 0; + %load/v 32, V_$006D3278[0], 8; + %cmpi/u 32, 255, 8; + %jmp/0xz T_25.83, 4; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.84; +T_25.83 ; + %assign V_$006D1C70[0], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; +T_25.84 ; + %jmp T_25.48; +T_25.24 ; + %ix/load 0, 10; + %assign/v0 V_$006D5A20[0], 0, 0; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.25 ; + %assign V_$006D62B0[0], 0, 0; + %assign V_$006D5FB0[0], 0, 0; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.26 ; + %load/v 32, V_$006D3310[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006D4A70[0], 0, 32; + %load/v 32, V_$006D3310[0], 8; + %cmpi/u 32, 255, 8; + %jmp/0xz T_25.85, 4; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[5], 0, 0; +T_25.85 ; + %jmp T_25.48; +T_25.27 ; + %assign V_$006D62B0[0], 0, 1; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %load/v 32, V_$006D32B0[0], 9; + %addi 32, 1, 9; + %ix/load 0, 9; + %assign/v0 V_$006D5200[0], 0, 32; + %assign V_$006D1C70[0], 0, 1; + %ix/load 0, 4; + %assign/v0 V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %jmp T_25.48; +T_25.28 ; + %assign V_$006D62B0[0], 0, 0; + %load 32, V_$006D68B8[0]; + %jmp/0xz T_25.87, 32; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %assign V_$006D5800[0], 0, 1; + %assign V_$006D5FB0[0], 0, 1; + %load 32, V_$006D66D8[0]; + %load 33, V_$006D66D8[1]; + %load 34, V_$006D66D8[2]; + %load 35, V_$006D66D8[3]; + %load 36, V_$006D66D8[4]; + %load 37, V_$006D66D8[5]; + %load 38, V_$006D66D8[6]; + %load 39, V_$006D66D8[7]; + %ix/load 0, 8; + %assign/v0 V_$006D5520[0], 0, 32; +T_25.87 ; + %jmp T_25.48; +T_25.29 ; + %load/v 32, V_$006D32B0[0], 9; + %cmpi/u 32, 0, 9; + %jmp/0xz T_25.89, 4; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %assign V_$006D5FB0[0], 0, 0; + %assign V_$006D5800[0], 0, 0; + %jmp T_25.90; +T_25.89 ; + %ix/load 0, 5; + %assign/v0 V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %assign V_$006D5FB0[0], 0, 0; + %assign V_$006D5800[0], 0, 0; +T_25.90 ; + %jmp T_25.48; +T_25.30 ; + %ix/load 0, 5; + %assign/v0 V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %assign V_$006D5FB0[0], 0, 0; + %ix/load 0, 9; + %assign/v0 V_$006D5200[0], 0, 0; + %jmp T_25.48; +T_25.31 ; + %assign V_$006D62B0[0], 0, 0; + %load 32, V_$006D7160[0]; + %jmp/0xz T_25.91, 32; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; +T_25.91 ; + %jmp T_25.48; +T_25.32 ; + %assign V_$006D62B0[0], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %jmp T_25.48; +T_25.33 ; + %load 32, V_$006D7198[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_25.93, 4; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %assign V_$006D62B0[0], 0, 1; +T_25.93 ; + %jmp T_25.48; +T_25.34 ; + %load 32, V_$006D7198[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_25.95, 4; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %assign V_$006D62B0[0], 0, 1; +T_25.95 ; + %jmp T_25.48; +T_25.35 ; + %assign V_$006D62B0[0], 0, 0; + %load/v 32, V_$006D32B0[0], 9; + %cmpi/u 32, 0, 9; + %jmp/0xz T_25.97, 4; + %ix/load 0, 4; + %assign/v0 V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.98; +T_25.97 ; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 0; +T_25.98 ; + %jmp T_25.48; +T_25.36 ; + %load 32, V_$006D7198[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_25.99, 4; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 0; + %load 32, V_$006D73E8[0]; + %load 33, V_$006D73E8[1]; + %load 34, V_$006D73E8[2]; + %load 35, V_$006D73E8[3]; + %load 36, V_$006D73E8[4]; + %load 37, V_$006D73E8[5]; + %load 38, V_$006D73E8[6]; + %load 39, V_$006D73E8[7]; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 32; + %assign V_$006D62B0[0], 0, 1; +T_25.99 ; + %jmp T_25.48; +T_25.37 ; + %assign V_$006D6330[0], 0, 1; + %load/v 32, V_$006D32B0[0], 9; + %addi 32, 1, 9; + %ix/load 0, 9; + %assign/v0 V_$006D5200[0], 0, 32; + %assign V_$006D1C70[0], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.38 ; + %assign V_$006D6330[0], 0, 0; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.39 ; + %ix/load 0, 9; + %assign/v0 V_$006D5200[0], 0, 0; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.40 ; + %load 32, V_$006D7198[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_25.101, 4; + %assign V_$006D1C70[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %assign V_$006D62B0[0], 0, 1; +T_25.101 ; + %jmp T_25.48; +T_25.41 ; + %assign V_$006D62B0[0], 0, 0; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %jmp T_25.48; +T_25.42 ; + %assign V_$006D62B0[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006D5A20[0], 0, 0; + %load 32, V_$006D7160[0]; + %jmp/0xz T_25.103, 32; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; +T_25.103 ; + %jmp T_25.48; +T_25.43 ; + %load 32, V_$006D7198[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_25.105, 4; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 0; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %assign V_$006D62B0[0], 0, 1; +T_25.105 ; + %jmp T_25.48; +T_25.44 ; + %load/v 32, V_$006D6CA8[0], 10; + %cmpi/u 32, 512, 10; + %jmp/0xz T_25.107, 4; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006D1C70[3], 0, 0; + %assign V_$006D63B0[0], 0, 0; + %assign V_$006D63B0[1], 0, 1; + %jmp T_25.108; +T_25.107 ; + %load/v 32, V_$006D3370[0], 5; + %cmpi/u 32, 5, 5; + %jmp/0xz T_25.109, 4; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %jmp T_25.110; +T_25.109 ; + %assign V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; +T_25.110 ; +T_25.108 ; + %jmp T_25.48; +T_25.45 ; + %ix/load 0, 4; + %assign/v0 V_$006D1C70[0], 0, 1; + %assign V_$006D1C70[4], 0, 0; + %assign V_$006D1C70[5], 0, 1; + %ix/load 0, 8; + %assign/v0 V_$006D6008[0], 0, 1; + %assign V_$006D62B0[0], 0, 1; + %load/v 32, V_$006D6CA8[0], 10; + %addi 32, 1, 10; + %ix/load 0, 10; + %assign/v0 V_$006D5A20[0], 0, 32; + %assign V_$006D5FB0[0], 0, 1; + %jmp T_25.48; +T_25.46 ; + %load 32, V_$006D68B8[0]; + %jmp/0xz T_25.111, 32; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 0; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %load 32, V_$006D66D8[0]; + %load 33, V_$006D66D8[1]; + %load 34, V_$006D66D8[2]; + %load 35, V_$006D66D8[3]; + %load 36, V_$006D66D8[4]; + %load 37, V_$006D66D8[5]; + %load 38, V_$006D66D8[6]; + %load 39, V_$006D66D8[7]; + %ix/load 0, 8; + %assign/v0 V_$006D4D10[0], 0, 32; +T_25.111 ; + %jmp T_25.48; +T_25.47 ; + %assign V_$006D1C70[0], 0, 0; + %assign V_$006D1C70[1], 0, 1; + %assign V_$006D1C70[2], 0, 1; + %assign V_$006D1C70[3], 0, 0; + %assign V_$006D1C70[4], 0, 1; + %assign V_$006D1C70[5], 0, 0; + %assign V_$006D62B0[0], 0, 0; + %assign V_$006D5FB0[0], 0, 0; + %jmp T_25.48; +T_25.48 ; + %jmp T_25; + .thread T_25, $push; + .scope S_006D0E50; +T_26 ; + %wait E_003DE478; + %load 32, V_$006D66A0[0]; + %jmp/0xz T_26.0, 32; + %ix/load 0, 6; + %assign/v0 V_$006D1830[0], 0, 0; + %jmp T_26.1; +T_26.0 ; + %load/v 32, V_$006D1C70[0], 6; + %ix/load 0, 6; + %assign/v0 V_$006D1830[0], 0, 32; +T_26.1 ; + %jmp T_26; + .thread T_26; + .scope S_006D0E50; +T_27 ; + %wait E_003DE478; + %load 32, V_$006D66A0[0]; + %jmp/0xz T_27.0, 32; + %assign V_$006D6E38[0], 0, 0; + %assign V_$006D6C70[0], 0, 1; + %assign V_$006D6488[0], 0, 0; + %assign V_$006D6488[1], 0, 0; + %assign V_$006D75E8[0], 0, 0; + %assign V_$006D75E8[1], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D7208[0], 0, 0; + %assign V_$006D72A8[0], 0, 0; + %assign V_$006D6920[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D2970[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D2AB0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D2C18[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D2D78[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D3138[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D2790[0], 0, 0; + %assign V_$006D6C38[0], 0, 0; + %assign V_$006D7488[0], 0, 0; + %assign V_$006D6B90[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D6958[0], 0, 0; + %ix/load 0, 9; + %assign/v0 V_$006D32B0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D3278[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D3310[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006D6CA8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D3370[0], 0, 0; + %jmp T_27.1; +T_27.0 ; + %load/v 32, V_$006D5F20[0], 1; + %assign V_$006D6E38[0], 0, 32; + %load/v 32, V_$006D5948[0], 1; + %assign V_$006D6C70[0], 0, 32; + %load/v 32, V_$006D5DD8[0], 2; + %assign V_$006D6488[0], 0, 32; + %assign V_$006D6488[1], 0, 33; + %load/v 32, V_$006D63B0[0], 2; + %assign V_$006D75E8[0], 0, 32; + %assign V_$006D75E8[1], 0, 33; + %load/v 32, V_$006D6008[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D7208[0], 0, 32; + %load/v 32, V_$006D62B0[0], 1; + %assign V_$006D72A8[0], 0, 32; + %load/v 32, V_$006D5FB0[0], 1; + %assign V_$006D6920[0], 0, 32; + %load/v 32, V_$006D3890[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D2970[0], 0, 32; + %load/v 32, V_$006D3B18[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D2AB0[0], 0, 32; + %load/v 32, V_$006D40D8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D2C18[0], 0, 32; + %load/v 32, V_$006D43B8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D2D78[0], 0, 32; + %load/v 32, V_$006D4F90[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D3138[0], 0, 32; + %load/v 32, V_$006D3580[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D2790[0], 0, 32; + %load/v 32, V_$006D5880[0], 1; + %assign V_$006D6C38[0], 0, 32; + %load/v 32, V_$006D6330[0], 1; + %assign V_$006D7488[0], 0, 32; + %load/v 32, V_$006D5800[0], 1; + %assign V_$006D6B90[0], 0, 32; + %load/v 32, V_$006D5520[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D6958[0], 0, 32; + %load/v 32, V_$006D5200[0], 9; + %ix/load 0, 9; + %assign/v0 V_$006D32B0[0], 0, 32; + %load/v 32, V_$006D4750[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D3278[0], 0, 32; + %load/v 32, V_$006D4A70[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D3310[0], 0, 32; + %load/v 32, V_$006D5A20[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006D6CA8[0], 0, 32; + %load/v 32, V_$006D4D10[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D3370[0], 0, 32; +T_27.1 ; + %jmp T_27; + .thread T_27; + .scope S_006CC9E8; +T_28 ; + %wait E_006CCC00; + %load 32, V_$006D13D0[0]; + %load 33, V_$006D1428[0]; + %or 32, 33, 1; + %assign V_$006D1398[0], 0, 32; + %jmp T_28; + .thread T_28, $push; + .scope S_006CC9E8; +T_29 ; + %wait E_003DE478; + %load 32, V_$006CDA58[0]; + %load 33, V_$006CDA58[1]; + %load 34, V_$006CDA58[2]; + %load 35, V_$006CDA58[3]; + %load 36, V_$006CDA58[4]; + %load 37, V_$006CDA58[5]; + %load 38, V_$006CDA58[6]; + %load 39, V_$006CDA58[7]; + %load 40, V_$006CDCF8[0]; + %load 41, V_$006CDCF8[1]; + %load 42, V_$006CDCF8[2]; + %load 43, V_$006CDCF8[3]; + %load 44, V_$006CDCF8[4]; + %load 45, V_$006CDCF8[5]; + %load 46, V_$006CDCF8[6]; + %load 47, V_$006CDCF8[7]; + %or 32, 40, 8; + %ix/load 0, 8; + %assign/v0 V_$006CD788[0], 0, 32; + %load 32, V_$006CE428[0]; + %load 33, V_$006CE428[1]; + %load 34, V_$006CE428[2]; + %load 35, V_$006CE428[3]; + %load 36, V_$006CE428[4]; + %load 37, V_$006CE428[5]; + %load 38, V_$006CE428[6]; + %load 39, V_$006CE428[7]; + %load 40, V_$006CE538[0]; + %load 41, V_$006CE538[1]; + %load 42, V_$006CE538[2]; + %load 43, V_$006CE538[3]; + %load 44, V_$006CE538[4]; + %load 45, V_$006CE538[5]; + %load 46, V_$006CE538[6]; + %load 47, V_$006CE538[7]; + %or 32, 40, 8; + %ix/load 0, 8; + %assign/v0 V_$006CE188[0], 0, 32; + %load 32, V_$006CE460[0]; + %load 33, V_$006CE460[1]; + %load 34, V_$006CE460[2]; + %load 35, V_$006CE460[3]; + %load 36, V_$006CE460[4]; + %load 37, V_$006CE460[5]; + %load 38, V_$006CE460[6]; + %load 39, V_$006CE460[7]; + %load 40, V_$006CECD8[0]; + %load 41, V_$006CECD8[1]; + %load 42, V_$006CECD8[2]; + %load 43, V_$006CECD8[3]; + %load 44, V_$006CECD8[4]; + %load 45, V_$006CECD8[5]; + %load 46, V_$006CECD8[6]; + %load 47, V_$006CECD8[7]; + %or 32, 40, 8; + %ix/load 0, 8; + %assign/v0 V_$006CE7B0[0], 0, 32; + %load 32, V_$006CF3F8[0]; + %load 33, V_$006CF3F8[1]; + %load 34, V_$006CF3F8[2]; + %load 35, V_$006CF3F8[3]; + %load 36, V_$006CF3F8[4]; + %load 37, V_$006CF3F8[5]; + %load 38, V_$006CF3F8[6]; + %load 39, V_$006CF3F8[7]; + %load 40, V_$006CFF80[0]; + %load 41, V_$006CFF80[1]; + %load 42, V_$006CFF80[2]; + %load 43, V_$006CFF80[3]; + %load 44, V_$006CFF80[4]; + %load 45, V_$006CFF80[5]; + %load 46, V_$006CFF80[6]; + %load 47, V_$006CFF80[7]; + %or 32, 40, 8; + %ix/load 0, 8; + %assign/v0 V_$006CF158[0], 0, 32; + %load 32, V_$006CFA18[0]; + %load 33, V_$006CFA18[1]; + %load 34, V_$006CFA18[2]; + %load 35, V_$006CFA18[3]; + %load 36, V_$006CFA18[4]; + %load 37, V_$006CFA18[5]; + %load 38, V_$006CFA18[6]; + %load 39, V_$006CFA18[7]; + %load 40, V_$006CFCB8[0]; + %load 41, V_$006CFCB8[1]; + %load 42, V_$006CFCB8[2]; + %load 43, V_$006CFCB8[3]; + %load 44, V_$006CFCB8[4]; + %load 45, V_$006CFCB8[5]; + %load 46, V_$006CFCB8[6]; + %load 47, V_$006CFCB8[7]; + %or 32, 40, 8; + %ix/load 0, 8; + %assign/v0 V_$006CF750[0], 0, 32; + %load 32, V_$006CD390[0]; + %load 33, V_$006CD390[1]; + %load 34, V_$006CD390[2]; + %load 35, V_$006CD390[3]; + %load 36, V_$006CD390[4]; + %load 37, V_$006CD390[5]; + %load 38, V_$006CD390[6]; + %load 39, V_$006CD390[7]; + %load 40, V_$006CDF58[0]; + %load 41, V_$006CDF58[1]; + %load 42, V_$006CDF58[2]; + %load 43, V_$006CDF58[3]; + %load 44, V_$006CDF58[4]; + %load 45, V_$006CDF58[5]; + %load 46, V_$006CDF58[6]; + %load 47, V_$006CDF58[7]; + %or 32, 40, 8; + %ix/load 0, 8; + %assign/v0 V_$006CD0D8[0], 0, 32; + %jmp T_29; + .thread T_29; + .scope S_006CC9E8; +T_30 ; + %wait E_006CCA58; + %load/v 32, V_$006CCC20[0], 5; + %ix/load 0, 5; + %assign/v0 V_$006CCD78[0], 0, 32; + %load/v 32, V_$006D17B8[0], 1; + %assign V_$006D0AC0[0], 0, 32; + %load/v 32, V_$006D1678[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 32; + %load/v 32, V_$006D14A8[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006D0F08[0], 0, 32; + %load/v 32, V_$006D1308[0], 1; + %assign V_$006D04F0[0], 0, 32; + %load/v 32, V_$006D0B40[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D01A8[0], 0, 32; + %load/v 32, V_$006D1010[0], 1; + %assign V_$006D0488[0], 0, 32; + %load/v 32, V_$006D1360[0], 1; + %assign V_$006D0E18[0], 0, 32; + %load/v 32, V_$006CCC20[0], 5; + %cmpi/u 32, 17, 5; + %jmp/1 T_30.0, 6; + %cmpi/u 32, 18, 5; + %jmp/1 T_30.1, 6; + %cmpi/u 32, 0, 5; + %jmp/1 T_30.2, 6; + %cmpi/u 32, 1, 5; + %jmp/1 T_30.3, 6; + %cmpi/u 32, 2, 5; + %jmp/1 T_30.4, 6; + %cmpi/u 32, 3, 5; + %jmp/1 T_30.5, 6; + %cmpi/u 32, 4, 5; + %jmp/1 T_30.6, 6; + %cmpi/u 32, 5, 5; + %jmp/1 T_30.7, 6; + %cmpi/u 32, 6, 5; + %jmp/1 T_30.8, 6; + %cmpi/u 32, 7, 5; + %jmp/1 T_30.9, 6; + %cmpi/u 32, 8, 5; + %jmp/1 T_30.10, 6; + %cmpi/u 32, 9, 5; + %jmp/1 T_30.11, 6; + %cmpi/u 32, 10, 5; + %jmp/1 T_30.12, 6; + %cmpi/u 32, 11, 5; + %jmp/1 T_30.13, 6; + %cmpi/u 32, 12, 5; + %jmp/1 T_30.14, 6; + %cmpi/u 32, 13, 5; + %jmp/1 T_30.15, 6; + %cmpi/u 32, 14, 5; + %jmp/1 T_30.16, 6; + %cmpi/u 32, 15, 5; + %jmp/1 T_30.17, 6; + %cmpi/u 32, 16, 5; + %jmp/1 T_30.18, 6; + %cmpi/u 32, 19, 5; + %jmp/1 T_30.19, 6; + %jmp T_30.20; +T_30.0 ; + %assign V_$006D0E18[0], 0, 1; + %load/v 32, V_$006D1398[0], 1; + %jmp/0xz T_30.21, 32; + %ix/load 0, 4; + %assign/v0 V_$006CCD78[0], 0, 1; + %assign V_$006CCD78[4], 0, 0; + %assign V_$006D0E18[0], 0, 0; + %assign V_$006D0488[0], 0, 0; +T_30.21 ; + %jmp T_30.20; +T_30.1 ; + %assign V_$006D0E18[0], 0, 0; + %assign V_$006D0AC0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 0; + %assign V_$006D04F0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D01A8[0], 0, 0; + %assign V_$006D0488[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006D0F08[0], 0, 0; + %assign V_$006CCD78[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006CCD78[1], 0, 0; + %assign V_$006CCD78[4], 0, 1; + %jmp T_30.20; +T_30.2 ; + %assign V_$006D0AC0[0], 0, 0; + %assign V_$006CCD78[0], 0, 0; + %assign V_$006CCD78[1], 0, 1; + %assign V_$006CCD78[2], 0, 0; + %assign V_$006CCD78[3], 0, 1; + %assign V_$006CCD78[4], 0, 0; + %jmp T_30.20; +T_30.3 ; + %load 32, V_$006D1610[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_30.23, 4; + %ix/load 0, 5; + %assign/v0 V_$006CCD78[0], 0, 0; + %load/v 32, V_$006CE7B0[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 32; + %assign V_$006D0AC0[0], 0, 1; +T_30.23 ; + %jmp T_30.20; +T_30.4 ; + %ix/load 0, 4; + %assign/v0 V_$006CCD78[0], 0, 0; + %assign V_$006CCD78[4], 0, 1; + %jmp T_30.20; +T_30.5 ; + %assign V_$006D0AC0[0], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006CCD78[0], 0, 0; + %assign V_$006CCD78[3], 0, 1; + %assign V_$006CCD78[4], 0, 0; + %jmp T_30.20; +T_30.6 ; + %assign V_$006D0AC0[0], 0, 0; + %assign V_$006CCD78[0], 0, 1; + %ix/load 0, 4; + %assign/v0 V_$006CCD78[1], 0, 0; + %jmp T_30.20; +T_30.7 ; + %assign V_$006CCD78[0], 0, 1; + %assign V_$006CCD78[1], 0, 1; + %assign V_$006CCD78[2], 0, 0; + %assign V_$006CCD78[3], 0, 0; + %assign V_$006CCD78[4], 0, 1; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 1; + %assign V_$006D0AC0[0], 0, 1; + %load/v 32, V_$006D14A8[0], 10; + %addi 32, 1, 10; + %ix/load 0, 10; + %assign/v0 V_$006D0F08[0], 0, 32; + %assign V_$006D04F0[0], 0, 1; + %jmp T_30.20; +T_30.8 ; + %load 32, V_$006D12B0[0]; + %jmp/0xz T_30.25, 32; + %ix/load 0, 3; + %assign/v0 V_$006CCD78[0], 0, 1; + %assign V_$006CCD78[3], 0, 0; + %assign V_$006CCD78[4], 0, 0; + %load 32, V_$006D1150[0]; + %load 33, V_$006D1150[1]; + %load 34, V_$006D1150[2]; + %load 35, V_$006D1150[3]; + %load 36, V_$006D1150[4]; + %load 37, V_$006D1150[5]; + %load 38, V_$006D1150[6]; + %load 39, V_$006D1150[7]; + %ix/load 0, 8; + %assign/v0 V_$006D01A8[0], 0, 32; +T_30.25 ; + %jmp T_30.20; +T_30.9 ; + %load/v 32, V_$006D14A8[0], 10; + %cmpi/u 32, 512, 10; + %jmp/0xz T_30.27, 4; + %assign V_$006CCD78[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006CCD78[1], 0, 0; + %assign V_$006CCD78[4], 0, 1; + %assign V_$006D0488[0], 0, 1; + %jmp T_30.28; +T_30.27 ; + %load/v 32, V_$006D0B40[7], 1; + %cmpi/u 32, 0, 1; + %jmp/0xz T_30.29, 4; + %assign V_$006CCD78[0], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006CCD78[1], 0, 0; + %assign V_$006CCD78[4], 0, 1; + %jmp T_30.30; +T_30.29 ; + %assign V_$006CCD78[0], 0, 1; + %assign V_$006CCD78[1], 0, 0; + %assign V_$006CCD78[2], 0, 1; + %assign V_$006CCD78[3], 0, 0; + %assign V_$006CCD78[4], 0, 0; +T_30.30 ; +T_30.28 ; + %jmp T_30.20; +T_30.10 ; + %load 32, V_$006D1610[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_30.31, 4; + %assign V_$006CCD78[0], 0, 0; + %assign V_$006CCD78[1], 0, 0; + %assign V_$006CCD78[2], 0, 1; + %assign V_$006CCD78[3], 0, 0; + %assign V_$006CCD78[4], 0, 0; + %load/v 32, V_$006CE188[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 32; + %assign V_$006D0AC0[0], 0, 1; +T_30.31 ; + %jmp T_30.20; +T_30.11 ; + %assign V_$006D0AC0[0], 0, 0; + %assign V_$006CCD78[0], 0, 0; + %assign V_$006CCD78[1], 0, 0; + %assign V_$006CCD78[2], 0, 1; + %assign V_$006CCD78[3], 0, 1; + %assign V_$006CCD78[4], 0, 0; + %jmp T_30.20; +T_30.12 ; + %load 32, V_$006D1610[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_30.33, 4; + %assign V_$006CCD78[0], 0, 1; + %assign V_$006CCD78[1], 0, 0; + %assign V_$006CCD78[2], 0, 0; + %assign V_$006CCD78[3], 0, 1; + %assign V_$006CCD78[4], 0, 0; + %load/v 32, V_$006CF158[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 32; + %assign V_$006D0AC0[0], 0, 1; +T_30.33 ; + %jmp T_30.20; +T_30.13 ; + %assign V_$006D0AC0[0], 0, 0; + %assign V_$006CCD78[0], 0, 0; + %ix/load 0, 3; + %assign/v0 V_$006CCD78[1], 0, 1; + %assign V_$006CCD78[4], 0, 0; + %jmp T_30.20; +T_30.14 ; + %load 32, V_$006D1610[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_30.35, 4; + %assign V_$006CCD78[0], 0, 1; + %assign V_$006CCD78[1], 0, 1; + %assign V_$006CCD78[2], 0, 0; + %assign V_$006CCD78[3], 0, 1; + %assign V_$006CCD78[4], 0, 0; + %load/v 32, V_$006CF750[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 32; + %assign V_$006D0AC0[0], 0, 1; +T_30.35 ; + %jmp T_30.20; +T_30.15 ; + %assign V_$006D0AC0[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006D0F08[0], 0, 0; + %load 32, V_$006D15B8[0]; + %jmp/0xz T_30.37, 32; + %assign V_$006CCD78[0], 0, 1; + %assign V_$006CCD78[1], 0, 0; + %assign V_$006CCD78[2], 0, 1; + %assign V_$006CCD78[3], 0, 0; + %assign V_$006CCD78[4], 0, 0; +T_30.37 ; + %jmp T_30.20; +T_30.16 ; + %load 32, V_$006D1610[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_30.39, 4; + %assign V_$006CCD78[0], 0, 1; + %assign V_$006CCD78[1], 0, 0; + %assign V_$006CCD78[2], 0, 1; + %assign V_$006CCD78[3], 0, 1; + %assign V_$006CCD78[4], 0, 0; + %load/v 32, V_$006CD0D8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 32; + %assign V_$006D0AC0[0], 0, 1; +T_30.39 ; + %jmp T_30.20; +T_30.17 ; + %load 32, V_$006D1610[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_30.41, 4; + %assign V_$006CCD78[0], 0, 0; + %assign V_$006CCD78[1], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006CCD78[2], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 1; + %assign V_$006D0AC0[0], 0, 1; +T_30.41 ; + %jmp T_30.20; +T_30.18 ; + %assign V_$006D0AC0[0], 0, 0; + %load 32, V_$006D1610[0]; + %cmpi/u 32, 0, 1; + %jmp/0xz T_30.43, 4; + %assign V_$006CCD78[0], 0, 1; + %assign V_$006CCD78[1], 0, 1; + %ix/load 0, 3; + %assign/v0 V_$006CCD78[2], 0, 0; + %load/v 32, V_$006CD788[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D07C0[0], 0, 32; + %assign V_$006D0AC0[0], 0, 1; +T_30.43 ; + %jmp T_30.20; +T_30.19 ; + %assign V_$006CCD78[0], 0, 0; + %assign V_$006CCD78[1], 0, 1; + %assign V_$006CCD78[2], 0, 1; + %assign V_$006CCD78[3], 0, 0; + %assign V_$006CCD78[4], 0, 0; + %assign V_$006D0AC0[0], 0, 0; + %assign V_$006D04F0[0], 0, 0; + %jmp T_30.20; +T_30.20 ; + %jmp T_30; + .thread T_30, $push; + .scope S_006CC9E8; +T_31 ; + %wait E_003DE478; + %load 32, V_$006D1090[0]; + %jmp/0xz T_31.0, 32; + %assign V_$006CCC20[0], 0, 0; + %assign V_$006CCC20[1], 0, 1; + %assign V_$006CCC20[2], 0, 0; + %assign V_$006CCC20[3], 0, 0; + %assign V_$006CCC20[4], 0, 1; + %jmp T_31.1; +T_31.0 ; + %load/v 32, V_$006CCD78[0], 5; + %ix/load 0, 5; + %assign/v0 V_$006CCC20[0], 0, 32; +T_31.1 ; + %jmp T_31; + .thread T_31; + .scope S_006CC9E8; +T_32 ; + %wait E_003DE478; + %load 32, V_$006D1090[0]; + %jmp/0xz T_32.0, 32; + %assign V_$006D17B8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D1678[0], 0, 0; + %assign V_$006D1308[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006D0B40[0], 0, 0; + %assign V_$006D1010[0], 0, 0; + %assign V_$006D1360[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006D14A8[0], 0, 0; + %jmp T_32.1; +T_32.0 ; + %load/v 32, V_$006D0AC0[0], 1; + %assign V_$006D17B8[0], 0, 32; + %load/v 32, V_$006D07C0[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D1678[0], 0, 32; + %load/v 32, V_$006D04F0[0], 1; + %assign V_$006D1308[0], 0, 32; + %load/v 32, V_$006D01A8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006D0B40[0], 0, 32; + %load/v 32, V_$006D0488[0], 1; + %assign V_$006D1010[0], 0, 32; + %load/v 32, V_$006D0E18[0], 1; + %assign V_$006D1360[0], 0, 32; + %load/v 32, V_$006D0F08[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006D14A8[0], 0, 32; +T_32.1 ; + %jmp T_32; + .thread T_32; + .scope S_006CABC8; +T_33 ; + %wait E_003DE478; + %load 32, V_$006CBE80[0]; + %jmp/0xz T_33.0, 32; + %ix/load 0, 8; + %assign/v0 V_$006CC858[0], 0, 0; + %assign V_$006CC7A8[0], 0, 0; + %jmp T_33.1; +T_33.0 ; + %load 32, V_$006CBD38[0]; + %jmp/0xz T_33.2, 32; + %load 32, V_$006CBA78[0]; + %load 33, V_$006CBA78[1]; + %load 34, V_$006CBA78[2]; + %load 35, V_$006CBA78[3]; + %load 36, V_$006CBA78[4]; + %load 37, V_$006CBA78[5]; + %load 38, V_$006CBA78[6]; + %load 39, V_$006CBA78[7]; + %ix/load 0, 8; + %assign/v0 V_$006CC858[0], 0, 32; + %assign V_$006CC7A8[0], 0, 1; + %jmp T_33.3; +T_33.2 ; + %load 32, V_$006CBAB0[0]; + %jmp/0xz T_33.4, 32; + %load 32, V_$006CC038[0]; + %load 33, V_$006CC038[1]; + %load 34, V_$006CC038[2]; + %load 35, V_$006CC038[3]; + %load 36, V_$006CC038[4]; + %load 37, V_$006CC038[5]; + %load 38, V_$006CC038[6]; + %load 39, V_$006CC038[7]; + %ix/load 0, 8; + %assign/v0 V_$006CC858[0], 0, 32; + %assign V_$006CC7A8[0], 0, 1; + %jmp T_33.5; +T_33.4 ; + %load 32, V_$006CCE78[0]; + %jmp/0xz T_33.6, 32; + %load 32, V_$006CC2F8[0]; + %load 33, V_$006CC2F8[1]; + %load 34, V_$006CC2F8[2]; + %load 35, V_$006CC2F8[3]; + %load 36, V_$006CC2F8[4]; + %load 37, V_$006CC2F8[5]; + %load 38, V_$006CC2F8[6]; + %load 39, V_$006CC2F8[7]; + %ix/load 0, 8; + %assign/v0 V_$006CC858[0], 0, 32; + %assign V_$006CC7A8[0], 0, 1; + %jmp T_33.7; +T_33.6 ; + %load 32, V_$006CC720[0]; + %jmp/0xz T_33.8, 32; + %load 32, V_$006CCF00[0]; + %load 33, V_$006CCF00[1]; + %load 34, V_$006CCF00[2]; + %load 35, V_$006CCF00[3]; + %load 36, V_$006CCF00[4]; + %load 37, V_$006CCF00[5]; + %load 38, V_$006CCF00[6]; + %load 39, V_$006CCF00[7]; + %ix/load 0, 8; + %assign/v0 V_$006CC858[0], 0, 32; + %assign V_$006CC7A8[0], 0, 1; +T_33.8 ; +T_33.7 ; +T_33.5 ; +T_33.3 ; + %load 32, V_$006CC800[0]; + %jmp/0xz T_33.10, 32; + %assign V_$006CC7A8[0], 0, 0; +T_33.10 ; +T_33.1 ; + %jmp T_33; + .thread T_33; + .scope S_006CABC8; +T_34 ; + %wait E_003DE478; + %load 32, V_$006CBE80[0]; + %jmp/0xz T_34.0, 32; + %ix/load 0, 8; + %assign/v0 V_$006CB750[0], 0, 0; + %assign V_$006CB9B8[0], 0, 0; + %jmp T_34.1; +T_34.0 ; + %load 32, V_$006CBEB8[0]; + %load 33, V_$006CBF60[0]; + %or 32, 33, 1; + %load 33, V_$006CB4F8[0]; + %or 32, 33, 1; + %load 33, V_$006CB568[0]; + %or 32, 33, 1; + %jmp/0xz T_34.2, 32; + %assign V_$006CB9B8[0], 0, 0; +T_34.2 ; + %load 32, V_$006CBA20[0]; + %jmp/0xz T_34.4, 32; + %assign V_$006CB9B8[0], 0, 1; + %load 32, V_$006CB5F0[0]; + %load 33, V_$006CB5F0[1]; + %load 34, V_$006CB5F0[2]; + %load 35, V_$006CB5F0[3]; + %load 36, V_$006CB5F0[4]; + %load 37, V_$006CB5F0[5]; + %load 38, V_$006CB5F0[6]; + %load 39, V_$006CB5F0[7]; + %ix/load 0, 8; + %assign/v0 V_$006CB750[0], 0, 32; +T_34.4 ; +T_34.1 ; + %jmp T_34; + .thread T_34; + .scope S_006C9128; +T_35 ; + %wait E_006C8530; + %load/v 32, V_$006C9298[0], 2; + %assign V_$006C92D0[0], 0, 32; + %assign V_$006C92D0[1], 0, 33; + %load/v 32, V_$006CA688[0], 1; + %assign V_$006C9938[0], 0, 32; + %load/v 32, V_$006CAB30[0], 1; + %assign V_$006C99F8[0], 0, 32; + %load/v 32, V_$006CB278[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006CA2F0[0], 0, 32; + %load/v 32, V_$006CA718[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006C99C0[0], 0, 32; + %load/v 32, V_$006C9BE0[0], 4; + %ix/load 0, 4; + %assign/v0 V_$006C9FA0[0], 0, 32; + %load/v 32, V_$006C9D00[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006C9440[0], 0, 32; + %load/v 32, V_$006CAC78[0], 1; + %assign V_$006CA268[0], 0, 32; + %load/v 32, V_$006CAA28[0], 1; + %assign V_$006CA118[0], 0, 32; + %load/v 32, V_$006CAAD8[0], 1; + %assign V_$006CA198[0], 0, 32; + %load/v 32, V_$006C90B8[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006C9660[0], 0, 32; + %load/v 32, V_$006C9298[0], 2; + %cmpi/u 32, 0, 2; + %jmp/1 T_35.0, 6; + %cmpi/u 32, 1, 2; + %jmp/1 T_35.1, 6; + %cmpi/u 32, 2, 2; + %jmp/1 T_35.2, 6; + %cmpi/u 32, 3, 2; + %jmp/1 T_35.3, 6; + %jmp T_35.4; +T_35.0 ; + %assign V_$006C9938[0], 0, 0; + %assign V_$006C99F8[0], 0, 1; + %load 32, V_$006CAB90[0]; + %jmp/0xz T_35.5, 32; + %assign V_$006C92D0[0], 0, 1; + %assign V_$006C92D0[1], 0, 0; + %load 32, V_$006CAD08[0]; + %load 33, V_$006CAD08[1]; + %load 34, V_$006CAD08[2]; + %load 35, V_$006CAD08[3]; + %load 36, V_$006CAD08[4]; + %load 37, V_$006CAD08[5]; + %load 38, V_$006CAD08[6]; + %load 39, V_$006CAD08[7]; + %ix/load 0, 8; + %assign/v0 V_$006CA2F0[0], 0, 32; + %ix/load 0, 8; + %assign/v0 V_$006C99C0[0], 0, 0; + %ix/load 0, 4; + %assign/v0 V_$006C9FA0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006C9440[0], 0, 0; + %assign V_$006CA268[0], 0, 1; + %assign V_$006C99F8[0], 0, 0; +T_35.5 ; + %jmp T_35.4; +T_35.1 ; + %load/v 32, V_$006C9D00[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006C9440[0], 0, 32; + %assign V_$006CA268[0], 0, 0; + %assign V_$006C9938[0], 0, 0; + %load/v 32, V_$006C9D00[0], 8; + %load 40, V_$006C9CC8[0]; + %load 41, V_$006C9CC8[1]; + %load 42, V_$006C9CC8[2]; + %load 43, V_$006C9CC8[3]; + %load 44, V_$006C9CC8[4]; + %load 45, V_$006C9CC8[5]; + %load 46, V_$006C9CC8[6]; + %load 47, V_$006C9CC8[7]; + %cmp/u 32, 40, 8; + %mov 32, 4, 1; + %jmp/0xz T_35.7, 32; + %assign V_$006C92D0[0], 0, 0; + %assign V_$006C92D0[1], 0, 1; + %assign V_$006CA118[0], 0, 0; + %load/v 32, V_$006CB278[7], 1; + %assign V_$006CA198[0], 0, 32; + %mov 32, 0, 1; + %load/v 33, V_$006CB278[0], 7; + %ix/load 0, 8; + %assign/v0 V_$006CA2F0[0], 0, 32; + %ix/load 0, 8; + %assign/v0 V_$006C9440[0], 0, 0; +T_35.7 ; + %jmp T_35.4; +T_35.2 ; + %load/v 32, V_$006C9D00[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006C9440[0], 0, 32; + %load/v 32, V_$006C9BE0[0], 4; + %cmpi/u 32, 8, 4; + %mov 32, 4, 1; + %load 33, V_$006CAB90[0]; + %and 32, 33, 1; + %jmp/0xz T_35.9, 32; + %assign V_$006C92D0[0], 0, 1; + %assign V_$006C92D0[1], 0, 0; + %assign V_$006C9938[0], 0, 1; + %load/v 32, V_$006CA718[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006C9660[0], 0, 32; + %load 32, V_$006CAD08[0]; + %load 33, V_$006CAD08[1]; + %load 34, V_$006CAD08[2]; + %load 35, V_$006CAD08[3]; + %load 36, V_$006CAD08[4]; + %load 37, V_$006CAD08[5]; + %load 38, V_$006CAD08[6]; + %load 39, V_$006CAD08[7]; + %ix/load 0, 8; + %assign/v0 V_$006CA2F0[0], 0, 32; + %ix/load 0, 4; + %assign/v0 V_$006C9FA0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006C9440[0], 0, 0; + %assign V_$006CA268[0], 0, 1; + %jmp T_35.10; +T_35.9 ; + %load/v 32, V_$006C9BE0[0], 4; + %cmpi/u 32, 8, 4; + %jmp/0xz T_35.11, 4; + %assign V_$006C92D0[0], 0, 0; + %assign V_$006C92D0[1], 0, 0; + %assign V_$006C9938[0], 0, 1; + %load/v 32, V_$006CA718[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006C9660[0], 0, 32; + %jmp T_35.12; +T_35.11 ; + %load/v 32, V_$006C9D00[0], 8; + %load 40, V_$006C9CC8[0]; + %load 41, V_$006C9CC8[1]; + %load 42, V_$006C9CC8[2]; + %load 43, V_$006C9CC8[3]; + %load 44, V_$006C9CC8[4]; + %load 45, V_$006C9CC8[5]; + %load 46, V_$006C9CC8[6]; + %load 47, V_$006C9CC8[7]; + %cmp/u 32, 40, 8; + %mov 32, 4, 1; + %jmp/0xz T_35.13, 32; + %assign V_$006C92D0[0], 0, 1; + %assign V_$006C92D0[1], 0, 0; + %assign V_$006CA118[0], 0, 1; + %load/v 32, V_$006C9BE0[0], 4; + %addi 32, 1, 4; + %ix/load 0, 4; + %assign/v0 V_$006C9FA0[0], 0, 32; + %ix/load 0, 8; + %assign/v0 V_$006C9440[0], 0, 0; + %load 32, V_$006CAA80[0]; + %load/v 33, V_$006CA718[0], 7; + %ix/load 0, 8; + %assign/v0 V_$006C99C0[0], 0, 32; +T_35.13 ; +T_35.12 ; +T_35.10 ; + %jmp T_35.4; +T_35.3 ; + %ix/load 0, 4; + %assign/v0 V_$006C9FA0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006C9440[0], 0, 0; + %assign V_$006CA268[0], 0, 0; + %assign V_$006C9938[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006CA2F0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006C99C0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006C9660[0], 0, 0; + %assign V_$006CA198[0], 0, 0; + %assign V_$006CA118[0], 0, 0; + %assign V_$006C99F8[0], 0, 0; + %assign V_$006C92D0[0], 0, 0; + %assign V_$006C92D0[1], 0, 0; + %jmp T_35.4; +T_35.4 ; + %jmp T_35; + .thread T_35, $push; + .scope S_006C9128; +T_36 ; + %wait E_003DE478; + %load 32, V_$006CAEC0[0]; + %jmp/0xz T_36.0, 32; + %assign V_$006C9298[0], 0, 1; + %assign V_$006C9298[1], 0, 1; + %jmp T_36.1; +T_36.0 ; + %load/v 32, V_$006C92D0[0], 2; + %assign V_$006C9298[0], 0, 32; + %assign V_$006C9298[1], 0, 33; +T_36.1 ; + %jmp T_36; + .thread T_36; + .scope S_006C9128; +T_37 ; + %wait E_003DE478; + %load 32, V_$006CAEC0[0]; + %jmp/0xz T_37.0, 32; + %assign V_$006CA688[0], 0, 0; + %assign V_$006CAB30[0], 0, 0; + %assign V_$006CAC78[0], 0, 0; + %assign V_$006CAA28[0], 0, 0; + %assign V_$006CAAD8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006C90B8[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006CB278[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006CA718[0], 0, 0; + %ix/load 0, 4; + %assign/v0 V_$006C9BE0[0], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006C9D00[0], 0, 0; + %jmp T_37.1; +T_37.0 ; + %load/v 32, V_$006C9938[0], 1; + %assign V_$006CA688[0], 0, 32; + %load/v 32, V_$006C99F8[0], 1; + %assign V_$006CAB30[0], 0, 32; + %load/v 32, V_$006CA268[0], 1; + %assign V_$006CAC78[0], 0, 32; + %load/v 32, V_$006CA118[0], 1; + %assign V_$006CAA28[0], 0, 32; + %load/v 32, V_$006CA198[0], 1; + %assign V_$006CAAD8[0], 0, 32; + %load/v 32, V_$006C9660[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006C90B8[0], 0, 32; + %load/v 32, V_$006CA2F0[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006CB278[0], 0, 32; + %load/v 32, V_$006C99C0[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006CA718[0], 0, 32; + %load/v 32, V_$006C9FA0[0], 4; + %ix/load 0, 4; + %assign/v0 V_$006C9BE0[0], 0, 32; + %load/v 32, V_$006C9440[0], 8; + %ix/load 0, 8; + %assign/v0 V_$006C9D00[0], 0, 32; +T_37.1 ; + %jmp T_37; + .thread T_37; + .scope S_006C5C68; +T_38 ; + %wait E_003DE478; + %load 32, V_$006C6048[0]; + %load 33, V_$006C6048[1]; + %load 34, V_$006C6048[2]; + %load 35, V_$006C6048[3]; + %load 36, V_$006C6048[4]; + %load 37, V_$006C6048[5]; + %load 38, V_$006C6048[6]; + %load 39, V_$006C6048[7]; + %load 40, V_$006C6048[8]; + %ix/get 3, 32, 9; + %ix/mul 3, 8; + %load/m 32, M_$006C68E0; + %ix/add 3, 1; + %load/m 33, M_$006C68E0; + %ix/add 3, 1; + %load/m 34, M_$006C68E0; + %ix/add 3, 1; + %load/m 35, M_$006C68E0; + %ix/add 3, 1; + %load/m 36, M_$006C68E0; + %ix/add 3, 1; + %load/m 37, M_$006C68E0; + %ix/add 3, 1; + %load/m 38, M_$006C68E0; + %ix/add 3, 1; + %load/m 39, M_$006C68E0; + %ix/load 0, 8; + %assign/v0 V_$006C53E0[0], 0, 32; + %jmp T_38; + .thread T_38; + .scope S_006C5C68; +T_39 ; + %wait E_003DE0F8; + %load 32, V_$006C5300[0]; + %jmp/0xz T_39.0, 32; + %load 32, V_$006C6340[0]; + %load 33, V_$006C6340[1]; + %load 34, V_$006C6340[2]; + %load 35, V_$006C6340[3]; + %load 36, V_$006C6340[4]; + %load 37, V_$006C6340[5]; + %load 38, V_$006C6340[6]; + %load 39, V_$006C6340[7]; + %load 40, V_$006C5B38[0]; + %load 41, V_$006C5B38[1]; + %load 42, V_$006C5B38[2]; + %load 43, V_$006C5B38[3]; + %load 44, V_$006C5B38[4]; + %load 45, V_$006C5B38[5]; + %load 46, V_$006C5B38[6]; + %load 47, V_$006C5B38[7]; + %load 48, V_$006C5B38[8]; + %ix/get 3, 40, 9; + %ix/mul 3, 8; + %jmp/1 t_833, 4; + %assign/m M_$006C68E0, 0, 32; + %ix/add 3, 1; + %assign/m M_$006C68E0, 0, 33; + %ix/add 3, 1; + %assign/m M_$006C68E0, 0, 34; + %ix/add 3, 1; + %assign/m M_$006C68E0, 0, 35; + %ix/add 3, 1; + %assign/m M_$006C68E0, 0, 36; + %ix/add 3, 1; + %assign/m M_$006C68E0, 0, 37; + %ix/add 3, 1; + %assign/m M_$006C68E0, 0, 38; + %ix/add 3, 1; + %assign/m M_$006C68E0, 0, 39; +t_833 ; +T_39.0 ; + %jmp T_39; + .thread T_39; + .scope S_006C5A78; +T_40 ; + %wait E_003DE0F8; + %load/v 32, V_$006C73C8[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006C7F50[0], 0, 32; + %load 32, V_$006C8618[0]; + %load 33, V_$006C8210[0]; + %or 32, 33, 1; + %jmp/0xz T_40.0, 32; + %assign V_$006C8098[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006C5290[0], 0, 0; + %jmp T_40.1; +T_40.0 ; + %load 32, V_$006C81A0[0]; + %jmp/0xz T_40.2, 32; + %load/v 32, V_$006C5290[0], 10; + %addi 32, 1, 10; + %ix/load 0, 10; + %assign/v0 V_$006C5290[0], 0, 32; +T_40.2 ; + %load/v 32, V_$006C7F50[0], 9; + %load/v 41, V_$006C5290[0], 9; + %cmp/u 32, 41, 9; + %mov 32, 4, 1; + %load/v 33, V_$006C7F50[9], 1; + %load/v 34, V_$006C5290[9], 1; + %cmp/u 33, 34, 1; + %inv 4, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_40.4, 32; + %assign V_$006C8098[0], 0, 1; + %jmp T_40.5; +T_40.4 ; + %assign V_$006C8098[0], 0, 0; +T_40.5 ; +T_40.1 ; + %jmp T_40; + .thread T_40; + .scope S_006C5A78; +T_41 ; + %wait E_003DDD60; + %load/v 32, V_$006C5258[0], 10; + %load/v 42, V_$006C73C8[0], 10; + %sub 32, 42, 10; + %ix/load 0, 10; + %assign/v0 V_$006C52C8[0], 0, 32; + %jmp T_41; + .thread T_41, $push; + .scope S_006C5A78; +T_42 ; + %wait E_003DE478; + %load/v 32, V_$006C52C8[0], 10; + %mov 42, 0, 8; + %ix/load 0, 16; + %assign/v0 V_$006C82B8[0], 0, 32; + %load/v 32, V_$006C5290[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006C5258[0], 0, 32; + %load 32, V_$006C85E0[0]; + %load 33, V_$006C81D8[0]; + %or 32, 33, 1; + %jmp/0xz T_42.0, 32; + %assign V_$006C7FF8[0], 0, 1; + %ix/load 0, 10; + %assign/v0 V_$006C73C8[0], 0, 0; + %assign V_$006C8030[0], 0, 0; + %jmp T_42.1; +T_42.0 ; + %load 32, V_$006C8118[0]; + %assign V_$006C8030[0], 0, 32; + %load/v 33, V_$006C8030[0], 1; + %cmpi/u 33, 0, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_42.2, 32; + %load 32, V_$006C7978[0]; + %load 33, V_$006C7978[1]; + %load 34, V_$006C7978[2]; + %load 35, V_$006C7978[3]; + %load 36, V_$006C7978[4]; + %load 37, V_$006C7978[5]; + %load 38, V_$006C7978[6]; + %load 39, V_$006C7978[7]; + %ix/load 0, 8; + %assign/v0 V_$006C7CF0[0], 0, 32; + %load/v 32, V_$006C73C8[0], 10; + %addi 32, 1, 10; + %ix/load 0, 10; + %assign/v0 V_$006C73C8[0], 0, 32; +T_42.2 ; + %load/v 32, V_$006C5258[0], 10; + %load/v 42, V_$006C73C8[0], 10; + %cmp/u 32, 42, 10; + %mov 32, 4, 1; + %jmp/0xz T_42.4, 32; + %assign V_$006C7FF8[0], 0, 1; + %jmp T_42.5; +T_42.4 ; + %assign V_$006C7FF8[0], 0, 0; +T_42.5 ; +T_42.1 ; + %jmp T_42; + .thread T_42; + .scope S_006C5A78; +T_43 ; + %wait E_005F17F0; + %load/v 32, V_$006C5290[0], 9; + %ix/load 0, 9; + %assign/v0 V_$006C7270[0], 0, 32; + %load/v 32, V_$006C73C8[0], 9; + %ix/load 0, 9; + %assign/v0 V_$006C77D8[0], 0, 32; + %jmp T_43; + .thread T_43, $push; + .scope S_006C5098; +T_44 ; + %wait E_003DE0F8; + %load 32, V_$006C5A08[0]; + %load 33, V_$006C5478[0]; + %and 32, 33, 1; + %load 33, V_$006C5060[0]; + %load 34, V_$006C5060[1]; + %load 35, V_$006C5060[2]; + %cmpi/u 33, 4, 3; + %mov 33, 4, 1; + %and 32, 33, 1; + %load 33, V_$006C4F40[0]; + %and 32, 33, 1; + %load 33, V_$006C51F8[0]; + %and 32, 33, 1; + %jmp/0xz T_44.0, 32; + %assign V_$006C54E8[0], 0, 1; + %jmp T_44.1; +T_44.0 ; + %assign V_$006C54E8[0], 0, 0; +T_44.1 ; + %jmp T_44; + .thread T_44; + .scope S_006C5098; +T_45 ; + %wait E_003DE0F8; + %load 32, V_$006C58F0[0]; + %jmp/0xz T_45.0, 32; + %ix/load 0, 6; + %assign/v0 V_$006C5548[0], 0, 0; + %jmp T_45.1; +T_45.0 ; + %load/v 32, V_$006C54E8[0], 1; + %jmp/0xz T_45.2, 32; + %ix/load 0, 6; + %assign/v0 V_$006C5548[0], 0, 1; + %jmp T_45.3; +T_45.2 ; + %load/v 32, V_$006C5548[1], 5; + %mov 37, 0, 1; + %ix/load 0, 6; + %assign/v0 V_$006C5548[0], 0, 32; +T_45.3 ; +T_45.1 ; + %jmp T_45; + .thread T_45; + .scope S_006C5098; +T_46 ; + %wait E_003DE478; + %load 32, V_$006C5580[0]; + %assign V_$006C55F0[0], 0, 32; + %load/v 32, V_$006C55F0[0], 1; + %assign V_$006C55B8[0], 0, 32; + %jmp T_46; + .thread T_46; + .scope S_006C5098; +T_47 ; + %wait E_006C45B0; + %load 32, V_$006C5060[0]; + %load 33, V_$006C5060[1]; + %load 34, V_$006C5060[2]; + %cmpi/u 32, 0, 3; + %mov 32, 4, 1; + %load 33, V_$006C5A08[0]; + %and 32, 33, 1; + %load 33, V_$006C4F40[0]; + %and 32, 33, 1; + %load 33, V_$006C5478[0]; + %and 32, 33, 1; + %jmp/0xz T_47.0, 32; + %assign V_$006C54B0[0], 0, 1; + %jmp T_47.1; +T_47.0 ; + %assign V_$006C54B0[0], 0, 0; +T_47.1 ; + %jmp T_47; + .thread T_47, $push; + .scope S_006C2228; +T_48 ; + %wait E_003DE0F8; + %load 32, V_$006AC4E0[0]; + %load 33, V_$006AC4E0[1]; + %load 34, V_$006AC4E0[2]; + %load 35, V_$006AC4E0[3]; + %load 36, V_$006AC4E0[4]; + %load 37, V_$006AC4E0[5]; + %load 38, V_$006AC4E0[6]; + %load 39, V_$006AC4E0[7]; + %load 40, V_$006AC4E0[8]; + %ix/get 3, 32, 9; + %ix/mul 3, 8; + %load/m 32, M_$005D1E00; + %ix/add 3, 1; + %load/m 33, M_$005D1E00; + %ix/add 3, 1; + %load/m 34, M_$005D1E00; + %ix/add 3, 1; + %load/m 35, M_$005D1E00; + %ix/add 3, 1; + %load/m 36, M_$005D1E00; + %ix/add 3, 1; + %load/m 37, M_$005D1E00; + %ix/add 3, 1; + %load/m 38, M_$005D1E00; + %ix/add 3, 1; + %load/m 39, M_$005D1E00; + %ix/load 0, 8; + %assign/v0 V_$00639738[0], 0, 32; + %jmp T_48; + .thread T_48; + .scope S_006C2228; +T_49 ; + %wait E_003DE478; + %load 32, V_$006C27D8[0]; + %jmp/0xz T_49.0, 32; + %load 32, V_$006AD2C8[0]; + %load 33, V_$006AD2C8[1]; + %load 34, V_$006AD2C8[2]; + %load 35, V_$006AD2C8[3]; + %load 36, V_$006AD2C8[4]; + %load 37, V_$006AD2C8[5]; + %load 38, V_$006AD2C8[6]; + %load 39, V_$006AD2C8[7]; + %load 40, V_$006AC480[0]; + %load 41, V_$006AC480[1]; + %load 42, V_$006AC480[2]; + %load 43, V_$006AC480[3]; + %load 44, V_$006AC480[4]; + %load 45, V_$006AC480[5]; + %load 46, V_$006AC480[6]; + %load 47, V_$006AC480[7]; + %load 48, V_$006AC480[8]; + %ix/get 3, 40, 9; + %ix/mul 3, 8; + %jmp/1 t_863, 4; + %assign/m M_$005D1E00, 0, 32; + %ix/add 3, 1; + %assign/m M_$005D1E00, 0, 33; + %ix/add 3, 1; + %assign/m M_$005D1E00, 0, 34; + %ix/add 3, 1; + %assign/m M_$005D1E00, 0, 35; + %ix/add 3, 1; + %assign/m M_$005D1E00, 0, 36; + %ix/add 3, 1; + %assign/m M_$005D1E00, 0, 37; + %ix/add 3, 1; + %assign/m M_$005D1E00, 0, 38; + %ix/add 3, 1; + %assign/m M_$005D1E00, 0, 39; +t_863 ; +T_49.0 ; + %jmp T_49; + .thread T_49; + .scope S_006C2110; +T_50 ; + %wait E_003DE478; + %load/v 32, V_$006C3600[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006C3D38[0], 0, 32; + %load 32, V_$006C46F0[0]; + %load 33, V_$006C4360[0]; + %or 32, 33, 1; + %jmp/0xz T_50.0, 32; + %assign V_$006C4260[0], 0, 0; + %ix/load 0, 10; + %assign/v0 V_$006C2B10[0], 0, 0; + %jmp T_50.1; +T_50.0 ; + %load 32, V_$006C42D0[0]; + %jmp/0xz T_50.2, 32; + %load/v 32, V_$006C2B10[0], 10; + %addi 32, 1, 10; + %ix/load 0, 10; + %assign/v0 V_$006C2B10[0], 0, 32; +T_50.2 ; + %load/v 32, V_$006C3D38[0], 9; + %load/v 41, V_$006C2B10[0], 9; + %cmp/u 32, 41, 9; + %mov 32, 4, 1; + %load/v 33, V_$006C3D38[9], 1; + %load/v 34, V_$006C2B10[9], 1; + %cmp/u 33, 34, 1; + %inv 4, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_50.4, 32; + %assign V_$006C4260[0], 0, 1; + %jmp T_50.5; +T_50.4 ; + %assign V_$006C4260[0], 0, 0; +T_50.5 ; +T_50.1 ; + %jmp T_50; + .thread T_50; + .scope S_006C2110; +T_51 ; + %wait E_005EE048; + %load/v 32, V_$006C3170[0], 10; + %load/v 42, V_$006C3600[0], 10; + %sub 32, 42, 10; + %ix/load 0, 10; + %assign/v0 V_$006C2810[0], 0, 32; + %jmp T_51; + .thread T_51, $push; + .scope S_006C2110; +T_52 ; + %wait E_003DE0F8; + %load/v 32, V_$006C2810[0], 10; + %mov 42, 0, 8; + %ix/load 0, 16; + %assign/v0 V_$006C4398[0], 0, 32; + %load/v 32, V_$006C2B10[0], 10; + %ix/load 0, 10; + %assign/v0 V_$006C3170[0], 0, 32; + %load 32, V_$006C4698[0]; + %load 33, V_$006C4308[0]; + %or 32, 33, 1; + %jmp/0xz T_52.0, 32; + %assign V_$006C41F0[0], 0, 1; + %ix/load 0, 10; + %assign/v0 V_$006C3600[0], 0, 0; + %assign V_$006C4228[0], 0, 0; + %jmp T_52.1; +T_52.0 ; + %load 32, V_$006C4298[0]; + %assign V_$006C4228[0], 0, 32; + %load/v 33, V_$006C4228[0], 1; + %cmpi/u 33, 0, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %jmp/0xz T_52.2, 32; + %load 32, V_$006C3898[0]; + %load 33, V_$006C3898[1]; + %load 34, V_$006C3898[2]; + %load 35, V_$006C3898[3]; + %load 36, V_$006C3898[4]; + %load 37, V_$006C3898[5]; + %load 38, V_$006C3898[6]; + %load 39, V_$006C3898[7]; + %ix/load 0, 8; + %assign/v0 V_$006C4090[0], 0, 32; + %load/v 32, V_$006C3600[0], 10; + %addi 32, 1, 10; + %ix/load 0, 10; + %assign/v0 V_$006C3600[0], 0, 32; +T_52.2 ; + %load/v 32, V_$006C3170[0], 10; + %load/v 42, V_$006C3600[0], 10; + %cmp/u 32, 42, 10; + %mov 32, 4, 1; + %jmp/0xz T_52.4, 32; + %assign V_$006C41F0[0], 0, 1; + %jmp T_52.5; +T_52.4 ; + %assign V_$006C41F0[0], 0, 0; +T_52.5 ; +T_52.1 ; + %jmp T_52; + .thread T_52; + .scope S_006C2110; +T_53 ; + %wait E_005EEF18; + %load/v 32, V_$006C2B10[0], 9; + %ix/load 0, 9; + %assign/v0 V_$006C3508[0], 0, 32; + %load/v 32, V_$006C3600[0], 9; + %ix/load 0, 9; + %assign/v0 V_$006C3740[0], 0, 32; + %jmp T_53; + .thread T_53, $push; + .scope S_006C1658; +T_54 ; + %wait E_003DE0F8; + %load 32, V_$006685B0[0]; + %load 33, V_$006A7BA8[0]; + %and 32, 33, 1; + %load 33, V_$006A4EE8[0]; + %load 34, V_$006A4EE8[1]; + %load 35, V_$006A4EE8[2]; + %cmpi/u 33, 4, 3; + %mov 33, 4, 1; + %and 32, 33, 1; + %load 33, V_$006AA8A8[0]; + %and 32, 33, 1; + %load 33, V_$0065A890[0]; + %and 32, 33, 1; + %jmp/0xz T_54.0, 32; + %assign V_$006A7DD8[0], 0, 1; + %jmp T_54.1; +T_54.0 ; + %assign V_$006A7DD8[0], 0, 0; +T_54.1 ; + %jmp T_54; + .thread T_54; + .scope S_006C1658; +T_55 ; + %wait E_003DE0F8; + %load 32, V_$0065D6E8[0]; + %jmp/0xz T_55.0, 32; + %ix/load 0, 6; + %assign/v0 V_$00666B38[0], 0, 0; + %jmp T_55.1; +T_55.0 ; + %load/v 32, V_$006A7DD8[0], 1; + %jmp/0xz T_55.2, 32; + %ix/load 0, 6; + %assign/v0 V_$00666B38[0], 0, 1; + %jmp T_55.3; +T_55.2 ; + %load/v 32, V_$00666B38[1], 5; + %mov 37, 0, 1; + %ix/load 0, 6; + %assign/v0 V_$00666B38[0], 0, 32; +T_55.3 ; +T_55.1 ; + %jmp T_55; + .thread T_55; + .scope S_006C1658; +T_56 ; + %wait E_003DE478; + %load 32, V_$006A8D90[0]; + %assign V_$006A8850[0], 0, 32; + %load/v 32, V_$006A8850[0], 1; + %assign V_$006A9EA0[0], 0, 32; + %jmp T_56; + .thread T_56; + .scope S_006C1658; +T_57 ; + %wait E_003DDC30; + %load 32, V_$006A4EE8[0]; + %load 33, V_$006A4EE8[1]; + %load 34, V_$006A4EE8[2]; + %cmpi/u 32, 0, 3; + %jmp/1 T_57.0, 6; + %cmpi/u 32, 2, 3; + %jmp/1 T_57.1, 6; + %cmpi/u 32, 3, 3; + %jmp/1 T_57.2, 6; + %ix/load 0, 8; + %assign/v0 V_$006A5290[0], 0, 0; + %jmp T_57.4; +T_57.0 ; + %load 32, V_$00660078[0]; + %load 33, V_$00660078[1]; + %load 34, V_$00660078[2]; + %load 35, V_$00660078[3]; + %load 36, V_$00660078[4]; + %load 37, V_$00660078[5]; + %load 38, V_$00660078[6]; + %load 39, V_$00660078[7]; + %ix/load 0, 8; + %assign/v0 V_$006A5290[0], 0, 32; + %jmp T_57.4; +T_57.1 ; + %load 32, V_$00666678[8]; + %load 33, V_$00666678[9]; + %load 34, V_$00666678[10]; + %load 35, V_$00666678[11]; + %load 36, V_$00666678[12]; + %load 37, V_$00666678[13]; + %load 38, V_$00666678[14]; + %load 39, V_$00666678[15]; + %ix/load 0, 8; + %assign/v0 V_$006A5290[0], 0, 32; + %jmp T_57.4; +T_57.2 ; + %load 32, V_$00666678[0]; + %load 33, V_$00666678[1]; + %load 34, V_$00666678[2]; + %load 35, V_$00666678[3]; + %load 36, V_$00666678[4]; + %load 37, V_$00666678[5]; + %load 38, V_$00666678[6]; + %load 39, V_$00666678[7]; + %ix/load 0, 8; + %assign/v0 V_$006A5290[0], 0, 32; + %jmp T_57.4; +T_57.4 ; + %jmp T_57; + .thread T_57, $push; + .scope S_006C1658; +T_58 ; + %wait E_003DDB00; + %load 32, V_$006A4EE8[0]; + %load 33, V_$006A4EE8[1]; + %load 34, V_$006A4EE8[2]; + %cmpi/u 32, 0, 3; + %mov 32, 4, 1; + %load 33, V_$006685B0[0]; + %cmpi/u 33, 0, 1; + %mov 33, 4, 1; + %and 32, 33, 1; + %load 33, V_$006AA8A8[0]; + %and 32, 33, 1; + %load 33, V_$006A7BA8[0]; + %and 32, 33, 1; + %jmp/0xz T_58.0, 32; + %assign V_$006A76F0[0], 0, 1; + %jmp T_58.1; +T_58.0 ; + %assign V_$006A76F0[0], 0, 0; +T_58.1 ; + %jmp T_58; + .thread T_58, $push; + .scope S_00624D88; +T_59 ; + %set/v V_$0068AE60[0], 2, 8; + %set/v V_$0069AA18[0], 2, 8; + %set V_$0069A858[0], 0; + %set V_$006607B0[0], 2; + %set V_$006A5C98[0], 2; + %set V_$006A4238[0], 2; + %delay 1000; + %end; + .thread T_59; + .scope S_00633880; +T_60 ; + %set/v V_$006B08C8[0], 0, 2; + %end; + .thread T_60; + .scope S_00633880; +T_61 ; + %load/v 32, V_$006B08C8[0], 2; + %cmpi/u 32, 0, 2; + %jmp/1 T_61.0, 6; + %cmpi/u 32, 1, 2; + %jmp/1 T_61.1, 6; + %cmpi/u 32, 2, 2; + %jmp/1 T_61.2, 6; + %jmp T_61.3; +T_61.0 ; + %set/v V_$006B01E8[0], 1, 8; + %fork TD_testHarness.u_sdModel.txRxByte, S_006399E8; + %join; + %load/v 32, V_$006B00C0[0], 8; + %set/v V_$006B0718[0], 32, 8; + %load/v 32, V_$006B0718[0], 8; + %cmpi/u 32, 255, 8; + %jmp/0xz T_61.4, 4; + %assign V_$006B08C8[0], 0, 1; + %assign V_$006B08C8[1], 0, 0; + %ix/load 0, 8; + %assign/v0 V_$006B0438[0], 0, 0; +T_61.4 ; + %jmp T_61.3; +T_61.1 ; + %set/v V_$006B01E8[0], 1, 8; + %fork TD_testHarness.u_sdModel.txRxByte, S_006399E8; + %join; + %load/v 32, V_$006B00C0[0], 8; + %set/v V_$006B0718[0], 32, 8; + %load/v 32, V_$006B0718[0], 8; + %cmpi/u 32, 255, 8; + %jmp/0xz T_61.6, 4; + %load/v 32, V_$006B0438[0], 8; + %addi 32, 1, 8; + %ix/load 0, 8; + %assign/v0 V_$006B0438[0], 0, 32; + %load/v 32, V_$006B0438[0], 8; + %cmpi/u 32, 10, 8; + %jmp/0xz T_61.8, 4; + %load/v 32, V_$006B0578[0], 8; + %set/v V_$006B01E8[0], 32, 8; + %fork TD_testHarness.u_sdModel.txRxByte, S_006399E8; + %join; + %load/v 32, V_$006B00C0[0], 8; + %set/v V_$006B0718[0], 32, 8; + %assign V_$006B08C8[0], 0, 0; + %assign V_$006B08C8[1], 0, 1; +T_61.8 ; + %jmp T_61.7; +T_61.6 ; + %assign V_$006B08C8[0], 0, 0; + %assign V_$006B08C8[1], 0, 0; +T_61.7 ; + %jmp T_61.3; +T_61.2 ; + %set/v V_$006B01E8[0], 1, 8; + %fork TD_testHarness.u_sdModel.txRxByte, S_006399E8; + %join; + %load/v 32, V_$006B00C0[0], 8; + %set/v V_$006B0718[0], 32, 8; + %load/v 32, V_$006B0718[0], 8; + %cmpi/u 32, 255, 8; + %inv 4, 1; + %jmp/0xz T_61.10, 4; + %assign V_$006B08C8[0], 0, 0; + %assign V_$006B08C8[1], 0, 0; +T_61.10 ; + %jmp T_61.3; +T_61.3 ; + %jmp T_61; + .thread T_61; + .scope S_006338F0; +T_62 ; + %vpi_call "$dumpfile", "wave.vcd"; + %vpi_call "$dumpvars", 1'sb0, S_006C1500; + %end; + .thread T_62; + .scope S_006338F0; +T_63 ; + %wait E_003DE0F8; + %wait E_003DE0F8; + %wait E_003DE0F8; + %wait E_003DE0F8; + %wait E_003DE0F8; + %wait E_003DE0F8; + %wait E_003DE0F8; + %wait E_003DE0F8; + %assign V_$006E0BD0[0], 0, 1; + %wait E_003DE0F8; + %assign V_$006E0BD0[0], 0, 0; + %wait E_003DE0F8; + %end; + .thread T_63; + .scope S_006338F0; +T_64 ; + %delay 20000; + %assign V_$006DF4B8[0], 0, 0; + %delay 20000; + %assign V_$006DF4B8[0], 0, 1; + %jmp T_64; + .thread T_64; + .scope S_006338F0; +T_65 ; + %delay 10000; + %assign V_$006E3508[0], 0, 0; + %delay 10000; + %assign V_$006E3508[0], 0, 1; + %jmp T_65; + .thread T_65; diff --git a/usrp2/fpga/opencores/sd_interface/sim/wave.do b/usrp2/fpga/opencores/sd_interface/sim/wave.do new file mode 100644 index 00000000..0cc94b31 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/sim/wave.do @@ -0,0 +1,133 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider ctrlStsRegBI +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/dataIn +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/address +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/writeEn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/strobe_i +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/busClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiSysClk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/dataOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/ctrlStsRegSel +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransType +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatus +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessTxData +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessRxData +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstFromWire +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstSyncToBusClkOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstSyncToSpiClkOut +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDWriteError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDReadError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDInitError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDAddr +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiClkDelay +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/clk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstShift +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstFromBus +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessTxDataSTB +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiDirectAccessRxDataSTB +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransTypeSTB +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrlSTB +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatusSTB +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/rstSyncToSpiClkFirst +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrlShift +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatusReg1 +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransStatusReg2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDWriteErrorSTB +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDReadErrorSTB +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/SDInitErrorSTB +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl_reg1 +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl_reg2 +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_ctrlStsRegBI/spiTransCtrl_reg3 +add wave -noupdate -divider spiTxRxData +add wave -noupdate -divider readWriteSPIWireData +add wave -noupdate -divider spiCtrl +add wave -noupdate -divider initSD +add wave -noupdate -divider sendCmd +add wave -noupdate -divider sdModel +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiClk +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiDataIn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiDataOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_sdModel/spiCS_n +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/rxByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/respByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/smSt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_sdModel/cnt +add wave -noupdate -divider txFifo +add wave -noupdate -divider txFifoBI +add wave -noupdate -divider readWriteSDBlock +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/blockAddr +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/clk +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/readWriteSDBlockReq +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/respByte +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/respTout +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rst +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxDataIn +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxDataRdy +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/sendCmdRdy +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataEmpty +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataFull +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txFifoData +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/checkSumByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/cmdByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte1 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte3 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/dataByte4 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/readError +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/readWriteSDBlockRdy +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxDataRdyClr +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxFifoData +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/rxFifoWen +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/sendCmdReq +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/spiCS_n +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txDataWen +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/txFifoRen +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/writeError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_checkSumByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_cmdByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte1 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte3 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_dataByte4 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_readError +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_readWriteSDBlockRdy +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_rxDataRdyClr +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_rxFifoData +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_rxFifoWen +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_sendCmdReq +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_spiCS_n +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_txDataOut +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_txDataWen +add wave -noupdate -format Logic -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_txFifoRen +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_writeError +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/delCnt1 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_delCnt1 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/delCnt2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_delCnt2 +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/locRespByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_locRespByte +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/loopCnt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_loopCnt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/timeOutCnt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/next_timeOutCnt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/CurrState_rwBlkSt +add wave -noupdate -format Literal -radix hexadecimal /testHarness/u_spiMaster/u_readWriteSDBlock/NextState_rwBlkSt +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {717201000 ps} 0} {{Cursor 2} {102093853 ps} 0} +configure wave -namecolwidth 456 +configure wave -valuecolwidth 73 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {115986988 ps} diff --git a/usrp2/fpga/opencores/sd_interface/syn/spiMaster.qpf b/usrp2/fpga/opencores/sd_interface/syn/spiMaster.qpf new file mode 100644 index 00000000..f60b6c83 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/syn/spiMaster.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2007 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "7.2" +DATE = "14:03:18 February 21, 2008" + + +# Revisions + +PROJECT_REVISION = "spiMaster" diff --git a/usrp2/fpga/opencores/sd_interface/syn/spiMaster.qsf b/usrp2/fpga/opencores/sd_interface/syn/spiMaster.qsf new file mode 100644 index 00000000..3a5f8880 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/syn/spiMaster.qsf @@ -0,0 +1,57 @@ +# Copyright (C) 1991-2007 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# spiMaster_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20Q240C8 +set_global_assignment -name TOP_LEVEL_ENTITY spiMaster +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:03:18 FEBRUARY 21, 2008" +set_global_assignment -name LAST_QUARTUS_VERSION 7.2 +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace +set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 +set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBus_h.v +set_global_assignment -name VERILOG_FILE ../rtl/ctrlStsRegBI.v +set_global_assignment -name VERILOG_FILE ../rtl/dpMem_dc.v +set_global_assignment -name VERILOG_FILE ../rtl/fifoRTL.v +set_global_assignment -name VERILOG_FILE ../rtl/initSD.v +set_global_assignment -name VERILOG_FILE ../rtl/readWriteSDBlock.v +set_global_assignment -name VERILOG_FILE ../rtl/readWriteSPIWireData.v +set_global_assignment -name VERILOG_FILE ../rtl/RxFifo.v +set_global_assignment -name VERILOG_FILE ../rtl/RxFifoBI.v +set_global_assignment -name VERILOG_FILE ../rtl/sendCmd.v +set_global_assignment -name VERILOG_FILE ../rtl/spiCtrl.v +set_global_assignment -name VERILOG_FILE ../rtl/spiMaster.v +set_global_assignment -name VERILOG_FILE ../rtl/spiMaster_h.v +set_global_assignment -name VERILOG_FILE ../rtl/spiTxRxData.v +set_global_assignment -name VERILOG_FILE ../rtl/timescale.v +set_global_assignment -name VERILOG_FILE ../rtl/TxFifo.v +set_global_assignment -name VERILOG_FILE ../rtl/TxFifoBI.v +set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBI.v +set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" \ No newline at end of file diff --git a/usrp2/fpga/opencores/simple_gpio/CVS/Entries b/usrp2/fpga/opencores/simple_gpio/CVS/Entries new file mode 100644 index 00000000..df1462bb --- /dev/null +++ b/usrp2/fpga/opencores/simple_gpio/CVS/Entries @@ -0,0 +1 @@ +D/rtl//// diff --git a/usrp2/fpga/opencores/simple_gpio/CVS/Repository b/usrp2/fpga/opencores/simple_gpio/CVS/Repository new file mode 100644 index 00000000..b869a0de --- /dev/null +++ b/usrp2/fpga/opencores/simple_gpio/CVS/Repository @@ -0,0 +1 @@ +simple_gpio diff --git a/usrp2/fpga/opencores/simple_gpio/CVS/Root b/usrp2/fpga/opencores/simple_gpio/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/simple_gpio/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/simple_gpio/CVS/Template b/usrp2/fpga/opencores/simple_gpio/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Entries b/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Entries new file mode 100644 index 00000000..8c625813 --- /dev/null +++ b/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Entries @@ -0,0 +1,2 @@ +/simple_gpio.v/1.2/Sun Dec 22 16:10:17 2002// +D diff --git a/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Repository b/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Repository new file mode 100644 index 00000000..955303d8 --- /dev/null +++ b/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Repository @@ -0,0 +1 @@ +simple_gpio/rtl diff --git a/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Root b/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Template b/usrp2/fpga/opencores/simple_gpio/rtl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/simple_gpio/rtl/simple_gpio.v b/usrp2/fpga/opencores/simple_gpio/rtl/simple_gpio.v new file mode 100644 index 00000000..0b78f992 --- /dev/null +++ b/usrp2/fpga/opencores/simple_gpio/rtl/simple_gpio.v @@ -0,0 +1,193 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple General Purpose IO core //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: simple_gpio.v,v 1.2 2002/12/22 16:10:17 rherveille Exp $ +// +// $Date: 2002/12/22 16:10:17 $ +// $Revision: 1.2 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: simple_gpio.v,v $ +// Revision 1.2 2002/12/22 16:10:17 rherveille +// Fixed some typos in the documentation section. +// +// + + + +// +// Very basic 8bit GPIO core +// +// +// Registers: +// +// 0x00: Control Register +// bits 7:0 R/W Input/Output '1' = output mode +// '0' = input mode +// 0x01: Line Register +// bits 7:0 R Status Current GPIO pin level +// W Output GPIO pin output level +// +// +// HOWTO: +// +// Use a pin as an input: +// Program the corresponding bit in the control register to 'input mode' ('0'). +// The pin's state (input level) can be checked by reading the Line Register. +// Writing to the GPIO pin's Line Register bit while in input mode has no effect. +// +// Use a pin as an output: +// Program the corresponding bit in the control register to 'output mode' ('1'). +// Program the GPIO pin's output level by writing to the corresponding bit in +// the Line Register. +// Reading the GPIO pin's Line Register bit while in output mode returns the +// current output level. +// +// Addapt the core for fewer GPIOs: +// If less than 8 GPIOs are required, than the 'io' parameter can be set to +// the amount of required interrupts. GPIOs are mapped starting at the LSBs. +// So only the 'io' LSBs per register are valid. +// All other bits (i.e. the 8-'io' MSBs) are set to zero '0'. +// Codesize is approximately linear to the amount of interrupts. I.e. using +// 4 instead of 8 GPIO sources reduces the size by approx. half. +// + + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module simple_gpio( + clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, + gpio +); + + // + // Inputs & outputs + // + parameter io = 8; // number of GPIOs + + // 8bit WISHBONE bus slave interface + input clk_i; // clock + input rst_i; // reset (asynchronous active low) + input cyc_i; // cycle + input stb_i; // strobe + input adr_i; // address adr_i[1] + input we_i; // write enable + input [ 7:0] dat_i; // data output + output [ 7:0] dat_o; // data input + output ack_o; // normal bus termination + + // GPIO pins + inout [io:1] gpio; + + // + // Module body + // + reg [io:1] ctrl, line; // ControlRegister, LineRegister + reg [io:1] lgpio, llgpio; // LatchedGPIO pins + + // + // perform parameter checks + // + // synopsys translate_off + initial + begin + if(io > 8) + $display("simple_gpio: max. 8 GPIOs supported."); + end + // synopsys translate_on + + // + // WISHBONE interface + + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i or negedge rst_i) + if (~rst_i) + begin + ctrl <= #1 {io{1'b0}}; + line <= #1 {io{1'b0}}; + end + else if (wb_wr) + if ( adr_i ) + line <= #1 dat_i[io-1:0]; + else + ctrl <= #1 dat_i[io-1:0]; + + + reg [7:0] dat_o; + always @(posedge clk_i) + if ( adr_i ) + dat_o <= #1 { {(8-io){1'b0}}, llgpio}; + else + dat_o <= #1 { {(8-io){1'b0}}, ctrl}; + + reg ack_o; + always @(posedge clk_i or negedge rst_i) + if (~rst_i) + ack_o <= #1 1'b0; + else + ack_o <= #1 wb_acc & !ack_o; + + + // + // GPIO section + + // latch GPIO input pins + always @(posedge clk_i) + lgpio <= #1 gpio; + + // latch again (reduce meta-stability risc) + always @(posedge clk_i) + llgpio <= #1 lgpio; + + // assign GPIO outputs + integer n; + reg [io:1] igpio; // temporary internal signal + + always @(ctrl or line) + for(n=1;n<=io;n=n+1) + igpio[n] <= ctrl[n] ? line[n] : 1'bz; + + assign gpio = igpio; + +endmodule + diff --git a/usrp2/fpga/opencores/simple_pic/CVS/Entries b/usrp2/fpga/opencores/simple_pic/CVS/Entries new file mode 100644 index 00000000..df1462bb --- /dev/null +++ b/usrp2/fpga/opencores/simple_pic/CVS/Entries @@ -0,0 +1 @@ +D/rtl//// diff --git a/usrp2/fpga/opencores/simple_pic/CVS/Repository b/usrp2/fpga/opencores/simple_pic/CVS/Repository new file mode 100644 index 00000000..73de5bf2 --- /dev/null +++ b/usrp2/fpga/opencores/simple_pic/CVS/Repository @@ -0,0 +1 @@ +simple_pic diff --git a/usrp2/fpga/opencores/simple_pic/CVS/Root b/usrp2/fpga/opencores/simple_pic/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/simple_pic/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/simple_pic/CVS/Template b/usrp2/fpga/opencores/simple_pic/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/simple_pic/rtl/CVS/Entries b/usrp2/fpga/opencores/simple_pic/rtl/CVS/Entries new file mode 100644 index 00000000..e5e64109 --- /dev/null +++ b/usrp2/fpga/opencores/simple_pic/rtl/CVS/Entries @@ -0,0 +1,2 @@ +/simple_pic.v/1.3/Tue Dec 24 10:26:51 2002// +D diff --git a/usrp2/fpga/opencores/simple_pic/rtl/CVS/Repository b/usrp2/fpga/opencores/simple_pic/rtl/CVS/Repository new file mode 100644 index 00000000..2639a29e --- /dev/null +++ b/usrp2/fpga/opencores/simple_pic/rtl/CVS/Repository @@ -0,0 +1 @@ +simple_pic/rtl diff --git a/usrp2/fpga/opencores/simple_pic/rtl/CVS/Root b/usrp2/fpga/opencores/simple_pic/rtl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/simple_pic/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/simple_pic/rtl/CVS/Template b/usrp2/fpga/opencores/simple_pic/rtl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/simple_pic/rtl/simple_pic.v b/usrp2/fpga/opencores/simple_pic/rtl/simple_pic.v new file mode 100644 index 00000000..28184cbe --- /dev/null +++ b/usrp2/fpga/opencores/simple_pic/rtl/simple_pic.v @@ -0,0 +1,228 @@ + +// Modified by M. Ettus, 2008 for 32 bit width + +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple Programmable Interrupt Controller //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +// +// This is a simple Programmable Interrupt Controller. +// The number of interrupts is depending on the databus size. +// There's one interrupt input per databit (i.e. 16 interrupts for a 16 +// bit databus). +// All attached devices share the same CPU priority level. +// +// +// +// Registers: +// +// 0x00: EdgeEnable Register +// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source +// '0' = level triggered interrupt source +// 0x01: PolarityRegister +// bits 7:0 R/W Polarity '1' = high level / rising edge +// '0' = low level / falling edge +// 0x02: MaskRegister +// bits 7:0 R/W Mask '1' = interrupt masked (disabled) +// '0' = interrupt not masked (enabled) +// 0x03: PendingRegister +// bits 7:0 R/W Pending '1' = interrupt pending +// '0' = no interrupt pending +// +// A CPU interrupt is generated when an interrupt is pending and its +// MASK bit is cleared. +// +// +// +// HOWTO: +// +// Clearing pending interrupts: +// Writing a '1' to a bit in the interrupt pending register clears the +// interrupt. Make sure to clear the interrupt at the source before +// writing to the interrupt pending register. Otherwise the interrupt +// will be set again. +// +// Priority based interrupts: +// Upon reception of an interrupt, check the interrupt register and +// determine the highest priority interrupt. Mask all interrupts from the +// current level to the lowest level. This negates the interrupt line, and +// makes sure only interrupts with a higher level are triggered. After +// completion of the interrupt service routine, clear the interrupt source, +// the interrupt bit in the pending register, and restore the MASK register +// to it's previous state. +// +// Addapt the core for fewer interrupt sources: +// If less than 8 interrupt sources are required, than the 'is' parameter +// can be set to the amount of required interrupts. Interrupts are mapped +// starting at the LSBs. So only the 'is' LSBs per register are valid. All +// other bits (i.e. the 8-'is' MSBs) are set to zero '0'. +// Codesize is approximately linear to the amount of interrupts. I.e. using +// 4 instead of 8 interrupt sources reduces the size by approx. half. +// + + +module simple_pic( + clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, int_o, + irq +); + parameter is = 8; // Number of interrupt sources + parameter dwidth = 32; + // + // Inputs & outputs + // + + // 8bit WISHBONE bus slave interface + input clk_i; // clock + input rst_i; // reset (asynchronous active low) + input cyc_i; // cycle + input stb_i; // strobe (cycle and strobe are the same signal) + input [ 2:1] adr_i; // address + input we_i; // write enable + input [ dwidth-1:0] dat_i; // data output + output [ dwidth-1:0] dat_o; // data input + output ack_o; // normal bus termination + + output int_o; // interrupt output + + // + // Interrupt sources + // + input [is:1] irq; // interrupt request inputs + + + // + // Module body + // + reg [is:1] pol, edgen, pending, mask; // register bank + reg [is:1] lirq, dirq; // latched irqs, delayed latched irqs + + + // + // perform parameter checks + // + // synopsys translate_off + initial + begin + if(is > dwidth) + $display("simple_pic: max number of interrupts = data bus width."); + end + // synopsys translate_on + + // + // latch interrupt inputs + always @(posedge clk_i) + lirq <= #1 irq; + + // + // generate delayed latched irqs + always @(posedge clk_i) + dirq <= #1 lirq; + + + // + // generate actual triggers + function trigger; + input edgen, pol, lirq, dirq; + + reg edge_irq, level_irq; + begin + edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq); + level_irq = pol ? lirq : ~lirq; + + trigger = edgen ? edge_irq : level_irq; + end + endfunction + + reg [is:1] irq_event; + integer n; + always @(posedge clk_i) + for(n=1; n<=is; n=n+1) + irq_event[n] <= #1 trigger(edgen[n], pol[n], lirq[n], dirq[n]); + + // + // generate wishbone register bank writes + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i) + if (rst_i) + begin + pol <= #1 {is{1'b0}}; // clear polarity register + edgen <= #1 {is{1'b0}}; // clear edge enable register + mask <= #1 {is{1'b1}}; // mask all interrupts + end + else if(wb_wr) // wishbone write cycle?? + case (adr_i) // synopsys full_case parallel_case + 2'b00: edgen <= #1 dat_i[is-1:0]; // EDGE-ENABLE register + 2'b01: pol <= #1 dat_i[is-1:0]; // POLARITY register + 2'b10: mask <= #1 dat_i[is-1:0]; // MASK register + 2'b11: ; // PENDING register is a special case (see below) + endcase + + + // pending register is a special case + always @(posedge clk_i) + if (rst_i) + pending <= #1 {is{1'b0}}; // clear all pending interrupts + else if ( wb_wr & (&adr_i) ) + pending <= #1 (pending & ~dat_i[is-1:0]) | irq_event; + else + pending <= #1 pending | irq_event; + + // + // generate dat_o + reg [dwidth-1:0] dat_o; + always @(posedge clk_i) + case (adr_i) // synopsys full_case parallel_case + 2'b00: dat_o <= #1 { {(dwidth-is){1'b0}}, edgen}; + 2'b01: dat_o <= #1 { {(dwidth-is){1'b0}}, pol}; + 2'b10: dat_o <= #1 { {(dwidth-is){1'b0}}, mask}; + 2'b11: dat_o <= #1 { {(dwidth-is){1'b0}}, pending}; + endcase + + // + // generate ack_o + reg ack_o; + always @(posedge clk_i) + ack_o <= #1 wb_acc & !ack_o; + + // + // generate CPU interrupt signal + reg int_o; + always @(posedge clk_i) + if(rst_i) + int_o <= #1 0; + else + int_o <= #1 |(pending & ~mask); + +endmodule + diff --git a/usrp2/fpga/opencores/spi/CVS/Entries b/usrp2/fpga/opencores/spi/CVS/Entries new file mode 100644 index 00000000..62011c46 --- /dev/null +++ b/usrp2/fpga/opencores/spi/CVS/Entries @@ -0,0 +1,4 @@ +D/bench//// +D/doc//// +D/rtl//// +D/sim//// diff --git a/usrp2/fpga/opencores/spi/CVS/Repository b/usrp2/fpga/opencores/spi/CVS/Repository new file mode 100644 index 00000000..c928c4b7 --- /dev/null +++ b/usrp2/fpga/opencores/spi/CVS/Repository @@ -0,0 +1 @@ +spi diff --git a/usrp2/fpga/opencores/spi/CVS/Root b/usrp2/fpga/opencores/spi/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/CVS/Template b/usrp2/fpga/opencores/spi/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi/bench/CVS/Entries b/usrp2/fpga/opencores/spi/bench/CVS/Entries new file mode 100644 index 00000000..428c5622 --- /dev/null +++ b/usrp2/fpga/opencores/spi/bench/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/fpga/opencores/spi/bench/CVS/Repository b/usrp2/fpga/opencores/spi/bench/CVS/Repository new file mode 100644 index 00000000..f45728d0 --- /dev/null +++ b/usrp2/fpga/opencores/spi/bench/CVS/Repository @@ -0,0 +1 @@ +spi/bench diff --git a/usrp2/fpga/opencores/spi/bench/CVS/Root b/usrp2/fpga/opencores/spi/bench/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/bench/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/bench/CVS/Template b/usrp2/fpga/opencores/spi/bench/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi/bench/verilog/CVS/Entries b/usrp2/fpga/opencores/spi/bench/verilog/CVS/Entries new file mode 100644 index 00000000..68404f87 --- /dev/null +++ b/usrp2/fpga/opencores/spi/bench/verilog/CVS/Entries @@ -0,0 +1,4 @@ +/spi_slave_model.v/1.2/Wed Mar 26 16:00:03 2003// +/tb_spi_top.v/1.6/Mon Mar 15 17:46:04 2004// +/wb_master_model.v/1.1.1.1/Wed Jun 12 15:45:23 2002// +D diff --git a/usrp2/fpga/opencores/spi/bench/verilog/CVS/Repository b/usrp2/fpga/opencores/spi/bench/verilog/CVS/Repository new file mode 100644 index 00000000..78a3c4a9 --- /dev/null +++ b/usrp2/fpga/opencores/spi/bench/verilog/CVS/Repository @@ -0,0 +1 @@ +spi/bench/verilog diff --git a/usrp2/fpga/opencores/spi/bench/verilog/CVS/Root b/usrp2/fpga/opencores/spi/bench/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/bench/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/bench/verilog/CVS/Template b/usrp2/fpga/opencores/spi/bench/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi/bench/verilog/spi_slave_model.v b/usrp2/fpga/opencores/spi/bench/verilog/spi_slave_model.v new file mode 100644 index 00000000..dfdaed92 --- /dev/null +++ b/usrp2/fpga/opencores/spi/bench/verilog/spi_slave_model.v @@ -0,0 +1,73 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_slave_model.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "timescale.v" + +module spi_slave_model (rst, ss, sclk, mosi, miso); + + input rst; // reset + input ss; // slave select + input sclk; // serial clock + input mosi; // master out slave in + output miso; // master in slave out + + reg miso; + + reg rx_negedge; // slave receiving on negedge + reg tx_negedge; // slave transmiting on negedge + reg [31:0] data; // data register + + parameter Tp = 1; + + always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst) + begin + if (rst) + data <= #Tp 32'b0; + else if (!ss) + data <= #Tp {data[30:0], mosi}; + end + + always @(posedge(sclk && !tx_negedge) or negedge(sclk && tx_negedge)) + begin + miso <= #Tp data[31]; + end + +endmodule + diff --git a/usrp2/fpga/opencores/spi/bench/verilog/tb_spi_top.v b/usrp2/fpga/opencores/spi/bench/verilog/tb_spi_top.v new file mode 100644 index 00000000..529c0aca --- /dev/null +++ b/usrp2/fpga/opencores/spi/bench/verilog/tb_spi_top.v @@ -0,0 +1,339 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// tb_spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// Based on: //// +//// - i2c/bench/verilog/tst_bench_top.v //// +//// Copyright (C) 2001 Richard Herveille //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "timescale.v" + +module tb_spi_top(); + + reg clk; + reg rst; + wire [31:0] adr; + wire [31:0] dat_i, dat_o; + wire we; + wire [3:0] sel; + wire stb; + wire cyc; + wire ack; + wire err; + wire int; + + wire [7:0] ss; + wire sclk; + wire mosi; + wire miso; + + reg [31:0] q; + reg [31:0] q1; + reg [31:0] q2; + reg [31:0] q3; + reg [31:0] result; + + parameter SPI_RX_0 = 5'h0; + parameter SPI_RX_1 = 5'h4; + parameter SPI_RX_2 = 5'h8; + parameter SPI_RX_3 = 5'hc; + parameter SPI_TX_0 = 5'h0; + parameter SPI_TX_1 = 5'h4; + parameter SPI_TX_2 = 5'h8; + parameter SPI_TX_3 = 5'hc; + parameter SPI_CTRL = 5'h10; + parameter SPI_DIVIDE = 5'h14; + parameter SPI_SS = 5'h18; + + // Generate clock + always #5 clk = ~clk; + + // Wishbone master model + wb_master_model #(32, 32) i_wb_master ( + .clk(clk), .rst(rst), + .adr(adr), .din(dat_i), .dout(dat_o), + .cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0) + ); + + // SPI master core + spi_top i_spi_top ( + .wb_clk_i(clk), .wb_rst_i(rst), + .wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i), + .wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb), + .wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int), + .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) + ); + + // SPI slave model + spi_slave_model i_spi_slave ( + .rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso) + ); + + initial + begin + $display("\nstatus: %t Testbench started\n\n", $time); + + $dumpfile("bench.vcd"); + $dumpvars(1, tb_spi_top); + $dumpvars(1, tb_spi_top.i_spi_slave); + + // Initial values + clk = 0; + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b0; + + result = 32'h0; + + // Reset system + rst = 1'b0; // negate reset + #2; + rst = 1'b1; // assert reset + repeat(20) @(posedge clk); + rst = 1'b0; // negate reset + + $display("status: %t done reset", $time); + + @(posedge clk); + + // Program core + i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register + i_wb_master.wb_write(0, SPI_TX_0, 32'h5a); // set tx register to 0x5a + i_wb_master.wb_write(0, SPI_CTRL, 32'h208); // set 8 bit transfer + i_wb_master.wb_write(0, SPI_SS, 32'h01); // set ss 0 + + $display("status: %t programmed registers", $time); + + i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h00); // verify devider register + i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a); // verify tx register + i_wb_master.wb_cmp(0, SPI_CTRL, 32'h208); // verify tx register + i_wb_master.wb_cmp(0, SPI_SS, 32'h01); // verify ss register + + $display("status: %t verified registers", $time); + + i_spi_slave.rx_negedge = 1'b1; + i_spi_slave.tx_negedge = 1'b0; + i_spi_slave.data[31:0] = 32'ha5967e5a; + i_wb_master.wb_write(0, SPI_CTRL, 32'h308); // set 8 bit transfer, start transfer + + $display("status: %t generate transfer: 8 bit, msb first, tx posedge, rx negedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b1; + i_wb_master.wb_write(0, SPI_TX_0, 32'ha5); + i_wb_master.wb_write(0, SPI_CTRL, 32'h408); // set 8 bit transfer, tx negedge + i_wb_master.wb_write(0, SPI_CTRL, 32'h508); // set 8 bit transfer, tx negedge, start transfer + + $display("status: %t generate transfer: 8 bit, msb first, tx negedge, rx posedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b1; + i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5); + i_wb_master.wb_write(0, SPI_CTRL, 32'hc10); // set 16 bit transfer, tx negedge, lsb + i_wb_master.wb_write(0, SPI_CTRL, 32'hd10); // set 16 bit transfer, tx negedge, start transfer + + $display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b1; + i_spi_slave.tx_negedge = 1'b0; + i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210); + i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98); + i_wb_master.wb_write(0, SPI_CTRL, 32'h1a40); // set 64 bit transfer, rx negedge, lsb + i_wb_master.wb_write(0, SPI_CTRL, 32'h1b40); // set 64 bit transfer, rx negedge, start transfer + + $display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + i_wb_master.wb_read(1, SPI_RX_1, q1); + result = result + q1; + + if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b1; + i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff); + i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb); + i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677); + i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233); + i_wb_master.wb_write(0, SPI_CTRL, 32'h400); + i_wb_master.wb_write(0, SPI_CTRL, 32'h500); + + $display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time); + + // Check bsy bit + i_wb_master.wb_read(0, SPI_CTRL, q); + while (q[8]) + i_wb_master.wb_read(1, SPI_CTRL, q); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + i_wb_master.wb_read(1, SPI_RX_1, q1); + result = result + q1; + i_wb_master.wb_read(1, SPI_RX_2, q2); + result = result + q2; + i_wb_master.wb_read(1, SPI_RX_3, q3); + result = result + q3; + + if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b0; + i_spi_slave.tx_negedge = 1'b1; + i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5); + i_wb_master.wb_write(0, SPI_CTRL, 32'h1420); + i_wb_master.wb_write(0, SPI_CTRL, 32'h1520); + + $display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time); + + // Check interrupt signal + while (!int) + @(posedge clk); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + @(posedge clk); + if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b1; + i_spi_slave.tx_negedge = 1'b0; + i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421); + i_wb_master.wb_write(0, SPI_CTRL, 32'h3220); + i_wb_master.wb_write(0, SPI_CTRL, 32'h3320); + + $display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time); + + while (!int) + @(posedge clk); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + @(posedge clk); + if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + i_spi_slave.rx_negedge = 1'b1; + i_spi_slave.tx_negedge = 1'b0; + i_wb_master.wb_write(0, SPI_TX_0, 32'h1); + i_wb_master.wb_write(0, SPI_CTRL, 32'h3201); + i_wb_master.wb_write(0, SPI_CTRL, 32'h3301); + + $display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time); + + while (!int) + @(posedge clk); + + i_wb_master.wb_read(1, SPI_RX_0, q); + result = result + q; + + @(posedge clk); + if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0) + $display("status: %t transfer completed: ok", $time); + else + $display("status: %t transfer completed: nok", $time); + + $display("\n\nstatus: %t Testbench done", $time); + + #25000; // wait 25us + + $display("report (%h)", (result ^ 32'h2e8b36ab) + 32'hdeaddead); + $display("exit (%h)", result ^ 32'h2e8b36ab); + + $stop; + end + +endmodule + + diff --git a/usrp2/fpga/opencores/spi/bench/verilog/wb_master_model.v b/usrp2/fpga/opencores/spi/bench/verilog/wb_master_model.v new file mode 100644 index 00000000..3f8b7ee6 --- /dev/null +++ b/usrp2/fpga/opencores/spi/bench/verilog/wb_master_model.v @@ -0,0 +1,176 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wb_master_model.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// Based on: //// +//// - i2c/bench/verilog/wb_master_model.v //// +//// Copyright (C) 2001 Richard Herveille //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "timescale.v" + +module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); + + parameter dwidth = 32; + parameter awidth = 32; + + input clk, rst; + output [awidth -1:0] adr; + input [dwidth -1:0] din; + output [dwidth -1:0] dout; + output cyc, stb; + output we; + output [dwidth/8 -1:0] sel; + input ack, err, rty; + + // Internal signals + reg [awidth -1:0] adr; + reg [dwidth -1:0] dout; + reg cyc, stb; + reg we; + reg [dwidth/8 -1:0] sel; + + reg [dwidth -1:0] q; + + // Memory Logic + initial + begin + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + cyc = 1'b0; + stb = 1'bx; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + #1; + end + + // Wishbone write cycle + task wb_write; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signal + #1; + adr = a; + dout = d; + cyc = 1'b1; + stb = 1'b1; + we = 1'b1; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + + end + endtask + + // Wishbone read cycle + task wb_read; + input delay; + integer delay; + + input [awidth -1:0] a; + output [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signals + #1; + adr = a; + dout = {dwidth{1'bx}}; + cyc = 1'b1; + stb = 1'b1; + we = 1'b0; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + d = din; + + end + endtask + + // Wishbone compare cycle (read data from location and compare with expected data) + task wb_cmp; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d_exp; + + begin + wb_read (delay, a, q); + + if (d_exp !== q) + $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); + end + endtask + +endmodule + diff --git a/usrp2/fpga/opencores/spi/doc/CVS/Entries b/usrp2/fpga/opencores/spi/doc/CVS/Entries new file mode 100644 index 00000000..ff33fa59 --- /dev/null +++ b/usrp2/fpga/opencores/spi/doc/CVS/Entries @@ -0,0 +1,2 @@ +/spi.pdf/1.5/Mon Mar 15 17:46:05 2004/-kb/ +D/src//// diff --git a/usrp2/fpga/opencores/spi/doc/CVS/Repository b/usrp2/fpga/opencores/spi/doc/CVS/Repository new file mode 100644 index 00000000..772adcef --- /dev/null +++ b/usrp2/fpga/opencores/spi/doc/CVS/Repository @@ -0,0 +1 @@ +spi/doc diff --git a/usrp2/fpga/opencores/spi/doc/CVS/Root b/usrp2/fpga/opencores/spi/doc/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/doc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/doc/CVS/Template b/usrp2/fpga/opencores/spi/doc/CVS/Template new file mode 100644 index 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oAPIEk)^_YcNbGSsx^hiibRW*Q7n_!u&&%&08I*i9;2)E~4=btl_W%F@ literal 0 HcmV?d00001 diff --git a/usrp2/fpga/opencores/spi/rtl/CVS/Entries b/usrp2/fpga/opencores/spi/rtl/CVS/Entries new file mode 100644 index 00000000..428c5622 --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/fpga/opencores/spi/rtl/CVS/Repository b/usrp2/fpga/opencores/spi/rtl/CVS/Repository new file mode 100644 index 00000000..5fd79b19 --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/CVS/Repository @@ -0,0 +1 @@ +spi/rtl diff --git a/usrp2/fpga/opencores/spi/rtl/CVS/Root b/usrp2/fpga/opencores/spi/rtl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/rtl/CVS/Template b/usrp2/fpga/opencores/spi/rtl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Entries b/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Entries new file mode 100644 index 00000000..d125a165 --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Entries @@ -0,0 +1,6 @@ +/spi_clgen.v/1.3/Thu Jul 3 17:32:15 2003// +/spi_defines.v/1.8/Mon Mar 15 17:46:08 2004// +/spi_shift.v/1.7/Tue Jul 8 15:36:37 2003// +/spi_top.v/1.8/Tue Jul 8 15:36:37 2003// +/timescale.v/1.1.1.1/Wed Jun 12 15:45:23 2002// +D diff --git a/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Repository b/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Repository new file mode 100644 index 00000000..361b93bf --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Repository @@ -0,0 +1 @@ +spi/rtl/verilog diff --git a/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Root b/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Template b/usrp2/fpga/opencores/spi/rtl/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/fpga/opencores/spi/rtl/verilog/spi_clgen.v new file mode 100644 index 00000000..7bc4f6e5 --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/verilog/spi_clgen.v @@ -0,0 +1,108 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_clgen.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); + + parameter Tp = 1; + + input clk_in; // input clock (system clock) + input rst; // reset + input enable; // clock enable + input go; // start transfer + input last_clk; // last clock + input [`SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value) + output clk_out; // output clock + output pos_edge; // pulse marking positive edge of clk_out + output neg_edge; // pulse marking negative edge of clk_out + + reg clk_out; + reg pos_edge; + reg neg_edge; + + reg [`SPI_DIVIDER_LEN-1:0] cnt; // clock counter + wire cnt_zero; // conter is equal to zero + wire cnt_one; // conter is equal to one + + + assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}}; + assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; + + // Counter counts half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}}; + else + begin + if(!enable || cnt_zero) + cnt <= #Tp divider; + else + cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; + end + end + + // clk_out is asserted every other half period + always @(posedge clk_in or posedge rst) + begin + if(rst) + clk_out <= #Tp 1'b0; + else + clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + end + + // Pos and neg edge signals + always @(posedge clk_in or posedge rst) + begin + if(rst) + begin + pos_edge <= #Tp 1'b0; + neg_edge <= #Tp 1'b0; + end + else + begin + pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + end + end +endmodule + diff --git a/usrp2/fpga/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/fpga/opencores/spi/rtl/verilog/spi_defines.v new file mode 100644 index 00000000..a6925918 --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/verilog/spi_defines.v @@ -0,0 +1,159 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_define.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// +// Number of bits used for devider register. If used in system with +// low frequency of system clock this can be reduced. +// Use SPI_DIVIDER_LEN for fine tuning theexact number. +// +//`define SPI_DIVIDER_LEN_8 +`define SPI_DIVIDER_LEN_16 +//`define SPI_DIVIDER_LEN_24 +//`define SPI_DIVIDER_LEN_32 + +`ifdef SPI_DIVIDER_LEN_8 + `define SPI_DIVIDER_LEN 8 // Can be set from 1 to 8 +`endif +`ifdef SPI_DIVIDER_LEN_16 + `define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 +`endif +`ifdef SPI_DIVIDER_LEN_24 + `define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24 +`endif +`ifdef SPI_DIVIDER_LEN_32 + `define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32 +`endif + +// +// Maximum nuber of bits that can be send/received at once. +// Use SPI_MAX_CHAR for fine tuning the exact number, when using +// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. +// +`define SPI_MAX_CHAR_128 +//`define SPI_MAX_CHAR_64 +//`define SPI_MAX_CHAR_32 +//`define SPI_MAX_CHAR_24 +//`define SPI_MAX_CHAR_16 +//`define SPI_MAX_CHAR_8 + +`ifdef SPI_MAX_CHAR_128 + `define SPI_MAX_CHAR 128 // Can only be set to 128 + `define SPI_CHAR_LEN_BITS 7 +`endif +`ifdef SPI_MAX_CHAR_64 + `define SPI_MAX_CHAR 64 // Can only be set to 64 + `define SPI_CHAR_LEN_BITS 6 +`endif +`ifdef SPI_MAX_CHAR_32 + `define SPI_MAX_CHAR 32 // Can be set from 25 to 32 + `define SPI_CHAR_LEN_BITS 5 +`endif +`ifdef SPI_MAX_CHAR_24 + `define SPI_MAX_CHAR 24 // Can be set from 17 to 24 + `define SPI_CHAR_LEN_BITS 5 +`endif +`ifdef SPI_MAX_CHAR_16 + `define SPI_MAX_CHAR 16 // Can be set from 9 to 16 + `define SPI_CHAR_LEN_BITS 4 +`endif +`ifdef SPI_MAX_CHAR_8 + `define SPI_MAX_CHAR 8 // Can be set from 1 to 8 + `define SPI_CHAR_LEN_BITS 3 +`endif + +// +// Number of device select signals. Use SPI_SS_NB for fine tuning the +// exact number. +// +`define SPI_SS_NB_8 +//`define SPI_SS_NB_16 +//`define SPI_SS_NB_24 +//`define SPI_SS_NB_32 + +`ifdef SPI_SS_NB_8 + `define SPI_SS_NB 8 // Can be set from 1 to 8 +`endif +`ifdef SPI_SS_NB_16 + `define SPI_SS_NB 16 // Can be set from 9 to 16 +`endif +`ifdef SPI_SS_NB_24 + `define SPI_SS_NB 24 // Can be set from 17 to 24 +`endif +`ifdef SPI_SS_NB_32 + `define SPI_SS_NB 32 // Can be set from 25 to 32 +`endif + +// +// Bits of WISHBONE address used for partial decoding of SPI registers. +// +`define SPI_OFS_BITS 4:2 + +// +// Register offset +// +`define SPI_RX_0 0 +`define SPI_RX_1 1 +`define SPI_RX_2 2 +`define SPI_RX_3 3 +`define SPI_TX_0 0 +`define SPI_TX_1 1 +`define SPI_TX_2 2 +`define SPI_TX_3 3 +`define SPI_CTRL 4 +`define SPI_DEVIDE 5 +`define SPI_SS 6 + +// +// Number of bits in ctrl register +// +`define SPI_CTRL_BIT_NB 14 + +// +// Control register bit position +// +`define SPI_CTRL_ASS 13 +`define SPI_CTRL_IE 12 +`define SPI_CTRL_LSB 11 +`define SPI_CTRL_TX_NEGEDGE 10 +`define SPI_CTRL_RX_NEGEDGE 9 +`define SPI_CTRL_GO 8 +`define SPI_CTRL_RES_1 7 +`define SPI_CTRL_CHAR_LEN 6:0 + diff --git a/usrp2/fpga/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/fpga/opencores/spi/rtl/verilog/spi_shift.v new file mode 100644 index 00000000..b17ac8b1 --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/verilog/spi_shift.v @@ -0,0 +1,238 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_shift.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "spi_defines.v" +`include "timescale.v" + +module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, + pos_edge, neg_edge, rx_negedge, tx_negedge, + tip, last, + p_in, p_out, s_clk, s_in, s_out); + + parameter Tp = 1; + + input clk; // system clock + input rst; // reset + input [3:0] latch; // latch signal for storing the data in shift register + input [3:0] byte_sel; // byte select signals for storing the data in shift register + input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one) + input lsb; // lbs first on the line + input go; // start stansfer + input pos_edge; // recognize posedge of sclk + input neg_edge; // recognize negedge of sclk + input rx_negedge; // s_in is sampled on negative edge + input tx_negedge; // s_out is driven on negative edge + output tip; // transfer in progress + output last; // last bit + input [31:0] p_in; // parallel in + output [`SPI_MAX_CHAR-1:0] p_out; // parallel out + input s_clk; // serial clock + input s_in; // serial in + output s_out; // serial out + + reg s_out; + reg tip; + + reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count + reg [`SPI_MAX_CHAR-1:0] data; // shift register + wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position + wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position + wire rx_clk; // rx clock enable + wire tx_clk; // tx clock enable + + assign p_out = data; + + assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}; + assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : + (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1}); + + assign last = !(|cnt); + + assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk); + assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; + + // Character bit counter + always @(posedge clk or posedge rst) + begin + if(rst) + cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + else + begin + if(tip) + cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + else + cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + end + end + + // Transfer in progress + always @(posedge clk or posedge rst) + begin + if(rst) + tip <= #Tp 1'b0; + else if(go && ~tip) + tip <= #Tp 1'b1; + else if(tip && last && pos_edge) + tip <= #Tp 1'b0; + end + + // Sending bits to the line + always @(posedge clk or posedge rst) + begin + if (rst) + s_out <= #Tp 1'b0; + else + s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + end + + // Receiving bits from the line + always @(posedge clk or posedge rst) + begin + if (rst) + data <= #Tp {`SPI_MAX_CHAR{1'b0}}; +`ifdef SPI_MAX_CHAR_128 + else if (latch[0] && !tip) + begin + if (byte_sel[3]) + data[31:24] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + end + else if (latch[1] && !tip) + begin + if (byte_sel[3]) + data[63:56] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[55:48] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[47:40] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[39:32] <= #Tp p_in[7:0]; + end + else if (latch[2] && !tip) + begin + if (byte_sel[3]) + data[95:88] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[87:80] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[79:72] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[71:64] <= #Tp p_in[7:0]; + end + else if (latch[3] && !tip) + begin + if (byte_sel[3]) + data[127:120] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[119:112] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[111:104] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[103:96] <= #Tp p_in[7:0]; + end +`else +`ifdef SPI_MAX_CHAR_64 + else if (latch[0] && !tip) + begin + if (byte_sel[3]) + data[31:24] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + end + else if (latch[1] && !tip) + begin + if (byte_sel[3]) + data[63:56] <= #Tp p_in[31:24]; + if (byte_sel[2]) + data[55:48] <= #Tp p_in[23:16]; + if (byte_sel[1]) + data[47:40] <= #Tp p_in[15:8]; + if (byte_sel[0]) + data[39:32] <= #Tp p_in[7:0]; + end +`else + else if (latch[0] && !tip) + begin + `ifdef SPI_MAX_CHAR_8 + if (byte_sel[0]) + data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0]; + `endif + `ifdef SPI_MAX_CHAR_16 + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8]; + `endif + `ifdef SPI_MAX_CHAR_24 + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[2]) + data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16]; + `endif + `ifdef SPI_MAX_CHAR_32 + if (byte_sel[0]) + data[7:0] <= #Tp p_in[7:0]; + if (byte_sel[1]) + data[15:8] <= #Tp p_in[15:8]; + if (byte_sel[2]) + data[23:16] <= #Tp p_in[23:16]; + if (byte_sel[3]) + data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24]; + `endif + end +`endif +`endif + else + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + end + +endmodule + diff --git a/usrp2/fpga/opencores/spi/rtl/verilog/spi_top.v b/usrp2/fpga/opencores/spi/rtl/verilog/spi_top.v new file mode 100644 index 00000000..09b2e50e --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/verilog/spi_top.v @@ -0,0 +1,287 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" +`include "timescale.v" + +module spi_top +( + // Wishbone signals + wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, + + // SPI signals + ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i +); + + parameter Tp = 1; + + // Wishbone signals + input wb_clk_i; // master clock input + input wb_rst_i; // synchronous active high reset + input [4:0] wb_adr_i; // lower address bits + input [32-1:0] wb_dat_i; // databus input + output [32-1:0] wb_dat_o; // databus output + input [3:0] wb_sel_i; // byte select inputs + input wb_we_i; // write enable input + input wb_stb_i; // stobe/core select signal + input wb_cyc_i; // valid bus cycle input + output wb_ack_o; // bus cycle acknowledge output + output wb_err_o; // termination w/ error + output wb_int_o; // interrupt request signal output + + // SPI signals + output [`SPI_SS_NB-1:0] ss_pad_o; // slave select + output sclk_pad_o; // serial clock + output mosi_pad_o; // master out slave in + input miso_pad_i; // master in slave out + + reg [32-1:0] wb_dat_o; + reg wb_ack_o; + reg wb_int_o; + + // Internal signals + reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register + reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [`SPI_SS_NB-1:0] ss; // Slave select register + reg [32-1:0] wb_dat; // wb data out + wire [`SPI_MAX_CHAR-1:0] rx; // Rx register + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len + wire go; // go + wire lsb; // lsb first on line + wire ie; // interrupt enable + wire ass; // automatic slave select + wire spi_divider_sel; // divider register select + wire spi_ctrl_sel; // ctrl register select + wire [3:0] spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + // Address decoder + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE); + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); + assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); + assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1); + assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_2); + assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_3); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS); + + // Read from registers + always @(wb_adr_i or rx or ctrl or divider or ss) + begin + case (wb_adr_i[`SPI_OFS_BITS]) +`ifdef SPI_MAX_CHAR_128 + `SPI_RX_0: wb_dat = rx[31:0]; + `SPI_RX_1: wb_dat = rx[63:32]; + `SPI_RX_2: wb_dat = rx[95:64]; + `SPI_RX_3: wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]}; +`else +`ifdef SPI_MAX_CHAR_64 + `SPI_RX_0: wb_dat = rx[31:0]; + `SPI_RX_1: wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]}; + `SPI_RX_2: wb_dat = 32'b0; + `SPI_RX_3: wb_dat = 32'b0; +`else + `SPI_RX_0: wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]}; + `SPI_RX_1: wb_dat = 32'b0; + `SPI_RX_2: wb_dat = 32'b0; + `SPI_RX_3: wb_dat = 32'b0; +`endif +`endif + `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; + `SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; + `SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss}; + default: wb_dat = 32'bx; + endcase + end + + // Wb data out + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_dat_o <= #Tp 32'b0; + else + wb_dat_o <= #Tp wb_dat; + end + + // Wb acknowledge + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_ack_o <= #Tp 1'b0; + else + wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + end + + // Wb error + assign wb_err_o = 1'b0; + + // Interrupt + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + wb_int_o <= #Tp 1'b0; + else if (ie && tip && last_bit && pos_edge) + wb_int_o <= #Tp 1'b1; + else if (wb_ack_o) + wb_int_o <= #Tp 1'b0; + end + + // Divider register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}}; + else if (spi_divider_sel && wb_we_i && !tip) + begin + `ifdef SPI_DIVIDER_LEN_8 + if (wb_sel_i[0]) + divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0]; + `endif + `ifdef SPI_DIVIDER_LEN_16 + if (wb_sel_i[0]) + divider[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8]; + `endif + `ifdef SPI_DIVIDER_LEN_24 + if (wb_sel_i[0]) + divider[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + divider[15:8] <= #Tp wb_dat_i[15:8]; + if (wb_sel_i[2]) + divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16]; + `endif + `ifdef SPI_DIVIDER_LEN_32 + if (wb_sel_i[0]) + divider[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + divider[15:8] <= #Tp wb_dat_i[15:8]; + if (wb_sel_i[2]) + divider[23:16] <= #Tp wb_dat_i[23:16]; + if (wb_sel_i[3]) + divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24]; + `endif + end + end + + // Ctrl register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}}; + else if(spi_ctrl_sel && wb_we_i && !tip) + begin + if (wb_sel_i[0]) + ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; + if (wb_sel_i[1]) + ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + end + else if(tip && last_bit && pos_edge) + ctrl[`SPI_CTRL_GO] <= #Tp 1'b0; + end + + assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; + assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; + assign go = ctrl[`SPI_CTRL_GO]; + assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; + assign lsb = ctrl[`SPI_CTRL_LSB]; + assign ie = ctrl[`SPI_CTRL_IE]; + assign ass = ctrl[`SPI_CTRL_ASS]; + + // Slave select register + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + ss <= #Tp {`SPI_SS_NB{1'b0}}; + else if(spi_ss_sel && wb_we_i && !tip) + begin + `ifdef SPI_SS_NB_8 + if (wb_sel_i[0]) + ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + `endif + `ifdef SPI_SS_NB_16 + if (wb_sel_i[0]) + ss[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8]; + `endif + `ifdef SPI_SS_NB_24 + if (wb_sel_i[0]) + ss[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[15:8] <= #Tp wb_dat_i[15:8]; + if (wb_sel_i[2]) + ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16]; + `endif + `ifdef SPI_SS_NB_32 + if (wb_sel_i[0]) + ss[7:0] <= #Tp wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[15:8] <= #Tp wb_dat_i[15:8]; + if (wb_sel_i[2]) + ss[23:16] <= #Tp wb_dat_i[23:16]; + if (wb_sel_i[3]) + ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24]; + `endif + end + end + + assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}})); + + spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), + .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), + .neg_edge(neg_edge)); + + spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb), + .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), + .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), + .tip(tip), .last(last_bit), + .p_in(wb_dat_i), .p_out(rx), + .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); +endmodule + diff --git a/usrp2/fpga/opencores/spi/rtl/verilog/timescale.v b/usrp2/fpga/opencores/spi/rtl/verilog/timescale.v new file mode 100644 index 00000000..60d4ecbd --- /dev/null +++ b/usrp2/fpga/opencores/spi/rtl/verilog/timescale.v @@ -0,0 +1,2 @@ +`timescale 1ns / 10ps + diff --git a/usrp2/fpga/opencores/spi/sim/CVS/Entries b/usrp2/fpga/opencores/spi/sim/CVS/Entries new file mode 100644 index 00000000..54553333 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/CVS/Entries @@ -0,0 +1,2 @@ +D/rtl_sim//// +D/run//// diff --git a/usrp2/fpga/opencores/spi/sim/CVS/Repository b/usrp2/fpga/opencores/spi/sim/CVS/Repository new file mode 100644 index 00000000..9ec76930 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/CVS/Repository @@ -0,0 +1 @@ +spi/sim diff --git a/usrp2/fpga/opencores/spi/sim/CVS/Root b/usrp2/fpga/opencores/spi/sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/sim/CVS/Template b/usrp2/fpga/opencores/spi/sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Entries b/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Entries new file mode 100644 index 00000000..8ab9f73a --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Entries @@ -0,0 +1 @@ +D/run//// diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Repository b/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Repository new file mode 100644 index 00000000..c8c6a94c --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Repository @@ -0,0 +1 @@ +spi/sim/rtl_sim diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Root b/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Template b/usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Entries b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Entries new file mode 100644 index 00000000..8947f64a --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Entries @@ -0,0 +1,4 @@ +/rtl.fl/1.1/Mon Mar 15 17:46:08 2004// +/run_sim/1.1/Mon Mar 15 17:46:08 2004// +/sim.fl/1.1/Mon Mar 15 17:46:08 2004// +D diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Repository b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Repository new file mode 100644 index 00000000..5200bb19 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Repository @@ -0,0 +1 @@ +spi/sim/rtl_sim/run diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Root b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Template b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/run/rtl.fl b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/rtl.fl new file mode 100644 index 00000000..d84a0840 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/rtl.fl @@ -0,0 +1,3 @@ +spi_top.v +spi_clgen.v +spi_shift.v diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/run/run_sim b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/run_sim new file mode 100755 index 00000000..1b13a35b --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/run_sim @@ -0,0 +1,108 @@ +#!/bin/csh -f + +set current_par = 0 +set output_waveform = 0 +while ( $current_par < $# ) + @ current_par = $current_par + 1 + case wave: + @ output_waveform = 1 + breaksw + default: + echo 'Unknown option "'$argv[$current_par]'"!' + exit + breaksw + endsw +end + +echo "TEST: spi" + +#echo "-CDSLIB ./cds.lib" > ncvlog.args +#echo "-HDLVAR ./hdl.var" >> ncvlog.args +echo "-MESSAGES" > ncvlog.args +echo "-INCDIR ../../../bench/verilog" >> ncvlog.args +echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args +echo "-NOCOPYRIGHT" >> ncvlog.args +echo "-UPDATE" >> ncvlog.args +echo "-LOGFILE ncvlog.log" >> ncvlog.args + +foreach filename ( `cat ./rtl.fl` ) + echo "../../../rtl/verilog/"$filename >> ncvlog.args +end + +foreach filename ( `cat ./sim.fl` ) + echo "../../../bench/verilog/"$filename >> ncvlog.args +end + +ncvlog -f ncvlog.args +if ($status != 0) then + echo "STATUS: failed" + exit +endif + + +echo "-MESSAGES" > ncelab.args +echo "-NOCOPYRIGHT" >> ncelab.args +#echo "-CDSLIB ./cds.lib" >> ncelab.args +#echo "-HDLVAR ./hdl.var" >> ncelab.args +echo "-LOGFILE ncelab.log" >> ncelab.args +echo "-SNAPSHOT worklib.tb_spi_top:v" >> ncelab.args +echo "-NOTIMINGCHECKS" >> ncelab.args +echo "-ACCESS +RWC" >> ncelab.args +echo "tb_spi_top" >> ncelab.args + +ncelab -f ncelab.args +if ($status != 0) then + echo "STATUS: failed" + exit +endif + + +echo "-MESSAGES" > ncsim.args +echo "-NOCOPYRIGHT" >> ncsim.args +#echo "-CDSLIB ./cds.lib" >> ncsim.args +#echo "-HDLVAR ./hdl.var" >> ncsim.args +echo "-INPUT ncsim.tcl" >> ncsim.args +echo "-LOGFILE ncsim.log" >> ncsim.args +echo "worklib.tb_spi_top:v" >> ncsim.args + +if ( $output_waveform ) then + echo "database -open waves -shm -into ../out/wav" > ./ncsim.tcl + echo "probe -create -database waves -shm tb_spi_top -all -depth all" >> ./ncsim.tcl + echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl + echo "run" >> ./ncsim.tcl +else + echo "stop -create -time 25000000 -relative" >> ./ncsim.tcl + echo "run" > ./ncsim.tcl +endif + +echo "exit" >> ncsim.tcl + +ncsim -LICQUEUE -f ./ncsim.args + +set exit_line_nb = `sed -n '/exit/=' < ./ncsim.log` + +set dead_line_nb = 0 + +if ( $exit_line_nb ) then + + @ dead_line_nb = $exit_line_nb - 1 + set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ./ncsim.log` + set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ./ncsim.log` + + if ( "$dead_line" == "report (deaddead)" ) then + if ( "$exit_line" == "exit (00000000)" ) then + echo "STATUS: passed" #|tee -a ./run_sim.log 2>&1 + else + echo "STATUS: failed" #|tee -a ./run_sim.log 2>&1 + endif + else + echo "STATUS: failed" + endif + +endif + +exit + + + + diff --git a/usrp2/fpga/opencores/spi/sim/rtl_sim/run/sim.fl b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/sim.fl new file mode 100644 index 00000000..283aad1f --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/rtl_sim/run/sim.fl @@ -0,0 +1,3 @@ +tb_spi_top.v +wb_master_model.v +spi_slave_model.v diff --git a/usrp2/fpga/opencores/spi/sim/run/CVS/Entries b/usrp2/fpga/opencores/spi/sim/run/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/run/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/spi/sim/run/CVS/Repository b/usrp2/fpga/opencores/spi/sim/run/CVS/Repository new file mode 100644 index 00000000..e8646e70 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/run/CVS/Repository @@ -0,0 +1 @@ +spi/sim/run diff --git a/usrp2/fpga/opencores/spi/sim/run/CVS/Root b/usrp2/fpga/opencores/spi/sim/run/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi/sim/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi/sim/run/CVS/Template b/usrp2/fpga/opencores/spi/sim/run/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/COMPILE_LIST b/usrp2/fpga/opencores/spi_boot/COMPILE_LIST new file mode 100644 index 00000000..fc8f7d41 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/COMPILE_LIST @@ -0,0 +1,33 @@ + +Compile list for the spi_boot core +================================== +Version: $Date: 2005/04/14 21:26:22 $ + +bench/vhdl/tb.vhd +rtl/vhdl/spi_boot_pack-p.vhd +bench/vhdl/tb_pack-p.vhd +bench/vhdl/tb_elem.vhd +rtl/vhdl/chip-e.vhd +rtl/vhdl/chip-full-a.vhd +rtl/vhdl/spi_boot.vhd +rtl/vhdl/spi_counter.vhd +rtl/vhdl/spi_counter-c.vhd +rtl/vhdl/spi_boot-c.vhd +rtl/vhdl/chip-full-c.vhd +bench/vhdl/card.vhd +bench/vhdl/card-c.vhd +bench/vhdl/tb_elem-full-c.vhd +rtl/vhdl/chip-mmc-a.vhd +rtl/vhdl/chip-mmc-c.vhd +bench/vhdl/tb_elem-mmc-c.vhd +rtl/vhdl/chip-sd-a.vhd +rtl/vhdl/chip-sd-c.vhd +bench/vhdl/tb_elem-sd-c.vhd +rtl/vhdl/chip-minimal-a.vhd +rtl/vhdl/chip-minimal-c.vhd +bench/vhdl/tb_elem-minimal-c.vhd +bench/vhdl/tb-c.vhd +bench/vhdl/tb_rl.vhd +rtl/vhdl/sample/ram_loader.vhd +rtl/vhdl/sample/ram_loader-c.vhd +bench/vhdl/tb_rl-c.vhd diff --git a/usrp2/fpga/opencores/spi_boot/COPYING b/usrp2/fpga/opencores/spi_boot/COPYING new file mode 100644 index 00000000..60549be5 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) 19yy + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/usrp2/fpga/opencores/spi_boot/CVS/Entries b/usrp2/fpga/opencores/spi_boot/CVS/Entries new file mode 100644 index 00000000..d339433f --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/CVS/Entries @@ -0,0 +1,9 @@ +/COMPILE_LIST/1.2/Thu Apr 14 21:26:22 2005// +/COPYING/1.1/Tue Feb 8 20:14:49 2005// +/KNOWN_BUGS/1.1/Sun Feb 13 18:28:35 2005// +/README/1.12/Thu Apr 14 21:32:58 2005// +D/bench//// +D/doc//// +D/rtl//// +D/sim//// +D/sw//// diff --git a/usrp2/fpga/opencores/spi_boot/CVS/Repository b/usrp2/fpga/opencores/spi_boot/CVS/Repository new file mode 100644 index 00000000..6aa579d4 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/CVS/Repository @@ -0,0 +1 @@ +spi_boot diff --git a/usrp2/fpga/opencores/spi_boot/CVS/Root b/usrp2/fpga/opencores/spi_boot/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/CVS/Template b/usrp2/fpga/opencores/spi_boot/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/KNOWN_BUGS b/usrp2/fpga/opencores/spi_boot/KNOWN_BUGS new file mode 100644 index 00000000..298e4ba2 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/KNOWN_BUGS @@ -0,0 +1,4 @@ + +Known bugs of the spi_boot core +=============================== +Version: $Date: 2005/02/13 18:28:35 $ diff --git a/usrp2/fpga/opencores/spi_boot/README b/usrp2/fpga/opencores/spi_boot/README new file mode 100644 index 00000000..926b35bf --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/README @@ -0,0 +1,170 @@ + +README for the spi_boot core +============================ +Version: $Date: 2005/04/14 21:32:58 $ + + +Description +----------- + +The SD/MMC Bootloader is a CPLD design that manages configuration and +bootstrapping of FPGAs. It is able to retrieve the required data from +SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA +configuration process. SD cards as well as MMCs are operated in SPI mode which +is part of both standards thus eliminating the need for dedicated +implementations. The SD/MMC Bootloader fits both. Beyond configuration, this +core supports a bootstrapping strategy where multiple images are stored on one +single memory card. +For example consider a system completely based on SRAM. The bootloader +provides the initial configuration data from the first image to the FPGA. This +image contains a design which pulls the next image from the memory card and +transfers this data to SRAM. In the third step the final FPGA design is loaded +from the third image. +These images are clustered in sets which can be selected by external switches +for example. Several configuration sets can be stored on one memory card +allowing you to provide a number of applications which are downloaded quickly +to the FPGA. +The schematic (rev. B) shows how the core can be used with an FPGA board. I +use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300 +board. SV2 fits the "SERIAL MODE" connector on this board but you will have to +add a separate wire from R6 to attach INIT. Please check the proper use of the +pull-up resistors for your specific board. + + +Features +-------- + +* Configuration mode: configures SRAM based FPGAs via slave serial mode + (Xilinx and Altera) +* Data mode: provides stored data over a simple synchronous serial interface +* Broad compatability using SPI mode + + SecureDigital cards using dedicated initialization command + + MultiMediaCards (see below) +* Operation triggerd by power-up or card insertion +* Multiple configuration sets stored on on single memory card + + +Compatability +------------- + +These cards have been tested with the SD/MMC Bootloader: + + * Hama 64 MB SD + * SanDisk 128 MB SD + * SanDisk 64 MB MMC + * Panasonic 32 MB SD + +Some MMC might fail with this core as not all cards support CMD18 +(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific +model. In case your MMC does not implement CMD18 you might want to have a look +at the FPGA MMC-Card Config project. + + +Tools +----- + +Downloading the configuration data to the card is a straight forward +process. The images have to be written starting at dedicated locations. For +the provided toplevel designs, these locations are multiples of 256 K. I.e. 0, +0x40000, 0x80000 and so forth. + +dd (part of the GNU coreutils) serves this purpose: +$ dd if=ram_loader.bin of=/dev/sdX bs=512 +$ dd if=pongrom_6.bin of=/dev/sdX bs=512 seek=512 +$ dd if=pacman.bin of=/dev/sdX bs=512 seek=1024 + +The name of the device node depends on how the card reader is attached to the +kernel. For Linux systems this is most often something like /dev/sdX with X +ranging from a-z. Please note that it is essential to use the device without +any trailing numbers as they refer to partitions leading to wrong offsets for +data written to the card. +All this works perfectly for my Spartan IIe device as this FPGA expects the +configuration data as it is delivered from the card: Consecutive bytes each +with its most significant bit first. Altera devices like the FLEX family are +different here. They expect the bytes with least significant bit +first. Therefore, the configuration data has to be swapped bitwise before it +is written to the card. + + +Verification +------------ + +The spi_boot core comes with a simple testbench that simulates an SD/MMC +card. All four implementations of the core are verified there in parallel +while transferring the data for several sets. +You should normally not need to run the testbench. But in case you modified +the VHDL code the testbench gives some hints if the design has been broken. + + +Directory Structure +------------------- + +The core's directory structure follows the proposal of OpenCores.org. + +spi_boot + | + \--+-- doc : Documentation + | | + | \-- src : Source files of documentation + | + +-- rtl + | | + | \-- vhdl : VHDL code containing the RTL description + | of the core. + | + +-- bench + | | + | \-- vhdl : VHDL testbench code. + | + \-- sim + | + \-- rtl_sim : Directory for running simulations. + + +RAM Loader +---------- + +Directory rtl/vhdl/ram_loader contains the sample design which loads the next +image from the card and stores its contents to external asynchronous +RAM. After reading 64 KB it triggers a new configuration process for the final +FPGA design. +Refer to the code for the mechanisms involved. + + +Compiling the VHDL Code +----------------------- + +VHDL compilation and simulation tasks take place inside in sim/rtl_sim +directory. The project setup supports only the GHDL simulator (see +http://ghdl.free.fr). + +To compile the code simply type at the shell + +$ make + +This should result in a file called tb_behav_c0 which can be executed as any +other executable. + +The basic simple sequence list can be found in COMPILE_LIST. This can be +useful to quickly set up the analyze stage of any compiler or +synthesizer. Especially when synthesizing the code, you want to skip the VHDL +configurations in *-c.vhd and everything below the bench/ directory. + + +References +---------- + + * SanDisk SD Card Product Manual + http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf + + * SanDisk MMC Product Manual + http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf + + * Toshiba SD Card Specification + http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf + + * BurchED + http://burched.biz/ + + * FPGA MMC-Card Config project + http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview diff --git a/usrp2/fpga/opencores/spi_boot/bench/CVS/Entries b/usrp2/fpga/opencores/spi_boot/bench/CVS/Entries new file mode 100644 index 00000000..a4756ee6 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/CVS/Entries @@ -0,0 +1 @@ +D/vhdl//// diff --git a/usrp2/fpga/opencores/spi_boot/bench/CVS/Repository b/usrp2/fpga/opencores/spi_boot/bench/CVS/Repository new file mode 100644 index 00000000..ac45542a --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/CVS/Repository @@ -0,0 +1 @@ +spi_boot/bench diff --git a/usrp2/fpga/opencores/spi_boot/bench/CVS/Root b/usrp2/fpga/opencores/spi_boot/bench/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/bench/CVS/Template b/usrp2/fpga/opencores/spi_boot/bench/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Entries b/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Entries new file mode 100644 index 00000000..8649c9f9 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Entries @@ -0,0 +1,13 @@ +/card-c.vhd/1.1/Tue Feb 8 21:09:18 2005// +/card.vhd/1.2/Sun Feb 13 17:06:22 2005// +/tb-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem-full-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem-minimal-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem-mmc-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem-sd-c.vhd/1.1/Tue Feb 8 21:09:20 2005// +/tb_elem.vhd/1.7/Thu Apr 7 20:43:36 2005// +/tb_pack-p.vhd/1.2/Tue Mar 8 22:06:39 2005// +/tb_rl-c.vhd/1.1/Sun Apr 10 18:07:26 2005// +/tb_rl.vhd/1.1/Sun Apr 10 18:07:25 2005// +D diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Repository b/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Repository new file mode 100644 index 00000000..ce62c2b8 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Repository @@ -0,0 +1 @@ +spi_boot/bench/vhdl diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Root b/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Template b/usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/card-c.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/card-c.vhd new file mode 100644 index 00000000..797eb1c9 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/card-c.vhd @@ -0,0 +1,14 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: card-c.vhd,v 1.1 2005/02/08 21:09:18 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration card_behav_c0 of card is + + for behav + end for; + +end card_behav_c0; diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/card.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/card.vhd new file mode 100644 index 00000000..dcd67609 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/card.vhd @@ -0,0 +1,446 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Simple SD and MMC model +-- +-- $Id: card.vhd,v 1.2 2005/02/13 17:06:22 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity card is + + generic ( + card_type_g : string := "none"; + is_sd_card_g : integer := 1 + ); + + port ( + spi_clk_i : in std_logic; + spi_cs_n_i : in std_logic; + spi_data_i : in std_logic; + spi_data_o : out std_logic + ); + +end card; + + +library ieee; +use ieee.numeric_std.all; +library std; +use std.textio.all; + +use work.tb_pack.all; + +architecture behav of card is + + signal power_on_n_s : std_logic; + signal soft_res_n_s : std_logic; + signal res_n_s : std_logic; + + signal rx_s : std_logic_vector(47 downto 0); + + signal set_spi_mode_s, + spi_mode_q : boolean; + signal set_idle_mode_s, + poll_idle_mode_s : boolean; + signal idle_mode_q : natural; + + signal block_len_q, + block_len_s : unsigned(31 downto 0); + signal set_block_len_s : boolean; + + signal new_read_addr_s, + read_addr_q : unsigned(31 downto 0); + signal set_read_addr_s, + inc_read_addr_s : boolean; + + signal cmd_spi_data_s, + read_spi_data_s : std_logic; + signal start_read_s : boolean; + signal reading_s : boolean; + + procedure rise_clk is + begin + wait until spi_clk_i'event and to_X01(spi_clk_i) = '1'; + end rise_clk; + +-- procedure rise_clk(num : natural) is +-- begin +-- for i in 1 to num loop +-- rise_clk; +-- end loop; +-- end rise_clk; + + procedure fall_clk is + begin + wait until spi_clk_i'event and to_X01(spi_clk_i) = '0'; + end fall_clk; + + procedure fall_clk(num : natural) is + begin + for i in 1 to num loop + fall_clk; + end loop; + end fall_clk; + +begin + + res_n_s <= power_on_n_s and soft_res_n_s; + + ----------------------------------------------------------------------------- + -- Power on reset + ----------------------------------------------------------------------------- + por: process + begin + power_on_n_s <= '0'; + wait for 200 ns; + power_on_n_s <= '1'; + wait; + end process por; + + + ----------------------------------------------------------------------------- + -- + ctrl: process + + function check_crc(payload : in std_logic_vector(47 downto 0)) + return boolean is + + begin + + return calc_crc(payload(47 downto 8)) = payload(7 downto 1); + end check_crc; + + variable rx_v : std_logic_vector(47 downto 0); + variable cmd_v : std_logic_vector( 5 downto 0); + variable arg_v : std_logic_vector(31 downto 0); + variable crc_v : std_logic_vector( 6 downto 0); + variable wrong_v : std_logic; + variable read_data_v : boolean; + + begin + rx_s <= (others => '0'); + set_spi_mode_s <= false; + set_idle_mode_s <= false; + poll_idle_mode_s <= false; + cmd_spi_data_s <= '1'; + soft_res_n_s <= '1'; + set_block_len_s <= false; + block_len_s <= (others => '0'); + new_read_addr_s <= (others => '0'); + set_read_addr_s <= false; + start_read_s <= false; + read_data_v := false; + + loop + + rise_clk; + -- wait for startbit of command + while to_X01(spi_data_i) = '1' loop + rise_clk; + end loop; + rx_v(47) := '0'; + + -- read remaining 47 bits of command + for i in 46 downto 0 loop + rise_clk; + rx_v(i) := to_X01(spi_data_i); + end loop; + rx_s <= rx_v; + + -- dissect received data + cmd_v := rx_v(45 downto 40); + arg_v := rx_v(39 downto 8); + crc_v := rx_v( 7 downto 1); + + assert spi_mode_q or check_crc(payload => rx_v) + report "CRC mismatch" + severity error; + + wrong_v := '0'; + case cmd_v is + -- CMD0: GO_IDLE_STATE ------------------------------------------------ + when "000000" => + set_spi_mode_s <= true; + set_idle_mode_s <= true; + -- CMD1: SEND_OP_COND ------------------------------------------------- + when "000001" => + poll_idle_mode_s <= true; + -- CMD12: STOP_TRANSMISSION ------------------------------------------- + when "001100" => + start_read_s <= false; + read_data_v := false; + -- CMD16: SET_BLOCKLEN ------------------------------------------------ + when "010000" => + block_len_s <= unsigned(arg_v); + set_block_len_s <= true; + -- CMD18: READ_MULTIPLE_BLOCK ----------------------------------------- + when "010010" => + new_read_addr_s <= unsigned(arg_v); + set_read_addr_s <= true; + read_data_v := true; + -- CMD55: APPL_CMD ---------------------------------------------------- + when "110111" => + -- command only available for SD card + if is_sd_card_g /= 1 then + wrong_v := '1'; + end if; + -- ACMD41: SEND_OP_COND ----------------------------------------------- + when "101001" => + -- command only available for SD card + if is_sd_card_g /= 1 then + wrong_v := '1'; + else + poll_idle_mode_s <= true; + end if; + + when others => + wrong_v := '1'; + null; + end case; + + + -- spend some time before removing control signals + fall_clk(2); + poll_idle_mode_s <= false; + set_idle_mode_s <= false; + fall_clk(6); + set_spi_mode_s <= false; + set_block_len_s <= false; + set_read_addr_s <= false; + + if reading_s then + wait until not reading_s; + end if; + + + -- wait for a total two "bytes" before sending out response + for i in 1 to 8 loop + fall_clk; + end loop; + + for i in 7 downto 0 loop + fall_clk; + case i is + when 2 => + cmd_spi_data_s <= wrong_v; + when 0 => + if idle_mode_q = 0 then + cmd_spi_data_s <= '0'; + else + cmd_spi_data_s <= '1'; + end if; + when others => + cmd_spi_data_s <= '0'; + end case; + end loop; + fall_clk; + cmd_spi_data_s <= '1'; + + -- transmit data if requested + start_read_s <= read_data_v; + + end loop; + end process ctrl; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- + seq: process (res_n_s, + spi_clk_i, + set_spi_mode_s, + set_idle_mode_s, + poll_idle_mode_s, + set_block_len_s, + block_len_s) + + begin + if res_n_s = '0' then + spi_mode_q <= false; + idle_mode_q <= 5; + block_len_q <= (others => '0'); + read_addr_q <= (others => '0'); + + elsif spi_clk_i'event and spi_clk_i = '1' then + if set_spi_mode_s then + spi_mode_q <= true; + end if; + + if set_idle_mode_s then + idle_mode_q <= 5; + elsif poll_idle_mode_s then + if idle_mode_q > 0 then + idle_mode_q <= idle_mode_q - 1; + end if; + end if; + + if set_block_len_s then + block_len_q <= block_len_s; + end if; + + if set_read_addr_s then + read_addr_q <= new_read_addr_s; + elsif inc_read_addr_s then + read_addr_q <= read_addr_q + 1; + end if; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- + read_block: process + + variable t_v : unsigned(7 downto 0); + + begin + -- default assignments + inc_read_addr_s <= false; + reading_s <= false; + read_spi_data_s <= '1'; + + loop + if not start_read_s then + wait until start_read_s; + end if; + + reading_s <= true; + + fall_clk(8); -- delay for one "byte" + + -- send data token + fall_clk(7); -- 7 ones in a data token + read_spi_data_s <= '0'; + + -- send payload + payload: for i in 0 to to_integer(block_len_q)-1 loop + t_v := read_addr_q(0) & calc_crc(read_addr_q); + for bit in 7 downto 0 loop + fall_clk; + read_spi_data_s <= t_v(bit); + + exit payload when not start_read_s; + end loop; + inc_read_addr_s <= true; + rise_clk; + inc_read_addr_s <= false; + wait for 10 ns; + end loop; + + if start_read_s then + -- send crc + for i in 0 to 15 loop + fall_clk; + t_v := to_unsigned(i, 8); + read_spi_data_s <= t_v(0); + end loop; + fall_clk; + end if; + + read_spi_data_s <= '1'; + reading_s <= false; + -- loop for one "byte" + fall_clk(8); + + end loop; + end process read_block; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- + clk_check: process (spi_clk_i) + + variable last_rising_v : time := 0 ns; + variable dump_line : line; + + begin + if spi_clk_i'event and spi_clk_i = '1' then + if is_sd_card_g = 0 and card_type_g /= "Minimal Chip" and + idle_mode_q > 0 then + if now - last_rising_v < 2.5 us and last_rising_v > 0 ns then + write(dump_line, card_type_g); + write(dump_line, string'(" @ ")); + write(dump_line, now); + write(dump_line, string'(": Last rising edge of SPI clock ")); + write(dump_line, now - last_rising_v); + write(dump_line, string'(" ago.")); + writeline(output, dump_line); + end if; + + last_rising_v := now; + end if; + end if; + end process clk_check; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + spi_data_o <= cmd_spi_data_s and read_spi_data_s + when spi_cs_n_i = '0' else + 'Z'; + +end behav; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: card.vhd,v $ +-- Revision 1.2 2005/02/13 17:06:22 arniml +-- handle termination properly +-- +-- Revision 1.1 2005/02/08 21:09:20 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb-c.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb-c.vhd new file mode 100644 index 00000000..caa17136 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb-c.vhd @@ -0,0 +1,31 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_behav_c0 of tb is + + for behav + + for tb_elem_full_b : tb_elem + use configuration work.tb_elem_behav_full; + end for; + + for tb_elem_mmc_b : tb_elem + use configuration work.tb_elem_behav_mmc; + end for; + + for tb_elem_sd_b : tb_elem + use configuration work.tb_elem_behav_sd; + end for; + + for tb_elem_minimal_b : tb_elem + use configuration work.tb_elem_behav_minimal; + end for; + + end for; + +end tb_behav_c0; diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb.vhd new file mode 100644 index 00000000..b359fa7c --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb.vhd @@ -0,0 +1,201 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Testbench +-- +-- $Id: tb.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +entity tb is + +end tb; + + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb is + + component tb_elem + generic ( + chip_type_g : string := "none"; + has_sd_card_g : integer := 1 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + eos_o : out boolean + ); + end component; + + constant period_c : time := 100 ns; + constant reset_level_c : integer := 0; + + signal clk_s : std_logic; + signal reset_s : std_logic; + + signal eos_full_s, + eos_mmc_s, + eos_sd_s, + eos_minimal_s : boolean; + +begin + + + ----------------------------------------------------------------------------- + -- Testbench element including full featured chip + ----------------------------------------------------------------------------- + tb_elem_full_b : tb_elem + generic map ( + chip_type_g => "Full Chip", + has_sd_card_g => 1 + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + eos_o => eos_full_s + ); + + + ----------------------------------------------------------------------------- + -- Testbench element including MMC chip + ----------------------------------------------------------------------------- + tb_elem_mmc_b : tb_elem + generic map ( + chip_type_g => "MMC Chip", + has_sd_card_g => 0 + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + eos_o => eos_mmc_s + ); + + + ----------------------------------------------------------------------------- + -- Testbench element including SD chip + ----------------------------------------------------------------------------- + tb_elem_sd_b : tb_elem + generic map ( + chip_type_g => "SD Chip", + has_sd_card_g => 1 + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + eos_o => eos_sd_s + ); + + + ----------------------------------------------------------------------------- + -- Testbench element including cip with minimal features + ----------------------------------------------------------------------------- + tb_elem_minimal_b : tb_elem + generic map ( + chip_type_g => "Minimal Chip", + has_sd_card_g => 0 + ) + port map ( + clk_i => clk_s, + reset_i => reset_s, + eos_o => eos_minimal_s + ); + + + ----------------------------------------------------------------------------- + -- Clock Generator + ----------------------------------------------------------------------------- + clk: process + begin + clk_s <= '0'; + wait for period_c / 2; + clk_s <= '1'; + wait for period_c / 2; + end process clk; + + + ----------------------------------------------------------------------------- + -- Reset Generator + ----------------------------------------------------------------------------- + reset: process + begin + if reset_level_c = 0 then + reset_s <= '0'; + else + reset_s <= '1'; + end if; + + wait for period_c * 4 + 10 ns; + + reset_s <= not reset_s; + + wait; + end process reset; + + + ----------------------------------------------------------------------------- + -- End Of Simulation Detection + ----------------------------------------------------------------------------- + eos: process (eos_full_s, + eos_mmc_s, + eos_sd_s, + eos_minimal_s) + begin + + if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then + assert false + report "End of Simulation." + severity failure; + end if; + + end process eos; + +end behav; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: tb.vhd,v $ +-- Revision 1.1 2005/02/08 21:09:20 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd new file mode 100644 index 00000000..3c0fb902 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_elem-full-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_elem_behav_full of tb_elem is + + for behav + + for dut_b : chip + use configuration work.chip_full_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + end for; + +end tb_elem_behav_full; diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd new file mode 100644 index 00000000..1c33ac3d --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_elem-minimal-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_elem_behav_minimal of tb_elem is + + for behav + + for dut_b : chip + use configuration work.chip_minimal_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + end for; + +end tb_elem_behav_minimal; diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd new file mode 100644 index 00000000..b5baf604 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_elem-mmc-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_elem_behav_mmc of tb_elem is + + for behav + + for dut_b : chip + use configuration work.chip_mmc_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + end for; + +end tb_elem_behav_mmc; diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd new file mode 100644 index 00000000..9cdf3eaa --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd @@ -0,0 +1,23 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_elem-sd-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_elem_behav_sd of tb_elem is + + for behav + + for dut_b : chip + use configuration work.chip_sd_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + end for; + +end tb_elem_behav_sd; diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem.vhd new file mode 100644 index 00000000..689cec03 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem.vhd @@ -0,0 +1,376 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Generic testbench element for a specific feature set +-- +-- $Id: tb_elem.vhd,v 1.7 2005/04/07 20:43:36 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity tb_elem is + + generic ( + chip_type_g : string := "none"; + has_sd_card_g : integer := 1 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + eos_o : out boolean + ); + +end tb_elem; + + +library ieee; +use ieee.numeric_std.all; +library std; +use std.textio.all; + +use work.spi_boot_pack.all; +use work.tb_pack.all; + +architecture behav of tb_elem is + + component chip + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_n_i : in std_logic_vector(3 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + component card + generic ( + card_type_g : string := "none"; + is_sd_card_g : integer := 1 + ); + port ( + spi_clk_i : in std_logic; + spi_cs_n_i : in std_logic; + spi_data_i : in std_logic; + spi_data_o : out std_logic + ); + end component; + + signal reset_s : std_logic; + + -- SPI interface signals + signal spi_clk_s : std_logic; + signal spi_data_to_card_s : std_logic; + signal spi_data_from_card_s : std_logic; + signal spi_cs_n_s : std_logic; + + -- config related signals + signal start_s : std_logic; + signal mode_s : std_logic; + signal config_n_s : std_logic; + signal cfg_init_n_s : std_logic; + signal cfg_done_s : std_logic; + signal dat_done_s : std_logic; + signal cfg_clk_s : std_logic; + signal cfg_dat_s : std_logic; + signal data_s : unsigned(7 downto 0); + + signal set_sel_n_s : std_logic_vector(3 downto 0); + + constant verbose_c : boolean := false; + +begin + + -- weak pull-ups + spi_clk_s <= 'H'; + spi_cs_n_s <= 'H'; + spi_data_to_card_s <= 'H'; + + ----------------------------------------------------------------------------- + -- DUT + ----------------------------------------------------------------------------- + dut_b : chip + port map ( + clk_i => clk_i, + reset_i => reset_s, + set_sel_n_i => set_sel_n_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_from_card_s, + spi_data_out_o => spi_data_to_card_s, + start_i => start_s, + mode_i => mode_s, + config_n_o => config_n_s, + detached_o => open, + cfg_init_n_i => cfg_init_n_s, + cfg_done_i => cfg_done_s, + dat_done_i => dat_done_s, + cfg_clk_o => cfg_clk_s, + cfg_dat_o => cfg_dat_s + ); + + card_b : card + generic map ( + card_type_g => chip_type_g, + is_sd_card_g => has_sd_card_g + ) + port map ( + spi_clk_i => spi_clk_s, + spi_cs_n_i => spi_cs_n_s, + spi_data_i => spi_data_to_card_s, + spi_data_o => spi_data_from_card_s + ); + + + ----------------------------------------------------------------------------- + -- DUT Stimuli + -- + stim: process + + procedure rise_cfg_clk(num : integer) is + begin + for i in 1 to num loop + wait until cfg_clk_s'event and cfg_clk_s = '1'; + end loop; + end rise_cfg_clk; + +-- procedure fall_cfg_clk(num : integer) is +-- begin +-- for i in 1 to num loop +-- wait until cfg_clk_s'event and cfg_clk_s = '0'; +-- end loop; +-- end fall_cfg_clk; + + procedure rise_clk(num : integer) is + begin + for i in 1 to num loop + wait until clk_i'event and clk_i = '1'; + end loop; + end rise_clk; + + procedure read_check_byte(ref : unsigned(7 downto 0)) is + variable byte_v : unsigned(7 downto 0); + variable dump_line : line; + begin + for bit in 7 downto 0 loop + rise_cfg_clk(1); + byte_v(bit) := cfg_dat_s; + end loop; + data_s <= byte_v; + + if byte_v /= ref then + write(dump_line, chip_type_g); + write(dump_line, string'(" at ")); + write(dump_line, now); + write(dump_line, string'(": read_check_byte failed ")); + write(dump_line, to_integer(byte_v)); + write(dump_line, string'(" ")); + write(dump_line, to_integer(ref)); + writeline(output, dump_line); + end if; + end read_check_byte; + + variable dump_line : line; + variable addr_v : unsigned(31 downto 0); + variable temp_v : unsigned( 7 downto 0); + variable set_sel_v : unsigned(3 downto 0); + + begin + -- default assignments + -- these defaults show the required pull resistors + -- except start_i as this must be pulled high for automatic start + start_s <= '0'; + mode_s <= '1'; + cfg_init_n_s <= '1'; + cfg_done_s <= '0'; + dat_done_s <= '1'; + data_s <= (others => '1'); + addr_v := (others => '0'); + eos_o <= false; + set_sel_n_s <= (others => '1'); + reset_s <= '0'; + + -- loop through some sets + for set in 0 to 3 loop + set_sel_v := to_unsigned(set, 4); + addr_v(23 downto 20) := set_sel_v; -- must match num_bits_per_img_g + -- plus width_img_cnt_g + set_sel_n_s <= not std_logic_vector(set_sel_v); + + assert not verbose_c + report chip_type_g & ": Processing set " & to_string(set) + severity note; + + wait for 100 us; + reset_s <= '1'; + + assert not verbose_c + report chip_type_g & ": Requesting image 0" + severity note; + + -- signal start + start_s <= '1'; + mode_s <= '1'; + cfg_done_s <= '0'; + addr_v(19 downto 0) := (others => '0'); + wait until config_n_s = '0'; + -- run through configuration sequence + rise_clk(1); + cfg_init_n_s <= '0'; + rise_clk(3); + cfg_init_n_s <= '1'; + + -- and receive 32 bytes from image 0 + for i in 1 to 32 loop + temp_v := addr_v(0) & calc_crc(addr_v); + read_check_byte(temp_v); + addr_v := addr_v + 1; + end loop; + start_s <= '0'; + cfg_done_s <= '1'; + + rise_clk(10); + + assert not verbose_c + report chip_type_g & ": Requesting image 1" + severity note; + + -- request next image + mode_s <= '0'; + start_s <= '1'; + addr_v(17 downto 0) := (others => '0'); + addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd + dat_done_s <= '0'; + + -- receive another 32 bytes from image 1 + for i in 1 to 32 loop + temp_v := addr_v(0) & calc_crc(addr_v); + read_check_byte(temp_v); + addr_v := addr_v + 1; + end loop; + start_s <= '0'; + dat_done_s <= '1'; + + + rise_clk(10); + + assert not verbose_c + report chip_type_g & ": Requesting image 2" + severity note; + + -- request next image + mode_s <= '1'; + start_s <= '1'; + addr_v(17 downto 0) := (others => '0'); + addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd + + wait until config_n_s = '0'; + -- run through configuration sequence + rise_clk(1); + cfg_done_s <= '0'; + cfg_init_n_s <= '0'; + rise_clk(3); + cfg_init_n_s <= '1'; + + -- receive another 32 bytes from image 2 + for i in 1 to 32 loop + temp_v := addr_v(0) & calc_crc(addr_v); + read_check_byte(temp_v); + addr_v := addr_v + 1; + end loop; + start_s <= '0'; + cfg_done_s <= '1'; + + -- give dut a chance to stop current transfer + wait until spi_cs_n_s = '1'; + rise_clk(10); + + reset_s <= '0'; + end loop; + + eos_o <= true; + wait; + end process stim; + -- + ----------------------------------------------------------------------------- + +end behav; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: tb_elem.vhd,v $ +-- Revision 1.7 2005/04/07 20:43:36 arniml +-- add new port detached_o +-- +-- Revision 1.6 2005/03/09 19:48:04 arniml +-- make verbosity level switchable +-- +-- Revision 1.5 2005/03/08 22:06:21 arniml +-- added set selection +-- +-- Revision 1.4 2005/02/17 18:59:23 arniml +-- clarify wording for images +-- +-- Revision 1.3 2005/02/16 19:34:56 arniml +-- add weak pull-ups for SPI lines +-- +-- Revision 1.2 2005/02/13 17:14:03 arniml +-- change dat_done handling +-- +-- Revision 1.1 2005/02/08 21:09:20 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd new file mode 100644 index 00000000..7534aafd --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd @@ -0,0 +1,93 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_pack-p.vhd,v 1.2 2005/03/08 22:06:39 arniml Exp $ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package tb_pack is + + function calc_crc(payload : in std_logic_vector) return std_logic_vector; + function calc_crc(payload : in unsigned) return unsigned; + + function to_string(value : in integer) return string; + +end tb_pack; + + +package body tb_pack is + + function calc_crc(payload : in std_logic_vector) return std_logic_vector is + + variable crc_v : std_logic_vector(6 downto 0); + variable temp_v : std_logic; + + begin + + crc_v := (others => '0'); + + for i in payload'high downto payload'low loop + temp_v := payload(i) xor crc_v(6); + + crc_v(6 downto 4) := crc_v(5 downto 3); + crc_v(3) := crc_v(2) xor temp_v; + crc_v(2 downto 1) := crc_v(1 downto 0); + crc_v(0) := temp_v; + end loop; + + return crc_v; + end calc_crc; + + function calc_crc(payload : in unsigned) return unsigned is + begin + return unsigned(calc_crc(std_logic_vector(payload))); + end calc_crc; + + function to_string(value : in integer) return string is + variable str: string (11 downto 1); + variable val: integer := value; + variable digit: natural; + variable index: natural := 0; + begin + -- Taken from: + -- textio package body. This file is part of GHDL. + -- Copyright (C) 2002 Tristan Gingold. + -- Note: the absolute value of VAL cannot be directly taken, since + -- it may be greather that the maximum value of an INTEGER. + loop + -- LRM93 7.2.6 + -- (A rem B) has the sign of A and an absolute value less then + -- the absoulte value of B. + digit := abs (val rem 10); + val := val / 10; + index := index + 1; + str (index) := character'val(48 + digit); + exit when val = 0; + end loop; + if value < 0 then + index := index + 1; + str(index) := '-'; + end if; + + return str; + end to_string; + +end tb_pack; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: tb_pack-p.vhd,v $ +-- Revision 1.2 2005/03/08 22:06:39 arniml +-- added integer->string conversion function +-- +-- Revision 1.1 2005/02/08 21:09:20 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd new file mode 100644 index 00000000..84273abc --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd @@ -0,0 +1,27 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: tb_rl-c.vhd,v 1.1 2005/04/10 18:07:26 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration tb_rl_behav_c0 of tb_rl is + + for behav + + for dut_b : chip + use configuration work.chip_full_c0; + end for; + + for card_b : card + use configuration work.card_behav_c0; + end for; + + for rl_b : ram_loader + use configuration work.ram_loader_rtl_c0; + end for; + + end for; + +end tb_rl_behav_c0; diff --git a/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl.vhd b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl.vhd new file mode 100644 index 00000000..9f28e62b --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl.vhd @@ -0,0 +1,259 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Testbench for ram_loader +-- +-- $Id: tb_rl.vhd,v 1.1 2005/04/10 18:07:25 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +entity tb_rl is + +end tb_rl; + + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_rl is + + component chip + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_n_i : in std_logic_vector(3 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + component card + generic ( + card_type_g : string := "none"; + is_sd_card_g : integer := 1 + ); + port ( + spi_clk_i : in std_logic; + spi_cs_n_i : in std_logic; + spi_data_i : in std_logic; + spi_data_o : out std_logic + ); + end component; + + component ram_loader + port ( + clk_i : in std_logic; + reset_i : in std_logic; + lamp_o : out std_logic; + cfg_clk_i : in std_logic; + cfg_data_i : in std_logic; + start_o : out std_logic; + mode_o : out std_logic; + done_o : out std_logic; + detached_i : in std_logic; + ram_addr_o : out std_logic_vector(15 downto 0); + ram_data_b : out std_logic_vector( 7 downto 0); + ram_ce_no : out std_logic_vector( 3 downto 0); + ram_oe_no : out std_logic; + ram_we_no : out std_logic + ); + end component; + + constant period_c : time := 100 ns; + constant rl_period_c : time := 20 ns; + constant reset_level_c : integer := 0; + + signal clk_s : std_logic; + signal rl_clk_s: std_logic; + signal reset_s : std_logic; + + -- SPI interface signals + signal spi_clk_s : std_logic; + signal spi_data_to_card_s : std_logic; + signal spi_data_from_card_s : std_logic; + signal spi_cs_n_s : std_logic; + + -- config related signals + signal start_s : std_logic; + signal mode_s : std_logic; + signal config_n_s : std_logic; + signal cfg_init_n_s : std_logic; + signal cfg_done_s : std_logic; + signal dat_done_s : std_logic; + signal cfg_clk_s : std_logic; + signal cfg_dat_s : std_logic; + signal detached_s : std_logic; + + signal set_sel_n_s : std_logic_vector(3 downto 0); + +begin + + set_sel_n_s <= (others => '1'); + cfg_init_n_s <= '1'; + cfg_done_s <= '1'; + + ----------------------------------------------------------------------------- + -- DUT + ----------------------------------------------------------------------------- + dut_b : chip + port map ( + clk_i => clk_s, + reset_i => reset_s, + set_sel_n_i => set_sel_n_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_from_card_s, + spi_data_out_o => spi_data_to_card_s, + start_i => start_s, + mode_i => mode_s, + config_n_o => config_n_s, + detached_o => detached_s, + cfg_init_n_i => cfg_init_n_s, + cfg_done_i => cfg_done_s, + dat_done_i => dat_done_s, + cfg_clk_o => cfg_clk_s, + cfg_dat_o => cfg_dat_s + ); + + card_b : card + generic map ( + card_type_g => "Full Chip", + is_sd_card_g => 1 + ) + port map ( + spi_clk_i => spi_clk_s, + spi_cs_n_i => spi_cs_n_s, + spi_data_i => spi_data_to_card_s, + spi_data_o => spi_data_from_card_s + ); + + rl_b : ram_loader + port map ( + clk_i => rl_clk_s, + reset_i => reset_s, + lamp_o => open, + cfg_clk_i => cfg_clk_s, + cfg_data_i => cfg_dat_s, + start_o => start_s, + mode_o => mode_s, + done_o => dat_done_s, + detached_i => detached_s, + ram_addr_o => open, + ram_data_b => open, + ram_ce_no => open, + ram_oe_no => open, + ram_we_no => open + ); + + ----------------------------------------------------------------------------- + -- Clock Generator + ----------------------------------------------------------------------------- + clk: process + begin + clk_s <= '0'; + wait for period_c / 2; + clk_s <= '1'; + wait for period_c / 2; + end process clk; + + rl_clk: process + begin + rl_clk_s <= '0'; + wait for rl_period_c / 2; + rl_clk_s <= '1'; + wait for rl_period_c / 2; + end process rl_clk; + + + ----------------------------------------------------------------------------- + -- Reset Generator + ----------------------------------------------------------------------------- + reset: process + begin + if reset_level_c = 0 then + reset_s <= '0'; + else + reset_s <= '1'; + end if; + + wait for period_c * 4 + 10 ns; + + reset_s <= not reset_s; + + wait; + end process reset; + + + ----------------------------------------------------------------------------- + -- End of Simulation + ----------------------------------------------------------------------------- + eos: process + begin + wait for 4 ms; + assert false + report "No checks have been performed. Investigate waveforms." + severity note; + assert false + report "End of simulation." + severity failure; + end process eos; + +end behav; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: tb_rl.vhd,v $ +-- Revision 1.1 2005/04/10 18:07:25 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/doc/CVS/Entries b/usrp2/fpga/opencores/spi_boot/doc/CVS/Entries new file mode 100644 index 00000000..630615f4 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/doc/CVS/Entries @@ -0,0 +1,3 @@ +/spi_boot.pdf/1.6/Thu Mar 16 17:09:56 2006/-kb/ +/spi_boot_schematic.pdf/1.3/Thu Apr 14 21:20:35 2005/-kb/ +D/src//// diff --git a/usrp2/fpga/opencores/spi_boot/doc/CVS/Repository b/usrp2/fpga/opencores/spi_boot/doc/CVS/Repository new file mode 100644 index 00000000..07fb7884 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/doc/CVS/Repository @@ -0,0 +1 @@ +spi_boot/doc diff --git a/usrp2/fpga/opencores/spi_boot/doc/CVS/Root b/usrp2/fpga/opencores/spi_boot/doc/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/doc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/doc/CVS/Template b/usrp2/fpga/opencores/spi_boot/doc/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/doc/spi_boot.pdf b/usrp2/fpga/opencores/spi_boot/doc/spi_boot.pdf new file mode 100644 index 0000000000000000000000000000000000000000..a889c3f22569aa1bb2a50c2cf864308a8422e9b5 GIT binary patch literal 113923 zcma%hWl$wSvn7MO%iun^ySu|MxVyW%JA=E+;O_1Y7r3~)yE_cF%-emj5&Qkv_v3VC zRb_Sbtv;ERm3_&7iHg%P(KEx6kDSNm!?F`G64@DA!t(Mm$eP%iIhzx4eDx?Yh+9}Y zn>Z3Nh+7*tn~0hi*%_Pg^TRqhJDM2Sz`AEetBl*OF(P-~(LAPsVoa2XKF$}PRB

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zR*(2q;%mU3=--aXid9DIWGG5?F@KNZZ$#;{^Ilo}cD=Lrff1+_RMs{G%8ma1b7~-l zs~=a>D!ajLcVo&%(7ePx1v!%^=1wX$`-DS=Ypx= {1'b0,trigger_level}); + thre_int <= #1 threi_clear ? 0 : ier[`UART_IE_THRE] && lsr[`UART_LS_TFE]; + ms_int <= #1 ier[`UART_IE_MS] && (| msr[3:0]); + ti_int <= #1 ier[`UART_IE_RDA] && (counter_t == 6'b0); + end +end + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + int_o <= #1 1'b0; + else + if (| {rls_int,rda_int,thre_int,ms_int,ti_int}) + int_o <= #1 1'b1; + else + int_o <= #1 1'b0; +end + + +// Interrupt Identification register +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + iir <= #1 1; + else + if (rls_int) // interrupt occured and is enabled (not masked) + begin + iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value + iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending) + end + else + if (rda_int) + begin + iir[`UART_II_II] <= #1 `UART_II_RDA; + iir[`UART_II_IP] <= #1 1'b0; + end + else + if (ti_int) + begin + iir[`UART_II_II] <= #1 `UART_II_TI; + iir[`UART_II_IP] <= #1 1'b0; + end + else + if (thre_int) + begin + iir[`UART_II_II] <= #1 `UART_II_THRE; + iir[`UART_II_IP] <= #1 1'b0; + end + else + if (ms_int) + begin + iir[`UART_II_II] <= #1 `UART_II_MS; + iir[`UART_II_IP] <= #1 1'b0; + end + else // no interrupt is pending + begin + iir[`UART_II_IP] <= #1 1'b1; + end +end + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_top.v b/usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_top.v new file mode 100644 index 00000000..58059fa2 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_top.v @@ -0,0 +1,170 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_top.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core top level. //// +//// //// +//// Known problems (limits): //// +//// Note that transmitter and receiver instances are inside //// +//// the uart_regs.v file. //// +//// //// +//// To Do: //// +//// Nothing so far. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_top.v,v $ +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +`include "timescale.v" +`include "uart_defines.v" + +module uart_top ( + clk, + + // Wishbone signals + wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, + int_o, // interrupt request + + // UART signals + // serial input/output + stx_pad_o, srx_pad_i, + + // modem signals + rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i + + ); + +parameter uart_data_width = 8; +parameter uart_addr_width = `UART_ADDR_WIDTH; + +input clk; + +// WISHBONE interface +input wb_rst_i; +input [uart_addr_width-1:0] wb_addr_i; +input [uart_data_width-1:0] wb_dat_i; +output [uart_data_width-1:0] wb_dat_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +output wb_ack_o; +output int_o; + +// UART signals +input srx_pad_i; +output stx_pad_o; +output rts_pad_o; +input cts_pad_i; +output dtr_pad_o; +input dsr_pad_i; +input ri_pad_i; +input dcd_pad_i; + +wire stx_pad_o; +wire rts_pad_o; +wire dtr_pad_o; + +wire [uart_addr_width-1:0] wb_addr_i; +wire [uart_data_width-1:0] wb_dat_i; +wire [uart_data_width-1:0] wb_dat_o; + +wire we_o; // Write enable for registers +wire re_o; // Read enable for registers +// +// MODULE INSTANCES +// + +//// WISHBONE interface module +uart_wb wb_interface( + .clk( clk ), + .wb_rst_i( wb_rst_i ), + .wb_we_i( wb_we_i ), + .wb_stb_i( wb_stb_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_ack_o( wb_ack_o ), + .we_o( we_o ), + .re_o(re_o) + ); + +// Registers +uart_regs regs( + .clk( clk ), + .wb_rst_i( wb_rst_i ), + .wb_addr_i( wb_addr_i ), + .wb_dat_i( wb_dat_i ), + .wb_dat_o( wb_dat_o ), + .wb_we_i( we_o ), + .wb_re_i(re_o), + .modem_inputs( {cts_pad_i, dsr_pad_i, + ri_pad_i, dcd_pad_i} ), + .stx_pad_o( stx_pad_o ), + .srx_pad_i( srx_pad_i ), + .enable( enable ), + .rts_pad_o( rts_pad_o ), + .dtr_pad_o( dtr_pad_o ), + .int_o( int_o ) + ); + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_transmitter.v b/usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_transmitter.v new file mode 100644 index 00000000..a028f4ed --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_transmitter.v @@ -0,0 +1,288 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_transmitter.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core transmitter logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_transmitter.v,v $ +// Revision 1.6 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.5 2001/06/02 14:28:14 gorban +// Fixed receiver and transmitter. Major bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.1 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +`include "timescale.v" +`include "uart_defines.v" + +module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset); + +input clk; +input wb_rst_i; +input [7:0] lcr; +input tf_push; +input [7:0] wb_dat_i; +input enable; +input tx_reset; +output stx_pad_o; +output [2:0] state; +output [`UART_FIFO_COUNTER_W-1:0] tf_count; + +reg [2:0] state; +reg [4:0] counter; +reg [2:0] bit_counter; // counts the bits to be sent +reg [6:0] shift_out; // output shift register +reg stx_o_tmp; +reg parity_xor; // parity of the word +reg tf_pop; +reg bit_out; + +// TX FIFO instance +// +// Transmitter FIFO signals +wire [`UART_FIFO_WIDTH-1:0] tf_data_in; +wire [`UART_FIFO_WIDTH-1:0] tf_data_out; +wire tf_push; +wire tf_underrun; +wire tf_overrun; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; + +assign tf_data_in = wb_dat_i; + +uart_fifo fifo_tx( // error bit signal is not used in transmitter FIFO + .clk( clk ), + .wb_rst_i( wb_rst_i ), + .data_in( tf_data_in ), + .data_out( tf_data_out ), + .push( tf_push ), + .pop( tf_pop ), + .underrun( tf_underrun ), + .overrun( tf_overrun ), + .count( tf_count ), + .error_bit(), // Ta ni priklopljen. Prej je manjkal, dodal Igor + .fifo_reset( tx_reset ), + .reset_status(1'b0) +); + +// TRANSMITTER FINAL STATE MACHINE + +parameter s_idle = 3'd0; +parameter s_send_start = 3'd1; +parameter s_send_byte = 3'd2; +parameter s_send_parity = 3'd3; +parameter s_send_stop = 3'd4; +parameter s_pop_byte = 3'd5; + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + state <= #1 s_idle; + stx_o_tmp <= #1 1'b1; + counter <= #1 5'b0; + shift_out <= #1 7'b0; + bit_out <= #1 1'b0; + parity_xor <= #1 1'b0; + tf_pop <= #1 1'b0; + bit_counter <= #1 3'b0; + end + else + if (enable) + begin + case (state) + s_idle : if (~|tf_count) // if tf_count==0 + begin + state <= #1 s_idle; + stx_o_tmp <= #1 1'b1; + end + else + begin + tf_pop <= #1 1'b0; + stx_o_tmp <= #1 1'b1; + state <= #1 s_pop_byte; + end + s_pop_byte : begin + tf_pop <= #1 1'b1; + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : begin + bit_counter <= #1 3'b100; + parity_xor <= #1 ^tf_data_out[4:0]; + end + 2'b01 : begin + bit_counter <= #1 3'b101; + parity_xor <= #1 ^tf_data_out[5:0]; + end + 2'b10 : begin + bit_counter <= #1 3'b110; + parity_xor <= #1 ^tf_data_out[6:0]; + end + 2'b11 : begin + bit_counter <= #1 3'b111; + parity_xor <= #1 ^tf_data_out[7:0]; + end + endcase + {shift_out[6:0], bit_out} <= #1 tf_data_out; + state <= #1 s_send_start; + end + s_send_start : begin + tf_pop <= #1 1'b0; + if (~|counter) + counter <= #1 5'b01111; + else + if (counter == 5'b00001) + begin + counter <= #1 0; + state <= #1 s_send_byte; + end + else + counter <= #1 counter - 5'b00001; + stx_o_tmp <= #1 1'b0; + end + s_send_byte : begin + if (~|counter) + counter <= #1 5'b01111; + else + if (counter == 5'b00001) + begin + if (bit_counter > 3'b0) + begin + bit_counter <= #1 bit_counter - 1; + {shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]}; + state <= #1 s_send_byte; + end + else // end of byte + if (~lcr[`UART_LC_PE]) + begin + state <= #1 s_send_stop; + end + else + begin + case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) + 2'b00: bit_out <= #1 parity_xor; + 2'b01: bit_out <= #1 1'b1; + 2'b10: bit_out <= #1 ~parity_xor; + 2'b11: bit_out <= #1 1'b0; + endcase + state <= #1 s_send_parity; + end + counter <= #1 0; + end + else + counter <= #1 counter - 5'b00001; + stx_o_tmp <= #1 bit_out; // set output pin + end + s_send_parity : begin + if (~|counter) + counter <= #1 5'b01111; + else + if (counter == 5'b00001) + begin + counter <= #1 4'b0; + state <= #1 s_send_stop; + end + else + counter <= #1 counter - 5'b00001; + stx_o_tmp <= #1 bit_out; + end + s_send_stop : begin + if (~|counter) + begin + casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) + 3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor + 3'b100: counter <= #1 5'b10101; // 1.5 stop bit + 3'b1xx: counter <= #1 5'b11101; // 2 stop bits + endcase + end + else + if (counter == 5'b00001) + begin + counter <= #1 0; + state <= #1 s_idle; + end + else + counter <= #1 counter - 5'b00001; + stx_o_tmp <= #1 1'b1; + end + + default : // should never get here + state <= #1 s_idle; + endcase + end // end if enable +end // transmitter logic + +assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_wb.v b/usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_wb.v new file mode 100644 index 00000000..80f712ca --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog-backup/uart_wb.v @@ -0,0 +1,125 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_TX_FIFO.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core WISHBONE interface. //// +//// //// +//// Known problems (limits): //// +//// Inserts one wait state on all transfers. //// +//// Note affected signals and the way they are affected. //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_wb.v,v $ +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/21 19:12:01 gorban +// Corrected some Linter messages. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:13+02 jacob +// Initial revision +// +// + +// UART core WISHBONE interface +// +// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com) +// Company: Flextronics Semiconductor +// + +`include "timescale.v" + +module uart_wb (clk, + wb_rst_i, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, + we_o, re_o // Write and read enable output for the core + + ); + +input clk; + +// WISHBONE interface +input wb_rst_i; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +output wb_ack_o; +output we_o; +output re_o; + +wire we_o; +reg wb_ack_o; + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + wb_ack_o <= #1 1'b0; + end + else + begin +// wb_ack_o <= #1 wb_stb_i & wb_cyc_i; // 1 clock wait state on all transfers + wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers + end +end + +assign we_o = wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers +assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Entries b/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Entries new file mode 100644 index 00000000..92430839 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Entries @@ -0,0 +1,13 @@ +/raminfr.v/1.2/Mon Jul 29 21:16:18 2002// +/timescale.v/1.6/Fri Aug 24 21:01:12 2001// +/uart_debug_if.v/1.5/Mon Jul 29 21:16:18 2002// +/uart_defines.v/1.14/Fri Sep 12 07:26:58 2003// +/uart_receiver.v/1.31/Fri Jun 18 14:46:15 2004// +/uart_regs.v/1.42/Mon Nov 22 09:21:59 2004// +/uart_rfifo.v/1.4/Fri Jul 11 18:20:26 2003// +/uart_sync_flops.v/1.1/Fri May 21 11:43:25 2004// +/uart_tfifo.v/1.2/Mon Jul 29 21:16:18 2002// +/uart_top.v/1.19/Mon Jul 29 21:16:18 2002// +/uart_transmitter.v/1.19/Mon Jul 29 21:16:18 2002// +/uart_wb.v/1.17/Fri May 21 12:35:15 2004// +D diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Repository b/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Repository new file mode 100644 index 00000000..b0efc9db --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Repository @@ -0,0 +1 @@ +uart16550/rtl/verilog diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Root b/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Template b/usrp2/fpga/opencores/uart16550/rtl/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/raminfr.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/raminfr.v new file mode 100644 index 00000000..bd376d5d --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/raminfr.v @@ -0,0 +1,114 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// raminfr.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Inferrable Distributed RAM for FIFOs //// +//// //// +//// Known problems (limits): //// +//// None . //// +//// //// +//// To Do: //// +//// Nothing so far. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// //// +//// Created: 2002/07/22 //// +//// Last Updated: 2002/07/22 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: raminfr.v,v $ +// Revision 1.2 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.1 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// + +//Following is the Verilog code for a dual-port RAM with asynchronous read. +module raminfr + (clk, we, a, dpra, di, dpo); + +parameter addr_width = 4; +parameter data_width = 8; +parameter depth = 16; + +input clk; +input we; +input [addr_width-1:0] a; +input [addr_width-1:0] dpra; +input [data_width-1:0] di; +//output [data_width-1:0] spo; +output [data_width-1:0] dpo; +reg [data_width-1:0] ram [depth-1:0]; + +wire [data_width-1:0] dpo; +wire [data_width-1:0] di; +wire [addr_width-1:0] a; +wire [addr_width-1:0] dpra; + + always @(posedge clk) begin + if (we) + ram[a] <= di; + end +// assign spo = ram[a]; + assign dpo = ram[dpra]; +endmodule + diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/timescale.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/timescale.v new file mode 100644 index 00000000..051ee7a5 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/timescale.v @@ -0,0 +1,64 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// timescale.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Defines of the Core //// +//// //// +//// Known problems (limits): //// +//// None //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// Timescale define + +`timescale 1ns/10ps diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_debug_if.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_debug_if.v new file mode 100644 index 00000000..3c8ac1aa --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_debug_if.v @@ -0,0 +1,129 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_debug_if.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core debug interface. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// //// +//// Created: 2001/12/02 //// +//// (See log for the revision history) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_debug_if.v,v $ +// Revision 1.5 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.4 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.3 2001/12/19 08:40:03 mohor +// Warnings fixed (unused signals removed). +// +// Revision 1.2 2001/12/12 22:17:30 gorban +// some synthesis bugs fixed +// +// Revision 1.1 2001/12/04 21:14:16 gorban +// committed the debug interface file +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_debug_if (/*AUTOARG*/ +// Outputs +wb_dat32_o, +// Inputs +wb_adr_i, ier, iir, fcr, mcr, lcr, msr, +lsr, rf_count, tf_count, tstate, rstate +) ; + +input [`UART_ADDR_WIDTH-1:0] wb_adr_i; +output [31:0] wb_dat32_o; +input [3:0] ier; +input [3:0] iir; +input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored +input [4:0] mcr; +input [7:0] lcr; +input [7:0] msr; +input [7:0] lsr; +input [`UART_FIFO_COUNTER_W-1:0] rf_count; +input [`UART_FIFO_COUNTER_W-1:0] tf_count; +input [2:0] tstate; +input [3:0] rstate; + + +wire [`UART_ADDR_WIDTH-1:0] wb_adr_i; +reg [31:0] wb_dat32_o; + +always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr + or rf_count or rstate or tf_count or tstate or wb_adr_i) + case (wb_adr_i) + // 8 + 8 + 4 + 4 + 8 + 5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr}; + // 5 + 2 + 5 + 4 + 5 + 3 + 5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate}; + default: wb_dat32_o = 0; + endcase // case(wb_adr_i) + +endmodule // uart_debug_if + diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_defines.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_defines.v new file mode 100644 index 00000000..8b372cb5 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_defines.v @@ -0,0 +1,250 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_defines.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Defines of the Core //// +//// //// +//// Known problems (limits): //// +//// None //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_defines.v,v $ +// Revision 1.14 2003/09/12 07:26:58 dries +// adjusted comment + define +// +// Revision 1.13 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.12 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.10 2001/12/11 08:55:40 mohor +// Scratch register define added. +// +// Revision 1.9 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.8 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.7 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.6 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.5 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.4 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.3 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +// remove comments to restore to use the new version with 8 data bit interface +// in 32bit-bus mode, the wb_sel_i signal is used to put data in correct place +// also, in 8-bit version there'll be no debugging features included +// CAUTION: doesn't work with current version of OR1200 +//`define DATA_BUS_WIDTH_8 + +`ifdef DATA_BUS_WIDTH_8 + `define UART_ADDR_WIDTH 3 + `define UART_DATA_WIDTH 8 +`else + `define UART_ADDR_WIDTH 5 + `define UART_DATA_WIDTH 32 +`endif + +// Uncomment this if you want your UART to have +// 16xBaudrate output port. +// If defined, the enable signal will be used to drive baudrate_o signal +// It's frequency is 16xbaudrate + +`define UART_HAS_BAUDRATE_OUTPUT + +// Register addresses +`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer +`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter +`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable +`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification +`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control +`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control +`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control +`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status +`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status +`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register +`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2) +`define UART_REG_DL2 `UART_ADDR_WIDTH'd1 + +// Interrupt Enable register bits +`define UART_IE_RDA 0 // Received Data available interrupt +`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt +`define UART_IE_RLS 2 // Receiver Line Status Interrupt +`define UART_IE_MS 3 // Modem Status Interrupt + +// Interrupt Identification register bits +`define UART_II_IP 0 // Interrupt pending when 0 +`define UART_II_II 3:1 // Interrupt identification + +// Interrupt identification values for bits 3:1 +`define UART_II_RLS 3'b011 // Receiver Line Status +`define UART_II_RDA 3'b010 // Receiver Data available +`define UART_II_TI 3'b110 // Timeout Indication +`define UART_II_THRE 3'b001 // Transmitter Holding Register empty +`define UART_II_MS 3'b000 // Modem Status + +// FIFO Control Register bits +`define UART_FC_TL 1:0 // Trigger level + +// FIFO trigger level values +`define UART_FC_1 2'b00 +`define UART_FC_4 2'b01 +`define UART_FC_8 2'b10 +`define UART_FC_14 2'b11 + +// Line Control register bits +`define UART_LC_BITS 1:0 // bits in character +`define UART_LC_SB 2 // stop bits +`define UART_LC_PE 3 // parity enable +`define UART_LC_EP 4 // even parity +`define UART_LC_SP 5 // stick parity +`define UART_LC_BC 6 // Break control +`define UART_LC_DL 7 // Divisor Latch access bit + +// Modem Control register bits +`define UART_MC_DTR 0 +`define UART_MC_RTS 1 +`define UART_MC_OUT1 2 +`define UART_MC_OUT2 3 +`define UART_MC_LB 4 // Loopback mode + +// Line Status Register bits +`define UART_LS_DR 0 // Data ready +`define UART_LS_OE 1 // Overrun Error +`define UART_LS_PE 2 // Parity Error +`define UART_LS_FE 3 // Framing Error +`define UART_LS_BI 4 // Break interrupt +`define UART_LS_TFE 5 // Transmit FIFO is empty +`define UART_LS_TE 6 // Transmitter Empty indicator +`define UART_LS_EI 7 // Error indicator + +// Modem Status Register bits +`define UART_MS_DCTS 0 // Delta signals +`define UART_MS_DDSR 1 +`define UART_MS_TERI 2 +`define UART_MS_DDCD 3 +`define UART_MS_CCTS 4 // Complement signals +`define UART_MS_CDSR 5 +`define UART_MS_CRI 6 +`define UART_MS_CDCD 7 + +// FIFO parameter defines + +`define UART_FIFO_WIDTH 8 +`define UART_FIFO_DEPTH 16 +`define UART_FIFO_POINTER_W 4 +`define UART_FIFO_COUNTER_W 5 +// receiver fifo has width 11 because it has break, parity and framing error bits +`define UART_FIFO_REC_WIDTH 11 + + +`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded +`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register) +`define FAST_TEST 1 // 64/1024 packets are sent + + + + + + + diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_receiver.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_receiver.v new file mode 100644 index 00000000..a11d374c --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_receiver.v @@ -0,0 +1,485 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_receiver.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core receiver logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_receiver.v,v $ +// Revision 1.31 2004/06/18 14:46:15 tadejm +// Brandl Tobias repaired a bug regarding frame error in receiver when brake is received. +// +// Revision 1.29 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.28 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.27 2001/12/30 20:39:13 mohor +// More than one character was stored in case of break. End of the break +// was not detected correctly. +// +// Revision 1.26 2001/12/20 13:28:27 mohor +// Missing declaration of rf_push_q fixed. +// +// Revision 1.25 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.24 2001/12/19 08:03:34 mohor +// Warnings cleared. +// +// Revision 1.23 2001/12/19 07:33:54 mohor +// Synplicity was having troubles with the comment. +// +// Revision 1.22 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.21 2001/12/13 10:31:16 mohor +// timeout irq must be set regardless of the rda irq (rda irq does not reset the +// timeout counter). +// +// Revision 1.20 2001/12/10 19:52:05 gorban +// Igor fixed break condition bugs +// +// Revision 1.19 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.18 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.17 2001/11/28 19:36:39 gorban +// Fixed: timeout and break didn't pay attention to current data format when counting time +// +// Revision 1.16 2001/11/27 22:17:09 gorban +// Fixed bug that prevented synthesis in uart_receiver.v +// +// Revision 1.15 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.14 2001/11/10 12:43:21 gorban +// Logic Synthesis bugs fixed. Some other minor changes +// +// Revision 1.13 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.12 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.11 2001/10/31 15:19:22 gorban +// Fixes to break and timeout conditions +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.6 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.5 2001/06/02 14:28:14 gorban +// Fixed receiver and transmitter. Major bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.1 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, + counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); + +input clk; +input wb_rst_i; +input [7:0] lcr; +input rf_pop; +input srx_pad_i; +input enable; +input rx_reset; +input lsr_mask; + +output [9:0] counter_t; +output [`UART_FIFO_COUNTER_W-1:0] rf_count; +output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +output rf_overrun; +output rf_error_bit; +output [3:0] rstate; +output rf_push_pulse; + +reg [3:0] rstate; +reg [3:0] rcounter16; +reg [2:0] rbit_counter; +reg [7:0] rshift; // receiver shift register +reg rparity; // received parity +reg rparity_error; +reg rframing_error; // framing error flag +reg rbit_in; +reg rparity_xor; +reg [7:0] counter_b; // counts the 0 (low) signals +reg rf_push_q; + +// RX FIFO signals +reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in; +wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +wire rf_push_pulse; +reg rf_push; +wire rf_pop; +wire rf_overrun; +wire [`UART_FIFO_COUNTER_W-1:0] rf_count; +wire rf_error_bit; // an error (parity or framing) is inside the fifo +wire break_error = (counter_b == 0); + +// RX FIFO instance +uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx( + .clk( clk ), + .wb_rst_i( wb_rst_i ), + .data_in( rf_data_in ), + .data_out( rf_data_out ), + .push( rf_push_pulse ), + .pop( rf_pop ), + .overrun( rf_overrun ), + .count( rf_count ), + .error_bit( rf_error_bit ), + .fifo_reset( rx_reset ), + .reset_status(lsr_mask) +); + +wire rcounter16_eq_7 = (rcounter16 == 4'd7); +wire rcounter16_eq_0 = (rcounter16 == 4'd0); +wire rcounter16_eq_1 = (rcounter16 == 4'd1); + +wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1; + +parameter sr_idle = 4'd0; +parameter sr_rec_start = 4'd1; +parameter sr_rec_bit = 4'd2; +parameter sr_rec_parity = 4'd3; +parameter sr_rec_stop = 4'd4; +parameter sr_check_parity = 4'd5; +parameter sr_rec_prepare = 4'd6; +parameter sr_end_bit = 4'd7; +parameter sr_ca_lc_parity = 4'd8; +parameter sr_wait1 = 4'd9; +parameter sr_push = 4'd10; + + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + rstate <= #1 sr_idle; + rbit_in <= #1 1'b0; + rcounter16 <= #1 0; + rbit_counter <= #1 0; + rparity_xor <= #1 1'b0; + rframing_error <= #1 1'b0; + rparity_error <= #1 1'b0; + rparity <= #1 1'b0; + rshift <= #1 0; + rf_push <= #1 1'b0; + rf_data_in <= #1 0; + end + else + if (enable) + begin + case (rstate) + sr_idle : begin + rf_push <= #1 1'b0; + rf_data_in <= #1 0; + rcounter16 <= #1 4'b1110; + if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?) + begin + rstate <= #1 sr_rec_start; + end + end + sr_rec_start : begin + rf_push <= #1 1'b0; + if (rcounter16_eq_7) // check the pulse + if (srx_pad_i==1'b1) // no start bit + rstate <= #1 sr_idle; + else // start bit detected + rstate <= #1 sr_rec_prepare; + rcounter16 <= #1 rcounter16_minus_1; + end + sr_rec_prepare:begin + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : rbit_counter <= #1 3'b100; + 2'b01 : rbit_counter <= #1 3'b101; + 2'b10 : rbit_counter <= #1 3'b110; + 2'b11 : rbit_counter <= #1 3'b111; + endcase + if (rcounter16_eq_0) + begin + rstate <= #1 sr_rec_bit; + rcounter16 <= #1 4'b1110; + rshift <= #1 0; + end + else + rstate <= #1 sr_rec_prepare; + rcounter16 <= #1 rcounter16_minus_1; + end + sr_rec_bit : begin + if (rcounter16_eq_0) + rstate <= #1 sr_end_bit; + if (rcounter16_eq_7) // read the bit + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]}; + 2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]}; + 2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]}; + 2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]}; + endcase + rcounter16 <= #1 rcounter16_minus_1; + end + sr_end_bit : begin + if (rbit_counter==3'b0) // no more bits in word + if (lcr[`UART_LC_PE]) // choose state based on parity + rstate <= #1 sr_rec_parity; + else + begin + rstate <= #1 sr_rec_stop; + rparity_error <= #1 1'b0; // no parity - no error :) + end + else // else we have more bits to read + begin + rstate <= #1 sr_rec_bit; + rbit_counter <= #1 rbit_counter - 1'b1; + end + rcounter16 <= #1 4'b1110; + end + sr_rec_parity: begin + if (rcounter16_eq_7) // read the parity + begin + rparity <= #1 srx_pad_i; + rstate <= #1 sr_ca_lc_parity; + end + rcounter16 <= #1 rcounter16_minus_1; + end + sr_ca_lc_parity : begin // rcounter equals 6 + rcounter16 <= #1 rcounter16_minus_1; + rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data + rstate <= #1 sr_check_parity; + end + sr_check_parity: begin // rcounter equals 5 + case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) + 2'b00: rparity_error <= #1 rparity_xor == 0; // no error if parity 1 + 2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1 + 2'b10: rparity_error <= #1 rparity_xor == 1; // error if parity is odd + 2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0 + endcase + rcounter16 <= #1 rcounter16_minus_1; + rstate <= #1 sr_wait1; + end + sr_wait1 : if (rcounter16_eq_0) + begin + rstate <= #1 sr_rec_stop; + rcounter16 <= #1 4'b1110; + end + else + rcounter16 <= #1 rcounter16_minus_1; + sr_rec_stop : begin + if (rcounter16_eq_7) // read the parity + begin + rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit) + rstate <= #1 sr_push; + end + rcounter16 <= #1 rcounter16_minus_1; + end + sr_push : begin +/////////////////////////////////////// +// $display($time, ": received: %b", rf_data_in); + if(srx_pad_i | break_error) + begin + if(break_error) + rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO + else + rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error}; + rf_push <= #1 1'b1; + rstate <= #1 sr_idle; + end + else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i + begin + rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error}; + rf_push <= #1 1'b1; + rcounter16 <= #1 4'b1110; + rstate <= #1 sr_rec_start; + end + + end + default : rstate <= #1 sr_idle; + endcase + end // if (enable) +end // always of receiver + +always @ (posedge clk or posedge wb_rst_i) +begin + if(wb_rst_i) + rf_push_q <= 0; + else + rf_push_q <= #1 rf_push; +end + +assign rf_push_pulse = rf_push & ~rf_push_q; + + +// +// Break condition detection. +// Works in conjuction with the receiver state machine + +reg [9:0] toc_value; // value to be set to timeout counter + +always @(lcr) + case (lcr[3:0]) + 4'b0000 : toc_value = 447; // 7 bits + 4'b0100 : toc_value = 479; // 7.5 bits + 4'b0001, 4'b1000 : toc_value = 511; // 8 bits + 4'b1100 : toc_value = 543; // 8.5 bits + 4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits + 4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits + 4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits + 4'b1111 : toc_value = 767; // 12 bits + endcase // case(lcr[3:0]) + +wire [7:0] brc_value; // value to be set to break counter +assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + counter_b <= #1 8'd159; + else + if (srx_pad_i) + counter_b <= #1 brc_value; // character time length - 1 + else + if(enable & counter_b != 8'b0) // only work on enable times break not reached. + counter_b <= #1 counter_b - 1; // decrement break counter +end // always of break condition detection + +/// +/// Timeout condition detection +reg [9:0] counter_t; // counts the timeout condition clocks + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + counter_t <= #1 10'd639; // 10 bits for the default 8N1 + else + if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level + counter_t <= #1 toc_value; + else + if (enable && counter_t != 10'b0) // we don't want to underflow + counter_t <= #1 counter_t - 1; +end + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_regs.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_regs.v new file mode 100644 index 00000000..087524ab --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_regs.v @@ -0,0 +1,903 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_regs.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Registers of the uart 16550 core //// +//// //// +//// Known problems (limits): //// +//// Inserts 1 wait state in all WISHBONE transfers //// +//// //// +//// To Do: //// +//// Nothing or verification. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: (See log for the revision history //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_regs.v,v $ +// Revision 1.42 2004/11/22 09:21:59 igorm +// Timeout interrupt should be generated only when there is at least ony +// character in the fifo. +// +// Revision 1.41 2004/05/21 11:44:41 tadejm +// Added synchronizer flops for RX input. +// +// Revision 1.40 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.39 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.38 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.37 2001/12/27 13:24:09 mohor +// lsr[7] was not showing overrun errors. +// +// Revision 1.36 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.35 2001/12/19 08:03:34 mohor +// Warnings cleared. +// +// Revision 1.34 2001/12/19 07:33:54 mohor +// Synplicity was having troubles with the comment. +// +// Revision 1.33 2001/12/17 10:14:43 mohor +// Things related to msr register changed. After THRE IRQ occurs, and one +// character is written to the transmit fifo, the detection of the THRE bit in the +// LSR is delayed for one character time. +// +// Revision 1.32 2001/12/14 13:19:24 mohor +// MSR register fixed. +// +// Revision 1.31 2001/12/14 10:06:58 mohor +// After reset modem status register MSR should be reset. +// +// Revision 1.30 2001/12/13 10:09:13 mohor +// thre irq should be cleared only when being source of interrupt. +// +// Revision 1.29 2001/12/12 09:05:46 mohor +// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). +// +// Revision 1.28 2001/12/10 19:52:41 gorban +// Scratch register added +// +// Revision 1.27 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.26 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.25 2001/11/28 19:36:39 gorban +// Fixed: timeout and break didn't pay attention to current data format when counting time +// +// Revision 1.24 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.23 2001/11/12 21:57:29 gorban +// fixed more typo bugs +// +// Revision 1.22 2001/11/12 15:02:28 mohor +// lsr1r error fixed. +// +// Revision 1.21 2001/11/12 14:57:27 mohor +// ti_int_pnd error fixed. +// +// Revision 1.20 2001/11/12 14:50:27 mohor +// ti_int_d error fixed. +// +// Revision 1.19 2001/11/10 12:43:21 gorban +// Logic Synthesis bugs fixed. Some other minor changes +// +// Revision 1.18 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.17 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.16 2001/11/02 09:55:16 mohor +// no message +// +// Revision 1.15 2001/10/31 15:19:22 gorban +// Fixes to break and timeout conditions +// +// Revision 1.14 2001/10/29 17:00:46 gorban +// fixed parity sending and tx_fifo resets over- and underrun +// +// Revision 1.13 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.12 2001/10/19 16:21:40 gorban +// Changes data_out to be synchronous again as it should have been. +// +// Revision 1.11 2001/10/18 20:35:45 gorban +// small fix +// +// Revision 1.10 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.9 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.10 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.9 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.8 2001/05/29 20:05:04 gorban +// Fixed some bugs and synthesis problems. +// +// Revision 1.7 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.6 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.5 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +`define UART_DL1 7:0 +`define UART_DL2 15:8 + +module uart_regs (clk, + wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i, + +// additional signals + modem_inputs, + stx_pad_o, srx_pad_i, + +`ifdef DATA_BUS_WIDTH_8 +`else +// debug interface signals enabled +ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate, +`endif + rts_pad_o, dtr_pad_o, int_o +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud_o +`endif + + ); + +input clk; +input wb_rst_i; +input [`UART_ADDR_WIDTH-1:0] wb_addr_i; +input [7:0] wb_dat_i; +output [7:0] wb_dat_o; +input wb_we_i; +input wb_re_i; + +output stx_pad_o; +input srx_pad_i; + +input [3:0] modem_inputs; +output rts_pad_o; +output dtr_pad_o; +output int_o; +`ifdef UART_HAS_BAUDRATE_OUTPUT +output baud_o; +`endif + +`ifdef DATA_BUS_WIDTH_8 +`else +// if 32-bit databus and debug interface are enabled +output [3:0] ier; +output [3:0] iir; +output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored +output [4:0] mcr; +output [7:0] lcr; +output [7:0] msr; +output [7:0] lsr; +output [`UART_FIFO_COUNTER_W-1:0] rf_count; +output [`UART_FIFO_COUNTER_W-1:0] tf_count; +output [2:0] tstate; +output [3:0] rstate; + +`endif + +wire [3:0] modem_inputs; +reg enable; +`ifdef UART_HAS_BAUDRATE_OUTPUT +assign baud_o = enable; // baud_o is actually the enable signal +`endif + + +wire stx_pad_o; // received from transmitter module +wire srx_pad_i; +wire srx_pad; + +reg [7:0] wb_dat_o; + +wire [`UART_ADDR_WIDTH-1:0] wb_addr_i; +wire [7:0] wb_dat_i; + + +reg [3:0] ier; +reg [3:0] iir; +reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored +reg [4:0] mcr; +reg [7:0] lcr; +reg [7:0] msr; +reg [15:0] dl; // 32-bit divisor latch +reg [7:0] scratch; // UART scratch register +reg start_dlc; // activate dlc on writing to UART_DL1 +reg lsr_mask_d; // delay for lsr_mask condition +reg msi_reset; // reset MSR 4 lower bits indicator +//reg threi_clear; // THRE interrupt clear flag +reg [15:0] dlc; // 32-bit divisor latch counter +reg int_o; + +reg [3:0] trigger_level; // trigger level of the receiver FIFO +reg rx_reset; +reg tx_reset; + +wire dlab; // divisor latch access bit +wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits +wire loopback; // loopback bit (MCR bit 4) +wire cts, dsr, ri, dcd; // effective signals +wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback) +wire rts_pad_o, dtr_pad_o; // modem control outputs + +// LSR bits wires and regs +wire [7:0] lsr; +wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7; +reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r; +wire lsr_mask; // lsr_mask + +// +// ASSINGS +// + +assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r }; + +assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs; +assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]} + : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign dlab = lcr[`UART_LC_DL]; +assign loopback = mcr[4]; + +// assign modem outputs +assign rts_pad_o = mcr[`UART_MC_RTS]; +assign dtr_pad_o = mcr[`UART_MC_DTR]; + +// Interrupt signals +wire rls_int; // receiver line status interrupt +wire rda_int; // receiver data available interrupt +wire ti_int; // timeout indicator interrupt +wire thre_int; // transmitter holding register empty interrupt +wire ms_int; // modem status interrupt + +// FIFO signals +reg tf_push; +reg rf_pop; +wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +wire rf_error_bit; // an error (parity or framing) is inside the fifo +wire [`UART_FIFO_COUNTER_W-1:0] rf_count; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; +wire [2:0] tstate; +wire [3:0] rstate; +wire [9:0] counter_t; + +wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo. +reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle) +reg [7:0] block_value; // One character length minus stop bit + +// Transmitter Instance +wire serial_out; + +uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask); + + // Synchronizing and sampling serial RX input + uart_sync_flops i_uart_sync_flops + ( + .rst_i (wb_rst_i), + .clk_i (clk), + .stage1_rst_i (1'b0), + .stage1_clk_en_i (1'b1), + .async_dat_i (srx_pad_i), + .sync_dat_o (srx_pad) + ); + defparam i_uart_sync_flops.width = 1; + defparam i_uart_sync_flops.init_value = 1'b1; + +// handle loopback +wire serial_in = loopback ? serial_out : srx_pad; +assign stx_pad_o = loopback ? 1'b1 : serial_out; + + wire rf_push_pulse, rf_overrun; +// Receiver Instance +uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable, + counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); + + +// Asynchronous reading here because the outputs are sampled in uart_wb.v file +always @(dl or dlab or ier or iir or scratch + or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading +begin + case (wb_addr_i) + `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3]; + `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier; + `UART_REG_II : wb_dat_o = {4'b1100,iir}; + `UART_REG_LC : wb_dat_o = lcr; + `UART_REG_LS : wb_dat_o = lsr; + `UART_REG_MS : wb_dat_o = msr; + `UART_REG_SR : wb_dat_o = scratch; + default: wb_dat_o = 8'b0; // ?? + endcase // case(wb_addr_i) +end // always @ (dl or dlab or ier or iir or scratch... + + +// rf_pop signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + rf_pop <= #1 0; + else + if (rf_pop) // restore the signal to 0 after one clock cycle + rf_pop <= #1 0; + else + if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab) + rf_pop <= #1 1; // advance read pointer +end + +wire lsr_mask_condition; +wire iir_read; +wire msr_read; +wire fifo_read; +wire fifo_write; + +assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab); +assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab); +assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab); +assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab); +assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab); + +// lsr_mask_d delayed signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + lsr_mask_d <= #1 0; + else // reset bits in the Line Status Register + lsr_mask_d <= #1 lsr_mask_condition; +end + +// lsr_mask is rise detected +assign lsr_mask = lsr_mask_condition && ~lsr_mask_d; + +// msi_reset signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + msi_reset <= #1 1; + else + if (msi_reset) + msi_reset <= #1 0; + else + if (msr_read) + msi_reset <= #1 1; // reset bits in Modem Status Register +end + + +// +// WRITES AND RESETS // +// +// Line Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + lcr <= #1 8'b00000011; // 8n1 setting + else + if (wb_we_i && wb_addr_i==`UART_REG_LC) + lcr <= #1 wb_dat_i; + +// Interrupt Enable Register or UART_DL2 +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + begin + ier <= #1 4'b0000; // no interrupts after reset + dl[`UART_DL2] <= #1 8'b0; + end + else + if (wb_we_i && wb_addr_i==`UART_REG_IE) + if (dlab) + begin + dl[`UART_DL2] <= #1 wb_dat_i; + end + else + ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb + + +// FIFO Control Register and rx_reset, tx_reset signals +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + fcr <= #1 2'b11; + rx_reset <= #1 0; + tx_reset <= #1 0; + end else + if (wb_we_i && wb_addr_i==`UART_REG_FC) begin + fcr <= #1 wb_dat_i[7:6]; + rx_reset <= #1 wb_dat_i[1]; + tx_reset <= #1 wb_dat_i[2]; + end else begin + rx_reset <= #1 0; + tx_reset <= #1 0; + end + +// Modem Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + mcr <= #1 5'b0; + else + if (wb_we_i && wb_addr_i==`UART_REG_MC) + mcr <= #1 wb_dat_i[4:0]; + +// Scratch register +// Line Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + scratch <= #1 0; // 8n1 setting + else + if (wb_we_i && wb_addr_i==`UART_REG_SR) + scratch <= #1 wb_dat_i; + +// TX_FIFO or UART_DL1 +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + begin + dl[`UART_DL1] <= #1 8'b0; + tf_push <= #1 1'b0; + start_dlc <= #1 1'b0; + end + else + if (wb_we_i && wb_addr_i==`UART_REG_TR) + if (dlab) + begin + dl[`UART_DL1] <= #1 wb_dat_i; + start_dlc <= #1 1'b1; // enable DL counter + tf_push <= #1 1'b0; + end + else + begin + tf_push <= #1 1'b1; + start_dlc <= #1 1'b0; + end // else: !if(dlab) + else + begin + start_dlc <= #1 1'b0; + tf_push <= #1 1'b0; + end // else: !if(dlab) + +// Receiver FIFO trigger level selection logic (asynchronous mux) +always @(fcr) + case (fcr[`UART_FC_TL]) + 2'b00 : trigger_level = 1; + 2'b01 : trigger_level = 4; + 2'b10 : trigger_level = 8; + 2'b11 : trigger_level = 14; + endcase // case(fcr[`UART_FC_TL]) + +// +// STATUS REGISTERS // +// + +// Modem Status Register +reg [3:0] delayed_modem_signals; +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + msr <= #1 0; + delayed_modem_signals[3:0] <= #1 0; + end + else begin + msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 : + msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]); + msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c}; + delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts}; + end +end + + +// Line Status Register + +// activation conditions +assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition +assign lsr1 = rf_overrun; // Receiver overrun error +assign lsr2 = rf_data_out[1]; // parity error bit +assign lsr3 = rf_data_out[0]; // framing error bit +assign lsr4 = rf_data_out[2]; // break error in the character + +// Why is this here? Empty should be signalled in the fifo itself, + // to properly account for fifo length parameters + +assign lsr5 = (tf_count!=5'b01111); // transmitter fifo is not full +assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter completely empty +assign lsr7 = rf_error_bit | rf_overrun; + +// lsr bit0 (receiver data available) +reg lsr0_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr0_d <= #1 0; + else lsr0_d <= #1 lsr0; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr0r <= #1 0; + else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition + lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted + +// lsr bit 1 (receiver overrun) +reg lsr1_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr1_d <= #1 0; + else lsr1_d <= #1 lsr1; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr1r <= #1 0; + else lsr1r <= #1 lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise + +// lsr bit 2 (parity error) +reg lsr2_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr2_d <= #1 0; + else lsr2_d <= #1 lsr2; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr2r <= #1 0; + else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise + +// lsr bit 3 (framing error) +reg lsr3_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr3_d <= #1 0; + else lsr3_d <= #1 lsr3; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr3r <= #1 0; + else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise + +// lsr bit 4 (break indicator) +reg lsr4_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr4_d <= #1 0; + else lsr4_d <= #1 lsr4; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr4r <= #1 0; + else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d); + +// lsr bit 5 (transmitter fifo is empty) +reg lsr5_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr5_d <= #1 1; + else lsr5_d <= #1 lsr5; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr5r <= #1 1; + else lsr5r <= #1 lsr5; + //else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d); + +// lsr bit 6 (transmitter empty indicator) +reg lsr6_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr6_d <= #1 1; + else lsr6_d <= #1 lsr6; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr6r <= #1 1; + else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d); + +// lsr bit 7 (error in fifo) +reg lsr7_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr7_d <= #1 0; + else lsr7_d <= #1 lsr7; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr7r <= #1 0; + else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d); + +// Frequency divider +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + dlc <= #1 0; + else + if (start_dlc | ~ (|dlc)) + dlc <= #1 dl - 1; // preset counter + else + dlc <= #1 dlc - 1; // decrement counter +end + +// Enable signal generation logic +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + enable <= #1 1'b0; + else + if (|dl & ~(|dlc)) // dl>0 & dlc==0 + enable <= #1 1'b1; + else + enable <= #1 1'b0; +end + +// Delaying THRE status for one character cycle after a character is written to an empty fifo. +always @(lcr) + case (lcr[3:0]) + 4'b0000 : block_value = 95; // 6 bits + 4'b0100 : block_value = 103; // 6.5 bits + 4'b0001, 4'b1000 : block_value = 111; // 7 bits + 4'b1100 : block_value = 119; // 7.5 bits + 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits + 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits + 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits + 4'b1111 : block_value = 175; // 11 bits + endcase // case(lcr[3:0]) + +// Counting time of one character minus stop bit +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + block_cnt <= #1 8'd0; + else + if(lsr5r & fifo_write) // THRE bit set & write to fifo occured + block_cnt <= #1 block_value; + else + if (enable & block_cnt != 8'b0) // only work on enable times + block_cnt <= #1 block_cnt - 1; // decrement break counter +end // always of break condition detection + +// Generating THRE status enable signal +assign thre_set_en = ~(|block_cnt); + + +// +// INTERRUPT LOGIC +// + +assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]); +assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level}); +assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE]; +assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]); +assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count); + +reg rls_int_d; +reg thre_int_d; +reg ms_int_d; +reg ti_int_d; +reg rda_int_d; + +// delay lines +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rls_int_d <= #1 0; + else rls_int_d <= #1 rls_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rda_int_d <= #1 0; + else rda_int_d <= #1 rda_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) thre_int_d <= #1 0; + else thre_int_d <= #1 thre_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ms_int_d <= #1 0; + else ms_int_d <= #1 ms_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ti_int_d <= #1 0; + else ti_int_d <= #1 ti_int; + +// rise detection signals + +wire rls_int_rise; +wire thre_int_rise; +wire ms_int_rise; +wire ti_int_rise; +wire rda_int_rise; + +assign rda_int_rise = rda_int & ~rda_int_d; +assign rls_int_rise = rls_int & ~rls_int_d; +assign thre_int_rise = thre_int & ~thre_int_d; +assign ms_int_rise = ms_int & ~ms_int_d; +assign ti_int_rise = ti_int & ~ti_int_d; + +// interrupt pending flags +reg rls_int_pnd; +reg rda_int_pnd; +reg thre_int_pnd; +reg ms_int_pnd; +reg ti_int_pnd; + +// interrupt pending flags assignments +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rls_int_pnd <= #1 0; + else + rls_int_pnd <= #1 lsr_mask ? 0 : // reset condition + rls_int_rise ? 1 : // latch condition + rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rda_int_pnd <= #1 0; + else + rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition + rda_int_rise ? 1 : // latch condition + rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) thre_int_pnd <= #1 0; + else + thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 : + thre_int_rise ? 1 : + thre_int_pnd && ier[`UART_IE_THRE]; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ms_int_pnd <= #1 0; + else + ms_int_pnd <= #1 msr_read ? 0 : + ms_int_rise ? 1 : + ms_int_pnd && ier[`UART_IE_MS]; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ti_int_pnd <= #1 0; + else + ti_int_pnd <= #1 fifo_read ? 0 : + ti_int_rise ? 1 : + ti_int_pnd && ier[`UART_IE_RDA]; +// end of pending flags + +// INT_O logic +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + int_o <= #1 1'b0; + else + int_o <= #1 + rls_int_pnd ? ~lsr_mask : + rda_int_pnd ? 1 : + ti_int_pnd ? ~fifo_read : + thre_int_pnd ? !(fifo_write & iir_read) : + ms_int_pnd ? ~msr_read : + 0; // if no interrupt are pending +end + + +// Interrupt Identification register +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + iir <= #1 1; + else + if (rls_int_pnd) // interrupt is pending + begin + iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value + iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending) + end else // the sequence of conditions determines priority of interrupt identification + if (rda_int) + begin + iir[`UART_II_II] <= #1 `UART_II_RDA; + iir[`UART_II_IP] <= #1 1'b0; + end + else if (ti_int_pnd) + begin + iir[`UART_II_II] <= #1 `UART_II_TI; + iir[`UART_II_IP] <= #1 1'b0; + end + else if (thre_int_pnd) + begin + iir[`UART_II_II] <= #1 `UART_II_THRE; + iir[`UART_II_IP] <= #1 1'b0; + end + else if (ms_int_pnd) + begin + iir[`UART_II_II] <= #1 `UART_II_MS; + iir[`UART_II_IP] <= #1 1'b0; + end else // no interrupt is pending + begin + iir[`UART_II_II] <= #1 0; + iir[`UART_II_IP] <= #1 1'b1; + end +end + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_rfifo.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_rfifo.v new file mode 100644 index 00000000..21e9d25e --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_rfifo.v @@ -0,0 +1,323 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_rfifo.v (Modified from uart_fifo.v) //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core receiver FIFO //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2002/07/22 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_rfifo.v,v $ +// Revision 1.4 2003/07/11 18:20:26 gorban +// added clearing the receiver fifo statuses on resets +// +// Revision 1.3 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.2 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.1 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.16 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.15 2001/12/18 09:01:07 mohor +// Bug that was entered in the last update fixed (rx state machine). +// +// Revision 1.14 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.13 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.12 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.11 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/24 08:48:10 mohor +// FIFO was not cleared after the data was read bug fixed. +// +// Revision 1.7 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.3 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:48 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_rfifo (clk, + wb_rst_i, data_in, data_out, +// Control signals + push, // push strobe, active high + pop, // pop strobe, active high +// status signals + overrun, + count, + error_bit, + fifo_reset, + reset_status + ); + + +// FIFO parameters +parameter fifo_width = `UART_FIFO_WIDTH; +parameter fifo_depth = `UART_FIFO_DEPTH; +parameter fifo_pointer_w = `UART_FIFO_POINTER_W; +parameter fifo_counter_w = `UART_FIFO_COUNTER_W; + +input clk; +input wb_rst_i; +input push; +input pop; +input [fifo_width-1:0] data_in; +input fifo_reset; +input reset_status; + +output [fifo_width-1:0] data_out; +output overrun; +output [fifo_counter_w-1:0] count; +output error_bit; + +wire [fifo_width-1:0] data_out; +wire [7:0] data8_out; +// flags FIFO +reg [2:0] fifo[fifo_depth-1:0]; + +// FIFO pointers +reg [fifo_pointer_w-1:0] top; +reg [fifo_pointer_w-1:0] bottom; + +reg [fifo_counter_w-1:0] count; +reg overrun; + +wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; + +raminfr #(fifo_pointer_w,8,fifo_depth) rfifo + (.clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in[fifo_width-1:fifo_width-8]), + .dpo(data8_out) + ); + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + begin + top <= #1 0; + bottom <= #1 1'b0; + count <= #1 0; + fifo[0] <= #1 0; + fifo[1] <= #1 0; + fifo[2] <= #1 0; + fifo[3] <= #1 0; + fifo[4] <= #1 0; + fifo[5] <= #1 0; + fifo[6] <= #1 0; + fifo[7] <= #1 0; + fifo[8] <= #1 0; + fifo[9] <= #1 0; + fifo[10] <= #1 0; + fifo[11] <= #1 0; + fifo[12] <= #1 0; + fifo[13] <= #1 0; + fifo[14] <= #1 0; + fifo[15] <= #1 0; + end + else + if (fifo_reset) begin + top <= #1 0; + bottom <= #1 1'b0; + count <= #1 0; + fifo[0] <= #1 0; + fifo[1] <= #1 0; + fifo[2] <= #1 0; + fifo[3] <= #1 0; + fifo[4] <= #1 0; + fifo[5] <= #1 0; + fifo[6] <= #1 0; + fifo[7] <= #1 0; + fifo[8] <= #1 0; + fifo[9] <= #1 0; + fifo[10] <= #1 0; + fifo[11] <= #1 0; + fifo[12] <= #1 0; + fifo[13] <= #1 0; + fifo[14] <= #1 0; + fifo[15] <= #1 0; + end + else + begin + case ({push, pop}) + 2'b10 : if (count0) + begin + fifo[bottom] <= #1 0; + bottom <= #1 bottom + 1'b1; + count <= #1 count - 1'b1; + end + 2'b11 : begin + bottom <= #1 bottom + 1'b1; + top <= #1 top_plus_1; + fifo[top] <= #1 data_in[2:0]; + end + default: ; + endcase + end +end // always + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + overrun <= #1 1'b0; + else + if(fifo_reset | reset_status) + overrun <= #1 1'b0; + else + if(push & ~pop & (count==fifo_depth)) + overrun <= #1 1'b1; +end // always + + +// please note though that data_out is only valid one clock after pop signal +assign data_out = {data8_out,fifo[bottom]}; + +// Additional logic for detection of error conditions (parity and framing) inside the FIFO +// for the Line Status Register bit 7 + +wire [2:0] word0 = fifo[0]; +wire [2:0] word1 = fifo[1]; +wire [2:0] word2 = fifo[2]; +wire [2:0] word3 = fifo[3]; +wire [2:0] word4 = fifo[4]; +wire [2:0] word5 = fifo[5]; +wire [2:0] word6 = fifo[6]; +wire [2:0] word7 = fifo[7]; + +wire [2:0] word8 = fifo[8]; +wire [2:0] word9 = fifo[9]; +wire [2:0] word10 = fifo[10]; +wire [2:0] word11 = fifo[11]; +wire [2:0] word12 = fifo[12]; +wire [2:0] word13 = fifo[13]; +wire [2:0] word14 = fifo[14]; +wire [2:0] word15 = fifo[15]; + +// a 1 is returned if any of the error bits in the fifo is 1 +assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] | + word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] | + word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] | + word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] ); + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_sync_flops.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_sync_flops.v new file mode 100644 index 00000000..a822f26d --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_sync_flops.v @@ -0,0 +1,125 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_sync_flops.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core receiver logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - Andrej Erzen (andreje@flextronics.si) //// +//// - Tadej Markovic (tadejm@flextronics.si) //// +//// //// +//// Created: 2004/05/20 //// +//// Last Updated: 2004/05/20 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_sync_flops.v,v $ +// Revision 1.1 2004/05/21 11:43:25 tadejm +// Added to synchronize RX input to Wishbone clock. +// +// + + +`include "timescale.v" + + +module uart_sync_flops +( + // internal signals + rst_i, + clk_i, + stage1_rst_i, + stage1_clk_en_i, + async_dat_i, + sync_dat_o +); + +parameter Tp = 1; +parameter width = 1; +parameter init_value = 1'b0; + +input rst_i; // reset input +input clk_i; // clock input +input stage1_rst_i; // synchronous reset for stage 1 FF +input stage1_clk_en_i; // synchronous clock enable for stage 1 FF +input [width-1:0] async_dat_i; // asynchronous data input +output [width-1:0] sync_dat_o; // synchronous data output + + +// +// Interal signal declarations +// + +reg [width-1:0] sync_dat_o; +reg [width-1:0] flop_0; + + +// first stage +always @ (posedge clk_i or posedge rst_i) +begin + if (rst_i) + flop_0 <= #Tp {width{init_value}}; + else + flop_0 <= #Tp async_dat_i; +end + +// second stage +always @ (posedge clk_i or posedge rst_i) +begin + if (rst_i) + sync_dat_o <= #Tp {width{init_value}}; + else if (stage1_rst_i) + sync_dat_o <= #Tp {width{init_value}}; + else if (stage1_clk_en_i) + sync_dat_o <= #Tp flop_0; +end + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_tfifo.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_tfifo.v new file mode 100644 index 00000000..9b369aac --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_tfifo.v @@ -0,0 +1,246 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_tfifo.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core transmitter FIFO //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2002/07/22 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_tfifo.v,v $ +// Revision 1.2 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.1 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.16 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.15 2001/12/18 09:01:07 mohor +// Bug that was entered in the last update fixed (rx state machine). +// +// Revision 1.14 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.13 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.12 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.11 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/24 08:48:10 mohor +// FIFO was not cleared after the data was read bug fixed. +// +// Revision 1.7 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.3 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:48 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_tfifo (clk, + wb_rst_i, data_in, data_out, +// Control signals + push, // push strobe, active high + pop, // pop strobe, active high +// status signals + overrun, + count, + fifo_reset, + reset_status + ); + + +// FIFO parameters +parameter fifo_width = `UART_FIFO_WIDTH; +parameter fifo_depth = `UART_FIFO_DEPTH; +parameter fifo_pointer_w = `UART_FIFO_POINTER_W; +parameter fifo_counter_w = `UART_FIFO_COUNTER_W; + +input clk; +input wb_rst_i; +input push; +input pop; +input [fifo_width-1:0] data_in; +input fifo_reset; +input reset_status; + +output [fifo_width-1:0] data_out; +output overrun; +output [fifo_counter_w-1:0] count; + +wire [fifo_width-1:0] data_out; + +// FIFO pointers +reg [fifo_pointer_w-1:0] top; +reg [fifo_pointer_w-1:0] bottom; + +reg [fifo_counter_w-1:0] count; +reg overrun; +wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1; + +raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo + (.clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in), + .dpo(data_out) + ); + + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + begin + top <= #1 0; + bottom <= #1 1'b0; + count <= #1 0; + end + else + if (fifo_reset) begin + top <= #1 0; + bottom <= #1 1'b0; + count <= #1 0; + end + else + begin + case ({push, pop}) + 2'b10 : if (count0) + begin + bottom <= #1 bottom + 1'b1; + count <= #1 count - 1'b1; + end + 2'b11 : begin + bottom <= #1 bottom + 1'b1; + top <= #1 top_plus_1; + end + default: ; + endcase + end +end // always + +always @(posedge clk or posedge wb_rst_i) // synchronous FIFO +begin + if (wb_rst_i) + overrun <= #1 1'b0; + else + if(fifo_reset | reset_status) + overrun <= #1 1'b0; + else + if(push & (count==fifo_depth)) + overrun <= #1 1'b1; +end // always + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_top.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_top.v new file mode 100644 index 00000000..e57ca8e4 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_top.v @@ -0,0 +1,337 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_top.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core top level. //// +//// //// +//// Known problems (limits): //// +//// Note that transmitter and receiver instances are inside //// +//// the uart_regs.v file. //// +//// //// +//// To Do: //// +//// Nothing so far. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_top.v,v $ +// Revision 1.19 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.18 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.17 2001/12/19 08:40:03 mohor +// Warnings fixed (unused signals removed). +// +// Revision 1.16 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.15 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.14 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.13 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.12 2001/08/25 15:46:19 gorban +// Modified port names again +// +// Revision 1.11 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.10 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +`include "uart_defines.v" + +module uart_top + (wb_clk_i, + + // Wishbone signals + wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, + int_o, // interrupt request + + // UART signals + // serial input/output + stx_pad_o, srx_pad_i, + + // modem signals + rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i + `ifdef UART_HAS_BAUDRATE_OUTPUT + , baud_o + `endif + ); + + parameter uart_data_width = `UART_DATA_WIDTH; + parameter uart_addr_width = `UART_ADDR_WIDTH; + + input wb_clk_i; + + // WISHBONE interface + input wb_rst_i; + input [uart_addr_width-1:0] wb_adr_i; + input [uart_data_width-1:0] wb_dat_i; + output [uart_data_width-1:0] wb_dat_o; + input wb_we_i; + input wb_stb_i; + input wb_cyc_i; + input [3:0] wb_sel_i; + output wb_ack_o; + output int_o; + + // UART signals + input srx_pad_i; + output stx_pad_o; + output rts_pad_o; + input cts_pad_i; + output dtr_pad_o; + input dsr_pad_i; + input ri_pad_i; + input dcd_pad_i; + + // optional baudrate output + `ifdef UART_HAS_BAUDRATE_OUTPUT + output baud_o; + `endif + + wire stx_pad_o; + wire rts_pad_o; + wire dtr_pad_o; + + wire [uart_addr_width-1:0] wb_adr_i; + wire [uart_data_width-1:0] wb_dat_i; + wire [uart_data_width-1:0] wb_dat_o; + + wire [7:0] wb_dat8_i; // 8-bit internal data input + wire [7:0] wb_dat8_o; // 8-bit internal data output + wire [31:0] wb_dat32_o; // debug interface 32-bit output + wire [3:0] wb_sel_i; // WISHBONE select signal + wire [uart_addr_width-1:0] wb_adr_int; + wire we_o; // Write enable for registers + wire re_o; // Read enable for registers + // + // MODULE INSTANCES + // + + `ifdef DATA_BUS_WIDTH_8 + `else + // debug interface wires + wire [3:0] ier; + wire [3:0] iir; + wire [1:0] fcr; + wire [4:0] mcr; + wire [7:0] lcr; + wire [7:0] msr; + wire [7:0] lsr; + wire [`UART_FIFO_COUNTER_W-1:0] rf_count; + wire [`UART_FIFO_COUNTER_W-1:0] tf_count; + wire [2:0] tstate; + wire [3:0] rstate; + `endif + + `ifdef DATA_BUS_WIDTH_8 + //// WISHBONE interface module + uart_wb wb_interface + (.clk(wb_clk_i), + .wb_rst_i( wb_rst_i ), + .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), + .wb_dat8_i(wb_dat8_i), + .wb_dat8_o(wb_dat8_o), + .wb_dat32_o(32'b0), + .wb_sel_i(4'b0), + .wb_we_i( wb_we_i ), + .wb_stb_i( wb_stb_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_ack_o( wb_ack_o ), + .wb_adr_i(wb_adr_i), + .wb_adr_int(wb_adr_int), + .we_o( we_o ), + .re_o(re_o) + ); + `else + uart_wb wb_interface + (.clk( wb_clk_i ), + .wb_rst_i( wb_rst_i ), + .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), + .wb_dat8_i(wb_dat8_i), + .wb_dat8_o(wb_dat8_o), + .wb_sel_i(wb_sel_i), + .wb_dat32_o(wb_dat32_o), + .wb_we_i( wb_we_i ), + .wb_stb_i( wb_stb_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_ack_o( wb_ack_o ), + .wb_adr_i(wb_adr_i), + .wb_adr_int(wb_adr_int), + .we_o( we_o ), + .re_o(re_o) + ); + `endif + + // Registers + uart_regs + regs(.clk( wb_clk_i ), + .wb_rst_i( wb_rst_i ), + .wb_addr_i( wb_adr_int ), + .wb_dat_i( wb_dat8_i ), + .wb_dat_o( wb_dat8_o ), + .wb_we_i( we_o ), + .wb_re_i(re_o), + .modem_inputs({cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} ), + .stx_pad_o( stx_pad_o ), + .srx_pad_i( srx_pad_i ), + `ifdef DATA_BUS_WIDTH_8 + `else + // debug interface signals enabled + .ier(ier), + .iir(iir), + .fcr(fcr), + .mcr(mcr), + .lcr(lcr), + .msr(msr), + .lsr(lsr), + .rf_count(rf_count), + .tf_count(tf_count), + .tstate(tstate), + .rstate(rstate), + `endif + .rts_pad_o( rts_pad_o ), + .dtr_pad_o( dtr_pad_o ), + .int_o( int_o ) + `ifdef UART_HAS_BAUDRATE_OUTPUT + , .baud_o(baud_o) + `endif + + ); + + `ifdef DATA_BUS_WIDTH_8 + `else + uart_debug_if + dbg(// Outputs + .wb_dat32_o (wb_dat32_o[31:0]), + // Inputs + .wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]), + .ier (ier[3:0]), + .iir (iir[3:0]), + .fcr (fcr[1:0]), + .mcr (mcr[4:0]), + .lcr (lcr[7:0]), + .msr (msr[7:0]), + .lsr (lsr[7:0]), + .rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]), + .tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]), + .tstate (tstate[2:0]), + .rstate (rstate[3:0])); + `endif + + initial + begin + `ifdef DATA_BUS_WIDTH_8 + $display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n"); + `else + $display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n"); + `endif + `ifdef UART_HAS_BAUDRATE_OUTPUT + $display("(%m) UART INFO: Has baudrate output\n"); + `else + $display("(%m) UART INFO: Doesn't have baudrate output\n"); + `endif + end + +endmodule // uart_top + diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_transmitter.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_transmitter.v new file mode 100644 index 00000000..e27e6998 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_transmitter.v @@ -0,0 +1,355 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_transmitter.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core transmitter logic //// +//// //// +//// Known problems (limits): //// +//// None known //// +//// //// +//// To Do: //// +//// Thourough testing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_transmitter.v,v $ +// Revision 1.19 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.18 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.16 2002/01/08 11:29:40 mohor +// tf_pop was too wide. Now it is only 1 clk cycle width. +// +// Revision 1.15 2001/12/17 14:46:48 mohor +// overrun signal was moved to separate block because many sequential lsr +// reads were preventing data from being written to rx fifo. +// underrun signal was not used and was removed from the project. +// +// Revision 1.14 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.13 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.12 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.11 2001/10/29 17:00:46 gorban +// fixed parity sending and tx_fifo resets over- and underrun +// +// Revision 1.10 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.9 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.8 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.6 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.5 2001/06/02 14:28:14 gorban +// Fixed receiver and transmitter. Major bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.2 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.1 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask); + +input clk; +input wb_rst_i; +input [7:0] lcr; +input tf_push; +input [7:0] wb_dat_i; +input enable; +input tx_reset; +input lsr_mask; //reset of fifo +output stx_pad_o; +output [2:0] tstate; +output [`UART_FIFO_COUNTER_W-1:0] tf_count; + +reg [2:0] tstate; +reg [4:0] counter; +reg [2:0] bit_counter; // counts the bits to be sent +reg [6:0] shift_out; // output shift register +reg stx_o_tmp; +reg parity_xor; // parity of the word +reg tf_pop; +reg bit_out; + +// TX FIFO instance +// +// Transmitter FIFO signals + reg [`UART_FIFO_WIDTH-1:0] tf_data_in; +wire [`UART_FIFO_WIDTH-1:0] tf_data_out; +wire tf_push; +wire tf_overrun; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; + +always @(posedge clk) + tf_data_in <= wb_dat_i; + +uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO + .clk( clk ), + .wb_rst_i( wb_rst_i ), + .data_in( tf_data_in ), + .data_out( tf_data_out ), + .push( tf_push ), + .pop( tf_pop ), + .overrun( tf_overrun ), + .count( tf_count ), + .fifo_reset( tx_reset ), + .reset_status(lsr_mask) +); + +// TRANSMITTER FINAL STATE MACHINE + +parameter s_idle = 3'd0; +parameter s_send_start = 3'd1; +parameter s_send_byte = 3'd2; +parameter s_send_parity = 3'd3; +parameter s_send_stop = 3'd4; +parameter s_pop_byte = 3'd5; + +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + tstate <= #1 s_idle; + stx_o_tmp <= #1 1'b1; + counter <= #1 5'b0; + shift_out <= #1 7'b0; + bit_out <= #1 1'b0; + parity_xor <= #1 1'b0; + tf_pop <= #1 1'b0; + bit_counter <= #1 3'b0; + end + else + if (enable) + begin + case (tstate) + s_idle : if (~|tf_count) // if tf_count==0 + begin + tstate <= #1 s_idle; + stx_o_tmp <= #1 1'b1; + end + else + begin + tf_pop <= #1 1'b0; + stx_o_tmp <= #1 1'b1; + tstate <= #1 s_pop_byte; + end + s_pop_byte : begin + tf_pop <= #1 1'b1; + case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word + 2'b00 : begin + bit_counter <= #1 3'b100; + parity_xor <= #1 ^tf_data_out[4:0]; + end + 2'b01 : begin + bit_counter <= #1 3'b101; + parity_xor <= #1 ^tf_data_out[5:0]; + end + 2'b10 : begin + bit_counter <= #1 3'b110; + parity_xor <= #1 ^tf_data_out[6:0]; + end + 2'b11 : begin + bit_counter <= #1 3'b111; + parity_xor <= #1 ^tf_data_out[7:0]; + end + endcase + {shift_out[6:0], bit_out} <= #1 tf_data_out; + tstate <= #1 s_send_start; + end + s_send_start : begin + tf_pop <= #1 1'b0; + if (~|counter) + counter <= #1 5'b01111; + else + if (counter == 5'b00001) + begin + counter <= #1 0; + tstate <= #1 s_send_byte; + end + else + counter <= #1 counter - 1'b1; + stx_o_tmp <= #1 1'b0; + end + s_send_byte : begin + if (~|counter) + counter <= #1 5'b01111; + else + if (counter == 5'b00001) + begin + if (bit_counter > 3'b0) + begin + bit_counter <= #1 bit_counter - 1'b1; + {shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]}; + tstate <= #1 s_send_byte; + end + else // end of byte + if (~lcr[`UART_LC_PE]) + begin + tstate <= #1 s_send_stop; + end + else + begin + case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]}) + 2'b00: bit_out <= #1 ~parity_xor; + 2'b01: bit_out <= #1 1'b1; + 2'b10: bit_out <= #1 parity_xor; + 2'b11: bit_out <= #1 1'b0; + endcase + tstate <= #1 s_send_parity; + end + counter <= #1 0; + end + else + counter <= #1 counter - 1'b1; + stx_o_tmp <= #1 bit_out; // set output pin + end + s_send_parity : begin + if (~|counter) + counter <= #1 5'b01111; + else + if (counter == 5'b00001) + begin + counter <= #1 4'b0; + tstate <= #1 s_send_stop; + end + else + counter <= #1 counter - 1'b1; + stx_o_tmp <= #1 bit_out; + end + s_send_stop : begin + if (~|counter) + begin + casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]}) + 3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor + 3'b100: counter <= #1 5'b10101; // 1.5 stop bit + default: counter <= #1 5'b11101; // 2 stop bits + endcase + end + else + if (counter == 5'b00001) + begin + counter <= #1 0; + tstate <= #1 s_idle; + end + else + counter <= #1 counter - 1'b1; + stx_o_tmp <= #1 1'b1; + end + + default : // should never get here + tstate <= #1 s_idle; + endcase + end // end if enable + else + tf_pop <= #1 1'b0; // tf_pop must be 1 cycle width +end // transmitter logic + +assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_wb.v b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_wb.v new file mode 100644 index 00000000..daf43645 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/verilog/uart_wb.v @@ -0,0 +1,308 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_wb.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core WISHBONE interface. //// +//// //// +//// Known problems (limits): //// +//// Inserts one wait state on all transfers. //// +//// Note affected signals and the way they are affected. //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_wb.v,v $ +// Revision 1.17 2004/05/21 12:35:15 tadejm +// Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. +// +// Revision 1.16 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.15 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.12 2001/12/19 08:03:34 mohor +// Warnings cleared. +// +// Revision 1.11 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.10 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.9 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.8 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.7 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.4 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.3 2001/05/21 19:12:01 gorban +// Corrected some Linter messages. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:13+02 jacob +// Initial revision +// +// + +// UART core WISHBONE interface +// +// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com) +// Company: Flextronics Semiconductor +// + +`include "uart_defines.v" + +module uart_wb (clk, wb_rst_i, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i, + wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i, + we_o, re_o // Write and read enable output for the core + ); + + input clk; + + // WISHBONE interface + input wb_rst_i; + input wb_we_i; + input wb_stb_i; + input wb_cyc_i; + input [3:0] wb_sel_i; + input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line + +`ifdef DATA_BUS_WIDTH_8 + input [7:0] wb_dat_i; //input WISHBONE bus + output [7:0] wb_dat_o; + reg [7:0] wb_dat_o; + wire [7:0] wb_dat_i; + reg [7:0] wb_dat_is; +`else // for 32 data bus mode + input [31:0] wb_dat_i; //input WISHBONE bus + output [31:0] wb_dat_o; + reg [31:0] wb_dat_o; + wire [31:0] wb_dat_i; + reg [31:0] wb_dat_is; +`endif // !`ifdef DATA_BUS_WIDTH_8 + + output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus + input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o + output [7:0] wb_dat8_i; + input [31:0] wb_dat32_o; // 32 bit data output (for debug interface) + output wb_ack_o; + output we_o; + output re_o; + + wire we_o; + reg wb_ack_o; + reg [7:0] wb_dat8_i; + wire [7:0] wb_dat8_o; + wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus + reg [`UART_ADDR_WIDTH-1:0] wb_adr_is; + reg wb_we_is; + reg wb_cyc_is; + reg wb_stb_is; + reg [3:0] wb_sel_is; + wire [3:0] wb_sel_i; + reg wre ;// timing control signal for write or read enable + + // wb_ack_o FSM + reg [1:0] wbstate; + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + wb_ack_o <= #1 1'b0; + wbstate <= #1 0; + wre <= #1 1'b1; + end else + case (wbstate) + 0: begin + if (wb_stb_is & wb_cyc_is) begin + wre <= #1 0; + wbstate <= #1 1; + wb_ack_o <= #1 1; + end else begin + wre <= #1 1; + wb_ack_o <= #1 0; + end + end + 1: begin + wb_ack_o <= #1 0; + wbstate <= #1 2; + wre <= #1 0; + end + 2,3: begin + wb_ack_o <= #1 0; + wbstate <= #1 0; + wre <= #1 0; + end + endcase + + assign we_o = wb_we_is & wb_ack_o; + //assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers + assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers + + // Sample input signals + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + wb_adr_is <= #1 0; + wb_we_is <= #1 0; + wb_cyc_is <= #1 0; + wb_stb_is <= #1 0; + wb_dat_is <= #1 0; + wb_sel_is <= #1 0; + end else begin + wb_adr_is <= #1 wb_adr_i; + wb_we_is <= #1 wb_we_i; + wb_cyc_is <= #1 wb_cyc_i; + wb_stb_is <= #1 wb_stb_i; + wb_dat_is <= #1 wb_dat_i; + wb_sel_is <= #1 wb_sel_i; + end + +`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + wb_dat_o <= #1 0; + else + wb_dat_o <= #1 wb_dat8_o; + + always @(wb_dat_is) + wb_dat8_i = wb_dat_is; + + assign wb_adr_int = wb_adr_is; + +`else // 32-bit bus + // put output to the correct byte in 32 bits using select line + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + wb_dat_o <= #1 0; + else if (re_o) + case (wb_sel_is) + 4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o}; + 4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0}; + 4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0}; + 4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0}; + 4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output + default: wb_dat_o <= #1 0; + endcase // case(wb_sel_i) + + reg [1:0] wb_adr_int_lsb; + + always @(wb_sel_is or wb_dat_is) + begin + case (wb_sel_is) + 4'b0001 : wb_dat8_i = wb_dat_is[7:0]; + 4'b0010 : wb_dat8_i = wb_dat_is[15:8]; + 4'b0100 : wb_dat8_i = wb_dat_is[23:16]; + 4'b1000 : wb_dat8_i = wb_dat_is[31:24]; + default : wb_dat8_i = wb_dat_is[7:0]; + endcase // case(wb_sel_i) + + `ifdef LITLE_ENDIAN + case (wb_sel_is) + 4'b0001 : wb_adr_int_lsb = 2'h0; + 4'b0010 : wb_adr_int_lsb = 2'h1; + 4'b0100 : wb_adr_int_lsb = 2'h2; + 4'b1000 : wb_adr_int_lsb = 2'h3; + default : wb_adr_int_lsb = 2'h0; + endcase // case(wb_sel_i) + `else + case (wb_sel_is) + 4'b0001 : wb_adr_int_lsb = 2'h3; + 4'b0010 : wb_adr_int_lsb = 2'h2; + 4'b0100 : wb_adr_int_lsb = 2'h1; + 4'b1000 : wb_adr_int_lsb = 2'h0; + default : wb_adr_int_lsb = 2'h0; + endcase // case(wb_sel_i) + `endif + end + + assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb}; + +`endif // !`ifdef DATA_BUS_WIDTH_8 + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/rtl/vhdl/.keepme b/usrp2/fpga/opencores/uart16550/rtl/vhdl/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Entries b/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Entries new file mode 100644 index 00000000..f674e77e --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:52:50 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Repository b/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Repository new file mode 100644 index 00000000..952ae5ae --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Repository @@ -0,0 +1 @@ +uart16550/rtl/vhdl diff --git a/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Root b/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Template b/usrp2/fpga/opencores/uart16550/rtl/vhdl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/CVS/Entries @@ -0,0 +1 @@ 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b/usrp2/fpga/opencores/uart16550/sim/gate_sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/gate_sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/.keepme b/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Entries new file mode 100644 index 00000000..49302b14 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:52:53 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Repository new file mode 100644 index 00000000..23fff6f0 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/gate_sim/bin diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/gate_sim/bin/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/.keepme b/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Entries new file mode 100644 index 00000000..c6b9be28 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:52:56 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Repository new file mode 100644 index 00000000..a59f7759 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/gate_sim/log diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/gate_sim/log/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/.keepme b/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Entries new file mode 100644 index 00000000..ea09c988 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:52:58 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Repository new file mode 100644 index 00000000..90408263 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/gate_sim/out diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/gate_sim/out/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/.keepme b/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Entries new file mode 100644 index 00000000..170c5aa9 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:52:59 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Repository new file mode 100644 index 00000000..f0fe74e8 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/gate_sim/run diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/gate_sim/run/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/.keepme b/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Entries new file mode 100644 index 00000000..76093103 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:53:01 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Repository new file mode 100644 index 00000000..e90e5de3 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/gate_sim/src diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/gate_sim/src/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Entries.Log b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Entries.Log new file mode 100644 index 00000000..7a4fd3fe --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Entries.Log @@ -0,0 +1,5 @@ +A D/bin//// +A D/log//// +A D/out//// +A D/run//// +A D/src//// diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Repository new file mode 100644 index 00000000..6880ade9 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/rtl_sim diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries new file mode 100644 index 00000000..4993d601 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries @@ -0,0 +1,3 @@ +/nc.scr/1.4/Mon Jul 29 21:15:18 2002/-kb/ +/sim.tcl/1.2/Mon Dec 3 21:44:29 2001/-kb/ +D diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository new file mode 100644 index 00000000..1ea808f7 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/rtl_sim/bin diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/nc.scr b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/nc.scr new file mode 100644 index 00000000..c42e3c34 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/nc.scr @@ -0,0 +1,9 @@ ++libext+.v ++access+wr ++mess ++incdir+../../../rtl/verilog+../../../bench/verilog ++tcl+../bin/sim.tcl +-y ../../../rtl/verilog +-y ../../../bench/verilog +../../../bench/verilog/uart_test.v +//+gui diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/sim.tcl b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/sim.tcl new file mode 100644 index 00000000..18a0dbec --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/bin/sim.tcl @@ -0,0 +1,5 @@ +database -open waves -into ../out/uart -default +probe -create -shm uart_test -all -depth all +stop -create -time 1000000000ns -relative +run +quit diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/.keepme b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Entries new file mode 100644 index 00000000..8a92af1b --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Entries @@ -0,0 +1,4 @@ +/.keepme/1.1/Sun Aug 12 18:53:04 2001// +/uart_interrupts_report.log/1.1/Sat Mar 27 04:09:24 2004// +/uart_interrupts_verbose.log/1.1/Sat Mar 27 04:09:24 2004// +D diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Repository new file mode 100644 index 00000000..61aafb85 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/rtl_sim/log diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_report.log b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_report.log new file mode 100644 index 00000000..64b5c188 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_report.log @@ -0,0 +1,23 @@ + +--------------------------------------------------------------------------- + +Initialization of UART. + PASSED! + Simulation Time: 621000 + +--------------------------------------------------------------------------- + +Interrupt test. + FAILED! + Failure message: Bit 5 of LSR register not '1'!. + Simulation Time: 5734521200 + +--------------------------------------------------------------------------- + +TEST CASE execution summary: +Number of tests PASSED=1 +Number of tests FAILED=1 + Simulation End Time: 5834521200 + +--------------------------------------------------------------------------- + diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_verbose.log b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_verbose.log new file mode 100644 index 00000000..0382f36e --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/log/uart_interrupts_verbose.log @@ -0,0 +1,104 @@ + +--------------------------------------------------------------------------- +- Initialization of UART. +--------------------------------------------------------------------------- + +Time: 200 (testbench_utilities.do_reset) +*N, RESET signal asynchronously set. +Time: 200 (testbench_utilities.disable_clk_generators) +*N, Following clocks are DISABLED: +Time: 200 (testbench_utilities.disable_clk_generators) +*N, - WB_clk +Time: 200 (testbench_utilities.disable_clk_generators) +*N, - RX_clk +Time: 200 (testbench_utilities.disable_clk_generators) +*N, - TX_clk +Time: 200 (testbench_utilities.disable_clk_generators) +*N, - TX_clk_divided +Time: 200 (testbench_utilities.set_device_tx_rx_clk_divisor) +*N, UART DEVICE TX/RX clock divisor: 1000. +Time: 200 (testbench_utilities.set_wb_clock_period) +*N, WB & UART DEVICE TX/RX clock period: 64. +Time: 200 (testbench_utilities.enable_clk_generators) +*N, Following clocks are ENABLED: +Time: 200 (testbench_utilities.enable_clk_generators) +*N, - WB_clk +Time: 200 (testbench_utilities.enable_clk_generators) +*N, - RX_clk +Time: 200 (testbench_utilities.enable_clk_generators) +*N, - TX_clk +Time: 200 (testbench_utilities.enable_clk_generators) +*N, - TX_clk_divided +Time: 11100 (testbench_utilities.release_reset) +*N, RESET signal released synchronously to WB clk. +Time: 11100 (uart_wb_utilities.write_dlr) +*N, DLAB in LC Register is going to be 1. +Time: 11100 (uart_wb_utilities.write_dlr) +*N, Current LCR = 3. +Time: 11100 (uart_wb_utilities.write_lcr) +*N, WRITING UART's LC Register. +Time: 101000 (uart_wb_utilities.write_lcr) +*N, Write LCR = 83. +Time: 101000 (uart_wb_utilities.write_dlr) +*N, WRITING UART's DL Register [15:8]. +Time: 161000 (uart_wb_utilities.write_dlr) +*N, Write DLR [15:8] = 10. +Time: 161000 (uart_wb_utilities.write_dlr) +*N, WRITING UART's DL Register [ 7:0]. +Time: 281000 (uart_wb_utilities.write_dlr) +*N, Write DLR [ 7:0] = 0. +Time: 281000 (uart_wb_utilities.write_dlr) +*N, DLAB in LC Register is going to be 0. +Time: 281000 (uart_wb_utilities.write_lcr) +*N, WRITING UART's LC Register. +Time: 371000 (uart_wb_utilities.write_lcr) +*N, Write LCR = 3. +Time: 371000 (uart_wb_utilities.write_ier) +*N, WRITING UART's IE Register. +Time: 411000 (uart_wb_utilities.write_ier) +*N, Write IER = 7. +Time: 411000 (uart_wb_utilities.write_fcr) +*N, WRITING UART's FC Register. +Time: 511000 (uart_wb_utilities.write_fcr) +*N, Write FCR = c0. +Time: 511000 (uart_wb_utilities.write_lcr) +*N, WRITING UART's LC Register. +Time: 621000 (uart_wb_utilities.write_lcr) +*N, Write LCR = 3. +Time: 621000 (uart_device_utilities.set_rx_length) +*N, SETTING RX CHAR length. +Time: 621000 (uart_device_utilities.set_rx_length) +*N, Length: 8. +Time: 621000 (uart_device_utilities.disable_rx_parity) +*N, DISABLING RX CHAR parity. +Time: 621000 (uart_device_utilities.set_rx_second_stop_bit) +*N, SETTING RX CHAR 1 stop bit. +Time: 621000 (uart_device_utilities.set_tx_length) +*N, SETTING TX CHAR length. +Time: 621000 (uart_device_utilities.set_tx_length) +*N, Length: 8. +Time: 621000 (uart_device_utilities.disable_tx_parity) +*N, DISABLING TX CHAR parity. +Time: 621000 (uart_device_utilities.correct_tx_parity) +*N, DISABLING WRONG parity generation. +Time: 621000 (uart_device_utilities.correct_tx_frame) +*N, DISABLING WRONG frame generation. +Time: 621000 (uart_device_utilities.generate_tx_glitch) +*N, DISABLING 1 TIME glitch generation with CLKs delay. +Time: 621000 (uart_device_utilities.generate_tx_glitch) +*N, CLKs delay from start bit edge: 0. + +--------------------------------------------------------------------------- +- Interrupt test. +--------------------------------------------------------------------------- + +Time: 621000 (testbench_utilities.wait_for_num_of_wb_clk) +*N, Waiting for following number of WB CLK periods: +Time: 621000 (testbench_utilities.wait_for_num_of_wb_clk) +*N, Waiting for following number of WB CLK periods: 450000. +Time: 701000 (uart_wb_utilities.write_char) +*N, Write TRR = aa. +Time: 5734501000 (testbench.write_tx_shift_reg_read_tx_fifo) +*N, TX FIFO is empty! +Time: 5734521200 (testbench.tx_fifo_status_changing) +*E, Bit 5 of LSR register not '1'! diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/.keepme b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Entries new file mode 100644 index 00000000..b974d366 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:53:06 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Repository new file mode 100644 index 00000000..e52a5c28 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/rtl_sim/out diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/out/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Entries new file mode 100644 index 00000000..0f0e80b1 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Entries @@ -0,0 +1,4 @@ +/run_signalscan/1.1.1.1/Sun Aug 12 16:27:51 2001/-kb/ +/run_sim/1.1.1.1/Sun Aug 12 16:27:51 2001/-kb/ +/run_sim.scr/1.1/Sat Mar 27 04:07:47 2004// +D diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Repository new file mode 100644 index 00000000..6dea2247 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/rtl_sim/run diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_signalscan b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_signalscan new file mode 100755 index 00000000..cd653656 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_signalscan @@ -0,0 +1,2 @@ +signalscan ../out/uart/uart.trn & +# -do ../out/uart/uart.do & diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_sim b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_sim new file mode 100755 index 00000000..f86c2f9b --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_sim @@ -0,0 +1 @@ +ncverilog -f ../bin/nc.scr & diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_sim.scr b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_sim.scr new file mode 100644 index 00000000..6bc0c5ee --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/run/run_sim.scr @@ -0,0 +1,345 @@ +#!/bin/csh -f + + +# GLOBAL VARIABLES +################### + +set sim_top = testbench; +set arg_tool = "NCSim"; # By default NCSim is used as simulation tool +set arg_wave = 0; # By default waveform is not recorded +set arg_verb = 0; # By default basic display on monitor (no verbose) +set arg_test = 0; # By default all testcases are simulated + + +# GETTING PARAMETERS FROM COMMAND LINE +####################################### + +set cur_arg = 1; + +if ($#argv < 1) then + echo "" + echo " Verification without any argument:" +else + + while ($cur_arg <= $#argv) + + switch ("$argv[$cur_arg]") + # HELP ARGUMENT + case "-h": + goto help + breaksw + case "help": + goto help + breaksw + # TOOL ARGUMENT + case "-m": + set arg_tool = "ModelSim"; + echo " $argv[$cur_arg] - ModelSim tool" + breaksw + case "modelsim" + set arg_tool = "ModelSim"; + echo " $argv[$cur_arg] - ModelSim tool" + breaksw + # WAVEFORM ARGUMENT + case "-w": + @ arg_wave = 1; + echo " $argv[$cur_arg] - Waveform" + breaksw + case "waveform": + @ arg_wave = 1; + echo " $argv[$cur_arg] - Waveform" + breaksw + # VERBOSE ARGUMENT + case "-v": + @ arg_verb = 1; + echo " $argv[$cur_arg] - Verbose" + breaksw + case "verbose": + @ arg_verb = 1; + echo " $argv[$cur_arg] - Verbose" + breaksw + # TESTCASE ARGUMENT + default: + if (-e ../../../bench/verilog/testcases/$argv[$cur_arg].v) then + set arg_test = $argv[$cur_arg]; + echo " $argv[$cur_arg] - Testcase" + # INVALID ARGUMENT + else + echo "" + echo " Invalid verification argument: $argv[$cur_arg]" + goto help + endif + breaksw + endsw + + @ cur_arg++ + end + +endif + + +# SIMULATION LOOP +################## + +set cur_test_num = 0; + +simulate: + + + # DELETING FILES + ################# + + # Prepared files + if (-e ./file_list.lst) then + rm -rf ./file_list.lst + endif + if (-e ../bin/cds.lib) then + rm -rf ../bin/cds.lib + endif + if (-e ../bin/hdl.var) then + rm -rf ../bin/hdl.var + endif + if (-e ./compile.args) then + rm -rf ./compile.args + endif + if (-e ./elab.args) then + rm -rf ./elab.args + endif + if (-e ./sim.args) then + rm -rf ./sim.args + endif + if (-e ./sim.tcl) then + rm -rf ./sim.tcl + endif + if (-e ./sim.do) then + rm -rf ./sim.do + endif + + # Projects, Libraries and Logs + if (-e ./uart.mpf) then + rm -rf ./uart.mpf + endif + if (-e ./work) then + rm -rf ./work + endif + if (-e ./INCA_libs/worklib) then + rm -rf ./INCA_libs/worklib + endif + + + # PREPARING FILE LIST + ###################### + + # Design files + echo "../../../rtl/verilog/uart_top.v" >> ./file_list.lst + echo "../../../rtl/verilog/uart_wb.v" >> ./file_list.lst + echo "../../../rtl/verilog/uart_transmitter.v" >> ./file_list.lst + echo "../../../rtl/verilog/uart_receiver.v" >> ./file_list.lst + echo "../../../rtl/verilog/uart_tfifo.v" >> ./file_list.lst + echo "../../../rtl/verilog/uart_rfifo.v" >> ./file_list.lst + echo "../../../rtl/verilog/uart_regs.v" >> ./file_list.lst + echo "../../../rtl/verilog/uart_debug_if.v" >> ./file_list.lst + + # Testcase file + if ($arg_test == 0) then + set i = 0; + foreach testcase (../../../bench/verilog/testcases/uart*.v) + if ($i == $cur_test_num) then + set testcase_i = $testcase:t:r + endif + @ i++ + end + set max_test_num = $i; + else + set testcase_i = $arg_test; + set max_test_num = 1; + endif + echo "//////////////////////////////////////////////////" > ./file_list.lst + echo "// File created within script ${0}" >> ./file_list.lst + echo "// path: $cwd" >> ./file_list.lst + echo "// user: $user" >> ./file_list.lst + echo "//////////////////////////////////////////////////" >> ./file_list.lst + echo "../../../bench/verilog/testcases/$testcase_i.v" >> ./file_list.lst + # Delete vawe out file for this testcase, if it already exists + if (-e ../out/$testcase_i.wlf) then + rm -rf ../out/$testcase_i.wlf + endif + # Delete log out file for this testcase, if it already exists + if (-e ../log/$testcase_i.log) then + rm -rf ../log/$testcase_i.log + endif + + # Testbench files + echo "../../../bench/verilog/uart_testbench.v" >> ./file_list.lst + echo "../../../bench/verilog/wb_master_model.v" >> ./file_list.lst + echo "../../../bench/verilog/uart_device.v" >> ./file_list.lst + echo "../../../bench/verilog/uart_testbench_utilities.v" >> ./file_list.lst + echo "../../../bench/verilog/uart_wb_utilities.v" >> ./file_list.lst + echo "../../../bench/verilog/uart_device_utilities.v" >> ./file_list.lst + + + # COMPILING & ELABORATING + ########################## + + if ("$arg_tool" == "NCSim") then + + # cds.lib library file + echo "//////////////////////////////////////////////////" > ../bin/cds.lib + echo "// File created within script ${0}" >> ../bin/cds.lib + echo "// path: $cwd" >> ../bin/cds.lib + echo "// user: $0" >> ../bin/cds.lib + echo "//////////////////////////////////////////////////" >> ../bin/cds.lib + echo "DEFINE worklib ./INCA_libs/worklib" >> ../bin/cds.lib + + # hdl.var variable file + echo "//////////////////////////////////////////////////" > ../bin/hdl.var + echo "// File created within script ${0}" >> ../bin/hdl.var + echo "// path: $cwd" >> ../bin/hdl.var + echo "// user: $0" >> ../bin/hdl.var + echo "//////////////////////////////////////////////////" >> ../bin/hdl.var + echo "INCLUDE \$CDS_INST_DIR/tools/inca/files/hdl.var" >> ../bin/hdl.var + echo "DEFINE WORK worklib" >> ../bin/hdl.var + + # compile.args argument file + echo "//////////////////////////////////////////////////" > ./compile.args + echo "// File created within script ${0}" >> ./compile.args + echo "// path: $cwd" >> ./compile.args + echo "// user: $0" >> ./compile.args + echo "//////////////////////////////////////////////////" >> ./compile.args + echo "-CDSLIB ../bin/cds.lib" >> ./compile.args + echo "-HDLVAR ../bin/hdl.var" >> ./compile.args + echo "-MESSAGES" >> ./compile.args + echo "-NOCOPYRIGHT" >> ./compile.args + echo "-INCDIR ../../../rtl/verilog" >> ./compile.args + echo "-INCDIR ../../../bench/verilog" >> ./compile.args + echo "-INCDIR ../../../bench/verilog/testcases" >> ./compile.args + if ($arg_verb == 1) then + echo "-DEFINE VERBOSE" >> ./compile.args + endif + cat ./file_list.lst >> ./compile.args + + # compiling + ncvlog -LOGFILE ../log/$testcase_i.compile.log -f ./compile.args #> /dev/null + + # elab.args argument file + echo "//////////////////////////////////////////////////" > ./elab.args + echo "// File created within script ${0}" >> ./elab.args + echo "// path: $cwd" >> ./elab.args + echo "// user: $0" >> ./elab.args + echo "//////////////////////////////////////////////////" >> ./elab.args + echo "-CDSLIB ../bin/cds.lib" >> ./elab.args + echo "-HDLVAR ../bin/hdl.var" >> ./elab.args + echo "-MESSAGES" >> ./elab.args + echo "-NOCOPYRIGHT" >> ./elab.args + echo "-NOTIMINGCHECKS" >> ./elab.args + echo "-SNAPSHOT worklib.testbench:rtl" >> ./elab.args + echo "-NO_TCHK_MSG" >> ./elab.args + echo "-ACCESS +RWC" >> ./elab.args + echo "worklib.$sim_top" >> ./elab.args + + # elaborating + ncelab -LOGFILE ../log/$testcase_i.elab.log -f ./elab.args #> /dev/null + else + + # compile.args argument file + echo "+libext+.v" >> ./compile.args + echo "-y ../../../rtl/verilog" >> ./compile.args + echo "-y ../../../bench/verilog" >> ./compile.args + echo "-y ../../../bench/verilog/testcases" >> ./compile.args + echo "-work ./work" >> ./compile.args + echo "+incdir+../../../rtl/verilog" >> ./compile.args + echo "+incdir+../../../bench/verilog" >> ./compile.args + echo '+define+LOG_DIR=\"../log/$testcase_i\"' >> ./compile.args + if ($arg_verb == 1) then + echo "+define+VERBOSE" >> ./compile.args + endif + cat ./file_list.lst >> ./compile.args + + # open project +# echo "project new ./ testbench ./work" >> ./sim.do + vlib -dos ./work + + # compiling + # echo "vlog -f ./compile.args" >> ./sim.do + vlog -f ./compile.args + endif + + + # SIMULATING + ############# + + if ("$arg_tool" == "NCSim") then + + # sim.args argument file + echo "//////////////////////////////////////////////////" > ./sim.args + echo "// File created within script ${0}" >> ./sim.args + echo "// path: $cwd" >> ./sim.args + echo "// user: $0" >> ./sim.args + echo "//////////////////////////////////////////////////" >> ./sim.args + echo "-CDSLIB ../bin/cds.lib" >> ./sim.args + echo "-HDLVAR ../bin/hdl.var" >> ./sim.args + echo "-MESSAGES" >> ./sim.args + echo "-NOCOPYRIGHT" >> ./sim.args + echo "-INPUT ./sim.tcl" >> ./sim.args + echo "worklib.testbench:rtl" >> ./sim.args + + # sim.tcl file + echo "//////////////////////////////////////////////////" > ./sim.tcl + echo "// File created within script ${0}" >> ./sim.tcl + echo "// path: $cwd" >> ./sim.tcl + echo "// user: $0" >> ./sim.tcl + echo "//////////////////////////////////////////////////" >> ./sim.tcl + if ($arg_wave) then + echo "database -open waves -shm -into ../out/waves.shm" >> ./sim.tcl + echo "probe -create -database waves $sim_top -shm -all -depth all" >> ./sim.tcl + echo "run" >> ./sim.tcl + else + echo "run" >> ./sim.tcl + endif + echo "quit" >> ./sim.tcl + + # simulating + ncsim -LICQUEUE -LOGFILE ../log/$testcase_i.sim.log -f ./sim.args + else + + # sim.do do file + echo "vsim work.testbench work.testbench_utilities work.uart_wb_utilities work.uart_device_utilities work.testcase -wlf ../out/$testcase_i.wlf" >> ./sim.do + if ($arg_wave) then + echo "log -r -internal -ports /testbench/*" >> ./sim.do + endif + echo "run -all" >> ./sim.do + + vsim -c -do ./sim.do + + endif + + @ cur_test_num++ + + if ($cur_test_num < $max_test_num) then + goto simulate + endif + +exit + + +# HELP DISPLAY +############### + +help: + echo "" + echo " Valid verification arguments:" + echo " 'help' / '-h' : This help is displayed" + echo " 'modelsim' / '-m' : ModelSim simulation tool is used, otherwise" + echo " NCSim is used (default)" + echo " 'waveform' / '-w' : Waveform output is recorded, otherwise" + echo " NO waveform is recorded (default)" + echo " 'verbose' / '-v' : Verbose display on monitor, otherwise" + echo " basic display on monitor (default)" + echo " '\042testcase\042' : Testcase which is going to be simulated, otherwise" + echo " ALL testcases are simulated - regression (default);" + echo " Available testcases:" + foreach testcase (../../../bench/verilog/testcases/uart*.v) + echo " "$testcase:t:r + end + echo "" +exit diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/.keepme b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Entries b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Entries new file mode 100644 index 00000000..b974d366 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:53:06 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Repository b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Repository new file mode 100644 index 00000000..8c096f11 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/rtl_sim/src diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Root b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Template b/usrp2/fpga/opencores/uart16550/sim/rtl_sim/src/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/CVS/Entries b/usrp2/fpga/opencores/uart16550/syn/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/uart16550/syn/CVS/Entries.Log b/usrp2/fpga/opencores/uart16550/syn/CVS/Entries.Log new file mode 100644 index 00000000..7a4fd3fe --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/CVS/Entries.Log @@ -0,0 +1,5 @@ +A D/bin//// +A D/log//// +A D/out//// +A D/run//// +A D/src//// diff --git a/usrp2/fpga/opencores/uart16550/syn/CVS/Repository b/usrp2/fpga/opencores/uart16550/syn/CVS/Repository new file mode 100644 index 00000000..6af4f4f1 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/CVS/Repository @@ -0,0 +1 @@ +uart16550/syn diff --git a/usrp2/fpga/opencores/uart16550/syn/CVS/Root b/usrp2/fpga/opencores/uart16550/syn/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/syn/CVS/Template b/usrp2/fpga/opencores/uart16550/syn/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/bin/.keepme b/usrp2/fpga/opencores/uart16550/syn/bin/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Entries b/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Entries new file mode 100644 index 00000000..b974d366 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:53:06 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Repository b/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Repository new file mode 100644 index 00000000..e7bbabb1 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Repository @@ -0,0 +1 @@ +uart16550/syn/bin diff --git a/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Root b/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Template b/usrp2/fpga/opencores/uart16550/syn/bin/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/log/.keepme b/usrp2/fpga/opencores/uart16550/syn/log/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/log/CVS/Entries b/usrp2/fpga/opencores/uart16550/syn/log/CVS/Entries new file mode 100644 index 00000000..b974d366 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/log/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:53:06 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/syn/log/CVS/Repository b/usrp2/fpga/opencores/uart16550/syn/log/CVS/Repository new file mode 100644 index 00000000..e6e7d32f --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/log/CVS/Repository @@ -0,0 +1 @@ +uart16550/syn/log diff --git a/usrp2/fpga/opencores/uart16550/syn/log/CVS/Root b/usrp2/fpga/opencores/uart16550/syn/log/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/log/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/syn/log/CVS/Template b/usrp2/fpga/opencores/uart16550/syn/log/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/out/.keepme b/usrp2/fpga/opencores/uart16550/syn/out/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/out/CVS/Entries b/usrp2/fpga/opencores/uart16550/syn/out/CVS/Entries new file mode 100644 index 00000000..b974d366 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/out/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:53:06 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/syn/out/CVS/Repository b/usrp2/fpga/opencores/uart16550/syn/out/CVS/Repository new file mode 100644 index 00000000..2a89f947 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/out/CVS/Repository @@ -0,0 +1 @@ +uart16550/syn/out diff --git a/usrp2/fpga/opencores/uart16550/syn/out/CVS/Root b/usrp2/fpga/opencores/uart16550/syn/out/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/out/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/syn/out/CVS/Template b/usrp2/fpga/opencores/uart16550/syn/out/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/run/.keepme b/usrp2/fpga/opencores/uart16550/syn/run/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/run/CVS/Entries b/usrp2/fpga/opencores/uart16550/syn/run/CVS/Entries new file mode 100644 index 00000000..892fcc4a --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/run/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:53:07 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/syn/run/CVS/Repository b/usrp2/fpga/opencores/uart16550/syn/run/CVS/Repository new file mode 100644 index 00000000..5a41dd3c --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/run/CVS/Repository @@ -0,0 +1 @@ +uart16550/syn/run diff --git a/usrp2/fpga/opencores/uart16550/syn/run/CVS/Root b/usrp2/fpga/opencores/uart16550/syn/run/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/syn/run/CVS/Template b/usrp2/fpga/opencores/uart16550/syn/run/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/src/.keepme b/usrp2/fpga/opencores/uart16550/syn/src/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/syn/src/CVS/Entries b/usrp2/fpga/opencores/uart16550/syn/src/CVS/Entries new file mode 100644 index 00000000..892fcc4a --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/src/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:53:07 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/syn/src/CVS/Repository b/usrp2/fpga/opencores/uart16550/syn/src/CVS/Repository new file mode 100644 index 00000000..2ecee2b8 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/src/CVS/Repository @@ -0,0 +1 @@ +uart16550/syn/src diff --git a/usrp2/fpga/opencores/uart16550/syn/src/CVS/Root b/usrp2/fpga/opencores/uart16550/syn/src/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/syn/src/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/syn/src/CVS/Template b/usrp2/fpga/opencores/uart16550/syn/src/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/verilog/CVS/Entries b/usrp2/fpga/opencores/uart16550/verilog/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/verilog/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/uart16550/verilog/CVS/Repository b/usrp2/fpga/opencores/uart16550/verilog/CVS/Repository new file mode 100644 index 00000000..61165834 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/verilog/CVS/Repository @@ -0,0 +1 @@ +uart16550/verilog diff --git a/usrp2/fpga/opencores/uart16550/verilog/CVS/Root b/usrp2/fpga/opencores/uart16550/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/verilog/CVS/Template b/usrp2/fpga/opencores/uart16550/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/wb_conbus/CVS/Entries b/usrp2/fpga/opencores/wb_conbus/CVS/Entries new file mode 100644 index 00000000..38a42028 --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/CVS/Entries @@ -0,0 +1,2 @@ +D/bench//// +D/rtl//// diff --git a/usrp2/fpga/opencores/wb_conbus/CVS/Repository b/usrp2/fpga/opencores/wb_conbus/CVS/Repository new file mode 100644 index 00000000..df791b1f --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/CVS/Repository @@ -0,0 +1 @@ +wb_conbus diff --git a/usrp2/fpga/opencores/wb_conbus/CVS/Root b/usrp2/fpga/opencores/wb_conbus/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/wb_conbus/CVS/Template b/usrp2/fpga/opencores/wb_conbus/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/wb_conbus/bench/CVS/Entries b/usrp2/fpga/opencores/wb_conbus/bench/CVS/Entries new file mode 100644 index 00000000..428c5622 --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/bench/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/fpga/opencores/wb_conbus/bench/CVS/Repository b/usrp2/fpga/opencores/wb_conbus/bench/CVS/Repository new file mode 100644 index 00000000..eaa8d3ab --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/bench/CVS/Repository @@ -0,0 +1 @@ +wb_conbus/bench diff --git a/usrp2/fpga/opencores/wb_conbus/bench/CVS/Root b/usrp2/fpga/opencores/wb_conbus/bench/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/bench/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/wb_conbus/bench/CVS/Template b/usrp2/fpga/opencores/wb_conbus/bench/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Entries b/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Entries new file mode 100644 index 00000000..76919de4 --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Entries @@ -0,0 +1,6 @@ +/tb_wb_conbus_top.v/1.1.1.1/Sat Apr 19 08:40:17 2003// +/tests.v/1.1.1.1/Sat Apr 19 08:40:17 2003// +/wb_mast_model.v/1.1.1.1/Sat Apr 19 08:40:15 2003// +/wb_model_defines.v/1.1.1.1/Sat Apr 19 08:40:16 2003// +/wb_slv_model.v/1.1.1.1/Sat Apr 19 08:40:16 2003// +D diff --git a/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Repository b/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Repository new file mode 100644 index 00000000..30644530 --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Repository @@ -0,0 +1 @@ +wb_conbus/bench/verilog diff --git a/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Root b/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Template b/usrp2/fpga/opencores/wb_conbus/bench/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/wb_conbus/bench/verilog/tb_wb_conbus_top.v b/usrp2/fpga/opencores/wb_conbus/bench/verilog/tb_wb_conbus_top.v new file mode 100644 index 00000000..e15d089f --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/bench/verilog/tb_wb_conbus_top.v @@ -0,0 +1,759 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Top Level Test Bench //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +// +// +// rewrite from test the wb_conbus module +// +// + + +`include "wb_conbus_defines.v" + +module tb_wb_conbus; + +reg clk; +reg rst; + +// IO Prototypes +wire [31:0] m0_data_i; +wire [31:0] m0_data_o; +wire [31:0] m0_addr_i; +wire [3:0] m0_sel_i; +wire m0_we_i; +wire m0_cyc_i; +wire m0_stb_i; +wire m0_ack_o; +wire m0_err_o; +wire m0_rty_o; +wire [31:0] m1_data_i; +wire [31:0] m1_data_o; +wire [31:0] m1_addr_i; +wire [3:0] m1_sel_i; +wire m1_we_i; +wire m1_cyc_i; +wire m1_stb_i; +wire m1_ack_o; +wire m1_err_o; +wire m1_rty_o; +wire [31:0] m2_data_i; +wire [31:0] m2_data_o; +wire [31:0] m2_addr_i; +wire [3:0] m2_sel_i; +wire m2_we_i; +wire m2_cyc_i; +wire m2_stb_i; +wire m2_ack_o; +wire m2_err_o; +wire m2_rty_o; +wire [31:0] m3_data_i; +wire [31:0] m3_data_o; +wire [31:0] m3_addr_i; +wire [3:0] m3_sel_i; +wire m3_we_i; +wire m3_cyc_i; +wire m3_stb_i; +wire m3_ack_o; +wire m3_err_o; +wire m3_rty_o; +wire [31:0] m4_data_i; +wire [31:0] m4_data_o; +wire [31:0] m4_addr_i; +wire [3:0] m4_sel_i; +wire m4_we_i; +wire m4_cyc_i; +wire m4_stb_i; +wire m4_ack_o; +wire m4_err_o; +wire m4_rty_o; +wire [31:0] m5_data_i; +wire [31:0] m5_data_o; +wire [31:0] m5_addr_i; +wire [3:0] m5_sel_i; +wire m5_we_i; +wire m5_cyc_i; +wire m5_stb_i; +wire m5_ack_o; +wire m5_err_o; +wire m5_rty_o; +wire [31:0] m6_data_i; +wire [31:0] m6_data_o; +wire [31:0] m6_addr_i; +wire [3:0] m6_sel_i; +wire m6_we_i; +wire m6_cyc_i; +wire m6_stb_i; +wire m6_ack_o; +wire m6_err_o; +wire m6_rty_o; +wire [31:0] m7_data_i; +wire [31:0] m7_data_o; +wire [31:0] m7_addr_i; +wire [3:0] m7_sel_i; +wire m7_we_i; +wire m7_cyc_i; +wire m7_stb_i; +wire m7_ack_o; +wire m7_err_o; +wire m7_rty_o; +wire [31:0] s0_data_i; +wire [31:0] s0_data_o; +wire [31:0] s0_addr_o; +wire [3:0] s0_sel_o; +wire s0_we_o; +wire s0_cyc_o; +wire s0_stb_o; +wire s0_ack_i; +wire s0_err_i; +wire s0_rty_i; +wire [31:0] s1_data_i; +wire [31:0] s1_data_o; +wire [31:0] s1_addr_o; +wire [3:0] s1_sel_o; +wire s1_we_o; +wire s1_cyc_o; +wire s1_stb_o; +wire s1_ack_i; +wire s1_err_i; +wire s1_rty_i; +wire [31:0] s2_data_i; +wire [31:0] s2_data_o; +wire [31:0] s2_addr_o; +wire [3:0] s2_sel_o; +wire s2_we_o; +wire s2_cyc_o; +wire s2_stb_o; +wire s2_ack_i; +wire s2_err_i; +wire s2_rty_i; +wire [31:0] s3_data_i; +wire [31:0] s3_data_o; +wire [31:0] s3_addr_o; +wire [3:0] s3_sel_o; +wire s3_we_o; +wire s3_cyc_o; +wire s3_stb_o; +wire s3_ack_i; +wire s3_err_i; +wire s3_rty_i; +wire [31:0] s4_data_i; +wire [31:0] s4_data_o; +wire [31:0] s4_addr_o; +wire [3:0] s4_sel_o; +wire s4_we_o; +wire s4_cyc_o; +wire s4_stb_o; +wire s4_ack_i; +wire s4_err_i; +wire s4_rty_i; +wire [31:0] s5_data_i; +wire [31:0] s5_data_o; +wire [31:0] s5_addr_o; +wire [3:0] s5_sel_o; +wire s5_we_o; +wire s5_cyc_o; +wire s5_stb_o; +wire s5_ack_i; +wire s5_err_i; +wire s5_rty_i; +wire [31:0] s6_data_i; +wire [31:0] s6_data_o; +wire [31:0] s6_addr_o; +wire [3:0] s6_sel_o; +wire s6_we_o; +wire s6_cyc_o; +wire s6_stb_o; +wire s6_ack_i; +wire s6_err_i; +wire s6_rty_i; +wire [31:0] s7_data_i; +wire [31:0] s7_data_o; +wire [31:0] s7_addr_o; +wire [3:0] s7_sel_o; +wire s7_we_o; +wire s7_cyc_o; +wire s7_stb_o; +wire s7_ack_i; +wire s7_err_i; +wire s7_rty_i; + + + +// Test Bench Variables +reg [31:0] wd_cnt; +integer error_cnt; +integer verbose; + +// Misc Variables + +///////////////////////////////////////////////////////////////////// +// +// Defines +// + + +///////////////////////////////////////////////////////////////////// +// +// Simulation Initialization and Start up Section +// + + +initial + begin + $timeformat (-9, 1, " ns", 10); + + $display("\n\n"); + $display("*****************************************************"); + $display("* WISHBONE Connection Matrix Simulation started ... *"); + $display("*****************************************************"); + $display("\n"); + +`ifdef WAVES + $shm_open("waves"); + $shm_probe("AS",test,"AS"); + $display("INFO: Signal dump enabled ...\n\n"); +`endif + wd_cnt = 0; + error_cnt = 0; + clk = 1; + rst = 1; + verbose = 1; + + repeat(5) @(posedge clk); + s0.delay = 1; + s1.delay = 1; + s2.delay = 1; + s3.delay = 1; + s4.delay = 1; + s5.delay = 1; + s6.delay = 1; + s7.delay = 1; + + #1; + rst = 0; + repeat(5) @(posedge clk); + + // HERE IS WHERE THE TEST CASES GO ... + +if(1) // Full Regression Run + begin + $display(" ......................................................"); + $display(" : :"); + $display(" : Regression Run ... :"); + $display(" :....................................................:"); + verbose = 0; + + test_dp1; +// test_rf; +// test_arb1; +// test_arb2; + test_dp2; + + end +else +if(1) // Debug Tests + begin + $display(" ......................................................"); + $display(" : :"); + $display(" : Test Debug Testing ... :"); + $display(" :....................................................:"); + + test_dp2; + + end + +repeat(100) @(posedge clk); +$finish; +end // End of Initial + +///////////////////////////////////////////////////////////////////// +// +// Clock Generation +// + +always #5 clk = ~clk; + +///////////////////////////////////////////////////////////////////// +// +// Watchdog Counter +// + +always @(posedge clk) + if(m0_ack_o | m1_ack_o | m2_ack_o | m3_ack_o | + m4_ack_o | m5_ack_o | m6_ack_o | m7_ack_o) + wd_cnt = 0; + else + wd_cnt = wd_cnt +1; + +always @(wd_cnt) + if(wd_cnt > 5000000) + begin + $display("\n*******************************************"); + $display("*** ERROR: Watchdog Counter Expired ... ***"); + $display("*******************************************\n"); + $finish; + end + +///////////////////////////////////////////////////////////////////// +// +// IO Monitors +// + +///////////////////////////////////////////////////////////////////// +// +// WISHBONE Inter Connect +// + +wb_conbus_top #(4, + 4'h0, + 4, + 4'h1, + 4, + 4'h2, + 4'h3, + 4'h4, + 4'h5, + 4'h6, + 4'h7 + ) + conbus( + .clk_i( clk ), + .rst_i( rst ), + .m0_dat_i( m0_data_i ), + .m0_dat_o( m0_data_o ), + .m0_adr_i( m0_addr_i ), + .m0_sel_i( m0_sel_i ), + .m0_we_i( m0_we_i ), + .m0_cyc_i( m0_cyc_i ), + .m0_stb_i( m0_stb_i ), + .m0_ack_o( m0_ack_o ), + .m0_err_o( m0_err_o ), + .m0_rty_o( m0_rty_o ), + .m1_dat_i( m1_data_i ), + .m1_dat_o( m1_data_o ), + .m1_adr_i( m1_addr_i ), + .m1_sel_i( m1_sel_i ), + .m1_we_i( m1_we_i ), + .m1_cyc_i( m1_cyc_i ), + .m1_stb_i( m1_stb_i ), + .m1_ack_o( m1_ack_o ), + .m1_err_o( m1_err_o ), + .m1_rty_o( m1_rty_o ), + .m2_dat_i( m2_data_i ), + .m2_dat_o( m2_data_o ), + .m2_adr_i( m2_addr_i ), + .m2_sel_i( m2_sel_i ), + .m2_we_i( m2_we_i ), + .m2_cyc_i( m2_cyc_i ), + .m2_stb_i( m2_stb_i ), + .m2_ack_o( m2_ack_o ), + .m2_err_o( m2_err_o ), + .m2_rty_o( m2_rty_o ), + .m3_dat_i( m3_data_i ), + .m3_dat_o( m3_data_o ), + .m3_adr_i( m3_addr_i ), + .m3_sel_i( m3_sel_i ), + .m3_we_i( m3_we_i ), + .m3_cyc_i( m3_cyc_i ), + .m3_stb_i( m3_stb_i ), + .m3_ack_o( m3_ack_o ), + .m3_err_o( m3_err_o ), + .m3_rty_o( m3_rty_o ), + .m4_dat_i( m4_data_i ), + .m4_dat_o( m4_data_o ), + .m4_adr_i( m4_addr_i ), + .m4_sel_i( m4_sel_i ), + .m4_we_i( m4_we_i ), + .m4_cyc_i( m4_cyc_i ), + .m4_stb_i( m4_stb_i ), + .m4_ack_o( m4_ack_o ), + .m4_err_o( m4_err_o ), + .m4_rty_o( m4_rty_o ), + .m5_dat_i( m5_data_i ), + .m5_dat_o( m5_data_o ), + .m5_adr_i( m5_addr_i ), + .m5_sel_i( m5_sel_i ), + .m5_we_i( m5_we_i ), + .m5_cyc_i( m5_cyc_i ), + .m5_stb_i( m5_stb_i ), + .m5_ack_o( m5_ack_o ), + .m5_err_o( m5_err_o ), + .m5_rty_o( m5_rty_o ), + .m6_dat_i( m6_data_i ), + .m6_dat_o( m6_data_o ), + .m6_adr_i( m6_addr_i ), + .m6_sel_i( m6_sel_i ), + .m6_we_i( m6_we_i ), + .m6_cyc_i( m6_cyc_i ), + .m6_stb_i( m6_stb_i ), + .m6_ack_o( m6_ack_o ), + .m6_err_o( m6_err_o ), + .m6_rty_o( m6_rty_o ), + .m7_dat_i( m7_data_i ), + .m7_dat_o( m7_data_o ), + .m7_adr_i( m7_addr_i ), + .m7_sel_i( m7_sel_i ), + .m7_we_i( m7_we_i ), + .m7_cyc_i( m7_cyc_i ), + .m7_stb_i( m7_stb_i ), + .m7_ack_o( m7_ack_o ), + .m7_err_o( m7_err_o ), + .m7_rty_o( m7_rty_o ), + .s0_dat_i( s0_data_i ), + .s0_dat_o( s0_data_o ), + .s0_adr_o( s0_addr_o ), + .s0_sel_o( s0_sel_o ), + .s0_we_o( s0_we_o ), + .s0_cyc_o( s0_cyc_o ), + .s0_stb_o( s0_stb_o ), + .s0_ack_i( s0_ack_i ), + .s0_err_i( s0_err_i ), + .s0_rty_i( s0_rty_i ), + .s1_dat_i( s1_data_i ), + .s1_dat_o( s1_data_o ), + .s1_adr_o( s1_addr_o ), + .s1_sel_o( s1_sel_o ), + .s1_we_o( s1_we_o ), + .s1_cyc_o( s1_cyc_o ), + .s1_stb_o( s1_stb_o ), + .s1_ack_i( s1_ack_i ), + .s1_err_i( s1_err_i ), + .s1_rty_i( s1_rty_i ), + .s2_dat_i( s2_data_i ), + .s2_dat_o( s2_data_o ), + .s2_adr_o( s2_addr_o ), + .s2_sel_o( s2_sel_o ), + .s2_we_o( s2_we_o ), + .s2_cyc_o( s2_cyc_o ), + .s2_stb_o( s2_stb_o ), + .s2_ack_i( s2_ack_i ), + .s2_err_i( s2_err_i ), + .s2_rty_i( s2_rty_i ), + .s3_dat_i( s3_data_i ), + .s3_dat_o( s3_data_o ), + .s3_adr_o( s3_addr_o ), + .s3_sel_o( s3_sel_o ), + .s3_we_o( s3_we_o ), + .s3_cyc_o( s3_cyc_o ), + .s3_stb_o( s3_stb_o ), + .s3_ack_i( s3_ack_i ), + .s3_err_i( s3_err_i ), + .s3_rty_i( s3_rty_i ), + .s4_dat_i( s4_data_i ), + .s4_dat_o( s4_data_o ), + .s4_adr_o( s4_addr_o ), + .s4_sel_o( s4_sel_o ), + .s4_we_o( s4_we_o ), + .s4_cyc_o( s4_cyc_o ), + .s4_stb_o( s4_stb_o ), + .s4_ack_i( s4_ack_i ), + .s4_err_i( s4_err_i ), + .s4_rty_i( s4_rty_i ), + .s5_dat_i( s5_data_i ), + .s5_dat_o( s5_data_o ), + .s5_adr_o( s5_addr_o ), + .s5_sel_o( s5_sel_o ), + .s5_we_o( s5_we_o ), + .s5_cyc_o( s5_cyc_o ), + .s5_stb_o( s5_stb_o ), + .s5_ack_i( s5_ack_i ), + .s5_err_i( s5_err_i ), + .s5_rty_i( s5_rty_i ), + .s6_dat_i( s6_data_i ), + .s6_dat_o( s6_data_o ), + .s6_adr_o( s6_addr_o ), + .s6_sel_o( s6_sel_o ), + .s6_we_o( s6_we_o ), + .s6_cyc_o( s6_cyc_o ), + .s6_stb_o( s6_stb_o ), + .s6_ack_i( s6_ack_i ), + .s6_err_i( s6_err_i ), + .s6_rty_i( s6_rty_i ), + .s7_dat_i( s7_data_i ), + .s7_dat_o( s7_data_o ), + .s7_adr_o( s7_addr_o ), + .s7_sel_o( s7_sel_o ), + .s7_we_o( s7_we_o ), + .s7_cyc_o( s7_cyc_o ), + .s7_stb_o( s7_stb_o ), + .s7_ack_i( s7_ack_i ), + .s7_err_i( s7_err_i ), + .s7_rty_i( s7_rty_i ) + ); + + +///////////////////////////////////////////////////////////////////// +// +// WISHBONE Master Models +// + +wb_mast m0( .clk( clk ), + .rst( ~rst ), + .adr( m0_addr_i ), + .din( m0_data_o ), + .dout( m0_data_i ), + .cyc( m0_cyc_i ), + .stb( m0_stb_i ), + .sel( m0_sel_i ), + .we( m0_we_i ), + .ack( m0_ack_o ), + .err( m0_err_o ), + .rty( m0_rty_o ) + ); + +wb_mast m1( .clk( clk ), + .rst( ~rst ), + .adr( m1_addr_i ), + .din( m1_data_o ), + .dout( m1_data_i ), + .cyc( m1_cyc_i ), + .stb( m1_stb_i ), + .sel( m1_sel_i ), + .we( m1_we_i ), + .ack( m1_ack_o ), + .err( m1_err_o ), + .rty( m1_rty_o ) + ); + +wb_mast m2( .clk( clk ), + .rst( ~rst ), + .adr( m2_addr_i ), + .din( m2_data_o ), + .dout( m2_data_i ), + .cyc( m2_cyc_i ), + .stb( m2_stb_i ), + .sel( m2_sel_i ), + .we( m2_we_i ), + .ack( m2_ack_o ), + .err( m2_err_o ), + .rty( m2_rty_o ) + ); + +wb_mast m3( .clk( clk ), + .rst( ~rst ), + .adr( m3_addr_i ), + .din( m3_data_o ), + .dout( m3_data_i ), + .cyc( m3_cyc_i ), + .stb( m3_stb_i ), + .sel( m3_sel_i ), + .we( m3_we_i ), + .ack( m3_ack_o ), + .err( m3_err_o ), + .rty( m3_rty_o ) + ); + +wb_mast m4( .clk( clk ), + .rst( ~rst ), + .adr( m4_addr_i ), + .din( m4_data_o ), + .dout( m4_data_i ), + .cyc( m4_cyc_i ), + .stb( m4_stb_i ), + .sel( m4_sel_i ), + .we( m4_we_i ), + .ack( m4_ack_o ), + .err( m4_err_o ), + .rty( m4_rty_o ) + ); + +wb_mast m5( .clk( clk ), + .rst( ~rst ), + .adr( m5_addr_i ), + .din( m5_data_o ), + .dout( m5_data_i ), + .cyc( m5_cyc_i ), + .stb( m5_stb_i ), + .sel( m5_sel_i ), + .we( m5_we_i ), + .ack( m5_ack_o ), + .err( m5_err_o ), + .rty( m5_rty_o ) + ); + +wb_mast m6( .clk( clk ), + .rst( ~rst ), + .adr( m6_addr_i ), + .din( m6_data_o ), + .dout( m6_data_i ), + .cyc( m6_cyc_i ), + .stb( m6_stb_i ), + .sel( m6_sel_i ), + .we( m6_we_i ), + .ack( m6_ack_o ), + .err( m6_err_o ), + .rty( m6_rty_o ) + ); + +wb_mast m7( .clk( clk ), + .rst( ~rst ), + .adr( m7_addr_i ), + .din( m7_data_o ), + .dout( m7_data_i ), + .cyc( m7_cyc_i ), + .stb( m7_stb_i ), + .sel( m7_sel_i ), + .we( m7_we_i ), + .ack( m7_ack_o ), + .err( m7_err_o ), + .rty( m7_rty_o ) + ); + + +///////////////////////////////////////////////////////////////////// +// +// WISHBONE Slave Models +// + +wb_slv s0( .clk( clk ), + .rst( ~rst ), + .adr( s0_addr_o ), + .din( s0_data_o ), + .dout( s0_data_i ), + .cyc( s0_cyc_o ), + .stb( s0_stb_o ), + .sel( s0_sel_o ), + .we( s0_we_o ), + .ack( s0_ack_i ), + .err( s0_err_i ), + .rty( s0_rty_i ) + ); + +wb_slv s1( .clk( clk ), + .rst( ~rst ), + .adr( s1_addr_o ), + .din( s1_data_o ), + .dout( s1_data_i ), + .cyc( s1_cyc_o ), + .stb( s1_stb_o ), + .sel( s1_sel_o ), + .we( s1_we_o ), + .ack( s1_ack_i ), + .err( s1_err_i ), + .rty( s1_rty_i ) + ); + +wb_slv s2( .clk( clk ), + .rst( ~rst ), + .adr( s2_addr_o ), + .din( s2_data_o ), + .dout( s2_data_i ), + .cyc( s2_cyc_o ), + .stb( s2_stb_o ), + .sel( s2_sel_o ), + .we( s2_we_o ), + .ack( s2_ack_i ), + .err( s2_err_i ), + .rty( s2_rty_i ) + ); + +wb_slv s3( .clk( clk ), + .rst( ~rst ), + .adr( s3_addr_o ), + .din( s3_data_o ), + .dout( s3_data_i ), + .cyc( s3_cyc_o ), + .stb( s3_stb_o ), + .sel( s3_sel_o ), + .we( s3_we_o ), + .ack( s3_ack_i ), + .err( s3_err_i ), + .rty( s3_rty_i ) + ); + +wb_slv s4( .clk( clk ), + .rst( ~rst ), + .adr( s4_addr_o ), + .din( s4_data_o ), + .dout( s4_data_i ), + .cyc( s4_cyc_o ), + .stb( s4_stb_o ), + .sel( s4_sel_o ), + .we( s4_we_o ), + .ack( s4_ack_i ), + .err( s4_err_i ), + .rty( s4_rty_i ) + ); + +wb_slv s5( .clk( clk ), + .rst( ~rst ), + .adr( s5_addr_o ), + .din( s5_data_o ), + .dout( s5_data_i ), + .cyc( s5_cyc_o ), + .stb( s5_stb_o ), + .sel( s5_sel_o ), + .we( s5_we_o ), + .ack( s5_ack_i ), + .err( s5_err_i ), + .rty( s5_rty_i ) + ); + +wb_slv s6( .clk( clk ), + .rst( ~rst ), + .adr( s6_addr_o ), + .din( s6_data_o ), + .dout( s6_data_i ), + .cyc( s6_cyc_o ), + .stb( s6_stb_o ), + .sel( s6_sel_o ), + .we( s6_we_o ), + .ack( s6_ack_i ), + .err( s6_err_i ), + .rty( s6_rty_i ) + ); + +wb_slv s7( .clk( clk ), + .rst( ~rst ), + .adr( s7_addr_o ), + .din( s7_data_o ), + .dout( s7_data_i ), + .cyc( s7_cyc_o ), + .stb( s7_stb_o ), + .sel( s7_sel_o ), + .we( s7_we_o ), + .ack( s7_ack_i ), + .err( s7_err_i ), + .rty( s7_rty_i ) + ); + + +`include "tests.v" + +endmodule + diff --git a/usrp2/fpga/opencores/wb_conbus/bench/verilog/tests.v b/usrp2/fpga/opencores/wb_conbus/bench/verilog/tests.v new file mode 100644 index 00000000..5067f269 --- /dev/null +++ b/usrp2/fpga/opencores/wb_conbus/bench/verilog/tests.v @@ -0,0 +1,828 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Matrix Test Cases //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: tests.v,v 1.1.1.1 2003/04/19 08:40:17 johny Exp $ +// +// $Date: 2003/04/19 08:40:17 $ +// $Revision: 1.1.1.1 $ +// $Author: johny $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: tests.v,v $ +// Revision 1.1.1.1 2003/04/19 08:40:17 johny +// no message +// +// Revision 1.1.1.1 2001/10/19 11:04:27 rudi +// WISHBONE CONMAX IP Core +// +// +// +// +// +// + + +task show_errors; + +begin + +$display("\n"); +$display(" +--------------------+"); +$display(" | Total ERRORS: %0d |", error_cnt); +$display(" +--------------------+"); + +end +endtask + + +task init_all_mem; + +begin + s0.fill_mem(1); + s1.fill_mem(1); + s2.fill_mem(1); + s3.fill_mem(1); + s4.fill_mem(1); + s5.fill_mem(1); + s6.fill_mem(1); + s7.fill_mem(1); + + + m0.mem_fill; + m1.mem_fill; + m2.mem_fill; + m3.mem_fill; + m4.mem_fill; + m5.mem_fill; + m6.mem_fill; + m7.mem_fill; + +end +endtask + + +task verify; +input master; +input slave; +input count; + +integer master, slave, count; +begin +verify_sub(master,slave,count,0,0); +end +endtask + + +task verify_sub; +input master; +input slave; +input count; +input mo; +input so; + +integer master, slave, count; +integer mo, so; +integer o; +integer n; +reg [31:0] mdata, sdata; + +begin + +//$display("V2: %0d %0d %0d %0d %0d",master, slave, count, mo,so); + +for(n=0;n60M , and 374 SLICE if using Multiplexor bus +// or 150 SLICE if using tri-state bus. +// +`include "wb_conbus_defines.v" +//`define WB_USE_TRISTATE + + +module wb_conbus_top( + clk_i, rst_i, + + // Master 0 Interface + m0_dat_i, m0_dat_o, m0_adr_i, m0_sel_i, m0_we_i, m0_cyc_i, + m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, m0_cab_i, + + // Master 1 Interface + m1_dat_i, m1_dat_o, m1_adr_i, m1_sel_i, m1_we_i, m1_cyc_i, + m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, m1_cab_i, + + // Master 2 Interface + m2_dat_i, m2_dat_o, m2_adr_i, m2_sel_i, m2_we_i, m2_cyc_i, + m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, m2_cab_i, + + // Master 3 Interface + m3_dat_i, m3_dat_o, m3_adr_i, m3_sel_i, m3_we_i, m3_cyc_i, + m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, m3_cab_i, + + // Master 4 Interface + m4_dat_i, m4_dat_o, m4_adr_i, m4_sel_i, m4_we_i, m4_cyc_i, + m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, m4_cab_i, + + // Master 5 Interface + m5_dat_i, m5_dat_o, m5_adr_i, m5_sel_i, m5_we_i, m5_cyc_i, + m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, m5_cab_i, + + // Master 6 Interface + m6_dat_i, m6_dat_o, m6_adr_i, m6_sel_i, m6_we_i, m6_cyc_i, + m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, m6_cab_i, + + // Master 7 Interface + m7_dat_i, m7_dat_o, m7_adr_i, m7_sel_i, m7_we_i, m7_cyc_i, + m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o, m7_cab_i, + + // Slave 0 Interface + s0_dat_i, s0_dat_o, s0_adr_o, s0_sel_o, s0_we_o, s0_cyc_o, + s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, s0_cab_o, + + // Slave 1 Interface + s1_dat_i, s1_dat_o, s1_adr_o, s1_sel_o, s1_we_o, s1_cyc_o, + s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, s1_cab_o, + + // Slave 2 Interface + s2_dat_i, s2_dat_o, s2_adr_o, s2_sel_o, s2_we_o, s2_cyc_o, + s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, s2_cab_o, + + // Slave 3 Interface + s3_dat_i, s3_dat_o, s3_adr_o, s3_sel_o, s3_we_o, s3_cyc_o, + s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, s3_cab_o, + + // Slave 4 Interface + s4_dat_i, s4_dat_o, s4_adr_o, s4_sel_o, s4_we_o, s4_cyc_o, + s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, s4_cab_o, + + // Slave 5 Interface + s5_dat_i, s5_dat_o, s5_adr_o, s5_sel_o, s5_we_o, s5_cyc_o, + s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, s5_cab_o, + + // Slave 6 Interface + s6_dat_i, s6_dat_o, s6_adr_o, s6_sel_o, s6_we_o, s6_cyc_o, + s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, s6_cab_o, + + // Slave 7 Interface + s7_dat_i, s7_dat_o, s7_adr_o, s7_sel_o, s7_we_o, s7_cyc_o, + s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, s7_cab_o + + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + + +parameter s0_addr_w = 4 ; // slave 0 address decode width +parameter s0_addr = 4'h0; // slave 0 address +parameter s1_addr_w = 4 ; // slave 1 address decode width +parameter s1_addr = 4'h1; // slave 1 address +parameter s27_addr_w = 8 ; // slave 2 to slave 7 address decode width +parameter s2_addr = 8'h92; // slave 2 address +parameter s3_addr = 8'h93; // slave 3 address +parameter s4_addr = 8'h94; // slave 4 address +parameter s5_addr = 8'h95; // slave 5 address +parameter s6_addr = 8'h96; // slave 6 address +parameter s7_addr = 8'h97; // slave 7 address + + parameter dw = 32; // Data bus Width + parameter aw = 32; // Address bus Width + parameter sw = dw / 8; // Number of Select Lines + parameter mbusw = aw + sw + dw + 4; //address width + byte select width + dat width + cyc + we + stb +cab , input from master interface + parameter sbusw = 3; // ack + err + rty, input from slave interface + parameter mselectw = 8; // number of masters + parameter sselectw = 8; // number of slavers + + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; + +// Master 0 Interface +input [dw-1:0] m0_dat_i; +output [dw-1:0] m0_dat_o; +input [aw-1:0] m0_adr_i; +input [sw-1:0] m0_sel_i; +input m0_we_i; +input m0_cyc_i; +input m0_stb_i; +input m0_cab_i; +output m0_ack_o; +output m0_err_o; +output m0_rty_o; + +// Master 1 Interface +input [dw-1:0] m1_dat_i; +output [dw-1:0] m1_dat_o; +input [aw-1:0] m1_adr_i; +input [sw-1:0] m1_sel_i; +input m1_we_i; +input m1_cyc_i; +input m1_stb_i; +input m1_cab_i; +output m1_ack_o; +output m1_err_o; +output m1_rty_o; + +// Master 2 Interface +input [dw-1:0] m2_dat_i; +output [dw-1:0] m2_dat_o; +input [aw-1:0] m2_adr_i; +input [sw-1:0] m2_sel_i; +input m2_we_i; +input m2_cyc_i; +input m2_stb_i; +input m2_cab_i; +output m2_ack_o; +output m2_err_o; +output m2_rty_o; + +// Master 3 Interface +input [dw-1:0] m3_dat_i; +output [dw-1:0] m3_dat_o; +input [aw-1:0] m3_adr_i; +input [sw-1:0] m3_sel_i; +input m3_we_i; +input m3_cyc_i; +input m3_stb_i; +input m3_cab_i; +output m3_ack_o; +output m3_err_o; +output m3_rty_o; + +// Master 4 Interface +input [dw-1:0] m4_dat_i; +output [dw-1:0] m4_dat_o; +input [aw-1:0] m4_adr_i; +input [sw-1:0] m4_sel_i; +input m4_we_i; +input m4_cyc_i; +input m4_stb_i; +input m4_cab_i; +output m4_ack_o; +output m4_err_o; +output m4_rty_o; + +// Master 5 Interface +input [dw-1:0] m5_dat_i; +output [dw-1:0] m5_dat_o; +input [aw-1:0] m5_adr_i; +input [sw-1:0] m5_sel_i; +input m5_we_i; +input m5_cyc_i; +input m5_stb_i; +input m5_cab_i; +output m5_ack_o; +output m5_err_o; +output m5_rty_o; + +// Master 6 Interface +input [dw-1:0] m6_dat_i; +output [dw-1:0] m6_dat_o; +input [aw-1:0] m6_adr_i; +input [sw-1:0] m6_sel_i; +input m6_we_i; +input m6_cyc_i; +input m6_stb_i; +input m6_cab_i; +output m6_ack_o; +output m6_err_o; +output m6_rty_o; + +// Master 7 Interface +input [dw-1:0] m7_dat_i; +output [dw-1:0] m7_dat_o; +input [aw-1:0] m7_adr_i; +input [sw-1:0] m7_sel_i; +input m7_we_i; +input m7_cyc_i; +input m7_stb_i; +input m7_cab_i; +output m7_ack_o; +output m7_err_o; +output m7_rty_o; + +// Slave 0 Interface +input [dw-1:0] s0_dat_i; +output [dw-1:0] s0_dat_o; +output [aw-1:0] s0_adr_o; +output [sw-1:0] s0_sel_o; +output s0_we_o; +output s0_cyc_o; +output s0_stb_o; +output s0_cab_o; +input s0_ack_i; +input s0_err_i; +input s0_rty_i; + +// Slave 1 Interface +input [dw-1:0] s1_dat_i; +output [dw-1:0] s1_dat_o; +output [aw-1:0] s1_adr_o; +output [sw-1:0] s1_sel_o; +output s1_we_o; +output s1_cyc_o; +output s1_stb_o; +output s1_cab_o; +input s1_ack_i; +input s1_err_i; +input s1_rty_i; + +// Slave 2 Interface +input [dw-1:0] s2_dat_i; +output [dw-1:0] s2_dat_o; +output [aw-1:0] s2_adr_o; +output [sw-1:0] s2_sel_o; +output s2_we_o; +output s2_cyc_o; +output s2_stb_o; +output s2_cab_o; +input s2_ack_i; +input s2_err_i; +input s2_rty_i; + +// Slave 3 Interface +input [dw-1:0] s3_dat_i; +output [dw-1:0] s3_dat_o; +output [aw-1:0] s3_adr_o; +output [sw-1:0] s3_sel_o; +output s3_we_o; +output s3_cyc_o; +output s3_stb_o; +output s3_cab_o; +input s3_ack_i; +input s3_err_i; +input s3_rty_i; + +// Slave 4 Interface +input [dw-1:0] s4_dat_i; +output [dw-1:0] s4_dat_o; +output [aw-1:0] s4_adr_o; +output [sw-1:0] s4_sel_o; +output s4_we_o; +output s4_cyc_o; +output s4_stb_o; +output s4_cab_o; +input s4_ack_i; +input s4_err_i; +input s4_rty_i; + +// Slave 5 Interface +input [dw-1:0] s5_dat_i; +output [dw-1:0] s5_dat_o; +output [aw-1:0] s5_adr_o; +output [sw-1:0] s5_sel_o; +output s5_we_o; +output s5_cyc_o; +output s5_stb_o; +output s5_cab_o; +input s5_ack_i; +input s5_err_i; +input s5_rty_i; + +// Slave 6 Interface +input [dw-1:0] s6_dat_i; +output [dw-1:0] s6_dat_o; +output [aw-1:0] s6_adr_o; +output [sw-1:0] s6_sel_o; +output s6_we_o; +output s6_cyc_o; +output s6_stb_o; +output s6_cab_o; +input s6_ack_i; +input s6_err_i; +input s6_rty_i; + +// Slave 7 Interface +input [dw-1:0] s7_dat_i; +output [dw-1:0] s7_dat_o; +output [aw-1:0] s7_adr_o; +output [sw-1:0] s7_sel_o; +output s7_we_o; +output s7_cyc_o; +output s7_stb_o; +output s7_cab_o; +input s7_ack_i; +input s7_err_i; +input s7_rty_i; + + +//////////////////////////////////////////////////////////////////// +// +// Local wires +// + +wire [mselectw -1:0] i_gnt_arb; +wire [2:0] gnt; +reg [sselectw -1:0] i_ssel_dec; +`ifdef WB_USE_TRISTATE +wire [mbusw -1:0] i_bus_m; +`else +reg [mbusw -1:0] i_bus_m; // internal share bus, master data and control to slave +`endif +wire [dw -1:0] i_dat_s; // internal share bus , slave data to master +wire [sbusw -1:0] i_bus_s; // internal share bus , slave control to master + + + +//////////////////////////////////////////////////////////////////// +// +// Master output Interfaces +// + +// master0 +assign m0_dat_o = i_dat_s; +assign {m0_ack_o, m0_err_o, m0_rty_o} = i_bus_s & {3{i_gnt_arb[0]}}; + +// master1 +assign m1_dat_o = i_dat_s; +assign {m1_ack_o, m1_err_o, m1_rty_o} = i_bus_s & {3{i_gnt_arb[1]}}; + +// master2 + +assign m2_dat_o = i_dat_s; +assign {m2_ack_o, m2_err_o, m2_rty_o} = i_bus_s & {3{i_gnt_arb[2]}}; + +// master3 + +assign m3_dat_o = i_dat_s; +assign {m3_ack_o, m3_err_o, m3_rty_o} = i_bus_s & {3{i_gnt_arb[3]}}; + +// master4 + +assign m4_dat_o = i_dat_s; +assign {m4_ack_o, m4_err_o, m4_rty_o} = i_bus_s & {3{i_gnt_arb[4]}}; + +// master5 + +assign m5_dat_o = i_dat_s; +assign {m5_ack_o, m5_err_o, m5_rty_o} = i_bus_s & {3{i_gnt_arb[5]}}; + +// master6 + +assign m6_dat_o = i_dat_s; +assign {m6_ack_o, m6_err_o, m6_rty_o} = i_bus_s & {3{i_gnt_arb[6]}}; + +// master7 + +assign m7_dat_o = i_dat_s; +assign {m7_ack_o, m7_err_o, m7_rty_o} = i_bus_s & {3{i_gnt_arb[7]}}; + + +assign i_bus_s = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i , + s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i , + s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i }; + +//////////////////////////////// +// Slave output interface +// +// slave0 +assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cab_o,s0_cyc_o} = i_bus_m[mbusw -1:1]; +assign s0_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[0]; // stb_o = cyc_i & stb_i & i_ssel_dec + +// slave1 + +assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cab_o, s1_cyc_o} = i_bus_m[mbusw -1:1]; +assign s1_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[1]; + +// slave2 + +assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cab_o, s2_cyc_o} = i_bus_m[mbusw -1:1]; +assign s2_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[2]; + +// slave3 + +assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cab_o, s3_cyc_o} = i_bus_m[mbusw -1:1]; +assign s3_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[3]; + +// slave4 + +assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cab_o, s4_cyc_o} = i_bus_m[mbusw -1:1]; +assign s4_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[4]; + +// slave5 + +assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cab_o, s5_cyc_o} = i_bus_m[mbusw -1:1]; +assign s5_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[5]; + +// slave6 + +assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cab_o, s6_cyc_o} = i_bus_m[mbusw -1:1]; +assign s6_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[6]; + +// slave7 + +assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cab_o, s7_cyc_o} = i_bus_m[mbusw -1:1]; +assign s7_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[7]; + +/////////////////////////////////////// +// Master and Slave input interface +// + +`ifdef WB_USE_TRISTATE +// input from master interface +assign i_bus_m = i_gnt_arb[0] ? {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i, m0_stb_i} : 72'bz ; +assign i_bus_m = i_gnt_arb[1] ? {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i,m1_cyc_i, m1_stb_i} : 72'bz ; +assign i_bus_m = i_gnt_arb[2] ? {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i, m2_stb_i} : 72'bz ; +assign i_bus_m = i_gnt_arb[3] ? {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i, m3_stb_i} : 72'bz ; +assign i_bus_m = i_gnt_arb[4] ? {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i, m4_stb_i} : 72'bz ; +assign i_bus_m = i_gnt_arb[5] ? {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i, m5_stb_i} : 72'bz ; +assign i_bus_m = i_gnt_arb[6] ? {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i, m6_stb_i} : 72'bz ; +assign i_bus_m = i_gnt_arb[7] ? {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i} : 72'bz ; +// input from slave interface +assign i_dat_s = i_ssel_dec[0] ? s0_dat_i: 32'bz; +assign i_dat_s = i_ssel_dec[1] ? s1_dat_i: 32'bz; +assign i_dat_s = i_ssel_dec[2] ? s2_dat_i: 32'bz; +assign i_dat_s = i_ssel_dec[3] ? s3_dat_i: 32'bz; +assign i_dat_s = i_ssel_dec[4] ? s4_dat_i: 32'bz; +assign i_dat_s = i_ssel_dec[5] ? s5_dat_i: 32'bz; +assign i_dat_s = i_ssel_dec[6] ? s6_dat_i: 32'bz; +assign i_dat_s = i_ssel_dec[7] ? s7_dat_i: 32'bz; + +`else + +always @(gnt , m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i, + m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i, + m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i, + m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i, + m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i, + m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i, + m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i, + m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i) + case(gnt) + 3'h0: i_bus_m = {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i}; + 3'h1: i_bus_m = {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i}; + 3'h2: i_bus_m = {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i}; + 3'h3: i_bus_m = {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i}; + 3'h4: i_bus_m = {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i}; + 3'h5: i_bus_m = {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i}; + 3'h6: i_bus_m = {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i}; + 3'h7: i_bus_m = {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i}; + default:i_bus_m = 72'b0;//{m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i}; +endcase + +assign i_dat_s = i_ssel_dec[0] ? s0_dat_i : + i_ssel_dec[1] ? s1_dat_i : + i_ssel_dec[2] ? s2_dat_i : + i_ssel_dec[3] ? s3_dat_i : + i_ssel_dec[4] ? s4_dat_i : + i_ssel_dec[5] ? s5_dat_i : + i_ssel_dec[6] ? s6_dat_i : + i_ssel_dec[7] ? s7_dat_i : {dw{1'b0}}; +`endif +// +// arbitor +// +assign i_gnt_arb[0] = (gnt == 3'd0); +assign i_gnt_arb[1] = (gnt == 3'd1); +assign i_gnt_arb[2] = (gnt == 3'd2); +assign i_gnt_arb[3] = (gnt == 3'd3); +assign i_gnt_arb[4] = (gnt == 3'd4); +assign i_gnt_arb[5] = (gnt == 3'd5); +assign i_gnt_arb[6] = (gnt == 3'd6); +assign i_gnt_arb[7] = (gnt == 3'd7); + +wb_conbus_arb wb_conbus_arb( + .clk(clk_i), + .rst(rst_i), + .req({ m7_cyc_i, + m6_cyc_i, + m5_cyc_i, + m4_cyc_i, + m3_cyc_i, + m2_cyc_i, + m1_cyc_i, + m0_cyc_i}), + .gnt(gnt) +); + +////////////////////////////////// +// address decode logic +// +wire [7:0] m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec; +always @(gnt, m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec) + case(gnt) + 3'h0: i_ssel_dec = m0_ssel_dec; + 3'h1: i_ssel_dec = m1_ssel_dec; + 3'h2: i_ssel_dec = m2_ssel_dec; + 3'h3: i_ssel_dec = m3_ssel_dec; + 3'h4: i_ssel_dec = m4_ssel_dec; + 3'h5: i_ssel_dec = m5_ssel_dec; + 3'h6: i_ssel_dec = m6_ssel_dec; + 3'h7: i_ssel_dec = m7_ssel_dec; + default: i_ssel_dec = 7'b0; +endcase +// +// decode all master address before arbitor for running faster +// +assign m0_ssel_dec[0] = (m0_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); +assign m0_ssel_dec[1] = (m0_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); +assign m0_ssel_dec[2] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr); +assign m0_ssel_dec[3] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr); +assign m0_ssel_dec[4] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr); +assign m0_ssel_dec[5] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr); +assign m0_ssel_dec[6] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr); +assign m0_ssel_dec[7] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr); + +assign m1_ssel_dec[0] = (m1_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); +assign m1_ssel_dec[1] = (m1_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); +assign m1_ssel_dec[2] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr); +assign m1_ssel_dec[3] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr); +assign m1_ssel_dec[4] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr); +assign m1_ssel_dec[5] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr); +assign m1_ssel_dec[6] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr); +assign m1_ssel_dec[7] = (m1_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr); + +assign m2_ssel_dec[0] = (m2_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); +assign m2_ssel_dec[1] = (m2_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); +assign m2_ssel_dec[2] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr); +assign m2_ssel_dec[3] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr); +assign m2_ssel_dec[4] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr); +assign m2_ssel_dec[5] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr); +assign m2_ssel_dec[6] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr); +assign m2_ssel_dec[7] = (m2_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr); + +assign m3_ssel_dec[0] = (m3_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); +assign m3_ssel_dec[1] = (m3_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); +assign m3_ssel_dec[2] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr); +assign m3_ssel_dec[3] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr); +assign m3_ssel_dec[4] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr); +assign m3_ssel_dec[5] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr); +assign m3_ssel_dec[6] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr); +assign m3_ssel_dec[7] = (m3_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr); + +assign m4_ssel_dec[0] = (m4_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); +assign m4_ssel_dec[1] = (m4_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); +assign m4_ssel_dec[2] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr); +assign m4_ssel_dec[3] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr); +assign m4_ssel_dec[4] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr); +assign m4_ssel_dec[5] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr); +assign m4_ssel_dec[6] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr); +assign m4_ssel_dec[7] = (m4_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr); + +assign m5_ssel_dec[0] = (m5_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); +assign m5_ssel_dec[1] = (m5_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); +assign m5_ssel_dec[2] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr); +assign m5_ssel_dec[3] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr); +assign m5_ssel_dec[4] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr); +assign m5_ssel_dec[5] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr); +assign m5_ssel_dec[6] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr); +assign m5_ssel_dec[7] = (m5_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr); + +assign m6_ssel_dec[0] = (m6_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); +assign m6_ssel_dec[1] = (m6_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); +assign m6_ssel_dec[2] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr); +assign m6_ssel_dec[3] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr); +assign m6_ssel_dec[4] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr); +assign m6_ssel_dec[5] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr); +assign m6_ssel_dec[6] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr); +assign m6_ssel_dec[7] = (m6_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr); + +assign m7_ssel_dec[0] = (m7_adr_i[aw -1 : aw - s0_addr_w ] == s0_addr); +assign m7_ssel_dec[1] = (m7_adr_i[aw -1 : aw - s1_addr_w ] == s1_addr); +assign m7_ssel_dec[2] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s2_addr); +assign m7_ssel_dec[3] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s3_addr); +assign m7_ssel_dec[4] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s4_addr); +assign m7_ssel_dec[5] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s5_addr); +assign m7_ssel_dec[6] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s6_addr); +assign m7_ssel_dec[7] = (m7_adr_i[aw -1 : aw - s27_addr_w ] == s7_addr); + +//assign i_ssel_dec[0] = (i_bus_m[mbusw -1 : mbusw - s0_addr_w ] == s0_addr); +//assign i_ssel_dec[1] = (i_bus_m[mbusw -1 : mbusw - s1_addr_w ] == s1_addr); +//assign i_ssel_dec[2] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s2_addr); +//assign i_ssel_dec[3] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s3_addr); +//assign i_ssel_dec[4] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s4_addr); +//assign i_ssel_dec[5] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s5_addr); +//assign i_ssel_dec[6] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s6_addr); +//assign i_ssel_dec[7] = (i_bus_m[mbusw -1 : mbusw - s27_addr_w ] == s7_addr); + + +endmodule + diff --git a/usrp2/fpga/sdr_lib/HB.sav b/usrp2/fpga/sdr_lib/HB.sav new file mode 100644 index 00000000..c5087e8a --- /dev/null +++ b/usrp2/fpga/sdr_lib/HB.sav @@ -0,0 +1,56 @@ +[size] 1400 967 +[pos] -1 -1 +*-46.395245 2565000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] hb_dec_tb. +@420 +hb_dec_tb.data_in[17:0] +@28 +hb_dec_tb.strobe_in +hb_dec_tb.strobe_out +hb_dec_tb.uut.write_even +@22 +hb_dec_tb.uut.addr_even[3:0] +@420 +hb_dec_tb.uut.data_even[17:0] +hb_dec_tb.uut.data_odd_a[17:0] +hb_dec_tb.uut.data_odd_b[17:0] +hb_dec_tb.uut.data_odd_c[17:0] +hb_dec_tb.uut.data_odd_d[17:0] +@28 +hb_dec_tb.uut.write_odd +@420 +hb_dec_tb.uut.prod1[35:0] +hb_dec_tb.uut.prod2[35:0] +@24 +hb_dec_tb.uut.phase[2:0] +@28 +hb_dec_tb.uut.stb_in +hb_dec_tb.uut.stb_out +@420 +hb_dec_tb.uut.sum2[17:0] +hb_dec_tb.uut.stb_out_pre[15:0] +@28 +hb_dec_tb.uut.do_acc +hb_dec_tb.uut.clear +@420 +hb_dec_tb.uut.sum1[17:0] +hb_dec_tb.uut.coeff1[17:0] +hb_dec_tb.uut.prod1[35:0] +hb_dec_tb.uut.prod2[35:0] +hb_dec_tb.uut.final_sum[17:0] +hb_dec_tb.uut.coeff2[17:0] +hb_dec_tb.uut.sum_of_prod[21:0] +hb_dec_tb.data_out[17:0] +@28 +hb_dec_tb.uut.do_acc +hb_dec_tb.uut.clear +@24 +hb_dec_tb.uut.addr_odd_a[3:0] +hb_dec_tb.uut.addr_odd_b[3:0] +hb_dec_tb.uut.addr_odd_c[3:0] +hb_dec_tb.uut.addr_odd_d[3:0] +@28 +hb_dec_tb.uut.write_odd +hb_dec_tb.uut.write_even +@22 +hb_dec_tb.uut.data_even[17:0] diff --git a/usrp2/fpga/sdr_lib/SMALL_HB.sav b/usrp2/fpga/sdr_lib/SMALL_HB.sav new file mode 100644 index 00000000..96ba0063 --- /dev/null +++ b/usrp2/fpga/sdr_lib/SMALL_HB.sav @@ -0,0 +1,40 @@ +[size] 1400 967 +[pos] -1 -1 +*-11.608687 1834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] small_hb_dec_tb. +[treeopen] small_hb_dec_tb.uut. +@28 +small_hb_dec_tb.uut.clk +small_hb_dec_tb.uut.phase +@10421 +small_hb_dec_tb.uut.data_in[17:0] +@420 +small_hb_dec_tb.uut.d1[17:0] +small_hb_dec_tb.uut.d2[17:0] +small_hb_dec_tb.uut.d3[17:0] +small_hb_dec_tb.uut.d4[17:0] +small_hb_dec_tb.uut.d5[17:0] +small_hb_dec_tb.uut.d6[17:0] +small_hb_dec_tb.uut.coeff[17:0] +small_hb_dec_tb.uut.sum[17:0] +small_hb_dec_tb.uut.prod[35:0] +small_hb_dec_tb.uut.accum_rnd[17:0] +@28 +small_hb_dec_tb.uut.stb_in +@420 +small_hb_dec_tb.uut.final_sum[17:0] +@28 +small_hb_dec_tb.uut.go +small_hb_dec_tb.uut.go_d1 +small_hb_dec_tb.uut.go_d2 +small_hb_dec_tb.uut.go_d3 +small_hb_dec_tb.uut.go_d4 +small_hb_dec_tb.uut.stb_out +@420 +small_hb_dec_tb.uut.data_out[17:0] +small_hb_dec_tb.uut.prod[35:0] +small_hb_dec_tb.uut.accum_rnd[17:0] +small_hb_dec_tb.uut.final_sum[17:0] +@10421 +small_hb_dec_tb.uut.round_acc.out[17:0] +small_hb_dec_tb.uut.data_out[17:0] diff --git a/usrp2/fpga/sdr_lib/acc.v b/usrp2/fpga/sdr_lib/acc.v new file mode 100644 index 00000000..a2da9c86 --- /dev/null +++ b/usrp2/fpga/sdr_lib/acc.v @@ -0,0 +1,28 @@ + +module acc + #(parameter IWIDTH=16, OWIDTH=30) + (input clk, + input clear, + input acc, + input [IWIDTH-1:0] in, + output reg [OWIDTH-1:0] out); + + wire [OWIDTH-1:0] in_signext; + sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) + acc_signext (.in(in),.out(in_signext)); + + // CLEAR & ~ACC --> clears the accumulator + // CLEAR & ACC --> loads the accumulator + // ~CLEAR & ACC --> accumulates + // ~CLEAR & ~ACC --> hold + + wire [OWIDTH-1:0] addend1 = clear ? 0 : out; + wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext; + wire [OWIDTH-1:0] sum_int = addend1 + addend2; + + always @(posedge clk) + out <= sum_int; + +endmodule // acc + + diff --git a/usrp2/fpga/sdr_lib/add2.v b/usrp2/fpga/sdr_lib/add2.v new file mode 100644 index 00000000..13fff803 --- /dev/null +++ b/usrp2/fpga/sdr_lib/add2.v @@ -0,0 +1,11 @@ + +module add2 + #(parameter WIDTH=16) + (input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output [WIDTH-1:0] sum); + + wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; + assign sum = sum_int[WIDTH:1]; // Note -- will have some bias + +endmodule // add2 diff --git a/usrp2/fpga/sdr_lib/add2_and_round.v b/usrp2/fpga/sdr_lib/add2_and_round.v new file mode 100644 index 00000000..146af28d --- /dev/null +++ b/usrp2/fpga/sdr_lib/add2_and_round.v @@ -0,0 +1,11 @@ + +module add2_and_round + #(parameter WIDTH=16) + (input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output [WIDTH-1:0] sum); + + wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; + assign sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]); + +endmodule // add2_and_round diff --git a/usrp2/fpga/sdr_lib/add2_and_round_reg.v b/usrp2/fpga/sdr_lib/add2_and_round_reg.v new file mode 100644 index 00000000..e7fcbf1a --- /dev/null +++ b/usrp2/fpga/sdr_lib/add2_and_round_reg.v @@ -0,0 +1,16 @@ + +module add2_and_round_reg + #(parameter WIDTH=16) + (input clk, + input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output reg [WIDTH-1:0] sum); + + wire [WIDTH-1:0] sum_int; + + add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int)); + + always @(posedge clk) + sum <= sum_int; + +endmodule // add2_and_round_reg diff --git a/usrp2/fpga/sdr_lib/add2_reg.v b/usrp2/fpga/sdr_lib/add2_reg.v new file mode 100644 index 00000000..456cf315 --- /dev/null +++ b/usrp2/fpga/sdr_lib/add2_reg.v @@ -0,0 +1,17 @@ + +module add2_reg + #(parameter WIDTH=16) + (input clk, + input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output reg [WIDTH-1:0] sum); + + wire [WIDTH-1:0] sum_int; + + add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int)); + + always @(posedge clk) + sum <= sum_int; + +endmodule // add2_reg + diff --git a/usrp2/fpga/sdr_lib/cic_dec_shifter.v b/usrp2/fpga/sdr_lib/cic_dec_shifter.v new file mode 100644 index 00000000..aa5ac895 --- /dev/null +++ b/usrp2/fpga/sdr_lib/cic_dec_shifter.v @@ -0,0 +1,106 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +// NOTE This only works for N=4, max decim rate of 128 +// NOTE signal "rate" is EQUAL TO the actual rate, no more -1 BS + +module cic_dec_shifter(rate,signal_in,signal_out); + parameter bw = 16; + parameter maxbitgain = 28; + + input [7:0] rate; + input wire [bw+maxbitgain-1:0] signal_in; + output reg [bw-1:0] signal_out; + + function [4:0] bitgain; + input [7:0] rate; + case(rate) + // Exact Cases -- N*log2(rate) + 8'd1 : bitgain = 0; + 8'd2 : bitgain = 4; + 8'd4 : bitgain = 8; + 8'd8 : bitgain = 12; + 8'd16 : bitgain = 16; + 8'd32 : bitgain = 20; + 8'd64 : bitgain = 24; + 8'd128 : bitgain = 28; + + // Nearest without overflow -- ceil(N*log2(rate)) + 8'd3 : bitgain = 7; + 8'd5 : bitgain = 10; + 8'd6 : bitgain = 11; + 8'd7 : bitgain = 12; + 8'd9 : bitgain = 13; + 8'd10,8'd11 : bitgain = 14; + 8'd12,8'd13 : bitgain = 15; + 8'd14,8'd15 : bitgain = 16; + 8'd17,8'd18,8'd19 : bitgain = 17; + 8'd20,8'd21,8'd22 : bitgain = 18; + 8'd23,8'd24,8'd25,8'd26 : bitgain = 19; + 8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20; + 8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21; + 8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22; + 8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23; + 8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24; + 8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25; + 8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26; + 8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27; + default : bitgain = 28; + endcase // case(rate) + endfunction // bitgain + + wire [4:0] shift = bitgain(rate); + + // We should be able to do this, but can't .... + // assign signal_out = signal_in[shift+bw-1:shift]; + + always @* + case(shift) + 5'd0 : signal_out = signal_in[0+bw-1:0]; + 5'd4 : signal_out = signal_in[4+bw-1:4]; + 5'd7 : signal_out = signal_in[7+bw-1:7]; + 5'd8 : signal_out = signal_in[8+bw-1:8]; + 5'd10 : signal_out = signal_in[10+bw-1:10]; + 5'd11 : signal_out = signal_in[11+bw-1:11]; + 5'd12 : signal_out = signal_in[12+bw-1:12]; + 5'd13 : signal_out = signal_in[13+bw-1:13]; + 5'd14 : signal_out = signal_in[14+bw-1:14]; + 5'd15 : signal_out = signal_in[15+bw-1:15]; + 5'd16 : signal_out = signal_in[16+bw-1:16]; + 5'd17 : signal_out = signal_in[17+bw-1:17]; + 5'd18 : signal_out = signal_in[18+bw-1:18]; + 5'd19 : signal_out = signal_in[19+bw-1:19]; + 5'd20 : signal_out = signal_in[20+bw-1:20]; + 5'd21 : signal_out = signal_in[21+bw-1:21]; + 5'd22 : signal_out = signal_in[22+bw-1:22]; + 5'd23 : signal_out = signal_in[23+bw-1:23]; + 5'd24 : signal_out = signal_in[24+bw-1:24]; + 5'd25 : signal_out = signal_in[25+bw-1:25]; + 5'd26 : signal_out = signal_in[26+bw-1:26]; + 5'd27 : signal_out = signal_in[27+bw-1:27]; + 5'd28 : signal_out = signal_in[28+bw-1:28]; + + default : signal_out = signal_in[28+bw-1:28]; + endcase // case(shift) + +endmodule // cic_dec_shifter + diff --git a/usrp2/fpga/sdr_lib/cic_decim.v b/usrp2/fpga/sdr_lib/cic_decim.v new file mode 100755 index 00000000..9a03081b --- /dev/null +++ b/usrp2/fpga/sdr_lib/cic_decim.v @@ -0,0 +1,88 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +module cic_decim + #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7) + (input clock, + input reset, + input enable, + input [7:0] rate, + input strobe_in, + input strobe_out, + input [bw-1:0] signal_in, + output reg [bw-1:0] signal_out); + + localparam maxbitgain = N * log2_of_max_rate; + + wire [bw+maxbitgain-1:0] signal_in_ext; + reg [bw+maxbitgain-1:0] integrator [0:N-1]; + reg [bw+maxbitgain-1:0] differentiator [0:N-1]; + reg [bw+maxbitgain-1:0] pipeline [0:N-1]; + reg [bw+maxbitgain-1:0] sampler; + + integer i; + + sign_extend #(bw,bw+maxbitgain) + ext_input (.in(signal_in),.out(signal_in_ext)); + + always @(posedge clock) + if(reset) + for(i=0;i 0 ; i = i - 1 ) begin + delay[i] = delay[i-1] ; + end + delay[0] = data_in ; + + // clear the temp reg + temp = 18'd0 ; + if( (decim && (count == rate-1)) || !decim ) begin + count <= 0 ; + for( i = 0 ; i < 31 ; i = i + 1 ) begin + // Multiply Accumulate + temp = temp + delay[i]*coeffs[i] ; + end + // Assign data output + data_out <= temp >>> 15 ; + end + end + end + end +endmodule diff --git a/usrp2/fpga/sdr_lib/halfband_tb.v b/usrp2/fpga/sdr_lib/halfband_tb.v new file mode 100644 index 00000000..231dd00d --- /dev/null +++ b/usrp2/fpga/sdr_lib/halfband_tb.v @@ -0,0 +1,120 @@ +module halfband_tb( ) ; + + // Parameters for instantiation + parameter clocks = 2 ; // Number of clocks per input + parameter decim = 0 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + reg strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #100 reset = 1'b0 ; + + // Enable the entire system + initial enable = 1'b1 ; + + // Instantiate UUT + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + + integer i, ri, ro, infile, outfile ; + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + strobe_in <= 1'd0 ; + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( posedge clock ) begin + #1 ; + strobe_in <= 1'b1 ; + if( !$feof(infile) ) + ri = $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + + // Clocked in - set the strobe to 0 if the number of + // clocks per sample is greater than 1 + if( clocks > 1 ) begin + @(posedge clock) begin + strobe_in <= 1'b0 ; + end + + // Wait for the specified number of cycles + for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin + @(posedge clock) #1 ; + end + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $stop ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + $display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + endofsim <= 1'b1 ; + end + end + end + +endmodule diff --git a/usrp2/fpga/sdr_lib/hb/acc.v b/usrp2/fpga/sdr_lib/hb/acc.v new file mode 100644 index 00000000..195d5ea9 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/acc.v @@ -0,0 +1,22 @@ + + +module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, + input signed [30:0] addend, output reg signed [33:0] sum ); + + always @(posedge clock) + if(reset) + sum <= #1 34'd0; + //else if(clear & enable_in) + // sum <= #1 addend; + //else if(clear) + // sum <= #1 34'd0; + else if(clear) + sum <= #1 addend; + else if(enable_in) + sum <= #1 sum + addend; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // acc + diff --git a/usrp2/fpga/sdr_lib/hb/coeff_ram.v b/usrp2/fpga/sdr_lib/hb/coeff_ram.v new file mode 100644 index 00000000..65460822 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/coeff_ram.v @@ -0,0 +1,26 @@ + + +module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data); + + always @(posedge clock) + case (rd_addr) + 4'd0 : rd_data <= #1 -16'd16; + 4'd1 : rd_data <= #1 16'd74; + 4'd2 : rd_data <= #1 -16'd254; + 4'd3 : rd_data <= #1 16'd669; + 4'd4 : rd_data <= #1 -16'd1468; + 4'd5 : rd_data <= #1 16'd2950; + 4'd6 : rd_data <= #1 -16'd6158; + 4'd7 : rd_data <= #1 16'd20585; + 4'd8 : rd_data <= #1 16'd20585; + 4'd9 : rd_data <= #1 -16'd6158; + 4'd10 : rd_data <= #1 16'd2950; + 4'd11 : rd_data <= #1 -16'd1468; + 4'd12 : rd_data <= #1 16'd669; + 4'd13 : rd_data <= #1 -16'd254; + 4'd14 : rd_data <= #1 16'd74; + 4'd15 : rd_data <= #1 -16'd16; + default : rd_data <= #1 16'd0; + endcase // case(rd_addr) + +endmodule // ram diff --git a/usrp2/fpga/sdr_lib/hb/coeff_rom.v b/usrp2/fpga/sdr_lib/hb/coeff_rom.v new file mode 100644 index 00000000..7f8886b4 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/coeff_rom.v @@ -0,0 +1,19 @@ + + +module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); + + always @(posedge clock) + case (addr) + 3'd0 : data <= #1 -16'd49; + 3'd1 : data <= #1 16'd165; + 3'd2 : data <= #1 -16'd412; + 3'd3 : data <= #1 16'd873; + 3'd4 : data <= #1 -16'd1681; + 3'd5 : data <= #1 16'd3135; + 3'd6 : data <= #1 -16'd6282; + 3'd7 : data <= #1 16'd20628; + endcase // case(addr) + +endmodule // coeff_rom + + diff --git a/usrp2/fpga/sdr_lib/hb/halfband_decim.v b/usrp2/fpga/sdr_lib/hb/halfband_decim.v new file mode 100644 index 00000000..dff4d902 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/halfband_decim.v @@ -0,0 +1,163 @@ +/* -*- verilog -*- + * + * USRP - Universal Software Radio Peripheral + * + * Copyright (C) 2005 Matt Ettus + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA + */ + +/* + * This implements a 31-tap halfband filter that decimates by two. + * The coefficients are symmetric, and with the exception of the middle tap, + * every other coefficient is zero. The middle section of taps looks like this: + * + * ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ... + * | + * middle tap -------+ + * + * See coeff_rom.v for the full set. The taps are scaled relative to 32768, + * thus the middle tap equals 1.0. Not counting the middle tap, there are 8 + * non-zero taps on each side, and they are symmetric. A naive implementation + * requires a mulitply for each non-zero tap. Because of symmetry, we can + * replace 2 multiplies with 1 add and 1 multiply. Thus, to compute each output + * sample, we need to perform 8 multiplications. Since the middle tap is 1.0, + * we just add the corresponding delay line value. + * + * About timing: We implement this with a single multiplier, so it takes + * 8 cycles to compute a single output. However, since we're decimating by two + * we can accept a new input value every 4 cycles. strobe_in is asserted when + * there's a new input sample available. Depending on the overall decimation + * rate, strobe_in may be asserted less frequently than once every 4 clocks. + * On the output side, we assert strobe_out when output contains a new sample. + * + * Implementation: Every time strobe_in is asserted we store the new data into + * the delay line. We split the delay line into two components, one for the + * even samples, and one for the odd samples. ram16_odd is the delay line for + * the odd samples. This ram is written on each odd assertion of strobe_in, and + * is read on each clock when we're computing the dot product. ram16_even is + * similar, although because it holds the even samples we must be able to read + * two samples from different addresses at the same time, while writing the incoming + * even samples. Thus it's "triple-ported". + */ + +module halfband_decim + (input clock, input reset, input enable, input strobe_in, output wire strobe_out, + input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl); + + reg [3:0] rd_addr1; + reg [3:0] rd_addr2; + reg [3:0] phase; + reg [3:0] base_addr; + + wire signed [15:0] mac_out,middle_data, sum, coeff; + wire signed [30:0] product; + wire signed [33:0] sum_even; + wire clear; + reg store_odd; + + always @(posedge clock) + if(reset) + store_odd <= #1 1'b0; + else + if(strobe_in) + store_odd <= #1 ~store_odd; + + wire start = strobe_in & store_odd; + always @(posedge clock) + if(reset) + base_addr <= #1 4'd0; + else if(start) + base_addr <= #1 base_addr + 4'd1; + + always @(posedge clock) + if(reset) + phase <= #1 4'd8; + else if (start) + phase <= #1 4'd0; + else if(phase != 4'd8) + phase <= #1 phase + 4'd1; + + reg start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD; + always @(posedge clock) + begin + start_d1 <= #1 start; + start_d2 <= #1 start_d1; + start_d3 <= #1 start_d2; + start_d4 <= #1 start_d3; + start_d5 <= #1 start_d4; + start_d6 <= #1 start_d5; + start_d7 <= #1 start_d6; + start_d8 <= #1 start_d7; + start_d9 <= #1 start_d8; + start_dA <= #1 start_d9; + start_dB <= #1 start_dA; + start_dC <= #1 start_dB; + start_dD <= #1 start_dC; + end // always @ (posedge clock) + + reg mult_en, mult_en_pre; + always @(posedge clock) + begin + mult_en_pre <= #1 phase!=8; + mult_en <= #1 mult_en_pre; + end + + assign clear = start_d4; // was dC + wire latch_result = start_d4; // was dC + assign strobe_out = start_d5; // was dD + wire acc_en; + + always @* + case(phase[2:0]) + 3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end + 3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end + 3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end + 3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end + 3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end + 3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end + 3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end + 3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end + default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end + endcase // case(phase) + + coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff)); + + ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd), + .wr_addr(base_addr),.wr_data(data_in), + .rd_addr1(rd_addr1),.rd_addr2(rd_addr2), + .sum(sum)); + + ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd), // Holds middle items + .wr_addr(base_addr),.wr_data(data_in), + //.rd_addr(base_addr+4'd7),.rd_data(middle_data)); + .rd_addr(base_addr+4'd6),.rd_data(middle_data)); + + mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en)); + + acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(), + .clear(clear),.addend(product),.sum(sum_even)); + + wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!! + + always @(posedge clock) + if(reset) + data_out <= #1 16'd0; + else if(latch_result) + data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]); + + assign debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase}; + +endmodule // halfband_decim diff --git a/usrp2/fpga/sdr_lib/hb/halfband_interp.v b/usrp2/fpga/sdr_lib/hb/halfband_interp.v new file mode 100644 index 00000000..cdb11c1f --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/halfband_interp.v @@ -0,0 +1,121 @@ + + +module halfband_interp + (input clock, input reset, input enable, + input strobe_in, input strobe_out, + input [15:0] signal_in_i, input [15:0] signal_in_q, + output reg [15:0] signal_out_i, output reg [15:0] signal_out_q, + output wire [12:0] debug); + + wire [15:0] coeff_ram_out; + wire [15:0] data_ram_out_i; + wire [15:0] data_ram_out_q; + + wire [3:0] data_rd_addr; + reg [3:0] data_wr_addr; + reg [2:0] coeff_rd_addr; + + wire filt_done; + + wire [15:0] mac_out_i; + wire [15:0] mac_out_q; + reg [15:0] delayed_middle_i, delayed_middle_q; + wire [7:0] shift = 8'd9; + + reg stb_out_happened; + + wire [15:0] data_ram_out_i_b; + + always @(posedge clock) + if(strobe_in) + stb_out_happened <= #1 1'b0; + else if(strobe_out) + stb_out_happened <= #1 1'b1; + +assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr}; + + wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i; + wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q; + +/* always @(posedge clock) + if(reset) + begin + signal_out_i <= #1 16'd0; + signal_out_q <= #1 16'd0; + end + else if(strobe_in) + begin + signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff + signal_out_q <= #1 delayed_middle_q; + end + //else if(filt_done&stb_out_happened) + else if(stb_out_happened) + begin + signal_out_i <= #1 mac_out_i; + signal_out_q <= #1 mac_out_q; + end +*/ + + always @(posedge clock) + if(reset) + coeff_rd_addr <= #1 3'd0; + else if(coeff_rd_addr != 3'd0) + coeff_rd_addr <= #1 coeff_rd_addr + 3'd1; + else if(strobe_in) + coeff_rd_addr <= #1 3'd1; + + reg filt_done_d1; + always@(posedge clock) + filt_done_d1 <= #1 filt_done; + + always @(posedge clock) + if(reset) + data_wr_addr <= #1 4'd0; + //else if(strobe_in) + else if(filt_done & ~filt_done_d1) + data_wr_addr <= #1 data_wr_addr + 4'd1; + + always @(posedge clock) + if(coeff_rd_addr == 3'd7) + begin + delayed_middle_i <= #1 data_ram_out_i_b; + // delayed_middle_q <= #1 data_ram_out_q_b; + end + +// always @(posedge clock) +// if(reset) +// data_rd_addr <= #1 4'd0; +// else if(strobe_in) +// data_rd_addr <= #1 data_wr_addr + 4'd1; +// else if(!filt_done) +// data_rd_addr <= #1 data_rd_addr + 4'd1; +// else +// data_rd_addr <= #1 data_wr_addr; + + wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr}; + wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr}; +// always @(posedge clock) +// if(reset) +// filt_done <= #1 1'b1; +// else if(strobe_in) + // filt_done <= #1 1'b0; +// else if(coeff_rd_addr == 4'd0) +// filt_done <= #1 1'b1; + + assign filt_done = (coeff_rd_addr == 3'd0); + + coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) ); + + ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i), + .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i)); + + ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q), + .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q)); + + mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), + .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) ); + + mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in), + .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) ); + +endmodule // halfband_interp diff --git a/usrp2/fpga/sdr_lib/hb/hbd_tb/HBD b/usrp2/fpga/sdr_lib/hb/hbd_tb/HBD new file mode 100644 index 00000000..574fbba9 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/hbd_tb/HBD @@ -0,0 +1,80 @@ +*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +test_hbd.clock +test_hbd.reset +@420 +test_hbd.halfband_decim.middle_data[15:0] +@22 +test_hbd.halfband_decim.sum_even[33:0] +test_hbd.halfband_decim.base_addr[3:0] +@420 +test_hbd.i_in[15:0] +@24 +test_hbd.halfband_decim.phase[3:0] +test_hbd.halfband_decim.ram16_even.rd_addr1[3:0] +test_hbd.halfband_decim.ram16_even.rd_addr2[3:0] +test_hbd.halfband_decim.ram16_even.wr_addr[3:0] +test_hbd.halfband_decim.ram16_even.wr_data[15:0] +@28 +test_hbd.halfband_decim.ram16_even.write +@420 +test_hbd.halfband_decim.sum[15:0] +test_hbd.halfband_decim.product[30:0] +test_hbd.halfband_decim.dout[33:0] +test_hbd.halfband_decim.sum_even[33:0] +@22 +test_hbd.halfband_decim.acc.addend[30:0] +@28 +test_hbd.halfband_decim.acc.reset +@420 +test_hbd.halfband_decim.acc.sum[33:0] +test_hbd.halfband_decim.mult.x[15:0] +test_hbd.halfband_decim.mult.y[15:0] +@28 +test_hbd.halfband_decim.acc.clear +test_hbd.strobe_in +test_hbd.strobe_out +test_hbd.halfband_decim.acc_en +@420 +test_hbd.i_out[15:0] +@28 +test_hbd.halfband_decim.mult_en +test_hbd.halfband_decim.latch_result +@420 +test_hbd.halfband_decim.sum[15:0] +test_hbd.halfband_decim.sum_even[33:0] +test_hbd.halfband_decim.dout[33:0] +test_hbd.halfband_decim.data_out[15:0] +@22 +test_hbd.halfband_decim.data_out[15:0] +@28 +test_hbd.halfband_decim.dout[33:0] +@29 +test_hbd.halfband_decim.acc_en +@22 +test_hbd.halfband_decim.base_addr[3:0] +@28 +test_hbd.halfband_decim.clear +test_hbd.halfband_decim.latch_result +test_hbd.halfband_decim.mult_en +test_hbd.halfband_decim.mult_en_pre +@22 +test_hbd.halfband_decim.phase[3:0] +@28 +test_hbd.halfband_decim.start +test_hbd.halfband_decim.start_d1 +test_hbd.halfband_decim.start_d2 +test_hbd.halfband_decim.start_d3 +test_hbd.halfband_decim.start_d4 +test_hbd.halfband_decim.start_d5 +test_hbd.halfband_decim.start_d6 +test_hbd.halfband_decim.start_d7 +test_hbd.halfband_decim.start_d8 +test_hbd.halfband_decim.start_d9 +test_hbd.halfband_decim.start_dA +test_hbd.halfband_decim.start_dB +test_hbd.halfband_decim.start_dC +test_hbd.halfband_decim.start_dD +test_hbd.halfband_decim.store_odd +test_hbd.halfband_decim.strobe_in +test_hbd.halfband_decim.strobe_out diff --git a/usrp2/fpga/sdr_lib/hb/hbd_tb/really_golden b/usrp2/fpga/sdr_lib/hb/hbd_tb/really_golden new file mode 100644 index 00000000..2d24a9e1 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/hbd_tb/really_golden @@ -0,0 +1,142 @@ +VCD info: dumpfile test_hbd.vcd opened for output. + x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8192 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 +- 4 + 18 +- 63 + 167 +- 367 + 737 +- 1539 + 5146 + 5146 +- 1539 + 737 +- 367 + 167 +- 63 + 18 +- 4 + 0 + 0 + 0 + 0 + 0 +- 4 + 14 +- 49 + 118 +- 249 + 488 + 7141 +12287 +17433 +15894 +16631 +16264 +16432 +16368 +16387 +16383 +16383 +16383 +16383 +16383 +16387 +16368 +16432 +16264 +16631 +15894 + 9241 + 4095 +- 1051 + 488 +- 249 + 118 +- 49 + 14 +- 4 + 0 + 0 + 0 + 0 + 0 +- 4 + 14 +- 49 + 118 +- 249 + 488 +- 1051 +12287 +17433 +15894 +16631 +16264 +16432 +16368 +16387 +16383 +16383 +16383 +16383 +16383 +16387 +16368 +16432 +16264 +16631 +15894 +17433 + 4095 +- 1051 + 488 +- 249 + 118 +- 49 + 14 +- 4 + 0 + 0 + 0 + 0 diff --git a/usrp2/fpga/sdr_lib/hb/hbd_tb/regression b/usrp2/fpga/sdr_lib/hb/hbd_tb/regression new file mode 100644 index 00000000..fc279c2f --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/hbd_tb/regression @@ -0,0 +1,95 @@ +echo "Baseline 1000" +iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v ; ./test_hbd >golden +diff golden really_golden + +echo +echo "Test 100" +iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 50" +iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 40" +iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 30" +iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 25" +iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 20" +iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 19" +iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 18" +iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 17" +iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 16" +iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 15" +iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 14" +iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 13" +iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 12" +iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 11" +iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 10" +iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 9" +iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 8" +iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 7" +iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 6" +iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 5" +iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 4" +iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v ; ./test_hbd >output ; diff output golden + +echo +echo "Test 3" +iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v ; ./test_hbd >output ; diff output golden diff --git a/usrp2/fpga/sdr_lib/hb/hbd_tb/run_hbd b/usrp2/fpga/sdr_lib/hb/hbd_tb/run_hbd new file mode 100755 index 00000000..b8aec757 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/hbd_tb/run_hbd @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog -y .. -o test_hbd test_hbd.v +./test_hbd diff --git a/usrp2/fpga/sdr_lib/hb/hbd_tb/test_hbd.v b/usrp2/fpga/sdr_lib/hb/hbd_tb/test_hbd.v new file mode 100644 index 00000000..01ab5e7e --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/hbd_tb/test_hbd.v @@ -0,0 +1,75 @@ + + +module test_hbd(); + + reg clock; + initial clock = 1'b0; + always #5 clock <= ~clock; + + reg reset; + initial reset = 1'b1; + initial #1000 reset = 1'b0; + + initial $dumpfile("test_hbd.vcd"); + initial $dumpvars(0,test_hbd); + + reg [15:0] i_in, q_in; + wire [15:0] i_out, q_out; + + reg strobe_in; + wire strobe_out; + reg coeff_write; + reg [15:0] coeff_data; + reg [4:0] coeff_addr; + + halfband_decim halfband_decim + ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out), + .data_in(i_in),.data_out(i_out) ); + + always @(posedge strobe_out) + if(i_out[15]) + $display("-%d",65536-i_out); + else + $display("%d",i_out); + + initial + begin + strobe_in = 1'b0; + @(negedge reset); + @(posedge clock); + while(1) + begin + strobe_in <= #1 1'b1; + @(posedge clock); + strobe_in <= #1 1'b0; + repeat (`RATE) + @(posedge clock); + end + end + + initial #10000000 $finish; // Just in case... + + initial + begin + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd16384; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (41) @(posedge strobe_in); + i_in <= #1 16'd16384; + repeat (40) @(posedge strobe_in); + i_in <= #1 16'd0; + repeat (40) @(posedge strobe_in); + repeat (7) @(posedge clock); + $finish; + end // initial begin +endmodule // test_hb diff --git a/usrp2/fpga/sdr_lib/hb/mac.v b/usrp2/fpga/sdr_lib/hb/mac.v new file mode 100644 index 00000000..5a270bc7 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/mac.v @@ -0,0 +1,58 @@ + + +module mac (input clock, input reset, input enable, input clear, + input signed [15:0] x, input signed [15:0] y, + input [7:0] shift, output [15:0] z ); + + reg signed [30:0] product; + reg signed [39:0] z_int; + reg signed [15:0] z_shift; + + reg enable_d1; + always @(posedge clock) + enable_d1 <= #1 enable; + + always @(posedge clock) + if(reset | clear) + z_int <= #1 40'd0; + else if(enable_d1) + z_int <= #1 z_int + {{9{product[30]}},product}; + + always @(posedge clock) + product <= #1 x*y; + + always @* // FIXME full case? parallel case? + case(shift) + //8'd0 : z_shift <= z_int[39:24]; + //8'd1 : z_shift <= z_int[38:23]; + //8'd2 : z_shift <= z_int[37:22]; + //8'd3 : z_shift <= z_int[36:21]; + //8'd4 : z_shift <= z_int[35:20]; + //8'd5 : z_shift <= z_int[34:19]; + 8'd6 : z_shift <= z_int[33:18]; + 8'd7 : z_shift <= z_int[32:17]; + 8'd8 : z_shift <= z_int[31:16]; + 8'd9 : z_shift <= z_int[30:15]; + 8'd10 : z_shift <= z_int[29:14]; + 8'd11 : z_shift <= z_int[28:13]; + //8'd12 : z_shift <= z_int[27:12]; + //8'd13 : z_shift <= z_int[26:11]; + //8'd14 : z_shift <= z_int[25:10]; + //8'd15 : z_shift <= z_int[24:9]; + //8'd16 : z_shift <= z_int[23:8]; + //8'd17 : z_shift <= z_int[22:7]; + //8'd18 : z_shift <= z_int[21:6]; + //8'd19 : z_shift <= z_int[20:5]; + //8'd20 : z_shift <= z_int[19:4]; + //8'd21 : z_shift <= z_int[18:3]; + //8'd22 : z_shift <= z_int[17:2]; + //8'd23 : z_shift <= z_int[16:1]; + //8'd24 : z_shift <= z_int[15:0]; + default : z_shift <= z_int[15:0]; + endcase // case(shift) + + // FIXME do we need to saturate? + //assign z = z_shift; + assign z = z_int[15:0]; + +endmodule // mac diff --git a/usrp2/fpga/sdr_lib/hb/mult.v b/usrp2/fpga/sdr_lib/hb/mult.v new file mode 100644 index 00000000..a8d4cb1b --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/mult.v @@ -0,0 +1,16 @@ + + +module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, + input enable_in, output reg enable_out ); + + always @(posedge clock) + if(enable_in) + product <= #1 x*y; + else + product <= #1 31'd0; + + always @(posedge clock) + enable_out <= #1 enable_in; + +endmodule // mult + diff --git a/usrp2/fpga/sdr_lib/hb/ram16_2port.v b/usrp2/fpga/sdr_lib/hb/ram16_2port.v new file mode 100644 index 00000000..e1761a92 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/ram16_2port.v @@ -0,0 +1,22 @@ + + +module ram16_2port (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr1, output reg [15:0] rd_data1, + input [3:0] rd_addr2, output reg [15:0] rd_data2); + + reg [15:0] ram_array [0:31]; + + always @(posedge clock) + rd_data1 <= #1 ram_array[rd_addr1]; + + always @(posedge clock) + rd_data2 <= #1 ram_array[rd_addr2]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram16_2port + + diff --git a/usrp2/fpga/sdr_lib/hb/ram16_2sum.v b/usrp2/fpga/sdr_lib/hb/ram16_2sum.v new file mode 100644 index 00000000..559b06fd --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/ram16_2sum.v @@ -0,0 +1,27 @@ + + +module ram16_2sum (input clock, input write, + input [3:0] wr_addr, input [15:0] wr_data, + input [3:0] rd_addr1, input [3:0] rd_addr2, + output reg [15:0] sum); + + reg signed [15:0] ram_array [0:15]; + reg signed [15:0] a,b; + wire signed [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + always @(posedge clock) + begin + a <= #1 ram_array[rd_addr1]; + b <= #1 ram_array[rd_addr2]; + end + + assign sum_int = {a[15],a} + {b[15],b}; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + +endmodule // ram16_2sum diff --git a/usrp2/fpga/sdr_lib/hb/ram32_2sum.v b/usrp2/fpga/sdr_lib/hb/ram32_2sum.v new file mode 100644 index 00000000..d1f55b7d --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb/ram32_2sum.v @@ -0,0 +1,22 @@ + + +module ram32_2sum (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr1, input [4:0] rd_addr2, + output reg [15:0] sum); + + reg [15:0] ram_array [0:31]; + wire [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2]; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + + +endmodule // ram32_2sum + diff --git a/usrp2/fpga/sdr_lib/hb_dec.v b/usrp2/fpga/sdr_lib/hb_dec.v new file mode 100644 index 00000000..b256eb57 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb_dec.v @@ -0,0 +1,170 @@ +// Final halfband decimator +// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] +// Strobe in cannot come faster than every 2nd clock cycle +// These taps designed by halfgen4 from ldoolittle +// myfilt = round(2^18 * halfgen4(.7/4,8)) + +module hb_dec + #(parameter IWIDTH=18, OWIDTH=18, CWIDTH=18, ACCWIDTH=24) + (input clk, + input rst, + input bypass, + input [8:0] cpi, // Clocks per input -- equal to the decimation ratio ahead of this block + input stb_in, + input [IWIDTH-1:0] data_in, + output reg stb_out, + output reg [OWIDTH-1:0] data_out); + + // Control + reg [3:0] addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d; + wire write_odd, write_even, do_mult; + reg odd; + reg [2:0] phase, phase_d1; + reg stb_out_int; + wire clear, do_acc; + assign do_mult = 1; + + always @(posedge clk) + if(rst) + odd <= 0; + else if(stb_in) + odd <= ~odd; + + assign write_odd = stb_in & odd; + assign write_even = stb_in & ~odd; + + always @(posedge clk) + if(rst) + phase <= 0; + else if(stb_in & odd) + phase <= 1; + else if(phase == 4) + phase <= 0; + else if(phase != 0) + phase <= phase + 1; + + always @(posedge clk) + phase_d1 <= phase; + + reg [15:0] stb_out_pre; + always @(posedge clk) + if(rst) + stb_out_pre <= 0; + else + stb_out_pre <= {stb_out_pre[14:0],(stb_in & odd)}; + + always @* + case(phase) + 1 : begin addr_odd_a = 0; addr_odd_b = 15; end + 2 : begin addr_odd_a = 1; addr_odd_b = 14; end + 3 : begin addr_odd_a = 2; addr_odd_b = 13; end + 4 : begin addr_odd_a = 3; addr_odd_b = 12; end + default : begin addr_odd_a = 0; addr_odd_b = 15; end + endcase // case(phase) + + always @* + case(phase) + 1 : begin addr_odd_c = 4; addr_odd_d = 11; end + 2 : begin addr_odd_c = 5; addr_odd_d = 10; end + 3 : begin addr_odd_c = 6; addr_odd_d = 9; end + 4 : begin addr_odd_c = 7; addr_odd_d = 8; end + default : begin addr_odd_c = 4; addr_odd_d = 11; end + endcase // case(phase) + + assign do_acc = |stb_out_pre[6:3]; + assign clear = stb_out_pre[3]; + + // Data + wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d; + wire [IWIDTH-1:0] sum1, sum2; + wire [OWIDTH-1:0] final_sum; + reg [CWIDTH-1:0] coeff1, coeff2; + wire [35:0] prod1, prod2; + + always @* // Outer coeffs + case(phase_d1) + 1 : coeff1 = -107; + 2 : coeff1 = 445; + 3 : coeff1 = -1271; + 4 : coeff1 = 2959; + default : coeff1 = -107; + endcase // case(phase) + + always @* // Inner coeffs + case(phase_d1) + 1 : coeff2 = -6107; + 2 : coeff2 = 11953; + 3 : coeff2 = -24706; + 4 : coeff2 = 82359; + default : coeff2 = -6107; + endcase // case(phase) + + srl #(.WIDTH(IWIDTH)) srl_odd_a + (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_a),.out(data_odd_a)); + srl #(.WIDTH(IWIDTH)) srl_odd_b + (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_b),.out(data_odd_b)); + srl #(.WIDTH(IWIDTH)) srl_odd_c + (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_c),.out(data_odd_c)); + srl #(.WIDTH(IWIDTH)) srl_odd_d + (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_d),.out(data_odd_d)); + + add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1)); + add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2)); + + wire [IWIDTH-1:0] data_even; + reg [3:0] addr_even; + + always @(posedge clk) + case(cpi) + // 1 is an error + 2 : addr_even <= 9; // Maximum speed (overall decim by 4) + 3, 4, 5, 6, 7 : addr_even <= 8; + default : addr_even <= 7; + endcase // case(cpi) + + srl #(.WIDTH(IWIDTH)) srl_even + (.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even)); + + localparam MWIDTH = ACCWIDTH-2; + wire [MWIDTH-1:0] sum_of_prod; + + MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) ); + MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) ); + add2_and_round_reg #(.WIDTH(MWIDTH)) + add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod)); + + wire [ACCWIDTH-1:0] acc_out; + + acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) + acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out)); + + localparam SHIFT_FACTOR = ACCWIDTH-IWIDTH-5; + wire [ACCWIDTH-1:0] data_even_signext; + wire [ACCWIDTH:0] final_sum_unrounded; + + sign_extend #(.bits_in(IWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR)) + signext_data_even (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR])); + assign data_even_signext[SHIFT_FACTOR-1:0] = 0; + + add2_reg /* add2_and_round_reg */ #(.WIDTH(ACCWIDTH+1)) + final_adder (.clk(clk), .in1({acc_out,1'b0}), .in2({data_even_signext,1'b0}), .sum(final_sum_unrounded)); + + round_reg #(.bits_in(ACCWIDTH-4),.bits_out(OWIDTH)) + final_round (.clk(clk),.in(final_sum_unrounded[ACCWIDTH-5:0]),.out(final_sum)); + + // Output + always @(posedge clk) + if(bypass) + data_out <= data_in; + else if(stb_out_pre[9]) + data_out <= final_sum; + + always @(posedge clk) + if(rst) + stb_out <= 0; + else if(bypass) + stb_out <= stb_in; + else + stb_out <= stb_out_pre[9]; + +endmodule // hb_dec diff --git a/usrp2/fpga/sdr_lib/hb_dec_tb.v b/usrp2/fpga/sdr_lib/hb_dec_tb.v new file mode 100644 index 00000000..3e5faa80 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb_dec_tb.v @@ -0,0 +1,140 @@ +module hb_dec_tb( ) ; + + // Parameters for instantiation + parameter clocks = 9'd2 ; // Number of clocks per input + parameter decim = 1 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + reg strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + initial + begin + $dumpfile("hb_dec_tb.vcd"); + $dumpvars(0,hb_dec_tb); + end + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #1000 reset = 1'b0 ; + + // Enable the entire system + initial enable = 1'b1 ; + + // Instantiate UUT + /* + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + */ + + + hb_dec #(.IWIDTH(18),.OWIDTH(18),.CWIDTH(18),.ACCWIDTH(24)) uut + (.clk(clock),.rst(reset),.bypass(0),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in), + .stb_out(strobe_out),.data_out(data_out) ); + + integer i, ri, ro, infile, outfile ; + + always @(posedge clock) + begin + if(strobe_out) + $display(data_out); + end + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + strobe_in <= 1'd0 ; + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( posedge clock ) begin + //#1 ; + strobe_in <= 1'b1 ; + if( !$feof(infile) ) + ri = $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + + // Clocked in - set the strobe to 0 if the number of + // clocks per sample is greater than 1 + if( clocks > 1 ) begin + @(posedge clock) begin + strobe_in <= 1'b0 ; + end + + // Wait for the specified number of cycles + for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin + @(posedge clock) #1 ; + end + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $finish ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + //$display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + endofsim <= 1'b1 ; + end + end + end + +endmodule // hb_dec_tb + diff --git a/usrp2/fpga/sdr_lib/hb_interp.v b/usrp2/fpga/sdr_lib/hb_interp.v new file mode 100644 index 00000000..d16807e1 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb_interp.v @@ -0,0 +1,157 @@ +// First halfband iterpolator +// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] +// Strobe in cannot come faster than every 4th clock cycle, +// Strobe out cannot come faster than every 2nd clock cycle + +// These taps designed by halfgen4 from ldoolittle +// myfilt = round(2^18 * halfgen4(.7/4,8)) + +module hb_interp + #(parameter IWIDTH=18, OWIDTH=18, ACCWIDTH=24) + (input clk, + input rst, + input bypass, + input [7:0] cpo, // Clocks per output, must be at least 2 + input stb_in, + input [IWIDTH-1:0] data_in, + input stb_out, + output reg [OWIDTH-1:0] data_out); + + localparam MWIDTH = ACCWIDTH-2; + localparam CWIDTH = 18; + + reg [CWIDTH-1:0] coeff1, coeff2; + reg [3:0] addr_a, addr_b, addr_c, addr_d, addr_e; + wire [IWIDTH-1:0] data_a, data_b, data_c, data_d, data_e, sum1, sum2; + wire [35:0] prod1, prod2; + + reg [2:0] phase, phase_d1, phase_d2, phase_d3, phase_d4, phase_d5; + + always @(posedge clk) + if(rst) + phase <= 0; + else + if(stb_in) + phase <= 1; + else if(phase==4) + phase <= 0; + else if(phase!=0) + phase <= phase + 1; + always @(posedge clk) phase_d1 <= phase; + always @(posedge clk) phase_d2 <= phase_d1; + always @(posedge clk) phase_d3 <= phase_d2; + always @(posedge clk) phase_d4 <= phase_d3; + always @(posedge clk) phase_d5 <= phase_d4; + + srl #(.WIDTH(IWIDTH)) srl_a + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_a),.out(data_a)); + srl #(.WIDTH(IWIDTH)) srl_b + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_b),.out(data_b)); + srl #(.WIDTH(IWIDTH)) srl_c + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_c),.out(data_c)); + srl #(.WIDTH(IWIDTH)) srl_d + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_d),.out(data_d)); + srl #(.WIDTH(IWIDTH)) srl_e + (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_e),.out(data_e)); + + always @* + case(phase) + 1 : begin addr_a = 0; addr_b = 15; end + 2 : begin addr_a = 1; addr_b = 14; end + 3 : begin addr_a = 2; addr_b = 13; end + 4 : begin addr_a = 3; addr_b = 12; end + default : begin addr_a = 0; addr_b = 15; end + endcase // case(phase) + + always @* + case(phase) + 1 : begin addr_c = 4; addr_d = 11; end + 2 : begin addr_c = 5; addr_d = 10; end + 3 : begin addr_c = 6; addr_d = 9; end + 4 : begin addr_c = 7; addr_d = 8; end + default : begin addr_c = 4; addr_d = 11; end + endcase // case(phase) + + always @* + case(cpo) + 2 : addr_e <= 9; + 3,4,5,6,7,8 : addr_e <= 8; + default : addr_e <= 7; // This case works for 256, which = 0 due to overflow outside this block + endcase // case(cpo) + + always @* // Outer coeffs + case(phase_d1) + 1 : coeff1 = -107; + 2 : coeff1 = 445; + 3 : coeff1 = -1271; + 4 : coeff1 = 2959; + default : coeff1 = -107; + endcase // case(phase) + + always @* // Inner coeffs + case(phase_d1) + 1 : coeff2 = -6107; + 2 : coeff2 = 11953; + 3 : coeff2 = -24706; + 4 : coeff2 = 82359; + default : coeff2 = -6107; + endcase // case(phase) + + add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_a),.in2(data_b),.sum(sum1)); + add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_c),.in2(data_d),.sum(sum2)); + // sum1, sum2 available on phase_d1 + + wire do_mult = 1; + MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) ); + MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) ); + // prod1, prod2 available on phase_d2 + + wire [MWIDTH-1:0] sum_of_prod; + + add2_and_round_reg #(.WIDTH(MWIDTH)) + add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod)); + // sum_of_prod available on phase_d3 + + wire [ACCWIDTH-1:0] acc_out; + wire [OWIDTH-1:0] acc_round; + + wire clear = (phase_d3 == 1); + wire do_acc = (phase_d3 != 0); + + acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) + acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out)); + // acc_out available on phase_d4 + + wire [ACCWIDTH-6:0] clipped_acc; + clip #(.bits_in(ACCWIDTH),.bits_out(ACCWIDTH-5)) final_clip(.in(acc_out),.out(clipped_acc)); + + reg [ACCWIDTH-6:0] clipped_reg; + always @(posedge clk) + if(phase_d4 == 4) + clipped_reg <= clipped_acc; + // clipped_reg available on phase_d5 + + wire [OWIDTH-1:0] data_out_round; + round #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH)) final_round (.in(clipped_reg),.out(data_out_round)); + + reg odd; + always @(posedge clk) + if(rst) + odd <= 0; + else if(stb_in) + odd <= 0; + else if(stb_out) + odd <= 1; + + always @(posedge clk) + if(bypass) + data_out <= data_in; + else if(stb_out) + if(odd) + data_out <= data_e; + else + data_out <= data_out_round; + + // data_out available on phase_d6 + +endmodule // hb_interp diff --git a/usrp2/fpga/sdr_lib/hb_interp_tb.v b/usrp2/fpga/sdr_lib/hb_interp_tb.v new file mode 100644 index 00000000..52f137f2 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb_interp_tb.v @@ -0,0 +1,132 @@ +module hb_interp_tb( ) ; + + // Parameters for instantiation + parameter clocks = 8'd2 ; // Number of clocks per output + parameter decim = 1 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + wire strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + initial + begin + $dumpfile("hb_interp_tb.vcd"); + $dumpvars(0,hb_interp_tb); + end + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #1000 reset = 1'b0 ; + + always @(posedge clock) + enable <= ~reset; + + // Instantiate UUT + /* + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + */ + + cic_strober #(.WIDTH(8)) + out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks), + .strobe_fast(1),.strobe_slow(strobe_out) ); + + cic_strober #(.WIDTH(8)) + in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2), + .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); + + hb_interp #() uut + (.clk(clock),.rst(reset),.bypass(0),.cpo(clocks),.stb_in(strobe_in),.data_in(data_in), + .stb_out(strobe_out),/* .output_rate(clocks), */ .data_out(data_out) ); + + integer i, ri, ro, infile, outfile ; + + always @(posedge clock) + begin + if(strobe_out) + $display(data_out); + end + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( negedge clock ) begin + if(strobe_in) + if( !$feof(infile) ) + ri <= #1 $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $finish ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + //$display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + if($feof(infile)) + endofsim <= 1'b1 ; + end + end + end + +endmodule // small_hb_int_tb diff --git a/usrp2/fpga/sdr_lib/hb_tb.v b/usrp2/fpga/sdr_lib/hb_tb.v new file mode 100644 index 00000000..7e960fd1 --- /dev/null +++ b/usrp2/fpga/sdr_lib/hb_tb.v @@ -0,0 +1,155 @@ + +module hb_tb(); + + localparam SWIDTH = 17; + localparam CWIDTH = 18; + localparam TWIDTH = 20; + localparam ACC_WIDTH = 40; + + reg clk = 0, rst = 1; + wire strobe_in, strobe_out; + reg [SWIDTH-1:0] sample_in; + wire signed [SWIDTH:0] sample_out; + + reg set_stb; + reg [7:0] set_addr; + reg [31:0] set_data; + + localparam DECIM = 3; + + initial $dumpfile("hb_tb.vcd"); + initial $dumpvars(0,hb_tb); + + always #5 clk <= ~clk; + initial + begin + @(posedge clk); + @(negedge clk); + rst <= 0; + end + + reg [7:0] stb_counter; + always @(posedge clk) + if(rst) + stb_counter <= 0; + else + if(stb_counter == 0) + stb_counter <= DECIM; + else + stb_counter <= stb_counter - 1; + assign strobe_in = (stb_counter == 0); + + hb_decim #(.SWIDTH(SWIDTH),.CWIDTH(CWIDTH), + .TWIDTH(TWIDTH),.ACC_WIDTH(ACC_WIDTH)) hb_decim + (.clk(clk), .rst(rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .sample_in(sample_in), + .strobe_in(strobe_in), + .sample_out(sample_out), + .strobe_out(strobe_out) + ); + + initial + begin : load_coeffs + @(negedge rst); + @(posedge clk); + set_addr <= 124; // load coeffs + set_stb <= 1; + set_data <= -18'd49; + @(posedge clk); + set_data <= 18'd165; + @(posedge clk); + set_data <= -18'd412; + @(posedge clk); + set_data <= 18'd873; + @(posedge clk); + set_data <= -18'd1681; + @(posedge clk); + set_data <= 18'd3135; + @(posedge clk); + set_data <= -18'd6282; + @(posedge clk); + set_data <= 18'd20628; + @(posedge clk); + set_addr <=125; // load table + // { stb_out, accum, load_accum, done, even_addr, odd_addr_a, odd_addr_b, coeff_addr } + set_data <= {1'b1,1'b1,1'b0,1'b1,4'd15,4'd15,4'd0,4'd0}; // Phase 8 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd14,4'd1,4'd1}; // Phase 7 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd13,4'd2,4'd2}; // Phase 6 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd12,4'd3,4'd3}; // Phase 5 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd11,4'd4,4'd4}; // Phase 4 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd10,4'd5,4'd5}; // Phase 3 + @(posedge clk); + set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd9,4'd6,4'd6}; // Phase 2 + @(posedge clk); + set_data <= {1'b0,1'b0,1'b1,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 1 + @(posedge clk); + set_data <= {1'b0,1'b0,1'b0,1'b0,4'd15,4'd8,4'd7,4'd7}; // Phase 0 + @(posedge clk); + set_stb <= 0; + end // block: load_coeffs + + initial + begin + sample_in <= 0; + repeat(40) + @(posedge strobe_in); + $display("EVEN"); + sample_in <= 0; + repeat(10) + @(posedge strobe_in); + sample_in <= 1; + @(posedge strobe_in); + sample_in <= 0; + repeat(40) + @(posedge strobe_in); + sample_in <= 1; + repeat(40) + @(posedge strobe_in); + sample_in <= 0; + repeat(60) + @(posedge strobe_in); + sample_in <= 1; + repeat(2) + @(posedge strobe_in); + sample_in <= 0; + repeat(60) + @(posedge strobe_in); + $display("ODD"); + sample_in <= 0; + repeat(10) + @(posedge strobe_in); + sample_in <= 1; + @(posedge strobe_in); + sample_in <= 0; + repeat(40) + @(posedge strobe_in); + sample_in <= 1; + repeat(40) + @(posedge strobe_in); + sample_in <= 0; + repeat(60) + @(posedge strobe_in); + sample_in <= 1; + repeat(2) + @(posedge strobe_in); + sample_in <= 0; + repeat(60) + @(posedge strobe_in); + $finish; + end + + always @(posedge clk) + if(strobe_in) + $display(sample_in); + + always @(posedge clk) + if(strobe_out) + $display("\t",sample_out); + +endmodule // hb_tb diff --git a/usrp2/fpga/sdr_lib/input.dat b/usrp2/fpga/sdr_lib/input.dat new file mode 100644 index 00000000..1e649ac2 --- /dev/null +++ b/usrp2/fpga/sdr_lib/input.dat @@ -0,0 +1,341 @@ +0 +0 +0 +0 +0 +0 +0 +0 +-131072 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +131071 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +131071 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +100000 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +-131072 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +-131072 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 diff --git a/usrp2/fpga/sdr_lib/output.dat b/usrp2/fpga/sdr_lib/output.dat new file mode 100644 index 00000000..15db3ced --- /dev/null +++ b/usrp2/fpga/sdr_lib/output.dat @@ -0,0 +1,130 @@ +-1390 +0 +1604 +0 +-1896 +0 +2317 +0 +-2979 +0 +4172 +0 +-6953 +0 +20860 +32768 +20860 +0 +-6953 +0 +4172 +0 +-2979 +0 +2317 +0 +-1896 +0 +1604 +0 +-1390 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 + diff --git a/usrp2/fpga/sdr_lib/round.v b/usrp2/fpga/sdr_lib/round.v new file mode 100644 index 00000000..bff08883 --- /dev/null +++ b/usrp2/fpga/sdr_lib/round.v @@ -0,0 +1,33 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Rounding "macro" +// Keeps the topmost bits, does proper 2s comp rounding - round to zero + +module round + #(parameter bits_in=0, + parameter bits_out=0) + (input [bits_in-1:0] in, + output [bits_out-1:0] out); + + assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] & |in[bits_in-bits_out-1:0]); + +endmodule // round diff --git a/usrp2/fpga/sdr_lib/round_reg.v b/usrp2/fpga/sdr_lib/round_reg.v new file mode 100644 index 00000000..aa0972da --- /dev/null +++ b/usrp2/fpga/sdr_lib/round_reg.v @@ -0,0 +1,39 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2008 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +// Rounding "macro" +// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero) + +module round_reg + #(parameter bits_in=0, + parameter bits_out=0) + (input clk, + input [bits_in-1:0] in, + output reg [bits_out-1:0] out); + + wire [bits_out-1:0] temp; + + round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp)); + + always @(posedge clk) + out <= temp; + +endmodule // round diff --git a/usrp2/fpga/sdr_lib/rssi.v b/usrp2/fpga/sdr_lib/rssi.v new file mode 100644 index 00000000..e45e2148 --- /dev/null +++ b/usrp2/fpga/sdr_lib/rssi.v @@ -0,0 +1,30 @@ + + +module rssi (input clock, input reset, input enable, + input [11:0] adc, output [15:0] rssi, output [15:0] over_count); + + wire over_hi = (adc == 12'h7FF); + wire over_lo = (adc == 12'h800); + wire over = over_hi | over_lo; + + reg [25:0] over_count_int; + always @(posedge clock) + if(reset | ~enable) + over_count_int <= #1 26'd0; + else + over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10]; + + assign over_count = over_count_int[25:10]; + + wire [11:0] abs_adc = adc[11] ? ~adc : adc; + + reg [25:0] rssi_int; + always @(posedge clock) + if(reset | ~enable) + rssi_int <= #1 26'd0; + else + rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10]; + + assign rssi = rssi_int[25:10]; + +endmodule // rssi diff --git a/usrp2/fpga/sdr_lib/rx_control.v b/usrp2/fpga/sdr_lib/rx_control.v new file mode 100644 index 00000000..d41a28bc --- /dev/null +++ b/usrp2/fpga/sdr_lib/rx_control.v @@ -0,0 +1,213 @@ + +`define DSP_CORE_RX_BASE 160 + +module rx_control + #(parameter FIFOSIZE = 10) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [31:0] master_time, + output overrun, + + // To Buffer interface + output [31:0] wr_dat_o, + output wr_write_o, + output wr_done_o, + output wr_error_o, + + input wr_ready_i, + input wr_full_i, + + // From DSP Core + input [31:0] sample, + output run, + input strobe, + + // FIFO Levels + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty, + + // Debug + output [31:0] debug_rx + ); + + wire [31:0] new_time, new_command; + wire sc_pre1, clear_overrun; + wire [31:0] rcvtime_pre; + reg [31:0] rcvtime; + wire [8:0] lines_per_frame; + wire [20:0] numlines; + wire send_imm_pre, chain_pre; + reg send_imm, chain; + wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl; + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(new_time),.changed(sc_pre1)); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+4)) sr_4 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(new_command),.changed()); + + setting_reg #(.my_addr(`DSP_CORE_RX_BASE+5)) sr_5 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_overrun)); + + reg sc_pre2; + always @(posedge clk) + sc_pre2 <= sc_pre1; + assign write_ctrl = sc_pre1 & ~sc_pre2; + + shortfifo #(.WIDTH(64)) commandfifo + (.clk(clk),.rst(rst),.clear(clear_overrun), + .datain({new_command,new_time}), .write(write_ctrl), .full(full_ctrl), + .dataout({send_imm_pre,chain_pre,numlines,lines_per_frame,rcvtime_pre}), + .read(read_ctrl), .empty(empty_ctrl) ); + + // Buffer interface to internal FIFO + wire write, full, read, empty; + wire sop_o, eop_o; + + reg xfer_state; + localparam XFER_IDLE = 1'b0; + localparam XFER_GO = 1'b1; + + always @(posedge clk) + if(rst) + xfer_state <= XFER_IDLE; + else + if(clear_overrun) + xfer_state <= XFER_IDLE; + else + case(xfer_state) + XFER_IDLE : + if(wr_ready_i) + xfer_state <= XFER_GO; + XFER_GO : + if((eop_o | wr_full_i) & wr_write_o) + xfer_state <= XFER_IDLE; + default : + xfer_state <= XFER_IDLE; + endcase // case(xfer_state) + + assign wr_write_o = (xfer_state == XFER_GO) & ~empty; + assign wr_done_o = (eop_o & wr_write_o); + assign wr_error_o = 0; // FIXME add check here for eop if we have wr_full_i once we have IBS + + assign read = wr_write_o | (~empty & ~sop_o); // FIXME what if there is junk between packets? + + wire [33:0] fifo_line; + + // Internal FIFO, size 9 is 2K, size 10 is 4K + cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo + (.clk(clk),.rst(rst),.clear(clear_overrun), + .datain(fifo_line), .write(write), .full(full), + .dataout({sop_o,eop_o,wr_dat_o}), .read(read), .empty(empty), + .space(),.occupied(fifo_occupied) ); + assign fifo_full = full; + assign fifo_empty = empty; + + // Internal FIFO to DSP interface + reg [22:0] lines_left; + reg [8:0] lines_left_frame; + localparam IBS_IDLE = 0; + localparam IBS_WAITING = 1; + localparam IBS_FIRSTLINE = 2; + localparam IBS_RUNNING = 3; + localparam IBS_OVERRUN = 4; + + reg [2:0] ibs_state; + + wire [32:0] delta_time = {1'b0,rcvtime}-{1'b0,master_time}; + wire too_late = (delta_time[32:31] == 2'b11) & ~send_imm; + wire go_now = send_imm | ( master_time == rcvtime ); + + always @(posedge clk) + if(rst) + begin + ibs_state <= IBS_IDLE; + lines_left <= 0; + lines_left_frame <= 0; + rcvtime <= 0; + send_imm <= 0; + chain <= 0; + end + else + if(clear_overrun) + begin + ibs_state <= IBS_IDLE; + lines_left <= 0; + lines_left_frame <= 0; + rcvtime <= 0; + send_imm <= 0; + chain <= 0; + end + else + case(ibs_state) + IBS_IDLE : + if(~empty_ctrl) + begin + lines_left <= numlines; + lines_left_frame <= lines_per_frame; + rcvtime <= rcvtime_pre; + ibs_state <= IBS_WAITING; + send_imm <= send_imm_pre; + chain <= chain_pre; + end + IBS_WAITING : + if(go_now) + ibs_state <= IBS_FIRSTLINE; + else if(too_late) + ibs_state <= IBS_OVERRUN; + IBS_FIRSTLINE : + if(full | strobe) + ibs_state <= IBS_OVERRUN; + else + ibs_state <= IBS_RUNNING; + IBS_RUNNING : + if(strobe) + if(full) + ibs_state <= IBS_OVERRUN; + else + begin + lines_left <= lines_left - 1; + if(lines_left == 1) + if(~chain) + ibs_state <= IBS_IDLE; + else if(empty_ctrl) + ibs_state <= IBS_OVERRUN; + else + begin + lines_left <= numlines; + lines_left_frame <= lines_per_frame; + rcvtime <= rcvtime_pre; + ibs_state <= IBS_FIRSTLINE; + send_imm <= send_imm_pre; + chain <= chain_pre; + end + else if(lines_left_frame == 1) + begin + lines_left_frame <= lines_per_frame; + ibs_state <= IBS_FIRSTLINE; + end + else + lines_left_frame <= lines_left_frame - 1; + end // else: !if(full) + endcase // case(ibs_state) + + assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {1'b1,1'b0,master_time} : + {1'b0,((lines_left==1)|(lines_left_frame==1)),sample}; + + assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & ~full; // & (ibs_state == IBS_RUNNING) should strobe only when running + assign overrun = (ibs_state == IBS_OVERRUN); + assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE); + assign read_ctrl = ( (ibs_state == IBS_IDLE) | + ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) + & ~empty_ctrl; + + assign debug_rx = { 6'd0,send_imm,chain, + wr_write_o, wr_done_o, wr_ready_i, wr_full_i,xfer_state,eop_o, sop_o, run, + write,full,read,empty,write_ctrl,full_ctrl,read_ctrl,empty_ctrl, + sc_pre1, clear_overrun, go_now, too_late, overrun, ibs_state[2:0] }; +endmodule // rx_control diff --git a/usrp2/fpga/sdr_lib/rx_dcoffset.v b/usrp2/fpga/sdr_lib/rx_dcoffset.v new file mode 100644 index 00000000..bedbd40e --- /dev/null +++ b/usrp2/fpga/sdr_lib/rx_dcoffset.v @@ -0,0 +1,43 @@ + + +module rx_dcoffset + #(parameter WIDTH=14, + parameter ADDR=8'd0) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input signed [WIDTH-1:0] adc_in, output signed [WIDTH-1:0] adc_out); + + // Because of some extra delays to make timing easier, the transfer function is: + // (z-1)/(z^2-z-alpha) where alpha is 1/2^n + + wire set_now = set_stb & (ADDR == set_addr); + + reg fixed; // uses fixed offset + wire signed [WIDTH-1:0] fixed_dco; + reg signed [31:0] integrator; + + always @(posedge clk) + if(rst) + begin + fixed <= 0; + integrator <= 32'd0; + end + else if(set_now) + begin + integrator <= {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}}; + fixed <= set_data[31]; + end + else if(~fixed) + integrator <= integrator + adc_out; + + wire [WIDTH:0] scaled_integrator; + + round #(.bits_in(33),.bits_out(15)) round (.in({integrator[31],integrator}),.out(scaled_integrator)); + + wire [WIDTH:0] adc_out_int = {adc_in[WIDTH-1],adc_in} - scaled_integrator; + + clip_reg #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip_adc + (.clk(clk),.in(adc_out_int),.out(adc_out)); + + +endmodule // rx_dcoffset diff --git a/usrp2/fpga/sdr_lib/rx_dcoffset_tb.v b/usrp2/fpga/sdr_lib/rx_dcoffset_tb.v new file mode 100644 index 00000000..a8b4ec20 --- /dev/null +++ b/usrp2/fpga/sdr_lib/rx_dcoffset_tb.v @@ -0,0 +1,25 @@ + +`timescale 1ns/1ns +module rx_dcoffset_tb(); + + reg clk, rst; + + initial rst = 1; + initial #1000 rst = 0; + initial clk = 0; + always #5 clk = ~clk; + + initial $dumpfile("rx_dcoffset_tb.vcd"); + initial $dumpvars(0,rx_dcoffset_tb); + + reg [13:0] adc_in = 7; + wire [13:0] adc_out; + + always @(posedge clk) + $display("%d\t%d",adc_in,adc_out); + + rx_dcoffset #(.WIDTH(14),.ADDR(0)) + rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0), + .adc_in(adc_in),.adc_out(adc_out)); + +endmodule // longfifo_tb diff --git a/usrp2/fpga/sdr_lib/sign_extend.v b/usrp2/fpga/sdr_lib/sign_extend.v new file mode 100644 index 00000000..eae67faf --- /dev/null +++ b/usrp2/fpga/sdr_lib/sign_extend.v @@ -0,0 +1,35 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + + +// Sign extension "macro" +// bits_out should be greater than bits_in + +module sign_extend (in,out); + parameter bits_in=0; // FIXME Quartus insists on a default + parameter bits_out=0; + + input [bits_in-1:0] in; + output [bits_out-1:0] out; + + assign out = {{(bits_out-bits_in){in[bits_in-1]}},in}; + +endmodule diff --git a/usrp2/fpga/sdr_lib/small_hb_dec.v b/usrp2/fpga/sdr_lib/small_hb_dec.v new file mode 100644 index 00000000..9957de15 --- /dev/null +++ b/usrp2/fpga/sdr_lib/small_hb_dec.v @@ -0,0 +1,99 @@ +// Short halfband decimator (intended to be followed by another stage) +// Implements impulse responses of the form [A 0 B 0.5 B 0 A] +// +// These taps designed by halfgen4 from ldoolittle: +// 2 * 131072 * halfgen4(.75/8,2) +module small_hb_dec + #(parameter WIDTH=18) + (input clk, + input rst, + input bypass, + input stb_in, + input [WIDTH-1:0] data_in, + output reg stb_out, + output [WIDTH-1:0] data_out); + + reg stb_in_d1; + reg [WIDTH-1:0] data_in_d1; + always @(posedge clk) stb_in_d1 <= stb_in; + always @(posedge clk) data_in_d1 <= data_in; + + wire go; + reg phase, go_d1, go_d2, go_d3, go_d4; + always @(posedge clk) + if(rst) + phase <= 0; + else if(stb_in_d1) + phase <= ~phase; + assign go = stb_in_d1 & phase; + always @(posedge clk) go_d1 <= go; + always @(posedge clk) go_d2 <= go_d1; + always @(posedge clk) go_d3 <= go_d2; + always @(posedge clk) go_d4 <= go_d3; + + wire [17:0] coeff_a = -10690; + wire [17:0] coeff_b = 75809; + + reg [WIDTH-1:0] d1, d2, d3, d4 , d5, d6; + always @(posedge clk) + if(stb_in_d1 | rst) + begin + d1 <= data_in_d1; + d2 <= d1; + d3 <= d2; + d4 <= d3; + d5 <= d4; + d6 <= d5; + end + + reg [17:0] sum_a, sum_b, middle, middle_d1; + wire [17:0] sum_a_unreg, sum_b_unreg; + add2 #(.WIDTH(18)) add2_a (.in1(data_in_d1),.in2(d6),.sum(sum_a_unreg)); + add2 #(.WIDTH(18)) add2_b (.in1(d2),.in2(d4),.sum(sum_b_unreg)); + + always @(posedge clk) + if(go) + begin + sum_a <= sum_a_unreg; + sum_b <= sum_b_unreg; + middle <= d3; + end + + always @(posedge clk) + if(go_d1) + middle_d1 <= middle; + + wire [17:0] sum = go_d1 ? sum_b : sum_a; + wire [17:0] coeff = go_d1 ? coeff_b : coeff_a; + wire [35:0] prod; + MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), .B(sum) ); + + reg [35:0] accum; + always @(posedge clk) + if(rst) + accum <= 0; + else if(go_d2) + accum <= {middle_d1[17],middle_d1[17],middle_d1,16'd0} + {prod}; + else if(go_d3) + accum <= accum + {prod}; + + wire [17:0] accum_rnd; + round #(.bits_in(36),.bits_out(18)) round_acc (.in(accum),.out(accum_rnd)); + + reg [17:0] final_sum; + always @(posedge clk) + if(bypass) + final_sum <= data_in_d1; + else if(go_d4) + final_sum <= accum_rnd; + + assign data_out = final_sum; + + always @(posedge clk) + if(rst) + stb_out <= 0; + else if(bypass) + stb_out <= stb_in_d1; + else + stb_out <= go_d4; +endmodule // small_hb_dec diff --git a/usrp2/fpga/sdr_lib/small_hb_dec_tb.v b/usrp2/fpga/sdr_lib/small_hb_dec_tb.v new file mode 100644 index 00000000..0d6a0689 --- /dev/null +++ b/usrp2/fpga/sdr_lib/small_hb_dec_tb.v @@ -0,0 +1,140 @@ +module hb_dec_tb( ) ; + + // Parameters for instantiation + parameter clocks = 9'd2 ; // Number of clocks per input + parameter decim = 1 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + reg strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + initial + begin + $dumpfile("hb_dec_tb.vcd"); + $dumpvars(0,hb_dec_tb); + end + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #1000 reset = 1'b0 ; + + // Enable the entire system + initial enable = 1'b1 ; + + // Instantiate UUT + /* + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + */ + + + small_hb_dec #(.WIDTH(18)) uut + (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), + .stb_out(strobe_out),.data_out(data_out) ); + + integer i, ri, ro, infile, outfile ; + + always @(posedge clock) + begin + if(strobe_out) + $display(data_out); + end + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + strobe_in <= 1'd0 ; + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( posedge clock ) begin + //#1 ; + strobe_in <= 1'b1 ; + if( !$feof(infile) ) + ri = $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + + // Clocked in - set the strobe to 0 if the number of + // clocks per sample is greater than 1 + if( clocks > 1 ) begin + @(posedge clock) begin + strobe_in <= 1'b0 ; + end + + // Wait for the specified number of cycles + for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin + @(posedge clock) #1 ; + end + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $finish ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + //$display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + endofsim <= 1'b1 ; + end + end + end + +endmodule // hb_dec_tb + diff --git a/usrp2/fpga/sdr_lib/small_hb_int.v b/usrp2/fpga/sdr_lib/small_hb_int.v new file mode 100644 index 00000000..f80d3cac --- /dev/null +++ b/usrp2/fpga/sdr_lib/small_hb_int.v @@ -0,0 +1,85 @@ +// Short halfband decimator (intended to be followed by another stage) +// Implements impulse responses of the form [A 0 B 0.5 B 0 A] +// +// These taps designed by halfgen4 from ldoolittle: +// 2 * 131072 * halfgen4(.75/8,2) + +module small_hb_int + #(parameter WIDTH=18) + (input clk, + input rst, + input bypass, + input stb_in, + input [WIDTH-1:0] data_in, + input [7:0] output_rate, + input stb_out, + output reg [WIDTH-1:0] data_out); + + reg phase; + reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6; + + localparam MWIDTH = 36; + wire [MWIDTH-1:0] prod; + + reg [6:0] stbin_d; + + always @(posedge clk) + stbin_d <= {stbin_d[5:0],stb_in}; + + always @(posedge clk) + if(stb_in) + begin + d1 <= data_in; + d2 <= d1; + d3 <= d2; + d4 <= d3; + d5 <= d4; + d6 <= d5; + end + + wire [WIDTH-1:0] sum_outer, sum_inner; + add2_and_round_reg #(.WIDTH(WIDTH)) add_outer (.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer)); + add2_and_round_reg #(.WIDTH(WIDTH)) add_inner (.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner)); + + wire [17:0] coeff_outer = -10690; + wire [17:0] coeff_inner = 75809; + + MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? coeff_outer : coeff_inner), + .B(stbin_d[1] ? sum_outer : sum_inner) ); + + wire [MWIDTH:0] accum; + acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) + acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum)); + + wire [WIDTH+2:0] accum_rnd; + round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3)) + final_round (.clk(clk),.in(accum),.out(accum_rnd)); + + wire [WIDTH-1:0] clipped; + clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) + final_clip (.clk(clk),.in(accum_rnd),.out(clipped)); + + reg [WIDTH-1:0] saved, saved_d3; + always @(posedge clk) + if(stbin_d[6]) + saved <= clipped; + + always @(posedge clk) + if(stbin_d[3]) + saved_d3 <= d3; + + always @(posedge clk) + if(bypass) + data_out <= data_in; + else if(stb_in & stb_out) + case(output_rate) + 1 : data_out <= d6; + 2 : data_out <= d4; + 3, 4, 5, 6, 7 : data_out <= d3; + default : data_out <= d2; + endcase // case(output_rate) + else if(stb_out) + data_out <= saved; + +endmodule // small_hb_int + diff --git a/usrp2/fpga/sdr_lib/small_hb_int_tb.v b/usrp2/fpga/sdr_lib/small_hb_int_tb.v new file mode 100644 index 00000000..71d77f0a --- /dev/null +++ b/usrp2/fpga/sdr_lib/small_hb_int_tb.v @@ -0,0 +1,132 @@ +module small_hb_int_tb( ) ; + + // Parameters for instantiation + parameter clocks = 8'd1 ; // Number of clocks per output + parameter decim = 1 ; // Sets the filter to decimate + parameter rate = 2 ; // Sets the decimation rate + + reg clock ; + reg reset ; + reg enable ; + wire strobe_in ; + reg signed [17:0] data_in ; + wire strobe_out ; + wire signed [17:0] data_out ; + + initial + begin + $dumpfile("small_hb_int_tb.vcd"); + $dumpvars(0,small_hb_int_tb); + end + + // Setup the clock + initial clock = 1'b0 ; + always #5 clock <= ~clock ; + + // Come out of reset after a while + initial reset = 1'b1 ; + initial #1000 reset = 1'b0 ; + + always @(posedge clock) + enable <= ~reset; + + // Instantiate UUT + /* + halfband_ideal + #( + .decim ( decim ), + .rate ( rate ) + ) uut( + .clock ( clock ), + .reset ( reset ), + .enable ( enable ), + .strobe_in ( strobe_in ), + .data_in ( data_in ), + .strobe_out ( strobe_out ), + .data_out ( data_out ) + ) ; + */ + + cic_strober #(.WIDTH(8)) + out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks), + .strobe_fast(1),.strobe_slow(strobe_out) ); + + cic_strober #(.WIDTH(8)) + in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2), + .strobe_fast(strobe_out),.strobe_slow(strobe_in) ); + + small_hb_int #(.WIDTH(18)) uut + (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in), + .stb_out(strobe_out),.output_rate(clocks),.data_out(data_out) ); + + integer i, ri, ro, infile, outfile ; + + always @(posedge clock) + begin + if(strobe_out) + $display(data_out); + end + + // Setup file IO + initial begin + infile = $fopen("input.dat","r") ; + outfile = $fopen("output.dat","r") ; + $timeformat(-9, 2, " ns", 10) ; + end + + reg endofsim ; + reg signed [17:0] compare ; + integer noe ; + initial noe = 0 ; + + initial begin + // Initialize inputs + data_in <= 18'd0 ; + + // Wait for reset to go away + @(negedge reset) #0 ; + + // While we're still simulating ... + while( !endofsim ) begin + + // Write the input from the file or 0 if EOF... + @( negedge clock ) begin + if(strobe_in) + if( !$feof(infile) ) + ri <= #1 $fscanf( infile, "%d", data_in ) ; + else + data_in <= 18'd0 ; + end + end + + // Print out the number of errors that occured + if( noe ) + $display( "FAILED: %d errors during simulation", noe ) ; + else + $display( "PASSED: Simulation successful" ) ; + + $finish ; + end + + // Output comparison of simulated values versus known good values + always @ (posedge clock) begin + if( reset ) + endofsim <= 1'b0 ; + else begin + if( !$feof(outfile) ) begin + if( strobe_out ) begin + ro = $fscanf( outfile, "%d\n", compare ) ; + if( compare != data_out ) begin + //$display( "%t: %d != %d", $realtime, data_out, compare ) ; + noe = noe + 1 ; + end + end + end else begin + // Signal end of simulation when no more outputs + if($feof(infile)) + endofsim <= 1'b1 ; + end + end + end + +endmodule // small_hb_int_tb diff --git a/usrp2/fpga/sdr_lib/tx_control.v b/usrp2/fpga/sdr_lib/tx_control.v new file mode 100644 index 00000000..0c4ab1a5 --- /dev/null +++ b/usrp2/fpga/sdr_lib/tx_control.v @@ -0,0 +1,160 @@ + +`define DSP_CORE_TX_BASE 128 + +module tx_control + #(parameter FIFOSIZE = 10) + (input clk, input rst, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + + input [31:0] master_time, + output underrun, + + // To Buffer interface + input [31:0] rd_dat_i, + input rd_sop_i, + input rd_eop_i, + output rd_read_o, + output rd_done_o, + output rd_error_o, + + // To DSP Core + output [31:0] sample, + output run, + input strobe, + + // FIFO Levels + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty, + + // Debug + output [31:0] debug + ); + + // Buffer interface to internal FIFO + wire write_data, write_ctrl, full_data, full_ctrl; + wire read_data, read_ctrl, empty_data, empty_ctrl; + wire clear_state; + reg [1:0] xfer_state; + reg [2:0] held_flags; + + localparam XFER_IDLE = 0; + localparam XFER_1 = 1; + localparam XFER_2 = 2; + localparam XFER_DATA = 3; + + always @(posedge clk) + if(rst) + xfer_state <= XFER_IDLE; + else + if(clear_state) + xfer_state <= XFER_IDLE; + else + case(xfer_state) + XFER_IDLE : + if(rd_sop_i) + xfer_state <= XFER_1; + XFER_1 : + begin + xfer_state <= XFER_2; + held_flags <= rd_dat_i[2:0]; + end + XFER_2 : + if(~full_ctrl) + xfer_state <= XFER_DATA; + XFER_DATA : + if(rd_eop_i & ~full_data) + xfer_state <= XFER_IDLE; + endcase // case(xfer_state) + + assign write_data = (xfer_state == XFER_DATA) & ~full_data; + assign write_ctrl = (xfer_state == XFER_2) & ~full_ctrl; + + assign rd_read_o = (xfer_state == XFER_1) | write_data | write_ctrl; + assign rd_done_o = 0; // Always take everything we're given + assign rd_error_o = 0; // Should we indicate overruns here? + + wire [31:0] data_o; + wire sop_o, eop_o, eob, sob, send_imm; + wire [31:0] sendtime; + wire [4:0] occ_ctrl; + + cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) txctrlfifo + (.clk(clk),.rst(rst),.clear(clear_state), + .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write_data), .full(full_data), + .dataout({sop_o,eop_o,data_o}), .read(read_data), .empty(empty_data), + .space(), .occupied(fifo_occupied) ); + assign fifo_full = full_data; + assign fifo_empty = empty_data; + + shortfifo #(.WIDTH(35)) ctrlfifo + (.clk(clk),.rst(rst),.clear(clear_state), + .datain({held_flags[2:0],rd_dat_i}), .write(write_ctrl), .full(full_ctrl), + .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), .empty(empty_ctrl), + .space(), .occupied(occ_ctrl) ); + + // Internal FIFO to DSP interface + reg [2:0] ibs_state; + + localparam IBS_IDLE = 0; + localparam IBS_WAIT = 1; + localparam IBS_RUNNING = 2; + localparam IBS_CONT_BURST = 3; + localparam IBS_UNDERRUN = 7; + + wire [32:0] delta_time = {1'b0,sendtime}-{1'b0,master_time}; + + wire too_late = (delta_time[32:31] == 2'b11); + wire go_now = ( master_time == sendtime ); + + always @(posedge clk) + if(rst) + ibs_state <= IBS_IDLE; + else + case(ibs_state) + IBS_IDLE : + if(~empty_ctrl & ~empty_data) + ibs_state <= IBS_WAIT; + IBS_WAIT : + if(send_imm) + ibs_state <= IBS_RUNNING; + else if(too_late) + ibs_state <= IBS_UNDERRUN; + else if(go_now) + ibs_state <= IBS_RUNNING; + IBS_RUNNING : + if(strobe) + if(empty_data) + ibs_state <= IBS_UNDERRUN; + else if(eop_o) + if(eob) + ibs_state <= IBS_IDLE; + else + ibs_state <= IBS_CONT_BURST; + IBS_CONT_BURST : + if(~empty_ctrl) // & ~empty_data) + ibs_state <= IBS_RUNNING; + else if(strobe) + ibs_state <= IBS_UNDERRUN; + IBS_UNDERRUN : // FIXME Should probably clean everything out + if(clear_state) + ibs_state <= IBS_IDLE; + endcase // case(ibs_state) + + assign read_ctrl = (ibs_state == IBS_RUNNING) & strobe & eop_o; // & ~empty_ctrl; + assign read_data = (ibs_state == IBS_RUNNING) & strobe & ~empty_data; + assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_CONT_BURST); + assign underrun = (ibs_state == IBS_UNDERRUN); + + wire [7:0] interp_rate; + setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_state)); + + assign sample = data_o; + + assign debug = { {16'b0}, + { read_data, write_data, read_ctrl, write_ctrl, xfer_state[1:0],full_ctrl,empty_ctrl }, + { occ_ctrl, eop_o, clear_state, underrun} }; + +endmodule // tx_control diff --git a/usrp2/fpga/serdes/serdes.v b/usrp2/fpga/serdes/serdes.v new file mode 100644 index 00000000..81e9f2b4 --- /dev/null +++ b/usrp2/fpga/serdes/serdes.v @@ -0,0 +1,65 @@ + +// SERDES TX and RX along with all flow control logic + +module serdes + #(parameter TXFIFOSIZE = 9, + parameter RXFIFOSIZE = 9) + (input clk, input rst, + // TX side + output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb, + input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o, + input rd_sop_i, input rd_eop_i, + // RX side + input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb, + output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o, + input wr_ready_i, input wr_full_i, + + output [15:0] tx_occupied, output tx_full, output tx_empty, + output [15:0] rx_occupied, output rx_full, output rx_empty, + + output [31:0] debug0, + output [31:0] debug1); + + wire [15:0] fifo_space; + wire xon_rcvd, xoff_rcvd, inhibit_tx, send_xon, send_xoff, sent; + wire [31:0] debug_rx, debug_tx; + + serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx + (.clk(clk),.rst(rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd_dat_i),.rd_read_o(rd_read_o),.rd_done_o(rd_done_o),.rd_error_o(rd_error_o), + .rd_sop_i(rd_sop_i),.rd_eop_i(rd_eop_i), + .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent), + .fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty), + .debug(debug_tx) ); + + serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx + (.clk(clk),.rst(rst), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr_dat_o),.wr_write_o(wr_write_o),.wr_done_o(wr_done_o),.wr_error_o(wr_error_o), + .wr_ready_i(wr_ready_i),.wr_full_i(wr_full_i), + .fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd), + .fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty), + .debug(debug_rx) ); + + serdes_fc_tx serdes_fc_tx + (.clk(clk),.rst(rst), + .xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),.inhibit_tx(inhibit_tx) ); + + serdes_fc_rx #(.LWMARK(32),.HWMARK(128)) serdes_fc_rx + (.clk(clk),.rst(rst), + .fifo_space(fifo_space),.send_xon(send_xon),.send_xoff(send_xoff),.sent(sent) ); + + //assign debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] }; + //assign debug = debug_rx; + + assign debug0 = { { debug_tx[3:0] /* xfer_active,state[2:0] */, rd_read_o, rd_done_o, rd_sop_i, rd_eop_i }, + { debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb}, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug1 = { { debug_rx[7:0] }, /* odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */ + { wr_write_o, wr_error_o, wr_ready_i, wr_done_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb }, + { ser_r[15:8] }, + { ser_r[7:0] } }; +endmodule // serdes diff --git a/usrp2/fpga/serdes/serdes_fc_rx.v b/usrp2/fpga/serdes/serdes_fc_rx.v new file mode 100644 index 00000000..4dd46e27 --- /dev/null +++ b/usrp2/fpga/serdes/serdes_fc_rx.v @@ -0,0 +1,62 @@ + + +module serdes_fc_rx + #(parameter LWMARK = 64, + parameter HWMARK = 320) + (input clk, input rst, + input [15:0] fifo_space, + output reg send_xon, + output reg send_xoff, + input sent); + + reg [15:0] countdown; + reg send_xon_int, send_xoff_int; + + always @(posedge clk) + if(rst) + begin + send_xon_int <= 0; + send_xoff_int <= 0; + countdown <= 0; + end + else + begin + send_xon_int <= 0; + send_xoff_int <= 0; + if(countdown == 0) + if(fifo_space < LWMARK) + begin + send_xoff_int <= 1; + countdown <= 240; + end + else + ; + else + if(fifo_space > HWMARK) + begin + send_xon_int <= 1; + countdown <= 0; + end + else + countdown <= countdown - 1; + end // else: !if(rst) + + // If we are between the high and low water marks, we let the countdown expire + + always @(posedge clk) + if(rst) + send_xon <= 0; + else if(send_xon_int) + send_xon <= 1; + else if(sent) + send_xon <= 0; + + always @(posedge clk) + if(rst) + send_xoff <= 0; + else if(send_xoff_int) + send_xoff <= 1; + else if(sent) + send_xoff <= 0; + +endmodule // serdes_fc_rx diff --git a/usrp2/fpga/serdes/serdes_fc_tx.v b/usrp2/fpga/serdes/serdes_fc_tx.v new file mode 100644 index 00000000..2fe967c8 --- /dev/null +++ b/usrp2/fpga/serdes/serdes_fc_tx.v @@ -0,0 +1,24 @@ + + +module serdes_fc_tx + (input clk, input rst, + input xon_rcvd, input xoff_rcvd, output reg inhibit_tx); + + // XOFF means stop sending, XON means start sending + // clock domain stuff happens elsewhere, everything here is on main clk + + reg [15:0] state; + always @(posedge clk) + if(rst) + state <= 0; + else if(xoff_rcvd) + state <= 255; + else if(xon_rcvd) + state <= 0; + else if(state !=0) + state <= state - 1; + + always @(posedge clk) + inhibit_tx <= (state != 0); + +endmodule // serdes_fc_tx diff --git a/usrp2/fpga/serdes/serdes_rx.v b/usrp2/fpga/serdes/serdes_rx.v new file mode 100644 index 00000000..bbe263b1 --- /dev/null +++ b/usrp2/fpga/serdes/serdes_rx.v @@ -0,0 +1,353 @@ + +// SERDES Interface + +// LS-Byte is sent first, MS-Byte is second +// Invalid K Codes +// K0.0 000-00000 Error detected +// K31.7 111-11111 Loss of input signal + +// Valid K Codes +// K28.0 000-11100 +// K28.1 001-11100 Alternate COMMA? +// K28.2 010-11100 +// K28.3 011-11100 +// K28.4 100-11100 +// K28.5 101-11100 Standard COMMA? +// K28.6 110-11100 +// K28.7 111-11100 Bad COMMA? +// K23.7 111-10111 +// K27.7 111-11011 +// K29.7 111-11101 +// K30.7 111-11110 + +module serdes_rx + #(parameter FIFOSIZE = 9) + (input clk, + input rst, + + // RX HW Interface + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + output [31:0] wr_dat_o, + output wr_write_o, + output wr_done_o, + output wr_error_o, + input wr_ready_i, + input wr_full_i, + + output [15:0] fifo_space, + output xon_rcvd, output xoff_rcvd, + + output [15:0] fifo_occupied, output fifo_full, output fifo_empty, + output [31:0] debug + ); + + localparam K_COMMA = 8'b101_11100; // 0xBC K28.5 + localparam K_IDLE = 8'b001_11100; // 0x3C K28.1 + localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6 + localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4 + localparam K_XON = 8'b010_11100; // 0x5C K28.2 + localparam K_XOFF = 8'b011_11100; // 0x7C K28.3 + localparam K_LOS = 8'b111_11111; // 0xFF K31.7 + localparam K_ERROR = 8'b000_00000; // 0x00 K00.0 + localparam D_56 = 8'b110_00101; // 0xC5 D05.6 + + localparam IDLE = 3'd0; + localparam FIRSTLINE1 = 3'd1; + localparam FIRSTLINE2 = 3'd2; + localparam PKT1 = 3'd3; + localparam PKT2 = 3'd4; + localparam CRC_CHECK = 3'd5; + localparam ERROR = 3'd6; + localparam DONE = 3'd7; + + wire [17:0] even_data; + reg [17:0] odd_data; + wire [17:0] chosen_data; + reg odd; + + reg [31:0] line_i; + reg sop_i, eop_i, error_i; + wire error_o, sop_o, eop_o, write, read, empty, full; + reg [15:0] halfline; + reg [8:0] holder; + wire [31:0] line_o; + + reg [2:0] state; + + reg [15:0] CRC; + wire [15:0] nextCRC; + reg write_d; + + oneshot_2clk rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk)); + + /* + ss_rcvr #(.WIDTH(18)) ss_rcvr + (.rxclk(ser_rx_clk),.sysclk(clk),.rst(rst), + .data_in({ser_rkmsb,ser_rklsb,ser_r}),.data_out(even_data), + .clock_present()); + */ + assign even_data = {ser_rkmsb,ser_rklsb,ser_r}; + + always @(posedge ser_rx_clk) + if(rst_rxclk) + holder <= 9'd0; + else + holder <= {even_data[17],even_data[15:8]}; + + always @(posedge ser_rx_clk) + if(rst_rxclk) + odd_data <= 18'd0; + else + odd_data <= {even_data[16],holder[8],even_data[7:0],holder[7:0]}; + + assign chosen_data = odd ? odd_data : even_data; + + // Transfer xon and xoff info to the main system clock for flow control purposes + reg xon_rcvd_rxclk, xoff_rcvd_rxclk; + always @(posedge ser_rx_clk) + xon_rcvd_rxclk = ({1'b1,K_XON} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XON} == {ser_rklsb,ser_r[7:0]} ); + always @(posedge ser_rx_clk) + xoff_rcvd_rxclk = ({1'b1,K_XOFF} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XOFF} == {ser_rklsb,ser_r[7:0]} ); + + oneshot_2clk xon_1s(.clk_in(ser_rx_clk),.in(xon_rcvd_rxclk),.clk_out(clk),.out(xon_rcvd)); + oneshot_2clk xoff_1s(.clk_in(ser_rx_clk),.in(xoff_rcvd_rxclk),.clk_out(clk),.out(xoff_rcvd)); + + // If the other side is sending xon or xoff, or is flow controlled (b/c we told them to be), don't fill the fifos + wire wait_here = ((chosen_data == {2'b10,K_COMMA,D_56})|| + (chosen_data == {2'b11,K_XON,K_XON})|| + (chosen_data == {2'b11,K_XOFF,K_XOFF}) ); + + always @(posedge ser_rx_clk) + if(rst_rxclk) sop_i <= 0; + else if(state == FIRSTLINE1) sop_i <= 1; + else if(write_d) sop_i <= 0; + + reg write_pre; + always @(posedge ser_rx_clk) + if(rst_rxclk) + begin + state <= IDLE; + odd <= 0; + halfline <= 0; + line_i <= 0; + eop_i <= 0; + error_i <= 0; + write_pre <= 0; + end + else + case(state) + IDLE : + begin + error_i <= 0; + write_pre <= 0; + if(even_data == {2'b11,K_PKT_START,K_PKT_START}) + begin + state <= FIRSTLINE1; + odd <= 0; + end + else if(odd_data == {2'b11,K_PKT_START,K_PKT_START}) + begin + state <= FIRSTLINE1; + odd <= 1; + end + end + + FIRSTLINE1 : + if(chosen_data[17:16] == 0) + begin + halfline <= chosen_data[15:0]; + state <= FIRSTLINE2; + end + else if(wait_here) + ; // Flow Controlled, so wait here and do nothing + else + state <= ERROR; + + FIRSTLINE2 : + if(chosen_data[17:16] == 0) + begin + line_i <= {chosen_data[15:0],halfline}; + if(full) // No space to write to! Should have been avoided by flow control + state <= ERROR; + else + begin + state <= PKT1; + write_pre <= 1; + end + end // if (chosen_data[17:16] == 0) + else if(wait_here) + ; // Flow Controlled, so wait here and do nothing + else + state <= ERROR; + + PKT1 : + begin + write_pre <= 0; + if(chosen_data[17:16] == 0) + begin + halfline <= chosen_data[15:0]; + state <= PKT2; + end + else if(wait_here) + ; // Flow Controlled + else if(chosen_data == {2'b11,K_PKT_END,K_PKT_END}) + state <= CRC_CHECK; + else + state <= ERROR; + end // case: PKT1 + + PKT2 : + if(chosen_data[17:16] == 0) + begin + line_i <= {1'b0,1'b0,1'b0,chosen_data[15:0],halfline}; + if(full) // No space to write to! + state <= ERROR; + else + begin + state <= PKT1; + write_pre <= 1; + end + end // if (chosen_data[17:16] == 0) + else if(wait_here) + ; // Flow Controlled + else + state <= ERROR; + + CRC_CHECK : + if(chosen_data[17:0] == {2'b00,CRC}) + begin + if(full) + state <= ERROR; + else + begin + eop_i <= 1; + state <= DONE; + end + end + else if(wait_here) + ; + else + state <= ERROR; + + ERROR : + begin + error_i <= 1; + if(~full) + state <= IDLE; + end + DONE : + begin + state <= IDLE; + eop_i <= 0; + end + + endcase // case(state) + + + always @(posedge ser_rx_clk) + if(rst_rxclk) + CRC <= 16'hFFFF; + else if(state == IDLE) + CRC <= 16'hFFFF; + else if(chosen_data[17:16] == 2'b00) + CRC <= nextCRC; + + CRC16_D16 crc_blk(chosen_data[15:0],CRC,nextCRC); + + always @(posedge ser_rx_clk) + if(rst_rxclk) write_d <= 0; + else write_d <= write_pre; + + // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes + assign write = eop_i | (error_i & ~full) | (write_d & (state != CRC_CHECK)); + + +//`define CASC 1 +`define MYFIFO 1 +//`define XILFIFO 1 + +`ifdef CASC + cascadefifo2 #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo + (.clk(clk),.rst(rst),.clear(0), + .datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full), + .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty), + .space(fifo_space),.occupied(fifo_occupied) ); + assign fifo_full = full; + assign fifo_empty = empty; +`endif + +`ifdef MYFIFO + wire [FIFOSIZE-1:0] level; + fifo_2clock_casc #(.DWIDTH(35),.AWIDTH(FIFOSIZE)) serdes_rx_fifo + (.arst(rst), + .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full), + .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty), + .level_rclk(level) ); + assign fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - + {{(16-FIFOSIZE){1'b0}},level}; + assign fifo_occupied = { {(16-FIFOSIZE){1'b0}} ,level}; + assign fifo_full = full; // Note -- fifo_full is in the wrong clock domain + assign fifo_empty = empty; +`endif + +`ifdef XILFIFO + wire [FIFOSIZE-1:0] level; + fifo_generator_v4_1 ser_rx_fifo + (.din({error_i,sop_i,eop_i,line_i}), + .rd_clk(clk), + .rd_en(read), + .rst(rst), + .wr_clk(ser_rx_clk), + .wr_en(write), + .dout({error_o,sop_o,eop_o,line_o}), + .empty(empty), + .full(full), + .rd_data_count(level), + .wr_data_count() ); + assign fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} - + {{(16-FIFOSIZE){1'b0}},level}; + assign fifo_occupied = { {(16-FIFOSIZE){1'b0}}, level }; + assign fifo_full = full; // Note -- fifo_full is in the wrong clock domain + assign fifo_empty = empty; +`endif // `ifdef XILFIFO + + + // Internal FIFO to Buffer interface + reg xfer_active; + + always @(posedge clk) + if(rst) + xfer_active <= 0; + else if(xfer_active & ~empty & (eop_o | wr_full_i | error_o)) + xfer_active <= 0; + else if(wr_ready_i & sop_o) + xfer_active <= 1; + + assign read = (xfer_active | ~sop_o) & ~empty; + + assign wr_write_o = xfer_active & ~empty; + assign wr_done_o = eop_o & ~empty & xfer_active; + //assign wr_error_o = xfer_active & ((wr_full_i & ~eop_o & ~empty)|error_o); + assign wr_error_o = xfer_active & ~empty & error_o; + + assign wr_dat_o = line_o; + + /* + assign debug = { { fifo_space[15:8] }, + { fifo_space[7:0] }, + { 2'd0, error_i, sop_i, eop_i, error_o, sop_o, eop_o }, + { full, empty, write, read, xfer_active, state[2:0] } }; + + assign debug = { { xoff_rcvd,xon_rcvd,sop_i,eop_i,error_i,state[2:0] }, + { odd, wait_here, write_pre, write_d, write, full, chosen_data[17:16]}, + { chosen_data[15:8] }, + { chosen_data[7:0] } }; + */ + + assign debug = { full, empty, odd, xfer_active, sop_i, eop_i, error_i, state[2:0] }; + +endmodule // serdes_rx diff --git a/usrp2/fpga/serdes/serdes_tb.v b/usrp2/fpga/serdes/serdes_tb.v new file mode 100644 index 00000000..eb8e019f --- /dev/null +++ b/usrp2/fpga/serdes/serdes_tb.v @@ -0,0 +1,328 @@ + +// FIXME need to add flow control + +module serdes_tb(); + + reg clk, rst; + wire ser_rx_clk, ser_tx_clk; + wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb; + wire [15:0] ser_r, ser_t; + + initial clk = 0; + initial rst = 1; + initial #1000 rst = 0; + always #100 clk = ~clk; + + // Wishbone + reg [31:0] wb_dat_i; + wire [31:0] wb_dat_o_rx, wb_dat_o_tx; + reg wb_we, wb_en_rx, wb_en_tx; + reg [8:0] wb_adr; + + // Buffer Control + reg go, clear, read, write; + reg [3:0] buf_num; + wire [31:0] ctrl_word = {buf_num,3'b0,clear,write,read,step,lastline,firstline}; + reg [8:0] firstline = 0, lastline = 0; + reg [3:0] step = 1; + reg first_tx = 1, first_rx = 1; // for verif + + // TX Side + reg wb_we_tx; + wire en_tx, we_tx; + wire [8:0] addr_tx; + wire [31:0] f2r_tx, r2f_tx; + wire [31:0] data_tx; + wire read_tx, done_tx, error_tx, sop_tx, eop_tx; + + wire fdone_tx, ferror_tx; + + reg even; + reg channel_error = 0; + + serdes_tx serdes_tx + (.clk(clk),.rst(rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(data_tx),.rd_read_o(read_tx),.rd_done_o(done_tx), + .rd_error_o(error_tx),.rd_sop_i(sop_tx),.rd_eop_i(eop_tx) ); + + ram_2port #(.DWIDTH(32),.AWIDTH(9)) + ram_tx(.clka(clk),.ena(wb_en_tx),.wea(wb_we_tx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_tx), + .clkb(clk),.enb(en_tx),.web(we_tx),.addrb(addr_tx),.dib(f2r_tx),.dob(r2f_tx)); + + buffer_int #(.BUFF_NUM(1)) buffer_int_tx + (.clk(clk),.rst(rst), + .ctrl_word(ctrl_word),.go(go), + .done(fdone_tx),.error(ferror_tx), + + .en_o(en_tx),.we_o(we_tx),.addr_o(addr_tx),.dat_to_buf(f2r_tx),.dat_from_buf(r2f_tx), + + .wr_dat_i(0),.wr_write_i(0),.wr_done_i(0), + .wr_error_i(0),.wr_ready_o(),.wr_full_o(), + + .rd_dat_o(data_tx),.rd_read_i(read_tx),.rd_done_i(done_tx), + .rd_error_i(error_tx),.rd_sop_o(sop_tx),.rd_eop_o(eop_tx) ); + + + // RX Side + reg wb_we_rx; + wire en_rx, we_rx; + wire [8:0] addr_rx; + wire [31:0] f2r_rx, r2f_rx; + wire [31:0] data_rx; + wire write_rx, done_rx, error_rx, ready_rx, empty_rx; + + wire fdone_rx, ferror_rx; + + serdes_rx serdes_rx + (.clk(clk),.rst(rst), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(data_rx),.wr_write_o(write_rx),.wr_done_o(done_rx), + .wr_error_o(error_rx),.wr_ready_i(ready_rx),.wr_full_i(full_rx) ); + + ram_2port #(.DWIDTH(32),.AWIDTH(9)) + ram_rx(.clka(clk),.ena(wb_en_rx),.wea(wb_we_rx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_rx), + .clkb(clk),.enb(en_rx),.web(we_rx),.addrb(addr_rx),.dib(f2r_rx),.dob(r2f_rx) ); + + buffer_int #(.BUFF_NUM(0)) buffer_int_rx + (.clk(clk),.rst(rst), + .ctrl_word(ctrl_word),.go(go), + .done(fdone_rx),.error(ferror_rx), + + .en_o(en_rx),.we_o(we_rx),.addr_o(addr_rx),.dat_to_buf(f2r_rx),.dat_from_buf(r2f_rx), + + .wr_dat_i(data_rx),.wr_write_i(write_rx),.wr_done_i(done_rx), + .wr_error_i(error_rx),.wr_ready_o(ready_rx),.wr_full_o(full_rx), + + .rd_dat_o(),.rd_read_i(0),.rd_done_i(0), + .rd_error_i(0),.rd_sop_o(),.rd_eop_o() ); + + // Simulate the connection + serdes_model serdes_model + (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), + .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), + .even(even), .error(channel_error) ); + + initial begin + wb_en_rx <= 0; + wb_en_tx <=0; + wb_we_tx <= 0; + wb_we_rx <= 0; + wb_adr <= 0; + wb_dat_i <= 0; + go <= 0; + even <= 0; + @(negedge rst); + @(posedge clk); + FillTXRAM; + ClearRXRAM; + ResetBuffer(0); + ResetBuffer(1); + + // receive a full buffer + ReceiveSERDES(0,10); + SendSERDES(0,10); + + // Receive a partial buffer + SendSERDES(11,20); + ReceiveSERDES(11,50); + + // Receive too many for buffer + SendSERDES(21,100); + ReceiveSERDES(21,30); + + // Send 3 packets, then wait to receive them, so they stack up in the rx fifo + SendSERDES(31,40); + SendSERDES(41,50); + SendSERDES(51,60); + repeat (10) + @(posedge clk); + ReceiveSERDES(31,40); + ReceiveSERDES(41,50); + repeat (1000) + @(posedge clk); + ReceiveSERDES(51,60); + + // Overfill the FIFO, should get an error on 3rd packet + SendSERDES(1,400); + SendSERDES(1,400); + + + WaitForTX; + //WaitForRX; + + + repeat(1000) + @(posedge clk); + ReceiveSERDES(101,500); + ReceiveSERDES(101,500); + ReadRAM(80); + $finish; + end // initial begin + + always @(posedge clk) + if(write_rx) + $display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO FULL %d",data_rx, ready_rx, full_rx); + + always @(posedge clk) + if(read_tx) + $display("SERDES TX, FIFO READ %x, SOP %d, EOP %d",data_tx, sop_tx, eop_tx); + + initial begin + $dumpfile("serdes_tb.vcd"); + $dumpvars(0,serdes_tb); + end + + initial #10000000 $finish; + + initial #259300 channel_error <= 1; + initial #259500 channel_error <= 0; + + task FillTXRAM; + begin + wb_adr <= 0; + wb_dat_i <= 32'h10802000; + wb_we_tx <= 1; + wb_en_tx <= 1; + @(posedge clk); + repeat(511) begin + wb_dat_i <= wb_dat_i + 32'h00010001; + wb_adr <= wb_adr + 1; + @(posedge clk); + end // repeat (511) + wb_we_tx <= 0; + wb_en_tx <= 0; + @(posedge clk); + $display("Done entering Data into TX RAM\n"); + end + endtask // FillTXRAM + + task ClearRXRAM; + begin + wb_adr <= 0; + wb_dat_i <= 0; + wb_we_rx <= 1; + wb_en_rx <= 1; + wb_dat_i <= 0; + @(posedge clk); + repeat(511) begin + wb_adr <= wb_adr + 1; + @(posedge clk); + end // repeat (511) + wb_we_rx <= 0; + wb_en_rx <= 0; + @(posedge clk); + $display("Done clearing RX RAM\n"); + end + endtask // FillRAM + + task ReadRAM; + input [8:0] lastline; + begin + wb_en_rx <= 1; + wb_adr <= 0; + @(posedge clk); + @(posedge clk); + repeat(lastline) begin + $display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx); + wb_adr <= wb_adr + 1; + @(posedge clk); + @(posedge clk); + end // repeat (511) + $display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx); + wb_en_rx <= 0; + @(posedge clk); + $display("Done reading out RX RAM\n"); + end + endtask // FillRAM + + task ResetBuffer; + input [3:0] buffer_num; + begin + buf_num <= buffer_num; + clear <= 1; read <= 0; write <= 0; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Reset"); + end + endtask // ClearBuffer + + task SetBufferWrite; + input [3:0] buffer_num; + input [8:0] start; + input [8:0] stop; + begin + buf_num <= buffer_num; + clear <= 0; read <= 0; write <= 1; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Write"); + end + endtask // SetBufferWrite + + task SetBufferRead; + input [3:0] buffer_num; + input [8:0] start; + input [8:0] stop; + begin + buf_num <= buffer_num; + clear <= 0; read <= 1; write <= 0; + firstline <= start; + lastline <= stop; + go <= 1; + @(posedge clk); + go <= 0; + @(posedge clk); + $display("Buffer Set for Read"); + end + endtask // SetBufferRead + + task WaitForTX; + begin + while (!(fdone_tx | ferror_tx)) + @(posedge clk); + end + endtask // WaitForTX + + task WaitForRX; + begin + while (!(fdone_rx | ferror_rx)) + @(posedge clk); + end + endtask // WaitForRX + + task SendSERDES; + input [8:0] start; + input [8:0] stop; + begin + if(~first_tx) + WaitForTX; + else + first_tx <= 0; + ResetBuffer(1); + SetBufferRead(1,start,stop); + $display("Here"); + end + endtask // SendSERDES + + task ReceiveSERDES; + input [8:0] start; + input [8:0] stop; + begin + if(~first_rx) + WaitForRX; + else + first_rx <= 0; + ResetBuffer(0); + SetBufferWrite(0,start,stop); + $display("Here2"); + end + endtask // ReceiveSERDES + +endmodule // serdes_tb diff --git a/usrp2/fpga/serdes/serdes_tx.v b/usrp2/fpga/serdes/serdes_tx.v new file mode 100644 index 00000000..fa4abe5d --- /dev/null +++ b/usrp2/fpga/serdes/serdes_tx.v @@ -0,0 +1,199 @@ + +// SERDES Interface + +// LS-Byte is sent first, MS-Byte is second +// Invalid K Codes +// K0.0 000-00000 Error detected +// K31.7 111-11111 Loss of input signal + +// Valid K Codes +// K28.0 000-11100 +// K28.1 001-11100 Alternate COMMA? +// K28.2 010-11100 +// K28.3 011-11100 +// K28.4 100-11100 +// K28.5 101-11100 Standard COMMA? +// K28.6 110-11100 +// K28.7 111-11100 Bad COMMA? +// K23.7 111-10111 +// K27.7 111-11011 +// K29.7 111-11101 +// K30.7 111-11110 + +module serdes_tx + #(parameter FIFOSIZE = 9) + (input clk, + input rst, + + // TX HW Interface + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + // TX Stream Interface + input [31:0] rd_dat_i, + output rd_read_o, + output rd_done_o, + output rd_error_o, + input rd_sop_i, + input rd_eop_i, + + // Flow control interface + input inhibit_tx, + input send_xon, + input send_xoff, + output sent, + + // FIFO Levels + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty, + + // DEBUG + output [31:0] debug + ); + + localparam K_COMMA = 8'b101_11100; // 0xBC K28.5 + localparam K_IDLE = 8'b001_11100; // 0x3C K28.1 + localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6 + localparam K_PKT_END = 8'b100_11100; // 0x9C K28.4 + localparam K_XON = 8'b010_11100; // 0x5C K28.2 + localparam K_XOFF = 8'b011_11100; // 0x7C K28.3 + localparam K_LOS = 8'b111_11111; // 0xFF K31.7 + localparam K_ERROR = 8'b000_00000; // 0x00 K00.0 + localparam D_56 = 8'b110_00101; // 0xC5 D05.6 + assign ser_tx_clk = clk; + + localparam IDLE = 3'd0; + localparam RUN1 = 3'd1; + localparam RUN2 = 3'd2; + localparam DONE = 3'd3; + localparam SENDCRC = 3'd4; + localparam WAIT = 3'd5; + + reg [2:0] state; + + reg [15:0] CRC; + wire [15:0] nextCRC; + reg [3:0] wait_count; + + // Internal FIFO, size 9 is 2K, size 10 is 4K bytes + wire sop_o, eop_o, write, full, read, empty; + wire [31:0] data_o; + reg xfer_active; + + cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo + (.clk(clk),.rst(rst),.clear(0), + .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full), + .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty), + .space(), .occupied(fifo_occupied) ); + assign fifo_full = full; + assign fifo_empty = empty; + + // Buffer interface to internal FIFO + always @(posedge clk) + if(rst) + xfer_active <= 0; + else if(rd_eop_i & ~full) // In case we can't store last line right away + xfer_active <= 0; + else if(rd_sop_i) + xfer_active <= 1; + + assign write = xfer_active & ~full; + + assign rd_read_o = write; + assign rd_done_o = 0; // Always take everything we're given + assign rd_error_o = 0; // No chance for errors anticipated + + + // FIXME Implement flow control + + reg [15:0] second_word; + reg [33:0] pipeline; + + assign read = (~send_xon & ~send_xoff & (state==RUN2)) | ((state==IDLE) & ~empty & ~sop_o); + assign sent = send_xon | send_xoff; + // 2nd half of above probably not necessary. Just in case we get junk between packets + + always @(posedge clk) + if(rst) + begin + state <= IDLE; + wait_count <= 0; + {ser_tkmsb,ser_tklsb,ser_t} <= 18'd0; + //{2'b10,K_COMMA,K_COMMA}; + // make tkmsb and tklsb different so they can go in IOFFs + end + else + if(send_xon) + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XON,K_XON}; + else if(send_xoff) + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XOFF,K_XOFF}; + else + case(state) + IDLE : + begin + if(sop_o & ~empty & ~inhibit_tx) + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_START,K_PKT_START}; + state <= RUN1; + end + else + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; + end + RUN1 : + begin + if(empty | inhibit_tx) + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; + else + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[15:0]}; + state <= RUN2; + end + end + RUN2 : + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[31:16]}; + if(eop_o) + state <= DONE; + else + state <= RUN1; + end + DONE : + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_END,K_PKT_END}; + state <= SENDCRC; + end + SENDCRC : + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,CRC}; + state <= WAIT; + wait_count <= 4'd15; + end + WAIT : + begin + {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56}; + if(wait_count == 0) + state <= IDLE; + else + wait_count <= wait_count - 1; + end + default + state <= IDLE; + endcase // case(state) + + always @(posedge clk) + if(rst) + CRC <= 16'hFFFF; + else if(state == IDLE) + CRC <= 16'hFFFF; + else if( (~empty & ~inhibit_tx & (state==RUN1)) || (state==RUN2) ) + CRC <= nextCRC; + + CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC); + + assign debug = { 26'd0, full, empty, xfer_active, state[2:0] }; + +endmodule // serdes_tx + diff --git a/usrp2/fpga/testbench/BOOTSTRAP.sav b/usrp2/fpga/testbench/BOOTSTRAP.sav new file mode 100644 index 00000000..41501945 --- /dev/null +++ b/usrp2/fpga/testbench/BOOTSTRAP.sav @@ -0,0 +1,82 @@ +[size] 1400 971 +[pos] -1 -1 +*-26.028666 3485926000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +u2_sim_top.cpld_clk +u2_sim_top.cpld_detached +u2_sim_top.cpld_din +u2_sim_top.cpld_done +u2_sim_top.cpld_start +u2_sim_top.aux_clk +u2_sim_top.clk_fpga +u2_sim_top.clk_sel[1:0] +u2_sim_top.clk_en[1:0] +u2_sim_top.u2_basic.ram_loader_rst +u2_sim_top.u2_basic.wb_rst +u2_sim_top.u2_basic.sysctrl.POR +u2_sim_top.u2_basic.sysctrl.ram_loader_done_i +u2_sim_top.cpld_model.sclk +u2_sim_top.cpld_model.start +u2_sim_top.u2_basic.ram_loader.rst_i +u2_sim_top.sen_clk +u2_sim_top.sen_dac +u2_sim_top.sclk +@22 +u2_sim_top.u2_basic.shared_spi.wb_sel_i[3:0] +u2_sim_top.u2_basic.shared_spi.wb_adr_i[4:0] +u2_sim_top.u2_basic.shared_spi.wb_dat_i[31:0] +@28 +u2_sim_top.u2_basic.shared_spi.wb_we_i +u2_sim_top.u2_basic.shared_spi.wb_stb_i +u2_sim_top.u2_basic.shared_spi.wb_ack_o +@22 +u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] +u2_sim_top.u2_basic.shared_spi.ctrl[13:0] +u2_sim_top.u2_basic.shared_spi.divider[15:0] +u2_sim_top.u2_basic.shared_spi.char_len[6:0] +u2_sim_top.u2_basic.shared_spi.ss[7:0] +u2_sim_top.u2_basic.shared_spi.wb_dat_o[31:0] +u2_sim_top.u2_basic.shared_spi.rx[127:0] +@28 +u2_sim_top.u2_basic.control_lines.wb_stb_i +u2_sim_top.u2_basic.control_lines.wb_we_i +@22 +u2_sim_top.u2_basic.control_lines.wb_dat_i[31:0] +u2_sim_top.u2_basic.control_lines.wb_dat_o[31:0] +u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] +@28 +u2_sim_top.u2_basic.control_lines.wb_cyc_i +@22 +u2_sim_top.u2_basic.control_lines.wb_sel_i[3:0] +@28 +u2_sim_top.clock_ready +u2_sim_top.u2_basic.ram_loader.done_o +u2_sim_top.u2_basic.dsp_rst +u2_sim_top.u2_basic.ram_loader_rst +u2_sim_top.u2_basic.wb_rst +@22 +u2_sim_top.u2_basic.ID_ram.dwb_adr_i[12:0] +@28 +u2_sim_top.u2_basic.aeMB.iwb_ack_i +u2_sim_top.u2_basic.ram_loader_done +@22 +u2_sim_top.u2_basic.iram_rd_adr[15:0] +u2_sim_top.u2_basic.iram_rd_dat[31:0] +@28 +u2_sim_top.u2_basic.iram_wr_we +u2_sim_top.u2_basic.iram_wr_stb +@22 +u2_sim_top.u2_basic.iram_wr_sel[3:0] +u2_sim_top.u2_basic.iram_wr_dat[31:0] +u2_sim_top.u2_basic.iram_wr_adr[15:0] +@28 +u2_sim_top.u2_basic.ram_loader.ram_loader_done_o +u2_sim_top.u2_basic.ID_ram.dwb_we_i +u2_sim_top.u2_basic.ID_ram.iwb_we_i +u2_sim_top.u2_basic.ram_loader.ram_we +u2_sim_top.u2_basic.ram_loader.ram_we_q +u2_sim_top.u2_basic.ram_loader.ram_we_s +u2_sim_top.u2_basic.ram_loader.wb_ack_i +u2_sim_top.u2_basic.ID_ram.iwb_ack_o +u2_sim_top.u2_basic.ID_ram.iwb_stb_i +u2_sim_top.u2_basic.ID_ram.wb_rst_i diff --git a/usrp2/fpga/testbench/Makefile b/usrp2/fpga/testbench/Makefile new file mode 100644 index 00000000..6032a012 --- /dev/null +++ b/usrp2/fpga/testbench/Makefile @@ -0,0 +1,10 @@ +all: single dual + +single: + iverilog -Wimplicit -Wportbind -c cmdfile ../top/single_u2_sim/single_u2_sim.v -o single_u2_sim + +dual: + iverilog -Wimplicit -Wportbind -c cmdfile ../top/dual_u2_sim/dual_u2_sim.v -o dual_u2_sim + +clean: + rm -f single_u2_sim dual_u2_sim *.vcd *.lxt diff --git a/usrp2/fpga/testbench/PAUSE.sav b/usrp2/fpga/testbench/PAUSE.sav new file mode 100644 index 00000000..f5e1ea1a --- /dev/null +++ b/usrp2/fpga/testbench/PAUSE.sav @@ -0,0 +1,62 @@ +[size] 1400 967 +[pos] -1 -1 +*-16.314999 5250420000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] u2_sim_top. +[treeopen] u2_sim_top.u2_basic. +[treeopen] u2_sim_top.u2_basic.MAC_top. +[treeopen] u2_sim_top.u2_basic.MAC_top.U_MAC_tx. +@22 +u2_sim_top.GMII_TXD[7:0] +@28 +u2_sim_top.GMII_TX_EN +@200 +- +@24 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_hwmark[15:0] +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.fc_lwmark[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_frame_send_en +@22 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.pause_quanta_set[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rst +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_clk +@24 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.rx_fifo_space[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.tx_clk +@200 +- +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_gen_complete +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xoff_int_d1 +@200 +- +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_gen_complete +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.xon_int_d1 +@200 +- +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_apply +@22 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta[15:0] +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] +@28 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_sub +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_val +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d1 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pqval_d2 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.rst +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_clk +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.tx_pause_en +u2_sim_top.u2_basic.proc_int +@22 +u2_sim_top.u2_basic.MAC_top.flow_ctrl_rx.countdown[21:0] +u2_sim_top.u2_basic.MAC_top.flow_ctrl_tx.pause_quanta_counter[15:0] +@25 +u2_sim_top.u2_basic.MAC_top.U_MAC_tx.U_MAC_tx_ctrl.Current_state[3:0] diff --git a/usrp2/fpga/testbench/README b/usrp2/fpga/testbench/README new file mode 100644 index 00000000..14bbb68b --- /dev/null +++ b/usrp2/fpga/testbench/README @@ -0,0 +1,5 @@ +The path to happiness: + +make clean +make +./u2_sim +rom=../../firmware/eth_test.rom -lxt2 diff --git a/usrp2/fpga/testbench/SERDES.sav b/usrp2/fpga/testbench/SERDES.sav new file mode 100644 index 00000000..3bb6ba92 --- /dev/null +++ b/usrp2/fpga/testbench/SERDES.sav @@ -0,0 +1,35 @@ +[size] 1400 967 +[pos] -1 -1 +*-30.885946 6591910000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] u2_sim_top. +[treeopen] u2_sim_top.u2_basic. +[treeopen] u2_sim_top.u2_basic.serdes. +@22 +u2_sim_top.u2_basic.serdes.ser_t[15:0] +@28 +u2_sim_top.u2_basic.serdes.ser_tklsb +u2_sim_top.u2_basic.serdes.ser_tkmsb +u2_sim_top.u2_basic.ram_loader.ram_loader_done_o +u2_sim_top.u2_basic.proc_int +@22 +u2_sim_top.u2_basic.serdes.fifo_space[15:0] +@28 +u2_sim_top.u2_basic.serdes.inhibit_tx +u2_sim_top.u2_basic.serdes.send_xoff +u2_sim_top.u2_basic.serdes.send_xon +u2_sim_top.u2_basic.serdes.sent +u2_sim_top.u2_basic.serdes.xoff_rcvd +u2_sim_top.u2_basic.serdes.xon_rcvd +u2_sim_top.u2_basic.serdes.serdes_rx.wr_write_o +u2_sim_top.u2_basic.serdes.serdes_rx.wr_done_o +u2_sim_top.u2_basic.serdes.serdes_rx.write +@22 +u2_sim_top.u2_basic.serdes.serdes_rx.line_i[31:0] +@28 +(0)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] +(1)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] +@22 +#chosen_data[15:0] (2)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (3)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (4)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (5)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (6)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (7)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (8)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (9)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (10)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (11)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (12)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (13)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (14)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (15)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (16)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] (17)u2_sim_top.u2_basic.serdes.serdes_rx.chosen_data[17:0] +u2_sim_top.u2_basic.serdes.ser_t[15:0] +@28 +u2_sim_top.u2_basic.serdes.ser_tklsb diff --git a/usrp2/fpga/testbench/U2_SIM.sav b/usrp2/fpga/testbench/U2_SIM.sav new file mode 100644 index 00000000..d320c2b6 --- /dev/null +++ b/usrp2/fpga/testbench/U2_SIM.sav @@ -0,0 +1,95 @@ +[size] 1400 971 +[pos] -1 -1 +*-18.079937 3641000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +u2_sim_top.adc_oen_a +u2_sim_top.adc_oen_b +u2_sim_top.adc_pdn_a +u2_sim_top.adc_pdn_b +u2_sim_top.aux_clk +u2_sim_top.POR +u2_sim_top.clk_fpga +u2_sim_top.clk_en[1:0] +u2_sim_top.clk_sel[1:0] +u2_sim_top.led1 +u2_sim_top.led2 +u2_sim_top.sclk +u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.gnt[2:0] +u2_sim_top.sda_pad_o +u2_sim_top.sda_pad_oen_o +u2_sim_top.sdi +u2_sim_top.sdo +u2_sim_top.sen_clk +u2_sim_top.sen_dac +u2_sim_top.ser_enable +u2_sim_top.ser_loopen +u2_sim_top.ser_prbsen +u2_sim_top.ser_rx_en +u2_sim_top.u2_basic.sysctrl.start +u2_sim_top.u2_basic.sysctrl.POR +u2_sim_top.u2_basic.done +u2_sim_top.u2_basic.sysctrl.POR +u2_sim_top.u2_basic.sysctrl.aux_clk +u2_sim_top.u2_basic.sysctrl.clk_fpga +u2_sim_top.u2_basic.sysctrl.done +u2_sim_top.u2_basic.bus_writer.start +u2_sim_top.u2_basic.bus_writer.done +@22 +u2_sim_top.u2_basic.bus_writer.rom_addr[15:0] +u2_sim_top.u2_basic.bus_writer.rom_data[47:0] +u2_sim_top.u2_basic.bus_writer.state[3:0] +@29 +u2_sim_top.u2_basic.bus_writer.wb_ack_i +@22 +u2_sim_top.u2_basic.bus_writer.wb_adr_o[15:0] +@28 +u2_sim_top.u2_basic.bus_writer.wb_clk_i +u2_sim_top.u2_basic.bus_writer.wb_cyc_o +@22 +u2_sim_top.u2_basic.bus_writer.wb_dat_o[31:0] +u2_sim_top.u2_basic.bus_writer.wb_sel_o[3:0] +@28 +u2_sim_top.u2_basic.bus_writer.wb_stb_o +u2_sim_top.u2_basic.bus_writer.wb_we_o +u2_sim_top.u2_basic.bus_writer.wb_rst_i +u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.req[7:0] +u2_sim_top.sda_pad_i +u2_sim_top.u2_basic.wb_conbus_top.m0_cyc_i +u2_sim_top.u2_basic.wb_conbus_top.s0_cyc_o +@22 +u2_sim_top.u2_basic.wb_conbus_top.m0_adr_i[15:0] +u2_sim_top.u2_basic.wb_conbus_top.m1_adr_i[15:0] +@28 +u2_sim_top.u2_basic.wb_conbus_top.m0_stb_i +u2_sim_top.u2_basic.wb_conbus_top.m1_stb_i +u2_sim_top.u2_basic.wb_conbus_top.s0_stb_o +u2_sim_top.u2_basic.wb_conbus_top.s1_stb_o +u2_sim_top.u2_basic.wb_conbus_top.s2_stb_o +u2_sim_top.u2_basic.wb_conbus_top.s3_stb_o +u2_sim_top.u2_basic.wb_conbus_top.s0_ack_i +u2_sim_top.u2_basic.control_lines.wb_cyc_i +u2_sim_top.u2_basic.control_lines.wb_stb_i +u2_sim_top.u2_basic.control_lines.wb_we_i +u2_sim_top.u2_basic.control_lines.wb_ack_o +u2_sim_top.u2_basic.s0_ack +@22 +u2_sim_top.u2_basic.control_lines.internal_reg[31:0] +u2_sim_top.u2_basic.control_lines.port_output[31:0] +@28 +u2_sim_top.u2_basic.led1 +u2_sim_top.u2_basic.led2 +@22 +u2_sim_top.u2_basic.misc_outs[7:0] +u2_sim_top.u2_basic.clock_outs[7:0] +u2_sim_top.u2_basic.adc_outs[7:0] +u2_sim_top.u2_basic.serdes_outs[7:0] +@28 +u2_sim_top.u2_basic.shared_spi.miso_pad_i +u2_sim_top.u2_basic.shared_spi.mosi_pad_o +@22 +u2_sim_top.u2_basic.shared_spi.ss[7:0] +u2_sim_top.u2_basic.shared_spi.divider[15:0] +@28 +u2_sim_top.u2_basic.shared_spi.sclk_pad_o +@22 +u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0] diff --git a/usrp2/fpga/testbench/cmdfile b/usrp2/fpga/testbench/cmdfile new file mode 100644 index 00000000..d55567f7 --- /dev/null +++ b/usrp2/fpga/testbench/cmdfile @@ -0,0 +1,39 @@ + +# My stuff +-y . +-y ../top/u2_core +-y ../control_lib +-y ../serdes +-y ../sdr_lib +-y ../timing +-y ../coregen + +# Models +-y ../models +-y ../models/CY7C1356C + +# Open Cores +-y ../opencores/8b10b +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/wb_conbus/rtl/verilog ++incdir+../opencores/wb_conbus/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog +-y ../opencores/aemb/rtl/verilog +-y ../opencores/simple_pic/rtl + +# Ethernet ++incdir+../eth/rtl/verilog +-y ../eth/rtl/verilog +-y ../eth/rtl/verilog/MAC_tx +-y ../eth/rtl/verilog/MAC_rx +-y ../eth/rtl/verilog/miim +-y ../eth/rtl/verilog/TECH +-y ../eth/rtl/verilog/TECH/xilinx +-y ../eth/rtl/verilog/RMON +-y ../eth +-y ../eth/bench/verilog + +# Ethernet Models +-y ../eth/bench/verilog diff --git a/usrp2/fpga/timing/time_receiver.v b/usrp2/fpga/timing/time_receiver.v new file mode 100644 index 00000000..8e7d3f1e --- /dev/null +++ b/usrp2/fpga/timing/time_receiver.v @@ -0,0 +1,94 @@ + +module time_receiver + (input clk, input rst, + output [31:0] master_time, + output sync_rcvd, + input exp_pps_in); + + wire code_err, disp_err, dispout, complete_word; + reg disp_reg; + reg [9:0] shiftreg; + reg [3:0] bit_count; + wire [8:0] dataout; + reg [8:0] dataout_reg; + + always @(posedge clk) + shiftreg <= {exp_pps_in, shiftreg[9:1]}; + + localparam COMMA_0 = 10'h283; + localparam COMMA_1 = 10'h17c; + + wire found_comma = (shiftreg == COMMA_0) | (shiftreg == COMMA_1); + wire set_disp = (shiftreg == COMMA_1); + + always @(posedge clk) + if(rst) + bit_count <= 0; + else if(found_comma | complete_word) + bit_count <= 0; + else + bit_count <= bit_count + 1; + assign complete_word = (bit_count == 9); + + always @(posedge clk) + if(set_disp) + disp_reg <= 1; + else if(complete_word) + disp_reg <= dispout; + + always @(posedge clk) + if(complete_word) + dataout_reg <= dataout; + + decode_8b10b decode_8b10b + (.datain(shiftreg),.dispin(disp_reg), + .dataout(dataout),.dispout(dispout), + .code_err(code_err),.disp_err(disp_err) ); + + reg error; + always @(posedge clk) + if(complete_word) + error <= code_err | disp_err; + + localparam STATE_IDLE = 0; + localparam STATE_T0 = 1; + localparam STATE_T1 = 2; + localparam STATE_T2 = 3; + localparam STATE_T3 = 4; + + localparam HEAD = 9'h13c; + + reg [7:0] clock_a, clock_b, clock_c; + reg [2:0] state; + + always @(posedge clk) + if(rst) + state <= STATE_IDLE; + else if(complete_word) + case(state) + STATE_IDLE : + if(dataout_reg == HEAD) + state <= STATE_T0; + STATE_T0 : + begin + clock_a <= dataout_reg[7:0]; + state <= STATE_T1; + end + STATE_T1 : + begin + clock_b <= dataout_reg[7:0]; + state <= STATE_T2; + end + STATE_T2 : + begin + clock_c <= dataout_reg[7:0]; + state <= STATE_T3; + end + STATE_T3 : + state <= STATE_IDLE; + endcase // case(state) + + assign master_time = {clock_a, clock_b, clock_c, dataout_reg[7:0]}; + assign sync_rcvd = (complete_word & (state == STATE_T3)); + +endmodule // time_sender diff --git a/usrp2/fpga/timing/time_sender.v b/usrp2/fpga/timing/time_sender.v new file mode 100644 index 00000000..aa2fcbbd --- /dev/null +++ b/usrp2/fpga/timing/time_sender.v @@ -0,0 +1,110 @@ + + +module time_sender + (input clk, input rst, + input [31:0] master_time, + input send_sync, + output exp_pps_out); + + reg [7:0] datain; + reg k; + wire [9:0] dataout; + reg [9:0] dataout_reg; + reg disp_reg; + wire disp, new_word; + + encode_8b10b encode_8b10b + (.datain({k,datain}),.dispin(disp_reg), + .dataout(dataout),.dispout(disp)); + + assign exp_pps_out = dataout_reg[0]; + + always @(posedge clk) + if(rst) + disp_reg <= 0; + else if(new_word) + disp_reg <= disp; + + always @(posedge clk) + if(rst) + dataout_reg <= 0; + else if(new_word) + dataout_reg <= dataout; + else + dataout_reg <= {1'b0,dataout_reg[9:1]}; + + reg [4:0] state; + reg [3:0] bit_count; + + assign new_word = (bit_count == 9); + + always @(posedge clk) + if(rst) + bit_count <= 0; + else if(new_word | send_sync) + bit_count <= 0; + else + bit_count <= bit_count + 1; + + localparam SEND_IDLE = 0; + localparam SEND_HEAD = 1; + localparam SEND_T0 = 2; + localparam SEND_T1 = 3; + localparam SEND_T2 = 4; + localparam SEND_T3 = 5; + + localparam COMMA = 8'hBC; + localparam HEAD = 8'h3C; + + reg [31:0] master_time_reg; + + always @(posedge clk) + if(rst) + master_time_reg <= 0; + else if(send_sync) + master_time_reg <= master_time; + + always @(posedge clk) + if(rst) + begin + {k,datain} <= 0; + state <= SEND_IDLE; + end + else + if(send_sync) + state <= SEND_HEAD; + else if(new_word) + case(state) + SEND_IDLE : + {k,datain} <= {1'b1,COMMA}; + SEND_HEAD : + begin + {k,datain} <= {1'b1, HEAD}; + state <= SEND_T0; + end + SEND_T0 : + begin + {k,datain} <= {1'b0, master_time_reg[31:24] }; + state <= SEND_T1; + end + SEND_T1 : + begin + {k,datain} <= {1'b0, master_time_reg[23:16]}; + state <= SEND_T2; + end + SEND_T2 : + begin + {k,datain} <= {1'b0, master_time_reg[15:8]}; + state <= SEND_T3; + end + SEND_T3 : + begin + {k,datain} <= {1'b0, master_time_reg[7:0]}; + state <= SEND_IDLE; + end + default : + state <= SEND_IDLE; + endcase // case(state) + + +endmodule // time_sender diff --git a/usrp2/fpga/timing/time_sync.v b/usrp2/fpga/timing/time_sync.v new file mode 100644 index 00000000..990674c6 --- /dev/null +++ b/usrp2/fpga/timing/time_sync.v @@ -0,0 +1,110 @@ + + +module time_sync + (input wb_clk_i, input rst_i, + input cyc_i, input stb_i, input [2:0] adr_i, + input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o, + input sys_clk_i, output [31:0] master_time_o, + input pps_in, input exp_pps_in, output exp_pps_out, + output reg int_o ); + + wire [31:0] master_time_rcvd; + reg [31:0] master_time; + reg [31:0] delta_time; + + reg internal_tick; + wire sync_rcvd, pps_ext; + reg [31:0] tick_time, tick_time_wb; + wire tick_free_run; + reg tick_int_enable, tick_source, external_sync; + reg [31:0] tick_interval; + + // Generate master time + always @(posedge sys_clk_i) + if(rst_i) + master_time <= 0; + else if(external_sync & sync_rcvd) + master_time <= master_time_rcvd + delta_time; + else + master_time <= master_time + 1; + assign master_time_o = master_time; + + time_sender time_sender + (.clk(sys_clk_i),.rst(rst_i), + .master_time(master_time), + .send_sync(internal_tick), + .exp_pps_out(exp_pps_out) ); + + time_receiver time_receiver + (.clk(sys_clk_i),.rst(rst_i), + .master_time(master_time_rcvd), + .sync_rcvd(sync_rcvd), + .exp_pps_in(exp_pps_in) ); + + assign ack_o = stb_i; + + always @(posedge wb_clk_i) + if(rst_i) + begin + tick_source <= 0; + tick_int_enable <= 0; + external_sync <= 0; + tick_interval <= 100000-1; // default to 1K times per second + delta_time <= 0; + end + else if(stb_i & we_i) + if(adr_i[2:0] == 2) + delta_time <= dat_i; + else if(adr_i[2:0] == 1) + tick_interval <= dat_i; + else + begin + tick_source <= dat_i[0]; + tick_int_enable <= dat_i[1]; + external_sync <= dat_i[2]; + end + + always @(posedge sys_clk_i) + if(internal_tick) + tick_time <= master_time; + + always @(posedge wb_clk_i) + tick_time_wb <= tick_time; + + assign dat_o = tick_time_wb; + + always @(posedge sys_clk_i) + internal_tick <= (tick_source == 0) ? tick_free_run : pps_ext; + + reg [31:0] counter; + always @(posedge sys_clk_i) + if(rst_i) + counter <= 0; + else if(tick_free_run) + counter <= 0; + else + counter <= counter + 1; + assign tick_free_run = (counter >= tick_interval); + + // Properly Latch and edge detect External PPS input + reg pps_in_d1, pps_in_d2; + always @(posedge sys_clk_i) + begin + pps_in_d1 <= pps_in; + pps_in_d2 <= pps_in_d1; + end + assign pps_ext = pps_in_d1 & ~pps_in_d2; + + // Need to register this? + reg internal_tick_d1; + always @(posedge sys_clk_i) internal_tick_d1 <= internal_tick; + + always @(posedge wb_clk_i) + if(rst_i) + int_o <= 0; + else if(tick_int_enable & (internal_tick | internal_tick_d1)) + int_o <= 1; + else + int_o <= 0; + +endmodule // time_sync diff --git a/usrp2/fpga/timing/time_transfer_tb.v b/usrp2/fpga/timing/time_transfer_tb.v new file mode 100644 index 00000000..2b75c60b --- /dev/null +++ b/usrp2/fpga/timing/time_transfer_tb.v @@ -0,0 +1,50 @@ + +`timescale 1ns / 1ps + +module time_transfer_tb(); + + reg clk = 0, rst = 1; + always #5 clk = ~clk; + + initial + begin + @(negedge clk); + @(negedge clk); + rst <= 0; + end + + initial $dumpfile("time_transfer_tb.vcd"); + initial $dumpvars(0,time_transfer_tb); + + initial #100000000 $finish; + + wire exp_pps, pps, pps_rcv; + wire [31:0] master_clock_rcv; + reg [31:0] master_clock = 0; + reg [31:0] counter = 0; + + localparam PPS_PERIOD = 109; + always @(posedge clk) + if(counter == PPS_PERIOD) + counter <= 0; + else + counter <= counter + 1; + assign pps = (counter == (PPS_PERIOD-1)); + + always @(posedge clk) + master_clock <= master_clock + 1; + + time_sender time_sender + (.clk(clk),.rst(rst), + .master_clock(master_clock), + .pps(pps), + .exp_pps_out(exp_pps) ); + + time_receiver time_receiver + (.clk(clk),.rst(rst), + .master_clock(master_clock_rcv), + .pps(pps_rcv), + .exp_pps_in(exp_pps) ); + + wire [31:0] delta = master_clock - master_clock_rcv; +endmodule // time_transfer_tb diff --git a/usrp2/fpga/timing/timer.v b/usrp2/fpga/timing/timer.v new file mode 100644 index 00000000..70c9746b --- /dev/null +++ b/usrp2/fpga/timing/timer.v @@ -0,0 +1,40 @@ + + +module timer + (input wb_clk_i, input rst_i, + input cyc_i, input stb_i, input [2:0] adr_i, + input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o, + input sys_clk_i, input [31:0] master_time_i, + output int_o ); + + reg [31:0] time_wb; + always @(posedge wb_clk_i) + time_wb <= master_time_i; + + assign ack_o = stb_i; + + reg [31:0] int_time; + reg int_reg; + + always @(posedge sys_clk_i) + if(rst_i) + begin + int_time <= 0; + int_reg <= 0; + end + else if(|int_time && (master_time_i == int_time)) + begin + int_time <= 0; + int_reg <= 1; + end + else if(stb_i & we_i) + begin + int_time <= dat_i; + int_reg <= 0; + end + + assign dat_o = time_wb; + assign int_o = int_reg; + +endmodule // timer + diff --git a/usrp2/fpga/top/eth_test/eth_sim_top.v b/usrp2/fpga/top/eth_test/eth_sim_top.v new file mode 100644 index 00000000..640a4e60 --- /dev/null +++ b/usrp2/fpga/top/eth_test/eth_sim_top.v @@ -0,0 +1,437 @@ +////////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_basic +////////////////////////////////////////////////////////////////////////////////// + +module eth_sim_top + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output led1, + output led2, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + input PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx + ); + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] ser_debug; + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + parameter dw = 32; // Data bus width + parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i; + wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel; + wire m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack; + wire m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb; + wire m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc; + wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err; + wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty; + wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we; + + wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01), + .s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010), + .s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty) + ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + wire iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we; + wire [3:0] iram_wr_sel; + wire [aw-1:0] iram_wr_adr, iram_rd_adr; + wire [dw-1:0] iram_wr_dat, iram_rd_dat; + + wire bus_error, proc_int; + + assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0; + assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack; + + ram_loader #(.AWIDTH(16)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start), + .mode_o(cpld_mode), + .done_o(cpld_done), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr), + .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel), + .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack), + .ram_loader_done_o(ram_loader_done)); + + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr), + .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + assign proc_int = 1'b0; + + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + ram_wb_harvard #(.AWIDTH(14)) + ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat), + .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb), + .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel), + + .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel)); + + assign s0_err = 1'b0; + assign s0_rty = 1'b0; + + // Buffer Pool, slave #1 + wire rd0_read, rd0_ready, rd0_done, rd0_empty; + wire rd1_read, rd1_ready, rd1_done, rd1_empty; + wire rd2_read, rd2_ready, rd2_done, rd2_empty; + wire rd3_read, rd3_ready, rd3_done, rd3_empty; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_write, wr0_done, wr0_ready, wr0_full; + wire wr1_write, wr1_done, wr1_ready, wr1_full; + wire wr2_write, wr2_done, wr2_ready, wr2_full; + wire wr3_write, wr3_done, wr3_ready, wr3_full; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + +/* + buffer_pool buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), + + .stream_clk(dsp_clk),.stream_rst(dsp_rst), + // Write Interfaces + .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(), + .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(), + .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(), + .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(), + // Read Interfaces + .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty), + .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty), + .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty), + .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty) + ); +*/ + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i), + .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack), + + .wb_err_o(s2_err),.wb_int_o(s2_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + assign s2_rty = 1'b0; + + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(st_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_err = 1'b0; + assign s3_rty = 1'b0; + + // GPIOs -- Slave #4 + wire s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d; + assign s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d; + + simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a), + .gpio(/* io_tx[7:0]*/) ); + + simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b), + .gpio(/* io_tx[15:8] */) ); + + simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c), + .gpio(/* io_rx[7:0] */) ); + + simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we), + .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d), + .gpio(/* io_rx[15:8]*/) ); + + assign s4_err = 1'b0; + assign s4_rty = 1'b0; + + // Output control lines, SLAVE #5 + wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0]; + assign {led2, led1} = misc_outs[1:0]; + + wb_output_pins32 control_lines + (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i), + .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc), + .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) ); + + assign s5_err = 1'b0; + assign s5_rty = 1'b0; + + // Ethernet slave, #6 + eth_wrapper eth_wrapper + (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(), + .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode + .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER), + .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL), + .Mdio(MDIO),.Mdc(MDC), + // FIFO Interfaces + .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(), + .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(), + // Wishbone + .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack) + ); + + assign s6_err = 1'b0; + assign s6_rty = 1'b0; + + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_err = 1'b0; + assign s7_rty = 1'b0; + assign s7_dat_i = 32'd0; + + /////////////////////////////////////////////////////////////////////////// + // DSP + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_a; + adc_a_reg2 <= adc_a_reg1; + adc_b_reg1 <= adc_b; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg1 <= adc_ovf_a; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg1 <= adc_ovf_b; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done), + .rx_ready_i(wr1_ready),.rx_full_i(wr1_full), + .overrun() ); + + dsp_core_tx dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .dac_a(dac_a),.dac_b(dac_b), + .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done), + .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty), + .underrun() ); + + assign dsp_rst = wb_rst; + + ///////////////////////////////////////////////////////////////////////////////////// + // SERDES + serdes_tx serdes_tx + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done), + .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty) + ); + + serdes_rx serdes_rx + (.clk(dsp_clk),.rst(dsp_rst), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done) + ); + + // Debug Pins + wire [31:0] debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst}, + {1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached}, + {8'hAF}, + {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}}; + + wire [31:0] debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst}, + {iram_rd_adr[15:8]}, + {iram_rd_adr[7:0]}, + {serdes_outs}}; + + assign io_rx = ser_debug[31:16]; + assign io_tx = ser_debug[15:0]; + + assign debug = debug_wb; + + assign debug_clk[0] = wb_clk; + assign debug_clk[1] = dsp_clk; + +endmodule // eth_test + + +// Local Variables: +// verilog-library-directories:("." "subdir" "subdir2") +// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v") +// verilog-library-extensions:(".v" ".h") +// End: diff --git a/usrp2/fpga/top/eth_test/eth_tb.v b/usrp2/fpga/top/eth_test/eth_tb.v new file mode 100644 index 00000000..451ce1e7 --- /dev/null +++ b/usrp2/fpga/top/eth_test/eth_tb.v @@ -0,0 +1,257 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +// Nearly everything is an input + +module eth_tb(); + // Misc, debug + wire led1; + wire led2; + wire [31:0] debug; + wire [1:0] debug_clk; + + // Expansion + wire exp_pps_in; + wire exp_pps_out; + + // GMII + // GMII-CTRL + wire GMII_COL; + wire GMII_CRS; + + // GMII-TX + wire [7:0] GMII_TXD; + wire GMII_TX_EN; + wire GMII_TX_ER; + wire GMII_GTX_CLK; + wire GMII_TX_CLK; // 100mbps clk + + // GMII-RX + wire [7:0] GMII_RXD; + wire GMII_RX_CLK; + wire GMII_RX_DV; + wire GMII_RX_ER; + + // GMII-Management + wire MDIO; + wire MDC; + wire PHY_INTn; // open drain + wire PHY_RESETn; + wire PHY_CLK; // possibly use on-board osc + + // RAM + wire [17:0] RAM_D; + wire [18:0] RAM_A; + wire RAM_CE1n; + wire RAM_CENn; + wire RAM_CLK; + wire RAM_WEn; + wire RAM_OEn; + wire RAM_LDn; + + // SERDES + wire ser_enable; + wire ser_prbsen; + wire ser_loopen; + wire ser_rx_en; + + wire ser_tx_clk; + wire [15:0] ser_t; + wire ser_tklsb; + wire ser_tkmsb; + + wire ser_rx_clk; + wire [15:0] ser_r; + wire ser_rklsb; + wire ser_rkmsb; + + // CPLD interface + wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; + + // ADC + wire [13:0] adc_a; + wire adc_ovf_a; + wire adc_oen_a; + wire adc_pdn_a; + + wire [13:0] adc_b; + wire adc_ovf_b; + wire adc_oen_b; + wire adc_pdn_b; + + // DAC + wire [15:0] dac_a; + wire [15:0] dac_b; + + // I2C + wire SCL; + wire SDA; + + // Clock Gen Control + wire [1:0] clk_en; + wire [1:0] clk_sel; + wire clk_func; // FIXME is an input to control the 9510 + wire clk_status; + + // Clocks + reg clk_fpga; + wire clk_to_mac; + wire pps_in; + + // Generic SPI + wire sclk, mosi, miso; + wire sen_clk; + wire sen_dac; + wire sen_tx_db; + wire sen_tx_adc; + wire sen_tx_dac; + wire sen_rx_db; + wire sen_rx_adc; + wire sen_rx_dac; + + // GPIO to DBoards + wire [15:0] io_tx; + wire [15:0] io_rx; + + wire wb_clk, wb_rst; + wire start, clock_ready; + + reg aux_clk; + + initial aux_clk= 1'b0; + always #25 aux_clk = ~aux_clk; + + initial clk_fpga = 1'bx; + initial #3007 clk_fpga = 1'b0; + always #7 clk_fpga = ~clk_fpga; + + + wire div_clk; + reg [2:0] div_ctr = 0; + + always @(posedge clk_fpga or negedge clk_fpga) + if(div_ctr==5) + div_ctr = 0; + else + div_ctr = div_ctr + 1; + assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2); + + assign dsp_clk = clk_fpga; + assign wb_clk = clock_ready ? div_clk : aux_clk; + + initial + $monitor($time, ,clock_ready); + + initial begin + $dumpfile("eth_tb.vcd"); + $dumpvars(0,eth_tb); + end + + initial #10000000 $finish; + + cpld_model + cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), + .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); + + eth_sim_top eth_sim_top(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .led1 (led1), + .led2 (led2), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD[7:0]), + .GMII_TX_EN (GMII_TX_EN), + .GMII_TX_ER (GMII_TX_ER), + .GMII_GTX_CLK (GMII_GTX_CLK), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .PHY_CLK (PHY_CLK), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk), + .ser_t (ser_t[15:0]), + .ser_tklsb (ser_tklsb), + .ser_tkmsb (ser_tkmsb), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r[15:0]), + .ser_rklsb (ser_rklsb), + .ser_rkmsb (ser_rkmsb), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_oen_a (adc_oen_a), + .adc_pdn_a (adc_pdn_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_oen_b (adc_oen_b), + .adc_pdn_b (adc_pdn_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0])); + + // Experimental printf-like function + always @(posedge wb_clk) + begin + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000)) + $write("%x",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100)) + $display("%x",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004)) + $write("%c",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104)) + $display("%c",eth_sim_top.m0_dat_i); + if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008)) + $display(""); + end + + +endmodule // u2_sim_top + +// Local Variables: +// verilog-library-directories:("." "subdir" "subdir2") +// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v") +// verilog-library-extensions:(".v" ".h") +// End: diff --git a/usrp2/fpga/top/single_u2_sim/single_u2_sim.v b/usrp2/fpga/top/single_u2_sim/single_u2_sim.v new file mode 100644 index 00000000..4e891d38 --- /dev/null +++ b/usrp2/fpga/top/single_u2_sim/single_u2_sim.v @@ -0,0 +1,322 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module single_u2_sim(); + // Misc, debug + wire [7:0] leds; + wire [31:0] debug; + wire [1:0] debug_clk; + + // Expansion + wire exp_pps_in; + wire exp_pps_out; + + // GMII + // GMII-CTRL + wire GMII_COL; + wire GMII_CRS; + + // GMII-TX + wire [7:0] GMII_TXD; + wire GMII_TX_EN; + wire GMII_TX_ER; + wire GMII_GTX_CLK; + wire GMII_TX_CLK; // 100mbps clk + + // GMII-RX + wire [7:0] GMII_RXD; + wire GMII_RX_CLK; + wire GMII_RX_DV; + wire GMII_RX_ER; + + // GMII-Management + wire MDIO; + wire MDC; + wire PHY_INTn; // open drain + wire PHY_RESETn; + wire PHY_CLK; // possibly use on-board osc + + // RAM + wire [17:0] RAM_D; + wire [18:0] RAM_A; + wire RAM_CE1n; + wire RAM_CENn; + wire RAM_CLK; + wire RAM_WEn; + wire RAM_OEn; + wire RAM_LDn; + + // SERDES + wire ser_enable; + wire ser_prbsen; + wire ser_loopen; + wire ser_rx_en; + + wire ser_tx_clk; + wire [15:0] ser_t; + wire ser_tklsb; + wire ser_tkmsb; + + wire ser_rx_clk; + wire [15:0] ser_r; + wire ser_rklsb; + wire ser_rkmsb; + + // CPLD interface + wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; + + // ADC + wire [13:0] adc_a; + wire adc_ovf_a; + wire adc_on_a, adc_oe_a; + + wire [13:0] adc_b; + wire adc_ovf_b; + wire adc_on_b, adc_oe_b; + + // DAC + wire [15:0] dac_a; + wire [15:0] dac_b; + + // I2C + wire SCL; + wire SDA; + + // Clock Gen Control + wire [1:0] clk_en; + wire [1:0] clk_sel; + wire clk_func; // FIXME is an input to control the 9510 + wire clk_status; + + // Clocks + reg clk_fpga; + reg clk_to_mac; + wire pps_in; + + // Generic SPI + wire sclk, mosi, miso; + wire sen_clk; + wire sen_dac; + wire sen_tx_db; + wire sen_tx_adc; + wire sen_tx_dac; + wire sen_rx_db; + wire sen_rx_adc; + wire sen_rx_dac; + + // GPIO to DBoards + wire [15:0] io_tx; + wire [15:0] io_rx; + + wire wb_clk; + wire start, clock_ready; + + reg aux_clk; + + initial aux_clk= 1'b0; + always #6 aux_clk = ~aux_clk; + + initial clk_fpga = 1'bx; + initial #3007 clk_fpga = 1'b0; + always #5 clk_fpga = ~clk_fpga; + + initial clk_to_mac = 0; + always #4 clk_to_mac = ~clk_to_mac; + + wire div_clk, dsp_clk; + reg [7:0] div_ctr = 0; + + assign dsp_clk = clock_ready ? clk_fpga : aux_clk; + assign wb_clk = div_clk; + +`define CLK_DIV_2 1 +//`define CLK_DIV_3 + +`ifdef CLK_DIV_2 + localparam clock_divider = 4'd2; + always @(posedge dsp_clk) + div_ctr <= div_ctr + 1; + assign div_clk = div_ctr[0]; +`endif + +`ifdef CLK_DIV_3 + localparam clock_divider = 2; + always @(posedge dsp_clk or negedge dsp_clk) + if(div_ctr == 5) + div_ctr <= 0; + else + div_ctr <= div_ctr + 1; + assign div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2)); +`endif + + initial + $monitor($time, ,clock_ready); + + always #1000000 $monitor("Time in ns ",$time); + + initial begin + @(negedge cpld_done); + @(posedge cpld_done); + $dumpfile("single_u2_sim.lxt"); + $dumpvars(0,single_u2_sim); + end + + initial #10000000 $finish; + + cpld_model + cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), + .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); + + serdes_model serdes_model + (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t), + .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r), + .even(0),.error(0) ); + + adc_model adc_model + (.clk(dsp_clk),.rst(0), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a), + .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); + + wire [2:0] speed; + Phy_sim phy_model + (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), + .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), + .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), + .Crs(GMII_CRS), .Col(GMII_COL), + .Speed(speed), .Done(0) ); + pullup p3(MDIO); + + miim_model miim_model + (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK), + .phy_intn_o(PHY_INTn),.speed_o(speed) ); + + xlnx_glbl glbl (.GSR(),.GTS()); + + wire RAM_MODE = 1'b0; + cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A), + .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn), + .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0), + .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) ); + + M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0), + .SDA(SDA),.SCL(SCL),.RESET(0)); + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o; + wire sda_pad_i, sda_pad_o, sda_pad_oen_o; + + pullup p1(SCL); + pullup p2(SDA); + + assign scl_pad_i = SCL; + assign sda_pad_i = SDA; + + assign SCL = scl_pad_oen_o ? 1'bz : scl_pad_o; + assign SDA = sda_pad_oen_o ? 1'bz : sda_pad_o; + + // printf output + wire uart_baud_o, uart_tx_o, uart_rx_i; + assign uart_rx_i = 1'b1; + + uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o)); + + // End the simulation + always @(posedge wb_clk) + if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0)) + begin + $display($time, "Finish called.",); + $finish; + end + + u2_core #(.RAM_SIZE(24576)) + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD[7:0]), + .GMII_TX_EN (GMII_TX_EN), + .GMII_TX_ER (GMII_TX_ER), + .GMII_GTX_CLK (GMII_GTX_CLK), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk), + .ser_t (ser_t[15:0]), + .ser_tklsb (ser_tklsb), + .ser_tkmsb (ser_tkmsb), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r[15:0]), + .ser_rklsb (ser_rklsb), + .ser_rkmsb (ser_rkmsb), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (uart_baud_o), + .sim_mode (1'b1), + .clock_divider (clock_divider) + ); + +endmodule // single_u2_sim diff --git a/usrp2/fpga/top/tcl/ise_helper.tcl b/usrp2/fpga/top/tcl/ise_helper.tcl new file mode 100644 index 00000000..fe9db87a --- /dev/null +++ b/usrp2/fpga/top/tcl/ise_helper.tcl @@ -0,0 +1,89 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +proc set_props {process options} { + if ![string compare $options ""] { + return + } + set state 1 + foreach opt $options { + if $state { + set key $opt + set state 0 + } else { + puts ">>> Setting: $process\[$key\] = $opt" + if ![string compare $process "Project"] { + project set $key $opt + } else { + project set $key $opt -process $process + } + set state 1 + } + } +} + +if [file isfile $env(PROJ_FILE)] { + puts ">>> Opening project: $env(PROJ_FILE)" + project open $env(PROJ_FILE) +} else { + puts ">>> Creating project: $env(PROJ_FILE)" + project new $env(PROJ_FILE) + + ################################################## + # Set the project properties + ################################################## + set_props "Project" $env(PROJECT_PROPERTIES) + + ################################################## + # Add the sources + ################################################## + foreach source $env(SOURCES) { + set source $env(SOURCE_ROOT)$source + puts ">>> Adding source to project: $source" + xfile add $source + } + + ################################################## + # Set the top level module + ################################################## + project set top $env(TOP_MODULE) + + ################################################## + # Set the process properties + ################################################## + set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES) + set_props "Translate" $env(TRANSLATE_PROPERTIES) + set_props "Map" $env(MAP_PROPERTIES) + set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES) + set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES) + set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES) + set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES) +} + +if [string compare $env(PROCESS_RUN) ""] { + puts ">>> Running Process: $env(PROCESS_RUN)" + process run $env(PROCESS_RUN) +} + +project close +exit + + diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v new file mode 100755 index 00000000..cc5a35c7 --- /dev/null +++ b/usrp2/fpga/top/u2_core/u2_core.v @@ -0,0 +1,678 @@ +// //////////////////////////////////////////////////////////////////////////////// +// Module Name: u2_core +// //////////////////////////////////////////////////////////////////////////////// + +module u2_core + #(parameter RAM_SIZE=16384) + (// Clocks + input dsp_clk, + input wb_clk, + output clock_ready, + input clk_to_mac, + input pps_in, + + // Misc, debug + output [7:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in, + output exp_pps_out, + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output [7:0] GMII_TXD, + output GMII_TX_EN, + output GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output [15:0] ser_t, + output ser_tklsb, + output ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, + output cpld_mode, + output cpld_done, + input cpld_din, + input cpld_clk, + input cpld_detached, + //input por, + //output config_success, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_on_a, + output adc_oe_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_on_b, + output adc_oe_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + input scl_pad_i, + output scl_pad_o, + output scl_pad_oen_o, + input sda_pad_i, + output sda_pad_o, + output sda_pad_oen_o, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Generic SPI + output sclk, + output mosi, + input miso, + output sen_clk, + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output sen_rx_db, + output sen_rx_adc, + output sen_rx_dac, + + // GPIO to DBoards + inout [15:0] io_tx, + inout [15:0] io_rx, + + // External RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + input RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // Debug stuff + output uart_tx_o, + input uart_rx_i, + output uart_baud_o, + input sim_mode, + input [3:0] clock_divider + ); + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire ram_loader_done; + wire ram_loader_rst, wb_rst, dsp_rst; + + wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + + wire [31:0] debug_gpio_0, debug_gpio_1; + wire [31:0] atr_lines; + + wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; + + wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; + wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; + wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; + + // /////////////////////////////////////////////////////////////////////////////////////////////// + // Wishbone Single Master INTERCON + parameter dw = 32; // Data bus width + parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space + parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. + + wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i; + wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, + s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, + s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o, + s12_dat_i, s12_dat_o; + wire [aw-1:0] m0_adr,m1_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr; + wire [sw-1:0] m0_sel,m1_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel; + wire m0_ack,m1_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack; + wire m0_stb,m1_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb; + wire m0_cyc,m1_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc; + wire m0_err,m1_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err; + wire m0_rty,m1_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty; + wire m0_we,m1_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we; + + wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10), + .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10), + .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10), + .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10), + .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01), + .dw(dw),.aw(aw),.sw(sw)) wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), + .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), + .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), + .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), + .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), + .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), + .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), + .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty), + .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty), + .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty), + .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb), + .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty), + .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb), + .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty), + .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb), + .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty), + .s13_dat_i(0),.s13_ack_i(0),.s13_err_i(0),.s13_rty_i(0), + .s14_dat_i(0),.s14_ack_i(0),.s14_err_i(0),.s14_rty_i(0), + .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) ); + + ////////////////////////////////////////////////////////////////////////////////////////// + // Reset Controller + system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), + .ram_loader_rst_o(ram_loader_rst), + .wb_rst_o(wb_rst), + .ram_loader_done_i(ram_loader_done)); + + //assign config_success = ram_loader_done; + + // /////////////////////////////////////////////////////////////////// + // RAM Loader + + wire [31:0] ram_loader_dat, iwb_dat; + wire [15:0] ram_loader_adr, iwb_adr; + wire [3:0] ram_loader_sel; + wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire iwb_ack, iwb_stb; + ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + // CPLD Interface + .cfg_clk_i(cpld_clk), + .cfg_data_i(cpld_din), + .start_o(cpld_start), + .mode_o(cpld_mode), + .done_o(cpld_done), + .detached_i(cpld_detached), + // Wishbone Interface + .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), + .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), + .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), + .ram_loader_done_o(ram_loader_done)); + + // Processor + aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) + aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), + // Instruction Wishbone bus to I-RAM + .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), + .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + // Data Wishbone bus to system bus fabric + .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), + .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + // Interrupts and exceptions + .sys_int_i(proc_int),.sys_exc_i(bus_error) ); + + assign bus_error = m0_err | m0_rty; + + // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone + // I-port connects directly to processor and ram loader + + ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + + .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), + .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_done_i(ram_loader_done), + + .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), + .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + + .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); + + assign s0_err = 1'b0; + assign s0_rty = 1'b0; + + // Buffer Pool, slave #1 + wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop; + wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop; + wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop; + wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop; + wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + + wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full; + wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full; + wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full; + wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full; + wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + + buffer_pool buffer_pool + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .status(status),.sys_int_o(buffer_int), + + .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), + .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), + + // Write Interfaces + .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done), + .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full), + .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done), + .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full), + .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done), + .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full), + .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done), + .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full), + // Read Interfaces + .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done), + .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop), + .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done), + .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop), + .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done), + .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop), + .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done), + .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop) + ); + + // SPI -- Slave #2 + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + + assign s2_rty = 1'b0; + + // I2C -- Slave #3 + i2c_master_top #(.ARST_LVL(1)) + i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_i[31:8] = 24'd0; + assign s3_err = 1'b0; + assign s3_rty = 1'b0; + + // GPIOs -- Slave #4 + nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + assign s4_err = 1'b0; + assign s4_rty = 1'b0; + + // Buffer Pool Status -- Slave #5 + wb_readback_mux buff_pool_status + (.wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_stb_i(s5_stb), + .wb_adr_i(s5_adr), + .wb_dat_o(s5_dat_i), + .wb_ack_o(s5_ack), + + .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), + .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10({30'b0,clk_func,clk_status}), + .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) + ); + + assign s5_err = 1'b0; + assign s5_rty = 1'b0; + + // Slave, #6 Ethernet MAC, see below + + // Settings Bus -- Slave #7 + settings_bus settings_bus + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), + .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), + .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); + + assign s7_err = 1'b0; + assign s7_rty = 1'b0; + assign s7_dat_i = 32'd0; + + // Output control lines + wire [7:0] clock_outs, serdes_outs, adc_outs; + assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; + assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; + assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; + + wire phy_reset; + assign PHY_RESETn = ~phy_reset; + + setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + .in(set_data),.out(clock_outs),.changed()); + setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(serdes_outs),.changed()); + setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(adc_outs),.changed()); + setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(leds),.changed()); + setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(phy_reset),.changed()); + + // ///////////////////////////////////////////////////////////////////////// + // Ethernet MAC Slave #6 + + wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop; + wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err; + wire [31:0] Tx_mac_data, Rx_mac_data; + wire [1:0] Tx_mac_BE, Rx_mac_BE; + wire rst_mac; + + oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac)); + + MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11)) + MAC_top + (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk), + .rst_mac(rst_mac),.rst_user(dsp_rst), + .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]), + .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack), + .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE), + .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), + .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), + .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), + .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD), + .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD), + .Crs(GMII_CRS),.Col(GMII_COL), + .Mdio(MDIO),.Mdc(MDC), + .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2), + .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(), + .debug0(debug_mac0),.debug1(debug_mac1) ); + + assign s6_err = 1'b0; + assign s6_rty = 1'b0; + + mac_rxfifo_int mac_rxfifo_int + (.clk(dsp_clk),.rst(dsp_rst), + .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data), + .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop), + .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), + .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done), + .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full), + .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) ); + + mac_txfifo_int mac_txfifo_int + (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac), + .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), + .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), + .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done), + .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop), + .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) ); + + // ///////////////////////////////////////////////////////////////////////// + // Interrupt Controller, Slave #8 + + wire [8:0] irq={{6'b0,uart_tx_int, uart_rx_int}, + {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; + + simple_pic #(.is(9),.dwidth(32)) simple_pic + (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), + .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), + .irq(irq) ); + assign s8_err = 0; + assign s8_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // Master Timer, Slave #9 + + wire [31:0] master_time; + timer timer + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), + .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), + .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); + assign s9_err = 0; + assign s9_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // UART, Slave #10 + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack), + .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i), + .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), + .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); + + assign s10_err = 0; + assign s10_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller, Slave #11 + + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + + atr_controller atr_controller + (.clk_i(wb_clk),.rst_i(wb_rst), + .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), + .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), + .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + assign s11_err = 0; + assign s11_rty = 0; + + // ////////////////////////////////////////////////////////////////////////// + // Time Sync, Slave #12 + + time_sync time_sync + (.wb_clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]), + .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack), + .sys_clk_i(dsp_clk),.master_time_o(master_time), + .pps_in(pps_in),.exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), + .int_o(pps_int) ); + assign s12_err = 0; + assign s12_rty = 0; + + // ///////////////////////////////////////////////////////////////////////// + // DSP + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + + rx_control #(.FIFOSIZE(10)) rx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.overrun(overrun), + .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error), + .wr_ready_i(wr1_ready), .wr_full_i(wr1_full), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), + .debug_rx(debug_rx) ); + + // dummy_rx dsp_core_rx + dsp_core_rx dsp_core_rx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + tx_control #(.FIFOSIZE(10)) tx_control + (.clk(dsp_clk), .rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .master_time(master_time),.underrun(underrun), + .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop), + .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), + .debug(debug_txc) ); + + dsp_core_tx dsp_core_tx + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .dac_a(dac_a),.dac_b(dac_b), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); + + assign dsp_rst = wb_rst; + + // /////////////////////////////////////////////////////////////////////////////////// + // SERDES + + serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes + (.clk(dsp_clk),.rst(dsp_rst), + .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), + .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error), + .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop), + .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), + .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error), + .wr_ready_i(wr0_ready),.wr_full_i(wr0_full), + .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), + .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), + .debug0(debug_serdes0), .debug1(debug_serdes1) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // External RAM Interface + + extram_interface extram_interface + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .rd_dat_i(rd3_dat),.rd_read_o(rd3_read),.rd_done_o(rd3_done),.rd_error_o(rd3_error), + .rd_sop_i(rd3_sop),.rd_eop_i(rd3_eop), + .wr_dat_o(wr3_dat),.wr_write_o(wr3_write),.wr_done_o(wr3_done),.wr_error_o(wr3_error), + .wr_ready_i(wr3_ready),.wr_full_i(wr3_full), + .RAM_D(RAM_D),.RAM_A(RAM_A),.RAM_CE1n(RAM_CE1n),.RAM_CENn(RAM_CENn), + .RAM_CLK(RAM_CLK),.RAM_WEn(RAM_WEn),.RAM_OEn(RAM_OEn),.RAM_LDn(RAM_LDn) ); + + + // ///////////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // FIFO Level Debugging + reg [31:0] host_to_dsp_fifo, dsp_to_host_fifo, eth_mac_debug; + + always @(posedge dsp_clk) + host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, + {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; + + always @(posedge dsp_clk) + dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, + {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; + + always @(posedge dsp_clk) + eth_mac_debug <= { + // {eth_tx_full2, eth_tx_empty2, eth_tx_occ2[13:0]}, + // {underrun, overrun, debug_mac0[13:0] }, + {debug_txc[15:0]}, + {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; + + wire debug_mux; + setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(debug_mux),.changed()); + + assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; + + // Assign various commonly used debug buses. + /* + wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, + irq[7:0], + GMII_RXD, + GMII_TXD}; + + wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; + + wire [31:0] debug_time = {uart_tx_o, 7'b0, + irq[7:0], + 6'b0, GMII_RX_DV, GMII_TX_EN, + 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; + + wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, + irq[7:0], + proc_int, 7'b0 }; + + wire [31:0] debug_eth = + {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, + {8'd0}, + {8'd0}, + {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; + + assign debug_serdes0 = { { rd0_dat[7:0] }, + { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, + { ser_t[15:8] }, + { ser_t[7:0] } }; + + assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, + { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, + { ser_r[15:8] }, + { ser_r[7:0] } }; + + assign debug_gpio_1 = {uart_tx_o,7'd0, + 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, + debug_txc[15:0]}; + assign debug_gpio_1 = debug_rx; + assign debug_gpio_1 = debug_serdes1; + assign debug_gpio_1 = debug_eth; + + */ + + // Choose actual debug buses + assign debug_clk[0] = wb_clk; + assign debug_clk[1] = dsp_clk; + + //assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, + // {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; + + //assign debug = debug_tx_dsp; + //assign debug = debug_serdes0; + + assign debug_gpio_0 = 0; // debug_serdes1; + assign debug_gpio_1 = eth_mac_debug; + +endmodule // u2_core diff --git a/usrp2/fpga/top/u2_fpga/Makefile b/usrp2/fpga/top/u2_fpga/Makefile new file mode 100644 index 00000000..b3245d88 --- /dev/null +++ b/usrp2/fpga/top/u2_fpga/Makefile @@ -0,0 +1,129 @@ +FILENAME=u2_fpga_top +PARTNUM=xc3s1500-5fg456 + +all: project command xst ngd ncd ncd2 bit + +xst: + xst -ifn ${FILENAME}.cmd -ofn xst.log + +ngd: + ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME} + +ncd: + rm -rf ${FILENAME}.ncd + map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf + +# Place and route ncd file into new ncd file +ncd2: + par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf + +bit: + bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit + +clean: + @rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \ + *.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \ + *.blc *.bld *.ise_ISE_Backup *~ \ + *.pad *.ngm *.ngd *.par *.pcf *.unroutes \ + *.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt \ + *.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \ + output.dat coregen.log *.ngo *.log ${FILENAME}.map \ + ${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr + +command: + rm -rf ${FILENAME}.cmd + @echo "identification" >> ${FILENAME}.cmd + @echo "status" >> ${FILENAME}.cmd + @echo "time short" >> ${FILENAME}.cmd + @echo "memory on" >> ${FILENAME}.cmd + @echo "run " >> ${FILENAME}.cmd + @echo "-top ${FILENAME}" >> ${FILENAME}.cmd + @echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd + @echo "-ifmt Verilog " >> ${FILENAME}.cmd + @echo "-ofn ${FILENAME} " >> ${FILENAME}.cmd + @echo "-p ${PARTNUM}" >> ${FILENAME}.cmd + @echo "-bufg 6" >> ${FILENAME}.cmd + @echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}" >> ${FILENAME}.cmd + +project: + rm -f ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/TECH/duram.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/sign_extend.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cordic_stage.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cic_int_shifter.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cic_dec_shifter.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/Reg_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/ram_2port.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cordic.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cic_interp.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/cic_decim.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/eth_miim.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/RMON.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/Phy_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_tx.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_rx.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/strobe_gen.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/ss_rcvr.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/shortfifo.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/setting_reg.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/mux8.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/mux4.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/longfifo.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/decoder_3_8.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/buffer_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/CRC16_D16.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/tx_control.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/rx_control.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/dsp_core_tx.v" ' >> ${FILENAME}.prj + @echo '`include "../../sdr_lib/dsp_core_rx.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" ' >> ${FILENAME}.prj + @echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/rtl/verilog/MAC_top.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/mac_txfifo_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../eth/mac_rxfifo_int.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/wb_readback_mux.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/wb_1master.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/timer.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/system_control.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/settings_bus.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/serdes_tx.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/serdes_rx.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/ram_wb_harvard.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/ram_loader.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/nsgpio.v" ' >> ${FILENAME}.prj + @echo '`include "../../control_lib/buffer_pool.v" ' >> ${FILENAME}.prj + @echo '`include "../u2_basic/u2_basic.v" ' >> ${FILENAME}.prj + @echo '`include "u2_fpga_top.v" ' >> ${FILENAME}.prj + @echo '`include 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ztV!sH@HYPpM8Tvg6v><23Vb=Q&3RLWRas6bz|jBEW?N=3l%daMqA;WqoK4Bq`o~}T zzmKd#is9?^1A*4)go1C1b747-e*D+}(VtpGRNTQ z`S<@x)f6Xi>hXsuj=^iNSLjpR_m%I{KmDP9`UloNW%zn*5oisT3Tlt|a86kN`geZ( zi&nKK@OlgZvIakH-oDH|-2nvsU%{a+!Pdt*a?Sjm-~a93p5g=n{gL8ktXw4>)qWgc z!Tl0P*x#aC`X9k3ZW>u9@>P#VYBBGwAS&g~U%bd;T(}Gd8{G(qiA`}%4Tmm${o7rM zhi>*o6nBM!gNQlt`|9q>Y(R&{XkoNE8(bm;@9K|6^MSCHZBNaQ5GU@g-|$0 zudsE2$5ru@q6>%;^78b{qj%QQvpDKljd3!DG{@Ta1-a1vsGqlK|LTXPPplrO#HiP0 z0@%`FfAX8Z^YrH-ditX?eR30qK7w5mUC=YD8H*^5TbMDDVhqJBwJj9e-}=HA!I1v% J_gci?{|DX-JthDE literal 0 HcmV?d00001 diff --git a/usrp2/fpga/top/u2_fpga/u2_fpga.ucf b/usrp2/fpga/top/u2_fpga/u2_fpga.ucf new file mode 100755 index 00000000..5d212481 --- /dev/null +++ b/usrp2/fpga/top/u2_fpga/u2_fpga.ucf @@ -0,0 +1,341 @@ +NET "adc_a[0]" LOC = "A14" ; +NET "adc_a[10]" LOC = "D20" ; +NET "adc_a[11]" LOC = "D19" ; +NET "adc_a[12]" LOC = "D21" ; +NET "adc_a[13]" LOC = "E18" ; +NET "adc_a[1]" LOC = "B14" ; +NET "adc_a[2]" LOC = "C13" ; +NET "adc_a[3]" LOC = "D13" ; +NET "adc_a[4]" LOC = "A13" ; +NET "adc_a[5]" LOC = "B13" ; +NET "adc_a[6]" LOC = "E12" ; +NET "adc_a[7]" LOC = "C22" ; +NET "adc_a[8]" LOC = "C20" ; +NET "adc_a[9]" LOC = "C21" ; +NET "adc_b[0]" LOC = "A12" ; +NET "adc_b[10]" LOC = "D18" ; +NET "adc_b[11]" LOC = "B18" ; +NET "adc_b[12]" LOC = "D17" ; +NET "adc_b[13]" LOC = "E17" ; +NET "adc_b[1]" LOC = "E16" ; +NET "adc_b[2]" LOC = "F12" ; +NET "adc_b[3]" LOC = "F13" ; +NET "adc_b[4]" LOC = "F16" ; +NET "adc_b[5]" LOC = "F17" ; +NET "adc_b[6]" LOC = "C19" ; +NET "adc_b[7]" LOC = "B20" ; +NET "adc_b[8]" LOC = "B19" ; +NET "adc_b[9]" LOC = "C18" ; +NET "clk_en[0]" LOC = "C4" ; +NET "clk_en[1]" LOC = "D1" ; +NET "clk_sel[0]" LOC = "C3" ; +NET "clk_sel[1]" LOC = "C2" ; +NET "dac_a[0]" LOC = "A5" ; +NET "dac_a[10]" LOC = "L2" ; +NET "dac_a[11]" LOC = "L4" ; +NET "dac_a[12]" LOC = "L3" ; +NET "dac_a[13]" LOC = "L6" ; +NET "dac_a[14]" LOC = "L5" ; +NET "dac_a[15]" LOC = "K2" ; +NET "dac_a[1]" LOC = "B5" ; +NET "dac_a[2]" LOC = "C5" ; +NET "dac_a[3]" LOC = "D5" ; +NET "dac_a[4]" LOC = "A4" ; +NET "dac_a[5]" LOC = "B4" ; +NET "dac_a[6]" LOC = "F6" ; +NET "dac_a[7]" LOC = "D10" ; +NET "dac_a[8]" LOC = "D9" ; +NET "dac_a[9]" LOC = "A10" ; +NET "dac_b[0]" LOC = "D11" ; +NET "dac_b[10]" LOC = "F9" ; +NET "dac_b[11]" LOC = "A8" ; +NET "dac_b[12]" LOC = "B8" ; +NET "dac_b[13]" LOC = "D7" ; +NET "dac_b[14]" LOC = "E7" ; +NET "dac_b[15]" LOC = "B6" ; +NET "dac_b[1]" LOC = "E11" ; +NET "dac_b[2]" LOC = "F11" ; +NET "dac_b[3]" LOC = "B10" ; +NET "dac_b[4]" LOC = "C10" ; +NET "dac_b[5]" LOC = "E10" ; +NET "dac_b[6]" LOC = "F10" ; +NET "dac_b[7]" LOC = "A9" ; +NET "dac_b[8]" LOC = "B9" ; +NET "dac_b[9]" LOC = "E9" ; +NET "debug[0]" LOC = "N5" ; +NET "debug[10]" LOC = "R4" ; +NET "debug[11]" LOC = "T3" ; +NET "debug[12]" LOC = "U3" ; +NET "debug[13]" LOC = "M2" ; +NET "debug[14]" LOC = "M3" ; +NET "debug[15]" LOC = "M4" ; +NET "debug[16]" LOC = "M5" ; +NET "debug[17]" LOC = "M6" ; +NET "debug[18]" LOC = "N1" ; +NET "debug[19]" LOC = "N2" ; +NET "debug[1]" LOC = "N6" ; +NET "debug[20]" LOC = "N3" ; +NET "debug[21]" LOC = "T1" ; +NET "debug[22]" LOC = "T2" ; +NET "debug[23]" LOC = "U2" ; +NET "debug[24]" LOC = "T4" ; +NET "debug[25]" LOC = "U4" ; +NET "debug[26]" LOC = "T5" ; +NET "debug[27]" LOC = "T6" ; +NET "debug[28]" LOC = "U5" ; +NET "debug[29]" LOC = "V5" ; +NET "debug[2]" LOC = "P1" ; +NET "debug[30]" LOC = "W2" ; +NET "debug[31]" LOC = "W3" ; +NET "debug[3]" LOC = "P2" ; +NET "debug[4]" LOC = "P4" ; +NET "debug[5]" LOC = "P5" ; +NET "debug[6]" LOC = "R1" ; +NET "debug[7]" LOC = "R2" ; +NET "debug[8]" LOC = "P6" ; +NET "debug[9]" LOC = "R5" ; +NET "debug_clk[0]" LOC = "N4" ; +NET "debug_clk[1]" LOC = "M1" ; +NET "GMII_RXD[0]" LOC = "AA15" ; +NET "GMII_RXD[1]" LOC = "AB15" ; +NET "GMII_RXD[2]" LOC = "U14" ; +NET "GMII_RXD[3]" LOC = "V14" ; +NET "GMII_RXD[4]" LOC = "U13" ; +NET "GMII_RXD[5]" LOC = "V13" ; +NET "GMII_RXD[6]" LOC = "Y13" ; +NET "GMII_RXD[7]" LOC = "AA13" ; +NET "GMII_TXD[0]" LOC = "W14" ; +NET "GMII_TXD[1]" LOC = "AA20" ; +NET "GMII_TXD[2]" LOC = "AB20" ; +NET "GMII_TXD[3]" LOC = "Y18" ; +NET "GMII_TXD[4]" LOC = "AA18" ; +NET "GMII_TXD[5]" LOC = "AB18" ; +NET "GMII_TXD[6]" LOC = "V17" ; +NET "GMII_TXD[7]" LOC = "W17" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "RAM_A[0]" LOC = "N22" ; +NET "RAM_A[10]" LOC = "P18" ; +NET "RAM_A[11]" LOC = "R19" ; +NET "RAM_A[12]" LOC = "P19" ; +NET "RAM_A[13]" LOC = "R21" ; +NET "RAM_A[14]" LOC = "R22" ; +NET "RAM_A[15]" LOC = "T19" ; +NET "RAM_A[16]" LOC = "T20" ; +NET "RAM_A[17]" LOC = "U20" ; +NET "RAM_A[18]" LOC = "W19" ; +NET "RAM_A[1]" LOC = "N20" ; +NET "RAM_A[2]" LOC = "T21" ; +NET "RAM_A[3]" LOC = "M22" ; +NET "RAM_A[4]" LOC = "N19" ; +NET "RAM_A[5]" LOC = "N17" ; +NET "RAM_A[6]" LOC = "N18" ; +NET "RAM_A[7]" LOC = "P21" ; +NET "RAM_A[8]" LOC = "P22" ; +NET "RAM_A[9]" LOC = "P17" ; +NET "RAM_D[0]" LOC = "Y21" ; +NET "RAM_D[10]" LOC = "V22" ; +NET "RAM_D[11]" LOC = "V21" ; +NET "RAM_D[12]" LOC = "T17" ; +NET "RAM_D[13]" LOC = "U18" ; +NET "RAM_D[14]" LOC = "U21" ; +NET "RAM_D[15]" LOC = "R18" ; +NET "RAM_D[16]" LOC = "T18" ; +NET "RAM_D[17]" LOC = "T22" ; +NET "RAM_D[1]" LOC = "Y20" ; +NET "RAM_D[2]" LOC = "Y19" ; +NET "RAM_D[3]" LOC = "W22" ; +NET "RAM_D[4]" LOC = "Y22" ; +NET "RAM_D[5]" LOC = "V19" ; +NET "RAM_D[6]" LOC = "W21" ; +NET "RAM_D[7]" LOC = "W20" ; +NET "RAM_D[8]" LOC = "U19" ; +NET "RAM_D[9]" LOC = "V20" ; +NET "ser_r[0]" LOC = "AB10" ; +NET "ser_r[10]" LOC = "W10" ; +NET "ser_r[11]" LOC = "Y1" ; +NET "ser_r[12]" LOC = "Y3" ; +NET "ser_r[13]" LOC = "Y2" ; +NET "ser_r[14]" LOC = "W4" ; +NET "ser_r[15]" LOC = "W1" ; +NET "ser_r[1]" LOC = "AA10" ; +NET "ser_r[2]" LOC = "U9" ; +NET "ser_r[3]" LOC = "U6" ; +NET "ser_r[4]" LOC = "AB11" ; +NET "ser_r[5]" LOC = "Y7" ; +NET "ser_r[6]" LOC = "W7" ; +NET "ser_r[7]" LOC = "AB7" ; +NET "ser_r[8]" LOC = "AA7" ; +NET "ser_r[9]" LOC = "W9" ; +NET "ser_t[0]" LOC = "V7" ; +NET "ser_t[10]" LOC = "AA6" ; +NET "ser_t[11]" LOC = "Y6" ; +NET "ser_t[12]" LOC = "W8" ; +NET "ser_t[13]" LOC = "V8" ; +NET "ser_t[14]" LOC = "AB8" ; +NET "ser_t[15]" LOC = "AA8" ; +NET "ser_t[1]" LOC = "V10" ; +NET "ser_t[2]" LOC = "AB4" ; +NET "ser_t[3]" LOC = "AA4" ; +NET "ser_t[4]" LOC = "Y5" ; +NET "ser_t[5]" LOC = "W5" ; +NET "ser_t[6]" LOC = "AB5" ; +NET "ser_t[7]" LOC = "AA5" ; +NET "ser_t[8]" LOC = "W6" ; +NET "ser_t[9]" LOC = "V6" ; +NET "clk_muxed" TNM_NET = "clk_muxed"; +TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %; +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; +#PACE: Start of Constraints generated by PACE + +#PACE: Start of PACE I/O Pin Assignments +NET "adc_oen_a" LOC = "E19" ; +NET "adc_oen_b" LOC = "C17" ; +NET "adc_ovf_a" LOC = "F18" ; +NET "adc_ovf_b" LOC = "B17" ; +NET "adc_pdn_a" LOC = "E20" ; +NET "adc_pdn_b" LOC = "D15" ; +NET "clk_fpga_n" LOC = "B11" ; +NET "clk_fpga_p" LOC = "A11" ; +NET "clk_func" LOC = "C12" ; +NET "clk_status" LOC = "B12" ; +NET "clk_to_mac" LOC = "AB12" ; +NET "cpld_clk" LOC = "AB14" ; +NET "cpld_din" LOC = "AA14" ; +NET "cpld_done" LOC = "V12" ; +NET "cpld_mode" LOC = "U12" ; +NET "cpld_start" LOC = "AA9" ; +NET "exp_pps_in_n" LOC = "V4" ; +NET "exp_pps_in_p" LOC = "V3" ; +NET "exp_pps_out_n" LOC = "V2" ; +NET "exp_pps_out_p" LOC = "V1" ; +NET "GMII_COL" LOC = "U16" ; +NET "GMII_CRS" LOC = "U17" ; +NET "GMII_GTX_CLK" LOC = "AA17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_RX_CLK" LOC = "W16" ; +NET "GMII_RX_DV" LOC = "AB16" ; +NET "GMII_RX_ER" LOC = "AA16" ; +NET "GMII_TX_CLK" LOC = "W13" ; +NET "GMII_TX_EN" LOC = "Y17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TX_ER" LOC = "V16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "led1" LOC = "V11" ; +NET "led2" LOC = "Y12" ; +NET "MDC" LOC = "V18" ; +NET "MDIO" LOC = "Y16" | PULLUP ; +NET "PHY_CLK" LOC = "V15" ; +NET "PHY_INTn" LOC = "AB13" ; +NET "PHY_RESETn" LOC = "AA19" ; +NET "pps_in" LOC = "Y11" ; +NET "RAM_CE1n" LOC = "N21" ; +NET "RAM_CENn" LOC = "M18" ; +NET "RAM_CLK" LOC = "M17" ; +NET "RAM_LDn" LOC = "M21" ; +NET "RAM_OEn" LOC = "M19" ; +NET "RAM_WEn" LOC = "M20" ; +NET "SCL" LOC = "A7" ; +NET "SCL_force" LOC = "E8" ; +NET "sclk" LOC = "K5" ; +NET "sclk_rx_adc" LOC = "J17" ; +NET "sclk_rx_dac" LOC = "J19" ; +NET "sclk_rx_db" LOC = "F19" ; +NET "sclk_tx_adc" LOC = "H1" ; +NET "sclk_tx_dac" LOC = "J5" ; +NET "sclk_tx_db" LOC = "D3" ; +NET "SDA" LOC = "D8" ; +NET "SDA_force" LOC = "C11" ; +NET "sdi" LOC = "J1" ; +NET "sdi_rx_adc" LOC = "H22" ; +NET "sdi_rx_dac" LOC = "J21" ; +NET "sdi_rx_db" LOC = "H19" ; +NET "sdi_tx_adc" LOC = "J4" ; +NET "sdi_tx_dac" LOC = "J6" ; +NET "sdi_tx_db" LOC = "G4" ; +NET "sdo" LOC = "J2" ; +NET "sdo_rx_adc" LOC = "H21" ; +NET "sdo_rx_db" LOC = "G20" ; +NET "sdo_tx_adc" LOC = "H2" ; +NET "sdo_tx_db" LOC = "G3" ; +NET "sen_clk" LOC = "K6" ; +NET "sen_dac" LOC = "L1" ; +NET "sen_rx_adc" LOC = "H18" ; +NET "sen_rx_dac" LOC = "J18" ; +NET "sen_rx_db" LOC = "D22" ; +NET "sen_tx_adc" LOC = "G2" ; +NET "sen_tx_dac" LOC = "H4" ; +NET "sen_tx_db" LOC = "C1" ; +NET "ser_enable" LOC = "W11" ; +NET "ser_loopen" LOC = "Y4" ; +NET "ser_prbsen" LOC = "AA3" ; +NET "ser_rklsb" LOC = "V9" ; +NET "ser_rkmsb" LOC = "Y10" ; +NET "ser_rx_clk" LOC = "AA11" ; +NET "ser_rx_en" LOC = "AB9" ; +NET "ser_tklsb" LOC = "U10" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_tkmsb" LOC = "U11" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_tx_clk" LOC = "U7" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<0>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<1>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<2>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<3>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<4>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<5>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<6>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<7>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<8>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<9>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<10>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<11>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<12>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<13>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<14>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t<15>" IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +#PACE: Start of PACE Area Constraints + +#PACE: Start of PACE Prohibit Constraints + +#PACE: End of Constraints generated by PACE diff --git a/usrp2/fpga/top/u2_fpga/u2_fpga_top.prj b/usrp2/fpga/top/u2_fpga/u2_fpga_top.prj new file mode 100644 index 00000000..544415f4 --- /dev/null +++ b/usrp2/fpga/top/u2_fpga/u2_fpga_top.prj @@ -0,0 +1,102 @@ +verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v" +verilog work "../../control_lib/ram_2port.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v" +verilog work "../../coregen/fifo_generator_v4_1.v" +verilog work "../../control_lib/shortfifo.v" +verilog work "../../control_lib/longfifo.v" +verilog work "../../sdr_lib/sign_extend.v" +verilog work "../../sdr_lib/cordic_stage.v" +verilog work "../../sdr_lib/cic_int_shifter.v" +verilog work "../../sdr_lib/cic_dec_shifter.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v" +verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v" +verilog work "../../opencores/8b10b/encode_8b10b.v" +verilog work "../../opencores/8b10b/decode_8b10b.v" +verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v" +verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v" +verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v" +verilog work "../../eth/rtl/verilog/Reg_int.v" +verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v" +verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" +verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v" +verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" +verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" +verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" +verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" +verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" +verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" +verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" +verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" +verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" +verilog work "../../control_lib/ss_rcvr.v" +verilog work "../../control_lib/cascadefifo2.v" +verilog work "../../control_lib/CRC16_D16.v" +verilog work "../../timing/time_sender.v" +verilog work "../../timing/time_receiver.v" +verilog work "../../serdes/serdes_tx.v" +verilog work "../../serdes/serdes_rx.v" +verilog work "../../serdes/serdes_fc_tx.v" +verilog work "../../serdes/serdes_fc_rx.v" +verilog work "../../sdr_lib/round.v" +verilog work "../../sdr_lib/cordic.v" +verilog work "../../sdr_lib/cic_interp.v" +verilog work "../../sdr_lib/cic_decim.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v" +verilog work "../../opencores/spi/rtl/verilog/spi_shift.v" +verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v" +verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v" +verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v" +verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v" +verilog work "../../eth/rtl/verilog/eth_miim.v" +verilog work "../../eth/rtl/verilog/RMON.v" +verilog work "../../eth/rtl/verilog/Phy_int.v" +verilog work "../../eth/rtl/verilog/MAC_tx.v" +verilog work "../../eth/rtl/verilog/MAC_rx.v" +verilog work "../../eth/rtl/verilog/Clk_ctrl.v" +verilog work "../../control_lib/strobe_gen.v" +verilog work "../../control_lib/setting_reg.v" +verilog work "../../control_lib/mux8.v" +verilog work "../../control_lib/mux4.v" +verilog work "../../control_lib/icache.v" +verilog work "../../control_lib/dpram32.v" +verilog work "../../control_lib/decoder_3_8.v" +verilog work "../../control_lib/dcache.v" +verilog work "../../control_lib/buffer_int.v" +verilog work "../../timing/timer.v" +verilog work "../../timing/time_sync.v" +verilog work "../../serdes/serdes.v" +verilog work "../../sdr_lib/tx_control.v" +verilog work "../../sdr_lib/rx_control.v" +verilog work "../../sdr_lib/dsp_core_tx.v" +verilog work "../../sdr_lib/dsp_core_rx.v" +verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v" +verilog work "../../opencores/spi/rtl/verilog/spi_top.v" +verilog work "../../opencores/simple_pic/rtl/simple_pic.v" +verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v" +verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" +verilog work "../../eth/rtl/verilog/MAC_top.v" +verilog work "../../eth/mac_txfifo_int.v" +verilog work "../../eth/mac_rxfifo_int.v" +verilog work "../../control_lib/wb_readback_mux.v" +verilog work "../../control_lib/wb_1master.v" +verilog work "../../control_lib/system_control.v" +verilog work "../../control_lib/settings_bus.v" +verilog work "../../control_lib/ram_loader.v" +verilog work "../../control_lib/ram_harv_cache.v" +verilog work "../../control_lib/nsgpio.v" +verilog work "../../control_lib/extram_interface.v" +verilog work "../../control_lib/buffer_pool.v" +verilog work "../../control_lib/atr_controller.v" +verilog work "../u2_basic/u2_basic.v" +verilog work "u2_fpga_top.v" diff --git a/usrp2/fpga/top/u2_fpga/u2_fpga_top.v b/usrp2/fpga/top/u2_fpga/u2_fpga_top.v new file mode 100644 index 00000000..63798a0c --- /dev/null +++ b/usrp2/fpga/top/u2_fpga/u2_fpga_top.v @@ -0,0 +1,393 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2_fpga_top + ( + // Misc, debug + output led1, + output led2, + output [31:0] debug, + output [1:0] debug_clk, + + // Expansion + input exp_pps_in_p, // Diff + input exp_pps_in_n, // Diff + output exp_pps_out_p, // Diff + output exp_pps_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, // AA9 + output cpld_mode, // U12 + output cpld_done, // V12 + input cpld_din, // AA14 Now shared with CFG_Din + input cpld_clk, // AB14 serial clock + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + + // I2C + inout SCL, + inout SDA, + input SCL_force, + input SDA_force, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input clk_to_mac, + input pps_in, + + // Generic SPI + output sclk, + output sen_clk, + output sen_dac, + output sdi, + input sdo, + + // TX DBoard + output sen_tx_db, + output sclk_tx_db, + input sdo_tx_db, + output sdi_tx_db, + + output sen_tx_adc, + output sclk_tx_adc, + input sdo_tx_adc, + output sdi_tx_adc, + + output sen_tx_dac, + output sclk_tx_dac, + output sdi_tx_dac, + + inout [15:0] io_tx, + + // RX DBoard + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + inout [15:0] io_rx + ); + + // FPGA-specific pins connections + wire aux_clk = PHY_CLK; + //wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire + wire cpld_detached = SDA_force; // FIXME Hacked on with Blue Wire + + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_pps_in; + IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); + defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_pps_out; + OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); + defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge aux_clk) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + wire clk_muxed = clock_ready ? clk_fpga : aux_clk; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_muxed), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire led1_int, led2_int; + assign led1 = ~led1_int; + assign led2 = ~led2_int; + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + u2_basic u2_basic(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .led1 (led1_int), + .led2 (led2_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .PHY_CLK (PHY_CLK), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (), + .uart_rx_i (), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2_fpga_top diff --git a/usrp2/fpga/top/u2_rev2/Makefile b/usrp2/fpga/top/u2_rev2/Makefile new file mode 100644 index 00000000..a5969d62 --- /dev/null +++ b/usrp2/fpga/top/u2_rev2/Makefile @@ -0,0 +1,257 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u2_rev2 +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/buffer_int.v \ +control_lib/buffer_pool.v \ +control_lib/cascadefifo2.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/extram_interface.v \ +control_lib/fifo_2clock.v \ +control_lib/fifo_2clock_casc.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/longfifo.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +eth/mac_rxfifo_int.v \ +eth/mac_txfifo_int.v \ +eth/rtl/verilog/Clk_ctrl.v \ +eth/rtl/verilog/MAC_rx.v \ +eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ +eth/rtl/verilog/MAC_rx/CRC_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ +eth/rtl/verilog/MAC_top.v \ +eth/rtl/verilog/MAC_tx.v \ +eth/rtl/verilog/MAC_tx/CRC_gen.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ +eth/rtl/verilog/MAC_tx/Random_gen.v \ +eth/rtl/verilog/Phy_int.v \ +eth/rtl/verilog/RMON.v \ +eth/rtl/verilog/RMON/RMON_addr_gen.v \ +eth/rtl/verilog/RMON/RMON_ctrl.v \ +eth/rtl/verilog/Reg_int.v \ +eth/rtl/verilog/eth_miim.v \ +eth/rtl/verilog/flow_ctrl_rx.v \ +eth/rtl/verilog/flow_ctrl_tx.v \ +eth/rtl/verilog/miim/eth_clockgen.v \ +eth/rtl/verilog/miim/eth_outputcontrol.v \ +eth/rtl/verilog/miim/eth_shiftreg.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2_rev2/u2_rev2.ucf \ +top/u2_rev2/u2_rev2.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +#export TRANSLATE_PROPERTIES := \ +#"Macro Search Path" "$(SOURCE_ROOT)coregen/" +#export TRANSLATE_PROPERTIES := \ +#"Macro Search Path" "$(shell pwd)/../../coregen/" +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "../../coregen/" + +QUICK_MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +quick: + PROCESS_RUN="Generate Programming File" MAP_PROPERTIES='$(QUICK_MAP_PROPERTIES)' $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/fpga/top/u2_rev2/u2_rev2.ucf b/usrp2/fpga/top/u2_rev2/u2_rev2.ucf new file mode 100644 index 00000000..e18dc6f1 --- /dev/null +++ b/usrp2/fpga/top/u2_rev2/u2_rev2.ucf @@ -0,0 +1,337 @@ +NET "leds[0]" LOC = "F7" ; +NET "leds[1]" LOC = "E5" ; +NET "leds[2]" LOC = "B7" ; +NET "leds[3]" LOC = "C11" ; +NET "leds[4]" LOC = "AB19" ; +NET "debug[0]" LOC = "N5" ; +NET "debug[1]" LOC = "N6" ; +NET "debug[2]" LOC = "P1" ; +NET "debug[3]" LOC = "P2" ; +NET "debug[4]" LOC = "P4" ; +NET "debug[5]" LOC = "P5" ; +NET "debug[6]" LOC = "R1" ; +NET "debug[7]" LOC = "R2" ; +NET "debug[8]" LOC = "P6" ; +NET "debug[9]" LOC = "R5" ; +NET "debug[10]" LOC = "R4" ; +NET "debug[11]" LOC = "T3" ; +NET "debug[12]" LOC = "U3" ; +NET "debug[13]" LOC = "M2" ; +NET "debug[14]" LOC = "M3" ; +NET "debug[15]" LOC = "M4" ; +NET "debug[16]" LOC = "M5" ; +NET "debug[17]" LOC = "M6" ; +NET "debug[18]" LOC = "N1" ; +NET "debug[19]" LOC = "N2" ; +NET "debug[20]" LOC = "N3" ; +NET "debug[21]" LOC = "T1" ; +NET "debug[22]" LOC = "T2" ; +NET "debug[23]" LOC = "U2" ; +NET "debug[24]" LOC = "T4" ; +NET "debug[25]" LOC = "U4" ; +NET "debug[26]" LOC = "T5" ; +NET "debug[27]" LOC = "T6" ; +NET "debug[28]" LOC = "U5" ; +NET "debug[29]" LOC = "V5" ; +NET "debug[30]" LOC = "W2" ; +NET "debug[31]" LOC = "W3" ; +NET "debug_clk[0]" LOC = "N4" ; +NET "debug_clk[1]" LOC = "M1" ; +NET "uart_tx_o" LOC = "C7" ; +NET "uart_rx_i" LOC = "A3" ; +NET "exp_pps_in_p" LOC = "V3" ; +NET "exp_pps_in_n" LOC = "V4" ; +NET "exp_pps_out_p" LOC = "V1" ; +NET "exp_pps_out_n" LOC = "V2" ; +NET "GMII_COL" LOC = "U16" ; +NET "GMII_CRS" LOC = "U17" ; +NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_CLK" LOC = "W13" ; +NET "GMII_RXD[0]" LOC = "AA15" ; +NET "GMII_RXD[1]" LOC = "AB15" ; +NET "GMII_RXD[2]" LOC = "U14" ; +NET "GMII_RXD[3]" LOC = "V14" ; +NET "GMII_RXD[4]" LOC = "U13" ; +NET "GMII_RXD[5]" LOC = "V13" ; +NET "GMII_RXD[6]" LOC = "Y13" ; +NET "GMII_RXD[7]" LOC = "AA13" ; +NET "GMII_RX_CLK" LOC = "W16" ; +NET "GMII_RX_DV" LOC = "AB16" ; +NET "GMII_RX_ER" LOC = "AA16" ; +NET "MDIO" LOC = "Y16" |PULLUP ; +NET "MDC" LOC = "V18" ; +NET "PHY_INTn" LOC = "AB13" ; +NET "PHY_RESETn" LOC = "AA19" ; +NET "PHY_CLK" LOC = "V15" ; +NET "RAM_D[0]" LOC = "N20" ; +NET "RAM_D[1]" LOC = "N21" ; +NET "RAM_D[2]" LOC = "N22" ; +NET "RAM_D[3]" LOC = "M17" ; +NET "RAM_D[4]" LOC = "M18" ; +NET "RAM_D[5]" LOC = "M19" ; +NET "RAM_D[6]" LOC = "M20" ; +NET "RAM_D[7]" LOC = "M21" ; +NET "RAM_D[8]" LOC = "M22" ; +NET "RAM_D[9]" LOC = "Y22" ; +NET "RAM_D[10]" LOC = "Y21" ; +NET "RAM_D[11]" LOC = "Y20" ; +NET "RAM_D[12]" LOC = "Y19" ; +NET "RAM_D[13]" LOC = "W22" ; +NET "RAM_D[14]" LOC = "W21" ; +NET "RAM_D[15]" LOC = "W20" ; +NET "RAM_D[16]" LOC = "W19" ; +NET "RAM_D[17]" LOC = "V22" ; +NET "RAM_A[0]" LOC = "U21" ; +NET "RAM_A[1]" LOC = "T19" ; +NET "RAM_A[2]" LOC = "V21" ; +NET "RAM_A[3]" LOC = "V20" ; +NET "RAM_A[4]" LOC = "T20" ; +NET "RAM_A[5]" LOC = "T21" ; +NET "RAM_A[6]" LOC = "T22" ; +NET "RAM_A[7]" LOC = "T18" ; +NET "RAM_A[8]" LOC = "R18" ; +NET "RAM_A[9]" LOC = "P19" ; +NET "RAM_A[10]" LOC = "P21" ; +NET "RAM_A[11]" LOC = "P22" ; +NET "RAM_A[12]" LOC = "N19" ; +NET "RAM_A[13]" LOC = "N17" ; +NET "RAM_A[14]" LOC = "N18" ; +NET "RAM_A[15]" LOC = "T17" ; +NET "RAM_A[16]" LOC = "U19" ; +NET "RAM_A[17]" LOC = "U18" ; +NET "RAM_A[18]" LOC = "V19" ; +NET "RAM_CE1n" LOC = "U20" ; +NET "RAM_CENn" LOC = "P18" ; +NET "RAM_CLK" LOC = "P17" ; +NET "RAM_WEn" LOC = "R22" ; +NET "RAM_OEn" LOC = "R21" ; +NET "RAM_LDn" LOC = "R19" ; +NET "ser_enable" LOC = "W11" ; +NET "ser_prbsen" LOC = "AA3" ; +NET "ser_loopen" LOC = "Y4" ; +NET "ser_rx_en" LOC = "AB9" ; +NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_rx_clk" LOC = "AA11" ; +NET "ser_r[0]" LOC = "AB10" ; +NET "ser_r[1]" LOC = "AA10" ; +NET "ser_r[2]" LOC = "U9" ; +NET "ser_r[3]" LOC = "U6" ; +NET "ser_r[4]" LOC = "AB11" ; +NET "ser_r[5]" LOC = "Y7" ; +NET "ser_r[6]" LOC = "W7" ; +NET "ser_r[7]" LOC = "AB7" ; +NET "ser_r[8]" LOC = "AA7" ; +NET "ser_r[9]" LOC = "W9" ; +NET "ser_r[10]" LOC = "W10" ; +NET "ser_r[11]" LOC = "Y1" ; +NET "ser_r[12]" LOC = "Y3" ; +NET "ser_r[13]" LOC = "Y2" ; +NET "ser_r[14]" LOC = "W4" ; +NET "ser_r[15]" LOC = "W1" ; +NET "ser_rklsb" LOC = "V9" ; +NET "ser_rkmsb" LOC = "Y10" ; +NET "cpld_start" LOC = "AA9" ; +NET "cpld_mode" LOC = "U12" ; +NET "cpld_done" LOC = "V12" ; +NET "cpld_din" LOC = "AA14" ; +NET "cpld_clk" LOC = "AB14" ; +NET "cpld_detached" LOC = "V11" ; +NET "cpld_init_b" LOC = "W12" ; +NET "cpld_misc" LOC = "Y12" ; +NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; +NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; +NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; +NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; +NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; +NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; +NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; +NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; +NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; +NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; +NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; +NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; +NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; +NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; +NET "adc_ovf_a" LOC = "F18" ; +NET "adc_oen_a" LOC = "E19" ; +NET "adc_pdn_a" LOC = "E20" ; +NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; +NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; +NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; +NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; +NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; +NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; +NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; +NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; +NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; +NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; +NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; +NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; +NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; +NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; +NET "adc_ovf_b" LOC = "B17" ; +NET "adc_oen_b" LOC = "C17" ; +NET "adc_pdn_b" LOC = "D15" ; +NET "dac_a[0]" LOC = "A5" ; +NET "dac_a[1]" LOC = "B5" ; +NET "dac_a[2]" LOC = "C5" ; +NET "dac_a[3]" LOC = "D5" ; +NET "dac_a[4]" LOC = "A4" ; +NET "dac_a[5]" LOC = "B4" ; +NET "dac_a[6]" LOC = "F6" ; +NET "dac_a[7]" LOC = "D10" ; +NET "dac_a[8]" LOC = "D9" ; +NET "dac_a[9]" LOC = "A10" ; +NET "dac_a[10]" LOC = "L2" ; +NET "dac_a[11]" LOC = "L4" ; +NET "dac_a[12]" LOC = "L3" ; +NET "dac_a[13]" LOC = "L6" ; +NET "dac_a[14]" LOC = "L5" ; +NET "dac_a[15]" LOC = "K2" ; +NET "dac_b[0]" LOC = "D11" ; +NET "dac_b[1]" LOC = "E11" ; +NET "dac_b[2]" LOC = "F11" ; +NET "dac_b[3]" LOC = "B10" ; +NET "dac_b[4]" LOC = "C10" ; +NET "dac_b[5]" LOC = "E10" ; +NET "dac_b[6]" LOC = "F10" ; +NET "dac_b[7]" LOC = "A9" ; +NET "dac_b[8]" LOC = "B9" ; +NET "dac_b[9]" LOC = "E9" ; +NET "dac_b[10]" LOC = "F9" ; +NET "dac_b[11]" LOC = "A8" ; +NET "dac_b[12]" LOC = "B8" ; +NET "dac_b[13]" LOC = "D7" ; +NET "dac_b[14]" LOC = "E7" ; +NET "dac_b[15]" LOC = "B6" ; +NET "dac_lock" LOC = "D6" ; +NET "SCL" LOC = "A7" ; +NET "SDA" LOC = "D8" ; +NET "clk_en[0]" LOC = "C4" ; +NET "clk_en[1]" LOC = "D1" ; +NET "clk_sel[0]" LOC = "C3" ; +NET "clk_sel[1]" LOC = "C2" ; +NET "clk_func" LOC = "C12" ; +NET "clk_status" LOC = "B12" ; +NET "clk_fpga_p" LOC = "A11" ; +NET "clk_fpga_n" LOC = "B11" ; +NET "clk_to_mac" LOC = "AB12" ; +NET "pps_in" LOC = "Y11" ; +NET "sclk" LOC = "K5" ; +NET "sen_clk" LOC = "K6" ; +NET "sen_dac" LOC = "L1" ; +NET "sdi" LOC = "J1" ; +NET "sdo" LOC = "J2" ; +NET "sen_tx_db" LOC = "C1" ; +NET "sclk_tx_db" LOC = "D3" ; +NET "sdo_tx_db" LOC = "G3" ; +NET "sdi_tx_db" LOC = "G4" ; +NET "sen_tx_adc" LOC = "G2" ; +NET "sclk_tx_adc" LOC = "H1" ; +NET "sdo_tx_adc" LOC = "H2" ; +NET "sdi_tx_adc" LOC = "J4" ; +NET "sen_tx_dac" LOC = "H4" ; +NET "sclk_tx_dac" LOC = "J5" ; +NET "sdi_tx_dac" LOC = "J6" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; +NET "sen_rx_db" LOC = "D22" ; +NET "sclk_rx_db" LOC = "F19" ; +NET "sdo_rx_db" LOC = "G20" ; +NET "sdi_rx_db" LOC = "H19" ; +NET "sen_rx_adc" LOC = "H18" ; +NET "sclk_rx_adc" LOC = "J17" ; +NET "sdo_rx_adc" LOC = "H21" ; +NET "sdi_rx_adc" LOC = "H22" ; +NET "sen_rx_dac" LOC = "J18" ; +NET "sclk_rx_dac" LOC = "J19" ; +NET "sdi_rx_dac" LOC = "J21" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +#NET "dsp_clk" TNM_NET = "dsp_clk"; +#TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +#NET "wb_clk" TNM_NET = "wb_clk"; +#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %; + +NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; +NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/usrp2/fpga/top/u2_rev2/u2_rev2.v b/usrp2/fpga/top/u2_rev2/u2_rev2.v new file mode 100644 index 00000000..65d3ad65 --- /dev/null +++ b/usrp2/fpga/top/u2_rev2/u2_rev2.v @@ -0,0 +1,413 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2_rev2 + ( + // Misc, debug + output [4:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_pps_in_p, // Diff + input exp_pps_in_n, // Diff + output exp_pps_out_p, // Diff + output exp_pps_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, // AA9 + output cpld_mode, // U12 + output cpld_done, // V12 + input cpld_din, // AA14 Now shared with CFG_Din + input cpld_clk, // AB14 serial clock + input cpld_detached,// V11 unused + output cpld_init_b, // W12 unused dual purpose + input cpld_misc, // Y12 unused + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output reg [15:0] dac_a, + output reg [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input clk_to_mac, + input pps_in, + + // Generic SPI + output sclk, + output sen_clk, + output sen_dac, + output sdi, + input sdo, + + // TX DBoard + output sen_tx_db, + output sclk_tx_db, + input sdo_tx_db, + output sdi_tx_db, + + output sen_tx_adc, + output sclk_tx_adc, + input sdo_tx_adc, + output sdi_tx_adc, + + output sen_tx_dac, + output sclk_tx_dac, + output sdi_tx_dac, + + inout [15:0] io_tx, + + // RX DBoard + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + inout [15:0] io_rx + ); + + assign cpld_init_b = 0; + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + wire clk90, clk180, clk270; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_pps_in; + IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); + defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_pps_out; + OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); + defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_a; + adc_b_reg1 <= adc_b; + adc_ovf_a_reg1 <= adc_ovf_a; + adc_ovf_b_reg1 <= adc_ovf_b; + end + + always @(posedge dsp_clk) + begin + adc_a_reg2 <= adc_a_reg1; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(clk90), + .CLK180(clk180), + .CLK270(clk270), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = 5'b01111 ^ leds_int; // all except eth are active-low + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + wire [15:0] dac_a_int, dac_b_int; + always @(negedge dsp_clk) dac_a <= dac_a_int; + always @(negedge dsp_clk) dac_b <= dac_b_int; + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + u2_core #(.RAM_SIZE(32768)) + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2_rev2 diff --git a/usrp2/fpga/top/u2_rev3/Makefile b/usrp2/fpga/top/u2_rev3/Makefile new file mode 100644 index 00000000..897b68d6 --- /dev/null +++ b/usrp2/fpga/top/u2_rev3/Makefile @@ -0,0 +1,244 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u2_rev3 +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family Spartan3 \ +device xc3s2000 \ +package fg456 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/buffer_int.v \ +control_lib/buffer_pool.v \ +control_lib/cascadefifo2.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/extram_interface.v \ +control_lib/fifo_2clock.v \ +control_lib/fifo_2clock_casc.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/longfifo.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +eth/mac_rxfifo_int.v \ +eth/mac_txfifo_int.v \ +eth/rtl/verilog/Clk_ctrl.v \ +eth/rtl/verilog/MAC_rx.v \ +eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ +eth/rtl/verilog/MAC_rx/CRC_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ +eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ +eth/rtl/verilog/MAC_top.v \ +eth/rtl/verilog/MAC_tx.v \ +eth/rtl/verilog/MAC_tx/CRC_gen.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ +eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ +eth/rtl/verilog/MAC_tx/Random_gen.v \ +eth/rtl/verilog/Phy_int.v \ +eth/rtl/verilog/RMON.v \ +eth/rtl/verilog/RMON/RMON_addr_gen.v \ +eth/rtl/verilog/RMON/RMON_ctrl.v \ +eth/rtl/verilog/Reg_int.v \ +eth/rtl/verilog/eth_miim.v \ +eth/rtl/verilog/flow_ctrl_rx.v \ +eth/rtl/verilog/flow_ctrl_tx.v \ +eth/rtl/verilog/miim/eth_clockgen.v \ +eth/rtl/verilog/miim/eth_outputcontrol.v \ +eth/rtl/verilog/miim/eth_shiftreg.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u2_rev3/u2_rev3.ucf \ +top/u2_rev3/u2_rev3.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/fpga/top/u2_rev3/u2_rev3.ucf b/usrp2/fpga/top/u2_rev3/u2_rev3.ucf new file mode 100644 index 00000000..255a298a --- /dev/null +++ b/usrp2/fpga/top/u2_rev3/u2_rev3.ucf @@ -0,0 +1,333 @@ +NET "leds[0]" LOC = "E8" ; +NET "leds[1]" LOC = "F7" ; +NET "leds[2]" LOC = "E5" ; +NET "leds[3]" LOC = "B7" ; +NET "leds[4]" LOC = "C11" ; +NET "leds[5]" LOC = "AB19" ; +NET "debug[0]" LOC = "N5" ; +NET "debug[1]" LOC = "N6" ; +NET "debug[2]" LOC = "P1" ; +NET "debug[3]" LOC = "P2" ; +NET "debug[4]" LOC = "P4" ; +NET "debug[5]" LOC = "P5" ; +NET "debug[6]" LOC = "R1" ; +NET "debug[7]" LOC = "R2" ; +NET "debug[8]" LOC = "P6" ; +NET "debug[9]" LOC = "R5" ; +NET "debug[10]" LOC = "R4" ; +NET "debug[11]" LOC = "T3" ; +NET "debug[12]" LOC = "U3" ; +NET "debug[13]" LOC = "M2" ; +NET "debug[14]" LOC = "M3" ; +NET "debug[15]" LOC = "M4" ; +NET "debug[16]" LOC = "M5" ; +NET "debug[17]" LOC = "M6" ; +NET "debug[18]" LOC = "N1" ; +NET "debug[19]" LOC = "N2" ; +NET "debug[20]" LOC = "N3" ; +NET "debug[21]" LOC = "T1" ; +NET "debug[22]" LOC = "T2" ; +NET "debug[23]" LOC = "U2" ; +NET "debug[24]" LOC = "T4" ; +NET "debug[25]" LOC = "U4" ; +NET "debug[26]" LOC = "T5" ; +NET "debug[27]" LOC = "T6" ; +NET "debug[28]" LOC = "U5" ; +NET "debug[29]" LOC = "V5" ; +NET "debug[30]" LOC = "W2" ; +NET "debug[31]" LOC = "W3" ; +NET "debug_clk[0]" LOC = "N4" ; +NET "debug_clk[1]" LOC = "M1" ; +NET "uart_tx_o" LOC = "C7" ; +NET "uart_rx_i" LOC = "A3" ; +NET "exp_pps_in_p" LOC = "V3" ; +NET "exp_pps_in_n" LOC = "V4" ; +NET "exp_pps_out_p" LOC = "V1" ; +NET "exp_pps_out_n" LOC = "V2" ; +NET "GMII_COL" LOC = "U16" ; +NET "GMII_CRS" LOC = "U17" ; +NET "GMII_TXD[0]" LOC = "W14" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[1]" LOC = "AA20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[2]" LOC = "AB20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[3]" LOC = "Y18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[4]" LOC = "AA18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[5]" LOC = "AB18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[6]" LOC = "V17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TXD[7]" LOC = "W17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_EN" LOC = "Y17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_ER" LOC = "V16" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_GTX_CLK" LOC = "AA17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "GMII_TX_CLK" LOC = "W13" ; +NET "GMII_RXD[0]" LOC = "AA15" ; +NET "GMII_RXD[1]" LOC = "AB15" ; +NET "GMII_RXD[2]" LOC = "U14" ; +NET "GMII_RXD[3]" LOC = "V14" ; +NET "GMII_RXD[4]" LOC = "U13" ; +NET "GMII_RXD[5]" LOC = "V13" ; +NET "GMII_RXD[6]" LOC = "Y13" ; +NET "GMII_RXD[7]" LOC = "AA13" ; +NET "GMII_RX_CLK" LOC = "AA12" ; +NET "GMII_RX_DV" LOC = "AB16" ; +NET "GMII_RX_ER" LOC = "AA16" ; +NET "MDIO" LOC = "Y16" |PULLUP ; +NET "MDC" LOC = "V18" ; +NET "PHY_INTn" LOC = "AB13" ; +NET "PHY_RESETn" LOC = "AA19" ; +NET "PHY_CLK" LOC = "V15" ; +NET "RAM_D[0]" LOC = "N20" ; +NET "RAM_D[1]" LOC = "N21" ; +NET "RAM_D[2]" LOC = "N22" ; +NET "RAM_D[3]" LOC = "M17" ; +NET "RAM_D[4]" LOC = "M18" ; +NET "RAM_D[5]" LOC = "M19" ; +NET "RAM_D[6]" LOC = "M20" ; +NET "RAM_D[7]" LOC = "M21" ; +NET "RAM_D[8]" LOC = "M22" ; +NET "RAM_D[9]" LOC = "Y22" ; +NET "RAM_D[10]" LOC = "Y21" ; +NET "RAM_D[11]" LOC = "Y20" ; +NET "RAM_D[12]" LOC = "Y19" ; +NET "RAM_D[13]" LOC = "W22" ; +NET "RAM_D[14]" LOC = "W21" ; +NET "RAM_D[15]" LOC = "W20" ; +NET "RAM_D[16]" LOC = "W19" ; +NET "RAM_D[17]" LOC = "V22" ; +NET "RAM_A[0]" LOC = "U21" ; +NET "RAM_A[1]" LOC = "T19" ; +NET "RAM_A[2]" LOC = "V21" ; +NET "RAM_A[3]" LOC = "V20" ; +NET "RAM_A[4]" LOC = "T20" ; +NET "RAM_A[5]" LOC = "T21" ; +NET "RAM_A[6]" LOC = "T22" ; +NET "RAM_A[7]" LOC = "T18" ; +NET "RAM_A[8]" LOC = "R18" ; +NET "RAM_A[9]" LOC = "P19" ; +NET "RAM_A[10]" LOC = "P21" ; +NET "RAM_A[11]" LOC = "P22" ; +NET "RAM_A[12]" LOC = "N19" ; +NET "RAM_A[13]" LOC = "N17" ; +NET "RAM_A[14]" LOC = "N18" ; +NET "RAM_A[15]" LOC = "T17" ; +NET "RAM_A[16]" LOC = "U19" ; +NET "RAM_A[17]" LOC = "U18" ; +NET "RAM_A[18]" LOC = "V19" ; +NET "RAM_CE1n" LOC = "U20" ; +NET "RAM_CENn" LOC = "P18" ; +NET "RAM_CLK" LOC = "P17" ; +NET "RAM_WEn" LOC = "R22" ; +NET "RAM_OEn" LOC = "R21" ; +NET "RAM_LDn" LOC = "R19" ; +NET "ser_enable" LOC = "W11" ; +NET "ser_prbsen" LOC = "AA3" ; +NET "ser_loopen" LOC = "Y4" ; +NET "ser_rx_en" LOC = "AB9" ; +NET "ser_tx_clk" LOC = "U7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[0]" LOC = "V7" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[1]" LOC = "V10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[2]" LOC = "AB4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[3]" LOC = "AA4" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[4]" LOC = "Y5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[5]" LOC = "W5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[6]" LOC = "AB5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[7]" LOC = "AA5" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[8]" LOC = "W6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[9]" LOC = "V6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[10]" LOC = "AA6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[11]" LOC = "Y6" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[12]" LOC = "W8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[13]" LOC = "V8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[14]" LOC = "AB8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_t[15]" LOC = "AA8" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tklsb" LOC = "U10" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_tkmsb" LOC = "U11" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ; +NET "ser_rx_clk" LOC = "AA11" ; +NET "ser_r[0]" LOC = "AB10" ; +NET "ser_r[1]" LOC = "AA10" ; +NET "ser_r[2]" LOC = "U9" ; +NET "ser_r[3]" LOC = "U6" ; +NET "ser_r[4]" LOC = "AB11" ; +NET "ser_r[5]" LOC = "Y7" ; +NET "ser_r[6]" LOC = "W7" ; +NET "ser_r[7]" LOC = "AB7" ; +NET "ser_r[8]" LOC = "AA7" ; +NET "ser_r[9]" LOC = "W9" ; +NET "ser_r[10]" LOC = "W10" ; +NET "ser_r[11]" LOC = "Y1" ; +NET "ser_r[12]" LOC = "Y3" ; +NET "ser_r[13]" LOC = "Y2" ; +NET "ser_r[14]" LOC = "W4" ; +NET "ser_r[15]" LOC = "W1" ; +NET "ser_rklsb" LOC = "V9" ; +NET "ser_rkmsb" LOC = "Y10" ; +NET "cpld_start" LOC = "AA9" ; +NET "cpld_mode" LOC = "U12" ; +NET "cpld_done" LOC = "V12" ; +NET "cpld_din" LOC = "AA14" ; +NET "cpld_clk" LOC = "AB14" ; +NET "cpld_detached" LOC = "V11" ; +NET "cpld_init_b" LOC = "W12" ; +NET "cpld_misc" LOC = "Y12" ; +NET "POR" LOC = "W18" ; +NET "WDI" LOC = "W15" ; +NET "adc_a[0]" LOC = "A14" | IOBDELAY= "NONE" ; +NET "adc_a[1]" LOC = "B14" | IOBDELAY= "NONE" ; +NET "adc_a[2]" LOC = "C13" | IOBDELAY= "NONE" ; +NET "adc_a[3]" LOC = "D13" | IOBDELAY= "NONE" ; +NET "adc_a[4]" LOC = "A13" | IOBDELAY= "NONE" ; +NET "adc_a[5]" LOC = "B13" | IOBDELAY= "NONE" ; +NET "adc_a[6]" LOC = "E12" | IOBDELAY= "NONE" ; +NET "adc_a[7]" LOC = "C22" | IOBDELAY= "NONE" ; +NET "adc_a[8]" LOC = "C20" | IOBDELAY= "NONE" ; +NET "adc_a[9]" LOC = "C21" | IOBDELAY= "NONE" ; +NET "adc_a[10]" LOC = "D20" | IOBDELAY= "NONE" ; +NET "adc_a[11]" LOC = "D19" | IOBDELAY= "NONE" ; +NET "adc_a[12]" LOC = "D21" | IOBDELAY= "NONE" ; +NET "adc_a[13]" LOC = "E18" | IOBDELAY= "NONE" ; +NET "adc_ovf_a" LOC = "F18" ; +NET "adc_oen_a" LOC = "E19" ; +NET "adc_pdn_a" LOC = "E20" ; +NET "adc_b[0]" LOC = "A12" | IOBDELAY= "NONE"; +NET "adc_b[1]" LOC = "E16" | IOBDELAY= "NONE" ; +NET "adc_b[2]" LOC = "F12" | IOBDELAY= "NONE" ; +NET "adc_b[3]" LOC = "F13" | IOBDELAY= "NONE" ; +NET "adc_b[4]" LOC = "F16" | IOBDELAY= "NONE" ; +NET "adc_b[5]" LOC = "F17" | IOBDELAY= "NONE" ; +NET "adc_b[6]" LOC = "C19" | IOBDELAY= "NONE" ; +NET "adc_b[7]" LOC = "B20" | IOBDELAY= "NONE" ; +NET "adc_b[8]" LOC = "B19" | IOBDELAY= "NONE" ; +NET "adc_b[9]" LOC = "C18" | IOBDELAY= "NONE" ; +NET "adc_b[10]" LOC = "D18" | IOBDELAY= "NONE" ; +NET "adc_b[11]" LOC = "B18" | IOBDELAY= "NONE" ; +NET "adc_b[12]" LOC = "D17" | IOBDELAY= "NONE" ; +NET "adc_b[13]" LOC = "E17" | IOBDELAY= "NONE" ; +NET "adc_ovf_b" LOC = "B17" ; +NET "adc_oen_b" LOC = "C17" ; +NET "adc_pdn_b" LOC = "D15" ; +NET "dac_a[0]" LOC = "A5" ; +NET "dac_a[1]" LOC = "B5" ; +NET "dac_a[2]" LOC = "C5" ; +NET "dac_a[3]" LOC = "D5" ; +NET "dac_a[4]" LOC = "A4" ; +NET "dac_a[5]" LOC = "B4" ; +NET "dac_a[6]" LOC = "F6" ; +NET "dac_a[7]" LOC = "D10" ; +NET "dac_a[8]" LOC = "D9" ; +NET "dac_a[9]" LOC = "A10" ; +NET "dac_a[10]" LOC = "L2" ; +NET "dac_a[11]" LOC = "L4" ; +NET "dac_a[12]" LOC = "L3" ; +NET "dac_a[13]" LOC = "L6" ; +NET "dac_a[14]" LOC = "L5" ; +NET "dac_a[15]" LOC = "K2" ; +NET "dac_b[0]" LOC = "D11" ; +NET "dac_b[1]" LOC = "E11" ; +NET "dac_b[2]" LOC = "F11" ; +NET "dac_b[3]" LOC = "B10" ; +NET "dac_b[4]" LOC = "C10" ; +NET "dac_b[5]" LOC = "E10" ; +NET "dac_b[6]" LOC = "F10" ; +NET "dac_b[7]" LOC = "A9" ; +NET "dac_b[8]" LOC = "B9" ; +NET "dac_b[9]" LOC = "E9" ; +NET "dac_b[10]" LOC = "F9" ; +NET "dac_b[11]" LOC = "A8" ; +NET "dac_b[12]" LOC = "B8" ; +NET "dac_b[13]" LOC = "D7" ; +NET "dac_b[14]" LOC = "E7" ; +NET "dac_b[15]" LOC = "B6" ; +NET "dac_lock" LOC = "D6" ; +NET "SCL" LOC = "A7" ; +NET "SDA" LOC = "D8" ; +NET "clk_en[0]" LOC = "C4" ; +NET "clk_en[1]" LOC = "D1" ; +NET "clk_sel[0]" LOC = "C3" ; +NET "clk_sel[1]" LOC = "C2" ; +NET "clk_func" LOC = "C12" ; +NET "clk_status" LOC = "B12" ; +NET "clk_fpga_p" LOC = "A11" ; +NET "clk_fpga_n" LOC = "B11" ; +NET "clk_to_mac" LOC = "AB12" ; +NET "pps_in" LOC = "K1" ; +NET "sclk" LOC = "K5" ; +NET "sen_clk" LOC = "K6" ; +NET "sen_dac" LOC = "L1" ; +NET "sdi" LOC = "J1" ; +NET "sdo" LOC = "J2" ; +NET "sen_tx_db" LOC = "C1" ; +NET "sclk_tx_db" LOC = "D3" ; +NET "sdo_tx_db" LOC = "G3" ; +NET "sdi_tx_db" LOC = "G4" ; +NET "sen_tx_adc" LOC = "G2" ; +NET "sclk_tx_adc" LOC = "H1" ; +NET "sdo_tx_adc" LOC = "H2" ; +NET "sdi_tx_adc" LOC = "J4" ; +NET "sen_tx_dac" LOC = "H4" ; +NET "sclk_tx_dac" LOC = "J5" ; +NET "sdi_tx_dac" LOC = "J6" ; +NET "io_tx[0]" LOC = "K4" ; +NET "io_tx[1]" LOC = "K3" ; +NET "io_tx[2]" LOC = "G1" ; +NET "io_tx[3]" LOC = "G5" ; +NET "io_tx[4]" LOC = "H5" ; +NET "io_tx[5]" LOC = "F3" ; +NET "io_tx[6]" LOC = "F2" ; +NET "io_tx[7]" LOC = "F5" ; +NET "io_tx[8]" LOC = "G6" ; +NET "io_tx[9]" LOC = "E2" ; +NET "io_tx[10]" LOC = "E1" ; +NET "io_tx[11]" LOC = "E3" ; +NET "io_tx[12]" LOC = "F4" ; +NET "io_tx[13]" LOC = "D2" ; +NET "io_tx[14]" LOC = "D4" ; +NET "io_tx[15]" LOC = "E4" ; +NET "sen_rx_db" LOC = "D22" ; +NET "sclk_rx_db" LOC = "F19" ; +NET "sdo_rx_db" LOC = "G20" ; +NET "sdi_rx_db" LOC = "H19" ; +NET "sen_rx_adc" LOC = "H18" ; +NET "sclk_rx_adc" LOC = "J17" ; +NET "sdo_rx_adc" LOC = "H21" ; +NET "sdi_rx_adc" LOC = "H22" ; +NET "sen_rx_dac" LOC = "J18" ; +NET "sclk_rx_dac" LOC = "J19" ; +NET "sdi_rx_dac" LOC = "J21" ; +NET "io_rx[0]" LOC = "L21" ; +NET "io_rx[1]" LOC = "L20" ; +NET "io_rx[2]" LOC = "L19" ; +NET "io_rx[3]" LOC = "L18" ; +NET "io_rx[4]" LOC = "L17" ; +NET "io_rx[5]" LOC = "K22" ; +NET "io_rx[6]" LOC = "K21" ; +NET "io_rx[7]" LOC = "K20" ; +NET "io_rx[8]" LOC = "G22" ; +NET "io_rx[9]" LOC = "G21" ; +NET "io_rx[10]" LOC = "F21" ; +NET "io_rx[11]" LOC = "F20" ; +NET "io_rx[12]" LOC = "G19" ; +NET "io_rx[13]" LOC = "G18" ; +NET "io_rx[14]" LOC = "G17" ; +NET "io_rx[15]" LOC = "E22" ; + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "clk_fpga_p" TNM_NET = "clk_fpga_p"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + +NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE; + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; diff --git a/usrp2/fpga/top/u2_rev3/u2_rev3.v b/usrp2/fpga/top/u2_rev3/u2_rev3.v new file mode 100644 index 00000000..c1a81a96 --- /dev/null +++ b/usrp2/fpga/top/u2_rev3/u2_rev3.v @@ -0,0 +1,426 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2_rev3 + ( + // Misc, debug + output [5:0] leds, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_pps_in_p, // Diff + input exp_pps_in_n, // Diff + output exp_pps_out_p, // Diff + output exp_pps_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + + // RAM + inout [17:0] RAM_D, + output [18:0] RAM_A, + output RAM_CE1n, + output RAM_CENn, + output RAM_CLK, + output RAM_WEn, + output RAM_OEn, + output RAM_LDn, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // CPLD interface + output cpld_start, // AA9 + output cpld_mode, // U12 + output cpld_done, // V12 + input cpld_din, // AA14 Now shared with CFG_Din + input cpld_clk, // AB14 serial clock + input cpld_detached,// V11 unused + output cpld_init_b, // W12 unused dual purpose + input cpld_misc, // Y12 unused + + // Watchdog interface + input POR, + output WDI, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output reg [15:0] dac_a, + output reg [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input clk_to_mac, + input pps_in, + + // Generic SPI + output sclk, + output sen_clk, + output sen_dac, + output sdi, + input sdo, + + // TX DBoard + output sen_tx_db, + output sclk_tx_db, + input sdo_tx_db, + output sdi_tx_db, + + output sen_tx_adc, + output sclk_tx_adc, + input sdo_tx_adc, + output sdi_tx_adc, + + output sen_tx_dac, + output sclk_tx_dac, + output sdi_tx_dac, + + inout [15:0] io_tx, + + // RX DBoard + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + inout [15:0] io_rx + ); + + assign cpld_init_b = 0; + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + wire clk90, clk180, clk270; + + // reset the watchdog continuously + reg [15:0] wd; + always @(posedge wb_clk) + if(POR) + wd <= 0; + else + wd <= wd + 1; + assign WDI = wd[15]; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_pps_in; + IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); + defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_pps_out; + OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); + defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge clk_fpga) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; + reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; + + always @(posedge dsp_clk) + begin + adc_a_reg1 <= adc_a; + adc_b_reg1 <= adc_b; + adc_ovf_a_reg1 <= adc_ovf_a; + adc_ovf_b_reg1 <= adc_ovf_b; + end + + always @(posedge dsp_clk) + begin + adc_a_reg2 <= adc_a_reg1; + adc_b_reg2 <= adc_b_reg1; + adc_ovf_a_reg2 <= adc_ovf_a_reg1; + adc_ovf_b_reg2 <= adc_ovf_b_reg1; + end // always @ (posedge dsp_clk) + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(clk90), + .CLK180(clk180), + .CLK270(clk270), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [5:0] leds_int; + assign leds = 6'b011111 ^ leds_int; // all except eth are active-low + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + wire [15:0] dac_a_int, dac_b_int; + always @(negedge dsp_clk) dac_a <= dac_a_int; + always @(negedge dsp_clk) dac_b <= dac_b_int; + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + u2_core #(.RAM_SIZE(32768)) + u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a_reg2), + .adc_ovf_a (adc_ovf_a_reg2), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b_reg2), + .adc_ovf_b (adc_ovf_b_reg2), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a_int), + .dac_b (dac_b_int), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2_rev2 diff --git a/usrp2/fpga/top/u2plus/u2plus.ucf b/usrp2/fpga/top/u2plus/u2plus.ucf new file mode 100755 index 00000000..3f71d0b1 --- /dev/null +++ b/usrp2/fpga/top/u2plus/u2plus.ucf @@ -0,0 +1,280 @@ +NET "leds[0]" LOC = "A17" ; +NET "leds[1]" LOC = "B20" ; +NET "leds[2]" LOC = "D13" ; +NET "leds[3]" LOC = "A14" ; +NET "leds[4]" LOC = "W15" ; +NET "dipsw[0]" LOC = "C11" ; +NET "dipsw[1]" LOC = "F12" ; +NET "dipsw[2]" LOC = "E17" ; +NET "dipsw[3]" LOC = "E10" ; +NET "debug[0]" LOC = "AB19" ; +NET "debug[1]" LOC = "AA19" ; +NET "debug[2]" LOC = "U14" ; +NET "debug[3]" LOC = "U15" ; +NET "debug[4]" LOC = "AB17" ; +NET "debug[5]" LOC = "AB18" ; +NET "debug[6]" LOC = "Y13" ; +NET "debug[7]" LOC = "W14" ; +NET "debug[8]" LOC = "U13" ; +NET "debug[9]" LOC = "AA15" ; +NET "debug[10]" LOC = "AB14" ; +NET "debug[11]" LOC = "Y8" ; +NET "debug[12]" LOC = "Y9" ; +NET "debug[13]" LOC = "V7" ; +NET "debug[14]" LOC = "U8" ; +NET "debug[15]" LOC = "V10" ; +NET "debug[16]" LOC = "U9" ; +NET "debug[17]" LOC = "AB7" ; +NET "debug[18]" LOC = "AA8" ; +NET "debug[19]" LOC = "W8" ; +NET "debug[20]" LOC = "V8" ; +NET "debug[21]" LOC = "AB5" ; +NET "debug[22]" LOC = "AB6" ; +NET "debug[23]" LOC = "AB4" ; +NET "debug[24]" LOC = "AA4" ; +NET "debug[25]" LOC = "W5" ; +NET "debug[26]" LOC = "Y4" ; +NET "debug[27]" LOC = "V11" ; +NET "debug[28]" LOC = "U10" ; +NET "debug[29]" LOC = "AB10" ; +NET "debug[30]" LOC = "AA10" ; +NET "debug[31]" LOC = "Y5" ; +NET "debug_clk[0]" LOC = "V16" ; +NET "debug_clk[1]" LOC = "U16" ; +NET "uart_tx_o" LOC = "C19" ; +NET "uart_rx_i" LOC = "A20" ; +NET "exp_pps_in_p" LOC = "AA17" ; +NET "exp_pps_in_n" LOC = "AB16" ; +NET "exp_pps_out_p" LOC = "Y18" ; +NET "exp_pps_out_n" LOC = "Y19" ; +NET "GMII_COL" LOC = "J19" ; +NET "GMII_CRS" LOC = "E22" ; +NET "GMII_TXD[0]" LOC = "F22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[1]" LOC = "G18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[2]" LOC = "G17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[3]" LOC = "E20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[4]" LOC = "F21" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[5]" LOC = "E19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[6]" LOC = "D20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TXD[7]" LOC = "D22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TX_EN" LOC = "D21" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TX_ER" LOC = "F19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_GTX_CLK" LOC = "F18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "GMII_TX_CLK" LOC = "L20" ; +NET "GMII_RXD[0]" LOC = "K17" ; +NET "GMII_RXD[1]" LOC = "L18" ; +NET "GMII_RXD[2]" LOC = "J22" ; +NET "GMII_RXD[3]" LOC = "J21" ; +NET "GMII_RXD[4]" LOC = "G20" ; +NET "GMII_RXD[5]" LOC = "H21" ; +NET "GMII_RXD[6]" LOC = "C21" ; +NET "GMII_RXD[7]" LOC = "C22" ; +NET "GMII_RX_CLK" LOC = "L21" ; +NET "GMII_RX_DV" LOC = "G19" ; +NET "GMII_RX_ER" LOC = "F20" ; +NET "MDIO" LOC = "H22" | PULLUP ; +NET "MDC" LOC = "G22" ; +NET "PHY_INTn" LOC = "H20" ; +NET "PHY_RESETn" LOC = "J17" ; +NET "PHY_CLK" LOC = "M18" ; +NET "clk_to_mac" LOC = "L17" ; +NET "eth_led" LOC = "K16" ; +NET "ser_enable" LOC = "Y21" ; +NET "ser_prbsen" LOC = "U19" ; +NET "ser_loopen" LOC = "U18" ; +NET "ser_rx_en" LOC = "AA22" ; +NET "ser_tx_clk" LOC = "J20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[0]" LOC = "U20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[1]" LOC = "R18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[2]" LOC = "P19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[3]" LOC = "U22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[4]" LOC = "P16" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[5]" LOC = "N17" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[6]" LOC = "P22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[7]" LOC = "R22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[8]" LOC = "N19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[9]" LOC = "N20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[10]" LOC = "M22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[11]" LOC = "N22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[12]" LOC = "K22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[13]" LOC = "L22" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[14]" LOC = "K18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_t[15]" LOC = "K19" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_tklsb" LOC = "K20" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_tkmsb" LOC = "H18" | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = FAST ; +NET "ser_rx_clk" LOC = "N21" ; +NET "ser_r[0]" LOC = "T22" ; +NET "ser_r[1]" LOC = "W20" ; +NET "ser_r[2]" LOC = "W21" ; +NET "ser_r[3]" LOC = "U21" ; +NET "ser_r[4]" LOC = "V22" ; +NET "ser_r[5]" LOC = "P17" ; +NET "ser_r[6]" LOC = "R17" ; +NET "ser_r[7]" LOC = "P20" ; +NET "ser_r[8]" LOC = "R21" ; +NET "ser_r[9]" LOC = "V20" ; +NET "ser_r[10]" LOC = "W19" ; +NET "ser_r[11]" LOC = "T17" ; +NET "ser_r[12]" LOC = "T18" ; +NET "ser_r[13]" LOC = "Y22" ; +NET "ser_r[14]" LOC = "W22" ; +NET "ser_r[15]" LOC = "R20" ; +NET "ser_rklsb" LOC = "R19" ; +NET "ser_rkmsb" LOC = "T20" ; +NET "adc_a[0]" LOC = "P3" ; +NET "adc_a[1]" LOC = "N3" ; +NET "adc_a[2]" LOC = "AA1" ; +NET "adc_a[3]" LOC = "Y2" ; +NET "adc_a[4]" LOC = "C5" ; +NET "adc_a[5]" LOC = "E6" ; +NET "adc_a[6]" LOC = "C7" ; +NET "adc_a[7]" LOC = "E8" ; +NET "adc_a[8]" LOC = "F8" ; +NET "adc_a[9]" LOC = "A4" ; +NET "adc_a[10]" LOC = "B4" ; +NET "adc_a[11]" LOC = "C4" ; +NET "adc_a[12]" LOC = "D5" ; +NET "adc_a[13]" LOC = "A3" ; +NET "adc_ovf_a" LOC = "B3" ; +NET "adc_oen_a" LOC = "A6" ; +NET "adc_pdn_a" LOC = "D7" ; +NET "adc_b[0]" LOC = "J1" ; +NET "adc_b[1]" LOC = "M1" ; +NET "adc_b[2]" LOC = "P4" ; +NET "adc_b[3]" LOC = "E1" ; +NET "adc_b[4]" LOC = "D1" ; +NET "adc_b[5]" LOC = "D4" ; +NET "adc_b[6]" LOC = "D3" ; +NET "adc_b[7]" LOC = "J7" ; +NET "adc_b[8]" LOC = "J6" ; +NET "adc_b[9]" LOC = "J4" ; +NET "adc_b[10]" LOC = "J3" ; +NET "adc_b[11]" LOC = "N4" ; +NET "adc_b[12]" LOC = "M3" ; +NET "adc_b[13]" LOC = "U3" ; +NET "adc_ovf_b" LOC = "T3" ; +NET "adc_oen_b" LOC = "B6" ; +NET "adc_pdn_b" LOC = "A5" ; +NET "dac_a[0]" LOC = "N5" ; +NET "dac_a[1]" LOC = "N1" ; +NET "dac_a[2]" LOC = "K2" ; +NET "dac_a[3]" LOC = "K3" ; +NET "dac_a[4]" LOC = "K6" ; +NET "dac_a[5]" LOC = "L5" ; +NET "dac_a[6]" LOC = "H2" ; +NET "dac_a[7]" LOC = "K4" ; +NET "dac_a[8]" LOC = "K5" ; +NET "dac_a[9]" LOC = "G1" ; +NET "dac_a[10]" LOC = "H1" ; +NET "dac_a[11]" LOC = "H5" ; +NET "dac_a[12]" LOC = "H6" ; +NET "dac_a[13]" LOC = "E3" ; +NET "dac_a[14]" LOC = "E4" ; +NET "dac_a[15]" LOC = "G5" ; +NET "dac_b[0]" LOC = "G6" ; +NET "dac_b[1]" LOC = "F2" ; +NET "dac_b[2]" LOC = "F1" ; +NET "dac_b[3]" LOC = "H3" ; +NET "dac_b[4]" LOC = "H4" ; +NET "dac_b[5]" LOC = "F4" ; +NET "dac_b[6]" LOC = "F5" ; +NET "dac_b[7]" LOC = "C2" ; +NET "dac_b[8]" LOC = "C1" ; +NET "dac_b[9]" LOC = "F3" ; +NET "dac_b[10]" LOC = "G3" ; +NET "dac_b[11]" LOC = "M6" ; +NET "dac_b[12]" LOC = "N7" ; +NET "dac_b[13]" LOC = "L3" ; +NET "dac_b[14]" LOC = "M2" ; +NET "dac_b[15]" LOC = "K1" ; +NET "dac_lock" LOC = "L1" ; +NET "SCL" LOC = "B19" ; +NET "SDA" LOC = "B17" ; +NET "clk_en[0]" LOC = "AB20" ; +NET "clk_en[1]" LOC = "AA20" ; +NET "clk_sel[0]" LOC = "Y17" ; +NET "clk_sel[1]" LOC = "Y16" ; +NET "clk_func" LOC = "W13" ; +NET "clk_status" LOC = "W18" ; +NET "clk_fpga_p" LOC = "AA12" ; +NET "clk_fpga_n" LOC = "AB12" ; +NET "pps_in" LOC = "Y14" ; +NET "POR" LOC = "AB15" ; +NET "sclk" LOC = "AA14" ; +NET "sen_clk" LOC = "AB13" ; +NET "sdi" LOC = "V12" ; +NET "sdo" LOC = "U12" ; +NET "sen_dac" LOC = "W2" ; +NET "sen_tx_db" LOC = "W3" ; +NET "sen_tx_adc" LOC = "U5" ; +NET "sen_tx_dac" LOC = "U4" ; +NET "mosi_tx" LOC = "V4" ; +NET "miso_dac" LOC = "M5" ; +NET "miso_tx_db" LOC = "W1" ; +NET "miso_tx_adc" LOC = "Y1" ; +NET "sclk_tx" LOC = "V3" ; +NET "sen_rx_db" LOC = "B9" ; +NET "sclk_rx_db" LOC = "B8" ; +NET "sdo_rx_db" LOC = "A10" ; +NET "sdi_rx_db" LOC = "E12" ; +NET "sen_rx_adc" LOC = "A9" ; +NET "sclk_rx_adc" LOC = "A8" ; +NET "sdo_rx_adc" LOC = "A12" ; +NET "sdi_rx_adc" LOC = "A7" ; +NET "sen_rx_dac" LOC = "E11" ; +NET "sclk_rx_dac" LOC = "F10" ; +NET "sdi_rx_dac" LOC = "E7" ; +NET "io_tx[0]" LOC = "R3" ; +NET "io_tx[1]" LOC = "T4" ; +NET "io_tx[2]" LOC = "U2" ; +NET "io_tx[3]" LOC = "V1" ; +NET "io_tx[4]" LOC = "R5" ; +NET "io_tx[5]" LOC = "T1" ; +NET "io_tx[6]" LOC = "U1" ; +NET "io_tx[7]" LOC = "T6" ; +NET "io_tx[8]" LOC = "T5" ; +NET "io_tx[9]" LOC = "R2" ; +NET "io_tx[10]" LOC = "R1" ; +NET "io_tx[11]" LOC = "P6" ; +NET "io_tx[12]" LOC = "R6" ; +NET "io_tx[13]" LOC = "P1" ; +NET "io_tx[14]" LOC = "P2" ; +NET "io_tx[15]" LOC = "N6" ; + +NET "io_rx[0]" LOC = "G8" ; +NET "io_rx[1]" LOC = "F9" ; +NET "io_rx[2]" LOC = "C8" ; +NET "io_rx[3]" LOC = "D9" ; +NET "io_rx[4]" LOC = "C6" ; +NET "io_rx[5]" LOC = "D6" ; +NET "io_rx[6]" LOC = "C9" ; +NET "io_rx[7]" LOC = "D10" ; +NET "io_rx[8]" LOC = "B11" ; +NET "io_rx[9]" LOC = "A11" ; +NET "io_rx[10]" LOC = "C13" ; +NET "io_rx[11]" LOC = "C12" ; +NET "io_rx[12]" LOC = "F14" ; +NET "io_rx[13]" LOC = "F13" ; +NET "io_rx[14]" LOC = "D14" ; +NET "io_rx[15]" LOC = "A13" ; +NET "flash_cs" LOC = "U7" ; +NET "flash_clk" LOC = "V17" ; +NET "flash_mosi" LOC = "V13" ; +NET "flash_miso" LOC = "W17" ; + + +NET "clk_muxed" TNM_NET = "clk_muxed"; +TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %; + +NET "clk_to_mac" TNM_NET = "clk_to_mac"; +TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %; + +NET "cpld_clk" TNM_NET = "cpld_clk"; +TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %; + +NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK"; +TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %; + +NET "ser_rx_clk" TNM_NET = "ser_rx_clk"; +TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %; + diff --git a/usrp2/fpga/top/u2plus/u2plus.v b/usrp2/fpga/top/u2plus/u2plus.v new file mode 100644 index 00000000..e9544586 --- /dev/null +++ b/usrp2/fpga/top/u2plus/u2plus.v @@ -0,0 +1,377 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u2plus + ( + // Misc, debug + output [4:0] leds, // LED4 is shared w/INIT_B + input [3:0] dipsw, + output [31:0] debug, + output [1:0] debug_clk, + output uart_tx_o, + input uart_rx_i, + + // Expansion + input exp_pps_in_p, // Diff + input exp_pps_in_n, // Diff + output exp_pps_out_p, // Diff + output exp_pps_out_n, // Diff + + // GMII + // GMII-CTRL + input GMII_COL, + input GMII_CRS, + + // GMII-TX + output reg [7:0] GMII_TXD, + output reg GMII_TX_EN, + output reg GMII_TX_ER, + output GMII_GTX_CLK, + input GMII_TX_CLK, // 100mbps clk + + // GMII-RX + input [7:0] GMII_RXD, + input GMII_RX_CLK, + input GMII_RX_DV, + input GMII_RX_ER, + + // GMII-Management + inout MDIO, + output MDC, + input PHY_INTn, // open drain + output PHY_RESETn, + input PHY_CLK, // possibly use on-board osc + input clk_to_mac, + output eth_led, + + // SERDES + output ser_enable, + output ser_prbsen, + output ser_loopen, + output ser_rx_en, + + output ser_tx_clk, + output reg [15:0] ser_t, + output reg ser_tklsb, + output reg ser_tkmsb, + + input ser_rx_clk, + input [15:0] ser_r, + input ser_rklsb, + input ser_rkmsb, + + // ADC + input [13:0] adc_a, + input adc_ovf_a, + output adc_oen_a, + output adc_pdn_a, + + input [13:0] adc_b, + input adc_ovf_b, + output adc_oen_b, + output adc_pdn_b, + + // DAC + output [15:0] dac_a, + output [15:0] dac_b, + input dac_lock, // unused for now + + // I2C + inout SCL, + inout SDA, + + // Clock Gen Control + output [1:0] clk_en, + output [1:0] clk_sel, + input clk_func, // FIXME is an input to control the 9510 + input clk_status, + + // Clocks + input clk_fpga_p, // Diff + input clk_fpga_n, // Diff + input pps_in, + input POR, + + // AD9510 SPI + output sclk, + output sen_clk, + output sdi, + input sdo, + + // TX side SPI -- tx_db, tx_adc, tx_dac, 9777 + output sen_dac, + output sen_tx_db, + output sen_tx_adc, + output sen_tx_dac, + output mosi_tx, + input miso_dac, + input miso_tx_db, + input miso_tx_adc, + output sclk_tx, + + // RX side SPI + output sen_rx_db, + output sclk_rx_db, + input sdo_rx_db, + output sdi_rx_db, + + output sen_rx_adc, + output sclk_rx_adc, + input sdo_rx_adc, + output sdi_rx_adc, + + output sen_rx_dac, + output sclk_rx_dac, + output sdi_rx_dac, + + // DB IO Pins + inout [15:0] io_tx, + inout [15:0] io_rx, + + // SPI Flash + output flash_cs, + output flash_clk, + output flash_mosi, + input flash_miso + ); + + // FPGA-specific pins connections + wire aux_clk = PHY_CLK; + + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + wire exp_pps_in; + IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n)); + defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_pps_out; + OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out)); + defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25"; + + reg [5:0] clock_ready_d; + always @(posedge aux_clk) + clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready}; + + wire dcm_rst = ~&clock_ready_d & |clock_ready_d; + wire clk_muxed = clock_ready ? clk_fpga : aux_clk; + + wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b; + assign adc_oen_a = ~adc_oe_a; + assign adc_oen_b = ~adc_oe_b; + assign adc_pdn_a = ~adc_on_a; + assign adc_pdn_b = ~adc_on_b; + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_muxed), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = ~leds_int; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk_int; + assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0; + assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0; + + assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) | + (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) | + (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + /* + OFDDRRSE OFDDRRSE_serdes_inst + (.Q(ser_tx_clk), // Data output (connect directly to top-level port) + .C0(ser_tx_clk_int), // 0 degree clock input + .C1(~ser_tx_clk_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + */ + u2_core u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_pps_in), + .exp_pps_out (exp_pps_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .PHY_CLK (PHY_CLK), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (dac_a[15:0]), + .dac_b (dac_b[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + //.uart_rx_i (uart_rx_i), + .uart_rx_i (), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); + +endmodule // u2plus diff --git a/usrp2/host/Makefile.am b/usrp2/host/Makefile.am new file mode 100644 index 00000000..b6e30b5f --- /dev/null +++ b/usrp2/host/Makefile.am @@ -0,0 +1,29 @@ +# +# Copyright 2008 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +# + +include $(top_srcdir)/Makefile.common + +pkgconfigdir = $(libdir)/pkgconfig +pkgconfig_DATA = usrp2.pc + +EXTRA_DIST = \ + usrp2.pc.in + +SUBDIRS = include lib apps diff --git a/usrp2/host/apps/Makefile.am b/usrp2/host/apps/Makefile.am new file mode 100644 index 00000000..744dd570 --- /dev/null +++ b/usrp2/host/apps/Makefile.am @@ -0,0 +1,44 @@ +# +# Copyright 2007, 2008 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include $(top_srcdir)/Makefile.common + +AM_CPPFLAGS = \ + $(USRP2_INCLUDES) \ + $(STD_DEFINES_AND_INCLUDES) \ + $(CPPUNIT_INCLUDES) \ + $(GRUEL_INCLUDES) + +LDADD = \ + $(USRP2_LA) \ + $(GRUEL_LA) \ + $(OMNITHREAD_LA) + +bin_PROGRAMS = \ + find_usrps \ + usrp2_burn_mac_addr + +noinst_PROGRAMS = \ + gen_const \ + rx_streaming_samples \ + tx_samples + +find_usrps_SOURCES = find_usrps.cc +usrp2_burn_mac_addr_SOURCES = usrp2_burn_mac_addr.cc +rx_streaming_samples_SOURCES = rx_streaming_samples.cc +gen_const_SOURCES = gen_const.cc +tx_samples_SOURCES = tx_samples.cc diff --git a/usrp2/host/apps/find_usrps.cc b/usrp2/host/apps/find_usrps.cc new file mode 100644 index 00000000..1010c4af --- /dev/null +++ b/usrp2/host/apps/find_usrps.cc @@ -0,0 +1,70 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include + +static void +usage(const char *progname) +{ + fprintf(stderr, "usage: %s [-e ethN]\n", + progname); +} + +int +main(int argc, char **argv) +{ + int ch; + const char *interface = "eth0"; + + while ((ch = getopt(argc, argv, "he:")) != EOF){ + switch (ch){ + case 'e': + interface = optarg; + break; + + case 'h': + default: + usage(argv[0]); + exit(1); + } + } + + if (argc - optind != 0){ + usage(argv[0]); + exit(1); + } + + usrp2::props_vector_t r = usrp2::find(interface); + + for (size_t i = 0; i < r.size(); i++){ + std::cout << r[i] << std::endl; + } + + if (r.size() == 0){ + std::cerr << "No USRP2 found.\n"; + return 1; + } + + return 0; +} diff --git a/usrp2/host/apps/gen_2tone.py b/usrp2/host/apps/gen_2tone.py new file mode 100755 index 00000000..ec681d3e --- /dev/null +++ b/usrp2/host/apps/gen_2tone.py @@ -0,0 +1,75 @@ +#!/usr/bin/env python +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +from gnuradio import gr, eng_notation +from gnuradio.eng_option import eng_option +from optparse import OptionParser +import sys + +master_clock = 100e6 + +class my_top_block(gr.top_block): + + def __init__(self): + gr.top_block.__init__(self) + + parser = OptionParser(option_class=eng_option) + parser.add_option("-f", "--freq1", type="eng_float", default=1e6, + help="set waveform frequency to FREQ [default=%default]") + parser.add_option("-g", "--freq2", type="eng_float", default=1e6, + help="set waveform frequency to FREQ [default=%default]") + parser.add_option ("-a", "--amplitude1", type="eng_float", default=16e3, + help="set waveform amplitude to AMPLITUDE [default=%default]", metavar="AMPL") + parser.add_option ("-b", "--amplitude2", type="eng_float", default=16e3, + help="set waveform amplitude to AMPLITUDE [default=%default]", metavar="AMPL") + + parser.add_option("-i", "--interp", type="int", default=32, + help="assume fgpa interpolation rate is INTERP [default=%default]") + + (options, args) = parser.parse_args () + if len(args) != 0: + parser.print_help() + raise SystemExit, 1 + + + src0 = gr.sig_source_c(master_clock/options.interp, + gr.GR_SIN_WAVE, + options.freq1, + options.amplitude1) + src1 = gr.sig_source_c(master_clock/options.interp, + gr.GR_SIN_WAVE, + options.freq2, + options.amplitude2) + + adder = gr.add_cc() + + + c2s = gr.complex_to_interleaved_short() + + stdout_sink = gr.file_descriptor_sink(gr.sizeof_short, 1) + + self.connect(src0, (adder,0)) + self.connect(src1, (adder,1)) + self.connect(adder, c2s, stdout_sink) + + +if __name__ == '__main__': + try: + my_top_block().run() + except KeyboardInterrupt: + pass diff --git a/usrp2/host/apps/gen_const.cc b/usrp2/host/apps/gen_const.cc new file mode 100644 index 00000000..d2c36ebb --- /dev/null +++ b/usrp2/host/apps/gen_const.cc @@ -0,0 +1,27 @@ +#include +#include +#include +#include + +int +main(int argc, char **argv) +{ + if (argc != 3){ + fprintf(stderr, "usage: %s i-val q-val\n", argv[0]); + return 1; + } + + int i_val = strtol(argv[1], 0, 0); + int q_val = strtol(argv[2], 0, 0); + + static const int NSAMPLES = 16384; + + uint32_t sample[NSAMPLES]; + sample[0] = ((i_val & 0xffff) << 16) | (q_val & 0xffff); + for (int i = 1; i < NSAMPLES; i++) + sample[i] = sample[0]; + + while(1){ + write(1, sample, sizeof(sample)); + } +} diff --git a/usrp2/host/apps/gen_sine.py b/usrp2/host/apps/gen_sine.py new file mode 100755 index 00000000..6a44dd11 --- /dev/null +++ b/usrp2/host/apps/gen_sine.py @@ -0,0 +1,63 @@ +#!/usr/bin/env python +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +from gnuradio import gr, eng_notation +from gnuradio.eng_option import eng_option +from optparse import OptionParser +import sys + +master_clock = 100e6 + +class my_top_block(gr.top_block): + + def __init__(self): + gr.top_block.__init__(self) + + parser = OptionParser(option_class=eng_option) + parser.add_option("-f", "--freq", type="eng_float", default=1e6, + help="set waveform frequency to FREQ [default=%default]") + parser.add_option ("-a", "--amplitude", type="eng_float", default=16e3, + help="set waveform amplitude to AMPLITUDE [default=%default]", metavar="AMPL") + + parser.add_option("-i", "--interp", type="int", default=32, + help="assume fgpa interpolation rate is INTERP [default=%default]") + + (options, args) = parser.parse_args () + if len(args) != 0: + parser.print_help() + raise SystemExit, 1 + + + src0 = gr.sig_source_c(master_clock/options.interp, + gr.GR_SIN_WAVE, + options.freq, + options.amplitude) + + + c2s = gr.complex_to_interleaved_short() + + stdout_sink = gr.file_descriptor_sink(gr.sizeof_short, 1) + + self.connect(src0, c2s, stdout_sink) + + +if __name__ == '__main__': + try: + my_top_block().run() + except KeyboardInterrupt: + pass diff --git a/usrp2/host/apps/rx_samples.cc b/usrp2/host/apps/rx_samples.cc new file mode 100644 index 00000000..c1c3b591 --- /dev/null +++ b/usrp2/host/apps/rx_samples.cc @@ -0,0 +1,382 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include "usrp2_basic.h" +#include +#include +#include +#include +#include "strtod_si.h" +#include +#include +#include "gri_if_stats.h" +#include + + +typedef std::complex fcomplex; + +static volatile bool signaled = false; + +static void +sig_handler(int sig) +{ + signaled = true; +} + +static void +install_sig_handler(int signum, + void (*new_handler)(int)) +{ + struct sigaction new_action; + memset (&new_action, 0, sizeof (new_action)); + + new_action.sa_handler = new_handler; + sigemptyset (&new_action.sa_mask); + new_action.sa_flags = 0; + + if (sigaction (signum, &new_action, 0) < 0){ + perror ("sigaction (install new)"); + throw std::runtime_error ("sigaction"); + } +} + + +/* + * Vectorize me! + */ +void +convert_samples_to_complex(size_t nsamples, + uint32_t *i_samples, + fcomplex *c_samples) +{ + uint32_t *p = i_samples; + for (size_t i = 0; i < nsamples; i++){ + int16_t si = ((int16_t) (p[i] >> 16)); + int16_t sq = ((int16_t) (p[i] & 0xffff)); + c_samples[i] = fcomplex((float) si, (float) sq); + } +} + + +static void +usage(const char *progname) +{ + const char *p = strrchr(progname, '/'); // drop leading directory path + if (p) + p++; + + if (strncmp(p, "lt-", 3) == 0) // drop lt- libtool prefix + p += 3; + + fprintf(stderr, "Usage: %s [options]\n\n", p); + fprintf(stderr, "Options:\n"); + fprintf(stderr, " -h show this message and exit\n"); + fprintf(stderr, " -e ETH_INTERFACE specify ethernet interface [default=eth0]\n"); + fprintf(stderr, " -m MAC_ADDR mac address of USRP2 HH:HH [default=first one found]\n"); + fprintf(stderr, " -o OUTPUT_FILE set output filename [default=NONE]\n"); + fprintf(stderr, " -f FREQ set frequency to FREQ [default=0]\n"); + fprintf(stderr, " -d DECIM set decimation rate to DECIM [default=32]\n"); + fprintf(stderr, " -N NSAMPLES total number of samples to receive [default=2.5e6]\n"); + fprintf(stderr, " -F SAMPLES_PER_FRAME number of samples in each frame [default=371]\n"); + fprintf(stderr, " -S SCALE fpga scaling factor for I & Q [default=1024]\n"); + fprintf(stderr, " -M DONT_LOCK|LOCK_TO_SMA|LOCK_TO_MIMO specify MIMO clock source\n"); + fprintf(stderr, " -P provide clock to MIMO connector\n"); +} + +struct pkt_info { + int d_nsamples; + int d_timestamp; + unsigned int d_seqno; + + pkt_info(int nsamples, int timestamp, int seqno) + : d_nsamples(nsamples), + d_timestamp(timestamp), + d_seqno(seqno) {} +}; + +int +main(int argc, char **argv) +{ + + // options and their defaults + const char *interface = "eth0"; + const char *mac_addr_str = 0; + const char *output_filename = 0; + double freq = 0; + int32_t decim = 32; + int32_t nsamples = static_cast(2.5e6); + int32_t samples_per_frame = 371; + int32_t scale = 1024; + int mimo_config = MC_WE_DONT_LOCK; + bool provide_clock = false; + + int ch; + double tmp; + u2_mac_addr_t mac_addr; + + setvbuf(stdout, 0, _IOFBF, 64 * 1024); // make stdout fully buffered + + while ((ch = getopt(argc, argv, "he:m:o:f:d:N:F:S:M:P")) != EOF){ + switch (ch){ + + case 'e': + interface = optarg; + break; + + case 'm': + mac_addr_str = optarg; + if (!usrp2_basic::parse_mac_addr(optarg, &mac_addr)){ + std::cerr << "invalid mac addr: " << optarg << std::endl; + usage(argv[0]); + exit(1); + } + break; + + case 'o': + output_filename = optarg; + break; + + case 'f': + if (!strtod_si(optarg, &freq)){ + std::cerr << "invalid number: " << optarg << std::endl; + usage(argv[0]); + exit(1); + } + break; + + case 'N': + if (!strtod_si(optarg, &tmp)){ + std::cerr << "invalid number: " << optarg << std::endl; + usage(argv[0]); + exit(1); + } + nsamples = static_cast(tmp); + break; + + case 'F': + samples_per_frame = strtol(optarg, 0, 0); + break; + + case 'd': + decim = strtol(optarg, 0, 0); + break; + + case 'S': + if (!strtod_si(optarg, &tmp)){ + std::cerr << "invalid number: " << optarg << std::endl; + usage(argv[0]); + exit(1); + } + scale = static_cast(tmp); + break; + + case 'M': + if (strcmp(optarg, "DONT_LOCK") == 0) + mimo_config = MC_WE_DONT_LOCK; + else if (strcmp(optarg, "LOCK_TO_SMA") == 0) + mimo_config = MC_WE_LOCK_TO_SMA; + else if (strcmp(optarg, "LOCK_TO_MIMO") == 0) + mimo_config = MC_WE_LOCK_TO_MIMO; + else { + usage(argv[0]); + exit(1); + } + break; + + case 'P': + provide_clock = true; + break; + + case 'h': + default: + usage(argv[0]); + exit(1); + } + } + + if (argc - optind != 0){ + usage(argv[0]); + exit(1); + } + + FILE *of = 0; + if (output_filename) + of = fopen(output_filename, "wb"); + + usrp2_basic *u2 = new usrp2_basic(); + + if (!u2->open(interface)){ + std::cerr << "couldn't open " << interface << std::endl; + return 0; + } + + + install_sig_handler(SIGINT, sig_handler); + if (1){ + install_sig_handler(SIGALRM, sig_handler); + alarm(5); + } + + + std::vector r = u2->find_usrps(); + + for (size_t i = 0; i < r.size(); i++){ + std::cout << r[i] << std::endl; + } + + if (r.size() == 0){ + std::cerr << "No USRP2 found.\n"; + return 1; + } + + u2_mac_addr_t which = r[0].addr; // pick the first one + + + gr_rt_status_t rt = gr_enable_realtime_scheduling(); + if (rt != RT_OK) + std::cerr << "failed to enable realtime scheduling\n"; + + if (provide_clock) + mimo_config |= MC_PROVIDE_CLK_TO_MIMO; + + u2->config_mimo(which, mimo_confg); + + + gri_if_stats start, stop; + gri_get_if_stats(interface, &start); + + if (!u2->start_rx(which, freq, decim, nsamples, samples_per_frame, scale, scale)){ + std::cerr << "start_rx failed\n"; + return 1; + } + + + std::vector history; + history.reserve(64*1024); // preallocate 64K entries + + + long total_samples_recvd = 0; + + while (!signaled && total_samples_recvd < nsamples){ + u2_eth_samples_t pkt; + // fcomplex c_samples[U2_MAX_SAMPLES]; + + // read samples + int n = u2->read_samples(which, &pkt); + if (n <= 0) + break; + + total_samples_recvd += n; + + history.push_back(pkt_info(n, u2p_timestamp(&pkt.hdrs.fixed), pkt.hdrs.thdr.seqno)); + + // convert_samples_to_complex(n, pkt.samples, c_samples); + // size_t r = fwrite(c_samples, sizeof(fcomplex), n, of); + + if (of){ + fwrite(pkt.samples, sizeof(uint32_t), n, of); + fflush(of); + } + } + + + gri_get_if_stats(interface, &stop); + + if (!u2->stop_rx(which)){ + std::cerr << "stop_rx failed\n"; + return 1; + } + + + long expected_rx_packets = + (nsamples + samples_per_frame - 1)/samples_per_frame; + + long expected_rx_bytes = + expected_rx_packets * sizeof(u2_eth_packet_t) + nsamples * 4; + + + long total_pkts_recvd = 0; + total_samples_recvd = 0; + + int nbad_seqno = 0; + + for (unsigned i = 0; i < history.size(); i++){ + total_pkts_recvd++; + total_samples_recvd += history[i].d_nsamples; + + bool bad_seqno = history[i].d_seqno != (i & 0xff); + if (bad_seqno) + nbad_seqno++; + + printf("%3d %8d %8ld %8ld %3d %s\n", + history[i].d_nsamples, + history[i].d_timestamp, + total_pkts_recvd, total_samples_recvd, + history[i].d_seqno, + bad_seqno ? "BAD SEQNO" : "" + ); + } + + if (nbad_seqno == 0) + printf("\nAll sequence numbers are correct\n"); + else + printf("\n%d sequence numbers were INCORRECT\n", nbad_seqno); + + + printf("\nUser space statistics:\n"); + printf(" rx_samples: %8ld", total_samples_recvd); + printf(" expected %8d %s\n", + nsamples, + nsamples - total_samples_recvd == 0 ? "OK" : "NOT OK"); + + printf(" rx_packets: %8ld", total_pkts_recvd); + printf(" expected %8ld %s\n", + expected_rx_packets, + expected_rx_packets - total_pkts_recvd == 0 ? "OK" : "NOT OK"); + + + fflush(stdout); + + printf("\nKernel interface statistics:\n"); + + long long delta; + delta = stop.rx_bytes - start.rx_bytes; + printf(" rx_bytes: %8Ld", delta); + printf(" expected %8ld %s\n", + expected_rx_bytes, + expected_rx_bytes - delta == 0 ? "OK" : "NOT OK"); + + delta = stop.rx_packets - start.rx_packets; + printf(" rx_packets: %8Ld", delta); + printf(" expected %8ld %s\n", + expected_rx_packets, + expected_rx_packets - delta == 0 ? "OK" : "NOT OK"); + + printf(" rx_errs: %8Ld\n", stop.rx_errs - start.rx_errs); + printf(" rx_drop: %8Ld\n", stop.rx_drop - start.rx_drop); + printf(" tx_bytes: %8Ld\n", stop.tx_bytes - start.tx_bytes); + printf(" tx_packets: %8Ld\n", stop.tx_packets - start.tx_packets); + printf(" tx_errs: %8Ld\n", stop.tx_errs - start.tx_errs); + printf(" tx_drop: %8Ld\n", stop.tx_drop - start.tx_drop); + + + return 0; +} diff --git a/usrp2/host/apps/rx_streaming_samples.cc b/usrp2/host/apps/rx_streaming_samples.cc new file mode 100644 index 00000000..70f2c5d7 --- /dev/null +++ b/usrp2/host/apps/rx_streaming_samples.cc @@ -0,0 +1,372 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static volatile bool signaled = false; + +static void +sig_handler(int sig) +{ + signaled = true; +} + +static void +install_sig_handler(int signum, + void (*new_handler)(int)) +{ + struct sigaction new_action; + memset (&new_action, 0, sizeof (new_action)); + + new_action.sa_handler = new_handler; + sigemptyset (&new_action.sa_mask); + new_action.sa_flags = 0; + + if (sigaction (signum, &new_action, 0) < 0){ + perror ("sigaction (install new)"); + throw std::runtime_error ("sigaction"); + } +} + +// ------------------------------------------------------------------------ + +// FIXME make this a template + +class complex_16_file_writer : public usrp2::rx_nop_handler +{ + FILE *d_fp; + std::string d_filename; + +public: + + complex_16_file_writer(const std::string &filename, uint64_t max_samples) + : usrp2::rx_nop_handler(max_samples), d_filename(filename) + { + d_fp = fopen(filename.c_str(), "wb"); + if (d_fp == 0){ + perror(filename.c_str()); + throw std::invalid_argument(filename); + } + } + + ~complex_16_file_writer(); + + bool + operator()(const uint32_t *items, size_t nitems, const usrp2::rx_metadata *metadata) + { + bool ok = rx_nop_handler::operator()(items, nitems, metadata); + + size_t host_nitems = nitems; + std::complex host_items[host_nitems]; + + usrp2::copy_u2_complex_16_to_host_complex_16(nitems, items, host_items); + + size_t n = 0; + while (n < host_nitems){ + size_t r = fwrite(&host_items[n], sizeof(host_items[0]), host_nitems - n, d_fp); + n += r; + if (r == 0){ // out of space? + d_err = true; + perror(d_filename.c_str()); + ok = false; + break; + } + } + + return ok; + } +}; + +complex_16_file_writer::~complex_16_file_writer() +{ + fclose(d_fp); +} + +// ------------------------------------------------------------------------ + +class complex_float_file_writer : public usrp2::rx_nop_handler +{ + FILE *d_fp; + std::string d_filename; + +public: + + complex_float_file_writer(const std::string &filename, uint64_t max_samples) + : usrp2::rx_nop_handler(max_samples), d_filename(filename) + { + d_fp = fopen(filename.c_str(), "wb"); + if (d_fp == 0){ + perror(filename.c_str()); + throw std::invalid_argument(filename); + } + } + + ~complex_float_file_writer(); + + bool + operator()(const uint32_t *items, size_t nitems, const usrp2::rx_metadata *metadata) + { + bool ok = rx_nop_handler::operator()(items, nitems, metadata); + + size_t host_nitems = nitems; + std::complex host_items[host_nitems]; + + usrp2::copy_u2_complex_16_to_host_complex_float(nitems, items, host_items); + + size_t n = 0; + while (n < host_nitems){ + size_t r = fwrite(&host_items[n], sizeof(host_items[0]), host_nitems - n, d_fp); + n += r; + if (r == 0){ // out of space? + d_err = true; + perror(d_filename.c_str()); + ok = false; + break; + } + } + + return ok; + } +}; + +complex_float_file_writer::~complex_float_file_writer() +{ + fclose(d_fp); +} + +// ------------------------------------------------------------------------ + +static void +usage(const char *progname) +{ + const char *p = strrchr(progname, '/'); // drop leading directory path + if (p) + p++; + + if (strncmp(p, "lt-", 3) == 0) // drop lt- libtool prefix + p += 3; + + fprintf(stderr, "Usage: %s [options]\n\n", p); + fprintf(stderr, "Options:\n"); + fprintf(stderr, " -h show this message and exit\n"); + fprintf(stderr, " -e ETH_INTERFACE specify ethernet interface [default=eth0]\n"); + fprintf(stderr, " -m MAC_ADDR mac address of USRP2 HH:HH [default=first one found]\n"); + fprintf(stderr, " -f FREQUENCY specify receive center frequency in Hz [default=0.0]\n"); + fprintf(stderr, " -d DECIM specify receive decimation rate [default=5]\n"); + fprintf(stderr, " -g GAIN specify receive daughterboard gain [default=0]\n"); + fprintf(stderr, " -N NSAMPLES specify number of samples to receive [default=infinite]\n"); + fprintf(stderr, " -o OUTPUT_FILENAME specify file to receive samples [default=none]\n"); + fprintf(stderr, " -s write complex [default=complex]\n"); + fprintf(stderr, " -v verbose output\n"); +} + +int +main(int argc, char **argv) +{ + // options and their defaults + const char *interface = "eth0"; + const char *mac_addr_str = ""; + double rx_freq = 0.0; + int rx_decim = 5; + double rx_gain = 0.0; + uint64_t nsamples = 0; + bool output_shorts = false; + char *output_filename = 0; + bool verbose = false; + + int ch; + + while ((ch = getopt(argc, argv, "he:m:f:d:g:N:o:sv")) != EOF){ + double tmp; + switch (ch){ + + case 'e': + interface = optarg; + break; + + case 'm': + mac_addr_str = optarg; + break; + + case 'f': + if (!strtod_si(optarg, &rx_freq)) { + std::cerr << "invalid number: " << optarg << std::endl; + usage(argv[0]); + exit(1); + } + break; + + case 'g': + if (!strtod_si(optarg, &rx_gain)) { + std::cerr << "invalid number: " << optarg << std::endl; + usage(argv[0]); + exit(1); + } + break; + + case 'd': + rx_decim = strtol(optarg, 0, 0); + if (rx_decim < 4 or rx_decim > 512) { + std::cerr << "invalid decimation rate: " << optarg << std::endl; + usage(argv[0]); + exit(1); + } + break; + + case 'N': + if (!strtod_si(optarg, &tmp)) { + std::cerr << "invalid number: " << optarg << std::endl; + usage(argv[0]); + exit(1); + } + nsamples = static_cast(tmp); + break; + + case 's': + output_shorts = true; + break; + + case 'o': + output_filename = optarg; + break; + + case 'v': + verbose = true; + break; + + case 'h': + default: + usage(argv[0]); + exit(1); + } + } + + + install_sig_handler(SIGINT, sig_handler); + + usrp2::rx_nop_handler::sptr handler; + + if (output_filename){ + if (output_shorts) + handler = usrp2::rx_nop_handler::sptr(new complex_16_file_writer(output_filename, nsamples)); + else + handler = usrp2::rx_nop_handler::sptr(new complex_float_file_writer(output_filename, nsamples)); + } + else + handler = usrp2::rx_nop_handler::sptr(new usrp2::rx_nop_handler(nsamples)); + + gruel::rt_status_t rt = gruel::enable_realtime_scheduling(); + if (rt != gruel::RT_OK) + std::cerr << "Failed to enable realtime scheduling" << std::endl; + + usrp2::usrp2::sptr u2 = usrp2::usrp2::make(interface, mac_addr_str); + + // FIXME in case it was left running... + if (!u2->stop_rx_streaming()){ + fprintf(stderr, "stop_rx_streaming failed\n"); + } + + if (!u2->set_rx_gain(rx_gain)){ + fprintf(stderr, "set_rx_gain(%f) failed\n", rx_gain); + exit(1); + } + + usrp2::tune_result tr; + if (!u2->set_rx_center_freq(rx_freq, &tr)){ + fprintf(stderr, "set_rx_center_freq(%g) failed\n", rx_freq); + exit(1); + } + + if (verbose){ + printf("USRP2 MAC address: %s\n\n", u2->mac_addr().c_str()); + printf("Daughterboard configuration:\n"); + printf(" baseband_freq=%f\n", tr.baseband_freq); + printf(" ddc_freq=%f\n", tr.dxc_freq); + printf(" residual_freq=%f\n", tr.residual_freq); + printf(" inverted=%s\n\n", tr.spectrum_inverted ? "yes" : "no"); + } + + if (!u2->set_rx_decim(rx_decim)) { + fprintf(stderr, "set_rx_decim(%d) failed\n", rx_decim); + exit(1); + } + + if (verbose) + printf("USRP2 using decimation rate of %d\n", rx_decim); + + if (!u2->start_rx_streaming(0)){ + fprintf(stderr, "start_rx_streaming failed\n"); + exit(1); + } + + if (verbose) { + if (nsamples > 0) + printf("Receiving %zd samples\n\n", nsamples); + else + printf("Receiving infinite samples\n\n"); + } + + struct timeval start, end; + gettimeofday(&start, 0); + + while (!signaled && + !handler->has_errored_p() && + !handler->has_finished_p()) { + bool ok = u2->rx_samples(0, handler.get()); + if (!ok){ + fprintf(stderr, "u2->rx_samples failed\n"); + return 1; + } + } + + gettimeofday(&end, 0); + long n_usecs = end.tv_usec-start.tv_usec; + long n_secs = end.tv_sec-start.tv_sec; + double elapsed = (double)n_secs + (double)n_usecs*1e-6; + double mbs = handler->nsamples()*sizeof(uint32_t)/elapsed/1e6; + double pps = handler->nframes()/elapsed; + + u2->stop_rx_streaming(); + + if (verbose){ + printf("\nCopy handler called %li times.\n", handler->nframes()); + printf("Copy handler called with %li bytes.\n\n", handler->nsamples()*sizeof(uint32_t)); + printf("Elapsed time was %5.3f seconds.\n", elapsed); + printf("Packet rate was %1.0f pkts/sec.\n", pps); + printf("Approximate throughput was %5.2f MB/sec.\n", mbs); + printf("Total instances of overruns was %d.\n", u2->rx_overruns()); + printf("Total missing frames was %d.\n", u2->rx_missing()); + } + + return 0; +} diff --git a/usrp2/host/apps/stdin_int32_fft.py b/usrp2/host/apps/stdin_int32_fft.py new file mode 100755 index 00000000..5391863a --- /dev/null +++ b/usrp2/host/apps/stdin_int32_fft.py @@ -0,0 +1,201 @@ +#!/usr/bin/env python +# +# Copyright 2004,2005,2007,2008 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +from gnuradio import gr, gru +from gnuradio import eng_notation +from gnuradio.eng_option import eng_option +from gnuradio.wxgui import stdgui2, fftsink2, waterfallsink2, scopesink2, form, slider +from optparse import OptionParser +import wx +import sys +import numpy + + +class app_top_block(stdgui2.std_top_block): + def __init__(self, frame, panel, vbox, argv): + stdgui2.std_top_block.__init__(self, frame, panel, vbox, argv) + + self.frame = frame + self.panel = panel + + parser = OptionParser(option_class=eng_option) + parser.add_option("-d", "--decim", type="int", default=16, + help="set fgpa decimation rate to DECIM [default=%default]") + parser.add_option("-f", "--freq", type="eng_float", default=None, + help="set frequency to FREQ", metavar="FREQ") + parser.add_option("-W", "--waterfall", action="store_true", default=False, + help="Enable waterfall display") + parser.add_option("-S", "--oscilloscope", action="store_true", default=False, + help="Enable oscilloscope display") + (options, args) = parser.parse_args() + if len(args) != 0: + parser.print_help() + sys.exit(1) + self.options = options + self.options.gain = 1.0 + self.show_debug_info = True + + + input_rate = 100e6 / options.decim + + self.src = gr.file_descriptor_source(gr.sizeof_short, 0, False); + self.s2c = gr.interleaved_short_to_complex() + + if options.waterfall: + self.scope = \ + waterfallsink2.waterfall_sink_c (panel, fft_size=1024, sample_rate=input_rate) + elif options.oscilloscope: + self.scope = scopesink2.scope_sink_c(panel, sample_rate=input_rate) + else: + self.scope = fftsink2.fft_sink_c (panel, fft_size=1024, y_divs=12, sample_rate=input_rate,ref_level=110,fft_rate=20) + + self.connect(self.src, self.s2c, self.scope) + + self._build_gui(vbox) + self._setup_events() + + # set initial values + + if options.freq is None: + # if no freq was specified, use the mid-point + options.freq = 0.0 + + if self.show_debug_info: + self.myform['decim'].set_value(self.options.decim) + + + def _set_status_msg(self, msg): + self.frame.GetStatusBar().SetStatusText(msg, 0) + + def _build_gui(self, vbox): + + def _form_set_freq(kv): + return self.set_freq(kv['freq']) + + vbox.Add(self.scope.win, 10, wx.EXPAND) + + # add control area at the bottom + self.myform = myform = form.form() + hbox = wx.BoxSizer(wx.HORIZONTAL) + hbox.Add((5,0), 0, 0) + myform['freq'] = form.float_field( + parent=self.panel, sizer=hbox, label="Center freq", weight=1, + callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) + + hbox.Add((5,0), 0, 0) + vbox.Add(hbox, 0, wx.EXPAND) + + self._build_subpanel(vbox) + + def _build_subpanel(self, vbox_arg): + # build a secondary information panel (sometimes hidden) + + # FIXME figure out how to have this be a subpanel that is always + # created, but has its visibility controlled by foo.Show(True/False) + + def _form_set_decim(kv): + return self.set_decim(kv['decim']) + + if not(self.show_debug_info): + return + + panel = self.panel + vbox = vbox_arg + myform = self.myform + + #panel = wx.Panel(self.panel, -1) + #vbox = wx.BoxSizer(wx.VERTICAL) + + hbox = wx.BoxSizer(wx.HORIZONTAL) + hbox.Add((5,0), 0) + + myform['decim'] = form.int_field( + parent=panel, sizer=hbox, label="Decim", + callback=myform.check_input_and_call(_form_set_decim, self._set_status_msg)) + + hbox.Add((5,0), 0) + vbox.Add(hbox, 0, wx.EXPAND) + + + def set_freq(self, target_freq): + """ + Set the center frequency we're interested in. + + @param target_freq: frequency in Hz + @rypte: bool + + Tuning is a two step process. First we ask the front-end to + tune as close to the desired frequency as it can. Then we use + the result of that operation and our target_frequency to + determine the value for the digital down converter. + """ + + if True: + self.myform['freq'].set_value(target_freq) # update displayed value + if not self.options.waterfall and not self.options.oscilloscope: + self.scope.win.set_baseband_freq(target_freq) + return True + + return False + + def set_gain(self, gain): + self.myform['gain'].set_value(gain) # update displayed value + + def set_decim(self, decim): + input_rate = 100e6 / self.options.decim + self.scope.set_sample_rate(input_rate) + if self.show_debug_info: # update displayed values + self.myform['decim'].set_value(self.u.decim_rate()) + return ok + + def _setup_events(self): + if not self.options.waterfall and not self.options.oscilloscope: + self.scope.win.Bind(wx.EVT_LEFT_DCLICK, self.evt_left_dclick) + + def evt_left_dclick(self, event): + (ux, uy) = self.scope.win.GetXY(event) + if event.CmdDown(): + # Re-center on maximum power + points = self.scope.win._points + if self.scope.win.peak_hold: + if self.scope.win.peak_vals is not None: + ind = numpy.argmax(self.scope.win.peak_vals) + else: + ind = int(points.shape()[0]/2) + else: + ind = numpy.argmax(points[:,1]) + (freq, pwr) = points[ind] + target_freq = freq/self.scope.win._scale_factor + print ind, freq, pwr + self.set_freq(target_freq) + else: + # Re-center on clicked frequency + target_freq = ux/self.scope.win._scale_factor + self.set_freq(target_freq) + + +def main (): + app = stdgui2.stdapp(app_top_block, "USRP FFT", nstatus=1) + app.MainLoop() + +if __name__ == '__main__': + main () diff --git a/usrp2/host/apps/streaming_fft.py b/usrp2/host/apps/streaming_fft.py new file mode 100755 index 00000000..cd3606c9 --- /dev/null +++ b/usrp2/host/apps/streaming_fft.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python +# +# Copyright 2008 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +# + +import os +import os.path +import sys +from gnuradio.eng_option import eng_option +from optparse import OptionParser + +def main(): + parser = OptionParser(option_class=eng_option) + parser.add_option("-d", "--decim", type="int", default=16, + help="set fgpa decimation rate to DECIM [default=%default]") + parser.add_option("-f", "--freq", type="eng_float", default=0.0, + help="set frequency to FREQ", metavar="FREQ") + parser.add_option("-g", "--gain", type="string", default=None, + help="set gain to GAIN [default=%default]") + parser.add_option("-W", "--waterfall", action="store_true", default=False, + help="Enable waterfall display") + parser.add_option("-S", "--oscilloscope", action="store_true", default=False, + help="Enable oscilloscope display") + parser.add_option("-F", "--samples-per-frame", type="int", default=250, + help="[default=%default]") + parser.add_option("-e", "--eth", default="eth0", + help="specify ethernet interface [default=%default]") + + (options, args) = parser.parse_args() + if len(args) != 0: + parser.print_help() + sys.exit(1) + + + path = os.path.dirname(sys.argv[0]) + if path == '': + path = '.' + + + display_type = '' + if options.waterfall: + display_type = '-W' + if options.oscilloscope: + display_type = '-S' + + gain_clause = '' + if options.gain: + gain_clause = '-g ' + options.gain + + # FIXME: restore -F + cmd = "sudo %s/rx_streaming_samples -s -e %s -f %g -d %d %s -o /proc/self/fd/1 | %s/stdin_int32_fft.py %s -f %g -d %d" % ( + path, options.eth, options.freq, options.decim, gain_clause, + path, display_type, options.freq, options.decim) + + print cmd + os.system(cmd) + + +if __name__ == '__main__': + main() diff --git a/usrp2/host/apps/test.sh b/usrp2/host/apps/test.sh new file mode 100755 index 00000000..c533c333 --- /dev/null +++ b/usrp2/host/apps/test.sh @@ -0,0 +1,4 @@ +#!/bin/sh + +sudo ./rx_streaming_samples -d 4 -v -N 100M + diff --git a/usrp2/host/apps/tx_samples.cc b/usrp2/host/apps/tx_samples.cc new file mode 100644 index 00000000..b4a3c8ed --- /dev/null +++ b/usrp2/host/apps/tx_samples.cc @@ -0,0 +1,263 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +typedef std::complex fcomplex; + +static volatile bool signaled = false; + +static void +sig_handler(int sig) +{ + signaled = true; +} + +static void +install_sig_handler(int signum, + void (*new_handler)(int)) +{ + struct sigaction new_action; + memset (&new_action, 0, sizeof (new_action)); + + new_action.sa_handler = new_handler; + sigemptyset (&new_action.sa_mask); + new_action.sa_flags = 0; + + if (sigaction (signum, &new_action, 0) < 0){ + perror ("sigaction (install new)"); + throw std::runtime_error ("sigaction"); + } +} + + +static const char * +prettify_progname(const char *progname) // that's probably almost a word ;) +{ + const char *p = strrchr(progname, '/'); // drop leading directory path + if (p) + p++; + + if (strncmp(p, "lt-", 3) == 0) // drop lt- libtool prefix + p += 3; + + return p; +} + +static void +usage(const char *progname) +{ + fprintf(stderr, "Usage: %s [options]\n\n", prettify_progname(progname)); + fprintf(stderr, "Options:\n"); + fprintf(stderr, " -h show this message and exit\n"); + fprintf(stderr, " -e ETH_INTERFACE specify ethernet interface [default=eth0]\n"); + fprintf(stderr, " -m MAC_ADDR mac address of USRP2 HH:HH [default=first one found]\n"); + fprintf(stderr, " -I INPUT_FILE set input filename [default=stdin]\n"); + fprintf(stderr, " -r repeat. When EOF of input file is reached, seek to beginning\n"); + fprintf(stderr, " -f FREQ set frequency to FREQ [default=0]\n"); + fprintf(stderr, " -i INTERP set interpolation rate to INTERP [default=32]\n"); + fprintf(stderr, " -g gain set tx gain\n"); + fprintf(stderr, " -S SCALE fpga scaling factor for I & Q [default=256]\n"); +} + +#define GAIN_NOT_SET (-1000) +#define MAX_SAMPLES (371) + +int +main(int argc, char **argv) +{ + const char *interface = "eth0"; + const char *input_filename = 0; + bool repeat = false; + const char *mac_addr_str = ""; + double freq = 0; + int32_t interp = 32; + int32_t samples_per_frame = MAX_SAMPLES; + int32_t scale = 3000; + double gain = GAIN_NOT_SET; + + int ch; + double tmp; + + + while ((ch = getopt(argc, argv, "he:m:I:rf:i:S:F:g:")) != EOF){ + switch (ch){ + + case 'e': + interface = optarg; + break; + + case 'm': + mac_addr_str = optarg; +#if 0 + if (!usrp2_basic::parse_mac_addr(optarg, &mac_addr)){ + std::cerr << "invalid mac addr: " << optarg << std::endl; + usage(argv[0]); + return 1; + } +#endif + break; + + case 'I': + input_filename = optarg; + break; + + case 'r': + repeat = true; + break; + + case 'f': + if (!strtod_si(optarg, &freq)){ + std::cerr << "invalid number: " << optarg << std::endl; + usage(argv[0]); + return 1; + } + break; + + case 'F': + samples_per_frame = strtol(optarg, 0, 0); + break; + + case 'i': + interp = strtol(optarg, 0, 0); + break; + + case 'S': + if (!strtod_si(optarg, &tmp)){ + std::cerr << "invalid number: " << optarg << std::endl; + usage(argv[0]); + return 1; + } + scale = static_cast(tmp); + break; + + case 'h': + default: + usage(argv[0]); + return 1; + } + } + + + if (argc - optind != 0){ + usage(argv[0]); + return 1; + } + + if (samples_per_frame < 9 || samples_per_frame > MAX_SAMPLES){ + std::cerr << prettify_progname(argv[0]) + << ": samples_per_frame is out of range. " + << "Must be in [9, " << MAX_SAMPLES << "].\n"; + usage(argv[0]); + return 1; + } + + + FILE *fp = 0; + if (input_filename == 0) + fp = stdin; + else { + fp = fopen(input_filename, "rb"); + if (fp == 0){ + perror(input_filename); + return 1; + } + } + + install_sig_handler(SIGINT, sig_handler); + + + gruel::rt_status_t rt = gruel::enable_realtime_scheduling(); + if (rt != gruel::RT_OK) + std::cerr << "Failed to enable realtime scheduling" << std::endl; + + + usrp2::usrp2::sptr u2 = usrp2::usrp2::make(interface, mac_addr_str); + + if (gain != GAIN_NOT_SET){ + if (!u2->set_tx_gain(gain)){ + std::cerr << "set_tx_gain failed\n"; + return 1; + } + } + + usrp2::tune_result tr; + if (!u2->set_tx_center_freq(freq, &tr)){ + fprintf(stderr, "set_tx_center_freq(%g) failed\n", freq); + return 1; + } + + printf("Daughterboard configuration:\n"); + printf(" baseband_freq=%f\n", tr.baseband_freq); + printf(" duc_freq=%f\n", tr.dxc_freq); + printf(" residual_freq=%f\n", tr.residual_freq); + printf(" inverted=%s\n\n", tr.spectrum_inverted ? "yes" : "no"); + + if (!u2->set_tx_interp(interp)){ + fprintf(stderr, "set_tx_interp(%d) failed\n", interp); + return 1; + } + + if (!u2->set_tx_scale_iq(scale, scale)){ + std::cerr << "set_tx_scale_iq failed\n"; + return 1; + } + + + usrp2::tx_metadata md; + md.timestamp = -1; + md.start_of_burst = 1; + md.send_now = 1; + + while (!signaled){ + + std::complex samples[MAX_SAMPLES]; + + int r = fread(samples, sizeof(uint32_t), samples_per_frame, fp); + + // fprintf(stderr, "fread -> %d\n", r); + + if (r == 0){ + if (!repeat) + break; + if (fseek(fp, 0, SEEK_SET) == -1) + break; + } + + // FIXME if r < 9, pad to 9 for minimum packet size constraint + + if (!u2->tx_complex_int16(0, samples, r, &md)){ + fprintf(stderr, "tx_complex_int16 failed\n"); + break; + } + } + + return 0; +} diff --git a/usrp2/host/apps/usrp2_burn_mac_addr.cc b/usrp2/host/apps/usrp2_burn_mac_addr.cc new file mode 100644 index 00000000..6ee76c13 --- /dev/null +++ b/usrp2/host/apps/usrp2_burn_mac_addr.cc @@ -0,0 +1,176 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include + + +static volatile bool signaled = false; + +static void +sig_handler(int sig) +{ + signaled = true; +} + +static void +install_sig_handler(int signum, + void (*new_handler)(int)) +{ + struct sigaction new_action; + memset (&new_action, 0, sizeof (new_action)); + + new_action.sa_handler = new_handler; + sigemptyset (&new_action.sa_mask); + new_action.sa_flags = 0; + + if (sigaction (signum, &new_action, 0) < 0){ + perror ("sigaction (install new)"); + throw std::runtime_error ("sigaction"); + } +} + + +static void +usage(const char *progname) +{ + fprintf(stderr, "usage: %s [-e ethN] [-m old_mac_addr] new_mac_addr\n", + progname); + fprintf(stderr, " old_mac_addr defaults to 00:50:c2:85:3f:ff\n"); + fprintf(stderr, " new_mac_address must be HH:HH or HH:HH:HH:HH:HH:HH\n"); +} + +static bool +check_mac_addr_syntax(const std::string &s) +{ + unsigned char addr[6]; + + addr[0] = 0x00; // Matt's IAB + addr[1] = 0x50; + addr[2] = 0xC2; + addr[3] = 0x85; + addr[4] = 0x30; + addr[5] = 0x00; + + int len = s.size(); + + switch (len){ + + case 5: + return sscanf(s.c_str(), "%hhx:%hhx", &addr[4], &addr[5]) == 2; + + case 17: + return sscanf(s.c_str(), "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &addr[0], &addr[1], &addr[2], + &addr[3], &addr[4], &addr[5]) == 6; + default: + return false; + } + + return true; +} + + +int +main(int argc, char **argv) +{ + int ch; + const char *interface = "eth0"; + const char *old_mac_addr = "00:50:c2:85:3f:ff"; + const char *new_mac_addr = 0; + + while ((ch = getopt(argc, argv, "he:m:")) != EOF){ + switch (ch){ + case 'e': + interface = optarg; + break; + + case 'm': + old_mac_addr = optarg; + break; + + case 'h': + default: + usage(argv[0]); + exit(1); + } + } + + if (argc - optind != 1){ + usage(argv[0]); + exit(1); + } + + new_mac_addr = argv[optind]; + + if (!check_mac_addr_syntax(old_mac_addr)){ + fprintf(stderr, "invalid mac address: %s\n", old_mac_addr); + exit(1); + } + if (!check_mac_addr_syntax(new_mac_addr)){ + fprintf(stderr, "invalid mac address: %s\n", new_mac_addr); + exit(1); + } + + install_sig_handler(SIGINT, sig_handler); + + usrp2::usrp2::sptr u2; + + try { + u2 = usrp2::usrp2::make(interface, old_mac_addr); + } + catch (std::exception const &e){ + std::cerr << e.what() << std::endl; + return 1; + } + + if (!u2->burn_mac_addr(new_mac_addr)){ + std::cerr << "Failed to burn mac address: " + << new_mac_addr << std::endl; + return 1; + } + + u2.reset(); // close + + // wait 250 ms + struct timespec ts; + ts.tv_sec = 0; + ts.tv_nsec = 250000000; + nanosleep(&ts, 0); + + try { + u2 = usrp2::usrp2::make(interface, new_mac_addr); + } + catch (std::exception const &e){ + std::cerr << "Failed to connect to USRP2 using new addr: " + << new_mac_addr << std::endl; + std::cerr << e.what() << std::endl; + return 1; + } + + return 0; +} diff --git a/usrp2/host/include/Makefile.am b/usrp2/host/include/Makefile.am new file mode 100644 index 00000000..e2f7282b --- /dev/null +++ b/usrp2/host/include/Makefile.am @@ -0,0 +1,23 @@ +# +# Copyright 2008 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +# + +include $(top_srcdir)/Makefile.common + +SUBDIRS = usrp2 diff --git a/usrp2/host/include/usrp2/Makefile.am b/usrp2/host/include/usrp2/Makefile.am new file mode 100644 index 00000000..4c6dac89 --- /dev/null +++ b/usrp2/host/include/usrp2/Makefile.am @@ -0,0 +1,34 @@ +# +# Copyright 2008 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include $(top_srcdir)/Makefile.common + +INCLUDES = $(STD_DEFINES_AND_INCLUDES) $(CPPUNIT_INCLUDES) + +usrp2includedir = $(includedir)/usrp2 + +usrp2include_HEADERS = \ + copiers.h \ + copy_handler.h \ + data_handler.h \ + metadata.h \ + rx_nop_handler.h \ + rx_sample_handler.h \ + strtod_si.h \ + tune_result.h \ + usrp2.h \ + usrp2_cdefs.h diff --git a/usrp2/host/include/usrp2/copiers.h b/usrp2/host/include/usrp2/copiers.h new file mode 100644 index 00000000..43674f7a --- /dev/null +++ b/usrp2/host/include/usrp2/copiers.h @@ -0,0 +1,63 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_USRP2_COPIERS_H +#define INCLUDED_USRP2_COPIERS_H + +#include +#include + +namespace usrp2 { + + // FIXME we may want to rework this, but this will get us on the air + + /* + * ---------------------------------------------------------------- + * Copy and convert from USRP2 wire format to host format + * ---------------------------------------------------------------- + */ + + void + copy_u2_complex_16_to_host_complex_16(size_t nitems, + const uint32_t *items, + std::complex *host_items); + + void + copy_u2_complex_16_to_host_complex_float(size_t nitems, + const uint32_t *items, + std::complex *host_items); + + /* + * ---------------------------------------------------------------- + * Copy and convert from host format to USRP2 wire format + * ---------------------------------------------------------------- + */ + + void + copy_host_complex_16_to_u2_complex_16(size_t nitems, + const std::complex *host_items, + uint32_t *items); + + void + copy_host_complex_float_to_u2_complex_16(size_t nitems, + const std::complex *host_items, + uint32_t *items); +} + + +#endif /* INCLUDED_USRP2_COPIERS_H */ diff --git a/usrp2/host/include/usrp2/copy_handler.h b/usrp2/host/include/usrp2/copy_handler.h new file mode 100644 index 00000000..aef14cac --- /dev/null +++ b/usrp2/host/include/usrp2/copy_handler.h @@ -0,0 +1,51 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef INCLUDED_COPY_HANDLER_H +#define INCLUDED_COPY_HANDLER_H + +#include +#include + +namespace usrp2 { + + class copy_handler : public data_handler, boost::noncopyable + { + uint8_t *d_dest; // next write pointer + size_t d_space; // space left in destination buffer + size_t d_bytes; // total bytes copied + size_t d_times; // number of times invoked + + public: + copy_handler(void *dest, size_t len); + ~copy_handler(); + + virtual data_handler::result operator()(const void *base, size_t len); + + size_t bytes() const { return d_bytes; } + size_t times() const { return d_times; } + + static const size_t MIN_COPY_LEN = 1484; // FIXME: calculate eth packet - thdr + bool full() const { return d_space < MIN_COPY_LEN; } + }; + +} // namespace usrp2 + +#endif /* INCLUDED_COPY_HANDLER_H */ diff --git a/usrp2/host/include/usrp2/data_handler.h b/usrp2/host/include/usrp2/data_handler.h new file mode 100644 index 00000000..7317b38a --- /dev/null +++ b/usrp2/host/include/usrp2/data_handler.h @@ -0,0 +1,55 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef INCLUDED_DATA_HANDLER_H +#define INCLUDED_DATA_HANDLER_H + +#include +#include + +namespace usrp2 { + + /*! + * \brief Abstract function object called to handle received data blocks. + */ + class data_handler + { + public: + + enum result_bits { + RELEASE = 0x0000, //< OK to release data (opposite of KEEP) + KEEP = 0x0001, //< do not discard data + DONE = 0x0002, //< do not call this object again + }; + + typedef int result; //< bitmask of result_bits + + /*! + * \param base points to the beginning of the data + * \param len is the length in bytes of the data + * \returns bitmask composed of DONE, KEEP + */ + virtual result operator()(const void *base, size_t len) = 0; + virtual ~data_handler(); + }; + +} // namespace usrp2 + +#endif /* INCLUDED_DATA_HANDLER_H */ diff --git a/usrp2/host/include/usrp2/metadata.h b/usrp2/host/include/usrp2/metadata.h new file mode 100644 index 00000000..52efd07e --- /dev/null +++ b/usrp2/host/include/usrp2/metadata.h @@ -0,0 +1,60 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_USRP2_METADATA_H +#define INCLUDED_USRP2_METADATA_H + +#include + +namespace usrp2 { + + //! type of the timestamp returned from the USRP2 FPGA + typedef uint32_t fpga_timestamp; + + /*! + * \brief metadata associated with received frames + */ + struct rx_metadata { + uint32_t word0; //< debugging, extensions + fpga_timestamp timestamp; //< time that first sample of frame was received + unsigned int start_of_burst : 1; //< this frame is the start of a burst + unsigned int end_of_burst : 1; //< this frame is the end of a burst + unsigned int rx_overrun : 1; //< An Rx overrun occurred in the FPGA + // rssi + // agc_mode + + rx_metadata() : + word0(0), timestamp(0), start_of_burst(0), end_of_burst(0), rx_overrun(0) {} + }; + + /*! + * \brief metadata associated with transmitted frames + */ + struct tx_metadata { + fpga_timestamp timestamp; //< time to transmit first sample of frame + unsigned int send_now : 1; //< ignore timestamp, send now + unsigned int start_of_burst : 1; //< this frame is the start of a burst + unsigned int end_of_burst : 1; //< this frame is the end of a burst + // ... + + tx_metadata() : + timestamp(0), send_now(0), start_of_burst(0), end_of_burst(0) {} + }; + +}; // usrp2 + +#endif /* INCLUDED_USRP2_METADATA_H */ diff --git a/usrp2/host/include/usrp2/rx_nop_handler.h b/usrp2/host/include/usrp2/rx_nop_handler.h new file mode 100644 index 00000000..44ca5139 --- /dev/null +++ b/usrp2/host/include/usrp2/rx_nop_handler.h @@ -0,0 +1,128 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_RX_NOP_HANDLER_H +#define INCLUDED_RX_NOP_HANDLER_H + +#include +#include + +/*! + * Base class for receive handlers that must copy into potentially limited + * range destination buffers. + * + * Maintains counters for number of items copied, times invoked, and test + * for whether maximum has been reached. + * + * Derived classes should override the () operator, but call this + * parent class method at some point at the start of their own operations. + */ + +namespace usrp2 { + + class rx_nop_handler : public rx_sample_handler + { + uint64_t d_max_samples; + uint64_t d_max_quantum; + uint64_t d_nsamples; + uint64_t d_nframes; + + protected: + bool d_err; + + public: + + // Shared pointer to an instance of this class + typedef boost::shared_ptr sptr; + + /*! + * Constructor + * + * \param max_samples Maximum number of samples to copy. Use zero for no maximum. + * \param max_quantum Maximum number of samples required to accept in one call. + * Use 0 to indicate no maximum. + */ + rx_nop_handler(uint64_t max_samples, uint64_t max_quantum=0) + : d_max_samples(max_samples), d_max_quantum(max_quantum), + d_nsamples(0), d_nframes(0), d_err(false) {} + + /*! + * Destructor. Derived classes must implement their own, non-inline destructor. + */ + virtual ~rx_nop_handler(); + + /*! + * \brief Returns number of frames this copier was called with + */ + uint64_t nframes() const { return d_nframes; } + + /*! + * \brief Returns actual number of samples copied + */ + uint64_t nsamples() const { return d_nsamples; } + + /*! + * \brief Returns maximum number of samples that will be copied + */ + uint64_t max_samples() const { return d_max_samples; } + + /*! + * Returns true if an error has occurred. Derived classes must set d_err to true + * when an error occurs in the () operator + */ + bool has_errored_p() const { return d_err; } + + /*! + * \brief Returns true if this instance has reached the maximum number of samples + */ + bool has_finished_p() const + { return d_max_samples == 0 ? false : d_nsamples >= d_max_samples-d_max_quantum; } + + + /*! + * Function operator invoked by USRP2 RX API. Derived classes must override this method + * but then invoke it at the start of their processing. This operator will always be + * called at least once. + * + * \param items points to the first 32-bit word of uninterpreted sample data in the frame. + * \param nitems is the number of entries in the frame in units of uint32_t's. + * \param metadata is the additional per frame data provided by the USRP2 FPGA. + * + * \p items points to the raw sample data received off of the ethernet. The data is + * packed into big-endian 32-bit unsigned ints for transport, but the actual format + * of the data is dependent on the current configuration of the USRP2. The most common + * format is 16-bit I & Q, with I in the top of the 32-bit word. + * + * \returns true if the object wants to be called again with new data; + * false if no additional data is wanted. + */ + virtual bool operator()(const uint32_t *items, size_t nitems, const rx_metadata *metadata) + { + // printf("W0: %08x TS: %08x\n", metadata->word0, metadata->timestamp); + // printf("I0: %08x\n", items[0]); + + d_nsamples += nitems; + d_nframes++; + + return !has_finished_p(); + } + }; + +} /* namespace usrp2 */ + +#endif /* INCLUDED_RX_NOP_HANDLER */ diff --git a/usrp2/host/include/usrp2/rx_sample_handler.h b/usrp2/host/include/usrp2/rx_sample_handler.h new file mode 100644 index 00000000..480cbc4f --- /dev/null +++ b/usrp2/host/include/usrp2/rx_sample_handler.h @@ -0,0 +1,58 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_USRP2_RX_SAMPLE_HANDLER_H +#define INCLUDED_USRP2_RX_SAMPLE_HANDLER_H + +#include +#include + + +namespace usrp2 { + + /*! + * \brief Abstract function object called to handle received data blocks. + * + * An object derived from this class is passed to usrp2::rx_samples + * to process the received frames of samples. + */ + class rx_sample_handler { + public: + virtual ~rx_sample_handler(); + + /*! + * \param items points to the first 32-bit word of uninterpreted sample data in the frame. + * \param nitems is the number of entries in the frame in units of uint32_t's. + * \param metadata is the additional per frame data provided by the USRP2 FPGA. + * + * \p items points to the raw sample data received off of the ethernet. The data is + * packed into big-endian 32-bit unsigned ints for transport, but the actual format + * of the data is dependent on the current configuration of the USRP2. The most common + * format is 16-bit I & Q, with I in the top of the 32-bit word. + * + * This is the general purpose, low level interface and relies on other functions + * to handle all required endian-swapping and format conversion. \sa FIXME. + * + * \returns true if the object wants to be called again with new data; + * false if no additional data is wanted. + */ + virtual bool operator()(const uint32_t *items, size_t nitems, const rx_metadata *metadata) = 0; + }; + +}; + +#endif /* INCLUDED_RX_SAMPLE_HANDLER_H */ diff --git a/usrp2/host/include/usrp2/strtod_si.h b/usrp2/host/include/usrp2/strtod_si.h new file mode 100644 index 00000000..0a0f5a62 --- /dev/null +++ b/usrp2/host/include/usrp2/strtod_si.h @@ -0,0 +1,39 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_STRTOD_SI_H +#define INCLUDED_STRTOD_SI_H + +#include "usrp2_cdefs.h" +__U2_BEGIN_DECLS + + +/*! + * \brief convert string at s to double honoring any trailing SI suffixes + * + * \param[in] s is the string to convert + * \param[out] result is the converted value + * \returns non-zero iff conversion was successful. + */ +int strtod_si(const char *s, double *result); + +__U2_END_DECLS + + +#endif /* INCLUDED_STRTOD_SI_H */ + diff --git a/usrp2/host/include/usrp2/tune_result.h b/usrp2/host/include/usrp2/tune_result.h new file mode 100644 index 00000000..6fb2a682 --- /dev/null +++ b/usrp2/host/include/usrp2/tune_result.h @@ -0,0 +1,45 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_TUNE_RESULT_H +#define INCLUDED_TUNE_RESULT_H + +namespace usrp2 { + + class tune_result + { + public: + // RF frequency that corresponds to DC in the IF + double baseband_freq; + + // frequency programmed into the DDC/DUC + double dxc_freq; + + // residual frequency (typically < 0.01 Hz) + double residual_freq; + + // is the spectrum inverted? + bool spectrum_inverted; + + tune_result() + : baseband_freq(0), dxc_freq(0), residual_freq(0), spectrum_inverted(false) {} + }; + +} // namespace usrp2 + +#endif /* INCLUDED_TUNE_RESULT_H */ diff --git a/usrp2/host/include/usrp2/usrp2.h b/usrp2/host/include/usrp2/usrp2.h new file mode 100644 index 00000000..87433791 --- /dev/null +++ b/usrp2/host/include/usrp2/usrp2.h @@ -0,0 +1,287 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_USRP2_H +#define INCLUDED_USRP2_H + +#include +#include +#include +#include +//#include +#include +#include +#include + + +namespace usrp2 { + + /*! + * Structure to hold properties of USRP2 hardware devices. + * + */ + struct props + { + std::string addr; + uint16_t hw_rev; + uint8_t fpga_md5sum[16]; + uint8_t sw_md5sum[16]; + }; + + typedef std::vector props_vector_t; + + /*! + * \brief Search the ethernet for all USRP2s or for a specific USRP2. + * + * \param ifc is the name of the OS ethernet interface (e.g., "eth0") + * \param mac_addr is the MAC address of the desired USRP2, or "" to search for all. + * mac_addr must be either a zero length string, "", or must be of the form + * "01:02:03:04:05:06" or "05:06". + * + * \returns a vector of properties, 1 entry for each matching USRP2 found. + */ + props_vector_t find(const std::string &ifc, const std::string &mac_addr=""); + + class tune_result; + + class usrp2 : boost::noncopyable + { + public: + static const unsigned int MAX_CHAN = 30; + + /*! + * Shared pointer to this class + */ + typedef boost::shared_ptr sptr; + + /*! + * Static function to return an instance of usrp2 as a shared pointer + * + * \param ifc Network interface name, e.g., "eth0" + * \param addr Network mac address, e.g., "01:23:45:67:89:ab", "89:ab" or "". + * If \p addr is HH:HH, it's treated as if it were 00:50:c2:85:HH:HH + * "" will autoselect a USRP2 if there is only a single one on the local ethernet. + */ + static sptr make(const std::string &ifc, const std::string &addr=""); + + /*! + * Class destructor + */ + ~usrp2(); + + /*! + * Returns the MAC address associated with this USRP + */ + std::string mac_addr(); + + /*! + * Burn new mac address into EEPROM on USRP2 + * + * \param new_addr Network mac address, e.g., "01:23:45:67:89:ab" or "89:ab". + * If \p addr is HH:HH, it's treated as if it were 00:50:c2:85:HH:HH + */ + bool burn_mac_addr(const std::string &new_addr); + + /* + * ---------------------------------------------------------------- + * Rx configuration and control + * ---------------------------------------------------------------- + */ + + /*! + * Set receiver gain + */ + bool set_rx_gain(double gain); + + /*! + * Set receiver center frequency + */ + bool set_rx_center_freq(double frequency, tune_result *result); + + /*! + * Set receiver sample rate decimation + */ + bool set_rx_decim(int decimation_factor); + + /*! + * Set receiver IQ magnitude scaling + */ + bool set_rx_scale_iq(int scale_i, int scale_q); + + /*! + * Set received sample format + * + * domain: complex or real + * type: floating, fixed point, or raw + * depth: bits per sample + * + * Sets format over the wire for samples from USRP2. + */ + // bool set_rx_format(...); + + /*! + * Start streaming receive mode. USRP2 will send a continuous stream of + * DSP pipeline samples to host. Call rx_samples(...) to access. + * + * \param channel Stream channel number (0-30) + * \param items_per_frame Number of 32-bit items per frame. + */ + bool start_rx_streaming(unsigned int channel=0, unsigned int items_per_frame=0); + + /*! + * Stop streaming receive mode. + */ + bool stop_rx_streaming(unsigned int channel=0); + + /*! + * \brief Receive data from the specified channel + * This method is used to receive all data: streaming or discrete. + */ + bool rx_samples(unsigned int channel, rx_sample_handler *handler); + + /*! + * Returns number of times receive overruns have occurred + */ + unsigned int rx_overruns(); + + /*! + * Returns total number of missing frames from overruns. + */ + unsigned int rx_missing(); + + /* + * ---------------------------------------------------------------- + * Tx configuration and control + * ---------------------------------------------------------------- + */ + + /*! + * Set receiver gain + */ + bool set_tx_gain(double gain); + + /*! + * Set transmitter center frequency + */ + bool set_tx_center_freq(double frequency, tune_result *result); + + /*! + * Set transmitter sample rate interpolation + */ + bool set_tx_interp(int interpolation_factor); + + /*! + * Set transmit IQ magnitude scaling + */ + bool set_tx_scale_iq(int scale_i, int scale_q); + + /*! + * Set transmit sample format + * + * domain: complex or real + * type: floating, fixed point, or raw + * depth: bits per sample + * + * Sets format over the wire for samples to USRP2. + */ + // bool set_tx_format(...); + + /*! + * \brief transmit complex samples to USRP2 + * + * \param channel specifies the channel to send them to + * \param samples are the samples to transmit + * \param nsamples is the number of samples to transmit + * \param metadata provides the timestamp and flags + */ + bool tx_complex_float(unsigned int channel, + const std::complex *samples, + size_t nsamples, + const tx_metadata *metadata); + + /*! + * \brief transmit complex samples to USRP2 + * + * \param channel specifies the channel to send them to + * \param samples are the samples to transmit + * \param nsamples is the number of samples to transmit + * \param metadata provides the timestamp and flags + */ + bool tx_complex_int16(unsigned int channel, + const std::complex *samples, + size_t nsamples, + const tx_metadata *metadata); + + /*! + * \brief transmit raw uint32_t data items to USRP2 + * + * The caller is responsible for ensuring that the items are + * formatted appropriately for the USRP2 and its configuration. + * This method is used primarily by the system itself. Users + * should call tx_complex_float or tx_complex_16 instead. + * + * \param channel specifies the channel to send them to + * \param items are the data items to transmit + * \param nitems is the number of items to transmit + * \param metadata provides the timestamp and flags + */ + bool tx_raw(unsigned int channel, + const uint32_t *items, + size_t nitems, + const tx_metadata *metadata); + + // ---------------------------------------------------------------- + + /*! + * \brief MIMO configuration + * + * \param flags from usrp2_mimo_config.h + * + * 

    +     *   one of these:
+     *
+     *     MC_WE_DONT_LOCK
+     *     MC_WE_LOCK_TO_SMA
+     *     MC_WE_LOCK_TO_MIMO
+     *
+     *   and optionally this:
+     *
+     *     MC_PROVIDE_CLK_TO_MIMO
+     *
    + */ + bool config_mimo(int flags); + + class impl; // implementation details + + private: + // Static function to retrieve or create usrp2 instance + static sptr find_existing_or_make_new(const std::string &ifc, props *p); + + // Only class members can instantiate this class + usrp2(const std::string &ifc, props *p); + + // All private state is held in opaque pointer + std::auto_ptr d_impl; + }; + +}; + +std::ostream& operator<<(std::ostream &os, const usrp2::props &x); + + +#endif /* INCLUDED_USRP2_H */ diff --git a/usrp2/host/include/usrp2/usrp2_cdefs.h b/usrp2/host/include/usrp2/usrp2_cdefs.h new file mode 100644 index 00000000..71395cda --- /dev/null +++ b/usrp2/host/include/usrp2/usrp2_cdefs.h @@ -0,0 +1,34 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef INCLUDED_USRP2_CDEFS_H +#define INCLUDED_USRP2_CDEFS_H + +/* C++ needs to know that types and declarations are C, not C++. */ +#ifdef __cplusplus +# define __U2_BEGIN_DECLS extern "C" { +# define __U2_END_DECLS } +#else +# define __U2_BEGIN_DECLS +# define __U2_END_DECLS +#endif + +#endif /* INCLUDED_USRP2_CDEFS_H */ diff --git a/usrp2/host/lib/Makefile.am b/usrp2/host/lib/Makefile.am new file mode 100644 index 00000000..5c98600b --- /dev/null +++ b/usrp2/host/lib/Makefile.am @@ -0,0 +1,67 @@ +# +# Copyright 2007,2008 Free Software Foundation, Inc. +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +include $(top_srcdir)/Makefile.common + +AM_CPPFLAGS = \ + $(USRP2_INCLUDES) \ + $(BOOST_CPPFLAGS) \ + $(STD_DEFINES_AND_INCLUDES) \ + $(CPPUNIT_INCLUDES) \ + $(GRUEL_INCLUDES) + +bin_PROGRAMS = usrp2_socket_opener +usrp2_socket_opener_SOURCES = usrp2_socket_opener.cc + +lib_LTLIBRARIES = \ + libusrp2.la + +libusrp2_la_SOURCES = \ + control.cc \ + copiers.cc \ + copy_handler.cc \ + data_handler.cc \ + eth_buffer.cc \ + ethernet.cc \ + find.cc \ + open_usrp2_socket.cc \ + pktfilter.cc \ + ring.cc \ + rx_nop_handler.cc \ + rx_sample_handler.cc \ + strtod_si.c \ + usrp2.cc \ + usrp2_impl.cc \ + usrp2_thread.cc + +libusrp2_la_LIBADD = \ + $(OMNITHREAD_LA) \ + $(GRUEL_LIBS) \ + $(BOOST_LDFLAGS) $(BOOST_THREAD_LIB) + +# Private headers not needed for above the API development +noinst_HEADERS = \ + control.h \ + eth_buffer.h \ + eth_common.h \ + ethernet.h \ + open_usrp2_socket.h \ + pktfilter.h \ + ring.h \ + usrp2_bytesex.h \ + usrp2_impl.h \ + usrp2_thread.h diff --git a/usrp2/host/lib/control.cc b/usrp2/host/lib/control.cc new file mode 100644 index 00000000..97d969fa --- /dev/null +++ b/usrp2/host/lib/control.cc @@ -0,0 +1,57 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include "control.h" +#include + +namespace usrp2 { + + pending_reply::pending_reply(unsigned int rid, void *buffer, size_t len) + : d_rid(rid), d_mutex(), d_cond(&d_mutex), d_buffer(buffer), d_len(len) + { + } + + pending_reply::~pending_reply() + { + signal(); // Needed? + } + + int + pending_reply::wait(double secs) + { + omni_mutex_lock l(d_mutex); + omni_time abs_timeout = omni_time::time(omni_time(secs)); + return d_cond.timedwait(abs_timeout.d_secs, abs_timeout.d_nsecs); + } + + void + pending_reply::signal() + { + d_cond.signal(); + } + +} // namespace usrp2 + diff --git a/usrp2/host/lib/control.h b/usrp2/host/lib/control.h new file mode 100644 index 00000000..678f12e4 --- /dev/null +++ b/usrp2/host/lib/control.h @@ -0,0 +1,117 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_CONTROL_H +#define INCLUDED_CONTROL_H + +#include +#include + +namespace usrp2 { + /*! + * OP_CONFIG_RX_V2 command packet + */ + struct op_config_rx_v2_cmd + { + u2_eth_packet_t h; + op_config_rx_v2_t op; + op_generic_t eop; + }; + + struct op_start_rx_streaming_cmd + { + u2_eth_packet_t h; + op_start_rx_streaming_t op; + op_generic_t eop; + }; + + struct op_stop_rx_cmd { + u2_eth_packet_t h; + op_generic_t op; + op_generic_t eop; + }; + + struct op_config_tx_v2_cmd + { + u2_eth_packet_t h; + op_config_tx_v2_t op; + op_generic_t eop; + }; + + struct op_burn_mac_addr_cmd + { + u2_eth_packet_t h; + op_burn_mac_addr_t op; + op_generic_t eop; + }; + + /*! + * Control mechanism to allow API calls to block waiting for reply packets + */ + class pending_reply + { + private: + unsigned int d_rid; + omni_mutex d_mutex; + omni_condition d_cond; + void *d_buffer; + size_t d_len; + + public: + /*! + * Construct a pending reply from the reply ID, response packet + * buffer, and buffer length. + */ + pending_reply(unsigned int rid, void *buffer, size_t len); + + /*! + * Destructor. Signals creating thread. + */ + ~pending_reply(); + + /*! + * Block, waiting for reply packet. + * Returns: 1 = ok, reply packet in buffer + * 0 = timeout + */ + int wait(double secs); + + /*! + * Allows creating thread to resume after copying reply into buffer + */ + void signal(); + + /*! + * Retrieve pending reply ID + */ + unsigned int rid() const { return d_rid; } + + /*! + * Retrieve destination buffer address + */ + void *buffer() const { return d_buffer; } + + /*! + * Retrieve destination buffer length + */ + size_t len() const { return d_len; } + }; + +} // namespace usrp2 + +#endif /* INCLUDED_CONTROL_H */ diff --git a/usrp2/host/lib/copiers.cc b/usrp2/host/lib/copiers.cc new file mode 100644 index 00000000..833bb790 --- /dev/null +++ b/usrp2/host/lib/copiers.cc @@ -0,0 +1,133 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif +#include +#include +#include +#include +#include +#include +#include + +// FIXME need gruel::not_implemented + +namespace usrp2 { + + /* + * N.B., in all of these, uint32_t *items is NOT 32-bit aligned! + * FIXME Needs fix for non-x86 machines. + */ + + /* + * ---------------------------------------------------------------- + * Copy and convert from USRP2 wire format to host format + * ---------------------------------------------------------------- + */ + void + copy_u2_complex_16_to_host_complex_16(size_t nitems, + const uint32_t *items, + std::complex *host_items) + { +#ifdef WORDS_BIGENDIAN + + assert(sizeof(items[0]) == sizeof(host_items[0])); + memcpy(host_items, items, nitems * sizeof(items[0])); + +#else + + // FIXME SIMD welcome here + + for (size_t i = 0; i < nitems; i++){ + uint32_t t = ntohx(items[i]); + //printf("%9d\n", items[i]); + host_items[i] = std::complex((t >> 16), t & 0xffff); + } + +#endif + } + + + /* + * endian swap if required and map [-32768, 32767] -> [1.0, +1.0) + */ + void + copy_u2_complex_16_to_host_complex_float(size_t nitems, + const uint32_t *items, + std::complex *host_items) + { + for (size_t i = 0; i < nitems; i++){ + uint32_t t = ntohx(items[i]); + int16_t re = (t >> 16) & 0xffff; + int16_t im = (t & 0xffff); + host_items[i] = std::complex(re * 1.0/32768, im * 1.0/32768); + } + } + + /* + * ---------------------------------------------------------------- + * Copy and convert from host format to USRP2 wire format + * ---------------------------------------------------------------- + */ + void + copy_host_complex_16_to_u2_complex_16(size_t nitems, + const std::complex *host_items, + uint32_t *items) + { +#ifdef WORDS_BIGENDIAN + + assert(sizeof(items[0]) == sizeof(host_items[0])); + memcpy(items, host_items, nitems * sizeof(items[0])); + +#else + + // FIXME SIMD welcome here + + for (size_t i = 0; i < nitems; i++){ + items[i] = htonl((host_items[i].real() << 16) | (host_items[i].imag() & 0xffff)); + } + +#endif + } + + + static inline int16_t + clip_and_scale(float x) + { + return static_cast(rintf(gr_branchless_clip(x, 1.0) * 32767.0)); + } + + void + copy_host_complex_float_to_u2_complex_16(size_t nitems, + const std::complex *host_items, + uint32_t *items) + { + for (size_t i = 0; i < nitems; i++){ + int16_t re = clip_and_scale(host_items[i].real()); + int16_t im = clip_and_scale(host_items[i].imag()); + + items[i] = htonl((re << 16) | (im & 0xffff)); + } + } + +} diff --git a/usrp2/host/lib/copy_handler.cc b/usrp2/host/lib/copy_handler.cc new file mode 100644 index 00000000..92759084 --- /dev/null +++ b/usrp2/host/lib/copy_handler.cc @@ -0,0 +1,60 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include + +namespace usrp2 { + + copy_handler::copy_handler(void *dest, size_t len) + : d_dest((uint8_t *)dest), d_space(len), d_bytes(0), d_times(0) + { + } + + copy_handler::~copy_handler() + { + // NOP + } + + data_handler::result + copy_handler::operator()(const void *base, size_t len) + { + if (len > d_space) + return KEEP|DONE; // can't do anything, retry later + + memcpy(&d_dest[d_bytes], base, len); + d_space -= len; + d_bytes += len; + d_times++; + + if (d_space < MIN_COPY_LEN) + return DONE; // don't call me anymore + + return 0; + } + +} // namespace usrp2 + diff --git a/usrp2/host/lib/data_handler.cc b/usrp2/host/lib/data_handler.cc new file mode 100644 index 00000000..ba912368 --- /dev/null +++ b/usrp2/host/lib/data_handler.cc @@ -0,0 +1,32 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include + +namespace usrp2 { + + data_handler::~data_handler() + { + // default nop destructor + } + +} + diff --git a/usrp2/host/lib/eth_buffer.cc b/usrp2/host/lib/eth_buffer.cc new file mode 100644 index 00000000..7970ab87 --- /dev/null +++ b/usrp2/host/lib/eth_buffer.cc @@ -0,0 +1,273 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include "eth_buffer.h" +#include "ethernet.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define ETH_BUFFER_DEBUG 0 // define to 0 or 1 +#if ETH_BUFFER_DEBUG +#define DEBUG_LOG(x) ::write(2, (x), 1) +#else +#define DEBUG_LOG(X) +#endif + +#define MAX_MEM_SIZE 25e6 // ~0.25s @ 100 MB/s +#define MAX_SLAB_SIZE 131702 // 128 KB (FIXME fish out of /proc/slabinfo) +#define MAX_PKT_SIZE 1512 // we don't do jumbo frames + +namespace usrp2 { + + eth_buffer::eth_buffer(size_t rx_bufsize) + : d_fd(0), d_using_tpring(false), d_buflen(0), d_buf(0), d_frame_nr(0), + d_frame_size(0), d_head(0), d_ring(0), d_ethernet(new ethernet()) + { + if (rx_bufsize == 0) + d_buflen = (size_t)MAX_MEM_SIZE; + else + d_buflen = std::min((size_t)MAX_MEM_SIZE, rx_bufsize); + + memset(d_mac, 0, sizeof(d_mac)); + } + + eth_buffer::~eth_buffer() + { + close(); + } + + bool + eth_buffer::open(const std::string &ifname, int protocol) + { + if (!d_ethernet->open(ifname, protocol)) { + std::cerr << "eth_buffer: unable to open interface " + << ifname << std::endl; + return false; + } + + d_fd = d_ethernet->fd(); + memcpy(d_mac, d_ethernet->mac(), sizeof(d_mac)); + + struct tpacket_req req; + size_t page_size = getpagesize(); + + // Calculate minimum power-of-two aligned size for frames + req.tp_frame_size = + (unsigned int)rint(pow(2, ceil(log2(TPACKET_ALIGN(TPACKET_HDRLEN)+TPACKET_ALIGN(MAX_PKT_SIZE))))); + d_frame_size = req.tp_frame_size; + + // Calculate minimum contiguous pages needed to enclose a frame + int npages = (page_size > req.tp_frame_size) ? 1 : ((req.tp_frame_size+page_size-1)/page_size); + req.tp_block_size = page_size << (int)ceil(log2(npages)); + + // Calculate number of blocks + req.tp_block_nr = std::min((int)(MAX_SLAB_SIZE/sizeof(void*)), + (int)(d_buflen/req.tp_block_size)); + + // Recalculate buffer length + d_buflen = req.tp_block_nr*req.tp_block_size; + + // Finally, calculate total number of frames. Since frames, blocks, + // and pages are all power-of-two aligned, frames are contiguous + req.tp_frame_nr = d_buflen/req.tp_frame_size; + d_frame_nr = req.tp_frame_nr; + +#if 0 + if (ETH_BUFFER_DEBUG) + std::cerr << "eth_buffer:" + << " frame_size=" << req.tp_frame_size + << " block_size=" << req.tp_block_size + << " block_nr=" << req.tp_block_nr + << " frame_nr=" << req.tp_frame_nr + << " buflen=" << d_buflen + << std::endl; +#endif + + // Try to get kernel shared memory buffer + if (setsockopt(d_fd, SOL_PACKET, PACKET_RX_RING, (void *)&req, sizeof(req))) { + perror("eth_buffer: setsockopt"); + d_using_tpring = false; + if (!(d_buf = (uint8_t *)malloc(d_buflen))) { + std::cerr << "eth_buffer: failed to allocate packet memory" << std::endl; + return false; + } + + std::cerr << "eth_buffer: using malloc'd memory for buffer" << std::endl; + } + else { + d_using_tpring = true; + void *p = mmap(0, d_buflen, PROT_READ|PROT_WRITE, MAP_SHARED, d_fd, 0); + if (p == MAP_FAILED){ + perror("eth_buffer: mmap"); + return false; + } + d_buf = (uint8_t *) p; + + if (ETH_BUFFER_DEBUG) + std::cerr << "eth_buffer: using kernel shared mem for buffer" << std::endl; + } + + // Initialize our pointers into the packet ring + d_ring = std::vector(req.tp_frame_nr); + for (unsigned int i=0; i < req.tp_frame_nr; i++) { + d_ring[i] = (uint8_t *)(d_buf+i*req.tp_frame_size); + } + + // If not using kernel ring, instantiate select/read thread here + + return true; + } + + bool + eth_buffer::close() + { + // if we have background thread, stop it here + + if (!d_using_tpring && d_buf) + free(d_buf); + + return d_ethernet->close(); + } + + bool + eth_buffer::attach_pktfilter(pktfilter *pf) + { + return d_ethernet->attach_pktfilter(pf); + } + + inline bool + eth_buffer::frame_available() + { + return (((tpacket_hdr *)d_ring[d_head])->tp_status != TP_STATUS_KERNEL); + } + + eth_buffer::result + eth_buffer::rx_frames(data_handler *f, int timeout_in_ms) + { + DEBUG_LOG("\n"); + + while (!frame_available()) { + if (timeout_in_ms == 0) { + DEBUG_LOG("w"); + return EB_WOULD_BLOCK; + } + + struct pollfd pfd; + pfd.fd = d_fd; + pfd.revents = 0; + pfd.events = POLLIN; + + DEBUG_LOG("P"); + + int pres = poll(&pfd, 1, timeout_in_ms); + if (pres == -1) { + perror("poll"); + return EB_ERROR; + } + + if (pres == 0) { + DEBUG_LOG("t"); + return EB_TIMED_OUT; + } + } + + // Iterate through available packets + while (frame_available()) { + // Get start of ethernet frame and length + tpacket_hdr *hdr = (tpacket_hdr *)d_ring[d_head]; + void *base = (uint8_t *)hdr+hdr->tp_mac; + size_t len = hdr->tp_len; + + // FYI, (base % 4 == 2) Not what we want given the current FPGA + // code. This means that our uint32_t samples are not 4-byte + // aligned. We'll have to deal with it downstream. + + if (0) + fprintf(stderr, "eth_buffer: base = %p tp_mac = %3d tp_net = %3d\n", + base, hdr->tp_mac, hdr->tp_net); + + // Invoke data handler + data_handler::result r = (*f)(base, len); + if (!(r & data_handler::KEEP)) + hdr->tp_status = TP_STATUS_KERNEL; // mark it free + + inc_head(); + + if (r & data_handler::DONE) + break; + } + + DEBUG_LOG("|"); + return EB_OK; + } + + eth_buffer::result + eth_buffer::tx_frame(const void *base, size_t len, int flags) + { + DEBUG_LOG("T"); + + if (flags & EF_DONTWAIT) // FIXME: implement flags + throw std::runtime_error("tx_frame: EF_DONTWAIT not implemented"); + + int res = d_ethernet->write_packet(base, len); + if (res < 0 || (unsigned int)res != len) + return EB_ERROR; + + return EB_OK; + } + + eth_buffer::result + eth_buffer::tx_framev(const eth_iovec *iov, int iovcnt, int flags) + { + DEBUG_LOG("T"); + + if (flags & EF_DONTWAIT) // FIXME: implement flags + throw std::runtime_error("tx_frame: EF_DONTWAIT not implemented"); + + int res = d_ethernet->write_packetv(iov, iovcnt); + if (res < 0) + return EB_ERROR; + + return EB_OK; + } + + void + eth_buffer::release_frame(void *base) + { + // Get d_frame_size aligned header + tpacket_hdr *hdr = (tpacket_hdr *)((intptr_t)base & ~(d_frame_size-1)); + hdr->tp_status = TP_STATUS_KERNEL; // mark it free + } + +} // namespace usrp2 diff --git a/usrp2/host/lib/eth_buffer.h b/usrp2/host/lib/eth_buffer.h new file mode 100644 index 00000000..8dee9a4a --- /dev/null +++ b/usrp2/host/lib/eth_buffer.h @@ -0,0 +1,198 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef INCLUDED_USRP2_ETH_BUFFER_H +#define INCLUDED_USRP2_ETH_BUFFER_H + +#include "pktfilter.h" +#include +#include +#include +#include +#include + +namespace usrp2 { + + class ethernet; + class data_handler; + + /*! + * \brief high-performance interface to send and receive raw + * ethernet frames with out-of-order retirement of received frames. + * + * On many systems it should be possible to implement this on top of libpcap + * + * \internal + */ + class eth_buffer : boost::noncopyable + { + + int d_fd; // socket file descriptor + uint8_t d_mac[6]; // our mac address + bool d_using_tpring; // using kernel mapped packet ring + size_t d_buflen; // length of our buffer + uint8_t *d_buf; // packet ring + unsigned int d_frame_nr; // max frames on ring + size_t d_frame_size; // frame storage size + unsigned int d_head; // pointer to next frame + + std::vector d_ring; // pointers into buffer + std::auto_ptr d_ethernet; // our underlying interface + + bool frame_available(); + + void inc_head() + { + if (d_head + 1 >= d_frame_nr) + d_head = 0; + else + d_head = d_head + 1; + } + + + public: + + enum result { + EB_OK, //< everything's fine + EB_ERROR, //< A non-recoverable error occurred + EB_WOULD_BLOCK, //< A timeout of 0 was specified and nothing was ready + EB_TIMED_OUT, //< The timeout expired before anything was ready + }; + + static const unsigned int MAX_PKTLEN = 1512; + static const unsigned int MIN_PKTLEN = 64; + + /*! + * \param rx_bufsize is a hint as to the number of bytes of memory + * to allocate for received ethernet frames (0 -> reasonable default) + */ + eth_buffer(size_t rx_bufsize = 0); + ~eth_buffer(); + + /*! + * \brief open the specified interface + * + * \param ifname ethernet interface name, e.g., "eth0" + * \param protocol is the ethertype protocol number in network order. + * Use 0 to receive all protocols. + */ + bool open(const std::string &ifname, int protocol); + + /*! + * \brief close the interface + */ + bool close(); + + /*! + * \brief attach packet filter to socket to restrict which packets read sees. + * \param pf the packet filter + */ + bool attach_pktfilter(pktfilter *pf); + + /*! + * \brief return 6 byte string containing our MAC address + */ + const uint8_t *mac() const { return d_mac; } + + /*! + * \brief Call \p f for each frame in the receive buffer. + * \param f is the frame data handler + * \param timeout (in ms) controls behavior when there are no frames to read + * + * If \p timeout is 0, rx_frames will not wait for frames if none are + * available, and f will not be invoked. If \p timeout is -1 (the + * default), rx_frames will block indefinitely until frames are + * available. If \p timeout is positive, it indicates the number of + * milliseconds to wait for a frame to become available. Once the + * timeout has expired, rx_frames will return, f never having been + * invoked. + * + * \p f will be called on each ethernet frame that is available. + * \p f returns a bit mask with one of the following set or cleared: + * + * data_handler::KEEP - hold onto the frame and present it again during + * the next call to rx_frames, otherwise discard it + * + * data_handler::DONE - return from rx_frames now even though more frames + * might be available; otherwise continue if more + * frames are ready. + * + * The idea of holding onto a frame for the next iteration allows + * the caller to scan the received packet stream for particular + * classes of frames (such as command replies) leaving the rest + * intact. On the next call all kept frames, followed by any new + * frames received, will be presented in order to \p f. + * See usrp2.cc for an example of the pattern. + * + * \returns EB_OK if at least one frame was received + * \returns EB_WOULD_BLOCK if \p timeout is 0 and the call would have blocked + * \returns EB_TIMED_OUT if timeout occurred + * \returns EB_ERROR if there was an unrecoverable error. + */ + result rx_frames(data_handler *f, int timeout=-1); + + /* + * \brief Release frame from buffer + * + * Call to release a frame previously held by a data_handler::KEEP. + * The pointer may be offset from the base of the frame up to its length. + */ + void release_frame(void *p); + + /* + * \brief Write an ethernet frame to the interface. + * + * \param base points to the beginning of the frame (the 14-byte ethernet header). + * \param len is the length of the frame in bytes. + * \param flags is 0 or the bitwise-or of values from eth_flags + * + * The frame must begin with a 14-byte ethernet header. + * + * \returns EB_OK if the frame was successfully enqueued. + * \returns EB_WOULD_BLOCK if flags contains EF_DONT_WAIT and the call would have blocked. + * \returns EB_ERROR if there was an unrecoverable error. + */ + result tx_frame(const void *base, size_t len, int flags=0); + + /* + * \brief Write an ethernet frame to the interface using scatter/gather. + * + * \param iov points to an array of iovec structs + * \param iovcnt is the number of entries + * \param flags is 0 or the bitwise-or of values from eth_flags + * + * The frame must begin with a 14-byte ethernet header. + * + * \returns EB_OK if the frame was successfully enqueued. + * \returns EB_WOULD_BLOCK if flags contains EF_DONT_WAIT and the call would have blocked. + * \returns EB_ERROR if there was an unrecoverable error. + */ + result tx_framev(const eth_iovec *iov, int iovcnt, int flags=0); + + /* + * \brief Returns maximum possible number of frames in buffer + */ + unsigned int max_frames() const { return d_frame_nr; } + + }; + +}; // namespace usrp2 + +#endif /* INCLUDED_USRP2_ETH_BUFFER_H */ diff --git a/usrp2/host/lib/eth_common.h b/usrp2/host/lib/eth_common.h new file mode 100644 index 00000000..7c9feaa2 --- /dev/null +++ b/usrp2/host/lib/eth_common.h @@ -0,0 +1,38 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef INCLUDED_USRP2_ETH_COMMON_H +#define INCLUDED_USRP2_ETH_COMMON_H + +#include // FIXME autoconf this + +namespace usrp2 { + + enum eth_flags { + EF_DONTWAIT = 0x0001, + }; + + typedef struct iovec eth_iovec; // FIXME autoconf this + +} // namespace usrp2 + + +#endif /* INCLUDED_USRP2_ETH_COMMON_H */ diff --git a/usrp2/host/lib/ethernet.cc b/usrp2/host/lib/ethernet.cc new file mode 100644 index 00000000..65e989ce --- /dev/null +++ b/usrp2/host/lib/ethernet.cc @@ -0,0 +1,228 @@ +/* -*- c++ -*- */ +/* + * Copyright 2005,2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include "ethernet.h" +#include "pktfilter.h" +#include + +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include // packet filter + +namespace usrp2 { + + static int + open_packet_socket (std::string ifname, int protocol) + { +#if 0 + if (protocol == 0) + protocol = htons(ETH_P_ALL); + + int fd = socket (PF_PACKET, SOCK_RAW, protocol); +#else + int fd = usrp2::open_usrp2_socket(); +#endif + + if (fd == -1){ + fprintf (stderr, "%s: socket: %s\n", ifname.c_str(), strerror (errno)); + return -1; + } + + // get interface index + struct ifreq ifr; + memset (&ifr, 0, sizeof(ifr)); + strncpy (ifr.ifr_name, ifname.c_str(), sizeof (ifr.ifr_name)); + int res = ioctl (fd, SIOCGIFINDEX, &ifr); + if (res != 0){ + ::close (fd); + fprintf (stderr, "%s: SIOCGIFINDEX: %s\n", ifname.c_str(), strerror(errno)); + return -1; + } + int ifindex = ifr.ifr_ifindex; + + // bind to the specified interface + sockaddr_ll sa; + memset (&sa, 0, sizeof (sa)); + sa.sll_family = AF_PACKET; + sa.sll_protocol = protocol; + sa.sll_ifindex = ifindex; + res = bind (fd, (struct sockaddr *)&sa, sizeof (sa)); + if (res != 0){ + ::close (fd); + fprintf (stderr, "%s: bind: %s\n", ifname.c_str(), strerror(errno)); + return -1; + } + return fd; + } + + static void + extract_mac_addr (unsigned char *mac, const unsigned char *hwaddr) + { + int i; + for (i = 0; i < 6; i++) + mac[i] = 0xff; + + i = 0; + for (int j = 0; j < 14; j++){ + if (hwaddr[j] != 0xff){ + mac[i++] = hwaddr[j]; + if (i == 6) + return; + } + } + } + + static bool + get_mac_addr (std::string ifname, int fd, unsigned char *mac) + { + struct ifreq ifr; + memset (&ifr, 0, sizeof(ifr)); + strncpy (ifr.ifr_name, ifname.c_str(), sizeof (ifr.ifr_name)); + int res = ioctl (fd, SIOCGIFHWADDR, &ifr); + if (res != 0){ + fprintf (stderr, "%s: SIOCGIFHWADDR: %s\n", ifname.c_str(), strerror(errno)); + return false; + } + else { + if (0){ + for (unsigned i = 0; i < sizeof (ifr.ifr_hwaddr.sa_data); i++) + fprintf (stderr, "%02x", ifr.ifr_hwaddr.sa_data[i]); + fprintf (stderr, "\n"); + } + } + extract_mac_addr (mac, (unsigned char *)ifr.ifr_hwaddr.sa_data); + return true; + } + + ethernet::ethernet () + { + d_fd = -1; + memset (d_mac, 0, sizeof (d_mac)); + } + + ethernet::~ethernet () + { + close (); + } + + bool + ethernet::open (std::string ifname, int protocol) + { + if (d_fd != -1){ + fprintf (stderr, "ethernet: already open\n"); + return false; + } + if ((d_fd = open_packet_socket (ifname, protocol)) == -1){ + return false; + } + get_mac_addr (ifname, d_fd, d_mac); + return true; + } + + bool + ethernet::close () + { + if (d_fd >= 0){ + ::close (d_fd); + d_fd = -1; + } + return true; + } + + int + ethernet::read_packet (void *buf, int buflen) + { + int len = recvfrom (d_fd, buf, buflen, 0, (sockaddr *) 0, 0); + return len; + } + + int + ethernet::read_packet_dont_block (void *buf, int buflen) + { + int len = recvfrom (d_fd, buf, buflen, MSG_DONTWAIT, 0, 0); + if (len == -1 && errno == EAGAIN) + return 0; + + return len; + } + + int + ethernet::write_packet (const void *buf, int buflen) + { + int retval = send (d_fd, buf, buflen, 0); + if (retval < 0){ + if (errno == EINTR) + return write_packet (buf, buflen); + + perror ("ethernet:write_packet: send"); + return -1; + } + return retval; + } + + int + ethernet::write_packetv(const eth_iovec *iov, size_t iovlen) + { + struct msghdr mh; + memset(&mh, 0, sizeof(mh)); + mh.msg_iov = const_cast(iov); + mh.msg_iovlen = iovlen; + + int retval = sendmsg(d_fd, &mh, 0); + if (retval < 0){ + if (errno == EINTR) + return write_packetv(iov, iovlen); + + perror("ethernet:write_packetv: send"); + return -1; + } + return retval; + } + + bool + ethernet::attach_pktfilter (pktfilter *pf) + { + struct sock_fprog filter; + filter.len = pf->d_len; + filter.filter = pf->d_inst; + + int r = setsockopt (d_fd, SOL_SOCKET, SO_ATTACH_FILTER, &filter, sizeof (filter)); + if (r < 0){ + perror ("ethernet:attach: SO_ATTACH_FILTER"); + return false; + } + return true; + } + +} // namespace usrp2 diff --git a/usrp2/host/lib/ethernet.h b/usrp2/host/lib/ethernet.h new file mode 100644 index 00000000..24624f44 --- /dev/null +++ b/usrp2/host/lib/ethernet.h @@ -0,0 +1,124 @@ +/* -*- c++ -*- */ +/* + * Copyright 2005,2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_USRP2_ETHERNET_H +#define INCLUDED_USRP2_ETHERNET_H + +#include +#include +#include + +namespace usrp2 { + + class pktfilter; + + /*! + * \brief Read and write ethernet frames. + * + * This provides a low level interface to hardware that communicates + * via raw (non-IP) ethernet frames. + */ + class ethernet { + int d_fd; + uint8_t d_mac[6]; + + public: + ethernet (); + ~ethernet (); + + static const int MAX_PKTLEN = 1512; + static const int MIN_PKTLEN = 64; + + /*! + * \param ifname ethernet interface name, e.g., "eth0" + * \param protocol is the ethertype protocol number in network order. + * Use 0 to receive all protocols. + */ + bool open (std::string ifname, int protocol); + + bool close (); + + /*! + * \brief attach packet filter to socket to restrict which packets read sees. + * \param pf the packet filter + */ + bool attach_pktfilter (pktfilter *pf); + + /*! + * \brief return 6 byte string containing our MAC address + */ + const uint8_t *mac () const { return d_mac; } + + /*! + * \brief Return file descriptor associated with socket. + */ + int fd () const { return d_fd; } + + /*! + * \brief Read packet from interface. + * + * \param buf where to put the packet + * \param buflen maximum length of packet in bytes (should be >= 1528) + * + * \returns number of bytes read or -1 if trouble. + * + * Returned packet includes 14-byte ethhdr + */ + int read_packet (void *buf, int buflen); + + /*! + * \brief Read packet from interface, but don't block waiting + * + * \param buf where to put the packet + * \param buflen maximum length of packet in bytes (should be >= 1528) + * + * \returns number of bytes read, -1 if trouble or 0 if nothing available. + * + * Returned packet includes 14-byte ethhdr + */ + int read_packet_dont_block (void *buf, int buflen); + + /* + * \brief Write ethernet packet to interface. + * + * \param buf the packet to write + * \param buflen length of packet in bytes + * + * \returns number of bytes written or -1 if trouble. + * + * Packet must begin with 14-byte ethhdr, but does not include the FCS. + */ + int write_packet (const void *buf, int buflen); + + /* + * \brief Write ethernet packet to interface. + * + * \param iov scatter/gather array + * \param iovlen number of elements in iov + * + * \returns number of bytes written or -1 if trouble. + * + * Packet must begin with 14-byte ethhdr, but does not include the FCS. + */ + int write_packetv (const eth_iovec *iov, size_t iovlen); + + }; + +} // namespace usrp2 + +#endif /* INCLUDED_USRP2_ETHERNET_H */ diff --git a/usrp2/host/lib/find.cc b/usrp2/host/lib/find.cc new file mode 100644 index 00000000..f6c04a58 --- /dev/null +++ b/usrp2/host/lib/find.cc @@ -0,0 +1,181 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include +#include +#include "ethernet.h" +#include "pktfilter.h" +#include +#include +#include + +#define FIND_DEBUG 0 + + +// FIXME move to gruel + +static struct timeval +time_duration_to_timeval(boost::posix_time::time_duration delta) +{ + long total_us = delta.total_microseconds(); + if (total_us < 0) + throw std::invalid_argument("duration_to_time: delta is negative"); + + struct timeval tv; + tv.tv_sec = total_us / 1000000; + tv.tv_usec = total_us % 1000000; + return tv; +} + + +namespace usrp2 { + + static props + reply_to_props(const op_id_reply_t *r) + { + const uint8_t *mac = (const uint8_t *)&r->addr; + char addr_buf[128]; + snprintf(addr_buf, sizeof(addr_buf), "%02x:%02x:%02x:%02x:%02x:%02x", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + + props p; + p.addr = std::string(addr_buf); + p.hw_rev = ntohs(r->hw_rev); + memcpy(p.fpga_md5sum, r->fpga_md5sum, sizeof(p.fpga_md5sum)); + memcpy(p.sw_md5sum, r->sw_md5sum, sizeof(p.sw_md5sum)); + return p; + } + + static void + read_replies(ethernet *enet, struct timeval timeout, + const std::string &target_addr, props_vector_t &result) + { + struct reply { + u2_eth_packet_t h; + op_id_reply_t op_id_reply; + }; + + uint8_t pktbuf[ethernet::MAX_PKTLEN]; + memset(pktbuf, 0, sizeof(pktbuf)); + + fd_set read_fds; + FD_ZERO(&read_fds); + FD_SET(enet->fd(), &read_fds); + + select(enet->fd()+1, &read_fds, 0, 0, &timeout); + while(1) { + memset(pktbuf, 0, sizeof(pktbuf)); + int len = enet->read_packet_dont_block(pktbuf, sizeof(pktbuf)); + if (len < 0){ + perror("usrp2_basic: read_packet_dont_block"); + return; + } + if (len == 0) + break; + + reply *rp = (reply *)pktbuf; + if (u2p_chan(&rp->h.fixed) != CONTROL_CHAN) // ignore + continue; + if (rp->op_id_reply.opcode != OP_ID_REPLY) // ignore + continue; + + props p = reply_to_props(&rp->op_id_reply); + if (FIND_DEBUG) + std::cerr << "usrp2::find: response from " << p.addr << std::endl; + + if ((target_addr == "") || (target_addr == p.addr)) + result.push_back(p); + } + } + + props_vector_t + find(const std::string &ifc, const std::string &addr) + { + if (FIND_DEBUG) { + std::cerr << "usrp2::find: Searching interface " << ifc << " for " + << (addr == "" ? "all USRP2s" : addr) + << std::endl; + } + + props_vector_t result; + struct command { + u2_eth_packet_t h; + op_generic_t op_id; + }; + + std::auto_ptr enet(new ethernet()); + + if (!enet->open(ifc, htons(U2_ETHERTYPE))) + return result; + + std::auto_ptr pf(pktfilter::make_ethertype_inbound(U2_ETHERTYPE, enet->mac())); + if (!enet->attach_pktfilter(pf.get())) + return result; + + static u2_mac_addr_t broadcast_mac_addr = + {{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }}; + + uint8_t pktbuf[ethernet::MAX_PKTLEN]; + memset(pktbuf, 0, sizeof(pktbuf)); + + command *c = (command *)pktbuf; + c->h.ehdr.ethertype = htons(U2_ETHERTYPE); + c->h.ehdr.dst = broadcast_mac_addr; + memcpy(&c->h.ehdr.src, enet->mac(), 6); + c->h.thdr.flags = 0; + c->h.thdr.seqno = 0; + c->h.thdr.ack = 0; + u2p_set_word0(&c->h.fixed, 0, CONTROL_CHAN); + u2p_set_timestamp(&c->h.fixed, -1); + c->op_id.opcode = OP_ID; + c->op_id.len = sizeof(c->op_id); + int len = std::max((size_t) ethernet::MIN_PKTLEN, sizeof(command)); + if (enet->write_packet(c, len) != len) + return result; + + if (FIND_DEBUG) + std::cerr << "usrp2::find: broadcast ID command" << std::endl; + + /* + * Gather all responses that occur within 50ms + */ + boost::posix_time::ptime start(boost::posix_time::microsec_clock::universal_time()); + boost::posix_time::ptime limit(start + boost::posix_time::milliseconds(50)); + boost::posix_time::ptime now; + + while (1){ + now = boost::posix_time::microsec_clock::universal_time(); + if (now >= limit) + break; + + boost::posix_time::time_duration delta(limit - now); + struct timeval timeout = time_duration_to_timeval(delta); + + read_replies(enet.get(), timeout, addr, result); + } + return result; + } + +} // namespace usrp2 + diff --git a/usrp2/host/lib/open_usrp2_socket.cc b/usrp2/host/lib/open_usrp2_socket.cc new file mode 100644 index 00000000..cd729205 --- /dev/null +++ b/usrp2/host/lib/open_usrp2_socket.cc @@ -0,0 +1,130 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif +#include +#include +#include +#include +#include +#include +#include + +static const char *helper = "usrp2_socket_opener"; + +static ssize_t +read_fd(int fd, void *ptr, size_t nbytes, int *recvfd) +{ + struct msghdr msg; + struct iovec iov[1]; + ssize_t n; + +#ifdef HAVE_STRUCT_MSGHDR_MSG_CONTROL + union { + struct cmsghdr cm; + char control[CMSG_SPACE(sizeof (int))]; + } control_un; + struct cmsghdr *cmptr; + + msg.msg_control = control_un.control; + msg.msg_controllen = sizeof(control_un.control); +#else + int newfd; + + msg.msg_accrights = (char *) &newfd; + msg.msg_accrightslen = sizeof(int); +#endif + + msg.msg_name = NULL; + msg.msg_namelen = 0; + + iov[0].iov_base = ptr; + iov[0].iov_len = nbytes; + msg.msg_iov = iov; + msg.msg_iovlen = 1; + + if ((n = recvmsg(fd, &msg, 0)) <= 0) + return n; + +#ifdef HAVE_STRUCT_MSGHDR_MSG_CONTROL + if ((cmptr = CMSG_FIRSTHDR(&msg)) != NULL + && cmptr->cmsg_len == CMSG_LEN(sizeof(int))){ + if (cmptr->cmsg_level != SOL_SOCKET){ + fprintf(stderr, "read_fd: control level != SOL_SOCKET\n"); + return -1; + } + if (cmptr->cmsg_type != SCM_RIGHTS){ + fprintf(stderr, "read_fd: control type != SCM_RIGHTS\n"); + return -1; + } + *recvfd = *((int *) CMSG_DATA(cmptr)); + } else + *recvfd = -1; /* descriptor was not passed */ +#else + if (msg.msg_accrightslen == sizeof(int)) + *recvfd = newfd; + else + *recvfd = -1; /* descriptor was not passed */ +#endif + + return n; +} + +int +usrp2::open_usrp2_socket() +{ + int fd = -1, sockfd[2], status; + pid_t childpid; + char c, argsockfd[10]; + + if (socketpair(AF_LOCAL, SOCK_STREAM, 0, sockfd) != 0){ + perror("socketpair"); + return -1; + } + + if ((childpid = fork()) == 0) { /* child process */ + close(sockfd[0]); + snprintf(argsockfd, sizeof(argsockfd), "%d", sockfd[1]); + execlp(helper, helper, argsockfd, (char *) NULL); + std::string msg("execlp: couldn't exec " + std::string(helper)); + perror(msg.c_str()); + close(sockfd[0]); + close(sockfd[1]); + return -1; + } + + /* parent process - wait for the child to terminate */ + close(sockfd[1]); /* close the end we don't use */ + + waitpid(childpid, &status, 0); + if (!WIFEXITED(status)){ + fprintf(stderr, "child did not terminate\n"); + return -1; + } + if ((status = WEXITSTATUS(status)) == 0) + read_fd(sockfd[0], &c, 1, &fd); + else { + errno = status; /* bogus: set errno value from child's status */ + fd = -1; + } + + close(sockfd[0]); + return (fd); +} diff --git a/usrp2/host/lib/open_usrp2_socket.h b/usrp2/host/lib/open_usrp2_socket.h new file mode 100644 index 00000000..d42440ea --- /dev/null +++ b/usrp2/host/lib/open_usrp2_socket.h @@ -0,0 +1,34 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef INCLUDED_OPEN_USRP2_SOCKET_H +#define INCLUDED_OPEN_USRP2_SOCKET_H + +namespace usrp2 { + + /*! + * Return the result of executing: + * + * int fd = socket(PF_PACKET, SOCK_RAW, htons(0xBEEF)); + * + * Doing it in a way that we don't need to be running as root. + */ + int open_usrp2_socket(); +}; + + +#endif /* INCLUDED_OPEN_USRP2_SOCKET_H */ diff --git a/usrp2/host/lib/pktfilter.cc b/usrp2/host/lib/pktfilter.cc new file mode 100644 index 00000000..8341d015 --- /dev/null +++ b/usrp2/host/lib/pktfilter.cc @@ -0,0 +1,152 @@ +/* -*- c++ -*- */ +/* + * Copyright 2005,2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include "pktfilter.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include // packet filter + +namespace usrp2 { + + /* + * This is all based on the Berkeley Packet Filter (BPF) as implemented on Linux. + * + * The BPF allows you to run an interpreted program (a filter) in the + * kernel that sorts through the packets looking for ones you are + * interested in. This eliminates the overhead of passing all of the + * networking packets up into user space for filtering there. + * + * For documentation on this see + * /usr/src/linux/Documentation/networking/filter.txt, The BSD + * Berkeley Packet Filter manual page, and "The BSD Packet Filter: A + * New Architecture for User-level Packet Capture", by Steven McCanne + * and Van Jacobson. + */ + + pktfilter::pktfilter () + : d_len (0), d_inst (0) + { + // NOP + } + + pktfilter::~pktfilter () + { + delete [] d_inst; + } + + inline static sock_filter + make_stmt (__u16 code, __u32 k) + { + sock_filter f; + f.code = code; + f.jt = 0; + f.jf = 0; + f.k = k; + return f; + } + + inline static sock_filter + make_jump (__u16 code, __u32 k, __u8 jt, __u8 jf) + { + sock_filter f; + f.code = code; + f.jt = jt; + f.jf = jf; + f.k = k; + return f; + } + + /* + * Return a filter that harvests packets with the specified ethertype. + */ + pktfilter * + pktfilter::make_ethertype (unsigned short ethertype) + { + static const int MAX_LEN = 20; + sock_filter *inst = new sock_filter [MAX_LEN]; + pktfilter *pf = new pktfilter (); + + // nothing quite like coding in assembly without the benefit of an assembler ;-) + + // ignore packets that don't have the right ethertype + + int i = 0; + inst[i++] = make_stmt (BPF_LD|BPF_H|BPF_ABS, 12); // load ethertype + inst[i++] = make_jump (BPF_JMP|BPF_JEQ|BPF_K, ethertype, 1, 0); + inst[i++] = make_stmt (BPF_RET|BPF_K, 0); // return 0 (ignore packet) + inst[i++] = make_stmt (BPF_RET|BPF_K, (unsigned) -1); // return whole packet + + assert (i <= MAX_LEN); + + pf->d_inst = inst; + pf->d_len = i; + + return pf; + } + + /* + * Return a filter that harvests inbound packets with the specified ethertype. + * \param ethertype the ethertype we're looking for + * \param our_mac our ethernet MAC address so we can avoid pkts we sent + */ + pktfilter * + pktfilter::make_ethertype_inbound (unsigned short ethertype, const unsigned char *our_mac) + { + static const int MAX_LEN = 20; + sock_filter *inst = new sock_filter [MAX_LEN]; + pktfilter *pf = new pktfilter (); + + __u16 smac_hi = (our_mac[0] << 8) | our_mac[1]; + __u32 smac_lo = (our_mac[2] << 24) | (our_mac[3] << 16) | (our_mac[4] << 8) | our_mac[5]; + + // nothing quite like coding in assembly without the benefit of an assembler ;-) + + // ignore packets that have a different ethertype + // and packets that have a source mac address == our_mac (packets we sent) + + int i = 0; + inst[i++] = make_stmt (BPF_LD|BPF_H|BPF_ABS, 12); // load ethertype + inst[i++] = make_jump (BPF_JMP|BPF_JEQ|BPF_K, ethertype, 0, 5); + inst[i++] = make_stmt (BPF_LD|BPF_W|BPF_ABS, 8); // load low 32-bit of src mac + inst[i++] = make_jump (BPF_JMP|BPF_JEQ|BPF_K, smac_lo, 0, 2); + inst[i++] = make_stmt (BPF_LD|BPF_H|BPF_ABS, 6); // load high 16-bits of src mac + inst[i++] = make_jump (BPF_JMP|BPF_JEQ|BPF_K, smac_hi, 1, 0); + inst[i++] = make_stmt (BPF_RET|BPF_K, (unsigned) -1); // return whole packet + inst[i++] = make_stmt (BPF_RET|BPF_K, 0); // return 0 (ignore packet) + + assert (i <= MAX_LEN); + + pf->d_inst = inst; + pf->d_len = i; + + return pf; + } + +} // namespace usrp2 diff --git a/usrp2/host/lib/pktfilter.h b/usrp2/host/lib/pktfilter.h new file mode 100644 index 00000000..8b07fe14 --- /dev/null +++ b/usrp2/host/lib/pktfilter.h @@ -0,0 +1,55 @@ +/* -*- c++ -*- */ +/* + * Copyright 2005,2007,2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_USRP2_PKTFILTER_H +#define INCLUDED_USRP2_PKTFILTER_H + +struct sock_filter; + +namespace usrp2 { + + /* + * \brief Compile programs for the Berkeley Packet Filter + */ + class pktfilter { + public: + + unsigned d_len; // # of instructions + struct sock_filter *d_inst; // the instructions + + pktfilter (); + ~pktfilter (); + + /*! + * \brief Return a filter that harvests packets with the specified ethertype. + * \param ethertype the ethertype we're looking for. + */ + static pktfilter *make_ethertype (unsigned short ethertype); + + /*! + * \brief Return a filter that harvests inbound packets with the specified ethertype. + * \param ethertype the ethertype we're looking for + * \param our_mac our MAC address so we can avoid pkts we sent + */ + static pktfilter *make_ethertype_inbound (unsigned short ethertype, + const unsigned char *our_mac); + }; + +} // namespace usrp2 + +#endif /* INCLUDED_USRP2_PKTFILTER_H */ diff --git a/usrp2/host/lib/ring.cc b/usrp2/host/lib/ring.cc new file mode 100644 index 00000000..3c45821f --- /dev/null +++ b/usrp2/host/lib/ring.cc @@ -0,0 +1,78 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include "ring.h" + +namespace usrp2 { + + ring::ring(unsigned int entries) + : d_max(entries), d_read_ind(0), d_write_ind(0), d_ring(entries), + d_mutex(), d_not_empty(&d_mutex) + { + for (unsigned int i = 0; i < entries; i++) { + d_ring[i].d_base = 0; + d_ring[i].d_len = 0; + } + } + + void + ring::wait_for_not_empty() + { + omni_mutex_lock l(d_mutex); + while (empty()) + d_not_empty.wait(); + } + + bool + ring::enqueue(void *p, size_t len) + { + omni_mutex_lock l(d_mutex); + if (full()) + return false; + + d_ring[d_write_ind].d_len = len; + d_ring[d_write_ind].d_base = p; + + inc_write_ind(); + d_not_empty.signal(); + return true; + } + + bool + ring::dequeue(void **p, size_t *len) + { + omni_mutex_lock l(d_mutex); + if (empty()) + return false; + + *p = d_ring[d_read_ind].d_base; + *len = d_ring[d_read_ind].d_len; + + inc_read_ind(); + return true; + } + +} // namespace usrp2 + diff --git a/usrp2/host/lib/ring.h b/usrp2/host/lib/ring.h new file mode 100644 index 00000000..2f4346ca --- /dev/null +++ b/usrp2/host/lib/ring.h @@ -0,0 +1,83 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef INCLUDED_RING_H +#define INCLUDED_RING_H + +#include +#include +#include +#include + +namespace usrp2 { + + class ring; + typedef boost::shared_ptr ring_sptr; + + class ring + { + private: + + size_t d_max; + size_t d_read_ind; + size_t d_write_ind; + + struct ring_desc + { + void *d_base; + size_t d_len; + }; + std::vector d_ring; + + omni_mutex d_mutex; + omni_condition d_not_empty; + + void inc_read_ind() + { + if (d_read_ind + 1 >= d_max) + d_read_ind = 0; + else + d_read_ind = d_read_ind + 1; + } + + void inc_write_ind() + { + if (d_write_ind + 1 >= d_max) + d_write_ind = 0; + else + d_write_ind = d_write_ind + 1; + } + + bool empty() const { return d_read_ind == d_write_ind; } + bool full() const { return (d_write_ind+1)%d_max == d_read_ind; } + + public: + + ring(unsigned int entries); + + void wait_for_not_empty(); + + bool enqueue(void *p, size_t len); + bool dequeue(void **p, size_t *len); + }; + +} // namespace usrp2 + +#endif /* INCLUDED_RING_H */ diff --git a/usrp2/host/lib/rx_nop_handler.cc b/usrp2/host/lib/rx_nop_handler.cc new file mode 100644 index 00000000..96c9164a --- /dev/null +++ b/usrp2/host/lib/rx_nop_handler.cc @@ -0,0 +1,35 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include + +namespace usrp2 { + + rx_nop_handler::~rx_nop_handler() + { + } + +} // namespace usrp2 + diff --git a/usrp2/host/lib/rx_sample_handler.cc b/usrp2/host/lib/rx_sample_handler.cc new file mode 100644 index 00000000..4521025c --- /dev/null +++ b/usrp2/host/lib/rx_sample_handler.cc @@ -0,0 +1,27 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif +#include + +usrp2::rx_sample_handler::~rx_sample_handler() +{ + // nop +} diff --git a/usrp2/host/lib/strtod_si.c b/usrp2/host/lib/strtod_si.c new file mode 100644 index 00000000..5e5deb2b --- /dev/null +++ b/usrp2/host/lib/strtod_si.c @@ -0,0 +1,53 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#define true 1 +#define false 0 + +int +strtod_si(const char *s, double *result) +{ + *result = 0; + + char *endptr; + double r = strtod(s, &endptr); + if (s == endptr) + return false; + + switch (*endptr){ + case 'p': r *= 1e-12; break; + case 'n': r *= 1e-9; break; + case 'u': r *= 1e-6; break; + case 'm': r *= 1e-3; break; + case 'k': r *= 1e3; break; + case 'M': r *= 1e6; break; + case 'G': r *= 1e9; break; + case 'T': r *= 1e12; break; + default: + // ignore. FIXME could be more robust + break; + } + + *result = r; + return true; +} + + diff --git a/usrp2/host/lib/usrp2.cc b/usrp2/host/lib/usrp2.cc new file mode 100644 index 00000000..c71fb728 --- /dev/null +++ b/usrp2/host/lib/usrp2.cc @@ -0,0 +1,291 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include "usrp2_impl.h" +#include +#include +#include +#include +#include + +namespace usrp2 { + + // --- Table of weak pointers to usrps we know about --- + + // (Could be cleaned up and turned into a template) + + struct usrp_table_entry { + // inteface + normalized mac addr ("eth0:01:23:45:67:89:ab") + std::string key; + boost::weak_ptr value; + + usrp_table_entry(const std::string &_key, boost::weak_ptr _value) + : key(_key), value(_value) {} + }; + + typedef std::vector usrp_table; + + static boost::mutex s_table_mutex; + static usrp_table s_table; + + usrp2::sptr + usrp2::find_existing_or_make_new(const std::string &ifc, props *pr) + { + std::string key = ifc + ":" + pr->addr; + + boost::mutex::scoped_lock guard(s_table_mutex); + + for (usrp_table::iterator p = s_table.begin(); p != s_table.end();){ + if (p->value.expired()) // weak pointer is now dead + p = s_table.erase(p); // erase it + else { + if (key == p->key) // found it + return usrp2::sptr(p->value); + else + ++p; // keep looking + } + } + + // We don't have the USRP2 we're looking for + + // create a new one and stick it in the table. + usrp2::sptr r(new usrp2::usrp2(ifc, pr)); + usrp_table_entry t(key, r); + s_table.push_back(t); + + return r; + } + + // --- end of table code --- + + static bool + parse_mac_addr(const std::string &s, std::string &ns) + { + u2_mac_addr_t p; + + p.addr[0] = 0x00; // Matt's IAB + p.addr[1] = 0x50; + p.addr[2] = 0xC2; + p.addr[3] = 0x85; + p.addr[4] = 0x30; + p.addr[5] = 0x00; + + int len = s.size(); + switch (len) { + + case 5: + if (sscanf(s.c_str(), "%hhx:%hhx", &p.addr[4], &p.addr[5]) != 2) + return false; + break; + + case 17: + if (sscanf(s.c_str(), "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &p.addr[0], &p.addr[1], &p.addr[2], + &p.addr[3], &p.addr[4], &p.addr[5]) != 6) + return false; + break; + + default: + return false; + } + + char buf[128]; + snprintf(buf, sizeof(buf), + "%02x:%02x:%02x:%02x:%02x:%02x", + p.addr[0],p.addr[1],p.addr[2], + p.addr[3],p.addr[4],p.addr[5]); + ns = std::string(buf); + return true; + } + + usrp2::sptr + usrp2::make(const std::string &ifc, const std::string &addr) + { + std::string naddr = ""; + if (addr != "" && !parse_mac_addr(addr, naddr)) + throw std::runtime_error("Invalid MAC address"); + + props_vector_t u2s = find(ifc, naddr); + int n = u2s.size(); + + if (n == 0) { + if (addr == "") + throw std::runtime_error("No USRPs found on interface " + ifc); + else + throw std::runtime_error("No USRP found with addr " + addr + " on interface " + ifc); + } + + if (n > 1) + throw std::runtime_error("Multiple USRPs found on interface; must select by MAC address."); + + return find_existing_or_make_new(ifc, &u2s[0]); + } + + // Private constructor. Sole function is to create an impl. + usrp2::usrp2(const std::string &ifc, props *p) + : d_impl(new usrp2::impl(ifc, p)) + { + // NOP + } + + // Public class destructor. d_impl will auto-delete. + usrp2::~usrp2() + { + // NOP + } + + std::string + usrp2::mac_addr() + { + return d_impl->mac_addr(); + } + + bool + usrp2::burn_mac_addr(const std::string &new_addr) + { + return d_impl->burn_mac_addr(new_addr); + } + + + // Receive + + bool + usrp2::set_rx_gain(double gain) + { + return d_impl->set_rx_gain(gain); + } + + bool + usrp2::set_rx_center_freq(double frequency, tune_result *result) + { + return d_impl->set_rx_center_freq(frequency, result); + } + + bool + usrp2::set_rx_decim(int decimation_factor) + { + return d_impl->set_rx_decim(decimation_factor); + } + + bool + usrp2::set_rx_scale_iq(int scale_i, int scale_q) + { + return d_impl->set_rx_scale_iq(scale_i, scale_q); + } + + bool + usrp2::start_rx_streaming(unsigned int channel, unsigned int items_per_frame) + { + return d_impl->start_rx_streaming(channel, items_per_frame); + } + + bool + usrp2::rx_samples(unsigned int channel, rx_sample_handler *handler) + { + return d_impl->rx_samples(channel, handler); + } + + bool + usrp2::stop_rx_streaming(unsigned int channel) + { + return d_impl->stop_rx_streaming(channel); + } + + unsigned int + usrp2::rx_overruns() + { + return d_impl->rx_overruns(); + } + + unsigned int + usrp2::rx_missing() + { + return d_impl->rx_missing(); + } + + // Transmit + + bool + usrp2::set_tx_gain(double gain) + { + return d_impl->set_tx_gain(gain); + } + + bool + usrp2::set_tx_center_freq(double frequency, tune_result *result) + { + return d_impl->set_tx_center_freq(frequency, result); + } + + bool + usrp2::set_tx_interp(int interpolation_factor) + { + return d_impl->set_tx_interp(interpolation_factor); + } + + bool + usrp2::set_tx_scale_iq(int scale_i, int scale_q) + { + return d_impl->set_tx_scale_iq(scale_i, scale_q); + } + + bool + usrp2::tx_complex_float(unsigned int channel, + const std::complex *samples, + size_t nsamples, + const tx_metadata *metadata) + { + return d_impl->tx_complex_float(channel, samples, nsamples, metadata); + } + + bool + usrp2::tx_complex_int16(unsigned int channel, + const std::complex *samples, + size_t nsamples, + const tx_metadata *metadata) + { + return d_impl->tx_complex_int16(channel, samples, nsamples, metadata); + } + + bool + usrp2::tx_raw(unsigned int channel, + const uint32_t *items, + size_t nitems, + const tx_metadata *metadata) + { + return d_impl->tx_raw(channel, items, nitems, metadata); + } + +} // namespace usrp2 + + +std::ostream& operator<<(std::ostream &os, const usrp2::props &x) +{ + os << x.addr; + + char buf[128]; + snprintf(buf, sizeof(buf)," hw_rev = 0x%04x", x.hw_rev); + + os << buf; + return os; +} diff --git a/usrp2/host/lib/usrp2_bytesex.h b/usrp2/host/lib/usrp2_bytesex.h new file mode 100644 index 00000000..4f63d079 --- /dev/null +++ b/usrp2/host/lib/usrp2_bytesex.h @@ -0,0 +1,19 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include diff --git a/usrp2/host/lib/usrp2_impl.cc b/usrp2/host/lib/usrp2_impl.cc new file mode 100644 index 00000000..68cf676c --- /dev/null +++ b/usrp2/host/lib/usrp2_impl.cc @@ -0,0 +1,870 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include +#include +#include +#include "usrp2_impl.h" +#include "usrp2_thread.h" +#include "eth_buffer.h" +#include "pktfilter.h" +#include "control.h" +#include "ring.h" +#include +#include +#include +#include +#include +#include + +#define USRP2_IMPL_DEBUG 0 +#if USRP2_IMPL_DEBUG +#define DEBUG_LOG(x) ::write(2, x, 1) +#else +#define DEBUG_LOG(x) +#endif + +static const int DEFAULT_RX_SCALE = 1024; +static const int DEFAULT_TX_SCALE = 3000; + +namespace usrp2 { + + static const double DEF_CMD_TIMEOUT = 0.1; + + std::string + opcode_to_string(int opcode) + { + switch(opcode){ + case OP_EOP: return "OP_EOP"; + case OP_ID: return "OP_ID"; + case OP_ID_REPLY: return "OP_ID_REPLY"; + case OP_BURN_MAC_ADDR: return "OP_BURN_MAC_ADDR"; + case OP_READ_TIME: return "OP_READ_TIME"; + case OP_READ_TIME_REPLY: return "OP_READ_TIME_REPLY"; + case OP_CONFIG_RX_V2: return "OP_CONFIG_RX_V2"; + case OP_CONFIG_RX_REPLY_V2: return "OP_CONFIG_RX_REPLY_V2"; + case OP_CONFIG_TX_V2: return "OP_CONFIG_TX_V2"; + case OP_CONFIG_TX_REPLY_V2: return "OP_CONFIG_TX_REPLY_V2"; + case OP_START_RX_STREAMING: return "OP_START_RX_STREAMING"; + case OP_STOP_RX: return "OP_STOP_RX"; +#if 0 + case OP_WRITE_REG: return "OP_WRITE_REG"; + case OP_WRITE_REG_MASKED: return "OP_WRITE_REG_MASKED"; + case OP_READ_REG: return "OP_READ_REG"; + case OP_READ_REG_REPLY: return "OP_READ_REG_REPLY"; +#endif + default: + char buf[64]; + snprintf(buf, sizeof(buf), "", opcode); + return buf; + } + } + + + /*! + * \param p points to fixed header + * \param payload_len_in_bytes is length of the fixed hdr and the payload + * \param[out] items is set to point to the first uint32 item in the payload + * \param[out] nitems is set to the number of uint32 items in the payload + * \param[out] md is filled in with the parsed metadata from the frame. + */ + static bool + parse_rx_metadata(void *p, size_t payload_len_in_bytes, + uint32_t **items, size_t *nitems_in_uint32s, rx_metadata *md) + { + if (payload_len_in_bytes < sizeof(u2_fixed_hdr_t)) // invalid format + return false; + + // FIXME deal with the fact that (p % 4) == 2 + //assert((((uintptr_t) p) % 4) == 0); // must be 4-byte aligned + + u2_fixed_hdr_t *fh = static_cast(p); + + // FIXME unaligned loads! + md->word0 = u2p_word0(fh); + md->timestamp = u2p_timestamp(fh); + + // md->start_of_burst = (md->word0 & XXX) != 0; + // md->end_of_burst = (md->word0 & XXX) != 0; + // md->rx_overrun = (md->word0 & XXX) != 0; + + *items = (uint32_t *)(&fh[1]); + size_t nbytes = payload_len_in_bytes - sizeof(u2_fixed_hdr_t); + assert((nbytes % sizeof(uint32_t)) == 0); + *nitems_in_uint32s = nbytes / sizeof(uint32_t); + + return true; + } + + + usrp2::impl::impl(const std::string &ifc, props *p) + : d_eth_buf(new eth_buffer()), d_pf(0), d_bg_thread(0), d_bg_running(false), + d_rx_decim(0), d_rx_seqno(-1), d_tx_seqno(0), d_next_rid(0), + d_num_rx_frames(0), d_num_rx_missing(0), d_num_rx_overruns(0), d_num_rx_bytes(0), + d_num_enqueued(0), d_enqueued_mutex(), d_bg_pending_cond(&d_enqueued_mutex), + d_channel_rings(NCHANS) + { + if (!d_eth_buf->open(ifc, htons(U2_ETHERTYPE))) + throw std::runtime_error("Unable to register USRP2 protocol"); + + d_pf = pktfilter::make_ethertype_inbound(U2_ETHERTYPE, d_eth_buf->mac()); + if (!d_pf || !d_eth_buf->attach_pktfilter(d_pf)) + throw std::runtime_error("Unable to attach packet filter."); + + d_addr = p->addr; + + if (USRP2_IMPL_DEBUG) + std::cerr << "usrp2 constructor: using USRP2 at " << d_addr << std::endl; + + memset(d_pending_replies, 0, sizeof(d_pending_replies)); + + d_bg_thread = new usrp2_thread(this); + d_bg_thread->start(); + + // set workable defaults for scaling + if (!set_rx_scale_iq(DEFAULT_RX_SCALE, DEFAULT_RX_SCALE)) + std::cerr << "usrp2::ctor set_rx_scale_iq failed\n"; + + if (!set_tx_scale_iq(DEFAULT_TX_SCALE, DEFAULT_TX_SCALE)) + std::cerr << "usrp2::ctor set_tx_scale_iq failed\n"; + } + + usrp2::impl::~impl() + { + stop_bg(); + d_bg_thread = 0; // thread class deletes itself + delete d_pf; + d_eth_buf->close(); + delete d_eth_buf; + + if (USRP2_IMPL_DEBUG) { + std::cerr << std::endl + << "usrp2 destructor: received " << d_num_rx_frames + << " frames, with " << d_num_rx_missing << " lost (" + << (d_num_rx_frames == 0 ? 0 : (int)(100.0*d_num_rx_missing/d_num_rx_frames)) + << "%), totaling " << d_num_rx_bytes + << " bytes" << std::endl; + } + } + + bool + usrp2::impl::parse_mac_addr(const std::string &s, u2_mac_addr_t *p) + { + p->addr[0] = 0x00; // Matt's IAB + p->addr[1] = 0x50; + p->addr[2] = 0xC2; + p->addr[3] = 0x85; + p->addr[4] = 0x30; + p->addr[5] = 0x00; + + int len = s.size(); + + switch (len){ + + case 5: + return sscanf(s.c_str(), "%hhx:%hhx", &p->addr[4], &p->addr[5]) == 2; + + case 17: + return sscanf(s.c_str(), "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &p->addr[0], &p->addr[1], &p->addr[2], + &p->addr[3], &p->addr[4], &p->addr[5]) == 6; + default: + return false; + } + } + + void + usrp2::impl::init_et_hdrs(u2_eth_packet_t *p, const std::string &dst) + { + p->ehdr.ethertype = htons(U2_ETHERTYPE); + parse_mac_addr(dst, &p->ehdr.dst); + memcpy(&p->ehdr.src, d_eth_buf->mac(), 6); + p->thdr.flags = 0; // FIXME transport header values? + p->thdr.seqno = d_tx_seqno++; + p->thdr.ack = 0; + } + + void + usrp2::impl::init_etf_hdrs(u2_eth_packet_t *p, const std::string &dst, + int word0_flags, int chan, uint32_t timestamp) + { + init_et_hdrs(p, dst); + u2p_set_word0(&p->fixed, word0_flags, chan); + u2p_set_timestamp(&p->fixed, timestamp); + + if (chan == CONTROL_CHAN) { // no sequence numbers, back it out + p->thdr.seqno = 0; + d_tx_seqno--; + } + } + + void + usrp2::impl::init_config_rx_v2_cmd(op_config_rx_v2_cmd *cmd) + { + memset(cmd, 0, sizeof(*cmd)); + init_etf_hdrs(&cmd->h, d_addr, 0, CONTROL_CHAN, -1); + cmd->op.opcode = OP_CONFIG_RX_V2; + cmd->op.len = sizeof(cmd->op); + cmd->op.rid = d_next_rid++; + cmd->eop.opcode = OP_EOP; + cmd->eop.len = sizeof(cmd->eop); + } + + void + usrp2::impl::init_config_tx_v2_cmd(op_config_tx_v2_cmd *cmd) + { + memset(cmd, 0, sizeof(*cmd)); + init_etf_hdrs(&cmd->h, d_addr, 0, CONTROL_CHAN, -1); + cmd->op.opcode = OP_CONFIG_TX_V2; + cmd->op.len = sizeof(cmd->op); + cmd->op.rid = d_next_rid++; + cmd->eop.opcode = OP_EOP; + cmd->eop.len = sizeof(cmd->eop); + } + + bool + usrp2::impl::transmit_cmd(void *cmd, size_t len, pending_reply *p, double secs) + { + if (p) + d_pending_replies[p->rid()] = p; + + // Transmit command + if (d_eth_buf->tx_frame(cmd, len) != eth_buffer::EB_OK) { + d_pending_replies[p->rid()] = 0; + return false; + } + + int res = 1; + if (p) + res = p->wait(secs); + + d_pending_replies[p->rid()] = 0; + return res == 1; + } + + // ---------------------------------------------------------------- + // Background loop: received packet demuxing + // ---------------------------------------------------------------- + + void + usrp2::impl::stop_bg() + { + d_bg_running = false; + d_bg_pending_cond.signal(); + + void *dummy_status; + d_bg_thread->join(&dummy_status); + } + + void + usrp2::impl::bg_loop() + { + d_bg_running = true; + while(d_bg_running) { + DEBUG_LOG(":"); + // Receive available frames from ethernet buffer. Handler will + // process control frames, enqueue data packets in channel + // rings, and signal blocked API threads + int res = d_eth_buf->rx_frames(this, 100); // FIXME magic timeout + if (res == eth_buffer::EB_ERROR) + break; + + // Wait for user API thread(s) to process all enqueued packets. + // The channel ring thread that decrements d_num_enqueued to zero + // will signal this thread to continue. + { + omni_mutex_lock l(d_enqueued_mutex); + while(d_num_enqueued > 0 && d_bg_running) + d_bg_pending_cond.wait(); + } + } + d_bg_running = false; + } + + // + // passed to eth_buffer::rx_frames + // + data_handler::result + usrp2::impl::operator()(const void *base, size_t len) + { + u2_eth_samples_t *pkt = (u2_eth_samples_t *)base; + + // FIXME unaligned load! + int chan = u2p_chan(&pkt->hdrs.fixed); + + if (chan == CONTROL_CHAN) { // control packets + DEBUG_LOG("c"); + return handle_control_packet(base, len); + } + else { // data packets + return handle_data_packet(base, len); + } + + // not reached + } + + data_handler::result + usrp2::impl::handle_control_packet(const void *base, size_t len) + { + // point to beginning of payload (subpackets) + unsigned char *p = (unsigned char *)base + sizeof(u2_eth_packet_t); + + // FIXME (p % 4) == 2. Not good. Must watch for unaligned loads. + + // FIXME iterate over payload, handling more than a single subpacket. + + int opcode = p[0]; + unsigned int oplen = p[1]; + unsigned int rid = p[2]; + + pending_reply *rp = d_pending_replies[rid]; + if (rp) { + unsigned int buflen = rp->len(); + if (oplen != buflen) { + std::cerr << "usrp2: mismatched command reply length (expected: " + << buflen << " got: " << oplen << "). " + << "op = " << opcode_to_string(opcode) << std::endl; + } + + // Copy reply into caller's buffer + memcpy(rp->buffer(), p, std::min(oplen, buflen)); + rp->signal(); + d_pending_replies[rid] = 0; + return data_handler::RELEASE; + } + + // TODO: handle unsolicited, USRP2 initiated, or late replies + DEBUG_LOG("l"); + return data_handler::RELEASE; + } + + data_handler::result + usrp2::impl::handle_data_packet(const void *base, size_t len) + { + u2_eth_samples_t *pkt = (u2_eth_samples_t *)base; + d_num_rx_frames++; + d_num_rx_bytes += len; + + /* --- FIXME start of fake transport layer handler --- */ + + if (d_rx_seqno != -1) { + int expected_seqno = (d_rx_seqno + 1) & 0xFF; + int seqno = pkt->hdrs.thdr.seqno; + + if (seqno != expected_seqno) { + ::write(2, "S", 1); // missing sequence number + int missing = seqno - expected_seqno; + if (missing < 0) + missing += 256; + + d_num_rx_overruns++; + d_num_rx_missing += missing; + } + } + + d_rx_seqno = pkt->hdrs.thdr.seqno; + + /* --- end of fake transport layer handler --- */ + + // FIXME unaligned load! + unsigned int chan = u2p_chan(&pkt->hdrs.fixed); + + if (!d_channel_rings[chan]) { + DEBUG_LOG("!"); + return data_handler::RELEASE; // discard packet, no channel handler + } + + // Strip off ethernet header and transport header and enqueue the rest + + size_t offset = offsetof(u2_eth_samples_t, hdrs.fixed); + if (d_channel_rings[chan]->enqueue(&pkt->hdrs.fixed, len-offset)) { + inc_enqueued(); + DEBUG_LOG("+"); + return data_handler::KEEP; // channel ring runner will mark frame done + } + else { + DEBUG_LOG("!"); + return data_handler::RELEASE; // discard, no room in channel ring + } + return data_handler::RELEASE; + } + + + // ---------------------------------------------------------------- + // misc commands + // ---------------------------------------------------------------- + + bool + usrp2::impl::burn_mac_addr(const std::string &new_addr) + { + op_burn_mac_addr_cmd cmd; + op_generic_t reply; + + memset(&cmd, 0, sizeof(cmd)); + init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1); + cmd.op.opcode = OP_BURN_MAC_ADDR; + cmd.op.len = sizeof(cmd.op); + cmd.op.rid = d_next_rid++; + if (!parse_mac_addr(new_addr, &cmd.op.addr)) + return false; + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, 4*DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + return success; + } + + + // ---------------------------------------------------------------- + // Receive + // ---------------------------------------------------------------- + + bool + usrp2::impl::set_rx_gain(double gain) + { + op_config_rx_v2_cmd cmd; + op_config_rx_reply_v2_t reply; + + init_config_rx_v2_cmd(&cmd); + cmd.op.valid = htons(CFGV_GAIN); + cmd.op.gain = htons(u2_double_to_fxpt_gain(gain)); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + return success; + } + + bool + usrp2::impl::set_rx_center_freq(double frequency, tune_result *result) + { + op_config_rx_v2_cmd cmd; + op_config_rx_reply_v2_t reply; + + init_config_rx_v2_cmd(&cmd); + cmd.op.valid = htons(CFGV_FREQ); + u2_fxpt_freq_t fxpt = u2_double_to_fxpt_freq(frequency); + cmd.op.freq_hi = htonl(u2_fxpt_freq_hi(fxpt)); + cmd.op.freq_lo = htonl(u2_fxpt_freq_lo(fxpt)); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + if (result && success) { + result->baseband_freq = + u2_fxpt_freq_to_double( + u2_fxpt_freq_from_hilo(ntohl(reply.baseband_freq_hi), + ntohl(reply.baseband_freq_lo))); + + result->dxc_freq = + u2_fxpt_freq_to_double( + u2_fxpt_freq_from_hilo(ntohl(reply.ddc_freq_hi), + ntohl(reply.ddc_freq_lo))); + + result->residual_freq = + u2_fxpt_freq_to_double( + u2_fxpt_freq_from_hilo(ntohl(reply.residual_freq_hi), + ntohl(reply.residual_freq_lo))); + + result->spectrum_inverted = (bool)(ntohx(reply.inverted) == 1); + } + + return success; + } + + bool + usrp2::impl::set_rx_decim(int decimation_factor) + { + op_config_rx_v2_cmd cmd; + op_config_rx_reply_v2_t reply; + + init_config_rx_v2_cmd(&cmd); + cmd.op.valid = htons(CFGV_INTERP_DECIM); + cmd.op.decim = htonl(decimation_factor); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + return success; + } + + bool + usrp2::impl::set_rx_scale_iq(int scale_i, int scale_q) + { + op_config_rx_v2_cmd cmd; + op_config_rx_reply_v2_t reply; + + init_config_rx_v2_cmd(&cmd); + cmd.op.valid = htons(CFGV_SCALE_IQ); + cmd.op.scale_iq = htonl(((scale_i & 0xffff) << 16) | (scale_q & 0xffff)); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + return success; + } + + bool + usrp2::impl::start_rx_streaming(unsigned int channel, unsigned int items_per_frame) + { + if (channel > MAX_CHAN) { + std::cerr << "usrp2: invalid channel number (" << channel + << ")" << std::endl; + return false; + } + + if (channel > 0) { // until firmware supports multiple streams + std::cerr << "usrp2: channel " << channel + << " not implemented" << std::endl; + return false; + } + + if (d_channel_rings[channel]) { + std::cerr << "usrp2: channel " << channel + << " already streaming" << std::endl; + return false; + } + + d_channel_rings[channel] = ring_sptr(new ring(d_eth_buf->max_frames())); + + if (items_per_frame == 0) + items_per_frame = U2_MAX_SAMPLES; // minimize overhead + + op_start_rx_streaming_cmd cmd; + op_generic_t reply; + + memset(&cmd, 0, sizeof(cmd)); + init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1); + cmd.op.opcode = OP_START_RX_STREAMING; + cmd.op.len = sizeof(cmd.op); + cmd.op.rid = d_next_rid++; + cmd.op.items_per_frame = htonl(items_per_frame); + cmd.eop.opcode = OP_EOP; + cmd.eop.len = sizeof(cmd.eop); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + return success; + } + + bool + usrp2::impl::stop_rx_streaming(unsigned int channel) + { + if (channel > MAX_CHAN) { + std::cerr << "usrp2: invalid channel number (" << channel + << ")" << std::endl; + return false; + } + + if (channel > 0) { // until firmware supports multiple streams + std::cerr << "usrp2: channel " << channel + << " not implemented" << std::endl; + return false; + } + +#if 0 // don't be overzealous. + if (!d_channel_rings[channel]) { + std::cerr << "usrp2: channel " << channel + << " not streaming" << std::endl; + return false; + } +#endif + + op_stop_rx_cmd cmd; + op_generic_t reply; + + memset(&cmd, 0, sizeof(cmd)); + init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1); + cmd.op.opcode = OP_STOP_RX; + cmd.op.len = sizeof(cmd.op); + cmd.op.rid = d_next_rid++; + cmd.eop.opcode = OP_EOP; + cmd.eop.len = sizeof(cmd.eop); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + if (success) + d_channel_rings[channel].reset(); + + return success; + } + + + bool + usrp2::impl::rx_samples(unsigned int channel, rx_sample_handler *handler) + { + if (channel > MAX_CHAN) { + std::cerr << "usrp2: invalid channel (" << channel + << " )" << std::endl; + return false; + } + + if (channel > 0) { + std::cerr << "usrp2: channel " << channel + << " not implemented" << std::endl; + return false; + } + + ring_sptr rp = d_channel_rings[channel]; + if (!rp){ + std::cerr << "usrp2: channel " << channel + << " not receiving" << std::endl; + return false; + } + + // Wait for frames available in channel ring + DEBUG_LOG("W"); + rp->wait_for_not_empty(); + DEBUG_LOG("s"); + + // Iterate through frames and present to user + void *p; + size_t frame_len_in_bytes; + while (rp->dequeue(&p, &frame_len_in_bytes)) { + uint32_t *items; // points to beginning of data items + size_t nitems_in_uint32s; + rx_metadata md; + if (!parse_rx_metadata(p, frame_len_in_bytes, &items, &nitems_in_uint32s, &md)) + return false; + + bool want_more = (*handler)(items, nitems_in_uint32s, &md); + d_eth_buf->release_frame(p); + DEBUG_LOG("-"); + dec_enqueued(); + + if (!want_more) + break; + } + return true; + } + + // ---------------------------------------------------------------- + // Transmit + // ---------------------------------------------------------------- + + bool + usrp2::impl::set_tx_gain(double gain) + { + op_config_tx_v2_cmd cmd; + op_config_tx_reply_v2_t reply; + + init_config_tx_v2_cmd(&cmd); + cmd.op.valid = htons(CFGV_GAIN); + cmd.op.gain = htons(u2_double_to_fxpt_gain(gain)); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + return success; + } + + bool + usrp2::impl::set_tx_center_freq(double frequency, tune_result *result) + { + op_config_tx_v2_cmd cmd; + op_config_tx_reply_v2_t reply; + + init_config_tx_v2_cmd(&cmd); + cmd.op.valid = htons(CFGV_FREQ); + u2_fxpt_freq_t fxpt = u2_double_to_fxpt_freq(frequency); + cmd.op.freq_hi = htonl(u2_fxpt_freq_hi(fxpt)); + cmd.op.freq_lo = htonl(u2_fxpt_freq_lo(fxpt)); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + if (result && success) { + result->baseband_freq = + u2_fxpt_freq_to_double( + u2_fxpt_freq_from_hilo(ntohl(reply.baseband_freq_hi), + ntohl(reply.baseband_freq_lo))); + + result->dxc_freq = + u2_fxpt_freq_to_double( + u2_fxpt_freq_from_hilo(ntohl(reply.duc_freq_hi), + ntohl(reply.duc_freq_lo))); + + result->residual_freq = + u2_fxpt_freq_to_double( + u2_fxpt_freq_from_hilo(ntohl(reply.residual_freq_hi), + ntohl(reply.residual_freq_lo))); + + result->spectrum_inverted = (bool)(ntohx(reply.inverted) == 1); + } + + return success; + } + + bool + usrp2::impl::set_tx_interp(int interpolation_factor) + { + op_config_tx_v2_cmd cmd; + op_config_tx_reply_v2_t reply; + + init_config_tx_v2_cmd(&cmd); + cmd.op.valid = htons(CFGV_INTERP_DECIM); + cmd.op.interp = htonl(interpolation_factor); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + return success; + } + + bool + usrp2::impl::set_tx_scale_iq(int scale_i, int scale_q) + { + op_config_tx_v2_cmd cmd; + op_config_tx_reply_v2_t reply; + + init_config_tx_v2_cmd(&cmd); + cmd.op.valid = htons(CFGV_SCALE_IQ); + cmd.op.scale_iq = htonl(((scale_i & 0xffff) << 16) | (scale_q & 0xffff)); + + pending_reply p(cmd.op.rid, &reply, sizeof(reply)); + if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT)) + return false; + + bool success = (ntohx(reply.ok) == 1); + return success; + } + + bool + usrp2::impl::tx_complex_float(unsigned int channel, + const std::complex *samples, + size_t nsamples, + const tx_metadata *metadata) + { + uint32_t items[nsamples]; + copy_host_complex_float_to_u2_complex_16(nsamples, samples, items); + return tx_raw(channel, items, nsamples, metadata); + } + + bool + usrp2::impl::tx_complex_int16(unsigned int channel, + const std::complex *samples, + size_t nsamples, + const tx_metadata *metadata) + { +#ifdef WORDS_BIGENDIAN + + // Already binary equivalent to 16-bit I/Q on the wire. + // No conversion required. + + assert(sizeof(samples[0]) == sizeof(uint32_t)); + return tx_raw(channel, (const uint32_t *) samples, nsamples, metadata); + +#else + + uint32_t items[nsamples]; + copy_host_complex_16_to_u2_complex_16(nsamples, samples, items); + return tx_raw(channel, items, nsamples, metadata); + +#endif + } + + bool + usrp2::impl::tx_raw(unsigned int channel, + const uint32_t *items, + size_t nitems, + const tx_metadata *metadata) + { + if (nitems == 0) + return true; + + // FIXME there's the possibility that we send fewer than 9 items in a frame. + // That would end up glitching the transmitter, since the ethernet will pad to + // 64-bytes total (9 items). We really need some part of the stack to + // carry the real length (thdr?). + + // fragment as necessary then fire away + + size_t nframes = (nitems + U2_MAX_SAMPLES - 1) / U2_MAX_SAMPLES; + size_t last_frame = nframes - 1; + u2_eth_packet_t hdrs; + + size_t n = 0; + for (size_t fn = 0; fn < nframes; fn++){ + uint32_t timestamp = 0; + uint32_t flags = 0; + + if (fn == 0){ + timestamp = metadata->timestamp; + if (metadata->send_now) + flags |= U2P_TX_IMMEDIATE; + if (metadata->start_of_burst) + flags |= U2P_TX_START_OF_BURST; + } + if (fn > 0){ + flags |= U2P_TX_IMMEDIATE; + } + if (fn == last_frame){ + if (metadata->end_of_burst) + flags |= U2P_TX_END_OF_BURST; + } + + init_etf_hdrs(&hdrs, d_addr, flags, channel, timestamp); + + size_t i = std::min((size_t) U2_MAX_SAMPLES, nitems - n); + + eth_iovec iov[2]; + iov[0].iov_base = &hdrs; + iov[0].iov_len = sizeof(hdrs); + iov[1].iov_base = const_cast(&items[n]); + iov[1].iov_len = i * sizeof(uint32_t); + + if (d_eth_buf->tx_framev(iov, 2) != eth_buffer::EB_OK){ + return false; + } + + n += i; + } + + return true; + } + + +} // namespace usrp2 diff --git a/usrp2/host/lib/usrp2_impl.h b/usrp2/host/lib/usrp2_impl.h new file mode 100644 index 00000000..37109c9e --- /dev/null +++ b/usrp2/host/lib/usrp2_impl.h @@ -0,0 +1,133 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef INCLUDED_USRP2_IMPL_H +#define INCLUDED_USRP2_IMPL_H + +#include +#include +#include +#include +#include "control.h" +#include "ring.h" +#include + +namespace usrp2 { + + class eth_buffer; + class pktfilter; + class usrp2_thread; + class usrp2_tune_result; + class pending_reply; + class ring; + + class usrp2::impl : private data_handler + { + static const size_t NRIDS = 256; + static const size_t NCHANS = 32; + + eth_buffer *d_eth_buf; + pktfilter *d_pf; + std::string d_addr; // FIXME: use u2_mac_addr_t instead + usrp2_thread *d_bg_thread; + volatile bool d_bg_running; // TODO: multistate if needed + + int d_rx_decim; + int d_rx_seqno; + int d_tx_seqno; + int d_next_rid; + unsigned int d_num_rx_frames; + unsigned int d_num_rx_missing; + unsigned int d_num_rx_overruns; + unsigned int d_num_rx_bytes; + + unsigned int d_num_enqueued; + omni_mutex d_enqueued_mutex; + omni_condition d_bg_pending_cond; + + // all pending_replies are stack allocated, thus no possibility of leaking these + pending_reply *d_pending_replies[NRIDS]; // indexed by 8-bit reply id + + std::vector d_channel_rings; // indexed by 5-bit channel number + + void inc_enqueued() { + omni_mutex_lock l(d_enqueued_mutex); + d_num_enqueued++; + } + + void dec_enqueued() { + omni_mutex_lock l(d_enqueued_mutex); + if (--d_num_enqueued == 0) + d_bg_pending_cond.signal(); + } + + static bool parse_mac_addr(const std::string &s, u2_mac_addr_t *p); + void init_et_hdrs(u2_eth_packet_t *p, const std::string &dst); + void init_etf_hdrs(u2_eth_packet_t *p, const std::string &dst, + int word0_flags, int chan, uint32_t timestamp); + void stop_bg(); + void init_config_rx_v2_cmd(op_config_rx_v2_cmd *cmd); + void init_config_tx_v2_cmd(op_config_tx_v2_cmd *cmd); + bool transmit_cmd(void *cmd, size_t len, pending_reply *p, double secs=0.0); + virtual data_handler::result operator()(const void *base, size_t len); + data_handler::result handle_control_packet(const void *base, size_t len); + data_handler::result handle_data_packet(const void *base, size_t len); + + public: + impl(const std::string &ifc, props *p); + ~impl(); + + void bg_loop(); + + std::string mac_addr() const { return d_addr; } // FIXME: convert from u2_mac_addr_t + bool burn_mac_addr(const std::string &new_addr); + + bool set_rx_gain(double gain); + bool set_rx_center_freq(double frequency, tune_result *result); + bool set_rx_decim(int decimation_factor); + bool set_rx_scale_iq(int scale_i, int scale_q); + bool start_rx_streaming(unsigned int channel, unsigned int items_per_frame); + bool rx_samples(unsigned int channel, rx_sample_handler *handler); + bool stop_rx_streaming(unsigned int channel); + unsigned int rx_overruns() const { return d_num_rx_overruns; } + unsigned int rx_missing() const { return d_num_rx_missing; } + + bool set_tx_gain(double gain); + bool set_tx_center_freq(double frequency, tune_result *result); + bool set_tx_interp(int interpolation_factor); + bool set_tx_scale_iq(int scale_i, int scale_q); + + bool tx_complex_float(unsigned int channel, + const std::complex *samples, + size_t nsamples, + const tx_metadata *metadata); + + bool tx_complex_int16(unsigned int channel, + const std::complex *samples, + size_t nsamples, + const tx_metadata *metadata); + + bool tx_raw(unsigned int channel, + const uint32_t *items, + size_t nitems, + const tx_metadata *metadata); + }; + +} // namespace usrp2 + +#endif /* INCLUDED_USRP2_IMPL_H */ diff --git a/usrp2/host/lib/usrp2_socket_opener.cc b/usrp2/host/lib/usrp2_socket_opener.cc new file mode 100644 index 00000000..27d3935e --- /dev/null +++ b/usrp2/host/lib/usrp2_socket_opener.cc @@ -0,0 +1,143 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/*! + * setuid root program that opens a socket using (PF_PACKET, SOCK_RAW, + * htons(0xBEEF)), and sends the resulting file descriptor by way of + * of the file descriptor specified as the first command line argument. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef HAVE_ARPA_INET_H +#include +#elif defined(HAVE_NETINET_IN_H) +#include +#endif + + +ssize_t +write_fd(int fd, const void *ptr, size_t nbytes, int sendfd) +{ + struct msghdr msg; + struct iovec iov[1]; + +#ifdef HAVE_STRUCT_MSGHDR_MSG_CONTROL + union { + struct cmsghdr cm; + char control[CMSG_SPACE(sizeof(int))]; + } control_un; + struct cmsghdr *cmptr; + + msg.msg_control = control_un.control; + msg.msg_controllen = sizeof(control_un.control); + + cmptr = CMSG_FIRSTHDR(&msg); + cmptr->cmsg_len = CMSG_LEN(sizeof(int)); + cmptr->cmsg_level = SOL_SOCKET; + cmptr->cmsg_type = SCM_RIGHTS; + *((int *) CMSG_DATA(cmptr)) = sendfd; +#else + msg.msg_accrights = (char *) &sendfd; + msg.msg_accrightslen = sizeof(int); +#endif + + msg.msg_name = NULL; + msg.msg_namelen = 0; + + iov[0].iov_base = const_cast(ptr); + iov[0].iov_len = nbytes; + msg.msg_iov = iov; + msg.msg_iovlen = 1; + + return sendmsg(fd, &msg, 0); +} + +bool +reset_eids() +{ + if (setgid(getgid()) < 0){ + perror("setguid"); + return false; + } + + if (setuid(getuid()) < 0){ + perror("setuid"); + return false; + } + + return true; +} + + +static void +usage() +{ + fprintf(stderr, "usage: usrp2_socket_opener file-descriptor\n"); + exit(1); +} + +int +main(int argc, char **argv) +{ + if (argc != 2) + usage(); + + char *endptr; + int unix_domain_fd = strtol(argv[1], &endptr, 0); + if (*endptr != 0) + usage(); + + // FIXME get client credentials from unix_domain_fd using SCM_CREDENTIALS + + // open the raw socket + int socket_fd = socket(PF_PACKET, SOCK_RAW, htons(0xBEEF)); + if (socket_fd == -1){ + perror("socket(PF_PACKET, SOCK_RAW, htons(0xBEEF))"); + // printf("errno = %d\n", errno); + if (errno == EACCES || errno == ESPIPE){ + fprintf(stderr, "usrp2_socket_opener must be setuid root to open the socket using SOCK_RAW.\n"); + fprintf(stderr, "Running as root, please execute: \n"); + fprintf(stderr, " # chown root:usrp usrp2_socket_opener\n"); + fprintf(stderr, " # chmod 04750 usrp2_socket_opener\n"); + } + exit(2); + } + + // drop privs + if (!reset_eids()){ + fprintf(stderr, "Can't drop root permissions\n"); + exit(3); + } + + if (write_fd(unix_domain_fd, "", 1, socket_fd) != 1){ + perror("write_fd"); + exit(4); + } + + return 0; +} diff --git a/usrp2/host/lib/usrp2_thread.cc b/usrp2/host/lib/usrp2_thread.cc new file mode 100644 index 00000000..9e4e6dbe --- /dev/null +++ b/usrp2/host/lib/usrp2_thread.cc @@ -0,0 +1,63 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include "usrp2_thread.h" +#include "usrp2_impl.h" +#include +#include + +#define USRP2_THREAD_DEBUG 1 + +namespace usrp2 { + + usrp2_thread::usrp2_thread(usrp2::impl *u2) : + omni_thread(NULL, PRIORITY_HIGH), + d_u2(u2) + { + } + + usrp2_thread::~usrp2_thread() + { + // we don't own this, just forget it + d_u2 = 0; + } + + void + usrp2_thread::start() + { + start_undetached(); + } + + void * + usrp2_thread::run_undetached(void *arg) + { + if (gruel::enable_realtime_scheduling() != gruel::RT_OK) + std::cerr << "usrp2: failed to enable realtime scheduling" << std::endl; + + // This is the first code to run in the new thread context. + d_u2->bg_loop(); + + return 0; + } + +} // namespace usrp2 + diff --git a/usrp2/host/lib/usrp2_thread.h b/usrp2/host/lib/usrp2_thread.h new file mode 100644 index 00000000..c7f9e1aa --- /dev/null +++ b/usrp2/host/lib/usrp2_thread.h @@ -0,0 +1,47 @@ +/* -*- c++ -*- */ +/* + * Copyright 2008 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. + */ + +#ifndef INCLUDED_USRP2_THREAD_H +#define INCLUDED_USRP2_THREAD_H + +#include +#include + +namespace usrp2 { + + class usrp2_thread : public omni_thread + { + private: + usrp2::impl *d_u2; + + public: + usrp2_thread(usrp2::impl *u2); + ~usrp2_thread(); + + void start(); + + virtual void *run_undetached(void *arg); + }; + +} // namespace usrp2 + +#endif /* INCLUDED_USRP2_THREAD_H */ diff --git a/usrp2/host/usrp2.pc.in b/usrp2/host/usrp2.pc.in new file mode 100644 index 00000000..eaef5f41 --- /dev/null +++ b/usrp2/host/usrp2.pc.in @@ -0,0 +1,11 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: usrp2 +Description: Universal Software Radio Peripheral 2 +Requires: gnuradio-omnithread gruel +Version: @VERSION@ +Libs: -L${libdir} -lusrp2 +Cflags: -I${includedir} @DEFINES@ -- 2.30.2

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diff --git a/usrp2/fpga/opencores/spi_boot/doc/src/CVS/Repository b/usrp2/fpga/opencores/spi_boot/doc/src/CVS/Repository new file mode 100644 index 00000000..5f8aafef --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/doc/src/CVS/Repository @@ -0,0 +1 @@ +spi_boot/doc/src diff --git a/usrp2/fpga/opencores/spi_boot/doc/src/CVS/Root b/usrp2/fpga/opencores/spi_boot/doc/src/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/doc/src/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/doc/src/CVS/Template b/usrp2/fpga/opencores/spi_boot/doc/src/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/doc/src/architecture.eps b/usrp2/fpga/opencores/spi_boot/doc/src/architecture.eps new file mode 100644 index 00000000..3e70efdb --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/doc/src/architecture.eps @@ -0,0 +1,512 @@ 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3150 l + cp gs col0 s gr +/Courier-iso ff 150.00 scf sf +5310 3000 m +gs 1 -1 sc (Image 0) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +n 3870 2430 m 6750 2430 l 6750 2790 l 3870 2790 l + cp gs col0 s gr +/Courier-iso ff 150.00 scf sf +5310 2640 m +gs 1 -1 sc (Image 1) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +n 3870 2070 m 6750 2070 l 6750 2430 l 3870 2430 l + cp gs col0 s gr +/Courier-iso ff 150.00 scf sf +5310 2280 m +gs 1 -1 sc (...) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +n 3870 1710 m 6750 1710 l 6750 2070 l 3870 2070 l + cp gs col0 s gr +/Courier-iso ff 150.00 scf sf +5310 1920 m +gs 1 -1 sc (Image i-1) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +30.000 slw +n 3870 1710 m 6750 1710 l 6750 3150 l 3870 3150 l + cp gs col0 s gr +% Polyline +2 slj +7.500 slw +n 3780 1710 m 3778 1711 l 3775 1712 l 3769 1714 l 3761 1718 l 3753 1723 l + 3745 1729 l 3737 1737 l 3730 1746 l 3725 1757 l 3720 1770 l + 3717 1784 l 3714 1802 l 3713 1823 l 3712 1839 l 3711 1857 l + 3711 1876 l 3710 1897 l 3710 1919 l 3710 1943 l 3710 1968 l + 3710 1995 l 3710 2021 l 3709 2049 l 3709 2076 l 3708 2103 l + 3707 2129 l 3706 2155 l 3704 2179 l 3702 2202 l 3700 2224 l + 3697 2244 l 3694 2263 l 3690 2280 l 3682 2306 l 3673 2328 l + 3662 2348 l 3651 2366 l 3639 2380 l 3627 2393 l 3615 2403 l + 3605 2411 l 3597 2418 l 3590 2422 l 3586 2426 l 3585 2430 l + 3586 2434 l 3590 2438 l 3597 2442 l 3605 2449 l 3615 2457 l + 3627 2467 l 3639 2480 l 3651 2494 l 3662 2512 l 3673 2532 l + 3682 2554 l 3690 2580 l 3694 2597 l 3697 2616 l 3700 2636 l + 3702 2658 l 3704 2681 l 3706 2705 l 3707 2731 l 3708 2757 l + 3709 2784 l 3709 2811 l 3710 2839 l 3710 2865 l 3710 2892 l + 3710 2917 l 3710 2941 l 3710 2963 l 3711 2984 l 3711 3003 l + 3712 3021 l 3713 3038 l 3714 3058 l 3717 3076 l 3720 3090 l + 3725 3103 l 3730 3114 l 3737 3123 l 3745 3131 l 3753 3137 l + 3761 3142 l 3769 3146 l 3775 3148 l 3778 3149 l + 3780 3150 l gs col0 s gr +/Courier-iso ff 150.00 scf sf +3510 2475 m +gs 1 -1 sc (Set s-1) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 3060 m +gs 1 -1 sc (\(\(p-1\)*m\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 3105 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 2700 m +gs 1 -1 sc (\(\(p-1\)*m+1\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 2745 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 2340 m +gs 1 -1 sc (\(\(p-1\)*m+2\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 2385 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 1980 m +gs 1 -1 sc (\(\(p-1\)*m+m-1\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 2025 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 3690 m +gs 1 -1 sc (\(2*m\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 3735 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 4050 m +gs 1 -1 sc (\(1*m+m-1\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 4095 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 4410 m +gs 1 -1 sc (\(1*m+2\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 4455 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 4770 m +gs 1 -1 sc (\(1*m+1\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 4815 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 5130 m +gs 1 -1 sc (\(1*m\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 5175 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 6210 m +gs 1 -1 sc (1*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 6255 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 5850 m +gs 1 -1 sc (2*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 5895 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +/Courier-iso ff 120.00 scf sf +6930 5490 m +gs 1 -1 sc (\(m-1\)*bpi) col0 sh gr +/Courier-iso ff 150.00 scf sf +6930 5535 m +gs 1 -1 sc (2) dup sw pop neg 0 rm col0 sh gr +% Polyline +0 slj +n 3870 6300 m 6750 6300 l 6750 6660 l 3870 6660 l + cp gs col0 s gr +/Courier-iso ff 150.00 scf sf +5310 6510 m +gs 1 -1 sc (Image 0) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +n 3870 5940 m 6750 5940 l 6750 6300 l 3870 6300 l + cp gs col0 s gr +/Courier-iso ff 150.00 scf sf +5310 6150 m +gs 1 -1 sc (Image 1) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +n 3870 5580 m 6750 5580 l 6750 5940 l 3870 5940 l + cp gs col0 s gr +/Courier-iso ff 150.00 scf sf +5310 5790 m +gs 1 -1 sc (...) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +n 3870 5220 m 6750 5220 l 6750 5580 l 3870 5580 l + cp gs col0 s gr +/Courier-iso ff 150.00 scf sf +5310 5430 m +gs 1 -1 sc (Image i-1) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +30.000 slw +n 3870 5220 m 6750 5220 l 6750 6660 l 3870 6660 l + cp gs col0 s gr +% Polyline +2 slj +7.500 slw +n 3780 5220 m 3778 5221 l 3775 5222 l 3769 5224 l 3761 5228 l 3753 5233 l + 3745 5239 l 3737 5247 l 3730 5256 l 3725 5267 l 3720 5280 l + 3717 5294 l 3714 5312 l 3713 5333 l 3712 5349 l 3711 5367 l + 3711 5386 l 3710 5407 l 3710 5429 l 3710 5453 l 3710 5478 l + 3710 5505 l 3710 5531 l 3709 5559 l 3709 5586 l 3708 5613 l + 3707 5639 l 3706 5665 l 3704 5689 l 3702 5712 l 3700 5734 l + 3697 5754 l 3694 5773 l 3690 5790 l 3682 5816 l 3673 5838 l + 3662 5858 l 3651 5876 l 3639 5890 l 3627 5903 l 3615 5913 l + 3605 5921 l 3597 5928 l 3590 5932 l 3586 5936 l 3585 5940 l + 3586 5944 l 3590 5948 l 3597 5952 l 3605 5959 l 3615 5967 l + 3627 5977 l 3639 5990 l 3651 6004 l 3662 6022 l 3673 6042 l + 3682 6064 l 3690 6090 l 3694 6107 l 3697 6126 l 3700 6146 l + 3702 6168 l 3704 6191 l 3706 6215 l 3707 6241 l 3708 6267 l + 3709 6294 l 3709 6321 l 3710 6349 l 3710 6375 l 3710 6402 l + 3710 6427 l 3710 6451 l 3710 6473 l 3711 6494 l 3711 6513 l + 3712 6531 l 3713 6548 l 3714 6568 l 3717 6586 l 3720 6600 l + 3725 6613 l 3730 6624 l 3737 6633 l 3745 6641 l 3753 6647 l + 3761 6652 l 3769 6656 l 3775 6658 l 3778 6659 l + 3780 6660 l gs col0 s gr +/Courier-iso ff 150.00 scf sf +3510 5985 m +gs 1 -1 sc (Set 0) dup sw pop neg 0 rm col0 sh gr +% Polyline +0 slj +30.000 slw +n 3870 3780 m 6750 3780 l 6750 3150 l 3870 3150 l + cp gs col0 s gr +/Courier-iso ff 150.00 scf sf +5310 3480 m +gs 1 -1 sc (...) dup sw pop 2 div neg 0 rm col0 sh gr +% Polyline +7.500 slw +n 6750 2790 m + 6840 2790 l gs col0 s gr +% Polyline +n 6750 2430 m + 6840 2430 l gs col0 s gr +% Polyline +n 6750 2070 m + 6840 2070 l gs col0 s gr +% Polyline +30.000 slw +n 6750 3780 m + 6930 3780 l gs col0 s gr +% Polyline +n 6750 5220 m + 6930 5220 l gs col0 s gr +% Polyline +7.500 slw +n 6750 4140 m + 6840 4140 l gs col0 s gr +% Polyline +n 6750 4500 m + 6840 4500 l gs col0 s gr +% Polyline +n 6750 4860 m + 6840 4860 l gs col0 s gr +% Polyline +30.000 slw +n 6750 6660 m + 6930 6660 l gs col0 s gr +% Polyline +7.500 slw +n 6750 5580 m + 6840 5580 l gs col0 s gr +% Polyline +n 6750 5940 m + 6840 5940 l gs col0 s gr +% Polyline +n 6750 6300 m + 6840 6300 l gs col0 s gr +% Polyline +30.000 slw +n 6750 3150 m + 6930 3150 l gs col0 s gr +/Courier-iso ff 150.00 scf sf +6840 6615 m +gs 1 -1 sc (0) col0 sh gr +$F2psEnd +rs diff --git a/usrp2/fpga/opencores/spi_boot/doc/src/memory_organization.fig b/usrp2/fpga/opencores/spi_boot/doc/src/memory_organization.fig new file mode 100644 index 00000000..e9413110 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/doc/src/memory_organization.fig @@ -0,0 +1,176 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +6 3060 3735 6795 5265 +6 3870 4860 6750 5220 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 4860 6750 4860 6750 5220 3870 5220 3870 4860 +4 1 0 50 0 12 10 0.0000 4 120 630 5310 5070 Image 0\001 +-6 +6 3870 4500 6750 4860 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 4500 6750 4500 6750 4860 3870 4860 3870 4500 +4 1 0 50 0 12 10 0.0000 4 135 630 5310 4710 Image 1\001 +-6 +6 3870 4140 6750 4500 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 4140 6750 4140 6750 4500 3870 4500 3870 4140 +4 1 0 50 0 12 10 0.0000 4 30 270 5310 4350 ...\001 +-6 +6 3870 3780 6750 4140 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 3780 6750 3780 6750 4140 3870 4140 3870 3780 +4 1 0 50 0 12 10 0.0000 4 135 810 5310 3990 Image i-1\001 +-6 +2 2 0 3 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 3780 6750 3780 6750 5220 3870 5220 3870 3780 +3 0 0 1 0 7 50 0 -1 0.000 0 0 0 7 + 3780 3780 3690 3780 3735 4455 3510 4500 3735 4545 3690 5220 + 3780 5220 + 0.000 1.000 1.000 1.000 1.000 1.000 0.000 +4 2 0 50 0 12 10 0.0000 4 120 450 3510 4545 Set 1\001 +-6 +6 2880 1665 6795 3195 +6 3870 2790 6750 3150 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 2790 6750 2790 6750 3150 3870 3150 3870 2790 +4 1 0 50 0 12 10 0.0000 4 120 630 5310 3000 Image 0\001 +-6 +6 3870 2430 6750 2790 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 2430 6750 2430 6750 2790 3870 2790 3870 2430 +4 1 0 50 0 12 10 0.0000 4 135 630 5310 2640 Image 1\001 +-6 +6 3870 2070 6750 2430 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 2070 6750 2070 6750 2430 3870 2430 3870 2070 +4 1 0 50 0 12 10 0.0000 4 30 270 5310 2280 ...\001 +-6 +6 3870 1710 6750 2070 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 1710 6750 1710 6750 2070 3870 2070 3870 1710 +4 1 0 50 0 12 10 0.0000 4 135 810 5310 1920 Image i-1\001 +-6 +2 2 0 3 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 1710 6750 1710 6750 3150 3870 3150 3870 1710 +3 0 0 1 0 7 50 0 -1 0.000 0 0 0 7 + 3780 1710 3690 1710 3735 2385 3510 2430 3735 2475 3690 3150 + 3780 3150 + 0.000 1.000 1.000 1.000 1.000 1.000 0.000 +4 2 0 50 0 12 10 0.0000 4 120 630 3510 2475 Set s-1\001 +-6 +6 6840 2970 7920 3105 +4 0 0 50 0 12 8 0.0000 4 90 975 6930 3060 ((p-1)*m)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 3105 2\001 +-6 +6 6840 2610 8055 2745 +4 0 0 50 0 12 8 0.0000 4 90 1125 6930 2700 ((p-1)*m+1)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 2745 2\001 +-6 +6 6840 2250 8055 2385 +4 0 0 50 0 12 8 0.0000 4 90 1125 6930 2340 ((p-1)*m+2)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 2385 2\001 +-6 +6 6840 1890 8235 2025 +4 0 0 50 0 12 8 0.0000 4 90 1275 6930 1980 ((p-1)*m+m-1)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 2025 2\001 +-6 +6 6840 3600 7605 3735 +4 0 0 50 0 12 8 0.0000 4 90 675 6930 3690 (2*m)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 3735 2\001 +-6 +6 6840 3960 7920 4095 +4 0 0 50 0 12 8 0.0000 4 90 975 6930 4050 (1*m+m-1)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 4095 2\001 +-6 +6 6840 4320 7785 4455 +4 0 0 50 0 12 8 0.0000 4 90 825 6930 4410 (1*m+2)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 4455 2\001 +-6 +6 6840 4680 7785 4815 +4 0 0 50 0 12 8 0.0000 4 90 825 6930 4770 (1*m+1)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 4815 2\001 +-6 +6 6840 5040 7605 5175 +4 0 0 50 0 12 8 0.0000 4 90 675 6930 5130 (1*m)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 5175 2\001 +-6 +6 6840 6120 7335 6255 +4 0 0 50 0 12 8 0.0000 4 90 375 6930 6210 1*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 6255 2\001 +-6 +6 6840 5760 7335 5895 +4 0 0 50 0 12 8 0.0000 4 90 375 6930 5850 2*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 5895 2\001 +-6 +6 6840 5400 7605 5535 +4 0 0 50 0 12 8 0.0000 4 90 675 6930 5490 (m-1)*bpi\001 +4 2 0 50 0 12 10 0.0000 4 90 90 6930 5535 2\001 +-6 +6 3060 5175 6795 6705 +6 3870 6300 6750 6660 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 6300 6750 6300 6750 6660 3870 6660 3870 6300 +4 1 0 50 0 12 10 0.0000 4 120 630 5310 6510 Image 0\001 +-6 +6 3870 5940 6750 6300 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 5940 6750 5940 6750 6300 3870 6300 3870 5940 +4 1 0 50 0 12 10 0.0000 4 135 630 5310 6150 Image 1\001 +-6 +6 3870 5580 6750 5940 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 5580 6750 5580 6750 5940 3870 5940 3870 5580 +4 1 0 50 0 12 10 0.0000 4 30 270 5310 5790 ...\001 +-6 +6 3870 5220 6750 5580 +2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 5220 6750 5220 6750 5580 3870 5580 3870 5220 +4 1 0 50 0 12 10 0.0000 4 135 810 5310 5430 Image i-1\001 +-6 +2 2 0 3 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 5220 6750 5220 6750 6660 3870 6660 3870 5220 +3 0 0 1 0 7 50 0 -1 0.000 0 0 0 7 + 3780 5220 3690 5220 3735 5895 3510 5940 3735 5985 3690 6660 + 3780 6660 + 0.000 1.000 1.000 1.000 1.000 1.000 0.000 +4 2 0 50 0 12 10 0.0000 4 105 450 3510 5985 Set 0\001 +-6 +6 3825 3105 6795 3825 +2 2 0 3 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3870 3780 6750 3780 6750 3150 3870 3150 3870 3780 +4 1 0 50 0 12 10 0.0000 4 30 270 5310 3480 ...\001 +-6 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2 + 6750 2790 6840 2790 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2 + 6750 2430 6840 2430 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2 + 6750 2070 6840 2070 +2 1 0 3 0 7 50 0 -1 0.000 0 0 -1 0 0 2 + 6750 3780 6930 3780 +2 1 0 3 0 7 50 0 -1 0.000 0 0 -1 0 0 2 + 6750 5220 6930 5220 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2 + 6750 4140 6840 4140 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2 + 6750 4500 6840 4500 +2 1 0 1 0 7 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l 3802 6644 l 3780 6734 l 3757 6644 l cp +eoclip +n 3780 6390 m + 3780 6750 l gs col0 s gr gr + +% arrowhead +n 3757 6644 m 3780 6734 l 3802 6644 l 3757 6644 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3757 7755 m 3802 7755 l 3802 7634 l 3780 7724 l 3757 7634 l cp +eoclip +n 3780 7380 m + 3780 7740 l gs col0 s gr gr + +% arrowhead +n 3757 7634 m 3780 7724 l 3802 7634 l 3757 7634 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3765 5512 m 3765 5557 l 3886 5557 l 3796 5535 l 3886 5512 l cp +eoclip +n 4545 7020 m 5130 7020 l 5130 5535 l + 3780 5535 l gs col0 s gr gr + +% arrowhead +n 3886 5512 m 3796 5535 l 3886 5557 l 3886 5512 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3757 2805 m 3802 2805 l 3802 2684 l 3780 2774 l 3757 2684 l cp +eoclip +n 3780 8370 m 3780 8640 l 2520 8640 l 2520 2520 l 3780 2520 l + 3780 2790 l gs col0 s gr gr + +% arrowhead +n 3757 2684 m 3780 2774 l 3802 2684 l 3757 2684 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3765 3532 m 3765 3577 l 3886 3577 l 3796 3555 l 3886 3532 l cp +eoclip +n 4680 3555 m + 3780 3555 l gs col0 s gr gr + +% arrowhead +n 3886 3532 m 3796 3555 l 3886 3577 l 3886 3532 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6637 4785 m 6682 4785 l 6682 4664 l 6660 4754 l 6637 4664 l cp +eoclip +n 4500 4050 m 6660 4050 l + 6660 4770 l gs col0 s gr gr + +% arrowhead +n 6637 4664 m 6660 4754 l 6682 4664 l 6637 4664 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6645 4027 m 6645 4072 l 6766 4072 l 6676 4050 l 6766 4027 l cp +eoclip +n 7380 6030 m 7920 6030 l 7920 4050 l + 6660 4050 l gs col0 s gr gr + +% arrowhead +n 6766 4027 m 6676 4050 l 6766 4072 l 6766 4027 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6645 6502 m 6645 6547 l 6766 6547 l 6676 6525 l 6766 6502 l cp +eoclip +n 7380 8010 m 7920 8010 l 7920 6525 l + 6660 6525 l gs col0 s gr gr + +% arrowhead +n 6766 6502 m 6676 6525 l 6766 6547 l 6766 6502 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +3765 4522 m 3765 4567 l 3886 4567 l 3796 4545 l 3886 4522 l cp +eoclip +n 6660 8370 m 6660 8640 l 5310 8640 l 5310 4545 l + 3780 4545 l gs col0 s gr gr + +% arrowhead +n 3886 4522 m 3796 4545 l 3886 4567 l 3886 4522 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6637 5775 m 6682 5775 l 6682 5654 l 6660 5744 l 6637 5654 l cp +eoclip +n 6660 5400 m + 6660 5760 l gs col0 s gr gr + +% arrowhead +n 6637 5654 m 6660 5744 l 6682 5654 l 6637 5654 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6637 6765 m 6682 6765 l 6682 6644 l 6660 6734 l 6637 6644 l cp +eoclip +n 6660 6390 m + 6660 6750 l gs col0 s gr gr + +% arrowhead +n 6637 6644 m 6660 6734 l 6682 6644 l 6637 6644 l cp gs 0.00 setgray ef gr col0 s +% Polyline +gs clippath +6637 7755 m 6682 7755 l 6682 7634 l 6660 7724 l 6637 7634 l cp +eoclip +n 6660 7380 m + 6660 7740 l gs col0 s gr gr + +% arrowhead +n 6637 7634 m 6660 7724 l 6682 7634 l 6637 7634 l cp gs 0.00 setgray ef gr col0 s +/Helvetica ff 150.00 scf sf +3870 7560 m +gs 1 -1 sc (Yes) col0 sh gr +/Helvetica ff 150.00 scf sf +4590 6930 m +gs 1 -1 sc (No) col0 sh gr +/Helvetica ff 150.00 scf sf +4770 3600 m +gs 1 -1 sc (start) col0 sh gr +/Helvetica ff 150.00 scf sf +3690 4590 m +gs 1 -1 sc (No) dup sw pop neg 0 rm col0 sh gr +/Helvetica ff 150.00 scf sf +4590 3960 m +gs 1 -1 sc (Yes) col0 sh gr +/Helvetica ff 150.00 scf sf +7470 5940 m +gs 1 -1 sc (No) col0 sh gr +/Helvetica ff 150.00 scf sf +6570 6570 m +gs 1 -1 sc (Yes) dup sw pop neg 0 rm col0 sh gr +/Helvetica ff 150.00 scf sf +7470 7920 m +gs 1 -1 sc (No) col0 sh gr +/Helvetica ff 150.00 scf sf +6750 8550 m +gs 1 -1 sc (Yes) col0 sh gr +$F2psEnd +rs diff --git a/usrp2/fpga/opencores/spi_boot/doc/src/transfer.fig b/usrp2/fpga/opencores/spi_boot/doc/src/transfer.fig new file mode 100644 index 00000000..3d172405 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/doc/src/transfer.fig @@ -0,0 +1,119 @@ +#FIG 3.2 +Landscape +Center +Metric +A4 +65.00 +Single +-2 +1200 2 +6 2700 4725 4860 5445 +6 2970 4860 4590 5265 +4 1 0 50 0 16 10 0.0000 4 120 435 3780 5017 CMD18\001 +4 1 0 50 0 16 10 0.0000 4 120 1560 3780 5242 READ_MULTIPLE_BLOCKS\001 +-6 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 2745 4770 4815 4770 4815 5400 2745 5400 2745 4770 +-6 +6 3015 2745 4545 3465 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3060 2790 4500 2790 4500 3420 3060 3420 3060 2790 +4 1 0 50 0 16 10 0.0000 4 120 705 3780 3150 Wait for start\001 +-6 +6 3015 3735 4545 4455 +2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3780 3780 4500 4050 3780 4410 3060 4050 3780 3780 +4 1 0 50 0 16 10 0.0000 4 135 615 3780 4132 mode = 1?\001 +-6 +6 3015 5715 4545 6435 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3060 5760 4500 5760 4500 6390 3060 6390 3060 5760 +4 1 0 50 0 16 10 0.0000 4 120 645 3780 6120 Read block\001 +-6 +6 3015 6705 4545 7425 +2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 3780 6750 4500 7020 3780 7380 3060 7020 3780 6750 +4 1 0 50 0 16 10 0.0000 4 120 675 3780 7102 ???_done?\001 +-6 +6 2835 7695 4725 8415 +6 3105 7830 4455 8235 +4 1 0 50 0 16 10 0.0000 4 120 435 3780 7987 CMD12\001 +4 1 0 50 0 16 10 0.0000 4 120 1290 3780 8212 STOP_TRANSMISSION\001 +-6 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 2880 7740 4680 7740 4680 8370 2880 8370 2880 7740 +-6 +6 5895 4725 7425 5445 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 5940 4770 7380 4770 7380 5400 5940 5400 5940 4770 +4 1 0 50 0 16 10 0.0000 4 135 960 6660 5130 Activate config_n\001 +-6 +6 5895 5715 7425 6435 +2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 6660 5760 7380 6030 6660 6390 5940 6030 6660 5760 +4 1 0 50 0 16 10 0.0000 4 135 855 6660 6112 cfg_init_n low?\001 +-6 +6 5895 6705 7425 7425 +2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 5940 6750 7380 6750 7380 7380 5940 7380 5940 6750 +4 1 0 50 0 16 10 0.0000 4 135 1125 6660 7110 Deactivate config_n\001 +-6 +6 5895 7695 7425 8415 +2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5 + 6660 7740 7380 8010 6660 8370 5940 8010 6660 7740 +4 1 0 50 0 16 10 0.0000 4 135 915 6660 8092 cfg_init_n high?\001 +-6 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 3420 3780 3780 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 4410 3780 4770 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 5400 3780 5760 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 6390 3780 6750 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 3780 7380 3780 7740 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 + 1 1 1.00 45.00 90.00 + 4545 7020 5130 7020 5130 5535 3780 5535 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 6 + 1 1 1.00 45.00 90.00 + 3780 8370 3780 8640 2520 8640 2520 2520 3780 2520 3780 2790 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 4680 3555 3780 3555 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 3 + 1 1 1.00 45.00 90.00 + 4500 4050 6660 4050 6660 4770 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 + 1 1 1.00 45.00 90.00 + 7380 6030 7920 6030 7920 4050 6660 4050 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4 + 1 1 1.00 45.00 90.00 + 7380 8010 7920 8010 7920 6525 6660 6525 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 5 + 1 1 1.00 45.00 90.00 + 6660 8370 6660 8640 5310 8640 5310 4545 3780 4545 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 6660 5400 6660 5760 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 6660 6390 6660 6750 +2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2 + 1 1 1.00 45.00 90.00 + 6660 7380 6660 7740 +4 0 0 50 0 16 10 0.0000 4 105 210 3870 7560 Yes\001 +4 0 0 50 0 16 10 0.0000 4 105 165 4590 6930 No\001 +4 0 0 50 0 16 10 0.0000 4 105 240 4770 3600 start\001 +4 2 0 50 0 16 10 0.0000 4 105 165 3690 4590 No\001 +4 0 0 50 0 16 10 0.0000 4 105 210 4590 3960 Yes\001 +4 0 0 50 0 16 10 0.0000 4 105 165 7470 5940 No\001 +4 2 0 50 0 16 10 0.0000 4 105 210 6570 6570 Yes\001 +4 0 0 50 0 16 10 0.0000 4 105 165 7470 7920 No\001 +4 0 0 50 0 16 10 0.0000 4 105 210 6750 8550 Yes\001 diff --git a/usrp2/fpga/opencores/spi_boot/rtl/CVS/Entries b/usrp2/fpga/opencores/spi_boot/rtl/CVS/Entries new file mode 100644 index 00000000..a4756ee6 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/CVS/Entries @@ -0,0 +1 @@ +D/vhdl//// diff --git a/usrp2/fpga/opencores/spi_boot/rtl/CVS/Repository b/usrp2/fpga/opencores/spi_boot/rtl/CVS/Repository new file mode 100644 index 00000000..dcb0a69b --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/CVS/Repository @@ -0,0 +1 @@ +spi_boot/rtl diff --git a/usrp2/fpga/opencores/spi_boot/rtl/CVS/Root b/usrp2/fpga/opencores/spi_boot/rtl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/rtl/CVS/Template b/usrp2/fpga/opencores/spi_boot/rtl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Entries b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Entries new file mode 100644 index 00000000..880f353c --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Entries @@ -0,0 +1,15 @@ +/chip-e.vhd/1.3/Thu Apr 7 20:44:23 2005// +/chip-full-a.vhd/1.6/Thu Apr 7 20:44:23 2005// +/chip-full-c.vhd/1.1/Tue Feb 8 20:41:31 2005// +/chip-minimal-a.vhd/1.6/Thu Apr 7 20:44:23 2005// +/chip-minimal-c.vhd/1.1/Tue Feb 8 20:41:32 2005// +/chip-mmc-a.vhd/1.6/Thu Apr 7 20:44:23 2005// +/chip-mmc-c.vhd/1.1/Tue Feb 8 20:41:32 2005// +/chip-sd-a.vhd/1.6/Thu Apr 7 20:44:23 2005// +/chip-sd-c.vhd/1.1/Tue Feb 8 20:41:33 2005// +/spi_boot-c.vhd/1.2/Fri Feb 18 06:42:11 2005// +/spi_boot.vhd/1.9/Sun Feb 25 18:24:12 2007// +/spi_boot_pack-p.vhd/1.1/Tue Feb 8 20:41:33 2005// +/spi_counter-c.vhd/1.1/Tue Feb 8 20:41:33 2005// +/spi_counter.vhd/1.2/Sun Feb 25 18:24:12 2007// +D/sample//// diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Repository b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Repository new file mode 100644 index 00000000..a09f391e --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Repository @@ -0,0 +1 @@ +spi_boot/rtl/vhdl diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Root b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Template b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-e.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-e.vhd new file mode 100644 index 00000000..0bdd05af --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-e.vhd @@ -0,0 +1,91 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel +-- +-- $Id: chip-e.vhd,v 1.3 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity chip is + + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_n_i : in std_logic_vector(3 downto 0); + -- SD Card Interface ------------------------------------------------------ + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + -- FPGA Configuration Interface ------------------------------------------- + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + +end chip; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-e.vhd,v $ +-- Revision 1.3 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.2 2005/03/08 22:07:11 arniml +-- added set selection +-- +-- Revision 1.1 2005/02/08 20:41:30 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd new file mode 100644 index 00000000..e43ecb3c --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel design with full feature set +-- +-- $Id: chip-full-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +architecture full of chip is + + component spi_boot + generic ( + width_set_sel_g : integer := 4; + width_bit_cnt_g : integer := 6; + width_img_cnt_g : integer := 2; + num_bits_per_img_g : integer := 18; + sd_init_g : integer := 0; + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + signal spi_clk_s : std_logic; + signal spi_cs_n_s : std_logic; + signal spi_data_out_s : std_logic; + signal spi_en_outs_s : std_logic; + + signal set_sel_s : std_logic_vector(3 downto 0); + +begin + + set_sel_s <= not set_sel_n_i; + + spi_boot_b : spi_boot + generic map ( + width_set_sel_g => 4, -- 16 sets + width_bit_cnt_g => 12, -- 512 bytes per block + width_img_cnt_g => 2, -- 4 images + num_bits_per_img_g => 18, -- 256 kByte per image + sd_init_g => 1, -- use SD specific initialization + mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2) + width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + set_sel_i => set_sel_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_in_i, + spi_data_out_o => spi_data_out_s, + spi_en_outs_o => spi_en_outs_s, + start_i => start_i, + mode_i => mode_i, + config_n_o => config_n_o, + detached_o => detached_o, + cfg_init_n_i => cfg_init_n_i, + cfg_done_i => cfg_done_i, + dat_done_i => dat_done_i, + cfg_clk_o => cfg_clk_o, + cfg_dat_o => cfg_dat_o + ); + + ----------------------------------------------------------------------------- + -- Three state drivers for SPI outputs. + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_s + when spi_en_outs_s = '1' else + 'Z'; + spi_cs_n_o <= spi_cs_n_s + when spi_en_outs_s = '1' else + 'Z'; + spi_data_out_o <= spi_data_out_s + when spi_en_outs_s = '1' else + 'Z'; + +end full; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-full-a.vhd,v $ +-- Revision 1.6 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.5 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.4 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.3 2005/02/18 06:42:11 arniml +-- clarify wording for images +-- +-- Revision 1.2 2005/02/16 18:54:37 arniml +-- added tri-state drivers for spi outputs +-- +-- Revision 1.1 2005/02/08 20:41:31 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd new file mode 100644 index 00000000..da88552c --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: chip-full-c.vhd,v 1.1 2005/02/08 20:41:31 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration chip_full_c0 of chip is + + for full + + for spi_boot_b : spi_boot + use configuration work.spi_boot_rtl_c0; + end for; + + end for; + +end chip_full_c0; diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd new file mode 100644 index 00000000..090d0b79 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel design with minimal feature set +-- +-- $Id: chip-minimal-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +architecture minimal of chip is + + component spi_boot + generic ( + width_set_sel_g : integer := 4; + width_bit_cnt_g : integer := 6; + width_img_cnt_g : integer := 2; + num_bits_per_img_g : integer := 18; + sd_init_g : integer := 0; + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + signal spi_clk_s : std_logic; + signal spi_cs_n_s : std_logic; + signal spi_data_out_s : std_logic; + signal spi_en_outs_s : std_logic; + + signal set_sel_s : std_logic_vector(3 downto 0); + +begin + + set_sel_s <= not set_sel_n_i; + + spi_boot_b : spi_boot + generic map ( + width_set_sel_g => 4, -- 16 sets + width_bit_cnt_g => 6, -- 8 bytes per block + width_img_cnt_g => 2, -- 4 images + num_bits_per_img_g => 18, -- 256 kByte per image + sd_init_g => 0, -- no SD specific initialization + mmc_compat_clk_div_g => 0, -- no MMC compatibility + width_mmc_clk_div_g => 0 -- no MMC compatibility + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + set_sel_i => set_sel_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_in_i, + spi_data_out_o => spi_data_out_s, + spi_en_outs_o => spi_en_outs_s, + start_i => start_i, + mode_i => mode_i, + config_n_o => config_n_o, + detached_o => detached_o, + cfg_init_n_i => cfg_init_n_i, + cfg_done_i => cfg_done_i, + dat_done_i => dat_done_i, + cfg_clk_o => cfg_clk_o, + cfg_dat_o => cfg_dat_o + ); + + ----------------------------------------------------------------------------- + -- Three state drivers for SPI outputs. + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_s + when spi_en_outs_s = '1' else + 'Z'; + spi_cs_n_o <= spi_cs_n_s + when spi_en_outs_s = '1' else + 'Z'; + spi_data_out_o <= spi_data_out_s + when spi_en_outs_s = '1' else + 'Z'; + +end minimal; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-minimal-a.vhd,v $ +-- Revision 1.6 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.5 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.4 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.3 2005/02/18 06:42:12 arniml +-- clarify wording for images +-- +-- Revision 1.2 2005/02/16 18:54:39 arniml +-- added tri-state drivers for spi outputs +-- +-- Revision 1.1 2005/02/08 20:41:31 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd new file mode 100644 index 00000000..5547747b --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: chip-minimal-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration chip_minimal_c0 of chip is + + for minimal + + for spi_boot_b : spi_boot + use configuration work.spi_boot_rtl_c0; + end for; + + end for; + +end chip_minimal_c0; diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd new file mode 100644 index 00000000..cef42d26 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel design with MMC feature set +-- +-- $Id: chip-mmc-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +architecture mmc of chip is + + component spi_boot + generic ( + width_set_sel_g : integer := 4; + width_bit_cnt_g : integer := 6; + width_img_cnt_g : integer := 2; + num_bits_per_img_g : integer := 18; + sd_init_g : integer := 0; + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + signal spi_clk_s : std_logic; + signal spi_cs_n_s : std_logic; + signal spi_data_out_s : std_logic; + signal spi_en_outs_s : std_logic; + + signal set_sel_s : std_logic_vector(3 downto 0); + +begin + + set_sel_s <= not set_sel_n_i; + + spi_boot_b : spi_boot + generic map ( + width_set_sel_g => 4, -- 16 sets + width_bit_cnt_g => 12, -- 512 bytes per block + width_img_cnt_g => 2, -- 4 images + num_bits_per_img_g => 18, -- 256 kByte per image + sd_init_g => 0, -- no SD specific initialization + mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2) + width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + set_sel_i => set_sel_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_in_i, + spi_data_out_o => spi_data_out_s, + spi_en_outs_o => spi_en_outs_s, + start_i => start_i, + mode_i => mode_i, + config_n_o => config_n_o, + detached_o => detached_o, + cfg_init_n_i => cfg_init_n_i, + cfg_done_i => cfg_done_i, + dat_done_i => dat_done_i, + cfg_clk_o => cfg_clk_o, + cfg_dat_o => cfg_dat_o + ); + + ----------------------------------------------------------------------------- + -- Three state drivers for SPI outputs. + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_s + when spi_en_outs_s = '1' else + 'Z'; + spi_cs_n_o <= spi_cs_n_s + when spi_en_outs_s = '1' else + 'Z'; + spi_data_out_o <= spi_data_out_s + when spi_en_outs_s = '1' else + 'Z'; + +end mmc; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-mmc-a.vhd,v $ +-- Revision 1.6 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.5 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.4 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.3 2005/02/18 06:42:13 arniml +-- clarify wording for images +-- +-- Revision 1.2 2005/02/16 18:54:39 arniml +-- added tri-state drivers for spi outputs +-- +-- Revision 1.1 2005/02/08 20:41:32 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd new file mode 100644 index 00000000..6131013e --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: chip-mmc-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration chip_mmc_c0 of chip is + + for mmc + + for spi_boot_b : spi_boot + use configuration work.spi_boot_rtl_c0; + end for; + + end for; + +end chip_mmc_c0; diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd new file mode 100644 index 00000000..c955a5f3 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd @@ -0,0 +1,164 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Chip toplevel design with SD feature set +-- +-- $Id: chip-sd-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +architecture sd of chip is + + component spi_boot + generic ( + width_set_sel_g : integer := 4; + width_bit_cnt_g : integer := 6; + width_img_cnt_g : integer := 2; + num_bits_per_img_g : integer := 18; + sd_init_g : integer := 0; + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + reset_level_g : integer := 0 + ); + port ( + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + end component; + + signal spi_clk_s : std_logic; + signal spi_cs_n_s : std_logic; + signal spi_data_out_s : std_logic; + signal spi_en_outs_s : std_logic; + + signal set_sel_s : std_logic_vector(3 downto 0); + +begin + + set_sel_s <= not set_sel_n_i; + + spi_boot_b : spi_boot + generic map ( + width_set_sel_g => 4, -- 16 sets + width_bit_cnt_g => 12, -- 512 bytes per block + width_img_cnt_g => 2, -- 4 images + num_bits_per_img_g => 18, -- 256 kByte per image + sd_init_g => 1, -- SD specific initialization + mmc_compat_clk_div_g => 0, -- no MMC compatibility + width_mmc_clk_div_g => 0 -- no MMC compatibility + ) + port map ( + clk_i => clk_i, + reset_i => reset_i, + set_sel_i => set_sel_s, + spi_clk_o => spi_clk_s, + spi_cs_n_o => spi_cs_n_s, + spi_data_in_i => spi_data_in_i, + spi_data_out_o => spi_data_out_s, + spi_en_outs_o => spi_en_outs_s, + start_i => start_i, + mode_i => mode_i, + config_n_o => config_n_o, + detached_o => detached_o, + cfg_init_n_i => cfg_init_n_i, + cfg_done_i => cfg_done_i, + dat_done_i => dat_done_i, + cfg_clk_o => cfg_clk_o, + cfg_dat_o => cfg_dat_o + ); + + ----------------------------------------------------------------------------- + -- Three state drivers for SPI outputs. + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_s + when spi_en_outs_s = '1' else + 'Z'; + spi_cs_n_o <= spi_cs_n_s + when spi_en_outs_s = '1' else + 'Z'; + spi_data_out_o <= spi_data_out_s + when spi_en_outs_s = '1' else + 'Z'; + +end sd; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: chip-sd-a.vhd,v $ +-- Revision 1.6 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.5 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.4 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.3 2005/02/18 06:42:14 arniml +-- clarify wording for images +-- +-- Revision 1.2 2005/02/16 18:54:39 arniml +-- added tri-state drivers for spi outputs +-- +-- Revision 1.1 2005/02/08 20:41:32 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd new file mode 100644 index 00000000..91e41ddf --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd @@ -0,0 +1,19 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: chip-sd-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration chip_sd_c0 of chip is + + for sd + + for spi_boot_b : spi_boot + use configuration work.spi_boot_rtl_c0; + end for; + + end for; + +end chip_sd_c0; diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries new file mode 100644 index 00000000..552a7baa --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries @@ -0,0 +1,3 @@ +/ram_loader-c.vhd/1.1/Sun Apr 10 18:02:32 2005// +/ram_loader.vhd/1.2/Sun Apr 10 17:17:23 2005// +D diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository new file mode 100644 index 00000000..026a7398 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository @@ -0,0 +1 @@ +spi_boot/rtl/vhdl/sample diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Root b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Template b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd new file mode 100644 index 00000000..8b26c4d5 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd @@ -0,0 +1,10 @@ +------------------------------------------------------------------------------- +-- $Id: ram_loader-c.vhd,v 1.1 2005/04/10 18:02:32 arniml Exp $ +------------------------------------------------------------------------------- + +configuration ram_loader_rtl_c0 of ram_loader is + + for rtl + end for; + +end ram_loader_rtl_c0; diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd new file mode 100644 index 00000000..c604876d --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd @@ -0,0 +1,355 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Sample client for loading an image to asynchronous SRAM +-- +-- $Id: ram_loader.vhd,v 1.2 2005/04/10 17:17:23 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity ram_loader is + + port ( + -- Global Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + lamp_o : out std_logic; + -- Config Interface ------------------------------------------------------- + cfg_clk_i : in std_logic; + cfg_data_i : in std_logic; + start_o : out std_logic; + mode_o : out std_logic; + done_o : out std_logic; + detached_i : in std_logic; + -- Asynchronous RAM Interface --------------------------------------------- + ram_addr_o : out std_logic_vector(15 downto 0); + ram_data_b : out std_logic_vector( 7 downto 0); + ram_ce_no : out std_logic_vector( 3 downto 0); + ram_oe_no : out std_logic; + ram_we_no : out std_logic + ); + +end ram_loader; + + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of ram_loader is + + signal addr_q : unsigned(17 downto 0); + signal inc_addr_s : boolean; + + signal shift_dat_q : std_logic_vector(7 downto 0); + signal ser_dat_q : std_logic_vector(7 downto 0); + signal bit_q : unsigned(2 downto 0); + signal bit_ovfl_q : boolean; + + type fsm_t is (IDLE, + WE_ON, + WE_OFF, + INC_ADDR1, INC_ADDR2, + FINISHED); + signal fsm_s, + fsm_q : fsm_t; + signal done_q : std_logic; + signal done_s : boolean; + signal mode_q, + mode_s : std_logic; + + signal ram_we_n_q, + ram_we_n_s : std_logic; + signal ram_ce_n_q, + ram_ce_n_s : std_logic_vector(3 downto 0); + + type start_fsm_t is (WAIT_DETACH, + CHECK_NO_DONE, + WAIT_DONE); + signal start_fsm_s, + start_fsm_q : start_fsm_t; + + signal start_s, + start_q : std_logic; + signal enable_s, + enable_q : boolean; + +begin + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements the sequential elements clocked with cfg_clk_i. + -- + seq: process (cfg_clk_i, reset_i) + begin + if reset_i = '0' then + addr_q <= (others => '0'); + shift_dat_q <= (others => '0'); + ser_dat_q <= (others => '0'); + bit_q <= (others => '0'); + bit_ovfl_q <= false; + fsm_q <= IDLE; + ram_we_n_q <= '1'; + ram_ce_n_q <= (others => '1'); + done_q <= '0'; + mode_q <= '0'; + + elsif cfg_clk_i'event and cfg_clk_i = '1' then + if inc_addr_s then + addr_q <= addr_q + 1; + end if; + + if enable_q then + bit_q <= bit_q + 1; + bit_ovfl_q <= bit_q = 7; + + shift_dat_q(0) <= cfg_data_i; + shift_dat_q(7 downto 1) <= shift_dat_q(6 downto 0); + end if; + + -- update register when 8 serial bits have been shifted in + if bit_ovfl_q then + ser_dat_q <= shift_dat_q; + end if; + + fsm_q <= fsm_s; + + ram_we_n_q <= ram_we_n_s; + ram_ce_n_q <= ram_ce_n_s; + + -- done only settable once + if done_s then + done_q <= '1'; + end if; + + mode_q <= mode_s; + + end if; + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process fsm + -- + -- Purpose: + -- Implements the combinational logic of the RAM loader FSM. + -- + fsm: process (fsm_q, + bit_ovfl_q, + start_q, + addr_q) + begin + -- default assignments + inc_addr_s <= false; + ram_we_n_s <= '1'; + done_s <= false; + fsm_s <= IDLE; + lamp_o <= '1'; + mode_s <= '0'; + + case fsm_q is + when IDLE => + lamp_o <= '0'; + if start_q = '1' then + if bit_ovfl_q then + fsm_s <= WE_ON; + end if; + end if; + + when WE_ON => + ram_we_n_s <= '0'; + fsm_s <= WE_OFF; + + when WE_OFF => + fsm_s <= INC_ADDR1; + + when INC_ADDR1 => + fsm_s <= INC_ADDR2; + + when INC_ADDR2 => + if addr_q = "001111111111111111" then -- load only 64k + fsm_s <= FINISHED; + done_s <= true; + mode_s <= '1'; + else + inc_addr_s <= true; + fsm_s <= IDLE; + end if; + + when FINISHED => + fsm_s <= FINISHED; + lamp_o <= '1'; + mode_s <= '1'; + + when others => + end case; + + end process fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process ce_gen + -- + -- Purpose: + -- Generates the four CE signals for the external RAM chips. + -- + ce_gen: process (addr_q) + begin + ram_ce_n_s <= (others => '1'); + ram_ce_n_s(to_integer(addr_q(17 downto 16))) <= '0'; + end process ce_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process start_seq + -- + -- Purpose: + -- Implements the sequential elements clocked with clk_i. + -- + start_seq: process (clk_i, reset_i) + begin + if reset_i = '0' then + start_fsm_q <= WAIT_DETACH; + start_q <= '0'; + enable_q <= false; + + elsif clk_i'event and clk_i = '1' then + start_fsm_q <= start_fsm_s; + + enable_q <= enable_s; + + start_q <= start_s; + + end if; + end process start_seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process start_comb + -- + -- Purpose: + -- Implements the combinational logic of the start FSM. + -- + start_comb: process (start_fsm_q, + detached_i, + done_q, + enable_q, + start_q) + begin + -- default assignments + start_fsm_s <= WAIT_DETACH; + enable_s <= enable_q; + start_s <= start_q; + + case start_fsm_q is + -- Wait for detached_i to become '1' + -- This state is entered/left twice: + -- 1. after reset to start the data download + -- 2. after data download to start the next configuration cycle + when WAIT_DETACH => + if detached_i = '1' then + start_fsm_s <= CHECK_NO_DONE; + enable_s <= true; + start_s <= '1'; + + else + start_fsm_s <= WAIT_DETACH; + end if; + + -- Wait until done_q is '0' + -- This ensures that the FSM stalls when it has started the configuration + -- download. There must be no further action in this case. + when CHECK_NO_DONE => + if done_q = '0' then + start_fsm_s <= WAIT_DONE; + else + start_fsm_s <= CHECK_NO_DONE; + end if; + + -- Wait until done_q is '1' + -- done_q is the signal that the main FSM has finished its work. We + -- need to start the configuration download. + when WAIT_DONE => + if done_q = '1' then + start_fsm_s <= WAIT_DETACH; + enable_s <= false; + start_s <= '0'; + else + start_fsm_s <= WAIT_DONE; + end if; + + when others => + null; + + end case; + + end process start_comb; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + start_o <= start_q; + mode_o <= mode_q; + done_o <= done_q + when start_q = '1' else + '1'; + ram_addr_o <= std_logic_vector(addr_q(15 downto 0)); + ram_data_b <= ser_dat_q; + ram_oe_no <= '1'; + ram_ce_no <= ram_ce_n_q; + ram_we_no <= ram_we_n_q; + +end rtl; diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd new file mode 100644 index 00000000..6f11ed34 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd @@ -0,0 +1,27 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: spi_boot-c.vhd,v 1.2 2005/02/18 06:42:11 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration spi_boot_rtl_c0 of spi_boot is + + for rtl + + for img_cnt + for img_cnt_b : spi_counter + use configuration work.spi_counter_rtl_c0; + end for; + end for; + + for mmc_cnt + for mmc_cnt_b : spi_counter + use configuration work.spi_counter_rtl_c0; + end for; + end for; + + end for; + +end spi_boot_rtl_c0; diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot.vhd new file mode 100644 index 00000000..3d2b81da --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot.vhd @@ -0,0 +1,979 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: spi_boot.vhd,v 1.9 2007/02/25 18:24:12 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity spi_boot is + + generic ( + -- width of set selection + width_set_sel_g : integer := 4; + -- width of bit counter: minimum 6, maximum 12 + width_bit_cnt_g : integer := 6; + -- width of image counter: minimum 0, maximum n + width_img_cnt_g : integer := 2; + -- number of bits required to address one image + num_bits_per_img_g : integer := 18; + -- SD specific initialization + sd_init_g : integer := 0; + -- clock divider to reach 400 kHz for MMC compatibility + mmc_compat_clk_div_g : integer := 0; + width_mmc_clk_div_g : integer := 0; + -- active level of reset_i + reset_level_g : integer := 0 + ); + + port ( + -- System Interface ------------------------------------------------------- + clk_i : in std_logic; + reset_i : in std_logic; + set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0); + -- Card Interface --------------------------------------------------------- + spi_clk_o : out std_logic; + spi_cs_n_o : out std_logic; + spi_data_in_i : in std_logic; + spi_data_out_o : out std_logic; + spi_en_outs_o : out std_logic; + -- FPGA Configuration Interface ------------------------------------------- + start_i : in std_logic; + mode_i : in std_logic; + config_n_o : out std_logic; + detached_o : out std_logic; + cfg_init_n_i : in std_logic; + cfg_done_i : in std_logic; + dat_done_i : in std_logic; + cfg_clk_o : out std_logic; + cfg_dat_o : out std_logic + ); + +end spi_boot; + + +library ieee; +use ieee.numeric_std.all; +use work.spi_boot_pack.all; + +architecture rtl of spi_boot is + + component spi_counter + generic ( + cnt_width_g : integer := 4; + cnt_max_g : integer := 15 + ); + port ( + clk_i : in std_logic; + reset_i : in boolean; + cnt_en_i : in boolean; + cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); + cnt_ovfl_o : out boolean + ); + end component; + + + ----------------------------------------------------------------------------- + -- States of the controller FSM + -- + type ctrl_states_t is (POWER_UP1, POWER_UP2, + CMD0, + CMD1, + CMD55, ACMD41, + CMD16, + WAIT_START, + WAIT_INIT_LOW, WAIT_INIT_HIGH, + CMD18, CMD18_DATA, + CMD12, + INC_IMG_CNT); + -- + signal ctrl_fsm_q, + ctrl_fsm_s : ctrl_states_t; + -- + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- States of the command FSM + -- + type cmd_states_t is (CMD, START, R1, PAUSE); + -- + signal cmd_fsm_q, + cmd_fsm_s : cmd_states_t; + -- + ----------------------------------------------------------------------------- + + subtype op_r is integer range 5 downto 0; + type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7); + signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0); + signal res_bc_s : res_bc_t; + signal upper_bitcnt_zero_s : boolean; + + signal cfg_dat_q : std_logic; + + signal spi_clk_q : std_logic; + signal spi_clk_rising_q : boolean; + signal spi_clk_falling_q : boolean; + signal spi_dat_q, + spi_dat_s : std_logic; + signal spi_cs_n_q, + spi_cs_n_s : std_logic; + + signal cfg_clk_q : std_logic; + + signal start_q : std_logic; + + signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0); + signal cnt_en_img_s : boolean; + signal mmc_cnt_ovfl_s : boolean; + signal mmc_compat_s : boolean; + + signal cmd_finished_s : boolean; + + signal r1_result_q : std_logic; + signal done_q, + send_cmd12_q : boolean; + + signal en_outs_s, + en_outs_q : boolean; + + signal reset_s : boolean; + + signal true_s : boolean; + +begin + + true_s <= true; + + reset_s <= true + when (reset_level_g = 1 and reset_i = '1') or + (reset_level_g = 0 and reset_i = '0') else + false; + + ----------------------------------------------------------------------------- + -- Process seq + -- + -- Purpose: + -- Implements several sequential elements. + -- + seq: process (clk_i, reset_s) + + variable bit_cnt_v : unsigned(1 downto 0); + + begin + if reset_s then + -- reset bit counter to 63 for power up + bit_cnt_q <= (others => '0'); + bit_cnt_q(op_r) <= "111111"; + spi_dat_q <= '1'; + spi_cs_n_q <= '1'; + cfg_dat_q <= '1'; + start_q <= '0'; + done_q <= false; + send_cmd12_q <= false; + ctrl_fsm_q <= POWER_UP1; + cmd_fsm_q <= CMD; + r1_result_q <= '0'; + en_outs_q <= false; + + elsif clk_i'event and clk_i = '1' then + -- bit counter control + if spi_clk_rising_q then + case res_bc_s is + when NONE => + bit_cnt_q <= bit_cnt_q - 1; + when RES_MAX => + bit_cnt_q <= (others => '1'); + when RES_47 => + bit_cnt_q <= (others => '0'); + bit_cnt_q(op_r) <= "101111"; + when RES_15 => + bit_cnt_q <= (others => '0'); + bit_cnt_q(op_r) <= "001111"; + when RES_7 => + bit_cnt_q <= (others => '0'); + bit_cnt_q(op_r) <= "000111"; + when others => + bit_cnt_q <= (others => '0'); + end case; + end if; + + -- Card data output register + -- spi_clk_falling_q acts as enable during MMC clock compatibility mode. + -- As soon as this mode is left, the register must start latching. + -- There is no explicit relation to spi_clk_q anymore in normal mode. + -- Instead, spi_dat_s is operated by bit_cnt_q above which changes its + -- value after the rising edge of spi_clk_q. + -- -> spi_dat_q changes upon falling edge of spi_clk_q + if spi_clk_falling_q or not mmc_compat_s then + spi_dat_q <= spi_dat_s; + end if; + + -- config data output register + -- a new value is loaded when config clock is high, + -- i.e. input data is sampled with rising spi_clk + -- while output value changes on falling edge of cfg_clk + if cfg_clk_q = '1' and spi_clk_rising_q then + cfg_dat_q <= spi_data_in_i; + end if; + + -- Controller FSM state + ctrl_fsm_q <= ctrl_fsm_s; + + -- Command FSM state + cmd_fsm_q <= cmd_fsm_s; + + -- CS signal for SPI card + if spi_clk_q = '1' then + spi_cs_n_q <= spi_cs_n_s; + end if; + + -- Extract flags from R1 response + if cmd_fsm_q = R1 then + bit_cnt_v := bit_cnt_q(1 downto 0); + case bit_cnt_v(1 downto 0) is + when "10" => + -- always save "Illegal Command" flag + r1_result_q <= to_X01(spi_data_in_i); + when "00" => + -- overwrite with "Idle State" flag when not in CMD55 + if ctrl_fsm_q /= CMD55 then + r1_result_q <= to_X01(spi_data_in_i); + end if; + when others => + null; + end case; + end if; + + -- Start trigger register for rising edge detection + -- the reset value is '0' thus a rising edge will always be detected + -- after reset even though start_i is tied to '1' + if start_i = '0' then + start_q <= '0'; + elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then + start_q <= start_i; + end if; + + -- Marker for cfg_done and dat_done + if ctrl_fsm_q = CMD18_DATA then + if cfg_done_i = '1' and dat_done_i = '1' then + done_q <= true; + end if; + + if done_q and + (not upper_bitcnt_zero_s or cmd_fsm_q = START) then + -- activate sending of CMD12 when it is safe: + -- * upper bits of bit counter are not zero + -- -> transmission of CMD12 is not running + -- * cmd FSM is in START state + -- -> also no transmission running + send_cmd12_q <= true; + end if; + elsif ctrl_fsm_q = WAIT_START then + -- reset done_q when WAIT_START has been reached + -- this is necessary to let the stop transmission process come to + -- an end without interruption or generation of unwanted cfg_clk_q + done_q <= false; + send_cmd12_q <= false; + end if; + + -- output enable + if spi_clk_rising_q then + en_outs_q <= en_outs_s; + end if; + + end if; + + end process seq; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process upper_bits + -- + -- Purpose: + -- Detects that the upper bits of the bit counter are zero. + -- Upper bits = n downto 6, i.e. the optional part that is not required for + -- commands but for extension of data blocks. + -- + upper_bits: process (bit_cnt_q) + variable zero_v : boolean; + begin + + zero_v := true; + for i in bit_cnt_q'high downto 6 loop + if bit_cnt_q(i) = '1' then + zero_v := false; + end if; + end loop; + + upper_bitcnt_zero_s <= zero_v; + + end process upper_bits; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process clk_gen + -- + -- Purpose: + -- Generates clocks for card and FPGA configuration. + -- The card clock is free running with a divide by two of clk_i. + -- The clock for FPGA config has an enable and is stopped on high level. + -- There is a phase shift of half a period between spi_clk and cfg_clk. + -- + clk_gen: process (clk_i, reset_s) + begin + if reset_s then + spi_clk_q <= '0'; + cfg_clk_q <= '1'; + + elsif clk_i'event and clk_i = '1' then + + -- spi_clk_q rises according to the flag + -- it falls with overflow indication + -- the resulting duty cycle is not exactly 50:50, + -- high time is a bit longer + if mmc_compat_s then + -- MMC clock compatibility mode: + -- spi_clk_q rises when flagged by spi_clk_rising_q + if spi_clk_rising_q then + spi_clk_q <= '1'; + elsif mmc_cnt_ovfl_s then + -- upon counter overflow spi_clk_q falls in case it does not rise + spi_clk_q <= '0'; + end if; + else + -- normal mode + -- spi_clk_q follows spi_clk_rising_q + if spi_clk_rising_q then + spi_clk_q <= '1'; + else + spi_clk_q <= '0'; + end if; + end if; + + -- clock for FPGA config must be enabled and follows spi_clk + if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and + not done_q then + cfg_clk_q <= spi_clk_q; + else + cfg_clk_q <= '1'; + end if; + + end if; + + end process clk_gen; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Indication flags for rising and falling spi_clk_q. + -- Essential for MMC clock compatibility mode. + ----------------------------------------------------------------------------- + mmc_comap: if mmc_compat_clk_div_g > 0 generate + mmc_compat_sig: process (clk_i, reset_s) + begin + if reset_s then + spi_clk_rising_q <= false; + spi_clk_falling_q <= false; + + elsif clk_i'event and clk_i = '1' then + if mmc_compat_s then + -- MMC clock compatibility mode: + -- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q + -- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q + if mmc_cnt_ovfl_s then + spi_clk_rising_q <= spi_clk_q = '0'; + spi_clk_falling_q <= spi_clk_q = '1'; + else + spi_clk_rising_q <= false; + spi_clk_falling_q <= false; + end if; + else + -- normal mode + spi_clk_rising_q <= not spi_clk_rising_q; + spi_clk_falling_q <= true; + end if; + + end if; + end process mmc_compat_sig; + end generate; + + no_mmc_compat: if mmc_compat_clk_div_g = 0 generate + -- SPI clock rising whenever spi_clk_q is '0' + spi_clk_rising_q <= spi_clk_q = '0'; + -- SPI clock falling whenever spi_clk_q is '1' + spi_clk_falling_q <= spi_clk_q = '1'; + end generate; + + + ----------------------------------------------------------------------------- + -- Process ctrl_fsm + -- + -- Purpose: + -- Implements the controller FSM. + -- + ctrl_fsm: process (ctrl_fsm_q, + cmd_finished_s, r1_result_q, + start_i, start_q, mode_i, + cfg_init_n_i) + + variable mmc_compat_v : boolean; + + begin + -- default assignments + ctrl_fsm_s <= POWER_UP1; + config_n_o <= '1'; + cnt_en_img_s <= false; + spi_cs_n_s <= '0'; + mmc_compat_v := false; + en_outs_s <= true; + + case ctrl_fsm_q is + -- Let card finish power up, step 1 ------------------------------------- + when POWER_UP1 => + mmc_compat_v := true; + spi_cs_n_s <= '1'; + if cmd_finished_s then + ctrl_fsm_s <= POWER_UP2; + else + ctrl_fsm_s <= POWER_UP1; + end if; + + + -- Let card finish power up, step 2 ------------------------------------- + when POWER_UP2 => + mmc_compat_v := true; + if cmd_finished_s then + ctrl_fsm_s <= CMD0; + else + spi_cs_n_s <= '1'; + ctrl_fsm_s <= POWER_UP2; + end if; + + + -- Issue CMD0: GO_IDLE_STATE -------------------------------------------- + when CMD0 => + mmc_compat_v := true; + if cmd_finished_s then + if sd_init_g = 1 then + ctrl_fsm_s <= CMD55; + else + ctrl_fsm_s <= CMD1; + end if; + else + ctrl_fsm_s <= CMD0; + end if; + + + -- Issue CMD55: APP_CMD ------------------------------------------------- + when CMD55 => + if sd_init_g = 1 then + + mmc_compat_v := true; + if cmd_finished_s then + if r1_result_q = '0' then + -- command accepted, it's an SD card + ctrl_fsm_s <= ACMD41; + else + -- command rejected, it's an MMC card + ctrl_fsm_s <= CMD1; + end if; + else + ctrl_fsm_s <= CMD55; + end if; + + end if; + + + -- Issue ACMD41: SEND_OP_COND ------------------------------------------- + when ACMD41 => + if sd_init_g = 1 then + + mmc_compat_v := true; + if cmd_finished_s then + if r1_result_q = '0' then + ctrl_fsm_s <= CMD16; + else + ctrl_fsm_s <= CMD55; + end if; + else + ctrl_fsm_s <= ACMD41; + end if; + + end if; + + + -- Issue CMD1: SEND_OP_COND --------------------------------------------- + when CMD1 => + mmc_compat_v := true; + if cmd_finished_s then + if r1_result_q = '0' then + ctrl_fsm_s <= CMD16; + else + ctrl_fsm_s <= CMD1; + end if; + else + ctrl_fsm_s <= CMD1; + end if; + + + -- Issue CMD16: SET_BLOCKLEN -------------------------------------------- + when CMD16 => + if cmd_finished_s then + ctrl_fsm_s <= WAIT_START; + else + ctrl_fsm_s <= CMD16; + end if; + + + -- Wait for configuration start request --------------------------------- + when WAIT_START => + spi_cs_n_s <= '1'; + + -- detect rising edge of start_i + if start_i = '1' and start_q = '0' then + -- decide which mode is requested + if cmd_finished_s then + if mode_i = '0' then + ctrl_fsm_s <= CMD18; + else + ctrl_fsm_s <= WAIT_INIT_LOW; + end if; + else + en_outs_s <= false; + ctrl_fsm_s <= WAIT_START; + end if; + else + en_outs_s <= false; + ctrl_fsm_s <= WAIT_START; + end if; + + + -- Wait for INIT to become low ------------------------------------------ + when WAIT_INIT_LOW => + spi_cs_n_s <= '1'; + -- activate FPGA configuration + config_n_o <= '0'; + + if cfg_init_n_i = '0' then + ctrl_fsm_s <= WAIT_INIT_HIGH; + else + ctrl_fsm_s <= WAIT_INIT_LOW; + end if; + + + -- Wait for INIT to become high ----------------------------------------- + when WAIT_INIT_HIGH => + spi_cs_n_s <= '1'; + + if cfg_init_n_i = '1' and cmd_finished_s then + ctrl_fsm_s <= CMD18; + else + ctrl_fsm_s <= WAIT_INIT_HIGH; + end if; + + + -- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------ + when CMD18 => + if cmd_finished_s then + ctrl_fsm_s <= CMD18_DATA; + else + ctrl_fsm_s <= CMD18; + end if; + -- + -- receive a data block + when CMD18_DATA => + if cmd_finished_s then + ctrl_fsm_s <= CMD12; + else + ctrl_fsm_s <= CMD18_DATA; + end if; + + + -- Issued CMD12: STOP_TRANSMISSION -------------------------------------- + when CMD12 => + if cmd_finished_s then + ctrl_fsm_s <= INC_IMG_CNT; + else + ctrl_fsm_s <= CMD12; + end if; + + + -- Increment Image Counter ---------------------------------------------- + when INC_IMG_CNT => + spi_cs_n_s <= '1'; + ctrl_fsm_s <= WAIT_START; + cnt_en_img_s <= true; + + + + when others => + null; + + end case; + + -- mmc_compat_s is suppressed if MMC clock compatibility is not required + if mmc_compat_clk_div_g > 0 then + mmc_compat_s <= mmc_compat_v; + else + mmc_compat_s <= false; + end if; + + end process ctrl_fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process cmd_fsm + -- + -- Purpose: + -- Implements the command FSM. + -- + cmd_fsm: process (spi_clk_rising_q, + spi_data_in_i, + bit_cnt_q, + ctrl_fsm_q, + cmd_fsm_q, + send_cmd12_q) + + variable cnt_zero_v : boolean; + variable spi_data_low_v : boolean; + variable no_startbit_v : boolean; + + begin + -- default assignments + cmd_finished_s <= false; + cmd_fsm_s <= CMD; + res_bc_s <= NONE; + + cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0; + spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0'; + + -- these are no real commands thus there will be no startbit + case ctrl_fsm_q is + when POWER_UP1 | POWER_UP2 | + WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW => + no_startbit_v := true; + when others => + no_startbit_v := false; + end case; + + + case cmd_fsm_q is + -- Send the command ----------------------------------------------------- + when CMD => + if cnt_zero_v then + if ctrl_fsm_q /= CMD18_DATA then + -- normal commands including CMD12 require startbit of R1 response + cmd_fsm_s <= START; + else + if not send_cmd12_q then + -- CMD18_DATA needs to read CRC + cmd_fsm_s <= R1; + res_bc_s <= RES_15; + else + -- CMD18_DATA finished, scan for startbit of response + cmd_finished_s <= true; + cmd_fsm_s <= START; + end if; + end if; + else + cmd_fsm_s <= CMD; + end if; + + -- Wait for startbit of response ---------------------------------------- + when START => + -- startbit detection or skip of this check + if no_startbit_v and spi_clk_rising_q then + cmd_fsm_s <= R1; + res_bc_s <= RES_7; + elsif spi_data_low_v then + if ctrl_fsm_q /= CMD18_DATA then + cmd_fsm_s <= R1; + else + -- CMD18_DATA startbit detected, read payload + cmd_fsm_s <= CMD; + res_bc_s <= RES_MAX; + end if; + else + cmd_fsm_s <= START; + res_bc_s <= RES_7; + end if; + + -- Read R1 response ----------------------------------------------------- + when R1 => + if cnt_zero_v then + res_bc_s <= RES_7; + + if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then + cmd_fsm_s <= PAUSE; + else + -- CMD18 needs another startbit detection for the data token. + -- CMD18_DATA needs a startbit after having received the CRC, either + -- * next data token + -- * R1 response of CMD12 + cmd_fsm_s <= START; + + if ctrl_fsm_q = CMD18 then + -- CMD18 response received -> advance to CMD18_DATA + cmd_finished_s <= true; + end if; + end if; + else + cmd_fsm_s <= R1; + end if; + + -- PAUSE state -> required for Nrc, card response to host command ------- + when PAUSE => + if cnt_zero_v then + cmd_fsm_s <= CMD; + res_bc_s <= RES_47; + cmd_finished_s <= true; + else + cmd_fsm_s <= PAUSE; + end if; + + when others => + null; + + end case; + + end process cmd_fsm; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Process transmit + -- + -- Purpose: + -- Generates the serial data output values based on the current FSM state + -- + -- The local variable cmd_v is 64 bits wide in contrast to an SPI command + -- with 48 bits. There are two reasons for this: + -- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit + -- counter will start from 3F on its lowest 6 bits. Therefore, it is + -- necessary to provide all 64 positions in cmd_v. + -- * Reduces logic. + -- + transmit: process (ctrl_fsm_q, + cmd_fsm_q, + bit_cnt_q, + img_cnt_s, + send_cmd12_q, + set_sel_i, + upper_bitcnt_zero_s) + + subtype cmd_r is natural range 47 downto 0; + subtype cmd_t is std_logic_vector(cmd_r); + subtype ext_cmd_t is std_logic_vector(63 downto 0); + -- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS + constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101"; + constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1"; + constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1"; + constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1"; + constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1"; + constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1"; + constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1"; + + variable cmd_v : ext_cmd_t; + variable tx_v : boolean; + + begin + -- default assignments + spi_dat_s <= '1'; + cmd_v := (others => '1'); + tx_v := false; + + if cmd_fsm_q = CMD then + case ctrl_fsm_q is + when CMD0 => + cmd_v(cmd_r) := cmd0_c; + tx_v := true; + when CMD1 => + cmd_v(cmd_r) := cmd1_c; + tx_v := true; + when CMD16 => + cmd_v(cmd_r) := cmd16_c; + cmd_v(8 + width_bit_cnt_g-3) := '1'; + tx_v := true; + when CMD18 => + cmd_v(cmd_r) := cmd18_c; + -- insert image counter + cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + downto 8 + num_bits_per_img_g) := img_cnt_s; + -- insert set selection + cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + width_set_sel_g-1 + downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i; + tx_v := true; + when CMD18_DATA => + cmd_v(cmd_r) := cmd12_c; + + if send_cmd12_q and upper_bitcnt_zero_s then + tx_v := true; + end if; + when CMD55 => + cmd_v(cmd_r) := cmd55_c; + tx_v := true; + when ACMD41 => + cmd_v(cmd_r) := acmd41_c; + tx_v := true; + + when others => + null; + end case; + end if; + + if tx_v then + spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0))); + end if; + + end process transmit; + -- + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- Optional Image Counter + ----------------------------------------------------------------------------- + img_cnt: if width_img_cnt_g > 0 generate + img_cnt_b : spi_counter + generic map ( + cnt_width_g => width_img_cnt_g, + cnt_max_g => 2**width_img_cnt_g - 1 + ) + port map ( + clk_i => clk_i, + reset_i => reset_s, + cnt_en_i => cnt_en_img_s, + cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0), + cnt_ovfl_o => open + ); + img_cnt_s(width_img_cnt_g) <= '0'; + end generate; + + no_img_cnt: if width_img_cnt_g = 0 generate + img_cnt_s <= (others => '0'); + end generate; + + + ----------------------------------------------------------------------------- + -- Optional MMC compatibility counter + ----------------------------------------------------------------------------- + mmc_cnt: if mmc_compat_clk_div_g > 0 generate + mmc_cnt_b : spi_counter + generic map ( + cnt_width_g => width_mmc_clk_div_g, + cnt_max_g => mmc_compat_clk_div_g + ) + port map ( + clk_i => clk_i, + reset_i => reset_s, + cnt_en_i => true_s, + cnt_o => open, + cnt_ovfl_o => mmc_cnt_ovfl_s + ); + end generate; + + no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate + mmc_cnt_ovfl_s <= true; + end generate; + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + spi_clk_o <= spi_clk_q; + spi_cs_n_o <= spi_cs_n_q; + spi_data_out_o <= spi_dat_q; + spi_en_outs_o <= '1' + when en_outs_q else + '0'; + cfg_clk_o <= cfg_clk_q; + cfg_dat_o <= cfg_dat_q; + detached_o <= '0' + when en_outs_q else + '1'; + +end rtl; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: spi_boot.vhd,v $ +-- Revision 1.9 2007/02/25 18:24:12 arniml +-- fix type handling of resets +-- +-- Revision 1.8 2006/09/11 23:03:36 arniml +-- disable outputs with reset +-- +-- Revision 1.7 2005/04/07 20:44:23 arniml +-- add new port detached_o +-- +-- Revision 1.6 2005/03/09 19:48:34 arniml +-- invert level of set_sel input +-- +-- Revision 1.5 2005/03/08 22:07:12 arniml +-- added set selection +-- +-- Revision 1.4 2005/02/18 06:42:08 arniml +-- clarify wording for images +-- +-- Revision 1.3 2005/02/16 18:59:10 arniml +-- include output enable control for SPI outputs +-- +-- Revision 1.2 2005/02/13 17:25:51 arniml +-- major update to fix several problems +-- configuration/data download of multiple sets works now +-- +-- Revision 1.1 2005/02/08 20:41:33 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd new file mode 100644 index 00000000..ac8b544f --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: spi_boot_pack-p.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +package spi_boot_pack is + + function "=" (a : std_logic; b : integer) return boolean; + +end spi_boot_pack; + +package body spi_boot_pack is + + function "=" (a : std_logic; b : integer) return boolean is + variable result_v : boolean; + begin + result_v := false; + + case a is + when '0' => + if b = 0 then + result_v := true; + end if; + + when '1' => + if b = 1 then + result_v := true; + end if; + + when others => + null; + + end case; + + return result_v; + end; + +end spi_boot_pack; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: spi_boot_pack-p.vhd,v $ +-- Revision 1.1 2005/02/08 20:41:33 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd new file mode 100644 index 00000000..d81e20db --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd @@ -0,0 +1,14 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- +-- $Id: spi_counter-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $ +-- +------------------------------------------------------------------------------- + +configuration spi_counter_rtl_c0 of spi_counter is + + for rtl + end for; + +end spi_counter_rtl_c0; diff --git a/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter.vhd b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter.vhd new file mode 100644 index 00000000..8ec7357e --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter.vhd @@ -0,0 +1,118 @@ +------------------------------------------------------------------------------- +-- +-- SD/MMC Bootloader +-- Generic counter module +-- +-- $Id: spi_counter.vhd,v 1.2 2007/02/25 18:24:12 arniml Exp $ +-- +-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +-- +-- All rights reserved, see COPYING. +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/projects.cgi/web/spi_boot/overview +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +entity spi_counter is + + generic ( + cnt_width_g : integer := 4; + cnt_max_g : integer := 15 + ); + + port ( + clk_i : in std_logic; + reset_i : in boolean; + cnt_en_i : in boolean; + cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); + cnt_ovfl_o : out boolean + ); + +end spi_counter; + + +library ieee; +use ieee.numeric_std.all; +use work.spi_boot_pack.all; + +architecture rtl of spi_counter is + + signal cnt_q : unsigned(cnt_width_g-1 downto 0); + signal cnt_ovfl_s : boolean; + +begin + + cnt: process (clk_i, reset_i) + begin + if reset_i then + cnt_q <= (others => '0'); + + elsif clk_i'event and clk_i = '1' then + if cnt_en_i then + if not cnt_ovfl_s then + cnt_q <= cnt_q + 1; + else + cnt_q <= (others => '0'); + end if; + end if; + end if; + end process cnt; + + cnt_ovfl_s <= cnt_q = cnt_max_g; + + + ----------------------------------------------------------------------------- + -- Output Mapping + ----------------------------------------------------------------------------- + cnt_ovfl_o <= cnt_ovfl_s; + cnt_o <= std_logic_vector(cnt_q); + +end rtl; + + +------------------------------------------------------------------------------- +-- File History: +-- +-- $Log: spi_counter.vhd,v $ +-- Revision 1.2 2007/02/25 18:24:12 arniml +-- fix type handling of resets +-- +-- Revision 1.1 2005/02/08 20:41:33 arniml +-- initial check-in +-- +------------------------------------------------------------------------------- diff --git a/usrp2/fpga/opencores/spi_boot/sim/CVS/Entries b/usrp2/fpga/opencores/spi_boot/sim/CVS/Entries new file mode 100644 index 00000000..9487498a --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sim/CVS/Entries @@ -0,0 +1 @@ +D/rtl_sim//// diff --git a/usrp2/fpga/opencores/spi_boot/sim/CVS/Repository b/usrp2/fpga/opencores/spi_boot/sim/CVS/Repository new file mode 100644 index 00000000..4e2e0974 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sim/CVS/Repository @@ -0,0 +1 @@ +spi_boot/sim diff --git a/usrp2/fpga/opencores/spi_boot/sim/CVS/Root b/usrp2/fpga/opencores/spi_boot/sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/sim/CVS/Template b/usrp2/fpga/opencores/spi_boot/sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Entries b/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Entries new file mode 100644 index 00000000..e3d0dc14 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Entries @@ -0,0 +1,2 @@ +/Makefile/1.2/Sun Apr 10 18:14:19 2005// +D diff --git a/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Repository b/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Repository new file mode 100644 index 00000000..114ab862 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Repository @@ -0,0 +1 @@ +spi_boot/sim/rtl_sim diff --git a/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Root b/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Template b/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/Makefile b/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/Makefile new file mode 100644 index 00000000..46fb3c63 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sim/rtl_sim/Makefile @@ -0,0 +1,159 @@ +############################################################################## +# +# Makefile for the spi_boot project. +# +# The dependencies for all VHDL source files are stored here. +# +# Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) +# +# All rights reserved +# +############################################################################## + + +PROJECT_DIR = ../.. +RTL_DIR = $(PROJECT_DIR)/rtl/vhdl +BENCH_DIR = $(PROJECT_DIR)/bench/vhdl + + + +ANALYZE=ghdl -a --std=87 --workdir=work +ELABORATE=ghdl -e --std=87 --workdir=work + +.PHONY: all +all: work elaborate + +work: + mkdir work + +work/spi_boot_pack-p.o: $(RTL_DIR)/spi_boot_pack-p.vhd + $(ANALYZE) $(RTL_DIR)/spi_boot_pack-p.vhd + +work/spi_counter.o: $(RTL_DIR)/spi_counter.vhd \ + work/spi_boot_pack-p.o + $(ANALYZE) $(RTL_DIR)/spi_counter.vhd +work/spi_counter-c.o: $(RTL_DIR)/spi_counter-c.vhd \ + work/spi_counter.o + $(ANALYZE) $(RTL_DIR)/spi_counter-c.vhd + +work/spi_boot.o: $(RTL_DIR)/spi_boot.vhd \ + work/spi_boot_pack-p.o + $(ANALYZE) $(RTL_DIR)/spi_boot.vhd +work/spi_boot-c.o: $(RTL_DIR)/spi_boot-c.vhd \ + work/spi_boot.o \ + work/spi_counter-c.o + $(ANALYZE) $(RTL_DIR)/spi_boot-c.vhd + +work/chip-e.o: $(RTL_DIR)/chip-e.vhd + $(ANALYZE) $(RTL_DIR)/chip-e.vhd + +work/chip-full-a.o: $(RTL_DIR)/chip-full-a.vhd \ + work/chip-e.o + $(ANALYZE) $(RTL_DIR)/chip-full-a.vhd +work/chip-full-c.o: $(RTL_DIR)/chip-full-c.vhd \ + work/chip-full-a.o \ + work/spi_boot-c.o + $(ANALYZE) $(RTL_DIR)/chip-full-c.vhd + +work/chip-mmc-a.o: $(RTL_DIR)/chip-mmc-a.vhd \ + work/chip-e.o + $(ANALYZE) $(RTL_DIR)/chip-mmc-a.vhd +work/chip-mmc-c.o: $(RTL_DIR)/chip-mmc-c.vhd \ + work/chip-mmc-a.o \ + work/spi_boot-c.o + $(ANALYZE) $(RTL_DIR)/chip-mmc-c.vhd + +work/chip-sd-a.o: $(RTL_DIR)/chip-sd-a.vhd \ + work/chip-e.o + $(ANALYZE) $(RTL_DIR)/chip-sd-a.vhd +work/chip-sd-c.o: $(RTL_DIR)/chip-sd-c.vhd \ + work/chip-sd-a.o \ + work/spi_boot-c.o + $(ANALYZE) $(RTL_DIR)/chip-sd-c.vhd + +work/chip-minimal-a.o: $(RTL_DIR)/chip-minimal-a.vhd \ + work/chip-e.o + $(ANALYZE) $(RTL_DIR)/chip-minimal-a.vhd +work/chip-minimal-c.o: $(RTL_DIR)/chip-minimal-c.vhd \ + work/chip-minimal-a.o \ + work/spi_boot-c.o + $(ANALYZE) $(RTL_DIR)/chip-minimal-c.vhd + +work/ram_loader.o: $(RTL_DIR)/sample/ram_loader.vhd + $(ANALYZE) $(RTL_DIR)/sample/ram_loader.vhd +work/ram_loader-c.o: $(RTL_DIR)/sample/ram_loader-c.vhd \ + work/ram_loader.o + $(ANALYZE) $(RTL_DIR)/sample/ram_loader-c.vhd + +work/tb_pack-p.o: $(BENCH_DIR)/tb_pack-p.vhd + $(ANALYZE) $(BENCH_DIR)/tb_pack-p.vhd + +work/card.o: $(BENCH_DIR)/card.vhd \ + work/tb_pack-p.o + $(ANALYZE) $(BENCH_DIR)/card.vhd +work/card-c.o: $(BENCH_DIR)/card-c.vhd \ + work/card.o + $(ANALYZE) $(BENCH_DIR)/card-c.vhd + +work/tb_elem.o: $(BENCH_DIR)/tb_elem.vhd \ + work/spi_boot_pack-p.o \ + work/tb_pack-p.o + $(ANALYZE) $(BENCH_DIR)/tb_elem.vhd +work/tb_elem-full-c.o: $(BENCH_DIR)/tb_elem-full-c.vhd \ + work/tb_elem.o \ + work/chip-full-c.o \ + work/card-c.o + $(ANALYZE) $(BENCH_DIR)/tb_elem-full-c.vhd +work/tb_elem-mmc-c.o: $(BENCH_DIR)/tb_elem-mmc-c.vhd \ + work/tb_elem.o \ + work/chip-mmc-c.o \ + work/card-c.o + $(ANALYZE) $(BENCH_DIR)/tb_elem-mmc-c.vhd +work/tb_elem-sd-c.o: $(BENCH_DIR)/tb_elem-sd-c.vhd \ + work/tb_elem.o \ + work/chip-sd-c.o \ + work/card-c.o + $(ANALYZE) $(BENCH_DIR)/tb_elem-sd-c.vhd +work/tb_elem-minimal-c.o: $(BENCH_DIR)/tb_elem-minimal-c.vhd \ + work/tb_elem.o \ + work/chip-minimal-c.o \ + work/card-c.o + $(ANALYZE) $(BENCH_DIR)/tb_elem-minimal-c.vhd + +work/tb.o: $(BENCH_DIR)/tb.vhd + $(ANALYZE) $(BENCH_DIR)/tb.vhd +work/tb-c.o: $(BENCH_DIR)/tb-c.vhd \ + work/tb.o \ + work/tb_elem-full-c.o \ + work/tb_elem-mmc-c.o \ + work/tb_elem-sd-c.o \ + work/tb_elem-minimal-c.o + $(ANALYZE) $(BENCH_DIR)/tb-c.vhd + +work/tb_rl.o: $(BENCH_DIR)/tb_rl.vhd + $(ANALYZE) $(BENCH_DIR)/tb_rl.vhd +work/tb_rl-c.o: $(BENCH_DIR)/tb_rl-c.vhd \ + work/tb_rl.o \ + work/chip-full-c.o \ + work/card-c.o \ + work/ram_loader-c.o + $(ANALYZE) $(BENCH_DIR)/tb_rl-c.vhd + + +.PHONY: elaborate +elaborate: tb_behav_c0 tb_rl_behav_c0 + +tb_behav_c0: work/tb-c.o + $(ELABORATE) tb_behav_c0; \ + strip tb_behav_c0 + +tb_rl_behav_c0: work/tb_rl-c.o + $(ELABORATE) tb_rl_behav_c0; \ + strip tb_rl_behav_c0 + +.PHONY: analyze +analyze: work/tb-c.o work/tb_rl-c.o + +.PHONY: clean +clean: + rm -rf work tb_behav_c0 tb_rl_behav_c0 *~ diff --git a/usrp2/fpga/opencores/spi_boot/sw/CVS/Entries b/usrp2/fpga/opencores/spi_boot/sw/CVS/Entries new file mode 100644 index 00000000..0f2bd88d --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sw/CVS/Entries @@ -0,0 +1 @@ +D/misc//// diff --git a/usrp2/fpga/opencores/spi_boot/sw/CVS/Repository b/usrp2/fpga/opencores/spi_boot/sw/CVS/Repository new file mode 100644 index 00000000..98d181ec --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sw/CVS/Repository @@ -0,0 +1 @@ +spi_boot/sw diff --git a/usrp2/fpga/opencores/spi_boot/sw/CVS/Root b/usrp2/fpga/opencores/spi_boot/sw/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sw/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/sw/CVS/Template b/usrp2/fpga/opencores/spi_boot/sw/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Entries b/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Entries new file mode 100644 index 00000000..e46425fd --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Entries @@ -0,0 +1,2 @@ +/bit_reverse.c/1.1/Sun May 21 11:58:00 2006/-ko/ +D diff --git a/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Repository b/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Repository new file mode 100644 index 00000000..0519f4b5 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Repository @@ -0,0 +1 @@ +spi_boot/sw/misc diff --git a/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Root b/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Template b/usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/spi_boot/sw/misc/bit_reverse.c b/usrp2/fpga/opencores/spi_boot/sw/misc/bit_reverse.c new file mode 100644 index 00000000..9defb106 --- /dev/null +++ b/usrp2/fpga/opencores/spi_boot/sw/misc/bit_reverse.c @@ -0,0 +1,74 @@ +// Altera requires configuration bytes to be sent LSB first but the +// SD Card reads bytes MSB first +// This code reverses the bits of the altera bitstream so +// it will come out correct when read from the SD card +// $Log: bit_reverse.c,v $ +// Revision 1.1 2006/01/06 14:44:17 mbl +// initial version +// + + + +#include "stdio.h" +#include "string.h" + +FILE* fileOut; +FILE* fileIn; + +void outIOerror(char* pfn); +void inIOerror(char* pfn); + +int main(int argc, char* arg[]) +{ + unsigned char input, output; + unsigned char in_mask, out_mask; + int i; + + fileOut = fopen(arg[2],"wb"); + if (fileOut == NULL) + { + outIOerror(arg[2]); + exit(-1); + } + + printf("Opening input file %s\n", arg[1]); + fileIn = fopen(arg[1],"rb"); + if (fileIn == NULL) + { + inIOerror(arg[1]); + exit(-1); + } + + while (!feof(fileIn) && fgets((char*)&input, 2 ,fileIn) != NULL) + { + in_mask = 1; + out_mask = 0x80; + output = 0; + + for ( i=0; i < 8; ++i ) + { + if (input & in_mask) + { + output |= out_mask; + } + out_mask = out_mask >> 1; + in_mask = in_mask << 1; + } + fwrite((void*)&output,sizeof(char),1,fileOut); + } + + fclose(fileIn); + fclose(fileOut); + printf("\n%s has been created\n", arg[2]); + exit(0); +} + +void outIOerror(char *pfn) +{ + printf("I/O Error while writing to file=%s\n",pfn); +} + +void inIOerror(char *pfn) +{ + printf("I/O Error while reading file=%s\n",pfn); +} diff --git a/usrp2/fpga/opencores/uart16550/CVS/Entries b/usrp2/fpga/opencores/uart16550/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/uart16550/CVS/Entries.Log b/usrp2/fpga/opencores/uart16550/CVS/Entries.Log new file mode 100644 index 00000000..6b9716ed --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/CVS/Entries.Log @@ -0,0 +1,9 @@ +A D/Doc//// +A D/bench//// +A D/doc//// +A D/fv//// +A D/lint//// +A D/rtl//// +A D/sim//// +A D/syn//// +A D/verilog//// diff --git a/usrp2/fpga/opencores/uart16550/CVS/Repository b/usrp2/fpga/opencores/uart16550/CVS/Repository new file mode 100644 index 00000000..a210d158 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/CVS/Repository @@ -0,0 +1 @@ +uart16550 diff --git a/usrp2/fpga/opencores/uart16550/CVS/Root b/usrp2/fpga/opencores/uart16550/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/CVS/Template b/usrp2/fpga/opencores/uart16550/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/bench/CVS/Entries b/usrp2/fpga/opencores/uart16550/bench/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/uart16550/bench/CVS/Entries.Log b/usrp2/fpga/opencores/uart16550/bench/CVS/Entries.Log new file mode 100644 index 00000000..7bac3d43 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/CVS/Entries.Log @@ -0,0 +1,2 @@ +A D/verilog//// +A D/vhdl//// diff --git a/usrp2/fpga/opencores/uart16550/bench/CVS/Repository b/usrp2/fpga/opencores/uart16550/bench/CVS/Repository new file mode 100644 index 00000000..21bbf05f --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/CVS/Repository @@ -0,0 +1 @@ +uart16550/bench diff --git a/usrp2/fpga/opencores/uart16550/bench/CVS/Root b/usrp2/fpga/opencores/uart16550/bench/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/bench/CVS/Template b/usrp2/fpga/opencores/uart16550/bench/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Entries b/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Entries new file mode 100644 index 00000000..5d793ffe --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Entries @@ -0,0 +1,14 @@ +/readme.txt/1.1/Fri Jan 25 08:54:56 2002// +/uart_device.v/1.1/Sat Mar 27 03:55:16 2004// +/uart_device_utilities.v/1.1/Sat Mar 27 03:55:16 2004// +/uart_log.v/1.1/Sat Mar 27 03:55:16 2004// +/uart_test.v/1.6/Sat Mar 27 03:55:17 2004/-kb/ +/uart_testbench.v/1.1/Sat Mar 27 03:55:17 2004// +/uart_testbench_defines.v/1.1/Sat Mar 27 03:55:17 2004// +/uart_testbench_utilities.v/1.1/Sat Mar 27 03:55:17 2004// +/uart_wb_utilities.v/1.1/Sat Mar 27 03:55:17 2004// +/vapi.log/1.1/Fri Jan 25 08:54:56 2002// +/wb_mast.v/1.1/Mon Dec 3 21:44:23 2001// +/wb_master_model.v/1.1/Sat Mar 27 03:55:17 2004// +/wb_model_defines.v/1.1/Sat Mar 27 03:55:17 2004// +D diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Entries.Log b/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Entries.Log new file mode 100644 index 00000000..39baa300 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Entries.Log @@ -0,0 +1 @@ +A D/test_cases//// diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Repository b/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Repository new file mode 100644 index 00000000..1d1adf3d --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Repository @@ -0,0 +1 @@ +uart16550/bench/verilog diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Root b/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Template b/usrp2/fpga/opencores/uart16550/bench/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/readme.txt b/usrp2/fpga/opencores/uart16550/bench/verilog/readme.txt new file mode 100644 index 00000000..4eff5571 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/readme.txt @@ -0,0 +1,114 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// readme.txt //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Device interface for testing purposes //// +//// //// +//// Known problems (limits): //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created and updated: (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: readme.txt,v $ +// Revision 1.1 2002/01/25 08:54:56 mohor +// UART PHY added. Files are fully operational, working on HW. +// +// +// +// +// + + +Following files are making an UART16550 PHY and are used for testing: + +uart_device_if_defines.v - defines related to PHY +uart_device_if_memory.v - Module for initializing PHY (reading commands from vapi.log file) +uart_device_if.v - Uart PHY with additional feature for testing +vapi.log - File with commands (expected data, data to be send, etc.) +readme.txt - This file + + + + +OPERATION: +uart_device_if.v is a uart PHY and connects to the uart_top.v. PHY takes commands from vapi.log +file. Depending on command it can: +- set a mode (5, 6, 7, 8-bit, parity, stop bits, etc.) +- set a frequency divider (dll) +- send a character +- receive a character and compare it to the expected one +- send a glitch (after a certain period of time) +- send a break +- detect a break +- Check if fifo is empty/not empty (and generate an error if expected value differs from actual) +- delay (does nothing for certain number of characters) + +On the other side of uart some kind of host must be connected that controls the phy. + +This is the structure: + + + |||||||||||||| |||||||||||||||| |||||||||||||||| + | | | | | | + | Host | <----------> | UART | <----------> | PHY | + | | | | | | + |||||||||||||| |||||||||||||||| |||||||||||||||| + + + PHY must know how host sets th UART and work in the same mode. Besides that it must know what + host is sending or expecting to receive. Operation of the PHY must be written in the vapi.log + file. + + When I was using this testing environment, I used OpenRISC1200 as a host. Everything is fully + operational. UART was also tested in hardware (on two different boards), running uCLinux in + both, interrupt and polling mode. + + \ No newline at end of file diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Entries b/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Entries new file mode 100644 index 00000000..cb555d8d --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Entries @@ -0,0 +1,2 @@ +/uart_int.v/1.1/Sat Mar 27 04:04:57 2004// +D diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Repository b/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Repository new file mode 100644 index 00000000..56b75644 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Repository @@ -0,0 +1 @@ +uart16550/bench/verilog/test_cases diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Root b/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Template b/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/uart_int.v b/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/uart_int.v new file mode 100755 index 00000000..21ff66d2 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/test_cases/uart_int.v @@ -0,0 +1,279 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_int.v //// +//// //// +//// This file is part of the "uart16550" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Author(s): //// +//// - tadej@opencores.org (Tadej Markovic) //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_int.v,v $ +// Revision 1.1 2004/03/27 04:04:57 tadejm +// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. +// +// +// + + +`include "uart_defines.v" +`include "uart_testbench_defines.v" +`include "timescale.v" + +module testcase; + + +// Testcase INDEPENDENT code - common to all testcases +//##################################################### + + // Variables + // Testbench reporting events & signals + event severe_err_event; + event err_event; + event wrn_event; + event msg_event; + event val_event; + event testbench_log_written; + reg [7999: 0] tim; + reg [7999: 0] severe_err_msg; + reg [7999: 0] msg; + integer val; + // Testcase reporting events & signals + event testcase_log_written; + event test_end; + reg [1599: 0] test_name; + reg error_detected; + + // Module for writing to log files + uart_log log (); + defparam log.testcase_name = "uart_interrupts"; + + // Log + initial + fork + begin: init_log + reg ok; + // Delay allows all other blocks in this fork - join block to execute + #1; + log.start_log(ok); + if (ok !== 1'b1) + begin + `SEVERE_ERROR("Failed to open log file(s)!"); + disable init_log; + end + testcase_init; + testcase_test; + log.end_log; + # 100; + $finish; + end + begin + forever + begin + @(test_name); + error_detected = 1'b0; + log.report_test_name(test_name); + log.verbose_test_name(test_name); + -> testcase_log_written; + end + end + begin + forever + begin + @(test_end); + if (error_detected) + begin + log.tests_failed = log.tests_failed + 1'b1; + end + else + begin + log.tests_ok = log.tests_ok + 1'b1; + log.report_test_ok; + end + -> testcase_log_written; + end + end + begin + @(severe_err_event); + error_detected = 1'b1; + -> test_end; + @(testcase_log_written); + log.report_test_failed(severe_err_msg); + if (testcase.log.free == 0) + begin + wait (testcase.log.free); + severe_err_msg = "Failed to write to log file(s)!"; + end + log.verbose_severe_err(tim, severe_err_msg); + -> testbench_log_written; + # 100; $finish; + end + begin + forever + begin + @(err_event); + error_detected = 1'b1; + -> test_end; + @(testcase_log_written); + log.report_test_failed(msg); + if (testcase.log.free == 0) + begin + `SEVERE_ERROR("Failed to write to log file(s)!"); + end + log.verbose_err(tim, msg); + -> testbench_log_written; + `PROMPT; + end + end + begin + forever + begin + @(wrn_event); + if (testcase.log.free == 0) + begin + `SEVERE_ERROR("Failed to write to log file(s)!"); + end + log.verbose_wrn(tim, msg); + -> testbench_log_written; + end + end + begin + forever + begin + @(msg_event); + if (testcase.log.free == 0) + begin + `SEVERE_ERROR("Failed to write to log file(s)!"); + end + log.verbose_msg(tim, msg); + -> testbench_log_written; + end + end + begin + forever + begin + @(val_event); + if (testcase.log.free == 0) + begin + `SEVERE_ERROR("Failed to write to log file(s)!"); + end + log.verbose_val(tim, msg, val); + -> testbench_log_written; + end + end + join + + +// Testcase (DEPENDENT) code +//########################### + + // Initialization + task testcase_init; + begin:init + test_name = "Initialization of UART."; + @(testcase_log_written); + // + testbench_utilities.do_reset; + testbench_utilities.disable_clk_generators(1, 1, 1, 1); + testbench_utilities.set_device_tx_rx_clk_divisor(32'h1000); + testbench_utilities.set_wb_clock_period(100); + testbench_utilities.enable_clk_generators(1, 1, 1, 1); + #100; + testbench_utilities.release_reset; + // + uart_wb_utilities.write_dlr(16'h1000); + uart_wb_utilities.write_ier(8'h07); + uart_wb_utilities.write_fcr(8'hC0); + uart_wb_utilities.write_lcr(8'h03); + // + uart_device_utilities.set_rx_length(8); + uart_device_utilities.disable_rx_parity; + uart_device_utilities.set_rx_second_stop_bit(0); + // + uart_device_utilities.set_tx_length(8); + uart_device_utilities.disable_tx_parity; + uart_device_utilities.correct_tx_parity; + uart_device_utilities.correct_tx_frame; + uart_device_utilities.generate_tx_glitch(0); + + -> test_end; + @(testcase_log_written); + end + endtask // testcase_init + + // Testcase + task testcase_test; + begin:test + test_name = "Interrupt test."; + @(testcase_log_written); + fork + begin: test + uart_wb_utilities.write_char(8'hAA); + @(testbench.int_aserted); + `TC_MSG("INT ASSERTED!"); + uart_wb_utilities.write_char(8'hAA); + @(testbench.int_released); + `TC_MSG("INT RELEASED!"); + @(testbench.int_aserted); + `TC_MSG("INT ASSERTED!"); + uart_wb_utilities.read_iir; + @(testbench.int_released); + `TC_MSG("INT RELEASED!"); + end + begin: wait_end + @(testbench.i_uart_device.device_received_packet); + @(testbench.i_uart_device.device_received_packet); + repeat(2) @(testbench.i_uart_device.rx_clk); + disable test; + disable wait_clk; + end + begin: wait_clk + testbench_utilities.wait_for_num_of_wb_clk(32'h450000); + disable test; + disable wait_end; + end + join + repeat (4) @(posedge testbench.wb_clk); + # 100; + + -> test_end; + @(testcase_log_written); + end + endtask // testcase_test + + +endmodule + diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/uart_device.v b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_device.v new file mode 100644 index 00000000..01e971fb --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_device.v @@ -0,0 +1,717 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_device.v //// +//// //// +//// This file is part of the "uart16550" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Author(s): //// +//// - tadej@opencores.org (Tadej Markovic) //// +//// - igorm@opencores.org (Igor Mohor) //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_device.v,v $ +// Revision 1.1 2004/03/27 03:55:16 tadejm +// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. +// +// +// + + +`include "uart_testbench_defines.v" +`include "timescale.v" + +module uart_device +( + // UART signals + stx_i, + srx_o, + // Modem signals + rts_i, + cts_o, + dtr_i, + dsr_o, + ri_o, + dcd_o +); + + +// IN/OUT signals +//############### + + // UART signals + input stx_i; + output srx_o; + // Modem signals + input rts_i; + output cts_o; + input dtr_i; + output dsr_o; + output ri_o; + output dcd_o; + + +// INTERNAL signals +//################# + + + // Clock generation signals + //######################### + + // Operational and transmission clock signals + reg rx_clk; // RX device clock with period T_clk_period (should be equal to wb_clk_period) + reg tx_clk; // TX device clock with period (T_clk_period + T_clk_delay) + reg tx_clk_divided; // divided TX device clock with period ((T_clk_period + T_clk_delay) * T_divisor * 16) + // Clock enable signals + reg rx_clk_en = 1'b1; + reg tx_clk_en = 1'b1; + reg tx_clk_divided_en = 1'b1; + // Clock period variables + real T_clk_period = 20; + real T_clk_delay = 0; + integer T_divisor = 5; + + + // IN/OUT assignment signals + //########################## + + // Modem signals + wire rts; + wire dtr; + + + // UART receiver signals + //###################### + + // RX packet control signals + wire rx; + reg [3:0] rx_length; + reg rx_odd_parity; + reg rx_even_parity; + reg rx_stick1_parity; + reg rx_stick0_parity; + reg rx_parity_enabled; + reg rx_stop_bit_1; + reg rx_stop_bit_1_5; + reg rx_stop_bit_2; + // RX logic signals + wire [3:0] rx_total_length; + wire [5:0] rx_break_detection_length; + reg rx_packet_end; + reg rx_packet_end_q; + reg rx_clk_cnt_en; + reg [31:0] rx_clk_cnt; + reg rx_sample_clock; + integer rx_bit_index; + integer rx_stop_bit_index; + reg [7:0] rx_data; + reg [1:0] rx_stop; + reg rx_framing_error; + reg rx_parity; + reg rx_parity_error; + reg rx_break_detected; + reg rx_break_detected_q; + reg [31:0] rx_break_cnt; + // RX events + event device_received_packet; + event device_received_last_bit; + event device_received_stop_bit; + event device_detected_rx_break; + + + // UART transmitter signals + //######################### + + // TX packet control signals + reg tx; + reg [3:0] tx_length; + reg tx_odd_parity; + reg tx_even_parity; + reg tx_stick1_parity; + reg tx_stick0_parity; + reg tx_parity_enabled; + reg tx_parity_wrong; + reg tx_framing_wrong; + // TX logic signals + reg [23:0] tx_glitch_num; + reg start_tx_glitch_cnt; + reg [31:0] tx_glitch_cnt; + reg tx_glitch; + reg tx_break_enable; + reg [15:0] tx_break_num; + reg start_tx_break_cnt; + reg [31:0] tx_break_cnt; + reg tx_break; + // TX test signals + reg [7:0] sent_data; + reg tx_accept_next_framing_err; + reg tx_framing_err; + reg tx_framing_glitch_err; + // TX events + event device_sent_packet; + event sent_packet_received; + + +// Clock generation +//################# + + // Example of TESTBENCH's task for setting UART clock period: + // ---------------- + // task set_uart_clk_period; + // input [31:0] clk_period; + // begin + // //@(posedge testbench.uart_device.clk); + // testbench.uart_device.T_clk_period = clk_period; + // end + // endtask // set_uart_clk_period + // ---------------- + // Example of TESTBENCH's task for setting UART clock rising edge + // delayed for time_delay_i after WB clock rising edge: + // ---------------- + // task uart_clk_follows_wb_clk; + // input [31:0] time_delay_i; + // integer time_delay; + // begin + // time_delay = time_delay_i; + // @(posedge testbench.uart_device.clk); + // testbench.uart_device.clk_en = 1'b0; + // @(posedge wb_clk); + // #time_delay testbench.uart_device.clk = 1'b1; + // testbench.uart_device.clk_en = 1'b1; + // end + // endtask // uart_clk_follows_wb_clk + // ---------------- + + // rx_clk rising edge + always@(posedge rx_clk) + if (rx_clk_en) + #(T_clk_period / 2) rx_clk = 1'b0; + // rx_clk falling edge + always@(negedge rx_clk) + if (rx_clk_en) + #(T_clk_period / 2) rx_clk = 1'b1; + + // tx_clk rising edge + always@(posedge tx_clk) + if (tx_clk_en) + #((T_clk_period + T_clk_delay) / 2) tx_clk = 1'b0; + // tx_clk falling edge + always@(negedge tx_clk) + if (tx_clk_en) + #((T_clk_period + T_clk_delay) / 2) tx_clk = 1'b1; + + // tx_clk_divided rising edge + always@(posedge tx_clk_divided) + if (tx_clk_divided_en) + #(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) tx_clk_divided = 1'b0; + // tx_clk_divided falling edge + always@(negedge tx_clk_divided) + if (tx_clk_divided_en) + #(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) tx_clk_divided = 1'b1; + + // Inital CLK values + initial + begin:device + rx_clk = 1'b0; + tx_clk = 1'b0; + tx_clk_divided = 1'b0; + end + + +// IN/OUT assignments +//################### + + // UART output + assign srx_o = (tx ^ tx_glitch) & ~tx_break; + // Modem output + assign cts_o = 0; + assign dsr_o = 0; + assign ri_o = 0; + assign dcd_o = 0; + // UART input + assign rx = stx_i; + // Modem input + assign rts = rts_i; + assign dtr = dtr_i; + + +// UART receiver +//############## + + // Initial values for RX + initial + begin + // Default LENGTH + rx_length = 8; + // Default PARITY + rx_odd_parity = 1'b0; + rx_even_parity = 1'b0; + rx_stick1_parity = 1'b0; + rx_stick0_parity = 1'b0; + rx_parity_enabled = 1'b0; + // Default STOP + rx_stop_bit_1 = 1'b1; + rx_stop_bit_1_5 = 1'b0; + rx_stop_bit_2 = 1'b0; + end + + // Total length of RX packet (for proper generation of the rx_packet_end signal): + // data length + parity + 1 stop bit + second stop bit (when enabled) + assign rx_total_length = rx_length + rx_parity_enabled + 1 + rx_stop_bit_2; + // +1 is used because start bit was not included in rx_total_length. + assign rx_break_detection_length = rx_total_length + 1; + + // Generating rx_clk_cnt_en signal. + always@(posedge rx_clk) + begin + if (~rx_clk_cnt_en) + begin + wait (~rx); + end + rx_clk_cnt_en = 1; + rx_packet_end = 0; + wait (rx_packet_end); + rx_clk_cnt_en = 0; + wait (rx); // Must be high to continue, because of break condition + end + + // Counter used in data reception + always@(posedge rx_clk) + begin + if (rx_clk_cnt_en) + begin + if (rx_clk_cnt == (8 * T_divisor - 1) & rx) // False start bit detection + rx_packet_end = 1; + if (rx_clk_cnt_en) // Checking is still enabled after devisor clocks + rx_clk_cnt <= #1 rx_clk_cnt + 1; + else + rx_clk_cnt <= #1 0; + end + else + rx_clk_cnt <= #1 0; + end + + // Delayed rx_packet_end signal + always@(posedge rx_clk) + rx_packet_end_q = rx_packet_end; + + // Generating sample clock and end of the frame (Received data is sampled with this clock) + always@(posedge rx_clk) + begin + if (rx_clk_cnt == 8 * T_divisor - 1) + rx_bit_index = 0; + else if (rx_clk_cnt == (8 * T_divisor + 16 * T_divisor * (rx_bit_index + 1) - 1)) + begin + rx_sample_clock = 1; + rx_bit_index = rx_bit_index + 1; + if (rx_bit_index == rx_total_length) + rx_packet_end = 1; + end + else + rx_sample_clock = 0; + end + + // Sampling data (received data) + always@(posedge rx_clk) + begin + if (rx_sample_clock) + begin + if (rx_bit_index <= rx_length) // Sampling data + begin + rx_stop_bit_index <= 0; // Stop bit index reset at the beginning of the data stage +// $display("\t\t\t\t\t\t\t(rx_bit_index = %0d) Reading data bits = %0x", rx_bit_index, rx); + rx_data[rx_bit_index - 1] = rx; + if (rx_bit_index == rx_length) + -> device_received_last_bit; + end + else + begin + if (rx_bit_index == (rx_length + 1)) + begin + if (rx_parity_enabled) + begin +// $display("\t\t\t\t\t\t\t(rx_bit_index = %0d) Reading parity bits = %0x", rx_bit_index, rx); + end + else + begin + -> device_received_stop_bit; + rx_stop[rx_stop_bit_index] = rx; + rx_stop_bit_index <= rx_stop_bit_index + 1; + end + rx_parity = rx & rx_parity_enabled; + end + if (rx_bit_index >= (rx_length + 1 + rx_parity_enabled)) + begin +// $display("\t\t\t\t\t\t\t(rx_bit_index = %0d) Reading stop bits = %0x", rx_bit_index, rx); + rx_stop[rx_stop_bit_index] = rx; + rx_stop_bit_index <= rx_stop_bit_index + 1; + end + end + end + + // Filling the rest of the data with 0 + if (rx_length == 5) + rx_data[7:5] = 0; + if (rx_length == 6) + rx_data[7:6] = 0; + if (rx_length == 7) + rx_data[7] = 0; + + // Framing error generation + // When 1 or 1.5 stop bits are used, only first stop bit is checked + rx_framing_error = (rx_stop_bit_1 | rx_stop_bit_1_5) ? ~rx_stop[0] : ~(&rx_stop[1:0]); + + // Parity error generation + if (rx_odd_parity) + rx_parity_error = ~(^{rx_data, rx_parity}); + else if (rx_even_parity) + rx_parity_error = ^{rx_data, rx_parity}; + else if (rx_stick0_parity) + rx_parity_error = rx_parity; + else if (rx_stick1_parity) + rx_parity_error = ~rx_parity; + else + rx_parity_error = 0; + end + + // Break detection + always@(posedge rx_clk) + begin + rx_break_detected_q <= rx_break_detected; + if (rx) + begin + rx_break_cnt = 0; // Reseting counter + rx_break_detected = 0; // Clearing break detected signal + end + else + rx_break_cnt = rx_break_cnt + 1; + if (rx_break_cnt == rx_break_detection_length * 16 * T_divisor) + begin +// $display("\n(%0t) Break_detected.", $time); + rx_break_detected <= 1; + -> device_detected_rx_break; + end + end + + // Writing received data + always@(posedge rx_clk) + begin + if ((rx_packet_end & ~rx_packet_end_q) | (rx_break_detected & ~rx_break_detected_q)) + begin + wait (rx | rx_break_detected); // Waiting for "end of cycle detected" or "break to be activated" + // rx_break_detected + // rx_length + // rx_parity_enabled + // rx_odd_parity | rx_even_parity | rx_stick1_parity | rx_stick0_parity + // rx_stop_bit_1 | rx_stop_bit_1_5 | rx_stop_bit_2 + -> device_received_packet; + end + end + + +// UART transmitter +//################# + + // Initial values for TX + initial + begin + // Default LENGTH + tx_length = 8; + // Default PARITY + tx_odd_parity = 1'b0; + tx_even_parity = 1'b0; + tx_stick1_parity = 1'b0; + tx_stick0_parity = 1'b0; + tx_parity_enabled = 1'b0; + // Default CORRECT PARITY + tx_parity_wrong = 1'b0; + // Default CORRECT FRAME + tx_framing_wrong = 1'b0; + tx_framing_err = 0; + tx_framing_glitch_err = 0; + // Default NO GLITCH + tx_glitch_num = 24'h0; + // Default NO BREAK + tx_break_enable = 1'b0; + tx_break_num = 16'h0; + end + + // Counter for TX glitch generation + always@(posedge tx_clk or posedge start_tx_glitch_cnt) + begin + if (start_tx_glitch_cnt) + begin + tx_glitch_cnt <= tx_glitch_cnt + 1; + if (tx_glitch_cnt == ((tx_glitch_num - 1) * T_divisor)) + tx_glitch = 1'b1; + else if (tx_glitch_cnt == (tx_glitch_num * T_divisor)) + begin + tx_glitch = 1'b0; + start_tx_glitch_cnt = 1'b0; + end + end + else + tx_glitch_cnt <= 0; + end + + // Break setting & break counter + always@(posedge tx_clk) + begin + if (tx_break_enable && (tx_break_cnt == (tx_break_num * T_divisor))) + begin + start_tx_break_cnt = 0; + end + else if (start_tx_break_cnt) + begin + tx_break_cnt = tx_break_cnt + 1; + tx_break = 1; + end + else + begin + tx_break_cnt = 0; + tx_break = 0; + end + end + + // Sending packets + task send_packet; + input tx_random_i; + input [7:0] tx_data_i; + input num_of_tx_data_i; + reg [7:0] tx_data; + reg tx_parity_xor; + integer tx_bit_index; + integer num_of_tx_data; + reg last_tx_data; + begin + // SEVERE ERROR + if (// WRONG combinations of parameters for testing + ((T_clk_delay != 0) && (tx_parity_wrong || tx_framing_wrong)) || + ((T_clk_delay != 0) && (tx_glitch_num != 0)) || + ((T_clk_delay != 0) && (tx_break_enable)) || + ((tx_parity_wrong || tx_framing_wrong) && (tx_glitch_num != 0)) || + ((tx_parity_wrong || tx_framing_wrong) && (tx_break_enable)) || + ((tx_glitch_num != 0) && (tx_break_enable)) || + (tx_glitch_num > ((tx_length + 2'h2 + tx_parity_enabled) * 16 * T_divisor)) || // with STOP bit +// (tx_glitch_num > ((tx_length + 2'h1 + tx_parity_enabled) * 16 * T_divisor)) || // without STOP bit + // WRONG input parameters + (num_of_tx_data_i == 0) || + ((num_of_tx_data_i > 1) && tx_break_enable) + ) + begin + `SEVERE_ERROR("WRONG combination of parameters for testing UART receiver"); + end + + for (num_of_tx_data = 0; + num_of_tx_data < num_of_tx_data_i; + num_of_tx_data = (num_of_tx_data + 1'b1)) + begin + + if (num_of_tx_data == (num_of_tx_data_i - 1'b1)) + last_tx_data = 1'b1; + else + last_tx_data = 0; + + // TX data + if (~tx_random_i) + tx_data = tx_data_i; + else + tx_data = {$random}%256; // 0..255 + + // Sending start bit + @(posedge tx_clk_divided); + tx = 0; + if (tx_glitch_num > 0) + start_tx_glitch_cnt = 1; // enabling tx_glitch generation + if (tx_break_enable) + start_tx_break_cnt = 1; // Start counter that counts break tx_length + // Wait for almost 1 bit + #(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period + #((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period + + // Sending tx_data bits + for (tx_bit_index = 0; tx_bit_index < tx_length; tx_bit_index = tx_bit_index + 1) + begin + @(posedge tx_clk_divided); + tx = tx_data[tx_bit_index]; + end + // Wait for almost 1 bit + #(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period + #((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period + + sent_data = tx_data; + + // Calculating parity + if(tx_length == 5) + begin + tx_parity_xor = ^tx_data[4:0]; + end + else if(tx_length == 6) + begin + tx_parity_xor = ^tx_data[5:0]; + end + else if(tx_length == 7) + begin + tx_parity_xor = ^tx_data[6:0]; + end + else if(tx_length == 8) + begin + tx_parity_xor = ^tx_data[7:0]; + end + else + $display("WRONG length of TX data packet"); + + // Sending parity bit + if (tx_parity_enabled) + begin + @(posedge tx_clk_divided); + if (tx_odd_parity) + tx = tx_parity_wrong ^ (~tx_parity_xor); + else if (tx_even_parity) + tx = tx_parity_wrong ^ tx_parity_xor; + else if (tx_stick1_parity) + tx = tx_parity_wrong ^ 1; + else if (tx_stick0_parity) + tx = tx_parity_wrong ^ 0; + // Wait for almost 1 bit + #(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period + #((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period + end + + // Sending stop bit + if (~tx_framing_wrong || + (tx_glitch_num != ((((tx_length + 2'h2 + tx_parity_enabled) * 2) - 1'b1) * 8 * T_divisor))) + begin + @(posedge tx_clk_divided); + tx = 1; + // Wait for almost 1 bit + #(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period + #((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period + -> device_sent_packet; + @(sent_packet_received); + end + else if (~tx_framing_wrong || + (tx_glitch_num == ((((tx_length + 2'h2 + tx_parity_enabled) * 2) - 1'b1) * 8 * T_divisor))) + begin + @(posedge tx_clk_divided); + tx = 1; + // Wait for 1 bit + @(posedge tx_clk_divided); // this will be like 2. stop bit + -> device_sent_packet; + @(sent_packet_received); + end + else if (tx_framing_wrong && last_tx_data) + begin + @(posedge tx_clk_divided); + // Wrong stop | start bit + tx = 0; + @(posedge tx_clk_divided); + -> device_sent_packet; + @(sent_packet_received); + tx_framing_wrong = 0; + // TX data + tx = 1; + tx_data = 8'hFF; + // Sending tx_data bits + for (tx_bit_index = 0; tx_bit_index < tx_length; tx_bit_index = tx_bit_index + 1) + begin + @(posedge tx_clk_divided); + tx = tx_data[tx_bit_index]; + end + // Wait for almost 1 bit + #(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period + #((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period + + sent_data = tx_data; + + // Calculating parity + if(tx_length == 5) + begin + tx_parity_xor = ^tx_data[4:0]; + end + else if(tx_length == 6) + begin + tx_parity_xor = ^tx_data[5:0]; + end + else if(tx_length == 7) + begin + tx_parity_xor = ^tx_data[6:0]; + end + else if(tx_length == 8) + begin + tx_parity_xor = ^tx_data[7:0]; + end + else + $display("WRONG length of TX data packet"); + + // Sending parity bit + if (tx_parity_enabled) + begin + @(posedge tx_clk_divided); + if (tx_odd_parity) + tx = tx_parity_wrong ^ (~tx_parity_xor); + else if (tx_even_parity) + tx = tx_parity_wrong ^ tx_parity_xor; + else if (tx_stick1_parity) + tx = tx_parity_wrong ^ 1; + else if (tx_stick0_parity) + tx = tx_parity_wrong ^ 0; + // Wait for almost 1 bit + #(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period + #((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period + end + + // Stop bit + @(posedge tx_clk_divided); + tx = 1; + // Wait for almost 1 bit + #(((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor); // wait half period + #((((T_clk_period + T_clk_delay) / 2) * 16 * T_divisor) - 2); // wait 2 less than half period + -> device_sent_packet; + @(sent_packet_received); + tx_framing_wrong = 1'b1; + end + else if (last_tx_data) + begin + @(posedge tx_clk_divided); + -> device_sent_packet; + @(sent_packet_received); + end + end + end + endtask // send_packet + + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/uart_device_utilities.v b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_device_utilities.v new file mode 100644 index 00000000..813929b7 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_device_utilities.v @@ -0,0 +1,323 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_device_utilities.v //// +//// //// +//// This file is part of the "uart16550" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Author(s): //// +//// - tadej@opencores.org (Tadej Markovic) //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_device_utilities.v,v $ +// Revision 1.1 2004/03/27 03:55:16 tadejm +// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. +// +// +// + + +`include "uart_defines.v" +`include "uart_testbench_defines.v" +`include "wb_model_defines.v" +`include "timescale.v" + +module uart_device_utilities; + +// UART receiver setting TASKs +//############################ + + // Set RX length + task set_rx_length; + input [3:0] len; + begin + `UTILS_MSG("SETTING RX CHAR length."); + testbench.i_uart_device.rx_length = len; + `UTILS_VAL1("Length:", len); + end + endtask // set_rx_length + + // Enable RX odd parity + task enable_rx_odd_parity; + begin + `UTILS_MSG("ENABLING RX CHAR odd parity."); + testbench.i_uart_device.rx_odd_parity = 1'b1; + testbench.i_uart_device.rx_even_parity = 1'b0; + testbench.i_uart_device.rx_stick1_parity = 1'b0; + testbench.i_uart_device.rx_stick0_parity = 1'b0; + testbench.i_uart_device.rx_parity_enabled = 1'b1; + end + endtask // enable_rx_odd_parity + + // Enable RX even parity + task enable_rx_even_parity; + begin + `UTILS_MSG("ENABLING RX CHAR even parity."); + testbench.i_uart_device.rx_odd_parity = 1'b0; + testbench.i_uart_device.rx_even_parity = 1'b1; + testbench.i_uart_device.rx_stick1_parity = 1'b0; + testbench.i_uart_device.rx_stick0_parity = 1'b0; + testbench.i_uart_device.rx_parity_enabled = 1'b1; + end + endtask // enable_rx_even_parity + + // Enable RX stick1 parity + task enable_rx_stick1_parity; + begin + `UTILS_MSG("ENABLING RX CHAR stick1 parity."); + testbench.i_uart_device.rx_odd_parity = 1'b0; + testbench.i_uart_device.rx_even_parity = 1'b0; + testbench.i_uart_device.rx_stick1_parity = 1'b1; + testbench.i_uart_device.rx_stick0_parity = 1'b0; + testbench.i_uart_device.rx_parity_enabled = 1'b1; + end + endtask // enable_rx_stick1_parity + + // Enable RX stick0 parity + task enable_rx_stick0_parity; + begin + `UTILS_MSG("ENABLING RX CHAR stick0 parity."); + testbench.i_uart_device.rx_odd_parity = 1'b0; + testbench.i_uart_device.rx_even_parity = 1'b0; + testbench.i_uart_device.rx_stick1_parity = 1'b0; + testbench.i_uart_device.rx_stick0_parity = 1'b1; + testbench.i_uart_device.rx_parity_enabled = 1'b1; + end + endtask // enable_rx_stick0_parity + + // Disable RX parity + task disable_rx_parity; + begin + `UTILS_MSG("DISABLING RX CHAR parity."); + testbench.i_uart_device.rx_odd_parity = 1'b0; + testbench.i_uart_device.rx_even_parity = 1'b0; + testbench.i_uart_device.rx_stick1_parity = 1'b0; + testbench.i_uart_device.rx_stick0_parity = 1'b0; + testbench.i_uart_device.rx_parity_enabled = 1'b0; + end + endtask // disable_rx_parity + + // Set 1 or 2 (1.5) RX stop bits + task set_rx_second_stop_bit; + input second_stop_bit; + begin + if (~second_stop_bit) + begin + `UTILS_MSG("SETTING RX CHAR 1 stop bit."); + end + else if (second_stop_bit && (testbench.i_uart_device.rx_length == 5)) + begin + `UTILS_MSG("SETTING RX CHAR 1.5 stop bit."); + end + else + begin + `UTILS_MSG("SETTING RX CHAR 2 stop bits."); + end + testbench.i_uart_device.rx_stop_bit_1 = ~second_stop_bit; + testbench.i_uart_device.rx_stop_bit_1_5 = second_stop_bit & (testbench.i_uart_device.rx_length == 5); + testbench.i_uart_device.rx_stop_bit_2 = second_stop_bit & (testbench.i_uart_device.rx_length != 5); + end + endtask // set_rx_second_stop_bit + +// UART transmitter setting TASKs +//############################### + + // Set TX length + task set_tx_length; + input [3:0] len; + begin + `UTILS_MSG("SETTING TX CHAR length."); + testbench.i_uart_device.tx_length = len; + `UTILS_VAL1("Length:", len); + end + endtask // set_tx_length + + // Enable TX odd parity + task enable_tx_odd_parity; + begin + `UTILS_MSG("ENABLING TX CHAR odd parity."); + testbench.i_uart_device.tx_odd_parity = 1'b1; + testbench.i_uart_device.tx_even_parity = 1'b0; + testbench.i_uart_device.tx_stick1_parity = 1'b0; + testbench.i_uart_device.tx_stick0_parity = 1'b0; + testbench.i_uart_device.tx_parity_enabled = 1'b1; + end + endtask // enable_tx_odd_parity + + // Enable TX even parity + task enable_tx_even_parity; + begin + `UTILS_MSG("ENABLING TX CHAR even parity."); + testbench.i_uart_device.tx_odd_parity = 1'b0; + testbench.i_uart_device.tx_even_parity = 1'b1; + testbench.i_uart_device.tx_stick1_parity = 1'b0; + testbench.i_uart_device.tx_stick0_parity = 1'b0; + testbench.i_uart_device.tx_parity_enabled = 1'b1; + end + endtask // enable_tx_even_parity + + // Enable TX stick1 parity + task enable_tx_stick1_parity; + begin + `UTILS_MSG("ENABLING TX CHAR stick1 parity."); + testbench.i_uart_device.tx_odd_parity = 1'b0; + testbench.i_uart_device.tx_even_parity = 1'b0; + testbench.i_uart_device.tx_stick1_parity = 1'b1; + testbench.i_uart_device.tx_stick0_parity = 1'b0; + testbench.i_uart_device.tx_parity_enabled = 1'b1; + end + endtask // enable_tx_stick1_parity + + // Enable TX stick0 parity + task enable_tx_stick0_parity; + begin + `UTILS_MSG("ENABLING TX CHAR stick0 parity."); + testbench.i_uart_device.tx_odd_parity = 1'b0; + testbench.i_uart_device.tx_even_parity = 1'b0; + testbench.i_uart_device.tx_stick1_parity = 1'b0; + testbench.i_uart_device.tx_stick0_parity = 1'b1; + testbench.i_uart_device.tx_parity_enabled = 1'b1; + end + endtask // enable_tx_stick0_parity + + // Disable TX parity + task disable_tx_parity; + begin + `UTILS_MSG("DISABLING TX CHAR parity."); + testbench.i_uart_device.tx_odd_parity = 1'b0; + testbench.i_uart_device.tx_even_parity = 1'b0; + testbench.i_uart_device.tx_stick1_parity = 1'b0; + testbench.i_uart_device.tx_stick0_parity = 1'b0; + testbench.i_uart_device.tx_parity_enabled = 1'b0; + end + endtask // disable_tx_parity + + // Correct TX parity + task correct_tx_parity; + begin + `UTILS_MSG("DISABLING WRONG parity generation."); + testbench.i_uart_device.tx_parity_wrong = 1'b0; + end + endtask // correct_tx_parity + + // Wrong TX parity + task wrong_tx_parity; + begin + `UTILS_MSG("ENABLING WRONG parity generation."); + testbench.i_uart_device.tx_parity_wrong = 1'b1; + end + endtask // wrong_tx_parity + + // Correct TX frame + task correct_tx_frame; + begin + `UTILS_MSG("DISABLING WRONG frame generation."); + testbench.i_uart_device.tx_framing_wrong = 1'b0; + end + endtask // correct_tx_frame + + // Wrong TX frame + task wrong_tx_frame; + begin + `UTILS_MSG("ENABLING WRONG frame generation."); + testbench.i_uart_device.tx_framing_wrong = 1'b1; + end + endtask // wrong_tx_frame + + // Generate TX glitch + task generate_tx_glitch; + input [23:0] generate_glitch_num; + begin + if (generate_glitch_num == 0) + begin + `UTILS_MSG("DISABLING 1 TIME glitch generation with CLKs delay."); + end + else + begin + `UTILS_MSG("ENABLING 1 TIME glitch generation with CLKs delay."); + end + testbench.i_uart_device.tx_glitch_num = generate_glitch_num; + `UTILS_VAL1("CLKs delay from start bit edge:", generate_glitch_num); + end + endtask // generate_tx_glitch + + // Enable TX break + task enable_tx_break; + input [15:0] break_num; + begin + `UTILS_MSG("ENABLING brake generation with each TX CHAR with brake length."); + testbench.i_uart_device.tx_break_enable = 1'b1; + testbench.i_uart_device.tx_break_num = break_num; + `UTILS_VAL1("Brake bit length:", break_num); + end + endtask // enable_tx_break + + // Disable TX break + task disable_tx_break; + begin + `UTILS_MSG("DISABLING brake generation with each TX CHAR."); + testbench.i_uart_device.tx_break_enable = 1'b0; + end + endtask // disable_tx_break + +// UART transmitter send TASKs +//############################ + + // Send character + task send_char; + input [7:0] char; + begin + testbench.i_uart_device.send_packet(1'b0, char, 1); + end + endtask // Send character + + // Send random character + task send_rnd_char; + begin + testbench.i_uart_device.send_packet(1'b1, 8'h0, 1); + end + endtask // send_rnd_char + + // Send burst random character + task send_burst_rnd_char; + input [31:0] num_of_char; + integer i; + begin + testbench.i_uart_device.send_packet(1'b1, 8'h0, num_of_char); + end + endtask // send_burst_rnd_char + + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/uart_log.v b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_log.v new file mode 100644 index 00000000..0e87b9da --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_log.v @@ -0,0 +1,209 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_log.v //// +//// //// +//// This file is part of the "uart16550" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc, mihad@opencores.org //// +//// - Tadej Markovic, tadejm@opencores.org //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org //// +//// Tadej Markovic, tadejm@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_log.v,v $ +// Revision 1.1 2004/03/27 03:55:16 tadejm +// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module uart_log; + + +parameter testcase_name = ""; + +integer report_log_file_desc; +integer verbose_log_file_desc; + +reg free; +integer tests_ok; +integer tests_failed; + +initial free = 1; +initial tests_ok = 0; +initial tests_failed = 0; + +task start_log; + output ok_o; +begin + report_log_file_desc = $fopen({"../log/", testcase_name, "_report.log"}); + verbose_log_file_desc = $fopen({"../log/", testcase_name, "_verbose.log"}); + if ((report_log_file_desc == 0) || (verbose_log_file_desc == 0)) + ok_o = 1'b0; + else + ok_o = 1'b1; +end +endtask // start_log + +task end_log; +begin + report_add_delimiter; + $fdisplay(report_log_file_desc, "TEST CASE execution summary:"); + $fdisplay(report_log_file_desc, "Number of tests PASSED=%0d", tests_ok); + $fdisplay(report_log_file_desc, "Number of tests FAILED=%0d", tests_failed); + $fdisplay(report_log_file_desc, " Simulation End Time: %t", $time); + report_add_delimiter; + $fclose(report_log_file_desc); + $fclose(verbose_log_file_desc); +end +endtask // end_log + +task report_test_name; + input [1599:0] test_i; +begin + report_add_delimiter; + $fdisplay(report_log_file_desc, "%0s", test_i); +end +endtask // report_test_name + +task report_test_failed; + input [7999:0] message_i; +begin + $fdisplay(report_log_file_desc, " FAILED!"); + $fdisplay(report_log_file_desc, " Failure message: %0s.", message_i); + $fdisplay(report_log_file_desc, " Simulation Time: %t", $time); +end +endtask // report_test_failed + +task report_test_ok; +begin + $fdisplay(report_log_file_desc, " PASSED!"); + $fdisplay(report_log_file_desc, " Simulation Time: %t", $time); +end +endtask // report_test_ok + +task report_add_delimiter; +begin + $fdisplay(report_log_file_desc, ""); + $fdisplay(report_log_file_desc, "%0s", {75{"-"}}); + $fdisplay(report_log_file_desc, ""); +end +endtask // report_add_delimiter + +task report_add_text; + input [7999:0] text_i; +begin + $fdisplay(report_log_file_desc, " %0s", text_i); +end +endtask // report_add_text + +task verbose_test_name; + input [1599:0] test_i; +begin + free = 0; + $fdisplay(verbose_log_file_desc, ""); + $fdisplay(verbose_log_file_desc, "%0s", {75{"-"}}); + $fdisplay(verbose_log_file_desc, "- %0s", test_i); + $fdisplay(verbose_log_file_desc, "%0s", {75{"-"}}); + $fdisplay(verbose_log_file_desc, ""); + free = 1; +end +endtask // verbose_test_name + +task verbose_severe_err; + input [7999:0] time_i; + input [7999:0] severe_error_i; +begin + free = 0; + $fdisplay(verbose_log_file_desc, "%0s", time_i); + $fdisplay(verbose_log_file_desc, "*E, Reporting severe error:"); + $fdisplay(verbose_log_file_desc, " %0s", severe_error_i); + free = 1; +end +endtask // verbose_severe_err + +task verbose_err; + input [7999:0] time_i; + input [7999:0] error_i; +begin + free = 0; + $fdisplay(verbose_log_file_desc, "%0s", time_i); + $fdisplay(verbose_log_file_desc, "*E, %0s", error_i); + free = 1; +end +endtask // verbose_err + +task verbose_wrn; + input [7999:0] time_i; + input [7999:0] warning_i; +begin + free = 0; + $fdisplay(verbose_log_file_desc, "%0s", time_i); + $fdisplay(verbose_log_file_desc, "*W, %0s", warning_i); + free = 1; +end +endtask // verbose_wrn + +task verbose_msg; + input [7999:0] time_i; + input [7999:0] message_i; +begin + free = 0; + $fdisplay(verbose_log_file_desc, "%0s", time_i); + $fdisplay(verbose_log_file_desc, "*N, %0s", message_i); + free = 1; +end +endtask // verbose_msg + +task verbose_val; + input [7999:0] time_i; + input [7999:0] message_i; + input [31:0] value_i; +begin + free = 0; + $fdisplay(verbose_log_file_desc, "%0s", time_i); + $fdisplay(verbose_log_file_desc, "*N, %0s %0h.", message_i, value_i); + free = 1; +end +endtask // verbose_val + + +endmodule // uart_log + diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/uart_test.v b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_test.v new file mode 100644 index 00000000..5d61949b --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_test.v @@ -0,0 +1,339 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_test.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// UART core test bench //// +//// //// +//// Known problems (limits): //// +//// A very simple test bench. Creates two UARTS and sends //// +//// data on to the other. //// +//// //// +//// To Do: //// +//// More complete testing should be done!!! //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: 2001/05/17 //// +//// (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Jacob Gorban, gorban@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_test.v,v $ +// Revision 1.3 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.2 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:12+02 jacob +// Initial revision +// +// +//`define DATA_BUS_WIDTH_8 +`include "timescale.v" +module uart_test (); + +`include "uart_defines.v" + +reg clkr; +reg wb_rst_ir; +wire [`UART_ADDR_WIDTH-1:0] wb_adr_i; +wire [31:0] wb_dat_i; +wire [31:0] wb_dat_o; +wire [3:0] wb_sel_i; +wire pad_stx_o; +reg pad_srx_ir; + +integer e; + +uart_top uart_snd( + clk, + + // Wishbone signals + wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, + int_o, // interrupt request + + // UART signals + // serial input/output + pad_stx_o, pad_srx_i, + + // modem signals + rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud1_o +`endif + + + + ); + + +// All the signals and regs named with a 1 are receiver fifo signals + +wire [`UART_ADDR_WIDTH-1:0] wb1_adr_i; +wire [31:0] wb1_dat_i; +wire [31:0] wb1_dat_o; +wire [3:0] wb1_sel_i; +wire int1_o; +wire stx1_o; +reg srx1_ir; + +uart_top uart_rcv( + clk, + + // Wishbone signals + wb_rst_i, wb1_adr_i, wb1_dat_i, wb1_dat_o, wb1_we_i, wb1_stb_i, wb1_cyc_i, wb1_ack_o, wb1_sel_i, + int1_o, // interrupt request + + // UART signals + // serial input/output + stx1_o, srx1_i, + + // modem signals + rts1_o, cts1_i, dtr1_o, dsr1_i, ri1_i, dcd1_i +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud2_o +`endif + + ); + +assign clk = clkr; +assign wb_rst_i = wb_rst_ir; +assign pad_srx_i = pad_srx_ir; +assign cts_i = 1; //cts_ir; +assign dsr_i = 1; //dsr_ir; +assign ri_i = 1; //ri_ir; +assign dcd_i = 1; //dcd_ir; + +assign srx1_i = srx1_ir; +assign cts1_i = 1; //cts1_ir; +assign dsr1_i = 1; //dsr1_ir; +assign ri1_i = 1; //ri1_ir; +assign dcd1_i = 1; //dcd1_ir; + +reg [31:0] dat_o; +/////////// CONNECT THE UARTS +always @(pad_stx_o) +begin + srx1_ir = pad_stx_o; +end + +initial +begin + clkr = 0; + #50000 $finish; +end + +wb_mast wbm(// Outputs + .adr (wb_adr_i), + .dout (wb_dat_i), + .cyc (wb_cyc_i), + .stb (wb_stb_i), + .sel (wb_sel_i), + .we (wb_we_i), + // Inputs + .clk (clk), + .rst (wb_rst_i), + .din (wb_dat_o), + .ack (wb_ack_o), + .err (1'b0), + .rty (1'b0)); + +wb_mast wbm1(// Outputs + .adr (wb1_adr_i), + .dout (wb1_dat_i), + .cyc (wb1_cyc_i), + .stb (wb1_stb_i), + .sel (wb1_sel_i), + .we (wb1_we_i), + // Inputs + .clk (clk), + .rst (wb_rst_i), + .din (wb1_dat_o), + .ack (wb1_ack_o), + .err (1'b0), + .rty (1'b0)); + +// The test sequence +initial +begin + #1 wb_rst_ir = 1; + #10 wb_rst_ir = 0; + + //write to lcr. set bit 7 + //wb_cyc_ir = 1; + wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b10011011, 24'b0}); + // set dl to divide by 3 + wbm.wb_wr1(`UART_REG_DL1,4'b0001, 32'd2); + @(posedge clk); + @(posedge clk); + // restore normal registers + wbm.wb_wr1(`UART_REG_LC, 4'b1000, {8'b00011011, 24'b0}); //00011011 + + fork + begin + $display("%m : %t : sending : %h", $time, 8'b10000001); + wbm.wb_wr1(0, 4'b1, 32'b10000001); + @(posedge clk); + @(posedge clk); + $display("%m : %t : sending : %h", $time, 8'b01000010); + wbm.wb_wr1(0, 4'b1, 32'b01000010); + @(posedge clk); + @(posedge clk); + $display("%m : %t : sending : %h", $time, 8'b11000011); + wbm.wb_wr1(0, 4'b1, 32'b11000011); + @(posedge clk); + @(posedge clk); + $display("%m : %t : sending : %h", $time, 8'b00100100); + wbm.wb_wr1(0, 4'b1, 32'b00100100); + @(posedge clk); + @(posedge clk); + $display("%m : %t : sending : %h", $time, 8'b10100101); + wbm.wb_wr1(0, 4'b1, 32'b10100101); + @(posedge clk); + @(posedge clk); + $display("%m : %t : sending : %h", $time, 8'b01100110); + wbm.wb_wr1(0, 4'b1, 32'b01100110); + @(posedge clk); + @(posedge clk); + $display("%m : %t : sending : %h", $time, 8'b11100111); + wbm.wb_wr1(0, 4'b1, 32'b11100111); + @(posedge clk); + @(posedge clk); + $display("%m : %t : sending : %h", $time, 8'b00011000); + wbm.wb_wr1(0, 4'b1, 32'b00011000); + wait (uart_snd.regs.tstate==0 && uart_snd.regs.transmitter.tf_count==0); +// disable check; + end +// begin: check +// end + join +end + +always @(int1_o) + if (int1_o) + $display("INT_O high (%g)", $time); + else + $display("INT_O low (%g)", $time); + +always @(int1_o) +begin + if (int1_o) begin + wbm1.wb_rd1(2,4'b0100, dat_o); + $display("IIR : %h", dat_o); + wbm1.wb_rd1(5,4'b0010, dat_o); + $display("LSR : %h", dat_o); + wbm1.wb_rd1(0, 4'b1, dat_o); + $display("%m : %t : Data out: %h", $time, dat_o); + end +end + +// receiver side +initial +begin + #11; + //write to lcr. set bit 7 + //wb_cyc_ir = 1; + wbm1.wb_wr1(`UART_REG_LC, 4'b1000, {8'b10011011, 24'b0}); + // set dl to divide by 3 + wbm1.wb_wr1(`UART_REG_DL1, 4'b1, 32'd2); + @(posedge clk); + @(posedge clk); + // restore normal registers + wbm1.wb_wr1(`UART_REG_LC, 4'b1000, {8'b00011011, 24'b0}); + wbm1.wb_wr1(`UART_REG_IE, 4'b0010, {16'b0, 8'b00001111, 8'b0}); + wait(uart_rcv.regs.receiver.rf_count == 2); + e = 800; + while (e > 0) + begin + @(posedge clk) + if (uart_rcv.regs.enable) e = e - 1; + end + wbm1.wb_rd1(0, 4'b1, dat_o); + $display("%m : %t : Data out: %h", $time, dat_o); + @(posedge clk); + wbm1.wb_rd1(0, 4'b1, dat_o); + $display("%m : %t : Data out: %h", $time, dat_o); + $display("%m : Finish"); + e = 800; + while (e > 0) + begin + @(posedge clk) + if (uart_rcv.regs.enable) e = e - 1; + end + e = 800; + while (e > 0) + begin + @(posedge clk) + if (uart_rcv.regs.enable) e = e - 1; + end + $finish; +end + +//always @(uart_rcv.regs.rstate) +//begin +// $display($time,": Receiver state changed to: ", uart_rcv.regs.rstate); +//end + +initial + begin + `ifdef DATA_BUS_WIDTH_8 +$display("DATA BUS IS 8"); +`else +$display("DATA BUS IS 32"); +`endif + $display("%d %d", `UART_ADDR_WIDTH, `UART_DATA_WIDTH); + + end + + +always +begin + #5 clkr = ~clk; +end + +endmodule diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench.v b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench.v new file mode 100644 index 00000000..e126ade5 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench.v @@ -0,0 +1,1366 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_testbench.v //// +//// //// +//// This file is part of the "uart16550" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Author(s): //// +//// - tadej@opencores.org (Tadej Markovic) //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_testbench.v,v $ +// Revision 1.1 2004/03/27 03:55:17 tadejm +// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. +// +// +// + + +`include "uart_defines.v" +`include "uart_testbench_defines.v" +`include "wb_model_defines.v" +`include "timescale.v" + +module testbench; + + +parameter max_wait_cnt = 20000; + +// INTERNAL signals +//################# + + // WB slave signals + //################# + + // UART Wishbone Slave signals + wire wb_int_o; + wire [`UART_ADDR_WIDTH-1:0] wbs_adr_i; + wire [`UART_DATA_WIDTH-1:0] wbs_dat_i; + wire [`UART_DATA_WIDTH-1:0] wbs_dat_o; + wire [3:0] wbs_sel_i; + wire wbs_cyc_i; + wire wbs_stb_i; + wire [2:0] wbs_cti_i; + wire [1:0] wbs_bte_i; + wire wbs_we_i; + wire wbs_ack_o; + wire wbs_rty_o = 1'b0; + wire wbs_err_o = 1'b0; + + // UART signals + //############# + + // UART Serial Data I/O signals + wire stx_pad_o; + wire srx_pad_i; + // UART Modem I/O signals + wire rts_pad_o; + wire cts_pad_i; + wire dtr_pad_o; + wire dsr_pad_i; + wire ri_pad_i; + wire dcd_pad_i; + `ifdef UART_HAS_BAUDRATE_OUTPUT + wire baud_o; + `endif + + // System signals + //############### + + // WB clock signal + reg wb_clk; // divided device clock with period T_wb_clk_period + // WB clock enable signal + reg wb_clk_en = 1'b1; + // WB clock period variable + real T_wb_clk_period = 20; + // WB reset signal + reg wb_reset; + event reset_aserted; + event reset_released; + event int_aserted; + event int_released; + // Error detection event + event error_detected; + + // UART register monitor + //######################### + + // Line Status Register + // Reading LSR register + reg lsr_reg_read; + // Bit 0 - Data Ready + reg lsr_reg_bit0_change_allowed; + // Bit 1 - Overrun Error + reg lsr_reg_bit1_change_allowed; + // Bit 2 - Parity Error + reg lsr_reg_bit2_change_allowed; + reg [4:0] rx_fifo_par_rd_pointer; + integer i2; + // Bit 3 - Framing Error + reg lsr_reg_bit3_change_allowed; + reg [4:0] rx_fifo_frm_rd_pointer; + integer i3; + // Bit 4 - Break Interrupt + reg lsr_reg_bit4_change_allowed; + reg [4:0] rx_fifo_brk_rd_pointer; + integer i4; + // Bit 5 - Transmitter Holding Register Empty + reg lsr_reg_bit5_change_allowed; + // Bit 6 - Transmitter Empty + reg lsr_reg_bit6_change_allowed; + // Bit 7 - Error in RX FIFO + reg lsr_reg_bit7_change_allowed; + + // UART transmitter monitor + //######################### + + // TX FIFO signals + reg [7:0] tx_shift_reg; + reg tx_shift_reg_empty; + reg tx_start_bit_edge; + reg [7:0] tx_fifo [0:31]; + reg [4:0] tx_fifo_wr_pointer; + reg [4:0] tx_fifo_rd_pointer; + reg [4:0] tx_fifo_status; + + // UART receiver monitor + //###################### + + // RX FIFO signals + reg [7:0] rx_shift_reg; + reg rx_shift_reg_full; + reg rx_parity_err; + reg rx_framing_err; + reg rx_framing_glitch; + reg rx_break_int; + reg rx_overrun_err_occured; + reg [7:0] rx_fifo_data [0:31]; + reg [31:0] rx_fifo_par; + reg [31:0] rx_fifo_frm; + reg [31:0] rx_fifo_brk; + reg [4:0] rx_fifo_wr_pointer; + reg [4:0] rx_fifo_rd_pointer; + reg [4:0] rx_fifo_status; + reg rx_fifo_read; + + // UART register tracker + //###################### + + // Registers + wire [7:0] ier_reg; + wire [7:0] iir_reg; + wire [7:0] fcr_reg; + wire [7:0] lcr_reg; + wire [7:0] mcr_reg; + wire [7:0] lsr_reg; + wire [7:0] msr_reg; + wire [7:0] dll_reg; + wire [7:0] dlm_reg; + // Events + event ier_reg_changed; + event iir_reg_changed; + event fcr_reg_changed; + event lcr_reg_changed; + event mcr_reg_changed; + event lsr_reg_changed; + event msr_reg_changed; + event dll_reg_changed; + event dlm_reg_changed; + // Register access + reg [`UART_ADDR_WIDTH-1:0] reg_adr; + reg [`UART_DATA_WIDTH-1:0] reg_dat; + reg reg_dlab; + event reg_written; + event tx_reg_written; + event reg_read; + event rx_reg_read; + + + +uart_top #(`UART_DATA_WIDTH, `UART_ADDR_WIDTH) i_uart_top +( + .wb_clk_i (wb_clk), + .wb_rst_i (wb_reset), + .int_o (wb_int_o), +// WB slave signals - 2 address locations for two registers! + .wb_cyc_i (wbs_cyc_i), + .wb_stb_i (wbs_stb_i), + .wb_we_i (wbs_we_i), + .wb_sel_i (wbs_sel_i), + .wb_adr_i (wbs_adr_i), + .wb_dat_i (wbs_dat_i), + .wb_dat_o (wbs_dat_o), + .wb_ack_o (wbs_ack_o), +// UART signals + .stx_pad_o (stx_pad_o), + .srx_pad_i (srx_pad_i), +// Modem signals + .rts_pad_o (rts_pad_o), + .cts_pad_i (cts_pad_i), + .dtr_pad_o (dtr_pad_o), + .dsr_pad_i (dsr_pad_i), + .ri_pad_i (ri_pad_i), + .dcd_pad_i (dcd_pad_i) +`ifdef UART_HAS_BAUDRATE_OUTPUT + , + .baud_o (baud_o) +`endif +); + +uart_device i_uart_device +( +// UART signals + .stx_i (stx_pad_o), + .srx_o (srx_pad_i), +// Modem signals + .rts_i (rts_pad_o), + .cts_o (cts_pad_i), + .dtr_i (dtr_pad_o), + .dsr_o (dsr_pad_i), + .ri_o (ri_pad_i), + .dcd_o (dcd_pad_i) +); + +wb_master_model #(`UART_DATA_WIDTH, `UART_ADDR_WIDTH, 4) i_wb_master_model +( + .wb_rst_i (wb_reset), + .wb_clk_i (wb_clk), + .wbm_cyc_o (wbs_cyc_i), + .wbm_cti_o (), + .wbm_bte_o (), + .wbm_stb_o (wbs_stb_i), + .wbm_we_o (wbs_we_i), + .wbm_adr_o (wbs_adr_i), + .wbm_sel_o (wbs_sel_i), + .wbm_dat_o (wbs_dat_i), + .wbm_dat_i (wbs_dat_o), + .wbm_ack_i (wbs_ack_o), + .wbm_err_i (wbs_err_o), // inactive (1'b0) + .wbm_rty_i (wbs_rty_o) // inactive (1'b0) +); + + +initial +begin:system + // Initial system values + wb_reset = 1'b1; + wb_clk = 1'b0; +end + + +// WB clock generation (DEVICE clock is generated in uart_device.v) +//################################################################# + + // DEVICE's clock generation: + // ---------------- + // // rx_clk rising edge + // always@(posedge rx_clk) + // if (rx_clk_en) + // #(T_clk_period / 2) rx_clk = 1'b0; + // // rx_clk falling edge + // always@(negedge rx_clk) + // if (rx_clk_en) + // #(T_clk_period / 2) rx_clk = 1'b1; + // ---------------- + // DEVICE's transmit clocks generation: + // ---------------- + // // tx_clk rising edge + // always@(posedge tx_clk) + // if (tx_clk_en) + // #((T_clk_period / 2) * 16 * T_divisor) tx_clk = 1'b0; + // // tx_clk falling edge + // always@(negedge tx_clk) + // if (tx_clk_en) + // #((T_clk_period / 2) * 16 * T_divisor) tx_clk = 1'b1; + // ---------------- + + // WB clock + always@(posedge wb_clk) + if (wb_clk_en) + #(T_wb_clk_period / 2) wb_clk = 1'b0; + always@(negedge wb_clk) + if (wb_clk_en) + #(T_wb_clk_period / 2) wb_clk = 1'b1; + + +// SYSTEM signals tracker +//####################### + + // Reset + always@(posedge wb_reset) + -> reset_aserted; + always@(negedge wb_reset) + -> reset_released; + + // Interrupt + always@(posedge wb_int_o) + -> int_aserted; + always@(negedge wb_int_o) + -> int_released; + + +// UART register tracker +//###################### + + // UART registers: + // ---------------- + // RBR (R/ | ADR 0 | DLAB 0) + // [7:0] -RX---- "rxdata" Receiver Buffer Register + // ---------------- + // THR ( /W | ADR 0 | DLAB 0) + // [7:0] ----TX- "txdata" Transmitter Holding Register + // ---------------- + // IER (R/W | ADR 1 | DLAB 0) + // [0] -RX---- "1" Received Data Available & Receive Fifo Timeout + // [1] ----TX- "1" Transmitter Holding Register Empty + // [2] -RX---- "1" Receiver Line Status + // [3] -MODEM- "1" Modem Status + // ---------------- + // IIR (R/ | ADR 2) + // [0] ------- "0" Interrupt is Pending (decreasing priority level in following 3 bits) + // [3:1] -RX---- "011" Receiver Line Status - Overrun, Parity, Framing error or Break int. ---> READ LSR + // [3:1] -RX---- "010" Received Data Available - Fifo Trigger Level Reached ------------------> READ RBR (Fifo lower than trig.) + // [3:1] -RX---- "110" Timeout Indication - Fifo not empty & no Fifo action for 4 char times -> READ RBR + // [3:1] ----TX- "001" Transmitter Holding Register Empty - THR Empty ------------------------> READ IIR | WRITE THR + // [3:1] -MODEM- "000" Modem Status - CTS, DSR, DCD changed or RI changed from '0' to '1' ----> READ MSR + // ---------------- + // FCR ( /W | ADR 2) + // [1] -RX---- "1" Clear only Receiver Fifo (not shift register) + // [2] ----TX- "1" Clear only Transmitter Fifo (not shift register) + // [7:6] -RX---- "00" 1 BYTE Receiver Fifo Interrupt trigger level + // [7:6] -RX---- "01" 4 BYTEs Receiver Fifo Interrupt trigger level + // [7:6] -RX---- "10" 8 BYTEs Receiver Fifo Interrupt trigger level + // [7:6] -RX---- "11" 14 BYTEs Receiver Fifo Interrupt trigger level + // ---------------- + // LCR (R/W | ADR 3) + // [1:0] -RX-TX- "00" 5 bits in each character + // [1:0] -RX-TX- "01" 6 bits in each character + // [1:0] -RX-TX- "10" 7 bits in each character + // [1:0] -RX-TX- "11" 8 bits in each character + // [2] -RX-TX- "0" 1 stop bit + // [2] -RX-TX- "1" 1.5 stop bits (when 5 bits of char.) or 2 stop bits (when 6, 7 or 8 bits of char.) + // [3] -RX-TX- "1" Parity bit enabled + // [5:4] -RX-TX- "00" NO Stick Parity & ODD Parity bit - ODD num. of '1's is transmitted + // [5:4] -RX-TX- "01" NO Stick Parity & EVEN Parity bit - EVEN num. of '1's is transmitted + // [5:4] -RX-TX- "10" Stick Parity bit - Stick '1' as Parity bit + // [5:4] -RX-TX- "11" Stick Parity bit - Stick '0' as Parity bit + // [6] ----TX- "1" Break Control - Output is forced to '0' + // [7] ------- "1" DLAB - for access to DLL and DLM + // ---------------- + // MCR ( /W | ADR 4) + // [0] -MODEM- "1" Force DTR to '0' - in LoopBack connected to DSR input + // [1] -MODEM- "1" Force RTS to '0' - in LoopBack connected to CTS input + // [2] -MODEM- "1" Force N.C.1 to '0' - in LoopBack connected to RI input + // [3] -MODEM- "1" Force N.C.2 to '0' - in LoopBack connected to DCD input + // [4] -MODEM- "1" LoopBack mode + // ---------------- + // LSR (R/ | ADR 5) + // [0] -RX---- "1" Data Ready - At least 1 char. received and is in Fifo----------> READ RBR (Fifo empty) + // [1] -RX---- "1" Overrun Error - Fifo full & 1 char. received in shift reg. ----> READ LSR + // [2] -RX---- "1" Parity Error - top Fifo char. has invalid parity bit ----------> READ LSR + // [3] -RX---- "1" Framing Error - top Fifo char. has invalid stop bit -----------> READ LSR + // [4] -RX---- "1" Break Int. - top Fifo char. bits are '0' and it's ctrl. bits --> READ LSR + // [5] ----TX- "1" Transmitter Holding Register Empty - transmitter Fifo empty ---> WRITE THR + // [6] ----TX- "1" Transmitter EMpTy - transmitter Fifo empty & shift reg. empty -> WRITE THR + // [7] -RX---- "1" At least 1 Parity Error, Framing Error or Break Int. in Fifo --> READ LSR & No More Errors in Fifo + // ---------------- + // MSR (R/ | ADR 6) + // [0] -MODEM- "1" Delta CTS indicator - CTS has changed it's state --------------> READ MSR + // [1] -MODEM- "1" Delta DSR indicator - DSR has changed it's state --------------> READ MSR + // [2] -MODEM- "1" Trailing Edge of RI - RI has changed from '0' to '1' ----------> READ MSR + // [3] -MODEM- "1" Delta DCD indicator - DCD has changed it's state --------------> READ MSR + // [4] -MODEM- "x" Complement of CTS input | in LoopBack equal to RTS = MCR[1] + // [5] -MODEM- "x" Complement of DSR input | in LoopBack equal to DTR = MCR[0] + // [6] -MODEM- "x" Complement of RI input | in LoopBack equal to N.C.1 = MCR[2] + // [7] -MODEM- "x" Complement of DCD input | in LoopBack equal to N.C.2 = MCR[3] + // ---------------- + // DLL (R/W | ADR 0 | DLAB 1) + // [7:0] ------- "dl[ 7:0]" LSB of DL Reg. written 2. - dl == '0' disables outputs / dl = 1/(T_wb_clk_period*16*BaudRate) + // ---------------- + // DLM (R/W | ADR 1 | DLAB 1) + // [7:0] ------- "dl[15:8]" MSB of DL Reg. written 1. - dl == '0' disables outputs / dl = 1/(T_wb_clk_period*16*BaudRate) + // ---------------- + + // Transparent UART registers + assign ier_reg[7:0] = {4'h0, testbench.i_uart_top.regs.ier }; + assign iir_reg[7:0] = {4'hC, testbench.i_uart_top.regs.iir }; + assign fcr_reg[7:0] = { testbench.i_uart_top.regs.fcr, 6'h0}; + assign lcr_reg[7:0] = { testbench.i_uart_top.regs.lcr }; // lcr_reg[7] == DLAB !!! + assign mcr_reg[7:0] = {3'h0, testbench.i_uart_top.regs.mcr }; + assign lsr_reg[7:0] = { testbench.i_uart_top.regs.lsr }; + assign msr_reg[7:0] = { testbench.i_uart_top.regs.msr }; + assign dll_reg[7:0] = { testbench.i_uart_top.regs.dl[ 7:0] }; + assign dlm_reg[7:0] = { testbench.i_uart_top.regs.dl[15:8] }; + + // Tracking changes of registers + always@(ier_reg) + begin + -> ier_reg_changed; + end + always@(iir_reg) + begin + -> iir_reg_changed; + end + always@(fcr_reg) + begin + -> fcr_reg_changed; + end + always@(lcr_reg) + begin + -> lcr_reg_changed; + end + always@(mcr_reg) + begin + -> mcr_reg_changed; + end + always@(lsr_reg) + begin + -> lsr_reg_changed; + end + always@(msr_reg) + begin + -> msr_reg_changed; + end + always@(dll_reg) + begin + -> dll_reg_changed; + end + always@(dlm_reg) + begin + -> dlm_reg_changed; + end + + // Tracking read/write access to registers + always@(wbs_cyc_i or wbs_stb_i or wbs_we_i or wbs_sel_i or wbs_adr_i or + wbs_dat_i /*or wbs_ack_o*/ /*or posedge wb_clk*/) + begin + if (wbs_cyc_i && wbs_stb_i) + begin + if (wbs_we_i /*&& wbs_ack_o*/) // WRITE + begin + // LOG's example of detecting of register write: + // ---------------- + // case (wbs_adr_i) + // `UART_REG_TR: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!! + // -> dll_reg_written; + // else + // -> thr_reg_written; + // `UART_REG_IE: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!! + // -> dlm_reg_written; + // else + // -> ier_reg_written; + // `UART_REG_FC: -> fcr_reg_written; + // `UART_REG_LC: -> lcr_reg_written; + // `UART_REG_MC: -> mcr_reg_written; + // default: -> erroneous_write_location; + // endcase + // ---------------- + + reg_adr = wbs_adr_i; + reg_dat = wbs_dat_i; + reg_dlab = lcr_reg[7]; + -> reg_written; + if (~reg_dlab && (reg_adr == `UART_REG_TR)) // write to FIFO + -> tx_reg_written; + end + end + end + always@(wbs_cyc_i or wbs_stb_i or wbs_we_i or wbs_sel_i or wbs_adr_i or + wbs_dat_o or wbs_ack_o /*or posedge wb_clk*/) + begin + if (wbs_cyc_i && wbs_stb_i) + begin + if (~wbs_we_i && wbs_ack_o) // READ + begin + // LOG's example of detecting of register read: + // ---------------- + // case (wbs_adr_i) + // `UART_REG_RB: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!! + // -> dll_reg_read; + // else + // -> rbr_reg_read; + // `UART_REG_IE: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!! + // -> dlm_reg_read; + // else + // -> ier_reg_read; + // `UART_REG_II: -> iir_reg_read; + // `UART_REG_LC: -> lcr_reg_read; + // `UART_REG_LS: -> lsr_reg_read; + // `UART_REG_MS: -> msr_reg_read; + // default: -> erroneous_read_location; + // endcase + // ---------------- + + reg_adr = wbs_adr_i; + reg_dat = wbs_dat_o; + reg_dlab = lcr_reg[7]; + -> reg_read; + if (~reg_dlab && (reg_adr == `UART_REG_RB)) + -> rx_reg_read; + end + end + end + + +// UART register monitor +//####################### + + // Line Status Register + // Reading LSR register + initial + begin + lsr_reg_read = 0; + forever + begin + @(reg_read); + if (reg_adr == `UART_REG_LS) + begin + lsr_reg_read = 1'b1; + repeat (1) @(posedge wb_clk); + lsr_reg_read = 0; + end + end + end + // Bit 0 - Data Ready + initial + begin + lsr_reg_bit0_change_allowed = 0; + @(reset_released); + #10; + fork + begin: rx_fifo_status_changing + forever + begin + if (rx_fifo_status == 0) + begin + wait (rx_fifo_status > 0); + lsr_reg_bit0_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit0_change_allowed = 0; + if (~lsr_reg[0]) + begin + `BENCH_ERROR("Bit 0 of LSR register not '1'!"); + -> error_detected; + end + end + else + begin + wait (rx_fifo_status == 0); + lsr_reg_bit0_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit0_change_allowed = 0; + if (lsr_reg[0]) + begin + `BENCH_ERROR("Bit 0 of LSR register not '0'!"); + -> error_detected; + end + end + end + end + begin: lsr_reg_bit0_changing + forever + begin + wait (~lsr_reg_bit0_change_allowed); + begin + @(lsr_reg[0] or lsr_reg_bit0_change_allowed); + if (~lsr_reg_bit0_change_allowed) + begin + `BENCH_ERROR("Bit 0 of LSR register should not change!"); + -> error_detected; + end + end + end + end + join + end + // Bit 1 - Overrun Error + initial + begin + lsr_reg_bit1_change_allowed = 0; + @(reset_released); + #10; + fork + begin: rx_overrun_err_occured_changing + forever + begin + if (~rx_overrun_err_occured) + begin + wait (rx_overrun_err_occured); + lsr_reg_bit1_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit1_change_allowed = 0; + if (~lsr_reg[1]) + begin + `BENCH_ERROR("Bit 1 of LSR register not '1'!"); + -> error_detected; + end + end + else + begin + wait (lsr_reg_read); + lsr_reg_bit1_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit1_change_allowed = 0; + rx_overrun_err_occured = 0; + if (lsr_reg[1]) + begin + `BENCH_ERROR("Bit 1 of LSR register not '0'!"); + -> error_detected; + end + end + end + end + begin: lsr_reg_bit1_changing + forever + begin + wait (~lsr_reg_bit1_change_allowed); + begin + @(lsr_reg[1] or lsr_reg_bit1_change_allowed); + if (~lsr_reg_bit1_change_allowed) + begin + `BENCH_ERROR("Bit 1 of LSR register should not change!"); + -> error_detected; + end + end + end + end + join + end + // Bit 2 - Parity Error + initial + begin + lsr_reg_bit2_change_allowed = 0; + rx_fifo_par_rd_pointer = 0; + @(reset_released); + #10; + fork + begin: rx_parity_err_changing + forever + begin + if (~rx_fifo_par[rx_fifo_par_rd_pointer]) + begin + wait (rx_fifo_read); + lsr_reg_bit2_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit2_change_allowed = 0; + rx_fifo_par_rd_pointer = rx_fifo_par_rd_pointer + 1'b1; + // check bit + if (~lsr_reg[2] && rx_fifo_par[rx_fifo_par_rd_pointer]) + begin + `BENCH_ERROR("Bit 2 of LSR register not '1'!"); + -> error_detected; + end + else if (lsr_reg[2] && ~rx_fifo_par[rx_fifo_par_rd_pointer]) + begin + `BENCH_ERROR("Bit 2 of LSR register not '0'!"); + -> error_detected; + end + end + else + begin + wait (lsr_reg_read); + lsr_reg_bit2_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit2_change_allowed = 0; + if (rx_fifo_par_rd_pointer < rx_fifo_rd_pointer) + begin + for (i2 = rx_fifo_par_rd_pointer; i2 <= rx_fifo_rd_pointer; i2 = i2 + 1) + rx_fifo_par[i2] = 0; + rx_fifo_par_rd_pointer = rx_fifo_rd_pointer; + end + else if (rx_fifo_par_rd_pointer > rx_fifo_rd_pointer) + begin + for (i2 = rx_fifo_par_rd_pointer; i2 <= 31; i2 = i2 + 1) + rx_fifo_par[i2] = 0; + for (i2 = 0; i2 <= rx_fifo_rd_pointer; i2 = i2 + 1) + rx_fifo_par[i2] = 0; + rx_fifo_par_rd_pointer = rx_fifo_rd_pointer; + end + else + begin + rx_fifo_par = 0; + rx_fifo_par_rd_pointer = rx_fifo_rd_pointer; + end + // check bit + if (~lsr_reg[2] && rx_fifo_par[rx_fifo_par_rd_pointer]) + begin + `BENCH_ERROR("Bit 2 of LSR register not '1'!"); + -> error_detected; + end + else if (lsr_reg[2] && ~rx_fifo_par[rx_fifo_par_rd_pointer]) + begin + `BENCH_ERROR("Bit 2 of LSR register not '0'!"); + -> error_detected; + end + end + end + end + begin: lsr_reg_bit2_changing + forever + begin + wait (~lsr_reg_bit2_change_allowed); + begin + @(lsr_reg[2] or lsr_reg_bit2_change_allowed); + if (~lsr_reg_bit2_change_allowed) + begin + `BENCH_ERROR("Bit 2 of LSR register should not change!"); + -> error_detected; + end + end + end + end + join + end + // Bit 3 - Framing Error + initial + begin + lsr_reg_bit3_change_allowed = 0; + rx_fifo_frm_rd_pointer = 0; + @(reset_released); + #10; + fork + begin: rx_framing_err_changing + forever + begin + if (~rx_fifo_frm[rx_fifo_frm_rd_pointer]) + begin + wait (rx_fifo_read); + lsr_reg_bit3_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit3_change_allowed = 0; + rx_fifo_frm_rd_pointer = rx_fifo_frm_rd_pointer + 1'b1; + // check bit + if (~lsr_reg[3] && rx_fifo_frm[rx_fifo_frm_rd_pointer]) + begin + `BENCH_ERROR("Bit 3 of LSR register not '1'!"); + -> error_detected; + end + else if (lsr_reg[3] && ~rx_fifo_frm[rx_fifo_frm_rd_pointer]) + begin + `BENCH_ERROR("Bit 3 of LSR register not '0'!"); + -> error_detected; + end + end + else + begin + wait (lsr_reg_read); + lsr_reg_bit3_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit3_change_allowed = 0; + if (rx_fifo_frm_rd_pointer < rx_fifo_rd_pointer) + begin + for (i3 = rx_fifo_frm_rd_pointer; i3 <= rx_fifo_rd_pointer; i3 = i3 + 1) + rx_fifo_frm[i3] = 0; + rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer; + end + else if (rx_fifo_frm_rd_pointer > rx_fifo_rd_pointer) + begin + for (i3 = rx_fifo_frm_rd_pointer; i3 <= 31; i3 = i3 + 1) + rx_fifo_frm[i3] = 0; + for (i3 = 0; i3 <= rx_fifo_rd_pointer; i3 = i3 + 1) + rx_fifo_frm[i3] = 0; + rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer; + end + else + begin + rx_fifo_frm = 0; + rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer; + end + // check bit + if (~lsr_reg[3] && rx_fifo_frm[rx_fifo_frm_rd_pointer]) + begin + `BENCH_ERROR("Bit 3 of LSR register not '1'!"); + -> error_detected; + end + else if (lsr_reg[3] && ~rx_fifo_frm[rx_fifo_frm_rd_pointer]) + begin + `BENCH_ERROR("Bit 3 of LSR register not '0'!"); + -> error_detected; + end + end + end + end + begin: lsr_reg_bit3_changing + forever + begin + wait (~lsr_reg_bit3_change_allowed); + begin + @(lsr_reg[3] or lsr_reg_bit3_change_allowed); + if (~lsr_reg_bit3_change_allowed) + begin + `BENCH_ERROR("Bit 3 of LSR register should not change!"); + -> error_detected; + end + end + end + end + join + end + // Bit 4 - Break Interrupt + initial + begin + lsr_reg_bit4_change_allowed = 0; + rx_fifo_brk_rd_pointer = 0; + @(reset_released); + #10; + fork + begin: rx_break_int_changing + forever + begin + if (~rx_fifo_brk[rx_fifo_brk_rd_pointer]) + begin + wait (rx_fifo_read); + lsr_reg_bit4_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit4_change_allowed = 0; + rx_fifo_brk_rd_pointer = rx_fifo_brk_rd_pointer + 1'b1; + // check bit + if (~lsr_reg[4] && rx_fifo_brk[rx_fifo_brk_rd_pointer]) + begin + `BENCH_ERROR("Bit 4 of LSR register not '1'!"); + -> error_detected; + end + else if (lsr_reg[4] && ~rx_fifo_brk[rx_fifo_brk_rd_pointer]) + begin + `BENCH_ERROR("Bit 4 of LSR register not '0'!"); + -> error_detected; + end + end + else + begin + wait (lsr_reg_read); + lsr_reg_bit4_change_allowed = 1'b1; + repeat (1) @(posedge wb_clk); + #2; + lsr_reg_bit4_change_allowed = 0; + if (rx_fifo_brk_rd_pointer < rx_fifo_rd_pointer) + begin + for (i4 = rx_fifo_brk_rd_pointer; i4 <= rx_fifo_rd_pointer; i4 = i4 + 1) + rx_fifo_brk[i4] = 0; + rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer; + end + else if (rx_fifo_brk_rd_pointer > rx_fifo_rd_pointer) + begin + for (i4 = rx_fifo_brk_rd_pointer; i4 <= 31; i4 = i4 + 1) + rx_fifo_brk[i4] = 0; + for (i4 = 0; i4 <= rx_fifo_rd_pointer; i4 = i4 + 1) + rx_fifo_brk[i4] = 0; + rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer; + end + else + begin + rx_fifo_brk = 0; + rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer; + end + // check bit + if (~lsr_reg[4] && rx_fifo_brk[rx_fifo_brk_rd_pointer]) + begin + `BENCH_ERROR("Bit 4 of LSR register not '1'!"); + -> error_detected; + end + else if (lsr_reg[4] && ~rx_fifo_brk[rx_fifo_brk_rd_pointer]) + begin + `BENCH_ERROR("Bit 4 of LSR register not '0'!"); + -> error_detected; + end + end + end + end + begin: lsr_reg_bit4_changing + forever + begin + wait (~lsr_reg_bit4_change_allowed); + begin + @(lsr_reg[4] or lsr_reg_bit4_change_allowed); + if (~lsr_reg_bit4_change_allowed) + begin + `BENCH_ERROR("Bit 4 of LSR register should not change!"); + -> error_detected; + end + end + end + end + join + end + // Bit 5 - Transmitter Holding Register Empty + initial + begin + lsr_reg_bit5_change_allowed = 0; + @(reset_released); + #10; + fork + begin: tx_fifo_status_changing + forever + begin + if (tx_fifo_status == 0) + begin +// @(tx_reg_written); + wait (tx_fifo_status > 0); + lsr_reg_bit5_change_allowed = 1'b1; + repeat (3) @(posedge wb_clk); + #2; + lsr_reg_bit5_change_allowed = 0; + if (lsr_reg[5]) + begin + `BENCH_ERROR("Bit 5 of LSR register not '0'!"); + -> error_detected; + end + end + else + begin + wait (tx_fifo_status == 0); + lsr_reg_bit5_change_allowed = 1'b1; + repeat (3) @(posedge wb_clk); + #2; + lsr_reg_bit5_change_allowed = 0; + if (~lsr_reg[5]) + begin + `BENCH_ERROR("Bit 5 of LSR register not '1'!"); + -> error_detected; + end + end + end + end + begin: lsr_reg_bit5_changing + forever + begin + wait (~lsr_reg_bit5_change_allowed); + begin + @(lsr_reg[5] or lsr_reg_bit5_change_allowed); + if (~lsr_reg_bit5_change_allowed) + begin + `BENCH_ERROR("Bit 5 of LSR register should not change!"); + -> error_detected; + end + end + end + end + join + end + // Bit 6 - Transmitter Empty + initial + begin + lsr_reg_bit6_change_allowed = 0; + @(reset_released); + #10; + fork + begin: tx_fifo_status_and_shift_reg_changing + forever + begin + if ((tx_fifo_status == 0) && tx_shift_reg_empty) + begin +// @(tx_reg_written); + wait (tx_fifo_status > 0); + lsr_reg_bit6_change_allowed = 1'b1; + repeat (3) @(posedge wb_clk); + #2; + lsr_reg_bit6_change_allowed = 0; + if (lsr_reg[6]) + begin + `BENCH_ERROR("Bit 6 of LSR register not '0'!"); + -> error_detected; + end + end + else + begin + wait ((tx_fifo_status == 0) && tx_shift_reg_empty); + lsr_reg_bit6_change_allowed = 1'b1; + repeat (3) @(posedge wb_clk); + #2; + lsr_reg_bit6_change_allowed = 0; + if (~lsr_reg[6]) + begin + `BENCH_ERROR("Bit 6 of LSR register not '1'!"); + -> error_detected; + end + end + end + end + begin: lsr_reg_bit6_changing + forever + begin + wait (~lsr_reg_bit6_change_allowed); + begin + @(lsr_reg[6] or lsr_reg_bit6_change_allowed); + if (~lsr_reg_bit6_change_allowed) + begin + `BENCH_ERROR("Bit 6 of LSR register should not change!"); + -> error_detected; + end + end + end + end + join + end + // Bit 7 - Error in RX FIFO + initial + begin + lsr_reg_bit7_change_allowed = 0; + @(reset_released); + #10; + fork + begin: error_changing + forever + begin + if ((rx_fifo_par == 0) && (rx_fifo_frm == 0) && (rx_fifo_brk == 0)) + begin + wait (rx_parity_err || rx_framing_err || rx_framing_glitch || rx_break_int); + lsr_reg_bit7_change_allowed = 1'b1; + repeat (3) @(posedge wb_clk); + #2; + lsr_reg_bit7_change_allowed = 0; + // check bit + if (~lsr_reg[7]) + begin + `BENCH_ERROR("Bit 7 of LSR register not '1'!"); + -> error_detected; + end + end + else + begin + wait (lsr_reg_read && (rx_fifo_par == 0) && (rx_fifo_frm == 0) && (rx_fifo_brk == 0)); + lsr_reg_bit7_change_allowed = 1'b1; + repeat (2) @(posedge wb_clk); + #2; + lsr_reg_bit7_change_allowed = 0; + // check bit + if (lsr_reg[7]) + begin + `BENCH_ERROR("Bit 7 of LSR register not '0'!"); + -> error_detected; + end + end + end + end + begin: lsr_reg_bit7_changing + forever + begin + wait (~lsr_reg_bit7_change_allowed); + begin + @(lsr_reg[7] or lsr_reg_bit7_change_allowed); + if (~lsr_reg_bit7_change_allowed) + begin + `BENCH_ERROR("Bit 7 of LSR register should not change!"); + -> error_detected; + end + end + end + end + join + end + + +// UART transmitter monitor +//######################### + + // TX FIFO status + always@(tx_fifo_wr_pointer or tx_fifo_rd_pointer) + begin + if (tx_fifo_wr_pointer >= tx_fifo_rd_pointer) + tx_fifo_status = tx_fifo_wr_pointer - tx_fifo_rd_pointer; + else + tx_fifo_status = (5'h1F - tx_fifo_rd_pointer) + tx_fifo_wr_pointer; + end + // TX FIFO and TX data + initial + begin + tx_fifo_wr_pointer = 0; + tx_fifo_rd_pointer = 0; + tx_shift_reg_empty = 1; + tx_fifo_status = 0; + tx_start_bit_edge = 1; + fork + begin:write_tx_shift_reg_read_tx_fifo + forever + begin + wait ((tx_fifo_status !== 0) && tx_shift_reg_empty && tx_start_bit_edge && ~stx_pad_o); + tx_start_bit_edge = 0; + tx_shift_reg = tx_fifo[tx_fifo_rd_pointer]; + tx_shift_reg_empty = 0; + @(testbench.i_uart_device.device_received_last_bit); + repeat (16393) @(posedge wb_clk); + tx_fifo_rd_pointer = tx_fifo_rd_pointer + 1'b1; + @(posedge wb_clk); + if (tx_fifo_status == 0) + begin + `BENCH_MSG("TX FIFO is empty!"); + end + end + end + begin:write_tx_fifo + forever + begin + @(tx_reg_written); // write to FIFO + repeat (1) @(posedge wb_clk); // delay when writing into registers + if (tx_fifo_status <= 5'h0F) + begin + tx_fifo[tx_fifo_wr_pointer] = reg_dat; + tx_fifo_wr_pointer = tx_fifo_wr_pointer + 1'b1; + end + else // FIFO overflow + begin + `BENCH_WARNING("TX FIFO overflow!"); + end + end + end + begin:empty_tx_fifo + forever + begin + wait (fcr_reg[2]); + tx_fifo_wr_pointer = 0; + tx_fifo_rd_pointer = 0; + @(posedge wb_clk); + if (tx_fifo_status == 0) + begin + `BENCH_MSG("TX FIFO is empty!"); + end + end + end + begin:read_tx_shift_reg + forever + begin + @(testbench.i_uart_device.device_received_packet); + // Check data + if (tx_shift_reg != testbench.i_uart_device.rx_data) + begin + `BENCH_ERROR("TX data has ERROR!"); + -> error_detected; + end + else + `BENCH_MSG("TX data correct!"); + if (testbench.i_uart_device.rx_parity_error) + begin + `BENCH_ERROR("TX data has parity ERROR!"); + -> error_detected; + end + else + `BENCH_MSG("TX data parity correct!"); + if (testbench.i_uart_device.rx_framing_error) + begin + `BENCH_ERROR("TX data has framing ERROR!"); + -> error_detected; + end + else + `BENCH_MSG("TX data framing correct!"); + // Set TX FIFO read pointer + tx_start_bit_edge = 1; + repeat (7) @(wb_clk); + if (tx_shift_reg_empty == 0) + begin + tx_shift_reg_empty = 1'b1; + end + else + begin + `BENCH_ERROR("TX shift register empty while transmiting data!"); + -> error_detected; + end + end + end + join + end + + +// UART receiver monitor +//###################### + + // RX FIFO status + always@(rx_fifo_wr_pointer or rx_fifo_rd_pointer) + begin + if (rx_fifo_wr_pointer >= rx_fifo_rd_pointer) + rx_fifo_status = rx_fifo_wr_pointer - rx_fifo_rd_pointer; + else + rx_fifo_status = (5'h1F - rx_fifo_rd_pointer) + rx_fifo_wr_pointer; + end + // RX FIFO and RX data + initial + begin + rx_parity_err = 0; + rx_framing_err = 0; + rx_framing_glitch = 0; + rx_break_int = 0; + rx_overrun_err_occured = 0; + rx_fifo_par = 0; + rx_fifo_frm = 0; + rx_fifo_brk = 0; + rx_shift_reg_full = 0; + rx_fifo_wr_pointer = 0; + rx_fifo_rd_pointer = 0; + rx_fifo_status = 0; + fork + begin:write_rx_shift_reg + forever + begin + @(testbench.i_uart_device.device_sent_packet); + repeat (1) @(posedge wb_clk); + rx_shift_reg = testbench.i_uart_device.sent_data; + rx_parity_err = testbench.i_uart_device.tx_parity_enabled && + (testbench.i_uart_device.tx_parity_wrong || + ( // sample point is BIT_NUM * 2 - 1 => 3, 5, 7... + ((testbench.i_uart_device.tx_glitch_num == (3 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (5 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (7 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (9 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (11 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (13 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (15 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (17 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (19 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (21 * 8 * testbench.i_uart_device.T_divisor)) || + (testbench.i_uart_device.tx_glitch_num == (23 * 8 * testbench.i_uart_device.T_divisor))) && + (testbench.i_uart_device.tx_glitch_num[23:0] < ((testbench.i_uart_device.tx_length + 2'h1) * + 16 * testbench.i_uart_device.T_divisor)) + )); + rx_framing_err = testbench.i_uart_device.tx_framing_wrong; + rx_framing_glitch = (testbench.i_uart_device.tx_glitch_num == ((((testbench.i_uart_device.tx_length + 2'h2 + + testbench.i_uart_device.tx_parity_enabled) * + 2) - 1'b1) * 8 * testbench.i_uart_device.T_divisor)); + rx_break_int = testbench.i_uart_device.tx_break_enable && + (testbench.i_uart_device.tx_break_num[15:0] >= ((testbench.i_uart_device.tx_length + 2'h2 + + testbench.i_uart_device.tx_parity_enabled) * + 16 * testbench.i_uart_device.T_divisor)); + -> testbench.i_uart_device.sent_packet_received; + if (rx_fifo_status > 5'h0F) + rx_overrun_err_occured = 1'b1; + rx_shift_reg_full = 1'b1; + end + end + begin:write_rx_fifo_read_rx_shift_reg + forever + begin + wait (rx_shift_reg_full); + if (rx_fifo_status <= 5'h0F) + begin + rx_fifo_data[rx_fifo_wr_pointer] = testbench.i_uart_device.sent_data; + rx_fifo_par[rx_fifo_wr_pointer] = rx_parity_err; + rx_fifo_frm[rx_fifo_wr_pointer] = rx_framing_err || rx_framing_glitch; + rx_fifo_brk[rx_fifo_wr_pointer] = rx_break_int; + rx_fifo_wr_pointer = rx_fifo_wr_pointer + 1'b1; + end + else // FIFO overflow + begin + `BENCH_WARNING("RX FIFO overflow!"); + end + repeat (1) @(posedge wb_clk); + rx_shift_reg_full = 0; + end + end + begin:empty_rx_fifo + forever + begin + wait (fcr_reg[1]); + rx_fifo_wr_pointer = 0; + rx_fifo_rd_pointer = 0; +// rx_fifo_par = 0; +// rx_fifo_frm = 0; +// rx_fifo_brk = 0; + @(posedge wb_clk); + if (rx_fifo_status == 0) + begin + `BENCH_MSG("RX FIFO is empty!"); + end + end + end + begin:read_rx_fifo + rx_fifo_read = 0; + forever + begin + @(rx_reg_read); + if (rx_fifo_status > 0) + begin + rx_fifo_read = 1'b1; + // Check data + if (rx_fifo_data[rx_fifo_rd_pointer] != reg_dat) + begin + `BENCH_ERROR("RX data has ERROR!"); + -> error_detected; + end + else + begin + `BENCH_MSG("RX data correct!"); + end + // Set RX FIFO read pointer + repeat (1) @(posedge wb_clk); + rx_fifo_read = 0; + rx_fifo_rd_pointer = rx_fifo_rd_pointer + 1'b1; + end + else + begin + `BENCH_WARNING("Reading RX FIFO while RX FIFO is empty!"); + end + + + if ((~rx_fifo_frm[rx_fifo_rd_pointer] && lsr_reg[3]) || + (rx_fifo_frm[rx_fifo_rd_pointer] && ~lsr_reg[3])) + begin + `BENCH_ERROR("RX data has wrong framing ERROR!"); + -> error_detected; + end + else + `BENCH_MSG("RX data has correct framing error!"); + // Set RX FIFO read pointer + repeat (1) @(posedge wb_clk); + rx_fifo_read = 0; + if (rx_fifo_status > 0) + begin +// rx_fifo_par[rx_fifo_rd_pointer] = 1'b0; +// rx_fifo_frm[rx_fifo_rd_pointer] = 1'b0; +// rx_fifo_brk[rx_fifo_rd_pointer] = 1'b0; + rx_fifo_rd_pointer = rx_fifo_rd_pointer + 1'b1; + end + end + end + join + end + + +// UART interrupt monitor +//####################### + + + + +endmodule + + diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench_defines.v b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench_defines.v new file mode 100644 index 00000000..43c21692 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench_defines.v @@ -0,0 +1,89 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_testbench_defines.v //// +//// //// +//// This file is part of the "uart16550" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Author(s): //// +//// - tadej@opencores.org (Tadej Markovic) //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_testbench_defines.v,v $ +// Revision 1.1 2004/03/27 03:55:17 tadejm +// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. +// +// +// + + +`ifdef VERBOSE + // Displaying messages to CRT and providing to "testcase" + `define SEVERE_ERROR(TEXT) $display("Time: %t (%m)", $time); $display("*E, Object %m reporting severe error:"); $display(" %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.severe_err_msg = TEXT; -> testcase.severe_err_event; @(testcase.testbench_log_written) + `define UTILS_WARNING(TEXT) $display("Time: %t (%m)", $time); $display("*W, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.wrn_event; @(testcase.testbench_log_written) + `define UTILS_ERROR(TEXT) $display("Time: %t (%m)", $time); $display("*E, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.err_event; @(testcase.testbench_log_written) + `define BENCH_WARNING(TEXT) $display("Time: %t (%m)", $time); $display("*W, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.wrn_event; @(testcase.testbench_log_written) + `define BENCH_ERROR(TEXT) $display("Time: %t (%m)", $time); $display("*E, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.err_event; @(testcase.testbench_log_written) + `define TC_ERROR(TEXT) $display("Time: %t (%m)", $time); $display("*E, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.err_event; @(testcase.testbench_log_written) + `define DEVICE_WARNING(TEXT) $display("Time: %t (%m)", $time); $display("*W, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.wrn_event; @(testcase.testbench_log_written) + `define DEVICE_ERROR(TEXT) $display("Time: %t (%m)", $time); $display("*E, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.err_event; @(testcase.testbench_log_written) + // Displaying messages to CRT + `define UTILS_MSG(TEXT) $display("Time %t (%m)", $time); $display("*N, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.msg_event; @(testcase.testbench_log_written) + `define UTILS_VAL1(TEXT, VAL) $display("Time %t (%m)", $time); $display("*N, %0s %0h.", TEXT, VAL); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; testcase.val = VAL; -> testcase.val_event; @(testcase.testbench_log_written) + `define BENCH_MSG(TEXT) $display("Time %t (%m)", $time); $display("*N, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.msg_event; @(testcase.testbench_log_written) + `define BENCH_VAL1(TEXT, VAL) $display("Time %t (%m)", $time); $display("*N, %0s %0h.", TEXT, VAL); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; testcase.val = VAL; -> testcase.val_event; @(testcase.testbench_log_written) + `define TC_MSG(TEXT) $display("Time %t (%m)", $time); $display("*N, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.msg_event; @(testcase.testbench_log_written) + `define TC_VAL1(TEXT, VAL) $display("Time %t (%m)", $time); $display("*N, %0s %0h.", TEXT, VAL); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; testcase.val = VAL; -> testcase.val_event; @(testcase.testbench_log_written) +`else + // Displaying messages to CRT and providing to "testcase" + `define SEVERE_ERROR(TEXT) $display("*E, Object %m reporting severe error:"); $display(" %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.severe_err_msg = TEXT; -> testcase.severe_err_event; @(testcase.testbench_log_written) + `define UTILS_WARNING(TEXT) $display("*W, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.wrn_event; @(testcase.testbench_log_written) + `define UTILS_ERROR(TEXT) $display("*E, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.err_event; @(testcase.testbench_log_written) + `define BENCH_WARNING(TEXT) $display("*W, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.wrn_event; @(testcase.testbench_log_written) + `define BENCH_ERROR(TEXT) $display("*E, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.err_event; @(testcase.testbench_log_written) + `define TC_ERROR(TEXT) $display("*E, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.err_event; @(testcase.testbench_log_written) + `define DEVICE_WARNING(TEXT) $display("*W, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.wrn_event; @(testcase.testbench_log_written) + `define DEVICE_ERROR(TEXT) $display("*E, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.err_event; @(testcase.testbench_log_written) + // Displaying messages to CRT + `define UTILS_MSG(TEXT) $display("*N, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.msg_event; @(testcase.testbench_log_written) + `define UTILS_VAL1(TEXT, VAL) $display("*N, %0s %0h.", TEXT, VAL); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; testcase.val = VAL; -> testcase.val_event; @(testcase.testbench_log_written) + `define BENCH_MSG(TEXT) $display("*N, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.msg_event; @(testcase.testbench_log_written) + `define BENCH_VAL1(TEXT, VAL) $display("*N, %0s %0h.", TEXT, VAL); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; testcase.val = VAL; -> testcase.val_event; @(testcase.testbench_log_written) + `define TC_MSG(TEXT) $display("*N, %0s", TEXT); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; -> testcase.msg_event; @(testcase.testbench_log_written) + `define TC_VAL1(TEXT, VAL) $display("*N, %0s %0h.", TEXT, VAL); $sformat(testcase.tim, "Time: %t (%m)", $time); testcase.msg = TEXT; testcase.val = VAL; -> testcase.val_event; @(testcase.testbench_log_written) +`endif + +// Testcase end +`define PROMPT #1000000; log.end_log; $finish diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench_utilities.v b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench_utilities.v new file mode 100644 index 00000000..88eaac27 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_testbench_utilities.v @@ -0,0 +1,323 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_testbench_utilities.v //// +//// //// +//// This file is part of the "uart16550" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Author(s): //// +//// - tadej@opencores.org (Tadej Markovic) //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_testbench_utilities.v,v $ +// Revision 1.1 2004/03/27 03:55:17 tadejm +// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. +// +// +// + + +`include "uart_defines.v" +`include "uart_testbench_defines.v" +`include "wb_model_defines.v" +`include "timescale.v" + +module testbench_utilities; + +// Basic system TASKs +//################### + + // DO_RESET + task do_reset; + begin + testbench.wb_reset = 1'b1; + #1; + `UTILS_MSG("RESET signal asynchronously set."); + end + endtask // do_reset + + // RELEASE_RESET + task release_reset; + begin + @(posedge testbench.wb_clk); + #1; + testbench.wb_reset = 1'b0; + `UTILS_MSG("RESET signal released synchronously to WB clk."); + end + endtask // release_reset + + // DISABLE_CLK_GENERATORS + task disable_clk_generators; + input wb_clk_disable; + input rx_clk_disable; + input tx_clk_disable; + input tx_clk_divided_disable; + begin + `UTILS_MSG("Following clocks are DISABLED:"); + if (wb_clk_disable) + begin + testbench.wb_clk_en = 1'b0; + `UTILS_MSG("- WB_clk"); + end + if (rx_clk_disable) + begin + testbench.i_uart_device.rx_clk_en = 1'b0; + `UTILS_MSG("- RX_clk"); + end + if (tx_clk_disable) + begin + testbench.i_uart_device.tx_clk_en = 1'b0; + `UTILS_MSG("- TX_clk"); + end + if (tx_clk_divided_disable) + begin + testbench.i_uart_device.tx_clk_divided_en = 1'b0; + `UTILS_MSG("- TX_clk_divided"); + end + if (~wb_clk_disable && ~rx_clk_disable && ~tx_clk_disable && ~tx_clk_divided_disable) + begin + `UTILS_MSG("- NO clocks DISABLED"); + end + end + endtask // disable_clk_generators + + // ENABLE_CLK_GENERATORS + task enable_clk_generators; + input wb_clk_enable; + input rx_clk_enable; + input tx_clk_enable; + input tx_clk_divided_enable; + begin + `UTILS_MSG("Following clocks are ENABLED:"); + if (wb_clk_enable) + begin + testbench.wb_clk_en = 1'b1; + `UTILS_MSG("- WB_clk"); + end + if (rx_clk_enable) + begin + testbench.i_uart_device.rx_clk_en = 1'b1; + `UTILS_MSG("- RX_clk"); + end + if (tx_clk_enable) + begin + testbench.i_uart_device.tx_clk_en = 1'b1; + `UTILS_MSG("- TX_clk"); + end + if (tx_clk_divided_enable) + begin + testbench.i_uart_device.tx_clk_divided_en = 1'b1; + `UTILS_MSG("- TX_clk_divided"); + end + if (~wb_clk_enable && ~rx_clk_enable && ~tx_clk_enable && ~tx_clk_divided_enable) + begin + `UTILS_MSG("- NO clocks ENABLED"); + end + end + endtask // enable_clk_generators + + // SET_DEVICE_TX_RX_CLK_PERIOD + task set_device_tx_rx_clk_period; + input [31:0] clk_period; + begin + testbench.i_uart_device.T_clk_period = clk_period; + `UTILS_VAL1("UART DEVICE TX/RX clock period:", clk_period); + end + endtask // set_device_tx_rx_clk_period + + // SET_DEVICE_TX_CLK_DELAY + task set_device_tx_clk_delay; + input [31:0] tx_clk_delay; + begin + testbench.i_uart_device.T_clk_delay = tx_clk_delay; + `UTILS_VAL1("UART DEVICE TX clock delay:", tx_clk_delay); + end + endtask // set_device_tx_clk_delay + + // SET_DEVICE_TX_RX_CLK_DIVISOR + task set_device_tx_rx_clk_divisor; + input [31:0] clk_divisor; + begin + testbench.i_uart_device.T_divisor = clk_divisor; + `UTILS_VAL1("UART DEVICE TX/RX clock divisor:", clk_divisor); + end + endtask // set_device_tx_rx_clk_divisor + + // SET_WB_CLK_PERIOD + task set_wb_clock_period; + input [31:0] clk_period; + begin + testbench.T_wb_clk_period = clk_period; + testbench.i_uart_device.T_clk_period = clk_period; + `UTILS_VAL1("WB & UART DEVICE TX/RX clock period:", clk_period); + end + endtask // set_wb_clock_period + + // WB_CLK_FOLLOWS_DEVICE_RX_CLK + task wb_clk_follows_device_rx_clk; + input [31:0] time_delay_i; + integer time_delay; + begin + time_delay = time_delay_i; + @(posedge testbench.wb_clk); + testbench.wb_clk_en = 1'b0; + @(posedge testbench.i_uart_device.rx_clk); + #time_delay testbench.wb_clk = 1'b1; + testbench.wb_clk_en = 1'b1; + `UTILS_VAL1("WB followed UART DEVICE rising edge RX clock for time delay:", time_delay); + end + endtask // wb_clk_follows_device_rx_clk + + // DEVICE_RX_CLK_FOLLOWS_WB_CLK + task device_rx_clk_follows_wb_clk; + input [31:0] time_delay_i; + integer time_delay; + begin + time_delay = time_delay_i; + @(posedge testbench.i_uart_device.rx_clk); + testbench.i_uart_device.rx_clk_en = 1'b0; + @(posedge testbench.wb_clk); + #time_delay testbench.i_uart_device.rx_clk = 1'b1; + testbench.i_uart_device.rx_clk_en = 1'b1; + `UTILS_VAL1("UART DEVICE RX followed WB rising edge clock for time delay:", time_delay); + end + endtask // device_rx_clk_follows_wb_clk + +// Utility tasks +//############## + + // WAIT_FOR_NUM_OF_WB_CLK + task wait_for_num_of_wb_clk; + input [31:0] num_of_clk; + integer count; + begin + count = 0; + `UTILS_VAL1("Waiting for following number of WB CLK periods:", num_of_clk); + while (count < num_of_clk) + begin + @(testbench.wb_clk); + count = count + 1'b1; + #1; + end + `UTILS_MSG("Waiting expired."); + end + endtask // wait_for_num_of_wb_clk + + // WAIT_RX_FIFO_FULL_REGARDLESS_INT + task wait_rx_fifo_full_regardless_int; + integer count; + begin + count = 0; + `UTILS_MSG("Waiting for RX FIFO to get full regardless of interrupt."); + fork + begin:fifo_full_loop + while (testbench.i_uart_top.regs.receiver.fifo_rx.count < + testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth) // While RX fifo not full + begin + @(testbench.wb_clk); + end + disable counter; + `UTILS_MSG("RX FIFO got full."); + end + begin:counter + while (count < testbench.max_wait_cnt) + begin + @(testbench.wb_clk); + count = count + 1'b1; + #1; + end + disable fifo_full_loop; + `UTILS_ERROR("WAIT counter exceeded max value."); + end + join + end + endtask // wait_rx_fifo_full_regardless_int + + // WAIT_RX_FIFO_FULL_UNLESS_INT + task wait_rx_fifo_full_unless_int; + integer count; + begin + count = 0; + `UTILS_MSG("Waiting for RX FIFO to get full unless interrupt occures before."); + fork + begin:fifo_full_loop + while (testbench.i_uart_top.regs.receiver.fifo_rx.count < + testbench.i_uart_top.regs.receiver.fifo_rx.fifo_depth) // While RX fifo not full + begin + @(testbench.wb_clk); + end + disable counter; + disable int_loop; + `UTILS_MSG("RX FIFO got full."); + end + begin:int_loop + if (testbench.ier_reg[3:0] == 4'h0) + begin + `UTILS_MSG("All interrupts are disabled."); + end + else + begin + `UTILS_MSG("Interrupts are enabled in IE Register."); + `UTILS_VAL1("IER:", testbench.ier_reg); + @(testbench.int_aserted); + `UTILS_MSG("Interrupt is asserted. The pending interrupt of highest priority is in II Register."); + `UTILS_VAL1("IIR:", testbench.iir_reg); + disable counter; + disable fifo_full_loop; + end + end + begin:counter + while (count < testbench.max_wait_cnt) + begin + @(testbench.wb_clk); + count = count + 1'b1; + #1; + end + disable int_loop; + disable fifo_full_loop; + `UTILS_ERROR("WAIT counter exceeded max value."); + end + join + end + endtask // wait_rx_fifo_full_unless_int + + +// UART Initialize TASKs +//###################### + + // POSSIBLE INITIALIZE TASKS - NOW FEW STEPS ARE MADE IN EACH testcase!!! + + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/uart_wb_utilities.v b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_wb_utilities.v new file mode 100644 index 00000000..32b6bfce --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/uart_wb_utilities.v @@ -0,0 +1,362 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_wb_utilities.v //// +//// //// +//// This file is part of the "uart16550" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Author(s): //// +//// - tadej@opencores.org (Tadej Markovic) //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: uart_wb_utilities.v,v $ +// Revision 1.1 2004/03/27 03:55:17 tadejm +// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. +// +// +// + + +`include "uart_defines.v" +`include "uart_testbench_defines.v" +`include "wb_model_defines.v" +`include "timescale.v" + +module uart_wb_utilities; + +// Single read/write TASKs +//######################## + + // SINGLE_READ + task single_read; + input [`UART_ADDR_WIDTH-1:0] read_adr_i; + reg [3:0] read_sel_i; + reg `WBM_MODEL_READ_IN_TYPE read_stim; + reg `WBM_MODEL_READ_OUT_TYPE read_result; + integer master_waits; + integer slave_waits; + integer num_of_reads; + reg fast_b2b; + begin + read_sel_i = 4'hF; + testbench.i_wb_master_model.next_read_adr = read_adr_i; + testbench.i_wb_master_model.next_read_sel = read_sel_i; + testbench.i_wb_master_model.next_read_cti = 3'b000; // Clasic WB + testbench.i_wb_master_model.next_read_bte = $random; // Don't care hwen Clasic WB + master_waits = {$random} % 13; + slave_waits = 4; + num_of_reads = 1; + fast_b2b = 1'b0; + read_stim`WBM_MODEL_READ_WAITS = master_waits; + read_stim`WBM_MODEL_READ_ALLOWED_SLAVE_WAITS = slave_waits; + read_stim`WBM_MODEL_READ_LAST = (num_of_reads == 1); + read_stim`WBM_MODEL_READ_FAST_B2B = fast_b2b; + // Start read + testbench.i_wb_master_model.start_read(read_stim, read_result); + // ACK response + if (read_result`WBM_MODEL_READ_SLAVE_ACK !== 1'b1) + begin + `TC_ERROR("Wishbone master model did not receive expected transfer termination from the design."); + end + // + if (read_result`WBM_MODEL_READ_STIM_ERR !== 1'b0) + begin + `TC_ERROR("No reads done since design's wishbone slave interface responded with an error."); + end + // + if (read_result`WBM_MODEL_READ_DESIGN_ERR !== 1'b0) + begin + `TC_ERROR("Wishbone master model detected a design response error during single read access."); + end + end + endtask // single_read + + // SINGLE_WRITE + task single_write; + input [`UART_ADDR_WIDTH-1:0] write_adr_i; + input [`UART_DATA_WIDTH-1:0] write_dat_i; + reg [3:0] write_sel_i; + reg `WBM_MODEL_WRITE_IN_TYPE write_stim; + reg `WBM_MODEL_WRITE_OUT_TYPE write_result; + integer master_waits; + integer slave_waits; + integer num_of_writes; + reg fast_b2b; + begin + write_sel_i = 4'hF; + testbench.i_wb_master_model.next_write_adr = write_adr_i; + testbench.i_wb_master_model.next_write_sel = write_sel_i; + testbench.i_wb_master_model.next_write_dat = write_dat_i; + testbench.i_wb_master_model.next_write_cti = 3'b000; // Clasic WB + testbench.i_wb_master_model.next_write_bte = $random; // Don't care hwen Clasic WB + master_waits = {$random} % 13; + slave_waits = 4; + num_of_writes = 1; + fast_b2b = 1'b0; + write_stim`WBM_MODEL_WRITE_WAITS = master_waits; + write_stim`WBM_MODEL_WRITE_ALLOWED_SLAVE_WAITS = slave_waits; + write_stim`WBM_MODEL_WRITE_LAST = (num_of_writes == 1); + write_stim`WBM_MODEL_WRITE_FAST_B2B = fast_b2b; + // Start write + testbench.i_wb_master_model.start_write(write_stim, write_result); + // ACK response + if (write_result`WBM_MODEL_WRITE_SLAVE_ACK !== 1'b1) + begin + `TC_ERROR("Wishbone master model did not receive expected transfer termination from the design."); + end + // + if (write_result`WBM_MODEL_WRITE_STIM_ERR !== 1'b0) + begin + `TC_ERROR("No writes done since wishbone master model reported an error."); + end + // + if (write_result`WBM_MODEL_WRITE_DESIGN_ERR !== 1'b0) + begin + `TC_ERROR("Wishbone master model detected a design response error during single write access."); + end + end + endtask // single_write + +// Char read/write TASKs +//###################### + + // READ_CHAR + task read_char; + begin + if (testbench.lcr_reg[7] === 1'b1) // dlab == 1 + begin + `UTILS_ERROR("READING of CHAR from RB Register NOT possible, since DLAB in LC Register is set."); + end + else + begin + `UTILS_MSG("READING of CHAR from UART's RB Register."); + single_read(`UART_REG_RB); + `UTILS_VAL1("Read RBR =", testbench.i_wb_master_model.read_dat); + end + end + endtask // read_char + + // WRITE_CHAR + task write_char; + input [7:0] char_i; + begin + if (testbench.lcr_reg[7] === 1'b1) // dlab == 1 + begin + `UTILS_ERROR("WRITING CHAR to TR Register NOT possible, since DLAB in LC Register is set."); + end + else + begin + `UTILS_MSG("WRITING CHAR to UART's TR Register."); + single_write(`UART_REG_TR, char_i); + `UTILS_VAL1("Write TRR =", testbench.i_wb_master_model.write_dat); + end + end + endtask // write_char + +// Register read/write TASKs +//########################## + + // READ_IER - adr 1 + task read_ier; + begin + if (testbench.lcr_reg[7] === 1'b1) // dlab == 1 + begin + `UTILS_ERROR("READING of IE Register NOT possible, since DLAB in LC Register is set."); + end + else + begin + `UTILS_MSG("READING UART's IE Register."); + single_read(`UART_REG_IE); + `UTILS_VAL1("Read IER =", testbench.i_wb_master_model.read_dat); + end + end + endtask // read_ier + + // WRITE_IER - adr 1 + task write_ier; + input [7:0] data_i; + begin + if (testbench.lcr_reg[7] === 1'b1) // dlab == 1 + begin + `UTILS_ERROR("WRITING to IE Register NOT possible, since DLAB in LC Register is set."); + end + else + begin + `UTILS_MSG("WRITING UART's IE Register."); + single_write(`UART_REG_IE, data_i); + `UTILS_VAL1("Write IER =", testbench.i_wb_master_model.write_dat); + end + end + endtask // write_ier + + // READ_IIR - adr 2 + task read_iir; + begin + `UTILS_MSG("READING UART's II Register."); + single_read(`UART_REG_II); + `UTILS_VAL1("Read IIR =", testbench.i_wb_master_model.read_dat); + end + endtask // read_iir + + // WRITE_FCR - adr 2 + task write_fcr; + input [7:0] data_i; + begin + `UTILS_MSG("WRITING UART's FC Register."); + single_write(`UART_REG_FC, data_i); + `UTILS_VAL1("Write FCR =", testbench.i_wb_master_model.write_dat); + end + endtask // write_fcr + + // READ_LCR - adr 3 + task read_lcr; + begin + `UTILS_MSG("READING UART's LC Register."); + single_read(`UART_REG_LC); + `UTILS_VAL1("Read LCR =", testbench.i_wb_master_model.read_dat); + end + endtask // read_lcr + + // WRITE_LCR - adr 3 + task write_lcr; + input [7:0] data_i; + begin + `UTILS_MSG("WRITING UART's LC Register."); + single_write(`UART_REG_LC, data_i); + `UTILS_VAL1("Write LCR =", testbench.i_wb_master_model.write_dat); + end + endtask // write_lcr + + // WRITE_MCR - adr 4 + task write_mcr; + input [7:0] data_i; + begin + `UTILS_MSG("WRITING UART's MC Register."); + single_write(`UART_REG_MC, data_i); + `UTILS_VAL1("Write MCR =", testbench.i_wb_master_model.write_dat); + end + endtask // write_mcr + + // READ_LSR - adr 5 + task read_lsr; + begin + `UTILS_MSG("READING UART's LS Register."); + single_read(`UART_REG_LS); + `UTILS_VAL1("Read LSR =", testbench.i_wb_master_model.read_dat); + end + endtask // read_lsr + + // READ_MSR - adr 6 + task read_msr; + begin + `UTILS_MSG("READING UART's MS Register."); + single_read(`UART_REG_MS); + `UTILS_VAL1("Read MSR =", testbench.i_wb_master_model.read_dat); + end + endtask // read_msr + + // READ_DLR - adr 0, 1 + task read_dlr; + begin + if (testbench.lcr_reg[7] === 1'b0) // dlab == 0 + begin + // Setting DLAB + `UTILS_MSG("DLAB in LC Register is going to be 1."); + `UTILS_VAL1("Current LCR =", testbench.lcr_reg); + write_lcr(testbench.lcr_reg | 8'h80); + // Reading DL Register + `UTILS_MSG("READING UART's DL Register [15:8]."); + single_read(`UART_REG_DL2); + `UTILS_VAL1("Read DLR [15:8] =", testbench.i_wb_master_model.read_dat); + `UTILS_MSG("READING UART's DL Register [ 7:0]."); + single_read(`UART_REG_DL1); + `UTILS_VAL1("Read DLR [ 7:0] =", testbench.i_wb_master_model.read_dat); + // Resetting DLAB + `UTILS_MSG("DLAB in LC Register is going to be 0."); + write_lcr(testbench.lcr_reg & 8'h7F); + end + else + begin + `UTILS_MSG("DLAB in LC Register is already 1."); + `UTILS_VAL1("Current LCR =", testbench.lcr_reg); + // Reading DL Register + `UTILS_MSG("READING UART's DL Register [15:8]."); + single_read(`UART_REG_DL2); + `UTILS_VAL1("Read DLR [15:8] =", testbench.i_wb_master_model.read_dat); + `UTILS_MSG("READING UART's DL Register [ 7:0]."); + single_read(`UART_REG_DL1); + `UTILS_VAL1("Read DLR [ 7:0] =", testbench.i_wb_master_model.read_dat); + end + end + endtask // read_dlr + + // WRITE_DLR - adr 0, 1 + task write_dlr; + input [15:0] data_i; + begin + if (testbench.lcr_reg[7] === 1'b0) // dlab == 0 + begin + // Setting DLAB + `UTILS_MSG("DLAB in LC Register is going to be 1."); + `UTILS_VAL1("Current LCR =", testbench.lcr_reg); + write_lcr(testbench.lcr_reg | 8'h80); + // Writing DL Register + `UTILS_MSG("WRITING UART's DL Register [15:8]."); + single_write(`UART_REG_DL2, data_i[15:8]); + `UTILS_VAL1("Write DLR [15:8] =", testbench.i_wb_master_model.write_dat); + `UTILS_MSG("WRITING UART's DL Register [ 7:0]."); + single_write(`UART_REG_DL1, data_i[ 7:0]); + `UTILS_VAL1("Write DLR [ 7:0] =", testbench.i_wb_master_model.write_dat); + // Resetting DLAB + `UTILS_MSG("DLAB in LC Register is going to be 0."); + write_lcr(testbench.lcr_reg & 8'h7F); + end + else + begin + `UTILS_MSG("DLAB in LC Register is already 1."); + `UTILS_VAL1("Current LCR =", testbench.lcr_reg); + // Writing DL Register + `UTILS_MSG("WRITING UART's DL Register [15:8]."); + single_write(`UART_REG_DL2, data_i[15:8]); + `UTILS_VAL1("Write DLR [15:8] =", testbench.i_wb_master_model.write_dat); + `UTILS_MSG("WRITING UART's DL Register [ 7:0]."); + single_write(`UART_REG_DL1, data_i[ 7:0]); + `UTILS_VAL1("Write DLR [ 7:0] =", testbench.i_wb_master_model.write_dat); + end + end + endtask // write_dlr + + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/vapi.log b/usrp2/fpga/opencores/uart16550/bench/verilog/vapi.log new file mode 100644 index 00000000..ebbfae16 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/vapi.log @@ -0,0 +1,117 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// vapi.log //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Device interface for testing purposes //// +//// //// +//// Known problems (limits): //// +//// //// +//// To Do: //// +//// Nothing. //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created and updated: (See log for the revision history) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: vapi.log,v $ +// Revision 1.1 2002/01/25 08:54:56 mohor +// UART PHY added. Files are fully operational, working on HW. +// +// +// +// +// + + +001000020 // devisor 0x32 +002000300 // rx lcr 8n1 + +// Receive +10000034a // Receive J +100000361 // Receive a +100000363 // Receive c +10000030a // Receive \n + +// Send +000000371 // Transmit q - switching to interrupt mode +100000353 // Receive S +100000377 // Receive w +10000030a // Receive \n +006000020 // wait 32 tx cycles +000000331 // Transmit 1 +000000332 // Transmit 2 +000000333 // Transmit 3 +000000334 // Transmit 4 +000000335 // Transmit 5 +000000336 // Transmit 6 +000000337 // Transmit 7 +000000338 // Transmit 8 +000000339 // Transmit 9 +000000361 // Transmit a +000000362 // Transmit b +000000363 // Transmit c +000000364 // Transmit d +000000365 // Transmit e +000000366 // Transmit f +006000040 // wait 64 tx cycles +100000331 // Receive 1 +100000332 // Receive 2 +100000333 // Receive 3 +100000334 // Receive 4 +100000335 // Receive 5 +100000336 // Receive 6 +100000337 // Receive 7 +100000338 // Receive 8 +100000339 // Receive 9 +100000341 // Receive A +100000342 // Receive B +100000343 // Receive C +100000344 // Receive D +100000345 // Receive E +100000346 // Receive F + +200000000 // Exit simulation diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/wb_mast.v b/usrp2/fpga/opencores/uart16550/bench/verilog/wb_mast.v new file mode 100644 index 00000000..df257076 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/wb_mast.v @@ -0,0 +1,640 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Master Model //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_mast.v,v 1.1 2001/12/03 21:44:23 gorban Exp $ +// +// $Date: 2001/12/03 21:44:23 $ +// $Revision: 1.1 $ +// $Author: gorban $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: wb_mast.v,v $ +// Revision 1.1 2001/12/03 21:44:23 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// +// +// +// +// + +/* + +task mem_fill; + +- Fills local burst read (rd_buf[]) and write(wr_buf[]) buffers with random values. + + +task wb_wr1( 32 bit address, 4 bit byte select, 32 bit write data); + +- Performs a single WISHBONE write + + +task wb_wr4( 32 bit address, 4 bit byte select, integer delay, + 32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4); + +- Performs 4 consecutive WISHBONE writes +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_wr_mult( 32 bit address, 4 bit byte select, integer delay, + integer count); + +- Simular to wb_wr4, except it pwrforms "count" number of write cycles. + The data is taken from the internal wr_bub[] memory. +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_rmw( 32 bit address, 4 bit byte select, integer delay, + integer rcount, integer wcount); + +- This task performs "rcount" read cycles, followed by wcount write cycles. +- read data is placed in to the internal rd_buf[] memory, write data is + taken from the internal wr_buf[] memory. +- Strobe is deasserted between writes for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_rd1( 32 bit address, 4 bit byte select, 32 bit read data); + +- Performs a single WISHBONE write + + +task wb_rd4( 32 bit address, 4 bit byte select, integer delay, + 32 bit data 1, 32 bit data 2, 32 bit data 3, 32 bit data 4); + +- Performs 4 consecutive WISHBONE reads +- Strobe is deasserted between reads for 'delay' number of cycles + (This simulates wait state insertion ...) + + +task wb_rd_mult( 32 bit address, 4 bit byte select, integer delay, + integer count); + +- Simular to wb_rd4, except it pwrforms "count" number of read cycles. + The data is read in to the internal rd_buf[] memory. +- Strobe is deasserted between reads for 'delay' number of cycles + (This simulates wait state insertion ...) + + +*/ + + +//`include "wb_model_defines.v" + +module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); + +input clk, rst; +output [31:0] adr; +input [31:0] din; +output [31:0] dout; +output cyc, stb; +output [3:0] sel; +output we; +input ack, err, rty; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +parameter mem_size = 4096; + +reg [31:0] adr; +reg [31:0] dout; +reg cyc, stb; +reg [3:0] sel; +reg we; + +reg [31:0] rd_mem[mem_size:0]; +reg [31:0] wr_mem[mem_size:0]; +integer rd_cnt; +integer wr_cnt; + +//////////////////////////////////////////////////////////////////// +// +// Memory Logic +// + +initial + begin + adr = 32'hxxxx_xxxx; + dout = 32'hxxxx_xxxx; + cyc = 0; + stb = 0; + sel = 4'hx; + we = 1'hx; + rd_cnt = 0; + wr_cnt = 0; + #1; + $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); + end + + + +task mem_fill; + +integer n; +begin +rd_cnt = 0; +wr_cnt = 0; +for(n=0;n error_event ; + end + + if (wb_rst_i === `WB_MODEL_RST_ACTIVE) + begin + reset_done = 1'b0 ; + end + end +end +begin + forever + begin + @(wb_rst_i) ; + if (wb_rst_i === `WB_MODEL_RST_ACTIVE) + begin + @(posedge wb_clk_i or wb_rst_i) ; + if (wb_rst_i !== `WB_MODEL_RST_ACTIVE) + begin + error_message = "Reset de-activated prior to at least one positive clock transition" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + else + begin + reset_done = 1'b1 ; + end + end + end +end +join + +always@(wb_rst_i) +begin + if (wb_rst_i === `WB_MODEL_RST_ACTIVE) + wbm_cyc_o <= 1'b0 ; +end + +reg access_in_progress ; +initial access_in_progress = 1'b0 ; + +task start_write ; + input `WBM_MODEL_WRITE_IN_TYPE write_stim_i ; + output `WBM_MODEL_WRITE_OUT_TYPE write_res_o ; + reg [31: 0] num_of_slave_waits ; + reg end_access ; +begin:main + + write_res_o = 'h0 ; + + if (access_in_progress === 1'b1) + begin + error_message = "Task called when some other access was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + write_res_o`WBM_MODEL_WRITE_STIM_ERR = 1'b1 ; + disable main ; + end + + if (reset_done !== 1'b1) + begin + error_message = "Task called before reset was applied to the design" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + write_res_o`WBM_MODEL_WRITE_STIM_ERR = 1'b1 ; + disable main ; + end + + access_in_progress = 1'b1 ; + end_access = write_stim_i`WBM_MODEL_WRITE_LAST ; + + if (write_stim_i`WBM_MODEL_WRITE_FAST_B2B !== 1'b1) + @(posedge wb_clk_i) ; + + wbm_cyc_o <= #(Tperiod - Tsetup) 1'b1 ; + + insert_waits(write_stim_i`WBM_MODEL_WRITE_WAITS, 'h0, num_of_slave_waits) ; + + if ((num_of_slave_waits ^ num_of_slave_waits) === 'h0) + begin + error_message = "Slave responded to initial write access" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + num_of_slave_waits = 0 ; + + wbm_stb_o <= #(Tperiod - Tsetup) 1'b1 ; + wbm_we_o <= #(Tperiod - Tsetup) 1'b1 ; + wbm_adr_o <= #(Tperiod - Tsetup) next_write_adr ; + wbm_dat_o <= #(Tperiod - Tsetup) get_write_dat(next_write_dat, next_write_sel) ; + wbm_sel_o <= #(Tperiod - Tsetup) next_write_sel ; + wbm_cti_o <= #(Tperiod - Tsetup) next_write_cti ; + wbm_bte_o <= #(Tperiod - Tsetup) next_write_bte ; + + -> write_accepted ; + + @(posedge wb_clk_i) ; + + while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < write_stim_i`WBM_MODEL_WRITE_ALLOWED_SLAVE_WAITS)) + begin + num_of_slave_waits = num_of_slave_waits + 1'b1 ; + write_adr = wbm_adr_o ; + write_sel = wbm_sel_o ; + write_dat = wbm_dat_o ; + -> write_request ; + @(posedge wb_clk_i) ; + end + + if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0)) + begin + error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end_access = 1'b1 ; + write_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ; + end + else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1) + begin + error_message = "Cycle terminated because invalid slave response was received" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end_access = 1'b1 ; + write_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ; + end + else + begin + write_res_o`WBM_MODEL_WRITE_SLAVE_WAITS = num_of_slave_waits ; + write_res_o`WBM_MODEL_WRITE_SLAVE_ACK = wbm_ack_i ; + write_res_o`WBM_MODEL_WRITE_SLAVE_ERR = wbm_err_i ; + write_res_o`WBM_MODEL_WRITE_SLAVE_RTY = wbm_rty_i ; + + if (wbm_ack_i === 1'b1) + begin + write_adr = wbm_adr_o ; + write_dat = wbm_dat_o ; + write_sel = wbm_sel_o ; + -> write_transfer ; + end + end + + if (end_access) + begin + wbm_cyc_o <= #(Thold) 1'b0 ; + wbm_stb_o <= #(Thold) 1'bx ; + wbm_we_o <= #(Thold) 1'bx ; + wbm_sel_o <= #(Thold) 'hx ; + wbm_adr_o <= #(Thold) 'hx ; + wbm_dat_o <= #(Thold) 'hx ; + wbm_cti_o <= #(Thold) 'hx ; + wbm_bte_o <= #(Thold) 'hx ; + access_in_progress = 1'b0 ; + end +end +endtask // start_write + +task subsequent_write ; + input `WBM_MODEL_WRITE_IN_TYPE write_stim_i ; + output `WBM_MODEL_WRITE_OUT_TYPE write_res_o ; + reg [31: 0] num_of_slave_waits ; + reg end_access ; +begin:main + + write_res_o = 'h0 ; + + if (access_in_progress !== 1'b1) + begin + error_message = "Task called when no access was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + write_res_o`WBM_MODEL_WRITE_STIM_ERR = 1'b1 ; + disable main ; + end + + end_access = write_stim_i`WBM_MODEL_WRITE_LAST ; + + insert_waits(write_stim_i`WBM_MODEL_WRITE_WAITS, 'h0, num_of_slave_waits) ; + + if ((num_of_slave_waits ^ num_of_slave_waits) !== 'h0) + begin + num_of_slave_waits = write_stim_i`WBM_MODEL_WRITE_WAITS ; + end + + wbm_stb_o <= #(Tperiod - Tsetup) 1'b1 ; + wbm_we_o <= #(Tperiod - Tsetup) 1'b1 ; + wbm_adr_o <= #(Tperiod - Tsetup) next_write_adr ; + wbm_dat_o <= #(Tperiod - Tsetup) get_write_dat(next_write_dat, next_write_sel) ; + wbm_sel_o <= #(Tperiod - Tsetup) next_write_sel ; + wbm_cti_o <= #(Tperiod - Tsetup) next_write_cti ; + wbm_bte_o <= #(Tperiod - Tsetup) next_write_bte ; + + -> write_accepted ; + + @(posedge wb_clk_i) ; + + while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < write_stim_i`WBM_MODEL_WRITE_ALLOWED_SLAVE_WAITS)) + begin + num_of_slave_waits = num_of_slave_waits + 1'b1 ; + write_adr = wbm_adr_o ; + write_sel = wbm_sel_o ; + write_dat = wbm_dat_o ; + -> write_request ; + @(posedge wb_clk_i) ; + end + + if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0)) + begin + error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end_access = 1'b1 ; + write_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ; + end + else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1) + begin + error_message = "Cycle terminated because invalid slave response was received" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end_access = 1'b1 ; + write_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ; + end + else + begin + write_res_o`WBM_MODEL_WRITE_SLAVE_WAITS = num_of_slave_waits ; + write_res_o`WBM_MODEL_WRITE_SLAVE_ACK = wbm_ack_i ; + write_res_o`WBM_MODEL_WRITE_SLAVE_ERR = wbm_err_i ; + write_res_o`WBM_MODEL_WRITE_SLAVE_RTY = wbm_rty_i ; + + if (wbm_ack_i === 1'b1) + begin + write_adr = wbm_adr_o ; + write_dat = wbm_dat_o ; + write_sel = wbm_sel_o ; + -> write_transfer ; + end + end + + if (end_access) + begin + wbm_cyc_o <= #(Thold) 1'b0 ; + wbm_stb_o <= #(Thold) 1'bx ; + wbm_we_o <= #(Thold) 1'bx ; + wbm_sel_o <= #(Thold) 'hx ; + wbm_adr_o <= #(Thold) 'hx ; + wbm_dat_o <= #(Thold) 'hx ; + wbm_cti_o <= #(Thold) 'hx ; + wbm_bte_o <= #(Thold) 'hx ; + access_in_progress = 1'b0 ; + end +end +endtask // subsequent_write + +task start_read ; + input `WBM_MODEL_READ_IN_TYPE read_stim_i ; + output `WBM_MODEL_READ_OUT_TYPE read_res_o ; + reg [31: 0] num_of_slave_waits ; + reg end_access ; +begin:main + + read_res_o = 'h0 ; + + if (access_in_progress === 1'b1) + begin + error_message = "Task called when some other access was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + read_res_o`WBM_MODEL_READ_STIM_ERR = 1'b1 ; + disable main ; + end + + if (reset_done !== 1'b1) + begin + error_message = "Task called before reset was applied to the design" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + read_res_o`WBM_MODEL_READ_STIM_ERR = 1'b1 ; + disable main ; + end + + access_in_progress = 1'b1 ; + end_access = read_stim_i`WBM_MODEL_READ_LAST ; + + if (read_stim_i`WBM_MODEL_READ_FAST_B2B !== 1'b1) + @(posedge wb_clk_i) ; + + wbm_cyc_o <= #(Tperiod - Tsetup) 1'b1 ; + + insert_waits(read_stim_i`WBM_MODEL_READ_WAITS, 'h0, num_of_slave_waits) ; + + if ((num_of_slave_waits ^ num_of_slave_waits) === 'h0) + begin + error_message = "Slave responded to initial read access" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + num_of_slave_waits = 0 ; + + wbm_stb_o <= #(Tperiod - Tsetup) 1'b1 ; + wbm_we_o <= #(Tperiod - Tsetup) 1'b0 ; + wbm_adr_o <= #(Tperiod - Tsetup) next_read_adr ; + wbm_sel_o <= #(Tperiod - Tsetup) next_read_sel ; + wbm_cti_o <= #(Tperiod - Tsetup) next_read_cti ; + wbm_bte_o <= #(Tperiod - Tsetup) next_read_bte ; + + -> read_accepted ; + + @(posedge wb_clk_i) ; + + while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < read_stim_i`WBM_MODEL_READ_ALLOWED_SLAVE_WAITS)) + begin + num_of_slave_waits = num_of_slave_waits + 1'b1 ; + read_adr = wbm_adr_o ; + read_sel = wbm_sel_o ; + -> read_request ; + @(posedge wb_clk_i) ; + end + + if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0)) + begin + error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end_access = 1'b1 ; + read_res_o`WBM_MODEL_READ_DESIGN_ERR = 1'b1 ; + end + else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1) + begin + error_message = "Cycle terminated because invalid slave response was received" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end_access = 1'b1 ; + read_res_o`WBM_MODEL_READ_DESIGN_ERR = 1'b1 ; + end + else + begin + read_res_o`WBM_MODEL_READ_SLAVE_WAITS = num_of_slave_waits ; + read_res_o`WBM_MODEL_READ_SLAVE_ACK = wbm_ack_i ; + read_res_o`WBM_MODEL_READ_SLAVE_ERR = wbm_err_i ; + read_res_o`WBM_MODEL_READ_SLAVE_RTY = wbm_rty_i ; + + if (wbm_ack_i === 1'b1) + begin + read_adr = wbm_adr_o ; + read_dat = wbm_dat_i ; + read_sel = wbm_sel_o ; + -> read_transfer ; + end + end + + if (end_access) + begin + wbm_cyc_o <= #(Thold) 1'b0 ; + wbm_stb_o <= #(Thold) 1'bx ; + wbm_we_o <= #(Thold) 1'bx ; + wbm_sel_o <= #(Thold) 'hx ; + wbm_adr_o <= #(Thold) 'hx ; + wbm_cti_o <= #(Thold) 'hx ; + wbm_bte_o <= #(Thold) 'hx ; + access_in_progress = 1'b0 ; + end +end +endtask // start_read + +task subsequent_read ; + input `WBM_MODEL_READ_IN_TYPE read_stim_i ; + output `WBM_MODEL_READ_OUT_TYPE read_res_o ; + reg [31: 0] num_of_slave_waits ; + reg end_access ; +begin:main + + read_res_o = 'h0 ; + + if (access_in_progress !== 1'b1) + begin + error_message = "Task called when no access was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + read_res_o`WBM_MODEL_READ_STIM_ERR = 1'b1 ; + disable main ; + end + + end_access = read_stim_i`WBM_MODEL_READ_LAST ; + + insert_waits(read_stim_i`WBM_MODEL_READ_WAITS, 'h1, num_of_slave_waits) ; + + if ((num_of_slave_waits ^ num_of_slave_waits) !== 'h0) + begin + num_of_slave_waits = read_stim_i`WBM_MODEL_READ_WAITS ; + end + + wbm_stb_o <= #(Tperiod - Tsetup) 1'b1 ; + wbm_we_o <= #(Tperiod - Tsetup) 1'b0 ; + wbm_adr_o <= #(Tperiod - Tsetup) next_read_adr ; + wbm_sel_o <= #(Tperiod - Tsetup) next_read_sel ; + wbm_cti_o <= #(Tperiod - Tsetup) next_read_cti ; + wbm_bte_o <= #(Tperiod - Tsetup) next_read_bte ; + + -> read_accepted ; + + @(posedge wb_clk_i) ; + + while((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) & (num_of_slave_waits < read_stim_i`WBM_MODEL_READ_ALLOWED_SLAVE_WAITS)) + begin + num_of_slave_waits = num_of_slave_waits + 1'b1 ; + read_adr = wbm_adr_o ; + read_sel = wbm_sel_o ; + -> read_request ; + @(posedge wb_clk_i) ; + end + + if ((wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0)) + begin + error_message = "Cycle terminated because allowed number of slave wait states constraint violation" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end_access = 1'b1 ; + read_res_o`WBM_MODEL_READ_DESIGN_ERR = 1'b1 ; + end + else if ((wbm_ack_i + wbm_err_i + wbm_rty_i) !== 'h1) + begin + error_message = "Cycle terminated because invalid slave response was received" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end_access = 1'b1 ; + read_res_o`WBM_MODEL_WRITE_DESIGN_ERR = 1'b1 ; + end + else + begin + read_res_o`WBM_MODEL_READ_SLAVE_WAITS = num_of_slave_waits ; + read_res_o`WBM_MODEL_READ_SLAVE_ACK = wbm_ack_i ; + read_res_o`WBM_MODEL_READ_SLAVE_ERR = wbm_err_i ; + read_res_o`WBM_MODEL_READ_SLAVE_RTY = wbm_rty_i ; + + if (wbm_ack_i === 1'b1) + begin + read_adr = wbm_adr_o ; + read_dat = wbm_dat_i ; + read_sel = wbm_sel_o ; + -> read_transfer ; + end + end + + if (end_access) + begin + wbm_cyc_o <= #(Thold) 1'b0 ; + wbm_stb_o <= #(Thold) 1'bx ; + wbm_we_o <= #(Thold) 1'bx ; + wbm_sel_o <= #(Thold) 'hx ; + wbm_adr_o <= #(Thold) 'hx ; + wbm_cti_o <= #(Thold) 'hx ; + wbm_bte_o <= #(Thold) 'hx ; + access_in_progress = 1'b0 ; + end +end +endtask // subsequent_read + +task insert_waits ; + input [31: 0] num_of_waits_i ; + input read_req_on_wait_i ; + output [31: 0] num_of_slave_waits ; + reg [31: 0] cur_num_of_waits ; +begin + num_of_slave_waits = 'hx ; + + for (cur_num_of_waits = 0 ; cur_num_of_waits < num_of_waits_i ; cur_num_of_waits = cur_num_of_waits + 1'b1) + begin + wbm_stb_o <= #(Thold) 1'b0 ; + wbm_adr_o <= #(Thold) 'hx ; + wbm_sel_o <= #(Thold) 'hx ; + wbm_we_o <= #(Thold) 'hx ; + wbm_dat_o <= #(Thold) 'hx ; + wbm_cti_o <= #(Thold) 'hx ; + wbm_bte_o <= #(Thold) 'hx ; + + @(posedge wb_clk_i) ; + + if (read_req_on_wait_i) + begin + if ( (wbm_ack_i === 1'b0) & (wbm_err_i === 1'b0) & (wbm_rty_i === 1'b0) ) + begin + if ( (next_read_cti === 'h1) | (next_read_cti === 'h2) | (next_read_cti === 'h7) ) + begin + read_adr = next_read_adr ; + read_sel = next_read_sel ; + -> read_request ; + end + end + end + + if ((num_of_slave_waits ^ num_of_slave_waits) !== 'h0) + begin + if ((wbm_ack_i !== 1'b0) | (wbm_err_i !== 1'b0) | (wbm_rty_i !== 1'b0)) + num_of_slave_waits = cur_num_of_waits ; + end + end +end +endtask + +always@(posedge wb_clk_i) +begin:wb_monitoring_blk + reg burst_in_progress ; + reg ack_prev ; + reg rty_prev ; + reg err_prev ; + reg stb_prev ; + reg cyc_prev ; + reg [wb_dat_width - 1:0] sdat_prev ; + + ack_prev <= wbm_ack_i ; + rty_prev <= wbm_rty_i ; + err_prev <= wbm_err_i ; + stb_prev <= wbm_stb_o ; + cyc_prev <= wbm_cyc_o ; + sdat_prev <= wbm_dat_i ; + + if (wb_rst_i === `WB_MODEL_RST_ACTIVE) + begin + if (wbm_ack_i !== 1'b0) + begin + error_message = "ACK input signal was not de-asserted while reset was asserted" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + if (wbm_err_i !== 1'b0) + begin + error_message = "ERR input signal was not de-asserted while reset was asserted" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + if (wbm_rty_i !== 1'b0) + begin + error_message = "RTY input signal was not de-asserted while reset was asserted" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + burst_in_progress <= 1'b0 ; + end + else + begin + if (wbm_cyc_o !== 1'b1) + begin + if (wbm_ack_i !== 1'b0) + begin + error_message = "ACK input signal was asserted while no cycle was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + if (wbm_err_i !== 1'b0) + begin + error_message = "ERR input signal was asserted while no cycle was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + if (wbm_rty_i !== 1'b0) + begin + error_message = "RTY input signal was asserted while no cycle was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + end + else + begin + if (burst_in_progress !== 1'b1) + begin + if ((wbm_ack_i !== 1'b0) & (wbm_stb_o !== 1'b1)) + begin + error_message = "ACK input signal was asserted while STB was de-asserted and no burst was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + if ((wbm_err_i !== 1'b0) & (wbm_stb_o !== 1'b1)) + begin + error_message = "ERR input signal was asserted while STB was de-asserted and no burst was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + if ((wbm_rty_i !== 1'b0) & (wbm_stb_o !== 1'b1)) + begin + error_message = "RTY input signal was asserted while STB was de-asserted and no burst was in progress" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + end + else + begin + if ((ack_prev !== 1'b0) & (stb_prev !== 1'b1)) + begin + if (wbm_ack_i !== 1'b1) + begin + error_message = "Slave de-asserted ACK signal during burst cycle without receiving STB asserted" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + if (wbm_we_o !== 'b1) + begin + if (sdat_prev !== wbm_dat_i) + begin + error_message = "Slave changed the value of data output bus during burst cycle without receiving STB asserted" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + end + end + + if ((rty_prev !== 1'b0) & (stb_prev !== 1'b1) & (wbm_rty_i !== 1'b1)) + begin + error_message = "Slave de-asserted RTY signal during burst cycle without receiving STB asserted" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + + if ((err_prev !== 1'b0) & (stb_prev !== 1'b1) & (wbm_err_i !== 1'b1)) + begin + error_message = "Slave de-asserted ERR signal during burst cycle without receiving STB asserted" ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + end + + if (wbm_stb_o === 1'b1) + begin + case (wbm_cti_o) + 3'b000:burst_in_progress <= 1'b0 ; + 3'b001:burst_in_progress <= 1'b1 ; + 3'b010:burst_in_progress <= 1'b1 ; + 3'b011:burst_in_progress <= 1'b0 ; + 3'b100:burst_in_progress <= 1'b0 ; + 3'b101:burst_in_progress <= 1'b0 ; + 3'b110:burst_in_progress <= 1'b0 ; + 3'b111:if (wbm_ack_i === 1'b1) burst_in_progress <= 1'b0 ; + default: + begin + error_message = "WISHBONE master sent invalid cycle type identifier" ; + burst_in_progress <= 1'bx ; + `WB_MODEL_ERR_MSG(error_message) ; + -> error_event ; + end + endcase + + if (wbm_err_i === 1'b1) + burst_in_progress <= 1'b0 ; + + if (wbm_rty_i === 1'b1) + burst_in_progress <= 1'b0 ; + + end + end + end +end + +function [wb_dat_width - 1:0] get_write_dat ; + input [wb_dat_width - 1:0] dat_i ; + input [wb_sel_width - 1:0] sel_i ; + + integer cur_bit ; + reg [wb_dat_width - 1:0] dat_o ; +begin + for (cur_bit = 0 ; cur_bit < wb_dat_width ; cur_bit = cur_bit + 1'b1) + begin + if (sel_i[cur_bit >> 3] === 1'b1) + dat_o[cur_bit] = dat_i[cur_bit] ; + else + dat_o[cur_bit] = 1'bx ; + end + + get_write_dat = dat_o ; +end +endfunction // get_write_dat + +endmodule + diff --git a/usrp2/fpga/opencores/uart16550/bench/verilog/wb_model_defines.v b/usrp2/fpga/opencores/uart16550/bench/verilog/wb_model_defines.v new file mode 100644 index 00000000..16a2ca16 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/verilog/wb_model_defines.v @@ -0,0 +1,82 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wb_model_defines.v //// +//// //// +//// This file is part of the "uart16550" project //// +//// http://www.opencores.org/projects/uart16550/ //// +//// //// +//// Author(s): //// +//// - mihad@opencores.org (Miha Dolenc) //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: wb_model_defines.v,v $ +// Revision 1.1 2004/03/27 03:55:17 tadejm +// Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. +// +// +// + + +`define WB_MODEL_RST_ACTIVE 1'b1 +`define WB_MODEL_ERR_MSG(TEXT) $display("Error detected at time %t!", $time) ; $display("%m reports: %0s.", TEXT) ; testcase.msg = TEXT ; -> testcase.err_event + +`define WBM_MODEL_WRITE_IN_TYPE [65: 0] +`define WBM_MODEL_WRITE_WAITS [31: 0] +`define WBM_MODEL_WRITE_ALLOWED_SLAVE_WAITS [63:32] +`define WBM_MODEL_WRITE_LAST [64:64] +`define WBM_MODEL_WRITE_FAST_B2B [65:65] + +`define WBM_MODEL_WRITE_OUT_TYPE [36: 0] +`define WBM_MODEL_WRITE_SLAVE_WAITS [31: 0] +`define WBM_MODEL_WRITE_STIM_ERR [32:32] +`define WBM_MODEL_WRITE_DESIGN_ERR [33:33] +`define WBM_MODEL_WRITE_SLAVE_ACK [34:34] +`define WBM_MODEL_WRITE_SLAVE_ERR [35:35] +`define WBM_MODEL_WRITE_SLAVE_RTY [36:36] + +`define WBM_MODEL_READ_IN_TYPE [65: 0] +`define WBM_MODEL_READ_WAITS [31: 0] +`define WBM_MODEL_READ_ALLOWED_SLAVE_WAITS [63:32] +`define WBM_MODEL_READ_LAST [64:64] +`define WBM_MODEL_READ_FAST_B2B [65:65] + +`define WBM_MODEL_READ_OUT_TYPE [36: 0] +`define WBM_MODEL_READ_SLAVE_WAITS [31: 0] +`define WBM_MODEL_READ_STIM_ERR [32:32] +`define WBM_MODEL_READ_DESIGN_ERR [33:33] +`define WBM_MODEL_READ_SLAVE_ACK [34:34] +`define WBM_MODEL_READ_SLAVE_ERR [35:35] +`define WBM_MODEL_READ_SLAVE_RTY [36:36] + diff --git a/usrp2/fpga/opencores/uart16550/bench/vhdl/.keepme b/usrp2/fpga/opencores/uart16550/bench/vhdl/.keepme new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Entries b/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Entries new file mode 100644 index 00000000..7af05a67 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Entries @@ -0,0 +1,2 @@ +/.keepme/1.1/Sun Aug 12 18:52:37 2001// +D diff --git a/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Repository b/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Repository new file mode 100644 index 00000000..f9f65b2e --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Repository @@ -0,0 +1 @@ +uart16550/bench/vhdl diff --git a/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Root b/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Template b/usrp2/fpga/opencores/uart16550/bench/vhdl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/uart16550/doc/CHANGES.txt b/usrp2/fpga/opencores/uart16550/doc/CHANGES.txt new file mode 100644 index 00000000..7e427eb1 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/doc/CHANGES.txt @@ -0,0 +1,111 @@ +Note: This Changes file is being maintained since 25.5.2001. + +29.07.2002 +~~~~~~~~~~ +Reverted to have uart_defines.v file to be included in the verilog +files. It seems that it's been a bad idea in the first place. + +22.07.2002 +~~~~~~~~~~ +Notice that this file hasn't been updated for a while so not all changed are present. + +Bug Fixes: + * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. + Problem reported by Kenny.Tung. + * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. + +Improvements: + * Made FIFO's as general inferrable memory where possible. + So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). + This saves about 1/3 of the Slice count and reduces P&R and synthesis times. + + * Added optional baudrate output (baud_o). + This is identical to BAUDOUT* signal on 16550 chip. + It outputs 16xbit_clock_rate - the divided clock. + It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. + +Note: + The uart_defines.v file is no longer included in the source files. + So keep this in mind when doing simulation. Add it manually. + I've done this, so that you could you your own define files for + different configurations. I need this for the IrDA core I develop. + You can just uncomment the `includes if you want the old behaviour. + The uart_fifo.v file is no longer used. Intead uart_rfifo.v and uart_tfifo.v + file are now present. Also raminfr.v in the new inferred ram module. + + Check the new core and I hope you'll like it. + +10.08.2001 +~~~~~~~~~~ +* Modified naming of top signals and defines to be unique and easy to integrate +* Changed the directory structure of the core to new structure as described in OpenCores + coding guidelines. !!! +* Fixed (I hope) the detection of break condition +* Added top level parameters for data width and address line width + +23.06.2001 +~~~~~~~~~~ + +* With the help of Bob Kirstein another two bugs were fixed: + 1. Trasmitter was sending stop bit two 16xclock cycle slonger than needed. + 2. Receiver was losing 1 16xclock cycle on each character and went out of sync. + +* Major change: + I have modified the divisor latch register to be 16-bit long instead of 32 as I thought was + necessary for higher speed systems. Thanks to Rick Wright for pointing this out. + So now, DL3 and DL4 register bytes are not used. + Documentation is updated to follow this change. + +* Note that more than 1 stop bit in a byte i snot implemented. + +2.05.2001 +~~~~~~~~~ + +* Fixed transmitter and receiver - the start and the stop bits were sent and received complemented. + Big thanks go to Bob Kirstein for pointing this out to me. + + +31.05.2001 +~~~~~~~~~~ + +* Minor changes in register reading code +* Changed FCR to be 2 bits wide (reset bits are not needed) and instead enabled the rx_reset and tx_reset + signals which I forgot to implement. +* Changed defines for FCR. +* Cleaned ports that were not connected in top-level. +* Changed the code to have only one FIFO module instead of two to overcome versioning problem on the cost of + some additional gate count. UART_RX_FIFO was modified a little and renamed to UART_FIFO. +* UART_RX_FIFO.v and UART_TX_FIFO.v files removed from the project. +* Changes to receiver and transmitter modules concerning FIFO handling. +* Commented out `include "UART_defines" in all files but UART_top.v and test bench. +* Modified test bench a little for a little better check. + + +29.05.2001 +~~~~~~~~~~ + +* Fixed: Line Control Register block didn't have wb_rst_i in its sensitivity list +* Fixed: Modem Status Register block didn't have wb_rst_i in its sensitivity list and didn't set reset value +* Fixed rf_pop, lsr_mask, msi_reset and threi_clear not being synthesizable in release 1.7. (Thanks + to Pavel Korenski for pointing this to me) + + +27.05.2001 +~~~~~~~~~~ + +Thanks to Rick Wright for pointing me many of my bugs. + +* Fixed the rf_pop and lsr_mask flags not being deasserted. +* Fixed Time-Out interrupt not being masked by bit 0 in IER +* Fixed interrupt logic not being masked by IER +* Fixed bit 0 (interrupt pending) of IIR being set incorrectly +* Fixed Modem Status Register bits 3:0 handling (didn't work as should have) +* Fixed modem status interrupt to be related to bits [3:0] (deltas) instead of the bits 7:4 of MSR. + This way the interrupt is cleared upon reading from the MSR. +* Fixed THRE interrupt not being reset by reading IIR +* Changed Receiver and Transmitter FIFO, so that they do not use the FIFO_inc.v file because of problems + with #include command. +* Removed FIFO_inc.v from CVS tree. + +* Updated specifications .pdf file + diff --git a/usrp2/fpga/opencores/uart16550/doc/CVS/Entries b/usrp2/fpga/opencores/uart16550/doc/CVS/Entries new file mode 100644 index 00000000..15e067b1 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/doc/CVS/Entries @@ -0,0 +1,3 @@ +/CHANGES.txt/1.3/Mon Jul 29 21:15:17 2002/-kb/ +/UART_spec.pdf/1.6/Thu Dec 4 11:00:47 2003/-kb/ +D diff --git a/usrp2/fpga/opencores/uart16550/doc/CVS/Entries.Log b/usrp2/fpga/opencores/uart16550/doc/CVS/Entries.Log new file mode 100644 index 00000000..d269bfed --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/doc/CVS/Entries.Log @@ -0,0 +1 @@ +A D/src//// diff --git a/usrp2/fpga/opencores/uart16550/doc/CVS/Repository b/usrp2/fpga/opencores/uart16550/doc/CVS/Repository new file mode 100644 index 00000000..6e33cf21 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/doc/CVS/Repository @@ -0,0 +1 @@ +uart16550/doc diff --git a/usrp2/fpga/opencores/uart16550/doc/CVS/Root b/usrp2/fpga/opencores/uart16550/doc/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/uart16550/doc/CVS/Root @@ -0,0 +1 @@ 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zyaoj=qX<}fkOBoTmtiHIz&fl)I~3T=Cy=S&W+4>dTmuC;*Fu5LM+j;v$hi`a;qO?3 zXQ066H#m;(paAGU34R`c0-X6Mh7v}~(SSy@pbbm$2%dzJNuI?ExwuVEx6I+~bT+N`e_N(V$K%=9KfE3~2zzedp8MiV<^I&wmudSl z?wOXkzr+8Z%c6Pr+-KqIV$b#ZU-b`fj|DYJ7RdF4pB3q+Dt9W?IhWf)fbX~#XSeZ# zrn#u+$4zyVPmQK0+9ba4mocP{cfU;|)?R5*i0e9@ZL`3cPFX17t<4tB)DnBxR_rRTv#lG1Wb9$)wfO@c7;Inc_8j&GAGF^%p}2MDCC#m?@r=Fa z<;bAPba1SmE?venUW-mx#QUjz)kocZN#^|V?O^HrYu~oO)3N`E>#z<^q!FWZQAuZS z(bR>$W=elLTJ)iA;K)Bu(SAC3Fx=;K@3%NTulzz;D;x$q($LipAKgIA&`()^FzMQ@&Lr!wUFZ?hJ2aoLQWOe!G?TSx)~-#+b@a{&b$! zFkI(cozrg~pL7lf$17vH+0JlXxk?yTYx9^w{VRzf>ZhemHq<8C2$m^}xt1|^4b!=& zbFqQXe&!Xq-b|KDL+iT7*Svx?`g_zkk#)}M9?x$RoF&mbtEr)qIjieUPFioqaVqQa zqU)~WQKJGF;vb%iz8py|QetgcqfxKRXi;;jt zBq14tkb+dC;g{;7oGqw5c`N&WPM>F! detect falling edge on SDA while SCL is high + // detect stop condition => detect rising edge on SDA while SCL is high + always @(posedge clk or negedge nReset) + if (~nReset) + begin + sta_condition <= #1 1'b0; + sto_condition <= #1 1'b0; + end + else if (rst) + begin + sta_condition <= #1 1'b0; + sto_condition <= #1 1'b0; + end + else + begin + sta_condition <= #1 ~sSDA & dSDA & sSCL; + sto_condition <= #1 sSDA & ~dSDA & sSCL; + end + + // generate i2c bus busy signal + always @(posedge clk or negedge nReset) + if(!nReset) + busy <= #1 1'b0; + else if (rst) + busy <= #1 1'b0; + else + busy <= #1 (sta_condition | busy) & ~sto_condition; + + // generate arbitration lost signal + // aribitration lost when: + // 1) master drives SDA high, but the i2c bus is low + // 2) stop detected while not requested + reg cmd_stop; + always @(posedge clk or negedge nReset) + if (~nReset) + cmd_stop <= #1 1'b0; + else if (rst) + cmd_stop <= #1 1'b0; + else if (clk_en) + cmd_stop <= #1 cmd == `I2C_CMD_STOP; + + always @(posedge clk or negedge nReset) + if (~nReset) + al <= #1 1'b0; + else if (rst) + al <= #1 1'b0; + else + al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop); + + + // generate dout signal (store SDA on rising edge of SCL) + always @(posedge clk) + if(sSCL & ~dSCL) + dout <= #1 sSDA; + + // generate statemachine + + // nxt_state decoder + parameter [16:0] idle = 17'b0_0000_0000_0000_0000; + parameter [16:0] start_a = 17'b0_0000_0000_0000_0001; + parameter [16:0] start_b = 17'b0_0000_0000_0000_0010; + parameter [16:0] start_c = 17'b0_0000_0000_0000_0100; + parameter [16:0] start_d = 17'b0_0000_0000_0000_1000; + parameter [16:0] start_e = 17'b0_0000_0000_0001_0000; + parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000; + parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000; + parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000; + parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000; + parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000; + parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000; + parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000; + parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000; + parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000; + parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000; + parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000; + parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000; + + always @(posedge clk or negedge nReset) + if (!nReset) + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b0; + scl_oen <= #1 1'b1; + sda_oen <= #1 1'b1; + sda_chk <= #1 1'b0; + end + else if (rst | al) + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b0; + scl_oen <= #1 1'b1; + sda_oen <= #1 1'b1; + sda_chk <= #1 1'b0; + end + else + begin + cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle + + if (clk_en) + case (c_state) // synopsys full_case parallel_case + // idle state + idle: + begin + case (cmd) // synopsys full_case parallel_case + `I2C_CMD_START: + c_state <= #1 start_a; + + `I2C_CMD_STOP: + c_state <= #1 stop_a; + + `I2C_CMD_WRITE: + c_state <= #1 wr_a; + + `I2C_CMD_READ: + c_state <= #1 rd_a; + + default: + c_state <= #1 idle; + endcase + + scl_oen <= #1 scl_oen; // keep SCL in same state + sda_oen <= #1 sda_oen; // keep SDA in same state + sda_chk <= #1 1'b0; // don't check SDA output + end + + // start + start_a: + begin + c_state <= #1 start_b; + scl_oen <= #1 scl_oen; // keep SCL in same state + sda_oen <= #1 1'b1; // set SDA high + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_b: + begin + c_state <= #1 start_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 1'b1; // keep SDA high + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_c: + begin + c_state <= #1 start_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b0; // set SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_d: + begin + c_state <= #1 start_e; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + start_e: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b0; // set SCL low + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + // stop + stop_a: + begin + c_state <= #1 stop_b; + scl_oen <= #1 1'b0; // keep SCL low + sda_oen <= #1 1'b0; // set SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + stop_b: + begin + c_state <= #1 stop_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + stop_c: + begin + c_state <= #1 stop_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b0; // keep SDA low + sda_chk <= #1 1'b0; // don't check SDA output + end + + stop_d: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b1; // set SDA high + sda_chk <= #1 1'b0; // don't check SDA output + end + + // read + rd_a: + begin + c_state <= #1 rd_b; + scl_oen <= #1 1'b0; // keep SCL low + sda_oen <= #1 1'b1; // tri-state SDA + sda_chk <= #1 1'b0; // don't check SDA output + end + + rd_b: + begin + c_state <= #1 rd_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 1'b1; // keep SDA tri-stated + sda_chk <= #1 1'b0; // don't check SDA output + end + + rd_c: + begin + c_state <= #1 rd_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 1'b1; // keep SDA tri-stated + sda_chk <= #1 1'b0; // don't check SDA output + end + + rd_d: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b0; // set SCL low + sda_oen <= #1 1'b1; // keep SDA tri-stated + sda_chk <= #1 1'b0; // don't check SDA output + end + + // write + wr_a: + begin + c_state <= #1 wr_b; + scl_oen <= #1 1'b0; // keep SCL low + sda_oen <= #1 din; // set SDA + sda_chk <= #1 1'b0; // don't check SDA output (SCL low) + end + + wr_b: + begin + c_state <= #1 wr_c; + scl_oen <= #1 1'b1; // set SCL high + sda_oen <= #1 din; // keep SDA + sda_chk <= #1 1'b1; // check SDA output + end + + wr_c: + begin + c_state <= #1 wr_d; + scl_oen <= #1 1'b1; // keep SCL high + sda_oen <= #1 din; + sda_chk <= #1 1'b1; // check SDA output + end + + wr_d: + begin + c_state <= #1 idle; + cmd_ack <= #1 1'b1; + scl_oen <= #1 1'b0; // set SCL low + sda_oen <= #1 din; + sda_chk <= #1 1'b0; // don't check SDA output (SCL low) + end + + endcase + end + + + // assign scl and sda output (always gnd) + assign scl_o = 1'b0; + assign sda_o = 1'b0; + +endmodule diff --git a/usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v b/usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v new file mode 100644 index 00000000..d091d1e3 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v @@ -0,0 +1,344 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master byte-controller //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $ +// +// $Date: 2004/02/18 11:40:46 $ +// $Revision: 1.7 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_byte_ctrl.v,v $ +// Revision 1.7 2004/02/18 11:40:46 rherveille +// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. +// +// Revision 1.6 2003/08/09 07:01:33 rherveille +// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +// Fixed a potential bug in the byte controller's host-acknowledge generation. +// +// Revision 1.5 2002/12/26 15:02:32 rherveille +// Core is now a Multimaster I2C controller +// +// Revision 1.4 2002/11/30 22:24:40 rherveille +// Cleaned up code +// +// Revision 1.3 2001/11/05 11:59:25 rherveille +// Fixed wb_ack_o generation bug. +// Fixed bug in the byte_controller statemachine. +// Added headers. +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "i2c_master_defines.v" + +module i2c_master_byte_ctrl ( + clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din, + cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen ); + + // + // inputs & outputs + // + input clk; // master clock + input rst; // synchronous active high reset + input nReset; // asynchronous active low reset + input ena; // core enable signal + + input [15:0] clk_cnt; // 4x SCL + + // control inputs + input start; + input stop; + input read; + input write; + input ack_in; + input [7:0] din; + + // status outputs + output cmd_ack; + reg cmd_ack; + output ack_out; + reg ack_out; + output i2c_busy; + output i2c_al; + output [7:0] dout; + + // I2C signals + input scl_i; + output scl_o; + output scl_oen; + input sda_i; + output sda_o; + output sda_oen; + + + // + // Variable declarations + // + + // statemachine + parameter [4:0] ST_IDLE = 5'b0_0000; + parameter [4:0] ST_START = 5'b0_0001; + parameter [4:0] ST_READ = 5'b0_0010; + parameter [4:0] ST_WRITE = 5'b0_0100; + parameter [4:0] ST_ACK = 5'b0_1000; + parameter [4:0] ST_STOP = 5'b1_0000; + + // signals for bit_controller + reg [3:0] core_cmd; + reg core_txd; + wire core_ack, core_rxd; + + // signals for shift register + reg [7:0] sr; //8bit shift register + reg shift, ld; + + // signals for state machine + wire go; + reg [2:0] dcnt; + wire cnt_done; + + // + // Module body + // + + // hookup bit_controller + i2c_master_bit_ctrl bit_controller ( + .clk ( clk ), + .rst ( rst ), + .nReset ( nReset ), + .ena ( ena ), + .clk_cnt ( clk_cnt ), + .cmd ( core_cmd ), + .cmd_ack ( core_ack ), + .busy ( i2c_busy ), + .al ( i2c_al ), + .din ( core_txd ), + .dout ( core_rxd ), + .scl_i ( scl_i ), + .scl_o ( scl_o ), + .scl_oen ( scl_oen ), + .sda_i ( sda_i ), + .sda_o ( sda_o ), + .sda_oen ( sda_oen ) + ); + + // generate go-signal + assign go = (read | write | stop) & ~cmd_ack; + + // assign dout output to shift-register + assign dout = sr; + + // generate shift register + always @(posedge clk or negedge nReset) + if (!nReset) + sr <= #1 8'h0; + else if (rst) + sr <= #1 8'h0; + else if (ld) + sr <= #1 din; + else if (shift) + sr <= #1 {sr[6:0], core_rxd}; + + // generate counter + always @(posedge clk or negedge nReset) + if (!nReset) + dcnt <= #1 3'h0; + else if (rst) + dcnt <= #1 3'h0; + else if (ld) + dcnt <= #1 3'h7; + else if (shift) + dcnt <= #1 dcnt - 3'h1; + + assign cnt_done = ~(|dcnt); + + // + // state machine + // + reg [4:0] c_state; // synopsis enum_state + + always @(posedge clk or negedge nReset) + if (!nReset) + begin + core_cmd <= #1 `I2C_CMD_NOP; + core_txd <= #1 1'b0; + shift <= #1 1'b0; + ld <= #1 1'b0; + cmd_ack <= #1 1'b0; + c_state <= #1 ST_IDLE; + ack_out <= #1 1'b0; + end + else if (rst | i2c_al) + begin + core_cmd <= #1 `I2C_CMD_NOP; + core_txd <= #1 1'b0; + shift <= #1 1'b0; + ld <= #1 1'b0; + cmd_ack <= #1 1'b0; + c_state <= #1 ST_IDLE; + ack_out <= #1 1'b0; + end + else + begin + // initially reset all signals + core_txd <= #1 sr[7]; + shift <= #1 1'b0; + ld <= #1 1'b0; + cmd_ack <= #1 1'b0; + + case (c_state) // synopsys full_case parallel_case + ST_IDLE: + if (go) + begin + if (start) + begin + c_state <= #1 ST_START; + core_cmd <= #1 `I2C_CMD_START; + end + else if (read) + begin + c_state <= #1 ST_READ; + core_cmd <= #1 `I2C_CMD_READ; + end + else if (write) + begin + c_state <= #1 ST_WRITE; + core_cmd <= #1 `I2C_CMD_WRITE; + end + else // stop + begin + c_state <= #1 ST_STOP; + core_cmd <= #1 `I2C_CMD_STOP; + end + + ld <= #1 1'b1; + end + + ST_START: + if (core_ack) + begin + if (read) + begin + c_state <= #1 ST_READ; + core_cmd <= #1 `I2C_CMD_READ; + end + else + begin + c_state <= #1 ST_WRITE; + core_cmd <= #1 `I2C_CMD_WRITE; + end + + ld <= #1 1'b1; + end + + ST_WRITE: + if (core_ack) + if (cnt_done) + begin + c_state <= #1 ST_ACK; + core_cmd <= #1 `I2C_CMD_READ; + end + else + begin + c_state <= #1 ST_WRITE; // stay in same state + core_cmd <= #1 `I2C_CMD_WRITE; // write next bit + shift <= #1 1'b1; + end + + ST_READ: + if (core_ack) + begin + if (cnt_done) + begin + c_state <= #1 ST_ACK; + core_cmd <= #1 `I2C_CMD_WRITE; + end + else + begin + c_state <= #1 ST_READ; // stay in same state + core_cmd <= #1 `I2C_CMD_READ; // read next bit + end + + shift <= #1 1'b1; + core_txd <= #1 ack_in; + end + + ST_ACK: + if (core_ack) + begin + if (stop) + begin + c_state <= #1 ST_STOP; + core_cmd <= #1 `I2C_CMD_STOP; + end + else + begin + c_state <= #1 ST_IDLE; + core_cmd <= #1 `I2C_CMD_NOP; + + // generate command acknowledge signal + cmd_ack <= #1 1'b1; + end + + // assign ack_out output to bit_controller_rxd (contains last received bit) + ack_out <= #1 core_rxd; + + core_txd <= #1 1'b1; + end + else + core_txd <= #1 ack_in; + + ST_STOP: + if (core_ack) + begin + c_state <= #1 ST_IDLE; + core_cmd <= #1 `I2C_CMD_NOP; + + // generate command acknowledge signal + cmd_ack <= #1 1'b1; + end + + endcase + end +endmodule diff --git a/usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_defines.v b/usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_defines.v new file mode 100644 index 00000000..ee3b694f --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_defines.v @@ -0,0 +1,64 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master controller defines //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $ +// +// $Date: 2001/11/05 11:59:25 $ +// $Revision: 1.3 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_defines.v,v $ +// Revision 1.3 2001/11/05 11:59:25 rherveille +// Fixed wb_ack_o generation bug. +// Fixed bug in the byte_controller statemachine. +// Added headers. +// + + +// I2C registers wishbone addresses + +// bitcontroller states +`define I2C_CMD_NOP 4'b0000 +`define I2C_CMD_START 4'b0001 +`define I2C_CMD_STOP 4'b0010 +`define I2C_CMD_WRITE 4'b0100 +`define I2C_CMD_READ 4'b1000 diff --git a/usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_top.v b/usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_top.v new file mode 100644 index 00000000..30689bd7 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_top.v @@ -0,0 +1,301 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE revB.2 compliant I2C Master controller Top-level //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $ +// +// $Date: 2005/02/27 09:26:24 $ +// $Revision: 1.11 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_master_top.v,v $ +// Revision 1.11 2005/02/27 09:26:24 rherveille +// Fixed register overwrite issue. +// Removed full_case pragma, replaced it by a default statement. +// +// Revision 1.10 2003/09/01 10:34:38 rherveille +// Fix a blocking vs. non-blocking error in the wb_dat output mux. +// +// Revision 1.9 2003/01/09 16:44:45 rherveille +// Fixed a bug in the Command Register declaration. +// +// Revision 1.8 2002/12/26 16:05:12 rherveille +// Small code simplifications +// +// Revision 1.7 2002/12/26 15:02:32 rherveille +// Core is now a Multimaster I2C controller +// +// Revision 1.6 2002/11/30 22:24:40 rherveille +// Cleaned up code +// +// Revision 1.5 2001/11/10 10:52:55 rherveille +// Changed PRER reset value from 0x0000 to 0xffff, conform specs. +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "i2c_master_defines.v" + +module i2c_master_top( + wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o, + wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o, + scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o ); + + // parameters + parameter ARST_LVL = 1'b0; // asynchronous reset level + + // + // inputs & outputs + // + + // wishbone signals + input wb_clk_i; // master clock input + input wb_rst_i; // synchronous active high reset + input arst_i; // asynchronous reset + input [2:0] wb_adr_i; // lower address bits + input [7:0] wb_dat_i; // databus input + output [7:0] wb_dat_o; // databus output + input wb_we_i; // write enable input + input wb_stb_i; // stobe/core select signal + input wb_cyc_i; // valid bus cycle input + output wb_ack_o; // bus cycle acknowledge output + output wb_inta_o; // interrupt request signal output + + reg [7:0] wb_dat_o; + reg wb_ack_o; + reg wb_inta_o; + + // I2C signals + // i2c clock line + input scl_pad_i; // SCL-line input + output scl_pad_o; // SCL-line output (always 1'b0) + output scl_padoen_o; // SCL-line output enable (active low) + + // i2c data line + input sda_pad_i; // SDA-line input + output sda_pad_o; // SDA-line output (always 1'b0) + output sda_padoen_o; // SDA-line output enable (active low) + + + // + // variable declarations + // + + // registers + reg [15:0] prer; // clock prescale register + reg [ 7:0] ctr; // control register + reg [ 7:0] txr; // transmit register + wire [ 7:0] rxr; // receive register + reg [ 7:0] cr; // command register + wire [ 7:0] sr; // status register + + // done signal: command completed, clear command register + wire done; + + // core enable signal + wire core_en; + wire ien; + + // status register signals + wire irxack; + reg rxack; // received aknowledge from slave + reg tip; // transfer in progress + reg irq_flag; // interrupt pending flag + wire i2c_busy; // bus busy (start signal detected) + wire i2c_al; // i2c bus arbitration lost + reg al; // status register arbitration lost bit + + // + // module body + // + + // generate internal reset + wire rst_i = arst_i ^ ARST_LVL; + + // generate wishbone signals + wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i; + + // generate acknowledge output signal + always @(posedge wb_clk_i) + wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored + + // assign DAT_O + always @(posedge wb_clk_i) + begin + case (wb_adr_i) // synopsis parallel_case + 3'b000: wb_dat_o <= #1 prer[ 7:0]; + 3'b001: wb_dat_o <= #1 prer[15:8]; + 3'b010: wb_dat_o <= #1 ctr; + 3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr) + 3'b100: wb_dat_o <= #1 sr; // write is command register (cr) + 3'b101: wb_dat_o <= #1 txr; + 3'b110: wb_dat_o <= #1 cr; + 3'b111: wb_dat_o <= #1 0; // reserved + endcase + end + + // generate registers + always @(posedge wb_clk_i or negedge rst_i) + if (!rst_i) + begin + prer <= #1 16'hffff; + ctr <= #1 8'h0; + txr <= #1 8'h0; + end + else if (wb_rst_i) + begin + prer <= #1 16'hffff; + ctr <= #1 8'h0; + txr <= #1 8'h0; + end + else + if (wb_wacc) + case (wb_adr_i) // synopsis parallel_case + 3'b000 : prer [ 7:0] <= #1 wb_dat_i; + 3'b001 : prer [15:8] <= #1 wb_dat_i; + 3'b010 : ctr <= #1 wb_dat_i; + 3'b011 : txr <= #1 wb_dat_i; + default: ; + endcase + + // generate command register (special case) + always @(posedge wb_clk_i or negedge rst_i) + if (~rst_i) + cr <= #1 8'h0; + else if (wb_rst_i) + cr <= #1 8'h0; + else if (wb_wacc) + begin + if (core_en & (wb_adr_i == 3'b100) ) + cr <= #1 wb_dat_i; + end + else + begin + if (done | i2c_al) + cr[7:4] <= #1 4'h0; // clear command bits when done + // or when aribitration lost + cr[2:1] <= #1 2'b0; // reserved bits + cr[0] <= #1 2'b0; // clear IRQ_ACK bit + end + + + // decode command register + wire sta = cr[7]; + wire sto = cr[6]; + wire rd = cr[5]; + wire wr = cr[4]; + wire ack = cr[3]; + wire iack = cr[0]; + + // decode control register + assign core_en = ctr[7]; + assign ien = ctr[6]; + + // hookup byte controller block + i2c_master_byte_ctrl byte_controller ( + .clk ( wb_clk_i ), + .rst ( wb_rst_i ), + .nReset ( rst_i ), + .ena ( core_en ), + .clk_cnt ( prer ), + .start ( sta ), + .stop ( sto ), + .read ( rd ), + .write ( wr ), + .ack_in ( ack ), + .din ( txr ), + .cmd_ack ( done ), + .ack_out ( irxack ), + .dout ( rxr ), + .i2c_busy ( i2c_busy ), + .i2c_al ( i2c_al ), + .scl_i ( scl_pad_i ), + .scl_o ( scl_pad_o ), + .scl_oen ( scl_padoen_o ), + .sda_i ( sda_pad_i ), + .sda_o ( sda_pad_o ), + .sda_oen ( sda_padoen_o ) + ); + + // status register block + interrupt request signal + always @(posedge wb_clk_i or negedge rst_i) + if (!rst_i) + begin + al <= #1 1'b0; + rxack <= #1 1'b0; + tip <= #1 1'b0; + irq_flag <= #1 1'b0; + end + else if (wb_rst_i) + begin + al <= #1 1'b0; + rxack <= #1 1'b0; + tip <= #1 1'b0; + irq_flag <= #1 1'b0; + end + else + begin + al <= #1 i2c_al | (al & ~sta); + rxack <= #1 irxack; + tip <= #1 (rd | wr); + irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated + end + + // generate interrupt request signals + always @(posedge wb_clk_i or negedge rst_i) + if (!rst_i) + wb_inta_o <= #1 1'b0; + else if (wb_rst_i) + wb_inta_o <= #1 1'b0; + else + wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set) + + // assign status register bits + assign sr[7] = rxack; + assign sr[6] = i2c_busy; + assign sr[5] = al; + assign sr[4:2] = 3'h0; // reserved + assign sr[1] = tip; + assign sr[0] = irq_flag; + +endmodule diff --git a/usrp2/fpga/opencores/i2c/rtl/verilog/timescale.v b/usrp2/fpga/opencores/i2c/rtl/verilog/timescale.v new file mode 100644 index 00000000..60d4ecbd --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/verilog/timescale.v @@ -0,0 +1,2 @@ +`timescale 1ns / 10ps + diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Entries b/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Entries new file mode 100644 index 00000000..2a33278f --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Entries @@ -0,0 +1,7 @@ +/I2C.VHD/1.1/Mon Sep 24 12:21:51 2001// +/i2c_master_bit_ctrl.vhd/1.14/Wed Oct 11 12:10:13 2006// +/i2c_master_byte_ctrl.vhd/1.5/Wed Feb 18 11:41:48 2004// +/i2c_master_top.vhd/1.7/Sun Mar 14 10:17:03 2004// +/readme/1.2/Sat Nov 30 22:25:47 2002// +/tst_ds1621.vhd/1.1/Mon Sep 24 12:21:51 2001// +D diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Repository b/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Repository new file mode 100644 index 00000000..c210ff4e --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Repository @@ -0,0 +1 @@ +i2c/rtl/vhdl diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Root b/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Template b/usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/I2C.VHD b/usrp2/fpga/opencores/i2c/rtl/vhdl/I2C.VHD new file mode 100644 index 00000000..64d1eb65 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/vhdl/I2C.VHD @@ -0,0 +1,620 @@ +-- +-- Simple I2C controller +-- +-- 1) No multimaster +-- 2) No slave mode +-- 3) No fifo's +-- +-- notes: +-- Every command is acknowledged. Do not set a new command before previous is acknowledged. +-- Dout is available 1 clock cycle later as cmd_ack +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +package I2C is + component simple_i2c is + port ( + clk : in std_logic; + ena : in std_logic; + nReset : in std_logic; + + clk_cnt : in unsigned(7 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + Din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; + ack_out : out std_logic; + Dout : out std_logic_vector(7 downto 0); + + -- i2c signals + SCL : inout std_logic; + SDA : inout std_logic + ); + end component simple_i2c; +end package I2C; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity simple_i2c is + port ( + clk : in std_logic; + ena : in std_logic; + nReset : in std_logic; + + clk_cnt : in unsigned(7 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + Din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; + ack_out : out std_logic; + Dout : out std_logic_vector(7 downto 0); + + -- i2c signals + SCL : inout std_logic; + SDA : inout std_logic + ); +end entity simple_i2c; + +architecture structural of simple_i2c is + component i2c_core is + port ( + clk : in std_logic; + nReset : in std_logic; + + clk_cnt : in unsigned(7 downto 0); + + cmd : in std_logic_vector(2 downto 0); + cmd_ack : out std_logic; + busy : out std_logic; + + Din : in std_logic; + Dout : out std_logic; + + SCL : inout std_logic; + SDA : inout std_logic + ); + end component i2c_core; + + -- commands for i2c_core + constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; + constant CMD_START : std_logic_vector(2 downto 0) := "010"; + constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; + constant CMD_READ : std_logic_vector(2 downto 0) := "100"; + constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; + + -- signals for i2c_core + signal core_cmd : std_logic_vector(2 downto 0); + signal core_ack, core_busy, core_txd, core_rxd : std_logic; + + -- signals for shift register + signal sr : std_logic_vector(7 downto 0); -- 8bit shift register + signal shift, ld : std_logic; + + -- signals for state machine + signal go, host_ack : std_logic; +begin + -- hookup i2c core + u1: i2c_core port map (clk, nReset, clk_cnt, core_cmd, core_ack, core_busy, core_txd, core_rxd, SCL, SDA); + + -- generate host-command-acknowledge + cmd_ack <= host_ack; + + -- generate go-signal + go <= (read or write) and not host_ack; + + -- assign Dout output to shift-register + Dout <= sr; + + -- assign ack_out output to core_rxd (contains last received bit) + ack_out <= core_rxd; + + -- generate shift register + shift_register: process(clk) + begin + if (clk'event and clk = '1') then + if (ld = '1') then + sr <= din; + elsif (shift = '1') then + sr <= (sr(6 downto 0) & core_rxd); + end if; + end if; + end process shift_register; + + -- + -- state machine + -- + statemachine : block + type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); + signal state : states; + signal dcnt : unsigned(2 downto 0); + begin + -- + -- command interpreter, translate complex commands into simpler I2C commands + -- + nxt_state_decoder: process(clk, nReset, state) + variable nxt_state : states; + variable idcnt : unsigned(2 downto 0); + variable ihost_ack : std_logic; + variable icore_cmd : std_logic_vector(2 downto 0); + variable icore_txd : std_logic; + variable ishift, iload : std_logic; + begin + -- 8 databits (1byte) of data to shift-in/out + idcnt := dcnt; + + -- no acknowledge (until command complete) + ihost_ack := '0'; + + icore_txd := core_txd; + + -- keep current command to i2c_core + icore_cmd := core_cmd; + + -- no shifting or loading of shift-register + ishift := '0'; + iload := '0'; + + -- keep current state; + nxt_state := state; + case state is + when st_idle => + if (go = '1') then + if (start = '1') then + nxt_state := st_start; + icore_cmd := CMD_START; + elsif (read = '1') then + nxt_state := st_read; + icore_cmd := CMD_READ; + idcnt := "111"; + else + nxt_state := st_write; + icore_cmd := CMD_WRITE; + idcnt := "111"; + iload := '1'; + end if; + end if; + + when st_start => + if (core_ack = '1') then + if (read = '1') then + nxt_state := st_read; + icore_cmd := CMD_READ; + idcnt := "111"; + else + nxt_state := st_write; + icore_cmd := CMD_WRITE; + idcnt := "111"; + iload := '1'; + end if; + end if; + + when st_write => + if (core_ack = '1') then + idcnt := dcnt -1; -- count down Data_counter + icore_txd := sr(7); + if (dcnt = 0) then + nxt_state := st_ack; + icore_cmd := CMD_READ; + else + ishift := '1'; +-- icore_txd := sr(7); + end if; + end if; + + when st_read => + if (core_ack = '1') then + idcnt := dcnt -1; -- count down Data_counter + ishift := '1'; + if (dcnt = 0) then + nxt_state := st_ack; + icore_cmd := CMD_WRITE; + icore_txd := ack_in; + end if; + end if; + + when st_ack => + if (core_ack = '1') then + -- generate command acknowledge signal + ihost_ack := '1'; + + -- Perform an additional shift, needed for 'read' (store last received bit in shift register) + ishift := '1'; + + -- check for stop; Should a STOP command be generated ? + if (stop = '1') then + nxt_state := st_stop; + icore_cmd := CMD_STOP; + else + nxt_state := st_idle; + icore_cmd := CMD_NOP; + end if; + end if; + + when st_stop => + if (core_ack = '1') then + nxt_state := st_idle; + icore_cmd := CMD_NOP; + end if; + + when others => -- illegal states + nxt_state := st_idle; + icore_cmd := CMD_NOP; + end case; + + -- generate registers + if (nReset = '0') then + core_cmd <= CMD_NOP; + core_txd <= '0'; + + shift <= '0'; + ld <= '0'; + + dcnt <= "111"; + host_ack <= '0'; + + state <= st_idle; + elsif (clk'event and clk = '1') then + if (ena = '1') then + state <= nxt_state; + + dcnt <= idcnt; + shift <= ishift; + ld <= iload; + + core_cmd <= icore_cmd; + core_txd <= icore_txd; + + host_ack <= ihost_ack; + end if; + end if; + end process nxt_state_decoder; + + end block statemachine; + +end architecture structural; + + +-- +-- +-- I2C Core +-- +-- Translate simple commands into SCL/SDA transitions +-- Each command has 5 states, A/B/C/D/idle +-- +-- start: SCL ~~~~~~~~~~\____ +-- SDA ~~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- repstart SCL ____/~~~~\___ +-- SDA __/~~~\______ +-- x | A | B | C | D | i +-- +-- stop SCL ____/~~~~~~~~ +-- SDA ==\____/~~~~~ +-- x | A | B | C | D | i +-- +--- write SCL ____/~~~~\____ +-- SDA ==X=========X= +-- x | A | B | C | D | i +-- +--- read SCL ____/~~~~\____ +-- SDA XXXX=====XXXX +-- x | A | B | C | D | i +-- + +-- Timing: Normal mode Fast mode +----------------------------------------------------------------- +-- Fscl 100KHz 400KHz +-- Th_scl 4.0us 0.6us High period of SCL +-- Tl_scl 4.7us 1.3us Low period of SCL +-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition +-- Tsu:sto 4.0us 0.6us setup time for a stop conditon +-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity i2c_core is + port ( + clk : in std_logic; + nReset : in std_logic; + + clk_cnt : in unsigned(7 downto 0); + + cmd : in std_logic_vector(2 downto 0); + cmd_ack : out std_logic; + busy : out std_logic; + + Din : in std_logic; + Dout : out std_logic; + + SCL : inout std_logic; + SDA : inout std_logic + ); +end entity i2c_core; + +architecture structural of i2c_core is + constant CMD_NOP : std_logic_vector(2 downto 0) := "000"; + constant CMD_START : std_logic_vector(2 downto 0) := "010"; + constant CMD_STOP : std_logic_vector(2 downto 0) := "011"; + constant CMD_READ : std_logic_vector(2 downto 0) := "100"; + constant CMD_WRITE : std_logic_vector(2 downto 0) := "101"; + + type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); + signal state : cmds; + signal SDAo, SCLo : std_logic; + signal txd : std_logic; + signal clk_en, slave_wait :std_logic; + signal cnt : unsigned(7 downto 0) := clk_cnt; +begin + -- whenever the slave is not ready it can delay the cycle by pulling SCL low + slave_wait <= '1' when ((SCLo = '1') and (SCL = '0')) else '0'; + + -- generate clk enable signal + gen_clken: process(clk, nReset) + begin + if (nReset = '0') then + cnt <= (others => '0'); + clk_en <= '1'; --'0'; + elsif (clk'event and clk = '1') then + if (cnt = 0) then + clk_en <= '1'; + cnt <= clk_cnt; + else + if (slave_wait = '0') then + cnt <= cnt -1; + end if; + clk_en <= '0'; + end if; + end if; + end process gen_clken; + + -- generate statemachine + nxt_state_decoder : process (clk, nReset, state, cmd, SDA) + variable nxt_state : cmds; + variable icmd_ack, ibusy, store_sda : std_logic; + variable itxd : std_logic; + begin + + nxt_state := state; + + icmd_ack := '0'; -- default no acknowledge + ibusy := '1'; -- default busy + + store_sda := '0'; + + itxd := txd; + + case (state) is + -- idle + when idle => + case cmd is + when CMD_START => + nxt_state := start_a; + icmd_ack := '1'; -- command completed + + when CMD_STOP => + nxt_state := stop_a; + icmd_ack := '1'; -- command completed + + when CMD_WRITE => + nxt_state := wr_a; + icmd_ack := '1'; -- command completed + itxd := Din; + + when CMD_READ => + nxt_state := rd_a; + icmd_ack := '1'; -- command completed + + when others => + nxt_state := idle; +-- don't acknowledge NOP command icmd_ack := '1'; -- command completed + ibusy := '0'; + end case; + + -- start + when start_a => + nxt_state := start_b; + + when start_b => + nxt_state := start_c; + + when start_c => + nxt_state := start_d; + + when start_d => + nxt_state := idle; + ibusy := '0'; -- not busy when idle + + + -- stop + when stop_a => + nxt_state := stop_b; + + when stop_b => + nxt_state := stop_c; + + when stop_c => +-- nxt_state := stop_d; + +-- when stop_d => + nxt_state := idle; + ibusy := '0'; -- not busy when idle + + -- read + when rd_a => + nxt_state := rd_b; + + when rd_b => + nxt_state := rd_c; + + when rd_c => + nxt_state := rd_d; + store_sda := '1'; + + when rd_d => + nxt_state := idle; + ibusy := '0'; -- not busy when idle + + -- write + when wr_a => + nxt_state := wr_b; + + when wr_b => + nxt_state := wr_c; + + when wr_c => + nxt_state := wr_d; + + when wr_d => + nxt_state := idle; + ibusy := '0'; -- not busy when idle + + end case; + + -- generate regs + if (nReset = '0') then + state <= idle; + cmd_ack <= '0'; + busy <= '0'; + txd <= '0'; + Dout <= '0'; + elsif (clk'event and clk = '1') then + if (clk_en = '1') then + state <= nxt_state; + busy <= ibusy; + + txd <= itxd; + if (store_sda = '1') then + Dout <= SDA; + end if; + end if; + + cmd_ack <= icmd_ack and clk_en; + end if; + end process nxt_state_decoder; + + -- + -- convert states to SCL and SDA signals + -- + output_decoder: process (clk, nReset, state) + variable iscl, isda : std_logic; + begin + case (state) is + when idle => + iscl := SCLo; -- keep SCL in same state + isda := SDA; -- keep SDA in same state + + -- start + when start_a => + iscl := SCLo; -- keep SCL in same state (for repeated start) + isda := '1'; -- set SDA high + + when start_b => + iscl := '1'; -- set SCL high + isda := '1'; -- keep SDA high + + when start_c => + iscl := '1'; -- keep SCL high + isda := '0'; -- sel SDA low + + when start_d => + iscl := '0'; -- set SCL low + isda := '0'; -- keep SDA low + + -- stop + when stop_a => + iscl := '0'; -- keep SCL disabled + isda := '0'; -- set SDA low + + when stop_b => + iscl := '1'; -- set SCL high + isda := '0'; -- keep SDA low + + when stop_c => + iscl := '1'; -- keep SCL high + isda := '1'; -- set SDA high + + -- write + when wr_a => + iscl := '0'; -- keep SCL low +-- isda := txd; -- set SDA + isda := Din; + + when wr_b => + iscl := '1'; -- set SCL high +-- isda := txd; -- set SDA + isda := Din; + + when wr_c => + iscl := '1'; -- keep SCL high +-- isda := txd; -- set SDA + isda := Din; + + when wr_d => + iscl := '0'; -- set SCL low +-- isda := txd; -- set SDA + isda := Din; + + -- read + when rd_a => + iscl := '0'; -- keep SCL low + isda := '1'; -- tri-state SDA + + when rd_b => + iscl := '1'; -- set SCL high + isda := '1'; -- tri-state SDA + + when rd_c => + iscl := '1'; -- keep SCL high + isda := '1'; -- tri-state SDA + + when rd_d => + iscl := '0'; -- set SCL low + isda := '1'; -- tri-state SDA + end case; + + -- generate registers + if (nReset = '0') then + SCLo <= '1'; + SDAo <= '1'; + elsif (clk'event and clk = '1') then + if (clk_en = '1') then + SCLo <= iscl; + SDAo <= isda; + end if; + end if; + end process output_decoder; + + SCL <= '0' when (SCLo = '0') else 'Z'; -- since SCL is externally pulled-up convert a '1' to a 'Z'(tri-state) + SDA <= '0' when (SDAo = '0') else 'Z'; -- since SDA is externally pulled-up convert a '1' to a 'Z'(tri-state) +-- SCL <= SCLo; +-- SDA <= SDAo; + +end architecture structural; + + + + diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd b/usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd new file mode 100644 index 00000000..1b8eb96d --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd @@ -0,0 +1,495 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 I2C Master Core; bit-controller ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $ +-- +-- $Date: 2006/10/11 12:10:13 $ +-- $Revision: 1.14 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: i2c_master_bit_ctrl.vhd,v $ +-- Revision 1.14 2006/10/11 12:10:13 rherveille +-- Added missing semicolons ';' on endif +-- +-- Revision 1.13 2006/10/06 10:48:24 rherveille +-- fixed short scl high pulse after clock stretch +-- +-- Revision 1.12 2004/05/07 11:53:31 rherveille +-- Fixed previous fix :) Made a variable vs signal mistake. +-- +-- Revision 1.11 2004/05/07 11:04:00 rherveille +-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. +-- +-- Revision 1.10 2004/02/27 07:49:43 rherveille +-- Fixed a bug in the arbitration-lost signal generation. VHDL version only. +-- +-- Revision 1.9 2003/08/12 14:48:37 rherveille +-- Forgot an 'end if' :-/ +-- +-- Revision 1.8 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.7 2003/02/05 00:06:02 rherveille +-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. +-- +-- Revision 1.6 2003/02/01 02:03:06 rherveille +-- Fixed a few 'arbitration lost' bugs. VHDL version only. +-- +-- Revision 1.5 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.4 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.3 2002/10/30 18:09:53 rherveille +-- Fixed some reported minor start/stop generation timing issuess. +-- +-- Revision 1.2 2002/06/15 07:37:04 rherveille +-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. +-- +-- Revision 1.1 2001/11/05 12:02:33 rherveille +-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. +-- Code updated, is now up-to-date to doc. rev.0.4. +-- Added headers. +-- + + +-- +------------------------------------- +-- Bit controller section +------------------------------------ +-- +-- Translate simple commands into SCL/SDA transitions +-- Each command has 5 states, A/B/C/D/idle +-- +-- start: SCL ~~~~~~~~~~~~~~\____ +-- SDA XX/~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- repstart SCL ______/~~~~~~~\___ +-- SDA __/~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- stop SCL _______/~~~~~~~~~~~ +-- SDA ==\___________/~~~~~ +-- x | A | B | C | D | i +-- +--- write SCL ______/~~~~~~~\____ +-- SDA XXX===============XX +-- x | A | B | C | D | i +-- +--- read SCL ______/~~~~~~~\____ +-- SDA XXXXXXX=XXXXXXXXXXX +-- x | A | B | C | D | i +-- + +-- Timing: Normal mode Fast mode +----------------------------------------------------------------- +-- Fscl 100KHz 400KHz +-- Th_scl 4.0us 0.6us High period of SCL +-- Tl_scl 4.7us 1.3us Low period of SCL +-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition +-- Tsu:sto 4.0us 0.6us setup time for a stop conditon +-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity i2c_master_bit_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; + nReset : in std_logic; + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- clock prescale value + + cmd : in std_logic_vector(3 downto 0); + cmd_ack : out std_logic; -- command completed + busy : out std_logic; -- i2c bus busy + al : out std_logic; -- arbitration lost + + din : in std_logic; + dout : out std_logic; + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_bit_ctrl; + +architecture structural of i2c_master_bit_ctrl is + constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; + constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; + constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; + constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; + constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; + + type states is (idle, start_a, start_b, start_c, start_d, start_e, + stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); + signal c_state : states; + + signal iscl_oen, isda_oen : std_logic; -- internal I2C lines + signal sda_chk : std_logic; -- check SDA status (multi-master arbitration) + signal dscl_oen : std_logic; -- delayed scl_oen signals + signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs + signal clk_en, slave_wait : std_logic; -- clock generation signals + signal ial : std_logic; -- internal arbitration lost signal +-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation) + signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) + +begin + -- whenever the slave is not ready it can delay the cycle by pulling SCL low + -- delay scl_oen + process (clk) + begin + if (clk'event and clk = '1') then + dscl_oen <= iscl_oen; + end if; + end process; + slave_wait <= dscl_oen and not sSCL; + + -- generate clk enable signal + gen_clken: process(clk, nReset) + begin + if (nReset = '0') then + cnt <= (others => '0'); + clk_en <= '1'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + cnt <= (others => '0'); + clk_en <= '1'; + elsif ( (cnt = 0) or (ena = '0') ) then + cnt <= clk_cnt; + clk_en <= '1'; + elsif (slave_wait = '1') then + cnt <= cnt; + clk_en <= '0'; + else + cnt <= cnt -1; + clk_en <= '0'; + end if; + end if; + end process gen_clken; + + + -- generate bus status controller + bus_status_ctrl: block + signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA + signal sta_condition : std_logic; -- start detected + signal sto_condition : std_logic; -- stop detected + signal cmd_stop : std_logic; -- STOP command + signal ibusy : std_logic; -- internal busy signal + begin + -- synchronize SCL and SDA inputs + synch_scl_sda: process(clk, nReset) + begin + if (nReset = '0') then + sSCL <= '1'; + sSDA <= '1'; + + dSCL <= '1'; + dSDA <= '1'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + sSCL <= '1'; + sSDA <= '1'; + + dSCL <= '1'; + dSDA <= '1'; + else + sSCL <= scl_i; + sSDA <= sda_i; + + dSCL <= sSCL; + dSDA <= sSDA; + end if; + end if; + end process synch_SCL_SDA; + + -- detect start condition => detect falling edge on SDA while SCL is high + -- detect stop condition => detect rising edge on SDA while SCL is high + detect_sta_sto: process(clk, nReset) + begin + if (nReset = '0') then + sta_condition <= '0'; + sto_condition <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + sta_condition <= '0'; + sto_condition <= '0'; + else + sta_condition <= (not sSDA and dSDA) and sSCL; + sto_condition <= (sSDA and not dSDA) and sSCL; + end if; + end if; + end process detect_sta_sto; + + -- generate i2c-bus busy signal + gen_busy: process(clk, nReset) + begin + if (nReset = '0') then + ibusy <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + ibusy <= '0'; + else + ibusy <= (sta_condition or ibusy) and not sto_condition; + end if; + end if; + end process gen_busy; + busy <= ibusy; + + + -- generate arbitration lost signal + -- aribitration lost when: + -- 1) master drives SDA high, but the i2c bus is low + -- 2) stop detected while not requested (detect during 'idle' state) + gen_al: process(clk, nReset) + begin + if (nReset = '0') then + cmd_stop <= '0'; + ial <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + cmd_stop <= '0'; + ial <= '0'; + else + if (clk_en = '1') then + if (cmd = I2C_CMD_STOP) then + cmd_stop <= '1'; + else + cmd_stop <= '0'; + end if; + end if; + + if (c_state = idle) then + ial <= (sda_chk and not sSDA and isda_oen); + else + ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop); + end if; + + end if; + end if; + end process gen_al; + al <= ial; + + -- generate dout signal, store dout on rising edge of SCL + gen_dout: process(clk) + begin + if (clk'event and clk = '1') then + if (sSCL = '1' and dSCL = '0') then + dout <= sSDA; + end if; + end if; + end process gen_dout; + end block bus_status_ctrl; + + + -- generate statemachine + nxt_state_decoder : process (clk, nReset, c_state, cmd) + begin + if (nReset = '0') then + c_state <= idle; + cmd_ack <= '0'; + iscl_oen <= '1'; + isda_oen <= '1'; + sda_chk <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1' or ial = '1') then + c_state <= idle; + cmd_ack <= '0'; + iscl_oen <= '1'; + isda_oen <= '1'; + sda_chk <= '0'; + else + cmd_ack <= '0'; -- default no acknowledge + + if (clk_en = '1') then + case (c_state) is + -- idle + when idle => + case cmd is + when I2C_CMD_START => c_state <= start_a; + when I2C_CMD_STOP => c_state <= stop_a; + when I2C_CMD_WRITE => c_state <= wr_a; + when I2C_CMD_READ => c_state <= rd_a; + when others => c_state <= idle; -- NOP command + end case; + + iscl_oen <= iscl_oen; -- keep SCL in same state + isda_oen <= isda_oen; -- keep SDA in same state + sda_chk <= '0'; -- don't check SDA + + -- start + when start_a => + c_state <= start_b; + iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start) + isda_oen <= '1'; -- set SDA high + sda_chk <= '0'; -- don't check SDA + + when start_b => + c_state <= start_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '1'; -- keep SDA high + sda_chk <= '0'; -- don't check SDA + + when start_c => + c_state <= start_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- set SDA low + sda_chk <= '0'; -- don't check SDA + + when start_d => + c_state <= start_e; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when start_e => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + -- stop + when stop_a => + c_state <= stop_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= '0'; -- set SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_b => + c_state <= stop_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_c => + c_state <= stop_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '1'; -- set SDA high + sda_chk <= '0'; -- don't check SDA + + -- read + when rd_a => + c_state <= rd_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_b => + c_state <= rd_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_c => + c_state <= rd_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + -- write + when wr_a => + c_state <= wr_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= din; -- set SDA + sda_chk <= '0'; -- don't check SDA (SCL low) + + when wr_b => + c_state <= wr_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= din; -- keep SDA + sda_chk <= '1'; -- check SDA + + when wr_c => + c_state <= wr_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= din; -- keep SDA + sda_chk <= '1'; -- check SDA + + when wr_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= din; -- keep SDA + sda_chk <= '0'; -- don't check SDA (SCL low) + + when others => + + end case; + end if; + end if; + end if; + end process nxt_state_decoder; + + + -- assign outputs + scl_o <= '0'; + scl_oen <= iscl_oen; + sda_o <= '0'; + sda_oen <= isda_oen; +end architecture structural; + diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd b/usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd new file mode 100644 index 00000000..bdb2a881 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd @@ -0,0 +1,370 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 compl. I2C Master Core; byte-controller ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $ +-- +-- $Date: 2004/02/18 11:41:48 $ +-- $Revision: 1.5 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: i2c_master_byte_ctrl.vhd,v $ +-- Revision 1.5 2004/02/18 11:41:48 rherveille +-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. +-- +-- Revision 1.4 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.3 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.2 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.1 2001/11/05 12:02:33 rherveille +-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. +-- Code updated, is now up-to-date to doc. rev.0.4. +-- Added headers. +-- + + + + +-- +------------------------------------------ +-- Byte controller section +------------------------------------------ +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity i2c_master_byte_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) + nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; -- command done + ack_out : out std_logic; + i2c_busy : out std_logic; -- arbitration lost + i2c_al : out std_logic; -- i2c bus busy + dout : out std_logic_vector(7 downto 0); + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_byte_ctrl; + +architecture structural of i2c_master_byte_ctrl is + component i2c_master_bit_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; + nReset : in std_logic; + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- clock prescale value + + cmd : in std_logic_vector(3 downto 0); + cmd_ack : out std_logic; -- command done + busy : out std_logic; -- i2c bus busy + al : out std_logic; -- arbitration lost + + din : in std_logic; + dout : out std_logic; + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); + end component i2c_master_bit_ctrl; + + -- commands for bit_controller block + constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; + constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; + constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; + constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; + constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; + + -- signals for bit_controller + signal core_cmd : std_logic_vector(3 downto 0); + signal core_ack, core_txd, core_rxd : std_logic; + signal al : std_logic; + + -- signals for shift register + signal sr : std_logic_vector(7 downto 0); -- 8bit shift register + signal shift, ld : std_logic; + + -- signals for state machine + signal go, host_ack : std_logic; + signal dcnt : unsigned(2 downto 0); -- data counter + signal cnt_done : std_logic; + +begin + -- hookup bit_controller + bit_ctrl: i2c_master_bit_ctrl port map( + clk => clk, + rst => rst, + nReset => nReset, + ena => ena, + clk_cnt => clk_cnt, + cmd => core_cmd, + cmd_ack => core_ack, + busy => i2c_busy, + al => al, + din => core_txd, + dout => core_rxd, + scl_i => scl_i, + scl_o => scl_o, + scl_oen => scl_oen, + sda_i => sda_i, + sda_o => sda_o, + sda_oen => sda_oen + ); + i2c_al <= al; + + -- generate host-command-acknowledge + cmd_ack <= host_ack; + + -- generate go-signal + go <= (read or write or stop) and not host_ack; + + -- assign Dout output to shift-register + dout <= sr; + + -- generate shift register + shift_register: process(clk, nReset) + begin + if (nReset = '0') then + sr <= (others => '0'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + sr <= (others => '0'); + elsif (ld = '1') then + sr <= din; + elsif (shift = '1') then + sr <= (sr(6 downto 0) & core_rxd); + end if; + end if; + end process shift_register; + + -- generate data-counter + data_cnt: process(clk, nReset) + begin + if (nReset = '0') then + dcnt <= (others => '0'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + dcnt <= (others => '0'); + elsif (ld = '1') then + dcnt <= (others => '1'); -- load counter with 7 + elsif (shift = '1') then + dcnt <= dcnt -1; + end if; + end if; + end process data_cnt; + + cnt_done <= '1' when (dcnt = 0) else '0'; + + -- + -- state machine + -- + statemachine : block + type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); + signal c_state : states; + begin + -- + -- command interpreter, translate complex commands into simpler I2C commands + -- + nxt_state_decoder: process(clk, nReset) + begin + if (nReset = '0') then + core_cmd <= I2C_CMD_NOP; + core_txd <= '0'; + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + c_state <= st_idle; + ack_out <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1' or al = '1') then + core_cmd <= I2C_CMD_NOP; + core_txd <= '0'; + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + c_state <= st_idle; + ack_out <= '0'; + else + -- initialy reset all signal + core_txd <= sr(7); + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + + case c_state is + when st_idle => + if (go = '1') then + if (start = '1') then + c_state <= st_start; + core_cmd <= I2C_CMD_START; + elsif (read = '1') then + c_state <= st_read; + core_cmd <= I2C_CMD_READ; + elsif (write = '1') then + c_state <= st_write; + core_cmd <= I2C_CMD_WRITE; + else -- stop + c_state <= st_stop; + core_cmd <= I2C_CMD_STOP; + end if; + + ld <= '1'; + end if; + + when st_start => + if (core_ack = '1') then + if (read = '1') then + c_state <= st_read; + core_cmd <= I2C_CMD_READ; + else + c_state <= st_write; + core_cmd <= I2C_CMD_WRITE; + end if; + + ld <= '1'; + end if; + + when st_write => + if (core_ack = '1') then + if (cnt_done = '1') then + c_state <= st_ack; + core_cmd <= I2C_CMD_READ; + else + c_state <= st_write; -- stay in same state + core_cmd <= I2C_CMD_WRITE; -- write next bit + shift <= '1'; + end if; + end if; + + when st_read => + if (core_ack = '1') then + if (cnt_done = '1') then + c_state <= st_ack; + core_cmd <= I2C_CMD_WRITE; + else + c_state <= st_read; -- stay in same state + core_cmd <= I2C_CMD_READ; -- read next bit + end if; + + shift <= '1'; + core_txd <= ack_in; + end if; + + when st_ack => + if (core_ack = '1') then + -- check for stop; Should a STOP command be generated ? + if (stop = '1') then + c_state <= st_stop; + core_cmd <= I2C_CMD_STOP; + else + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + + -- generate command acknowledge signal + host_ack <= '1'; + end if; + + -- assign ack_out output to core_rxd (contains last received bit) + ack_out <= core_rxd; + + core_txd <= '1'; + else + core_txd <= ack_in; + end if; + + when st_stop => + if (core_ack = '1') then + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + + -- generate command acknowledge signal + host_ack <= '1'; + end if; + + when others => -- illegal states + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + report ("Byte controller entered illegal state."); + + end case; + + end if; + end if; + end process nxt_state_decoder; + + end block statemachine; + +end architecture structural; + diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_top.vhd b/usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_top.vhd new file mode 100644 index 00000000..a2557120 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_top.vhd @@ -0,0 +1,359 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 compl. I2C Master Core; top level ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $ +-- +-- $Date: 2004/03/14 10:17:03 $ +-- $Revision: 1.7 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: i2c_master_top.vhd,v $ +-- Revision 1.7 2004/03/14 10:17:03 rherveille +-- Fixed simulation issue when writing to CR register +-- +-- Revision 1.6 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.5 2003/02/01 02:03:06 rherveille +-- Fixed a few 'arbitration lost' bugs. VHDL version only. +-- +-- Revision 1.4 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.3 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.2 2001/11/10 10:52:44 rherveille +-- Changed PRER reset value from 0x0000 to 0xffff, conform specs. +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity i2c_master_top is + generic( + ARST_LVL : std_logic := '0' -- asynchronous reset level + ); + port ( + -- wishbone signals + wb_clk_i : in std_logic; -- master clock input + wb_rst_i : in std_logic := '0'; -- synchronous active high reset + arst_i : in std_logic := not ARST_LVL; -- asynchronous reset + wb_adr_i : in unsigned(2 downto 0); -- lower address bits + wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input + wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output + wb_we_i : in std_logic; -- Write enable input + wb_stb_i : in std_logic; -- Strobe signals / core select signal + wb_cyc_i : in std_logic; -- Valid bus cycle input + wb_ack_o : out std_logic; -- Bus cycle acknowledge output + wb_inta_o : out std_logic; -- interrupt request output signal + + -- i2c lines + scl_pad_i : in std_logic; -- i2c clock line input + scl_pad_o : out std_logic; -- i2c clock line output + scl_padoen_o : out std_logic; -- i2c clock line output enable, active low + sda_pad_i : in std_logic; -- i2c data line input + sda_pad_o : out std_logic; -- i2c data line output + sda_padoen_o : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_top; + +architecture structural of i2c_master_top is + component i2c_master_byte_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) + nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; + ack_out : out std_logic; + i2c_busy : out std_logic; + i2c_al : out std_logic; + dout : out std_logic_vector(7 downto 0); + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); + end component i2c_master_byte_ctrl; + + -- registers + signal prer : unsigned(15 downto 0); -- clock prescale register + signal ctr : std_logic_vector(7 downto 0); -- control register + signal txr : std_logic_vector(7 downto 0); -- transmit register + signal rxr : std_logic_vector(7 downto 0); -- receive register + signal cr : std_logic_vector(7 downto 0); -- command register + signal sr : std_logic_vector(7 downto 0); -- status register + + -- internal reset signal + signal rst_i : std_logic; + + -- wishbone write access + signal wb_wacc : std_logic; + + -- internal acknowledge signal + signal iack_o : std_logic; + + -- done signal: command completed, clear command register + signal done : std_logic; + + -- command register signals + signal sta, sto, rd, wr, ack, iack : std_logic; + + signal core_en : std_logic; -- core enable signal + signal ien : std_logic; -- interrupt enable signal + + -- status register signals + signal irxack, rxack : std_logic; -- received aknowledge from slave + signal tip : std_logic; -- transfer in progress + signal irq_flag : std_logic; -- interrupt pending flag + signal i2c_busy : std_logic; -- i2c bus busy (start signal detected) + signal i2c_al, al : std_logic; -- arbitration lost + +begin + -- generate internal reset signal + rst_i <= arst_i xor ARST_LVL; + + -- generate acknowledge output signal + gen_ack_o : process(wb_clk_i) + begin + if (wb_clk_i'event and wb_clk_i = '1') then + iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored + end if; + end process gen_ack_o; + wb_ack_o <= iack_o; + + + -- generate wishbone write access signal + wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i; + + -- assign wb_dat_o + assign_dato : process(wb_clk_i) + begin + if (wb_clk_i'event and wb_clk_i = '1') then + case wb_adr_i is + when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0)); + when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8)); + when "010" => wb_dat_o <= ctr; + when "011" => wb_dat_o <= rxr; -- write is transmit register TxR + when "100" => wb_dat_o <= sr; -- write is command register CR + + -- Debugging registers: + -- These registers are not documented. + -- Functionality could change in future releases + when "101" => wb_dat_o <= txr; + when "110" => wb_dat_o <= cr; + when "111" => wb_dat_o <= (others => '0'); + when others => wb_dat_o <= (others => 'X'); -- for simulation only + end case; + end if; + end process assign_dato; + + + -- generate registers (CR, SR see below) + gen_regs: process(rst_i, wb_clk_i) + begin + if (rst_i = '0') then + prer <= (others => '1'); + ctr <= (others => '0'); + txr <= (others => '0'); + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + prer <= (others => '1'); + ctr <= (others => '0'); + txr <= (others => '0'); + elsif (wb_wacc = '1') then + case wb_adr_i is + when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i); + when "001" => prer(15 downto 8) <= unsigned(wb_dat_i); + when "010" => ctr <= wb_dat_i; + when "011" => txr <= wb_dat_i; + when "100" => null; --write to CR, avoid executing the others clause + + -- illegal cases, for simulation only + when others => + report ("Illegal write address, setting all registers to unknown."); + prer <= (others => 'X'); + ctr <= (others => 'X'); + txr <= (others => 'X'); + end case; + end if; + end if; + end process gen_regs; + + + -- generate command register + gen_cr: process(rst_i, wb_clk_i) + begin + if (rst_i = '0') then + cr <= (others => '0'); + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + cr <= (others => '0'); + elsif (wb_wacc = '1') then + if ( (core_en = '1') and (wb_adr_i = 4) ) then + -- only take new commands when i2c core enabled + -- pending commands are finished + cr <= wb_dat_i; + end if; + else + if (done = '1' or i2c_al = '1') then + cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost + end if; + + cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' + cr(0) <= '0'; -- clear IRQ_ACK bit + end if; + end if; + end process gen_cr; + + -- decode command register + sta <= cr(7); + sto <= cr(6); + rd <= cr(5); + wr <= cr(4); + ack <= cr(3); + iack <= cr(0); + + -- decode control register + core_en <= ctr(7); + ien <= ctr(6); + + -- hookup byte controller block + byte_ctrl: i2c_master_byte_ctrl port map ( + clk => wb_clk_i, + rst => wb_rst_i, + nReset => rst_i, + ena => core_en, + clk_cnt => prer, + start => sta, + stop => sto, + read => rd, + write => wr, + ack_in => ack, + i2c_busy => i2c_busy, + i2c_al => i2c_al, + din => txr, + cmd_ack => done, + ack_out => irxack, + dout => rxr, + scl_i => scl_pad_i, + scl_o => scl_pad_o, + scl_oen => scl_padoen_o, + sda_i => sda_pad_i, + sda_o => sda_pad_o, + sda_oen => sda_padoen_o + ); + + + -- status register block + interrupt request signal + st_irq_block : block + begin + -- generate status register bits + gen_sr_bits: process (wb_clk_i, rst_i) + begin + if (rst_i = '0') then + al <= '0'; + rxack <= '0'; + tip <= '0'; + irq_flag <= '0'; + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + al <= '0'; + rxack <= '0'; + tip <= '0'; + irq_flag <= '0'; + else + al <= i2c_al or (al and not sta); + rxack <= irxack; + tip <= (rd or wr); + + -- interrupt request flag is always generated + irq_flag <= (done or i2c_al or irq_flag) and not iack; + end if; + end if; + end process gen_sr_bits; + + -- generate interrupt request signals + gen_irq: process (wb_clk_i, rst_i) + begin + if (rst_i = '0') then + wb_inta_o <= '0'; + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + wb_inta_o <= '0'; + else + -- interrupt signal is only generated when IEN (interrupt enable bit) is set + wb_inta_o <= irq_flag and ien; + end if; + end if; + end process gen_irq; + + -- assign status register bits + sr(7) <= rxack; + sr(6) <= i2c_busy; + sr(5) <= al; + sr(4 downto 2) <= (others => '0'); -- reserved + sr(1) <= tip; + sr(0) <= irq_flag; + end block; + +end architecture structural; diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/readme b/usrp2/fpga/opencores/i2c/rtl/vhdl/readme new file mode 100644 index 00000000..0d049f73 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/vhdl/readme @@ -0,0 +1,25 @@ + + +-- This code is provided for free and may be used and -- +-- distributed without restriction provided that the -- +-- copyright statement is not removed from the file and -- +-- that any derivative work contains the original -- +-- copyright notice and the associated disclaimer. -- + +-- Comments and suggestions are always welcome -- + +The i2c_master core consists of three files: + +- i2c_master_top -- top level +- i2c_master_byte_ctrl -- byte controller +- i2c_master_bit_ctrl -- bit controller + +VHDL needs to be compiled in order. The files are listed +above in descending order. + +I2C.VHD and tst_ds1621.vhd are not supported anymore. +They remain mostly for historical purposes, altough they +might prove usefull. + +Richard Herveille +rherveille@opencores.org diff --git a/usrp2/fpga/opencores/i2c/rtl/vhdl/tst_ds1621.vhd b/usrp2/fpga/opencores/i2c/rtl/vhdl/tst_ds1621.vhd new file mode 100644 index 00000000..ccf50460 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/rtl/vhdl/tst_ds1621.vhd @@ -0,0 +1,283 @@ +-- +-- +-- State machine for reading data from Dallas 1621 +-- +-- Testsystem for i2c controller +-- +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.i2c.all; + +entity DS1621_interface is + port ( + clk : in std_logic; + nReset : in std_logic; + + Dout : out std_logic_vector(7 downto 0); -- data read from ds1621 + + error : out std_logic; -- no correct ack received + + SCL : inout std_logic; + SDA : inout std_logic + ); +end entity DS1621_interface; + +architecture structural of DS1621_interface is + constant SLAVE_ADDR : std_logic_vector(6 downto 0) := "1001000"; + constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(20, 8); + + signal cmd_ack : std_logic; + signal D : std_logic_vector(7 downto 0); + signal lack, store_dout : std_logic; + + signal start, read, write, ack, stop : std_logic; + signal i2c_dout : std_logic_vector(7 downto 0); + +begin + -- hookup I2C controller + u1: simple_i2c port map (clk => clk, ena => '1', clk_cnt => clk_cnt, nReset => nReset, + read => read, write => write, start => start, stop => stop, ack_in => ack, cmd_ack => cmd_ack, + Din => D, Dout => i2c_dout, ack_out => lack, SCL => SCL, SDA => SDA); + + init_statemachine : block + type states is (i1, i2, i3, i4, i5, t1, t2, t3, t4, t5); + signal state : states; + begin + nxt_state_decoder: process(clk, nReset, state) + variable nxt_state : states; + variable iD : std_logic_vector(7 downto 0); + variable ierr : std_logic; + variable istart, iread, iwrite, iack, istop : std_logic; + variable istore_dout : std_logic; + begin + nxt_state := state; + ierr := '0'; + istore_dout := '0'; + + istart := start; + iread := read; + iwrite := write; + iack := ack; + istop := stop; + iD := D; + + case (state) is + -- init DS1621 + -- 1) send start condition + -- 2) send slave address + write + -- 3) check ack + -- 4) send "access config" command (0xAC) + -- 5) check ack + -- 6) send config register data (0x00) + -- 7) check ack + -- 8) send stop condition + -- 9) send start condition + -- 10) send slave address + write + -- 11) check ack + -- 12) send "start conversion" command (0xEE) + -- 13) check ack + -- 14) send stop condition + + when i1 => -- send start condition, sent slave address + write + nxt_state := i2; + istart := '1'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := (slave_addr & '0'); -- write to slave (R/W = '0') + + when i2 => -- send "access config" command + if (cmd_ack = '1') then + nxt_state := i3; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := x"AC"; + end if; + + when i3 => -- send config register data, sent stop condition + if (cmd_ack = '1') then + nxt_state := i4; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '1'; + iD := x"00"; + end if; + + when i4 => -- send start condition, sent slave address + write + if (cmd_ack = '1') then + nxt_state := i5; + + istart := '1'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := (slave_addr & '0'); -- write to slave (R/W = '0') + end if; + + when i5 => -- send "start conversion" command + stop condition + if (cmd_ack = '1') then + nxt_state := t1; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '1'; + iD := x"EE"; + end if; + -- read temperature + -- 1) sent start condition + -- 2) sent slave address + write + -- 3) check ack + -- 4) sent "read temperature" command (0xAA) + -- 5) check ack + -- 6) sent start condition + -- 7) sent slave address + read + -- 8) check ack + -- 9) read msb + -- 10) send ack + -- 11) read lsb + -- 12) send nack + -- 13) send stop condition + + when t1 => -- send start condition, sent slave address + write + if (cmd_ack = '1') then + nxt_state := t2; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '1'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := (slave_addr & '0'); -- write to slave (R/W = '0') + end if; + + when t2 => -- send read temperature command + if (cmd_ack = '1') then + nxt_state := t3; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := x"AA"; + end if; + + when t3 => -- send (repeated) start condition, send slave address + read + if (cmd_ack = '1') then + nxt_state := t4; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received, expected ACK + end if; + + istart := '1'; + iread := '0'; + iwrite := '1'; + iack := '0'; + istop := '0'; + iD := (slave_addr & '1'); -- read from slave (R/W = '1') + end if; + + when t4 => -- read MSB (hi-byte), send acknowledge + if (cmd_ack = '1') then + nxt_state := t5; + -- check aknowledge bit + if (lack = '1') then + ierr := '1'; -- no acknowledge received from last command, expected ACK + end if; + + istart := '0'; + iread := '1'; + iwrite := '0'; + iack := '0'; --ACK + istop := '0'; + end if; + + when t5 => -- read LSB (lo-byte), send acknowledge, sent stop + if (cmd_ack = '1') then + nxt_state := t1; + + istart := '0'; + iread := '1'; + iwrite := '0'; + iack := '1'; --NACK + istop := '1'; + + istore_dout := '1'; + end if; + end case; + + -- genregs + if (nReset = '0') then + state <= i1; + error <= '0'; + store_dout <= '0'; + + start <= '0'; + read <= '0'; + write <= '0'; + ack <= '0'; + stop <= '0'; + D <= (others => '0'); + elsif (clk'event and clk = '1') then + state <= nxt_state; + error <= ierr; + store_dout <= istore_dout; + + start <= istart; + read <= iread; + write <= iwrite; + ack <= iack; + stop <= istop; + D <= iD; + end if; + end process nxt_state_decoder; + end block init_statemachine; + + -- store temp + gen_dout : process(clk) + begin + if (clk'event and clk = '1') then + if (store_dout = '1') then + Dout <= i2c_dout; + end if; + end if; + end process gen_dout; + +end architecture structural; + + diff --git a/usrp2/fpga/opencores/i2c/sim/CVS/Entries b/usrp2/fpga/opencores/i2c/sim/CVS/Entries new file mode 100644 index 00000000..d08a896a --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/CVS/Entries @@ -0,0 +1 @@ +D/i2c_verilog//// diff --git a/usrp2/fpga/opencores/i2c/sim/CVS/Repository b/usrp2/fpga/opencores/i2c/sim/CVS/Repository new file mode 100644 index 00000000..500d8590 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/CVS/Repository @@ -0,0 +1 @@ +i2c/sim diff --git a/usrp2/fpga/opencores/i2c/sim/CVS/Root b/usrp2/fpga/opencores/i2c/sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/sim/CVS/Template b/usrp2/fpga/opencores/i2c/sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Entries b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Entries new file mode 100644 index 00000000..8ab9f73a --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Entries @@ -0,0 +1 @@ +D/run//// diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Repository b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Repository new file mode 100644 index 00000000..b97ee33c --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Repository @@ -0,0 +1 @@ +i2c/sim/i2c_verilog diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Root b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Template b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Entries b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Entries new file mode 100644 index 00000000..ddea0baa --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Entries @@ -0,0 +1,6 @@ +/bench.vcd/1.1/Sat Jun 15 07:37:05 2002// +/ncverilog.key/1.1/Sat Jun 15 07:37:11 2002// +/ncverilog.log/1.1/Sat Jun 15 07:37:11 2002// +/run/1.2/Fri Apr 6 09:02:38 2007// +D/INCA_libs//// +D/waves//// diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Repository b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Repository new file mode 100644 index 00000000..bdd990e7 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Repository @@ -0,0 +1 @@ +i2c/sim/i2c_verilog/run diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Root b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Template b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository new file mode 100644 index 00000000..6b760e39 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository @@ -0,0 +1 @@ +i2c/sim/i2c_verilog/run/INCA_libs diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/bench.vcd b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/bench.vcd new file mode 100644 index 00000000..9a364415 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/bench.vcd @@ -0,0 +1,1496812 @@ +$date + Jun 15, 2002 13:36:37 +$end +$version + ncsim: v03.40.(b001) +$end +$timescale + 10 ps +$end + +$scope module tst_bench_top $end +$var reg 1 ! clk $end +$var reg 1 " rstn $end +$var wire 1 # adr [31] $end +$var wire 1 $ adr [30] $end +$var wire 1 % adr [29] $end +$var wire 1 & adr [28] $end +$var wire 1 ' adr [27] $end +$var wire 1 ( adr [26] $end +$var wire 1 ) adr [25] $end +$var wire 1 * adr [24] $end +$var wire 1 + adr [23] $end +$var wire 1 , adr [22] $end +$var wire 1 - adr [21] $end +$var wire 1 . adr [20] $end +$var wire 1 / adr [19] $end +$var wire 1 0 adr [18] $end +$var wire 1 1 adr [17] $end +$var wire 1 2 adr [16] $end +$var wire 1 3 adr [15] $end +$var wire 1 4 adr [14] $end +$var wire 1 5 adr [13] $end +$var wire 1 6 adr [12] $end +$var wire 1 7 adr [11] $end +$var wire 1 8 adr [10] $end +$var wire 1 9 adr [9] $end +$var wire 1 : adr [8] $end +$var wire 1 ; adr [7] $end +$var wire 1 < adr [6] $end +$var wire 1 = adr [5] $end +$var wire 1 > adr [4] $end +$var wire 1 ? adr [3] $end +$var wire 1 @ adr [2] $end +$var wire 1 A adr [1] $end +$var wire 1 B adr [0] $end +$var wire 8 C dat_i [7:0] $end +$var wire 8 D dat_o [7:0] $end +$var wire 1 E we $end +$var wire 1 F stb $end +$var wire 1 G cyc $end +$var wire 1 H ack $end +$var wire 1 I inta $end +$var reg 8 J q [7:0] $end +$var reg 8 K qq [7:0] $end +$var wire 1 L scl $end +$var wire 1 M scl_o $end +$var wire 1 N scl_oen $end +$var wire 1 O sda $end +$var wire 1 P sda_o $end +$var wire 1 Q sda_oen $end +$var parameter 3 R PRER_LO $end +$var parameter 3 S PRER_HI $end +$var parameter 3 T CTR $end +$var parameter 3 U RXR $end +$var parameter 3 V TXR $end +$var parameter 3 W CR $end +$var parameter 3 X SR $end +$var parameter 3 Y TXR_R $end +$var parameter 3 Z CR_R $end + +$scope module i2c_slave $end +$var parameter 7 [ I2C_ADR $end +$var wire 1 L scl $end +$var wire 1 O sda $end +$var wire 1 \ debug $end +$var reg 8 ] mem_adr [7:0] $end +$var reg 8 ^ mem_do [7:0] $end +$var reg 1 _ sta $end +$var reg 1 ` d_sta $end +$var reg 1 a sto $end +$var reg 1 b d_sto $end +$var reg 8 c sr [7:0] $end +$var reg 1 d rw $end +$var wire 1 e my_adr $end +$var wire 1 f i2c_reset $end +$var reg 3 g bit_cnt [2:0] $end +$var wire 1 h acc_done $end +$var reg 1 i ld $end +$var reg 1 j sda_o $end +$var parameter 3 k idle $end +$var parameter 3 l slave_ack $end +$var parameter 3 m get_mem_adr $end +$var parameter 3 n gma_ack $end +$var parameter 3 o data $end +$var parameter 3 p data_ack $end +$var reg 3 q state [2:0] $end +$upscope $end + +$upscope $end + +$enddefinitions $end +$dumpvars +b101 p +b100 o +b11 n +b10 m +b1 l +b0 k +b1010000 [ +b110 Z +b101 Y +b100 X +b100 W +b11 V +b11 U +b10 T +b1 S +b0 R +0! +1" +x# +x$ +x% +x& +x' +x( +x) +x* +x+ +x, +x- +x. +x/ +x0 +x1 +x2 +x3 +x4 +x5 +x6 +x7 +x8 +x9 +x: +x; +x< +x= +x> +x? +x@ +xA +xB +bx C +bx D +xE +xF +0G +0H +xI +bx J +bx K +xL +0M +xN +xO +0P +xQ +0\ +bx ] +bx ^ +x_ +x` +xa +xb +bx c +xd +xe +xf +bx g +xh +xi +1j +b0 q +$end +#200 +0" +#300 +1Q +1N +0I +1O +1L +#400 +1a +bx1 c +1f +#500 +1! +1i +#1000 +0! +#1500 +1! +#2000 +0! +#2500 +1! +#3000 +0! +#3500 +1! +#4000 +0! +#4500 +1! +#5000 +0! +#5500 +1! +#6000 +0! +#6500 +1! +#7000 +0! +#7500 +1! +#8000 +0! +#8500 +1! +#9000 +0! +#9500 +1! +#10000 +0! +#10500 +1! +#11000 +0! +#11500 +1! +#12000 +0! +#12500 +1! +#13000 +0! +#13500 +1! +#14000 +0! +#14500 +1! +#15000 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new file mode 100644 index 00000000..a3abe509 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.key @@ -0,0 +1 @@ +exit diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.log b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.log new file mode 100644 index 00000000..420a1b9e --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.log @@ -0,0 +1,118 @@ +ncverilog: v03.40.(b001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc. +ncverilog: v03.40.(b001): Started on Jun 15, 2002 at 13:36:36 +ncverilog + +access+rwc + +linedebug + +define+"WAVES" + +incdir+../../../../bench/verilog + +incdir+../../../../rtl/verilog + +libext+.v + -y + /tools/synopsys/dw/sim_ver/ + ../../../../rtl/verilog/i2c_master_bit_ctrl.v + ../../../../rtl/verilog/i2c_master_byte_ctrl.v + ../../../../rtl/verilog/i2c_master_top.v + ../../../../bench/verilog/i2c_slave_model.v + ../../../../bench/verilog/wb_master_model.v + ../../../../bench/verilog/tst_bench_top.v + +ncverilog: *W,BADPRF: The +linedebug option may have an adverse performance impact. +file: ../../../../rtl/verilog/i2c_master_bit_ctrl.v + module worklib.i2c_master_bit_ctrl:v (up-to-date) + errors: 0, warnings: 0 +file: ../../../../rtl/verilog/i2c_master_byte_ctrl.v + module worklib.i2c_master_byte_ctrl:v (up-to-date) + errors: 0, warnings: 0 +file: ../../../../rtl/verilog/i2c_master_top.v + module worklib.i2c_master_top:v (up-to-date) + errors: 0, warnings: 0 +file: ../../../../bench/verilog/i2c_slave_model.v + module worklib.i2c_slave_model:v (up-to-date) + errors: 0, warnings: 0 +file: ../../../../bench/verilog/wb_master_model.v + module worklib.wb_master_model:v (up-to-date) + errors: 0, warnings: 0 +file: ../../../../bench/verilog/tst_bench_top.v + module worklib.tst_bench_top:v + errors: 0, warnings: 0 +ncvlog: *W,LIBNOU: Library "/tools/synopsys/dw/sim_ver/" given but not used. + Total errors/warnings found outside modules and primitives: + errors: 0, warnings: 1 + Caching library 'worklib' ....... Done + Elaborating the design hierarchy: + Building instance overlay tables: .................... Done + Generating native compiled code: + worklib.tst_bench_top:v <0x7fb52c98> + streams: 12, words: 59009 + Loading native compiled code: .................... Done + Building instance specific data structures. + Design hierarchy summary: + Instances Unique + Modules: 6 6 + Primitives: 2 1 + Registers: 68 68 + Scalar wires: 48 - + Expanded wires: 36 2 + Vectored wires: 6 - + Always blocks: 23 23 + Initial blocks: 3 3 + Cont. assignments: 28 28 + Pseudo assignments: 11 14 + Simulation timescale: 10ps + Writing initial simulation snapshot: worklib.tst_bench_top:v +Loading snapshot worklib.tst_bench_top:v .................... Done +ncsim> source /cds/tools/inca/files/ncsimrc +ncsim> run +INFO: Signal dump enabled ... + + + +status: 0 Testbench started + + + +INFO: WISHBONE MASTER MODEL INSTANTIATED (tst_bench_top.u0) + +status: 19500 done reset +status: 23600 programmed registers +status: 25600 verified registers +status: 27600 enabled core +status: 30600 generate 'start', write cmd a0 (slave address+write) +status: 2582600 tip==0 +status: 2585600 write slave memory address 01 +status: 4877600 tip==0 +status: 4880600 write data a5 +status: 7172600 tip==0 +status: 7175600 write next data 5a, generate 'stop' +status: 9467600 tip==0 +status: 19467600 wait 100us +status: 19470600 generate 'start', write cmd a0 (slave address+write) +status: 22014600 tip==0 +status: 22017600 write slave address 01 +status: 24309600 tip==0 +status: 24312600 generate 'repeated start', write cmd a1 (slave address+read) +status: 26858600 tip==0 +status: 26860600 read + ack +status: 29154600 tip==0 +status: 29158600 read + ack +status: 31448600 tip==0 +status: 31452600 read + ack +status: 33744600 tip==0 +status: 33746600 received xx from 3rd read address +status: 33748600 read + nack +status: 36038600 tip==0 +status: 36040600 received xx from 4th read address +status: 36043600 generate 'start', write cmd a0 (slave address+write). Check invalid address +status: 38589600 tip==0 +status: 38592600 write slave memory address 10 +status: 40884600 tip==0 +status: 40884600 Check for nack +status: 40886600 generate 'stop' +status: 40888600 tip==0 + + +status: 43388600 Testbench done +Simulation stopped via $stop(1) at time 433886 NS + 0 +/mnt/pooh/projects/I2C/bench/verilog/tst_bench_top.v:427 $stop; +ncsim> exit +ncverilog: v03.40.(b001): Exiting on Jun 15, 2002 at 13:47:48 (total: 00:11:12) diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/run b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/run new file mode 100755 index 00000000..41bcaab3 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/run @@ -0,0 +1,25 @@ +#!/bin/csh + +set i2c = ../../.. +set bench = $i2c/bench +set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves + +ncverilog \ + \ + +access+rwc \ + +define+WAVES \ + \ + +incdir+$bench/verilog \ + +incdir+$i2c/rtl/verilog \ + \ + $i2c/rtl/verilog/i2c_master_bit_ctrl.v \ + $i2c/rtl/verilog/i2c_master_byte_ctrl.v \ + $i2c/rtl/verilog/i2c_master_top.v \ + \ + $bench/verilog/i2c_slave_model.v \ + $bench/verilog/wb_master_model.v \ + $bench/verilog/tst_bench_top.v + + + + diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository new file mode 100644 index 00000000..94d106eb --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository @@ -0,0 +1 @@ +i2c/sim/i2c_verilog/run/waves diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template b/usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/software/CVS/Entries b/usrp2/fpga/opencores/i2c/software/CVS/Entries new file mode 100644 index 00000000..93461347 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/CVS/Entries @@ -0,0 +1,2 @@ +D/drivers//// +D/include//// diff --git a/usrp2/fpga/opencores/i2c/software/CVS/Repository b/usrp2/fpga/opencores/i2c/software/CVS/Repository new file mode 100644 index 00000000..1b4c9f0b --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/CVS/Repository @@ -0,0 +1 @@ +i2c/software diff --git a/usrp2/fpga/opencores/i2c/software/CVS/Root b/usrp2/fpga/opencores/i2c/software/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/software/CVS/Template b/usrp2/fpga/opencores/i2c/software/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/software/drivers/CVS/Entries b/usrp2/fpga/opencores/i2c/software/drivers/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/drivers/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/i2c/software/drivers/CVS/Repository b/usrp2/fpga/opencores/i2c/software/drivers/CVS/Repository new file mode 100644 index 00000000..260d7873 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/drivers/CVS/Repository @@ -0,0 +1 @@ +i2c/software/drivers diff --git a/usrp2/fpga/opencores/i2c/software/drivers/CVS/Root b/usrp2/fpga/opencores/i2c/software/drivers/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/drivers/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/software/drivers/CVS/Template b/usrp2/fpga/opencores/i2c/software/drivers/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/software/include/CVS/Entries b/usrp2/fpga/opencores/i2c/software/include/CVS/Entries new file mode 100644 index 00000000..ef11b0c7 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/include/CVS/Entries @@ -0,0 +1,2 @@ +/oc_i2c_master.h/1.1/Thu Nov 22 10:02:19 2001// +D diff --git a/usrp2/fpga/opencores/i2c/software/include/CVS/Repository b/usrp2/fpga/opencores/i2c/software/include/CVS/Repository new file mode 100644 index 00000000..2ea08eee --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/include/CVS/Repository @@ -0,0 +1 @@ +i2c/software/include diff --git a/usrp2/fpga/opencores/i2c/software/include/CVS/Root b/usrp2/fpga/opencores/i2c/software/include/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/include/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/software/include/CVS/Template b/usrp2/fpga/opencores/i2c/software/include/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/software/include/oc_i2c_master.h b/usrp2/fpga/opencores/i2c/software/include/oc_i2c_master.h new file mode 100644 index 00000000..7f7cfc41 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/software/include/oc_i2c_master.h @@ -0,0 +1,102 @@ +/* +///////////////////////////////////////////////////////////////////// +//// //// +//// Include file for OpenCores I2C Master core //// +//// //// +//// File : oc_i2c_master.h //// +//// Function: c-include file //// +//// //// +//// Authors: Richard Herveille (richard@asics.ws) //// +//// Filip Miletic //// +//// //// +//// www.opencores.org //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// Filip Miletic //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// +*/ + +/* + * Definitions for the Opencores i2c master core + */ + +/* --- Definitions for i2c master's registers --- */ + +/* ----- Read-write access */ + +#define OC_I2C_PRER_LO 0x00 /* Low byte clock prescaler register */ +#define OC_I2C_PRER_HI 0x01 /* High byte clock prescaler register */ +#define OC_I2C_CTR 0x02 /* Control register */ + +/* ----- Write-only registers */ + +#define OC_I2C_TXR 0x03 /* Transmit byte register */ +#define OC_I2C_CR 0x04 /* Command register */ + +/* ----- Read-only registers */ + +#define OC_I2C_RXR 0x03 /* Receive byte register */ +#define OC_I2C_SR 0x04 /* Status register */ + +/* ----- Bits definition */ + +/* ----- Control register */ + +#define OC_I2C_EN (1<<7) /* Core enable bit: */ + /* 1 - core is enabled */ + /* 0 - core is disabled */ +#define OC_I2C_IEN (1<<6) /* Interrupt enable bit */ + /* 1 - Interrupt enabled */ + /* 0 - Interrupt disabled */ + /* Other bits in CR are reserved */ + +/* ----- Command register bits */ + +#define OC_I2C_STA (1<<7) /* Generate (repeated) start condition*/ +#define OC_I2C_STO (1<<6) /* Generate stop condition */ +#define OC_I2C_RD (1<<5) /* Read from slave */ +#define OC_I2C_WR (1<<4) /* Write to slave */ +#define OC_I2C_ACK (1<<3) /* Acknowledge from slave */ + /* 1 - ACK */ + /* 0 - NACK */ +#define OC_I2C_IACK (1<<0) /* Interrupt acknowledge */ + +/* ----- Status register bits */ + +#define OC_I2C_RXACK (1<<7) /* ACK received from slave */ + /* 1 - ACK */ + /* 0 - NACK */ +#define OC_I2C_BUSY (1<<6) /* Busy bit */ +#define OC_I2C_TIP (1<<1) /* Transfer in progress */ +#define OC_I2C_IF (1<<0) /* Interrupt flag */ + +/* bit testing and setting macros */ + +#define OC_ISSET(reg,bitmask) ((reg)&(bitmask)) +#define OC_ISCLEAR(reg,bitmask) (!(OC_ISSET(reg,bitmask))) +#define OC_BITSET(reg,bitmask) ((reg)|(bitmask)) +#define OC_BITCLEAR(reg,bitmask) ((reg)|(~(bitmask))) +#define OC_BITTOGGLE(reg,bitmask) ((reg)^(bitmask)) +#define OC_REGMOVE(reg,value) ((reg)=(value)) \ No newline at end of file diff --git a/usrp2/fpga/opencores/i2c/verilog/CVS/Entries b/usrp2/fpga/opencores/i2c/verilog/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/verilog/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/i2c/verilog/CVS/Repository b/usrp2/fpga/opencores/i2c/verilog/CVS/Repository new file mode 100644 index 00000000..acc23265 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/verilog/CVS/Repository @@ -0,0 +1 @@ +i2c/verilog diff --git a/usrp2/fpga/opencores/i2c/verilog/CVS/Root b/usrp2/fpga/opencores/i2c/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/verilog/CVS/Template b/usrp2/fpga/opencores/i2c/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/vhdl/CVS/Entries b/usrp2/fpga/opencores/i2c/vhdl/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/vhdl/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/i2c/vhdl/CVS/Repository b/usrp2/fpga/opencores/i2c/vhdl/CVS/Repository new file mode 100644 index 00000000..8ee00a78 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/vhdl/CVS/Repository @@ -0,0 +1 @@ +i2c/vhdl diff --git a/usrp2/fpga/opencores/i2c/vhdl/CVS/Root b/usrp2/fpga/opencores/i2c/vhdl/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/vhdl/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/vhdl/CVS/Template b/usrp2/fpga/opencores/i2c/vhdl/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/sd_interface/RTL/RxFifo.v b/usrp2/fpga/opencores/sd_interface/RTL/RxFifo.v new file mode 100644 index 00000000..2d26cdc0 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/RxFifo.v @@ -0,0 +1,134 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RxFifo.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536 +//// fifo read access via bus interface, fifo write access is direct +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module RxFifo( + busClk, + spiSysClk, + rstSyncToBusClk, + rstSyncToSpiClk, + fifoWEn, + fifoFull, + busAddress, + busWriteEn, + busStrobe_i, + busFifoSelect, + busDataIn, + busDataOut, + fifoDataIn ); + //FIFO_DEPTH = 2^ADDR_WIDTH + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input busClk; +input spiSysClk; +input rstSyncToBusClk; +input rstSyncToSpiClk; +input fifoWEn; +output fifoFull; +input [2:0] busAddress; +input busWriteEn; +input busStrobe_i; +input busFifoSelect; +input [7:0] busDataIn; +output [7:0] busDataOut; +input [7:0] fifoDataIn; + +wire busClk; +wire spiSysClk; +wire rstSyncToBusClk; +wire rstSyncToSpiClk; +wire fifoWEn; +wire fifoFull; +wire [2:0] busAddress; +wire busWriteEn; +wire busStrobe_i; +wire busFifoSelect; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire [7:0] fifoDataIn; + +//internal wires and regs +wire [7:0] dataFromFifoToBus; +wire fifoREn; +wire forceEmptySyncToBusClk; +wire forceEmptySyncToSpiClk; +wire [15:0] numElementsInFifo; +wire fifoEmpty; //not used + +fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo( + .wrClk(spiSysClk), + .rdClk(busClk), + .rstSyncToWrClk(rstSyncToSpiClk), + .rstSyncToRdClk(rstSyncToBusClk), + .dataIn(fifoDataIn), + .dataOut(dataFromFifoToBus), + .fifoWEn(fifoWEn), + .fifoREn(fifoREn), + .fifoFull(fifoFull), + .fifoEmpty(fifoEmpty), + .forceEmptySyncToWrClk(forceEmptySyncToSpiClk), + .forceEmptySyncToRdClk(forceEmptySyncToBusClk), + .numElementsInFifo(numElementsInFifo) ); + +RxfifoBI u_RxfifoBI( + .address(busAddress), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .spiSysClk(spiSysClk), + .rstSyncToBusClk(rstSyncToBusClk), + .fifoSelect(busFifoSelect), + .fifoDataIn(dataFromFifoToBus), + .busDataIn(busDataIn), + .busDataOut(busDataOut), + .fifoREn(fifoREn), + .forceEmptySyncToBusClk(forceEmptySyncToBusClk), + .forceEmptySyncToSpiClk(forceEmptySyncToSpiClk), + .numElementsInFifo(numElementsInFifo) + ); + +endmodule diff --git a/usrp2/fpga/opencores/sd_interface/RTL/RxFifoBI.v b/usrp2/fpga/opencores/sd_interface/RTL/RxFifoBI.v new file mode 100644 index 00000000..e7314750 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/RxFifoBI.v @@ -0,0 +1,149 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RxfifoBI.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module RxfifoBI ( + address, + writeEn, + strobe_i, + busClk, + spiSysClk, + rstSyncToBusClk, + fifoSelect, + fifoDataIn, + busDataIn, + busDataOut, + fifoREn, + forceEmptySyncToSpiClk, + forceEmptySyncToBusClk, + numElementsInFifo + ); +input [2:0] address; +input writeEn; +input strobe_i; +input busClk; +input spiSysClk; +input rstSyncToBusClk; +input [7:0] fifoDataIn; +input [7:0] busDataIn; +output [7:0] busDataOut; +output fifoREn; +output forceEmptySyncToSpiClk; +output forceEmptySyncToBusClk; +input [15:0] numElementsInFifo; +input fifoSelect; + + +wire [2:0] address; +wire writeEn; +wire strobe_i; +wire busClk; +wire spiSysClk; +wire rstSyncToBusClk; +wire [7:0] fifoDataIn; +wire [7:0] busDataIn; +reg [7:0] busDataOut; +reg fifoREn; +reg forceEmptySyncToSpiClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoSelect; + +reg [5:0] forceEmptyShift; +reg forceEmpty; +reg forceEmptySyncToUsbClkFirst; + +//sync write +always @(posedge busClk) +begin + if (writeEn == 1'b1 && fifoSelect == 1'b1 && + address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1) + forceEmpty <= 1'b1; + else + forceEmpty <= 1'b0; +end + +//generate 'forceEmptySyncToBusClk' +//assuming that 'busClk' < 5 * 'spiSysClk'. ie 'busClk' < 240MHz +always @(posedge busClk) begin + if (rstSyncToBusClk == 1'b1) + forceEmptyShift <= 6'b000000; + else begin + if (forceEmpty == 1'b1) + forceEmptyShift <= 6'b111111; + else + forceEmptyShift <= {1'b0, forceEmptyShift[5:1]}; + end +end +assign forceEmptySyncToBusClk = forceEmptyShift[0]; + +// double sync across clock domains to generate 'forceEmptySyncToWrClk' +always @(posedge spiSysClk) begin + forceEmptySyncToUsbClkFirst <= forceEmptySyncToBusClk; + forceEmptySyncToSpiClk <= forceEmptySyncToUsbClkFirst; +end + +// async read mux +always @(address or fifoDataIn or numElementsInFifo) +begin + case (address) + `FIFO_DATA_REG : busDataOut <= fifoDataIn; + `FIFO_DATA_COUNT_MSB : busDataOut <= numElementsInFifo[15:8]; + `FIFO_DATA_COUNT_LSB : busDataOut <= numElementsInFifo[7:0]; + default: busDataOut <= 8'h00; + endcase +end + +//generate fifo read strobe +always @(address or writeEn or strobe_i or fifoSelect) begin + if (address == `FIFO_DATA_REG && writeEn == 1'b0 && + strobe_i == 1'b1 && fifoSelect == 1'b1) + fifoREn <= 1'b1; + else + fifoREn <= 1'b0; +end + + +endmodule diff --git a/usrp2/fpga/opencores/sd_interface/RTL/TxFifo.v b/usrp2/fpga/opencores/sd_interface/RTL/TxFifo.v new file mode 100644 index 00000000..12e11565 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/TxFifo.v @@ -0,0 +1,132 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// TxFifo.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized TxFifo wrapper. Min depth = 2, Max depth = 65536 +//// fifo write access via bus interface, fifo read access is direct +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module TxFifo( + busClk, + spiSysClk, + rstSyncToBusClk, + rstSyncToSpiClk, + fifoREn, + fifoEmpty, + busAddress, + busWriteEn, + busStrobe_i, + busFifoSelect, + busDataIn, + busDataOut, + fifoDataOut ); + //FIFO_DEPTH = 2^ADDR_WIDTH + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input busClk; +input spiSysClk; +input rstSyncToBusClk; +input rstSyncToSpiClk; +input fifoREn; +output fifoEmpty; +input [2:0] busAddress; +input busWriteEn; +input busStrobe_i; +input busFifoSelect; +input [7:0] busDataIn; +output [7:0] busDataOut; +output [7:0] fifoDataOut; + +wire busClk; +wire spiSysClk; +wire rstSyncToBusClk; +wire rstSyncToSpiClk; +wire fifoREn; +wire fifoEmpty; +wire [2:0] busAddress; +wire busWriteEn; +wire busStrobe_i; +wire busFifoSelect; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +wire [7:0] fifoDataOut; + +//internal wires and regs +wire fifoWEn; +wire forceEmptySyncToSpiClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoFull; + +fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo( + .wrClk(busClk), + .rdClk(spiSysClk), + .rstSyncToWrClk(rstSyncToBusClk), + .rstSyncToRdClk(rstSyncToSpiClk), + .dataIn(busDataIn), + .dataOut(fifoDataOut), + .fifoWEn(fifoWEn), + .fifoREn(fifoREn), + .fifoFull(fifoFull), + .fifoEmpty(fifoEmpty), + .forceEmptySyncToWrClk(forceEmptySyncToBusClk), + .forceEmptySyncToRdClk(forceEmptySyncToSpiClk), + .numElementsInFifo(numElementsInFifo) ); + +TxfifoBI u_TxfifoBI( + .address(busAddress), + .writeEn(busWriteEn), + .strobe_i(busStrobe_i), + .busClk(busClk), + .spiSysClk(spiSysClk), + .rstSyncToBusClk(rstSyncToBusClk), + .fifoSelect(busFifoSelect), + .busDataIn(busDataIn), + .busDataOut(busDataOut), + .fifoWEn(fifoWEn), + .forceEmptySyncToBusClk(forceEmptySyncToBusClk), + .forceEmptySyncToSpiClk(forceEmptySyncToSpiClk), + .numElementsInFifo(numElementsInFifo) + ); + +endmodule diff --git a/usrp2/fpga/opencores/sd_interface/RTL/TxFifoBI.v b/usrp2/fpga/opencores/sd_interface/RTL/TxFifoBI.v new file mode 100644 index 00000000..b3b860ef --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/TxFifoBI.v @@ -0,0 +1,139 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// TxfifoBI.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module TxfifoBI ( + address, writeEn, strobe_i, + busClk, + spiSysClk, + rstSyncToBusClk, + fifoSelect, + busDataIn, + busDataOut, + fifoWEn, + forceEmptySyncToSpiClk, + forceEmptySyncToBusClk, + numElementsInFifo + ); +input [2:0] address; +input writeEn; +input strobe_i; +input busClk; +input spiSysClk; +input rstSyncToBusClk; +input [7:0] busDataIn; +output [7:0] busDataOut; +output fifoWEn; +output forceEmptySyncToSpiClk; +output forceEmptySyncToBusClk; +input [15:0] numElementsInFifo; +input fifoSelect; + + +wire [2:0] address; +wire writeEn; +wire strobe_i; +wire busClk; +wire spiSysClk; +wire rstSyncToBusClk; +wire [7:0] busDataIn; +wire [7:0] busDataOut; +reg fifoWEn; +reg forceEmptySyncToSpiClk; +wire forceEmptySyncToBusClk; +wire [15:0] numElementsInFifo; +wire fifoSelect; + +reg [5:0] forceEmptyShift; +reg forceEmpty; +reg forceEmptySyncToSpiClkFirst; + +//sync write +always @(posedge busClk) +begin + if (writeEn == 1'b1 && fifoSelect == 1'b1 && + address == `FIFO_CONTROL_REG && strobe_i == 1'b1 && busDataIn[0] == 1'b1) + forceEmpty <= 1'b1; + else + forceEmpty <= 1'b0; +end + +//generate 'forceEmptySyncToBusClk' +//assuming that 'busClk' < 5 * 'spiSysClk'. ie 'busClk' < 240MHz +always @(posedge busClk) begin + if (rstSyncToBusClk == 1'b1) + forceEmptyShift <= 6'b000000; + else begin + if (forceEmpty == 1'b1) + forceEmptyShift <= 6'b111111; + else + forceEmptyShift <= {1'b0, forceEmptyShift[5:1]}; + end +end +assign forceEmptySyncToBusClk = forceEmptyShift[0]; + +// double sync across clock domains to generate 'forceEmptySyncToWrClk' +always @(posedge spiSysClk) begin + forceEmptySyncToSpiClkFirst <= forceEmptySyncToBusClk; + forceEmptySyncToSpiClk <= forceEmptySyncToSpiClkFirst; +end + + + +// async read mux +assign busDataOut = 8'h00; + + +//generate fifo write strobe +always @(address or writeEn or strobe_i or fifoSelect or busDataIn) begin + if (address == `FIFO_DATA_REG && writeEn == 1'b1 && + strobe_i == 1'b1 && fifoSelect == 1'b1) + fifoWEn <= 1'b1; + else + fifoWEn <= 1'b0; +end + + +endmodule diff --git a/usrp2/fpga/opencores/sd_interface/RTL/ctrlStsRegBI.v b/usrp2/fpga/opencores/sd_interface/RTL/ctrlStsRegBI.v new file mode 100644 index 00000000..b0baf57a --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/ctrlStsRegBI.v @@ -0,0 +1,267 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// ctrlStsRegBI.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module ctrlStsRegBI ( + busClk, + rstFromWire, + dataIn, + dataOut, + address, + writeEn, + strobe_i, + spiSysClk, + spiTransType, + spiTransCtrl, + spiTransStatus, + spiDirectAccessTxData, + spiDirectAccessRxData, + ctrlStsRegSel, + rstSyncToBusClkOut, + rstSyncToSpiClkOut, + SDWriteError, + SDReadError, + SDInitError, + SDAddr, + spiClkDelay +); + +input [7:0] dataIn; +input [7:0] address; +input writeEn; +input strobe_i; +input busClk; +input spiSysClk; +output [7:0] dataOut; +input ctrlStsRegSel; +output [1:0] spiTransType; +output spiTransCtrl; +input spiTransStatus; +output [7:0] spiDirectAccessTxData; +reg [7:0] spiDirectAccessTxData; +input [7:0] spiDirectAccessRxData; +input rstFromWire; +output rstSyncToBusClkOut; +output rstSyncToSpiClkOut; +input [1:0] SDWriteError; +input [1:0] SDReadError; +input [1:0] SDInitError; +output [31:0] SDAddr; +reg [31:0] SDAddr; +output [7:0] spiClkDelay; +reg [7:0] spiClkDelay; + +wire [7:0] dataIn; +wire [7:0] address; +wire writeEn; +wire strobe_i; +wire clk; +reg [7:0] dataOut; +reg [1:0] spiTransType; +reg spiTransCtrl; +wire ctrlStsRegSel; +wire rstFromWire; +reg rstSyncToBusClkOut; +reg rstSyncToSpiClkOut; + +//internal wire and regs +reg [5:0] rstShift; +reg rstFromBus; +reg [7:0] spiDirectAccessTxDataSTB; +reg [7:0] spiDirectAccessRxDataSTB; +reg [1:0] spiTransTypeSTB; +reg spiTransCtrlSTB; +reg spiTransStatusSTB; +reg rstSyncToSpiClkFirst; +reg [5:0] spiTransCtrlShift; +reg spiTransStatusReg1; +reg spiTransStatusReg2; +reg [1:0] SDWriteErrorSTB; +reg [1:0] SDReadErrorSTB; +reg [1:0] SDInitErrorSTB; +reg spiTransCtrl_reg1; +reg spiTransCtrl_reg2; +reg spiTransCtrl_reg3; + +//sync write demux +always @(posedge busClk) +begin + if (rstSyncToBusClkOut == 1'b1) begin + spiTransTypeSTB <= `DIRECT_ACCESS; + spiTransCtrlSTB <= `TRANS_STOP; + spiDirectAccessTxDataSTB <= 8'h00; + spiClkDelay <= `FAST_SPI_CLK; + end + else begin + if (writeEn == 1'b1 && ctrlStsRegSel == 1'b1 && strobe_i == 1'b1 && address == `SPI_MASTER_CONTROL_REG && dataIn[1] == 1'b1 ) + rstFromBus <= 1'b1; + else + rstFromBus <= 1'b0; + if (writeEn == 1'b1 && ctrlStsRegSel == 1'b1 && strobe_i == 1'b1 && address == `TRANS_CTRL_REG && dataIn[0] == 1'b1 ) + spiTransCtrlSTB <= 1'b1; + else + spiTransCtrlSTB <= 1'b0; + if (writeEn == 1'b1 && ctrlStsRegSel == 1'b1 && strobe_i == 1'b1) begin + case (address) + `TRANS_TYPE_REG: spiTransTypeSTB <= dataIn[1:0]; + `SD_ADDR_7_0_REG: SDAddr[7:0] <= dataIn; + `SD_ADDR_15_8_REG: SDAddr[15:8] <= dataIn; + `SD_ADDR_23_16_REG: SDAddr[23:16] <= dataIn; + `SD_ADDR_31_24_REG: SDAddr[31:24] <= dataIn; + `SPI_CLK_DEL_REG: spiClkDelay <= dataIn; + `DIRECT_ACCESS_DATA_REG: spiDirectAccessTxDataSTB <= dataIn; + endcase + end + end +end + +// async read mux +always @(address or spiTransTypeSTB or spiTransCtrlSTB or + spiTransStatusSTB or spiDirectAccessRxDataSTB or + SDAddr or SDInitErrorSTB or SDReadErrorSTB or SDWriteErrorSTB or + spiClkDelay) +begin + case (address) + `SPI_MASTER_VERSION_REG: dataOut <= `SPI_MASTER_VERSION_NUM; + `TRANS_TYPE_REG: dataOut <= { 6'b000000, spiTransTypeSTB}; + `TRANS_CTRL_REG: dataOut <= { 7'b0000000, spiTransCtrlSTB}; + `TRANS_STS_REG: dataOut <= { 7'b0000000, spiTransStatusSTB}; + `TRANS_ERROR_REG: dataOut <= {2'b00, SDWriteErrorSTB, SDReadErrorSTB, SDInitErrorSTB}; + `SD_ADDR_7_0_REG: dataOut <= SDAddr[7:0]; + `SD_ADDR_15_8_REG: dataOut <= SDAddr[15:8]; + `SD_ADDR_23_16_REG: dataOut <= SDAddr[23:16]; + `SD_ADDR_31_24_REG: dataOut <= SDAddr[31:24]; + `SPI_CLK_DEL_REG: dataOut <= spiClkDelay; + `DIRECT_ACCESS_DATA_REG: dataOut <= spiDirectAccessRxDataSTB; + default: dataOut <= 8'h00; + endcase +end + +// reset control +//generate 'rstSyncToBusClk' +//assuming that 'busClk' < 5 * 'spiSysClk'. +always @(posedge busClk) begin + if (rstFromWire == 1'b1 || rstFromBus == 1'b1) + rstShift <= 6'b111111; + else + rstShift <= {1'b0, rstShift[5:1]}; +end + +always @(rstShift) + rstSyncToBusClkOut <= rstShift[0]; + +// double sync across clock domains to generate 'rstSyncToSpiClkOut' +always @(posedge spiSysClk) begin + rstSyncToSpiClkFirst <= rstSyncToBusClkOut; + rstSyncToSpiClkOut <= rstSyncToSpiClkFirst; +end + + +// spi transaction control +//assuming that 'busClk' < 5 * 'spiSysClk'. +always @(posedge busClk) begin + if (rstSyncToBusClkOut == 1'b1) + spiTransCtrlShift <= 6'b000000; + else if (spiTransCtrlSTB == 1'b1) + spiTransCtrlShift <= 6'b111111; + else + spiTransCtrlShift <= {1'b0, spiTransCtrlShift[5:1]}; +end + +//re-sync to spiSysClk +always @(posedge spiSysClk) begin + if (rstSyncToSpiClkOut == 1'b1) begin + spiTransCtrl_reg1 <= 1'b0; + spiTransCtrl_reg2 <= 1'b0; + spiTransCtrl_reg3 <= 1'b0; + end + else begin + spiTransCtrl_reg1 <= spiTransCtrlShift[0]; + spiTransCtrl_reg2 <= spiTransCtrl_reg1; + spiTransCtrl_reg3 <= spiTransCtrl_reg2; + if (spiTransCtrl_reg3 == 1'b0 && spiTransCtrl_reg2 == 1'b1) + spiTransCtrl <= `TRANS_START; + else + spiTransCtrl <= `TRANS_STOP; + end +end + + + +//re-sync from busClk to spiSysClk. +always @(posedge spiSysClk) begin + if (rstSyncToSpiClkOut == 1'b1) begin + spiTransType <= `DIRECT_ACCESS; + spiDirectAccessTxData <= 8'h00; + end + else begin + spiDirectAccessTxData <= spiDirectAccessTxDataSTB; + spiTransType <= spiTransTypeSTB; + end +end + +//re-sync from spiSysClk to busClk +always @(posedge busClk) begin + if (rstSyncToBusClkOut == 1'b1) begin + spiTransStatusSTB <= `TRANS_NOT_BUSY; + spiTransStatusReg1 <= `TRANS_NOT_BUSY; + spiTransStatusReg2 <= `TRANS_NOT_BUSY; + end + else begin + spiTransStatusReg1 <= spiTransStatus; + spiTransStatusReg2 <= spiTransStatusReg1; + if (spiTransCtrlSTB == `TRANS_START) + spiTransStatusSTB <= `TRANS_BUSY; + else if (spiTransStatusReg2 == `TRANS_BUSY && spiTransStatusReg1 == `TRANS_NOT_BUSY) + spiTransStatusSTB <= `TRANS_NOT_BUSY; + end + spiDirectAccessRxDataSTB <= spiDirectAccessRxData; + SDWriteErrorSTB <= SDWriteError; + SDReadErrorSTB <= SDReadError; + SDInitErrorSTB <= SDInitError; +end + +endmodule + diff --git a/usrp2/fpga/opencores/sd_interface/RTL/dpMem_dc.v b/usrp2/fpga/opencores/sd_interface/RTL/dpMem_dc.v new file mode 100644 index 00000000..66cd253f --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/dpMem_dc.v @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dpMem_dc.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// Synchronous dual port memory with dual clocks +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module dpMem_dc( addrIn, addrOut, wrClk, rdClk, dataIn, writeEn, readEn, dataOut); + //FIFO_DEPTH = ADDR_WIDTH^2 + parameter FIFO_WIDTH = 8; + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +input wrClk; +input rdClk; +input [FIFO_WIDTH-1:0] dataIn; +output [FIFO_WIDTH-1:0] dataOut; +input writeEn; +input readEn; +input [ADDR_WIDTH-1:0] addrIn; +input [ADDR_WIDTH-1:0] addrOut; + +wire wrClk; +wire rdClk; +wire [FIFO_WIDTH-1:0] dataIn; +reg [FIFO_WIDTH-1:0] dataOut; +wire writeEn; +wire readEn; +wire [ADDR_WIDTH-1:0] addrIn; +wire [ADDR_WIDTH-1:0] addrOut; + +reg [FIFO_WIDTH-1:0] buffer [0:FIFO_DEPTH-1]; + +// synchronous read. Introduces one clock cycle delay +always @(posedge rdClk) begin + dataOut <= buffer[addrOut]; +end + +// synchronous write +always @(posedge wrClk) begin + if (writeEn == 1'b1) + buffer[addrIn] <= dataIn; +end + + +endmodule diff --git a/usrp2/fpga/opencores/sd_interface/RTL/fifoRTL.v b/usrp2/fpga/opencores/sd_interface/RTL/fifoRTL.v new file mode 100644 index 00000000..a20c4f85 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/fifoRTL.v @@ -0,0 +1,164 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// fifoRTL.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + +module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn, + dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty, + forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo); +//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536 + parameter FIFO_WIDTH = 8; + parameter FIFO_DEPTH = 64; + parameter ADDR_WIDTH = 6; + +// Two clock domains within this module +// These ports are within 'wrClk' domain +input wrClk; +input rstSyncToWrClk; +input [FIFO_WIDTH-1:0] dataIn; +input fifoWEn; +input forceEmptySyncToWrClk; +output fifoFull; + +// These ports are within 'rdClk' domain +input rdClk; +input rstSyncToRdClk; +output [FIFO_WIDTH-1:0] dataOut; +input fifoREn; +input forceEmptySyncToRdClk; +output fifoEmpty; +output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536 + +wire wrClk; +wire rdClk; +wire rstSyncToWrClk; +wire rstSyncToRdClk; +wire [FIFO_WIDTH-1:0] dataIn; +reg [FIFO_WIDTH-1:0] dataOut; +wire fifoWEn; +wire fifoREn; +reg fifoFull; +reg fifoEmpty; +wire forceEmpty; +reg [15:0]numElementsInFifo; + + +// local registers +reg [ADDR_WIDTH:0]bufferInIndex; +reg [ADDR_WIDTH:0]bufferInIndexSyncToRdClk; +reg [ADDR_WIDTH:0]bufferOutIndex; +reg [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk; +reg [ADDR_WIDTH-1:0]bufferInIndexToMem; +reg [ADDR_WIDTH-1:0]bufferOutIndexToMem; +reg [ADDR_WIDTH:0]bufferCnt; +reg fifoREnDelayed; +wire [FIFO_WIDTH-1:0] dataFromMem; + +always @(posedge wrClk) +begin + bufferOutIndexSyncToWrClk <= bufferOutIndex; + if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1) + begin + fifoFull <= 1'b0; + bufferInIndex <= 0; + end + else + begin + if (fifoWEn == 1'b1) begin + bufferInIndex <= bufferInIndex + 1'b1; + end + if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) && + (bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) ) + fifoFull <= 1'b1; + else + fifoFull <= 1'b0; + end +end + +always @(bufferInIndexSyncToRdClk or bufferOutIndex) + bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex; + +always @(posedge rdClk) +begin + numElementsInFifo <= { {16-ADDR_WIDTH-1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes + bufferInIndexSyncToRdClk <= bufferInIndex; + if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1) + begin + fifoEmpty <= 1'b1; + bufferOutIndex <= 0; + fifoREnDelayed <= 1'b0; + end + else + begin + fifoREnDelayed <= fifoREn; + if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin + dataOut <= dataFromMem; + bufferOutIndex <= bufferOutIndex + 1'b1; + end + if (bufferInIndexSyncToRdClk == bufferOutIndex) + fifoEmpty <= 1'b1; + else + fifoEmpty <= 1'b0; + end +end + + +always @(bufferInIndex or bufferOutIndex) begin + bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0]; + bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0]; +end + +dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_dpMem_dc ( + .addrIn(bufferInIndexToMem), + .addrOut(bufferOutIndexToMem), + .wrClk(wrClk), + .rdClk(rdClk), + .dataIn(dataIn), + .writeEn(fifoWEn), + .readEn(fifoREn), + .dataOut(dataFromMem)); + +endmodule diff --git a/usrp2/fpga/opencores/sd_interface/RTL/initSD.asf b/usrp2/fpga/opencores/sd_interface/RTL/initSD.asf new file mode 100644 index 00000000..5be88010 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/initSD.asf @@ -0,0 +1,226 @@ +VERSION=1.15 +HEADER +FILE="initSD.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="initSD" +FRAMES=ON +FREEOID=430 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// initSD.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// parameterized dual clock domain fifo. \n//// fifo depth is restricted to 2^ADDR_WIDTH\n//// No protection against over runs and under runs.\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. 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356 349 2 351 353 BEZIER "Transitions" | 158302,190095 158438,187775 158562,182275 158679,179771 +A 355 351 4 TEXT "Actions" | 166182,199224 1 0 0 "delCnt1 <= delCnt1 + 1'b1;\ndelCnt2 <= 8'h00;\nsendCmdReq <= 1'b0;" +A 354 353 4 TEXT "Actions" | 166728,176565 1 0 0 "delCnt2 <= delCnt2 + 1'b1;" +S 353 349 61440 ELLIPSE "States" | 158538,173289 6500 6500 +L 352 353 0 TEXT "State Labels" | 158538,173289 1 0 0 "DEL2\n/12/" +L 95 96 0 TEXT "Labels" | 155940,273023 1 0 0 "SDInitRdy" +I 368 0 130 Builtin OutPort | 86258,258018 "" "" +I 371 0 130 Builtin OutPort | 86455,252808 "" "" +L 372 371 0 TEXT "Labels" | 92455,252808 1 0 0 "dataByte2[7:0]" +I 373 0 130 Builtin OutPort | 86702,248115 "" "" +L 374 373 0 TEXT "Labels" | 92702,248115 1 0 0 "dataByte3[7:0]" +I 375 0 130 Builtin OutPort | 86702,243422 "" "" +L 376 375 0 TEXT "Labels" | 92702,243422 1 0 0 "dataByte4[7:0]" +L 383 384 0 TEXT "Labels" | 43326,249254 1 0 0 "delCnt1[9:0]" +I 382 0 2 Builtin InPort | 89010,228836 "" "" +L 381 382 0 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Builtin InPort | 152664,268382 "" "" +I 399 0 130 Builtin InPort | 179837,253714 "" "" +L 398 399 0 TEXT "Labels" | 185837,253714 1 0 0 "spiClkDelayIn[7:0]" +I 397 0 130 Builtin OutPort | 150335,263636 "" "" +L 396 397 0 TEXT "Labels" | 156335,263636 1 0 0 "initError[1:0]" +I 395 0 2 Builtin OutPort | 142620,234260 "" "" +L 394 395 0 TEXT "Labels" | 148620,234260 1 0 0 "spiCS_n" +I 391 0 130 Builtin InPort | 88818,224341 "" "" +L 390 391 0 TEXT "Labels" | 94818,224341 1 0 0 "respByte[7:0]" +C 389 388 0 TEXT "Conditions" | 64133,197548 1 0 0 "rst == 1'b1" +W 388 6 0 387 100 BEZIER "Transitions" | 49555,202550 64193,201024 91216,196545 105854,195019 +I 387 6 0 Builtin Reset | 49555,202550 +I 386 0 130 Builtin Signal | 40326,244334 "" "" +L 385 386 0 TEXT "Labels" | 43326,244334 1 0 0 "delCnt2[7:0]" +I 384 0 130 Builtin Signal | 40326,249254 "" "" +C 123 106 0 TEXT "Conditions" | 112795,161807 1 0 0 "SDInitReq == 1'b1" +L 118 117 0 TEXT "Labels" | 148296,254323 1 0 0 "txDataOut[7:0]" +I 117 0 130 Builtin OutPort | 142296,254323 "" "" +L 112 111 0 TEXT "Labels" | 148296,249682 1 0 0 "txDataWen" +L 392 393 0 TEXT "Labels" | 94804,219488 1 0 0 "respTout" +I 393 0 2 Builtin InPort | 88804,219488 "" "" +I 405 0 2 Builtin InPort | 123780,223280 "" "" +L 404 405 0 TEXT "Labels" | 129780,223280 1 0 0 "rxDataRdy" +I 403 0 2 Builtin OutPort | 121620,218480 "" "" +L 402 403 0 TEXT "Labels" | 127620,218480 1 0 0 "rxDataRdyClr" +S 401 142 65536 ELLIPSE "States" | 119702,164354 6500 6500 +L 400 401 0 TEXT "State Labels" | 119702,164354 1 0 0 "WT_DATA_EMPTY\n/13/" +L 135 136 0 TEXT "Labels" | 92903,270215 1 0 0 "spiClkDelayOut[7:0]" +I 136 0 130 Builtin OutPort | 86903,270215 "" "" +A 137 100 4 TEXT "Actions" | 166381,206571 1 0 0 "spiClkDelayOut <= spiClkDelayIn;\nSDInitRdy <= 1'b0;\nspiCS_n <= 1'b1;\ninitError <= `INIT_NO_ERROR;\ntxDataOut <= 8'h00;\ntxDataWen <= 1'b0;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;\nsendCmdReq <= 1'b0;\nloopCnt <= 8'h00;\ndelCnt1 <= 10'h000;\ndelCnt2 <= 8'h00;\nrxDataRdyClr <= 1'b0;" +A 138 102 4 TEXT "Actions" | 122260,190788 1 0 0 "SDInitRdy <= 1'b1;\nspiClkDelayOut <= spiClkDelayIn;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;" +A 139 106 16 TEXT "Actions" | 102988,155532 1 0 0 "SDInitRdy <= 1'b0;\nloopCnt <= 8'h00;\nspiClkDelayOut <= `SLOW_SPI_CLK;\ninitError <= `INIT_NO_ERROR;" +L 140 141 0 TEXT "State Labels" | 111114,126510 1 0 0 "CLK_SEQ" +S 141 6 8196 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111114,126510 6500 6500 +H 142 141 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +A 425 290 4 TEXT "Actions" | 124357,213854 1 0 0 "sendCmdReq <= 1'b0;" +I 421 142 0 Builtin Exit | 134364,140858 +I 145 142 0 Builtin Entry | 63487,251949 +S 149 142 12288 ELLIPSE "States" | 82209,235260 6500 6500 +L 150 149 0 TEXT "State Labels" | 82209,235260 1 0 0 "SEND_FF\n/2/" +S 151 142 16384 ELLIPSE "States" | 83028,207141 6500 6500 +L 152 151 0 TEXT "State Labels" | 83028,207141 1 0 0 "CHK_FIN\n/3/" +W 153 142 0 149 151 BEZIER "Transitions" | 82316,228817 82452,225541 82726,217079 82876,213607 +C 154 153 0 TEXT "Conditions" | 86589,230362 1 0 0 "txDataFull == 1'b0" +A 155 153 16 TEXT "Actions" | 85757,225151 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\nloopCnt <= loopCnt + 1'b1;" +A 156 151 4 TEXT "Actions" | 101046,207687 1 0 0 "txDataWen <= 1'b0;" +L 426 427 0 TEXT "Labels" | 150400,240650 1 0 0 "txDataEmpty" +I 427 0 2 Builtin InPort | 144400,240650 "" "" +W 428 142 0 401 421 BEZIER "Transitions" | 123115,158823 126115,154198 128614,145483 131614,140858 +C 429 428 0 TEXT "Conditions" | 127025,156275 1 0 0 "txDataEmpty == 1'b1" +W 162 142 0 145 149 BEZIER "Transitions" | 67172,251949 70925,248810 74553,243594 78306,240455 +W 164 142 1 151 401 BEZIER "Transitions" | 85234,201030 86934,197154 103559,165433 113217,164792 +C 165 164 0 TEXT "Conditions" | 91028,195541 1 0 0 "loopCnt == `SD_INIT_START_SEQ_LEN" +W 166 142 2 151 149 BEZIER "Transitions" | 76635,205968 69903,206580 58140,206268 54570,210178\ + 51000,214088 50184,228504 53380,232380 56576,236256\ + 69005,235825 75805,236369 +L 167 168 0 TEXT "State Labels" | 111972,95982 1 0 0 "RESET" +S 168 6 20484 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111972,95982 6500 6500 +H 169 168 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +L 191 192 0 TEXT "Labels" | 43350,253948 1 0 0 "loopCnt[7:0]" +I 192 0 130 Builtin Signal | 40350,253948 "" "" +END diff --git a/usrp2/fpga/opencores/sd_interface/RTL/initSD.v b/usrp2/fpga/opencores/sd_interface/RTL/initSD.v new file mode 100644 index 00000000..80b44673 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/initSD.v @@ -0,0 +1,386 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// initSD.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module initSD (checkSumByte, clk, cmdByte, dataByte1, dataByte2, dataByte3, dataByte4, initError, respByte, respTout, rst, rxDataRdy, rxDataRdyClr, SDInitRdy, SDInitReq, sendCmdRdy, sendCmdReq, spiClkDelayIn, spiClkDelayOut, spiCS_n, txDataEmpty, txDataFull, txDataOut, txDataWen); +input clk; +input [7:0]respByte; +input respTout; +input rst; +input rxDataRdy; +input SDInitReq; +input sendCmdRdy; +input [7:0]spiClkDelayIn; +input txDataEmpty; +input txDataFull; +output [7:0]checkSumByte; +output [7:0]cmdByte; +output [7:0]dataByte1; +output [7:0]dataByte2; +output [7:0]dataByte3; +output [7:0]dataByte4; +output [1:0]initError; +output rxDataRdyClr; +output SDInitRdy; +output sendCmdReq; +output [7:0]spiClkDelayOut; +output spiCS_n; +output [7:0]txDataOut; +output txDataWen; + +reg [7:0]checkSumByte, next_checkSumByte; +wire clk; +reg [7:0]cmdByte, next_cmdByte; +reg [7:0]dataByte1, next_dataByte1; +reg [7:0]dataByte2, next_dataByte2; +reg [7:0]dataByte3, next_dataByte3; +reg [7:0]dataByte4, next_dataByte4; +reg [1:0]initError, next_initError; +wire [7:0]respByte; +wire respTout; +wire rst; +wire rxDataRdy; +reg rxDataRdyClr, next_rxDataRdyClr; +reg SDInitRdy, next_SDInitRdy; +wire SDInitReq; +wire sendCmdRdy; +reg sendCmdReq, next_sendCmdReq; +wire [7:0]spiClkDelayIn; +reg [7:0]spiClkDelayOut, next_spiClkDelayOut; +reg spiCS_n, next_spiCS_n; +wire txDataEmpty; +wire txDataFull; +reg [7:0]txDataOut, next_txDataOut; +reg txDataWen, next_txDataWen; + +// diagram signals declarations +reg [9:0]delCnt1, next_delCnt1; +reg [7:0]delCnt2, next_delCnt2; +reg [7:0]loopCnt, next_loopCnt; + +// BINARY ENCODED state machine: initSDSt +// State codes definitions: +`define START 4'b0000 +`define WT_INIT_REQ 4'b0001 +`define CLK_SEQ_SEND_FF 4'b0010 +`define CLK_SEQ_CHK_FIN 4'b0011 +`define RESET_SEND_CMD 4'b0100 +`define RESET_DEL 4'b0101 +`define RESET_WT_FIN 4'b0110 +`define RESET_CHK_FIN 4'b0111 +`define INIT_WT_FIN 4'b1000 +`define INIT_CHK_FIN 4'b1001 +`define INIT_SEND_CMD 4'b1010 +`define INIT_DEL1 4'b1011 +`define INIT_DEL2 4'b1100 +`define CLK_SEQ_WT_DATA_EMPTY 4'b1101 + +reg [3:0]CurrState_initSDSt, NextState_initSDSt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: initSDSt + +// NextState logic (combinatorial) +always @ (spiClkDelayIn or SDInitReq or txDataFull or loopCnt or sendCmdRdy or respTout or respByte or delCnt1 or delCnt2 or txDataEmpty or spiClkDelayOut or SDInitRdy or spiCS_n or initError or txDataOut or txDataWen or cmdByte or dataByte1 or dataByte2 or dataByte3 or dataByte4 or checkSumByte or sendCmdReq or rxDataRdyClr or CurrState_initSDSt) +begin + NextState_initSDSt <= CurrState_initSDSt; + // Set default values for outputs and signals + next_spiClkDelayOut <= spiClkDelayOut; + next_SDInitRdy <= SDInitRdy; + next_spiCS_n <= spiCS_n; + next_initError <= initError; + next_txDataOut <= txDataOut; + next_txDataWen <= txDataWen; + next_cmdByte <= cmdByte; + next_dataByte1 <= dataByte1; + next_dataByte2 <= dataByte2; + next_dataByte3 <= dataByte3; + next_dataByte4 <= dataByte4; + next_checkSumByte <= checkSumByte; + next_sendCmdReq <= sendCmdReq; + next_loopCnt <= loopCnt; + next_delCnt1 <= delCnt1; + next_delCnt2 <= delCnt2; + next_rxDataRdyClr <= rxDataRdyClr; + case (CurrState_initSDSt) // synopsys parallel_case full_case + `START: + begin + next_spiClkDelayOut <= spiClkDelayIn; + next_SDInitRdy <= 1'b0; + next_spiCS_n <= 1'b1; + next_initError <= `INIT_NO_ERROR; + next_txDataOut <= 8'h00; + next_txDataWen <= 1'b0; + next_cmdByte <= 8'h00; + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h00; + next_sendCmdReq <= 1'b0; + next_loopCnt <= 8'h00; + next_delCnt1 <= 10'h000; + next_delCnt2 <= 8'h00; + next_rxDataRdyClr <= 1'b0; + NextState_initSDSt <= `WT_INIT_REQ; + end + `WT_INIT_REQ: + begin + next_SDInitRdy <= 1'b1; + next_spiClkDelayOut <= spiClkDelayIn; + next_cmdByte <= 8'h00; + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h00; + if (SDInitReq == 1'b1) + begin + NextState_initSDSt <= `CLK_SEQ_SEND_FF; + next_SDInitRdy <= 1'b0; + next_loopCnt <= 8'h00; + next_spiClkDelayOut <= `SLOW_SPI_CLK; + next_initError <= `INIT_NO_ERROR; + end + end + `CLK_SEQ_SEND_FF: + begin + if (txDataFull == 1'b0) + begin + NextState_initSDSt <= `CLK_SEQ_CHK_FIN; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_loopCnt <= loopCnt + 1'b1; + end + end + `CLK_SEQ_CHK_FIN: + begin + next_txDataWen <= 1'b0; + if (loopCnt == `SD_INIT_START_SEQ_LEN) + begin + NextState_initSDSt <= `CLK_SEQ_WT_DATA_EMPTY; + end + else + begin + NextState_initSDSt <= `CLK_SEQ_SEND_FF; + end + end + `CLK_SEQ_WT_DATA_EMPTY: + begin + if (txDataEmpty == 1'b1) + begin + NextState_initSDSt <= `RESET_SEND_CMD; + next_loopCnt <= 8'h00; + end + end + `RESET_SEND_CMD: + begin + next_cmdByte <= 8'h40; + //CMD0 + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h95; + next_sendCmdReq <= 1'b1; + next_loopCnt <= loopCnt + 1'b1; + next_spiCS_n <= 1'b0; + NextState_initSDSt <= `RESET_DEL; + end + `RESET_DEL: + begin + next_sendCmdReq <= 1'b0; + NextState_initSDSt <= `RESET_WT_FIN; + end + `RESET_WT_FIN: + begin + if (sendCmdRdy == 1'b1) + begin + NextState_initSDSt <= `RESET_CHK_FIN; + next_spiCS_n <= 1'b1; + end + end + `RESET_CHK_FIN: + begin + if ((respTout == 1'b1 || respByte != 8'h01) && loopCnt != 8'hff) + begin + NextState_initSDSt <= `RESET_SEND_CMD; + end + else if (respTout == 1'b1 || respByte != 8'h01) + begin + NextState_initSDSt <= `WT_INIT_REQ; + next_initError <= `INIT_CMD0_ERROR; + end + else + begin + NextState_initSDSt <= `INIT_SEND_CMD; + end + end + `INIT_WT_FIN: + begin + if (sendCmdRdy == 1'b1) + begin + NextState_initSDSt <= `INIT_CHK_FIN; + next_spiCS_n <= 1'b1; + end + end + `INIT_CHK_FIN: + begin + if ((respTout == 1'b1 || respByte != 8'h00) && loopCnt != 8'hff) + begin + NextState_initSDSt <= `INIT_SEND_CMD; + end + else if (respTout == 1'b1 || respByte != 8'h00) + begin + NextState_initSDSt <= `WT_INIT_REQ; + next_initError <= `INIT_CMD1_ERROR; + end + else + begin + NextState_initSDSt <= `WT_INIT_REQ; + end + end + `INIT_SEND_CMD: + begin + next_cmdByte <= 8'h41; + //CMD1 + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'hff; + next_sendCmdReq <= 1'b1; + next_loopCnt <= loopCnt + 1'b1; + next_spiCS_n <= 1'b0; + next_delCnt1 <= 10'h000; + NextState_initSDSt <= `INIT_DEL1; + end + `INIT_DEL1: + begin + next_delCnt1 <= delCnt1 + 1'b1; + next_delCnt2 <= 8'h00; + next_sendCmdReq <= 1'b0; + if (delCnt1 == `TWO_MS) + begin + NextState_initSDSt <= `INIT_WT_FIN; + end + else + begin + NextState_initSDSt <= `INIT_DEL2; + end + end + `INIT_DEL2: + begin + next_delCnt2 <= delCnt2 + 1'b1; + if (delCnt2 == 8'hff) + begin + NextState_initSDSt <= `INIT_DEL1; + end + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_initSDSt <= `START; + else + CurrState_initSDSt <= NextState_initSDSt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + spiClkDelayOut <= spiClkDelayIn; + SDInitRdy <= 1'b0; + spiCS_n <= 1'b1; + initError <= `INIT_NO_ERROR; + txDataOut <= 8'h00; + txDataWen <= 1'b0; + cmdByte <= 8'h00; + dataByte1 <= 8'h00; + dataByte2 <= 8'h00; + dataByte3 <= 8'h00; + dataByte4 <= 8'h00; + checkSumByte <= 8'h00; + sendCmdReq <= 1'b0; + rxDataRdyClr <= 1'b0; + loopCnt <= 8'h00; + delCnt1 <= 10'h000; + delCnt2 <= 8'h00; + end + else + begin + spiClkDelayOut <= next_spiClkDelayOut; + SDInitRdy <= next_SDInitRdy; + spiCS_n <= next_spiCS_n; + initError <= next_initError; + txDataOut <= next_txDataOut; + txDataWen <= next_txDataWen; + cmdByte <= next_cmdByte; + dataByte1 <= next_dataByte1; + dataByte2 <= next_dataByte2; + dataByte3 <= next_dataByte3; + dataByte4 <= next_dataByte4; + checkSumByte <= next_checkSumByte; + sendCmdReq <= next_sendCmdReq; + rxDataRdyClr <= next_rxDataRdyClr; + loopCnt <= next_loopCnt; + delCnt1 <= next_delCnt1; + delCnt2 <= next_delCnt2; + end +end + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/sd_interface/RTL/readWriteSDBlock.asf b/usrp2/fpga/opencores/sd_interface/RTL/readWriteSDBlock.asf new file mode 100644 index 00000000..32e59f00 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/readWriteSDBlock.asf @@ -0,0 +1,528 @@ +VERSION=1.15 +HEADER +FILE="readWriteSDBlock.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="readWriteSDBlock" +FRAMES=ON +FREEOID=575 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// readWriteSDBlock.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// parameterized dual clock domain fifo. \n//// fifo depth is restricted to 2^ADDR_WIDTH\n//// No protection against over runs and under runs.\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 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106026,166550 6500 6500 +W 350 338 0 368 369 BEZIER "Transitions" | 67549,239359 76627,234752 86180,250238 95258,245631 +C 349 348 0 TEXT "Conditions" | 111780,160832 1 0 0 "rxDataRdy == 1'b1" +W 348 338 0 351 346 BEZIER "Transitions" | 109408,161002 116386,149688 110826,148678 118545,137753 +L 347 346 0 TEXT "State Labels" | 122076,132298 1 0 0 "CHK_LOOP\n/26/" +S 346 338 135168 ELLIPSE "States" | 122076,132298 6500 6500 +H 338 337 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +S 337 6 131076 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 155556,94377 6500 6500 +L 336 337 0 TEXT "State Labels" | 155556,94377 1 0 0 "RD_TOKEN" +I 74 0 2 Builtin InPort | 195700,267632 "" "" +L 73 74 0 TEXT "Labels" | 201700,267632 1 0 0 "rst" +I 72 0 3 Builtin InPort | 195700,272800 "" "" +L 71 72 0 TEXT "Labels" | 201700,272800 1 0 0 "clk" +L 367 359 0 TEXT "State Labels" | 106340,218687 1 0 0 "SEND_CMD\n/28/" +L 366 365 0 TEXT "State Labels" | 53406,179998 1 0 0 "DEL2\n/29/" +S 365 338 147456 ELLIPSE "States" | 53406,179998 6500 6500 +W 364 338 3 346 361 BEZIER "Transitions" | 123583,125978 114391,113159 121643,95942 132878,90341 +I 361 338 0 Builtin Exit | 135456,90208 +A 360 359 4 TEXT "Actions" | 121852,234949 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\nrxDataRdyClr <= 1'b1;" +S 359 338 143360 ELLIPSE "States" | 106340,218687 6500 6500 +L 352 351 0 TEXT "State Labels" | 106026,166550 1 0 0 "WT_FIN\n/27/" +L 81 82 0 TEXT "State Labels" | 113220,195514 1 0 0 "ST_RW_SD\n/0/" +S 82 6 0 ELLIPSE "States" | 113220,195514 6500 6500 +L 83 84 0 TEXT "State Labels" | 115395,109896 1 0 0 "WR_CMD" +S 84 6 4100 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 115395,109896 6500 6500 +H 85 84 0 RECT 0,0,0 0 0 1 255,255,255 0 | 27860,28670 212360,276670 +S 92 85 8192 ELLIPSE "States" | 113016,225828 6500 6500 +L 93 92 0 TEXT "State Labels" | 113016,225828 1 0 0 "SEND_CMD\n/1/" +I 94 85 0 Builtin Entry | 70040,246500 +W 383 338 2 346 385 BEZIER "Transitions" | 128455,133541 138850,135296 180442,141646 191036,142273 +W 382 338 0 380 351 BEZIER "Transitions" | 105524,186872 105457,182130 105515,177755 105448,173013 +W 381 338 0 359 380 BEZIER "Transitions" | 105523,212247 105320,208453 105367,203608 105164,199814 +S 380 338 155648 ELLIPSE "States" | 105765,193344 6500 6500 +L 379 380 0 TEXT "State Labels" | 105765,193344 1 0 0 "DEL1\n/31/" +C 377 374 0 TEXT "Conditions" | 32353,125947 1 0 0 "locRespByte != 8'hfe && timeOutCnt != `ONE_HUNDRED_MS" +C 376 375 0 TEXT "Conditions" | 37395,199964 1 0 0 "delCnt1 == `MAX_8_BIT" +W 375 338 1 365 359 BEZIER "Transitions" | 55933,185983 60073,191941 68179,216209 76636,218125\ + 85094,220041 90522,226339 93570,226372 96618,226406\ + 99403,224529 101638,223174 +W 374 338 1 346 365 BEZIER "Transitions" | 116959,136304 87922,130964 55868,158884 57051,176025 +A 373 365 4 TEXT "Actions" | 64312,187877 1 0 0 "delCnt1 <= delCnt1 + 1'b1;\ndelCnt2 <= 8'h00;" +L 372 369 0 TEXT "State Labels" | 101285,243200 1 0 0 "INIT_LOOP\n/30/" +W 371 338 0 369 359 BEZIER "Transitions" | 101997,236742 102942,232760 103652,228930 104597,224948 +A 370 369 4 TEXT "Actions" | 114245,248870 1 0 0 "timeOutCnt <= 12'h000;" +S 369 338 151552 ELLIPSE "States" | 101285,243200 6500 6500 +I 368 338 0 Builtin Entry | 63364,239359 +W 98 85 0 103 118 BEZIER "Transitions" | 116097,168149 122999,156907 117254,149606 126108,141591 +C 99 98 0 TEXT "Conditions" | 118453,167900 1 0 0 "sendCmdRdy == 1'b1" +W 100 85 0 94 92 BEZIER "Transitions" | 73698,246500 82776,241893 98521,234027 107599,229420 +W 101 85 0 105 103 BEZIER "Transitions" | 112750,192148 112615,188422 112530,183906 112395,180180 +W 102 85 0 92 105 BEZIER "Transitions" | 112802,219339 112802,215071 112860,209370 112860,205102 +S 103 85 12288 ELLIPSE "States" | 112702,173691 6500 6500 +L 104 103 0 TEXT "State Labels" | 112702,173691 1 0 0 "WT_FIN\n/2/" +S 105 85 16384 ELLIPSE "States" | 113244,198623 6500 6500 +L 106 105 0 TEXT "State Labels" | 113244,198623 1 0 0 "DEL\n/3/" +A 107 92 4 TEXT "Actions" | 128528,242090 1 0 0 "cmdByte <= 8'h58; //CMD24 Block Write\ndataByte1 <= blockAddr[31:24];\ndataByte2 <= blockAddr[23:16];\ndataByte3 <= blockAddr[15:8];\ndataByte4 <= blockAddr[7:0];\ncheckSumByte <= 8'hff;\nsendCmdReq <= 1'b1;" +I 108 85 0 Builtin Exit | 143492,98981 +I 109 85 0 Builtin Link | 155880,111943 +L 110 109 0 TEXT "Labels" | 161880,111943 1 0 0 "WT_REQ" +W 111 85 2 118 109 BEZIER "Transitions" | 130637,137393 136286,130668 150231,116668 155880,109943 +A 387 383 16 TEXT "Actions" | 144060,138060 1 0 0 "readError <= `READ_TOKEN_ERROR;" +C 386 383 0 TEXT "Conditions" | 128229,146101 1 0 0 "timeOutCnt == `ONE_HUNDRED_MS" +I 385 338 0 Builtin Link | 190990,144650 +L 384 385 0 TEXT "Labels" | 196990,144650 1 0 0 "WT_REQ" +C 112 111 0 TEXT "Conditions" | 136613,139155 1 0 0 "respTout == 1'b1 || respByte != 8'h00" +A 113 111 16 TEXT "Actions" | 138698,128165 1 0 0 "writeError <= `WRITE_CMD_ERROR;" +W 116 85 3 118 108 BEZIER "Transitions" | 129307,136589 132634,127911 137330,107659 140657,98981 +L 117 118 0 TEXT "State Labels" | 128402,139117 1 0 0 "J1" +S 118 85 20484 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 128334,139455 3156 3017 +H 119 118 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +I 122 119 0 Builtin Entry | 96520,182880 +I 123 119 0 Builtin Exit | 110928,166692 +W 126 119 0 122 123 BEZIER "Transitions" | 100205,182880 103344,179877 105196,169695 108335,166692 +L 127 128 0 TEXT "State Labels" | 114166,175079 1 0 0 "WT_REQ\n/4/" +L 388 389 0 TEXT "State Labels" | 155343,73929 1 0 0 "RD_DATA" +S 389 6 159748 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 155343,73929 6500 6500 +H 390 389 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +S 128 6 24576 ELLIPSE "States" | 114166,175079 6500 6500 +L 129 130 0 TEXT "State Labels" | 116508,88574 1 0 0 "WR_TOKEN" +S 130 6 28676 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116508,88574 6500 6500 +H 131 130 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +W 138 131 0 144 141 BEZIER "Transitions" | 93143,232118 93346,228934 95399,216673 95425,213277 +A 139 138 16 TEXT "Actions" | 83596,226272 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +C 140 138 0 TEXT "Conditions" | 95421,232225 1 0 0 "txDataFull == 1'b0" +S 141 131 32768 ELLIPSE "States" | 95726,206806 6500 6500 +L 142 141 0 TEXT "State Labels" | 95726,206806 1 0 0 "FF1_FIN\n/5/" +A 143 141 4 TEXT "Actions" | 105171,209122 1 0 0 "txDataWen <= 1'b0;" +L 400 401 0 TEXT "State Labels" | 77852,226948 1 0 0 "ST_LOOP\n/32/" +S 401 390 163840 ELLIPSE "States" | 77852,226948 6500 6500 +A 402 401 4 TEXT "Actions" | 95196,229658 1 0 0 "txDataWen <= 1'b1;\ntxDataOut <= 8'hff;\nloopCnt <= loopCnt + 1'b1;" +L 403 404 0 TEXT "State Labels" | 78936,199306 1 0 0 "WT_DATA\n/33/" +S 404 390 167936 ELLIPSE "States" | 78936,199306 6500 6500 +W 406 390 0 401 404 BEZIER "Transitions" | 77695,220483 77762,216960 78169,209653 78270,205764 +A 408 404 4 TEXT "Actions" | 97364,200119 1 0 0 "txDataWen <= 1'b0;" +L 409 410 0 TEXT "State Labels" | 81375,162450 1 0 0 "CHK_LOOP\n/34/" +S 410 390 172032 ELLIPSE "States" | 81375,162450 6500 6500 +W 411 390 0 404 410 BEZIER "Transitions" | 79226,192822 79632,188351 80587,173613 80938,168928 +C 412 411 0 TEXT "Conditions" | 81955,194246 1 0 0 "rxDataRdy == 1'b1" +A 413 411 16 TEXT "Actions" | 74786,189659 1 0 0 "rxFifoWen <= 1'b1;\nrxDataRdyClr <= 1'b1;\nrxFifoData <= rxDataIn;" +L 414 415 0 TEXT "State Labels" | 83004,136975 1 0 0 "J1" +S 415 390 176132 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 83043,136396 3569 3569 +S 144 131 36864 ELLIPSE "States" | 92762,238598 6500 6500 +L 145 144 0 TEXT "State Labels" | 92762,238598 1 0 0 "FF1_ST\n/6/" +I 146 131 0 Builtin Entry | 51952,266176 +S 147 131 40960 ELLIPSE "States" | 101439,148824 6500 6500 +A 148 147 4 TEXT "Actions" | 110884,151140 1 0 0 "txDataWen <= 1'b0;" +L 149 147 0 TEXT "State Labels" | 101439,148824 1 0 0 "FF2_FIN\n/7/" +W 150 131 0 153 147 BEZIER "Transitions" | 98856,174136 99059,170952 101112,158691 101138,155295 +C 151 150 0 TEXT "Conditions" | 101134,174243 1 0 0 "txDataFull == 1'b0" +A 152 150 16 TEXT "Actions" | 89309,168290 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +S 153 131 45056 ELLIPSE "States" | 98475,180616 6500 6500 +L 154 153 0 TEXT "State Labels" | 98475,180616 1 0 0 "FF2_ST\n/8/" +S 155 131 49152 ELLIPSE "States" | 107423,92248 6500 6500 +A 156 155 4 TEXT "Actions" | 116868,94564 1 0 0 "txDataWen <= 1'b0;" +L 157 155 0 TEXT "State Labels" | 107423,92248 1 0 0 "FE_FIN\n/9/" +W 158 131 0 161 155 BEZIER "Transitions" | 104840,117560 105043,114376 107096,102115 107122,98719 +C 159 158 0 TEXT "Conditions" | 107118,117667 1 0 0 "txDataFull == 1'b0" +H 416 415 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +I 419 416 0 Builtin Entry | 126004,141930 +I 420 416 0 Builtin Exit | 144780,121920 +W 423 416 0 419 420 BEZIER "Transitions" | 129826,141930 134057,136743 137819,127107 142050,121920 +W 424 390 0 410 415 BEZIER "Transitions" | 81407,156099 81677,152387 82370,143719 82390,139900 +A 425 424 16 TEXT "Actions" | 80070,154260 1 0 0 "rxDataRdyClr <= 1'b0;\nrxFifoWen <= 1'b0;" +I 426 390 0 Builtin Entry | 42810,270090 +L 427 428 0 TEXT "State Labels" | 97350,266040 1 0 0 "CLR_RX\n/35/" +S 428 390 180224 ELLIPSE "States" | 97350,266040 6500 6500 +W 429 390 0 426 428 BEZIER "Transitions" | 46995,270090 55230,269685 82688,267193 90992,267387 +A 430 429 16 TEXT "Actions" | 55533,269709 1 0 0 "rxDataRdyClr <= 1'b1;" +W 431 390 0 428 401 BEZIER "Transitions" | 94484,260209 90569,252717 84564,240304 80649,232812 +A 160 158 16 TEXT "Actions" | 95293,111714 1 0 0 "txDataOut <= 8'hfe;\ntxDataWen <= 1'b1;" +S 161 131 53248 ELLIPSE "States" | 104459,124040 6500 6500 +L 162 161 0 TEXT "State Labels" | 104459,124040 1 0 0 "FE_ST\n/10/" +W 163 131 0 146 144 BEZIER "Transitions" | 55624,266176 64736,260940 79060,248435 88172,243199 +W 164 131 0 141 153 BEZIER "Transitions" | 95785,200373 96397,196089 96746,191299 97358,187015 +I 165 131 0 Builtin Exit | 140624,67616 +W 166 131 0 147 161 BEZIER "Transitions" | 101803,142336 102279,138596 102801,134171 103277,130431 +W 167 131 0 155 165 BEZIER "Transitions" | 112534,88234 120218,83134 130356,72716 138040,67616 +L 168 169 0 TEXT "State Labels" | 116501,66078 1 0 0 "WR_DATA" +S 169 6 229380 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116501,66078 6500 6500 +H 170 169 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +A 432 431 16 TEXT "Actions" | 85200,253080 1 0 0 "rxDataRdyClr <= 1'b0;\nloopCnt <= 9'b000000000;" +W 433 390 2 415 401 BEZIER "Transitions" | 79771,137821 72144,141736 57457,148725 53070,158681\ + 48683,168637 46387,200633 47433,211027 48480,221422\ + 54960,231008 58470,232695 61980,234383 68385,231511\ + 72165,230094 +W 440 390 0 451 441 BEZIER "Transitions" | 138130,91528 138333,88344 140386,76083 140412,72687 +S 441 390 184320 ELLIPSE "States" | 140713,66216 6500 6500 +L 442 441 0 TEXT "State Labels" | 140713,66216 1 0 0 "CS_FIN2\n/36/" +S 443 390 188416 ELLIPSE "States" | 75739,66216 6500 6500 +A 444 443 4 TEXT "Actions" | 85184,68532 1 0 0 "txDataWen <= 1'b0;" +L 445 443 0 TEXT "State Labels" | 75739,66216 1 0 0 "CS_FIN1\n/37/" +W 446 390 0 449 443 BEZIER "Transitions" | 73156,91528 73359,88344 75412,76083 75438,72687 +C 447 446 0 TEXT "Conditions" | 75434,91635 1 0 0 "txDataFull == 1'b0" +S 177 170 61440 ELLIPSE "States" | 78305,137464 6500 6500 +A 178 177 4 TEXT "Actions" | 87750,139780 1 0 0 "txDataWen <= 1'b0;" +L 179 177 0 TEXT "State Labels" | 78305,137464 1 0 0 "D_FIN\n/11/" +W 180 170 0 183 177 BEZIER "Transitions" | 75722,162776 75925,159592 77978,147331 78004,143935 +C 181 180 0 TEXT "Conditions" | 78000,162883 1 0 0 "txDataFull == 1'b0" +A 182 180 16 TEXT "Actions" | 66175,156930 1 0 0 "txDataOut <= txFifoData;\ntxDataWen <= 1'b1;" +S 183 170 65536 ELLIPSE "States" | 75341,169256 6500 6500 +L 184 183 0 TEXT "State Labels" | 75341,169256 1 0 0 "D_ST\n/12/" +L 187 188 0 TEXT "State Labels" | 72867,227889 1 0 0 "RD_FIFO1\n/13/" +S 188 170 69632 ELLIPSE "States" | 72867,227889 6500 6500 +L 189 190 0 TEXT "State Labels" | 73959,201135 1 0 0 "RD_FIFO2\n/14/" +S 190 170 73728 ELLIPSE "States" | 73959,201135 6500 6500 +A 191 188 4 TEXT "Actions" | 80895,230061 1 0 0 "txFifoRen <= 1'b1;\nloopCnt <= loopCnt + 1'b1;" +A 448 446 16 TEXT "Actions" | 63609,85682 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +S 449 390 192512 ELLIPSE "States" | 72775,98008 6500 6500 +L 450 449 0 TEXT "State Labels" | 72775,98008 1 0 0 "CS_ST1\n/38/" +S 451 390 196608 ELLIPSE "States" | 137749,98008 6500 6500 +L 452 451 0 TEXT "State Labels" | 137749,98008 1 0 0 "CS_ST2\n/39/" +A 453 440 16 TEXT "Actions" | 128583,85682 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +C 454 440 0 TEXT "Conditions" | 140408,91635 1 0 0 "txDataFull == 1'b0" +A 455 441 4 TEXT "Actions" | 150158,68532 1 0 0 "txDataWen <= 1'b0;" +W 456 390 1 415 449 BEZIER "Transitions" | 82185,132936 79630,124866 76715,112427 74160,104357 +W 457 390 0 443 451 BEZIER "Transitions" | 78514,60339 82952,55834 89399,47074 95182,45998\ + 100965,44922 115223,49631 117845,56120 120468,62609\ + 116702,83861 117071,91594 117441,99328 122688,109012\ + 125276,109920 127865,110828 131449,106344 134004,103318 +I 458 390 0 Builtin Exit | 161625,43107 +W 459 390 0 441 458 BEZIER "Transitions" | 144285,60786 148925,56213 153892,47680 158532,43107 +W 460 6 0 302 337 BEZIER "Transitions" | 155788,108419 155653,104081 155771,105011 155438,100848 +W 461 6 0 337 389 BEZIER "Transitions" | 155952,87899 155619,83040 155938,84926 155805,80404 +W 462 6 0 389 128 BEZIER "Transitions" | 160766,72622 181673,64668 193592,81881 194705,86831\ + 195819,91782 193010,106602 196539,114884 200068,123167\ + 183067,150177 177992,160070 172917,169964 164106,188182\ + 156924,189345 149743,190509 134447,187583 129526,185887\ + 124606,184192 121267,181269 119073,179341 +W 463 6 0 224 128 BEZIER "Transitions" | 112148,42964 96171,38095 88076,46646 81324,48345\ + 74572,50044 62626,66620 61422,77634 60219,88648\ + 53118,140235 53550,154499 53982,168763 75928,188049\ + 79879,189622 83830,191195 94548,186386 97872,185422\ + 101197,184458 106213,181091 109338,179429 +A 192 190 4 TEXT "Actions" | 82521,204408 1 0 0 "txFifoRen <= 1'b0;" +L 193 194 0 TEXT "State Labels" | 72048,257646 1 0 0 "LOOP_INIT\n/15/" +S 194 170 77824 ELLIPSE "States" | 72048,257646 6500 6500 +A 195 194 4 TEXT "Actions" | 89247,259284 1 0 0 "loopCnt <= 9'b000000000;" +S 196 170 81920 ELLIPSE "States" | 80801,98549 6500 6500 +L 197 196 0 TEXT "State Labels" | 80801,98549 1 0 0 "CS_ST1\n/16/" +W 198 170 0 196 201 BEZIER "Transitions" | 81182,92069 81385,88885 83438,76624 83464,73228 +A 199 198 16 TEXT "Actions" | 71635,86223 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +C 200 198 0 TEXT "Conditions" | 83460,92176 1 0 0 "txDataFull == 1'b0" +S 201 170 86016 ELLIPSE "States" | 83765,66757 6500 6500 +L 202 201 0 TEXT "State Labels" | 83765,66757 1 0 0 "CS_FIN1\n/17/" +A 203 201 4 TEXT "Actions" | 93210,69073 1 0 0 "txDataWen <= 1'b0;" +S 204 170 90112 ELLIPSE "States" | 148739,66757 6500 6500 +A 205 204 4 TEXT "Actions" | 158184,69073 1 0 0 "txDataWen <= 1'b0;\ntimeOutCnt <= 12'h000;" +L 206 204 0 TEXT "State Labels" | 148739,66757 1 0 0 "CS_FIN2\n/18/" +W 207 170 0 210 204 BEZIER "Transitions" | 146156,92069 146359,88885 148412,76624 148438,73228 +C 464 334 0 TEXT "Conditions" | 94994,146397 1 0 0 "readWriteSDBlockReq == `READ_SD_BLOCK" +C 465 298 0 TEXT "Conditions" | 55739,152492 1 0 0 "readWriteSDBlockReq == `WRITE_SD_BLOCK" +I 475 6 0 Builtin Reset | 49660,206134 +W 476 6 0 475 82 BEZIER "Transitions" | 49660,206134 64556,204256 92040,199052 106936,197174 +C 477 476 0 TEXT "Conditions" | 62428,209528 1 0 0 "rst == 1'b1" +L 478 479 0 TEXT "Labels" | 122230,269291 1 0 0 "readWriteSDBlockReq[1:0]" +I 479 0 130 Builtin InPort | 116230,269291 "" "" +L 223 224 0 TEXT "State Labels" | 116398,45340 1 0 0 "WR_BUSY" +C 208 207 0 TEXT "Conditions" | 148434,92176 1 0 0 "txDataFull == 1'b0" +A 209 207 16 TEXT "Actions" | 136609,86223 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;" +S 210 170 94208 ELLIPSE "States" | 145775,98549 6500 6500 +L 211 210 0 TEXT "State Labels" | 145775,98549 1 0 0 "CS_ST2\n/19/" +W 212 170 1 177 196 BEZIER "Transitions" | 78835,130988 79312,123617 80043,112406 80520,105035 +C 213 212 0 TEXT "Conditions" | 81603,129336 1 0 0 "loopCnt == 9'b000000000" +W 214 170 0 194 188 BEZIER "Transitions" | 72189,251169 72121,246119 72460,239413 72392,234363 +W 215 170 0 188 190 BEZIER "Transitions" | 72773,221428 73182,217197 73251,211851 73660,207620 +W 216 170 0 190 183 BEZIER "Transitions" | 74343,194648 74411,189188 74887,181191 74955,175731 +W 217 170 2 177 188 BEZIER "Transitions" | 71806,137461 65254,138211 53484,138960 49969,147866\ + 46455,156772 45498,190898 45396,201715 45294,212532\ + 45840,221679 48843,224169 51846,226660 60640,227203\ + 66373,227612 +W 218 170 0 201 210 BEZIER "Transitions" | 87098,61178 91397,57971 97506,51735 102658,50541\ + 107811,49347 119823,50985 122894,57434 125965,63884\ + 126239,88045 127637,96576 129036,105107 134361,115072\ + 136749,115515 139137,115959 142020,108931 144135,104836 +I 221 170 0 Builtin Entry | 39834,267201 +W 222 170 0 221 194 BEZIER "Transitions" | 43519,267201 49798,265427 59580,261403 65859,259629 +L 480 481 0 TEXT "Labels" | 120083,264098 1 0 0 "readWriteSDBlockRdy" +I 481 0 2 Builtin OutPort | 114083,264098 "" "" +L 482 483 0 TEXT "Labels" | 120083,259063 1 0 0 "spiCS_n" +I 483 0 2 Builtin OutPort | 114083,259063 "" "" +I 484 0 130 Builtin OutPort | 69013,272215 "" "" +L 485 484 0 TEXT "Labels" | 75013,272215 1 0 0 "cmdByte[7:0]" +I 486 0 130 Builtin OutPort | 68768,267735 "" "" +L 487 486 0 TEXT "Labels" | 74768,267735 1 0 0 "dataByte1[7:0]" +I 488 0 130 Builtin OutPort | 68965,262525 "" "" +L 489 488 0 TEXT "Labels" | 74965,262525 1 0 0 "dataByte2[7:0]" +I 490 0 130 Builtin OutPort | 69212,257832 "" "" +L 491 490 0 TEXT "Labels" | 75212,257832 1 0 0 "dataByte3[7:0]" +I 492 0 130 Builtin OutPort | 69212,253139 "" "" +L 493 492 0 TEXT "Labels" | 75212,253139 1 0 0 "dataByte4[7:0]" +I 494 0 130 Builtin OutPort | 69088,248199 "" "" +L 495 494 0 TEXT "Labels" | 75088,248199 1 0 0 "checkSumByte[7:0]" +W 239 225 1 237 241 BEZIER "Transitions" | 110570,148995 94430,151147 64068,154038 55628,162847\ + 47189,171657 45708,202593 49575,212814 53442,223036\ + 70390,232990 77013,235243 83637,237496 90160,236699\ + 94934,236229 +L 238 237 0 TEXT "State Labels" | 117061,148658 1 0 0 "CHK_FIN\n/40/" +S 237 225 200704 ELLIPSE "States" | 117061,148658 6500 6500 +C 236 235 0 TEXT "Conditions" | 106765,177192 1 0 0 "rxDataRdy == 1'b1" +W 235 225 0 232 237 BEZIER "Transitions" | 104393,177362 111371,166048 105811,165038 113530,154113 +W 234 225 0 240 268 BEZIER "Transitions" | 62534,255719 71612,251112 81165,266598 90243,261991 +L 233 232 0 TEXT "State Labels" | 101011,182910 1 0 0 "WT_FIN1\n/41/" +S 232 225 204800 ELLIPSE "States" | 101011,182910 6500 6500 +H 225 224 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +S 224 6 57348 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 116398,45340 6500 6500 +I 496 0 2 Builtin OutPort | 69306,243719 "" "" +L 497 496 0 TEXT "Labels" | 75306,243719 1 0 0 "sendCmdReq" +I 498 0 2 Builtin InPort | 71520,238553 "" "" +L 499 498 0 TEXT "Labels" | 77520,238553 1 0 0 "sendCmdRdy" +I 500 0 130 Builtin InPort | 71328,234058 "" "" +L 501 500 0 TEXT "Labels" | 77328,234058 1 0 0 "respByte[7:0]" +I 502 0 2 Builtin InPort | 150168,237862 "" "" +L 503 502 0 TEXT "Labels" | 156168,237862 1 0 0 "rxDataRdy" +I 504 0 2 Builtin InPort | 117135,232948 "" "" +L 505 504 0 TEXT "Labels" | 123135,232948 1 0 0 "txDataFull" +I 506 0 2 Builtin OutPort | 114678,237589 "" "" +L 507 506 0 TEXT "Labels" | 120678,237589 1 0 0 "txDataWen" +I 508 0 130 Builtin InPort | 149895,241957 "" "" +L 509 508 0 TEXT "Labels" | 155895,241957 1 0 0 "rxDataIn[7:0]" +I 510 0 130 Builtin OutPort | 114678,242230 "" "" +L 511 510 0 TEXT "Labels" | 120678,242230 1 0 0 "txDataOut[7:0]" +L 527 528 0 TEXT "Labels" | 190950,242120 1 0 0 "rxFifoData[7:0]" +I 526 0 2 Builtin OutPort | 185220,246980 "" "" +L 525 526 0 TEXT "Labels" | 191220,246980 1 0 0 "rxFifoWen" +I 524 0 130 Builtin InPort | 187380,252110 "" "" +L 523 524 0 TEXT "Labels" | 193380,252110 1 0 0 "txFifoData[7:0]" +I 522 0 2 Builtin OutPort | 184950,256970 "" "" +L 521 522 0 TEXT "Labels" | 190950,256970 1 0 0 "txFifoRen" +W 248 225 2 237 251 BEZIER "Transitions" | 121126,143587 165099,138575 140782,115097 127863,106694 +A 249 248 16 TEXT "Actions" | 144590,131826 1 0 0 "writeError <= `WRITE_BUSY_ERROR;" +C 250 248 0 TEXT "Conditions" | 128858,147492 1 0 0 "timeOutCnt == `TWO_FIFTY_MS" +C 255 254 0 TEXT "Conditions" | 114470,200483 1 0 0 "delCnt1 == `MAX_8_BIT" +W 254 225 1 243 232 BEZIER "Transitions" | 151179,193271 142375,193953 126550,195706 120373,194853\ + 114197,194000 109072,189975 105523,187587 +W 253 225 0 241 243 BEZIER "Transitions" | 101358,228597 101904,225390 102458,220616 103686,217545\ + 104915,214475 108737,208604 114128,207171 119520,205738\ + 137266,205875 142862,205499 148458,205124 153100,203486\ + 154430,202496 155761,201507 156185,199858 156526,198698 +A 252 241 4 TEXT "Actions" | 116837,251309 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\nrxDataRdyClr <= 1'b1;\ndelCnt1 <= 8'h00;" +I 251 225 0 Builtin Exit | 130441,106568 +C 247 239 0 TEXT "Conditions" | 32326,147044 1 0 0 "locRespByte == 8'h00 && timeOutCnt != `TWO_FIFTY_MS" +W 245 225 3 237 251 BEZIER "Transitions" | 118568,142338 109376,129519 116628,112302 127863,106701 +L 244 243 0 TEXT "State Labels" | 157604,192293 1 0 0 "DEL1\n/42/" +S 243 225 208896 ELLIPSE "States" | 157604,192293 6500 6500 +L 242 241 0 TEXT "State Labels" | 101325,235047 1 0 0 "SEND_CMD1\n/43/" +S 241 225 212992 ELLIPSE "States" | 101325,235047 6500 6500 +I 240 225 0 Builtin Entry | 58349,255719 +I 512 0 2 Builtin OutPort | 147984,233494 "" "" +L 513 512 0 TEXT "Labels" | 153984,233494 1 0 0 "rxDataRdyClr" +L 514 515 0 TEXT "Labels" | 77500,229855 1 0 0 "respTout" +I 515 0 2 Builtin InPort | 71500,229855 "" "" +A 516 82 4 TEXT "Actions" | 160072,222273 1 0 0 "readWriteSDBlockRdy <= 1'b0;\nspiCS_n <= 1'b1;\nreadError <= 1'b0;\nwriteError <= 1'b0;\ntxDataOut <= 8'h00;\ntxDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;\ncmdByte <= 8'h00;\ndataByte1 <= 8'h00;\ndataByte2 <= 8'h00;\ndataByte3 <= 8'h00;\ndataByte4 <= 8'h00;\ncheckSumByte <= 8'h00;\nsendCmdReq <= 1'b0;\nloopCnt <= 8'h00;\ndelCnt1 <= 8'h00;\ndelCnt2 <= 8'h00;\nreadError <= `READ_NO_ERROR;\nwriteError <= `WRITE_NO_ERROR;\ntxFifoRen <= 1'b0;\nrxFifoWen <= 1'b0;\nrxFifoData <= 8'h00;\ntimeOutCnt <= 12'h000;\nlocRespByte <= 8'h00;" +L 517 518 0 TEXT "Labels" | 120142,254523 1 0 0 "readError[1:0]" +I 518 0 130 Builtin OutPort | 114142,254523 "" "" +L 519 520 0 TEXT "Labels" | 119971,249897 1 0 0 "writeError[1:0]" +I 520 0 130 Builtin OutPort | 113971,249897 "" "" +L 543 544 0 TEXT "Labels" | 164114,261928 1 0 0 "delCnt1[7:0]" +C 542 541 0 TEXT "Conditions" | 31702,154694 1 0 0 "delCnt2 == 8'hff" +W 541 338 0 537 365 BEZIER "Transitions" | 45749,147689 44744,152468 35773,163628 34769,167402\ + 33765,171176 35012,179071 36950,181044 38889,183018\ + 44071,182291 47325,182291 +W 539 338 2 365 537 BEZIER "Transitions" | 51640,173745 51294,168275 56598,148666 56246,142125 +A 538 537 4 TEXT "Actions" | 36466,135651 1 0 0 "delCnt2 <= delCnt2 + 1'b1;" +S 537 338 225280 ELLIPSE "States" | 49762,142576 6500 6500 +L 536 537 0 TEXT "State Labels" | 49762,142576 1 0 0 "DEL3\n/46/" +C 535 534 0 TEXT "Conditions" | 154260,170964 1 0 0 "delCnt2 == 8'hff" +W 534 225 0 530 243 BEZIER "Transitions" | 179888,172413 174851,172206 165921,171447 162609,173482\ + 159297,175518 158039,181622 156452,185900 +A 533 530 4 TEXT "Actions" | 166680,162960 1 0 0 "delCnt2 <= delCnt2 + 1'b1;" +W 531 225 2 243 530 BEZIER "Transitions" | 163308,189179 168294,185855 176215,180648 181201,177324 +S 530 225 217088 ELLIPSE "States" | 186323,173323 6500 6500 +L 529 530 0 TEXT "State Labels" | 186323,173323 1 0 0 "DEL2\n/44/" +I 528 0 130 Builtin OutPort | 184950,242120 "" "" +A 270 268 4 TEXT "Actions" | 109230,265230 1 0 0 "timeOutCnt <= 12'h000;" +W 269 225 0 268 241 BEZIER "Transitions" | 96982,253102 97927,249120 98637,245290 99582,241308 +S 268 225 221184 ELLIPSE "States" | 96270,259560 6500 6500 +L 267 268 0 TEXT "State Labels" | 96270,259560 1 0 0 "INIT_LOOP\n/45/" +I 264 0 130 Builtin Signal | 161063,266638 "" "" +L 263 264 0 TEXT "Labels" | 164063,266638 1 0 0 "loopCnt[8:0]" +A 259 243 4 TEXT "Actions" | 166374,212237 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;\ndelCnt1 <= delCnt1 + 1'b1;\ndelCnt2 <= 8'h00;" +END diff --git a/usrp2/fpga/opencores/sd_interface/RTL/readWriteSDBlock.v b/usrp2/fpga/opencores/sd_interface/RTL/readWriteSDBlock.v new file mode 100644 index 00000000..92ae0aa3 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/readWriteSDBlock.v @@ -0,0 +1,730 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// readWriteSDBlock.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module readWriteSDBlock (blockAddr, checkSumByte, clk, cmdByte, dataByte1, dataByte2, dataByte3, dataByte4, readError, readWriteSDBlockRdy, readWriteSDBlockReq, respByte, respTout, rst, rxDataIn, rxDataRdy, rxDataRdyClr, rxFifoData, rxFifoWen, sendCmdRdy, sendCmdReq, spiCS_n, txDataEmpty, txDataFull, txDataOut, txDataWen, txFifoData, txFifoRen, writeError); +input [31:0]blockAddr; +input clk; +input [1:0]readWriteSDBlockReq; +input [7:0]respByte; +input respTout; +input rst; +input [7:0]rxDataIn; +input rxDataRdy; +input sendCmdRdy; +input txDataEmpty; +input txDataFull; +input [7:0]txFifoData; +output [7:0]checkSumByte; +output [7:0]cmdByte; +output [7:0]dataByte1; +output [7:0]dataByte2; +output [7:0]dataByte3; +output [7:0]dataByte4; +output [1:0]readError; +output readWriteSDBlockRdy; +output rxDataRdyClr; +output [7:0]rxFifoData; +output rxFifoWen; +output sendCmdReq; +output spiCS_n; +output [7:0]txDataOut; +output txDataWen; +output txFifoRen; +output [1:0]writeError; + +wire [31:0]blockAddr; +reg [7:0]checkSumByte, next_checkSumByte; +wire clk; +reg [7:0]cmdByte, next_cmdByte; +reg [7:0]dataByte1, next_dataByte1; +reg [7:0]dataByte2, next_dataByte2; +reg [7:0]dataByte3, next_dataByte3; +reg [7:0]dataByte4, next_dataByte4; +reg [1:0]readError, next_readError; +reg readWriteSDBlockRdy, next_readWriteSDBlockRdy; +wire [1:0]readWriteSDBlockReq; +wire [7:0]respByte; +wire respTout; +wire rst; +wire [7:0]rxDataIn; +wire rxDataRdy; +reg rxDataRdyClr, next_rxDataRdyClr; +reg [7:0]rxFifoData, next_rxFifoData; +reg rxFifoWen, next_rxFifoWen; +wire sendCmdRdy; +reg sendCmdReq, next_sendCmdReq; +reg spiCS_n, next_spiCS_n; +wire txDataEmpty; +wire txDataFull; +reg [7:0]txDataOut, next_txDataOut; +reg txDataWen, next_txDataWen; +wire [7:0]txFifoData; +reg txFifoRen, next_txFifoRen; +reg [1:0]writeError, next_writeError; + +// diagram signals declarations +reg [7:0]delCnt1, next_delCnt1; +reg [7:0]delCnt2, next_delCnt2; +reg [7:0]locRespByte, next_locRespByte; +reg [8:0]loopCnt, next_loopCnt; +reg [11:0]timeOutCnt, next_timeOutCnt; + +// BINARY ENCODED state machine: rwBlkSt +// State codes definitions: +`define ST_RW_SD 6'b000000 +`define WR_CMD_SEND_CMD 6'b000001 +`define WR_CMD_WT_FIN 6'b000010 +`define WR_CMD_DEL 6'b000011 +`define WT_REQ 6'b000100 +`define WR_TOKEN_FF1_FIN 6'b000101 +`define WR_TOKEN_FF1_ST 6'b000110 +`define WR_TOKEN_FF2_FIN 6'b000111 +`define WR_TOKEN_FF2_ST 6'b001000 +`define WR_TOKEN_FE_FIN 6'b001001 +`define WR_TOKEN_FE_ST 6'b001010 +`define WR_DATA_D_FIN 6'b001011 +`define WR_DATA_D_ST 6'b001100 +`define WR_DATA_RD_FIFO1 6'b001101 +`define WR_DATA_RD_FIFO2 6'b001110 +`define WR_DATA_LOOP_INIT 6'b001111 +`define WR_DATA_CS_ST1 6'b010000 +`define WR_DATA_CS_FIN1 6'b010001 +`define WR_DATA_CS_FIN2 6'b010010 +`define WR_DATA_CS_ST2 6'b010011 +`define WR_DATA_CHK_RESP 6'b010100 +`define WR_DATA_REQ_RESP_ST 6'b010101 +`define WR_DATA_REQ_RESP_FIN 6'b010110 +`define RD_CMD_SEND_CMD 6'b010111 +`define RD_CMD_WT_FIN 6'b011000 +`define RD_CMD_DEL 6'b011001 +`define RD_TOKEN_CHK_LOOP 6'b011010 +`define RD_TOKEN_WT_FIN 6'b011011 +`define RD_TOKEN_SEND_CMD 6'b011100 +`define RD_TOKEN_DEL2 6'b011101 +`define RD_TOKEN_INIT_LOOP 6'b011110 +`define RD_TOKEN_DEL1 6'b011111 +`define RD_DATA_ST_LOOP 6'b100000 +`define RD_DATA_WT_DATA 6'b100001 +`define RD_DATA_CHK_LOOP 6'b100010 +`define RD_DATA_CLR_RX 6'b100011 +`define RD_DATA_CS_FIN2 6'b100100 +`define RD_DATA_CS_FIN1 6'b100101 +`define RD_DATA_CS_ST1 6'b100110 +`define RD_DATA_CS_ST2 6'b100111 +`define WR_BUSY_CHK_FIN 6'b101000 +`define WR_BUSY_WT_FIN1 6'b101001 +`define WR_BUSY_DEL1 6'b101010 +`define WR_BUSY_SEND_CMD1 6'b101011 +`define WR_BUSY_DEL2 6'b101100 +`define WR_BUSY_INIT_LOOP 6'b101101 +`define RD_TOKEN_DEL3 6'b101110 +`define WR_DATA_DEL 6'b101111 + +reg [5:0]CurrState_rwBlkSt, NextState_rwBlkSt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: rwBlkSt + +// NextState logic (combinatorial) +always @ (blockAddr or sendCmdRdy or respTout or respByte or readWriteSDBlockReq or txDataFull or loopCnt or txFifoData or txDataEmpty or timeOutCnt or locRespByte or rxDataRdy or rxDataIn or delCnt1 or delCnt2 or readWriteSDBlockRdy or spiCS_n or readError or writeError or txDataOut or txDataWen or rxDataRdyClr or cmdByte or dataByte1 or dataByte2 or dataByte3 or dataByte4 or checkSumByte or sendCmdReq or txFifoRen or rxFifoWen or rxFifoData or CurrState_rwBlkSt) +begin + NextState_rwBlkSt <= CurrState_rwBlkSt; + // Set default values for outputs and signals + next_readWriteSDBlockRdy <= readWriteSDBlockRdy; + next_spiCS_n <= spiCS_n; + next_readError <= readError; + next_writeError <= writeError; + next_txDataOut <= txDataOut; + next_txDataWen <= txDataWen; + next_rxDataRdyClr <= rxDataRdyClr; + next_cmdByte <= cmdByte; + next_dataByte1 <= dataByte1; + next_dataByte2 <= dataByte2; + next_dataByte3 <= dataByte3; + next_dataByte4 <= dataByte4; + next_checkSumByte <= checkSumByte; + next_sendCmdReq <= sendCmdReq; + next_loopCnt <= loopCnt; + next_delCnt1 <= delCnt1; + next_delCnt2 <= delCnt2; + next_txFifoRen <= txFifoRen; + next_rxFifoWen <= rxFifoWen; + next_rxFifoData <= rxFifoData; + next_timeOutCnt <= timeOutCnt; + next_locRespByte <= locRespByte; + case (CurrState_rwBlkSt) // synopsys parallel_case full_case + `ST_RW_SD: + begin + next_readWriteSDBlockRdy <= 1'b0; + next_spiCS_n <= 1'b1; + next_readError <= 1'b0; + next_writeError <= 1'b0; + next_txDataOut <= 8'h00; + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + next_cmdByte <= 8'h00; + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h00; + next_sendCmdReq <= 1'b0; + next_loopCnt <= 8'h00; + next_delCnt1 <= 8'h00; + next_delCnt2 <= 8'h00; + next_readError <= `READ_NO_ERROR; + next_writeError <= `WRITE_NO_ERROR; + next_txFifoRen <= 1'b0; + next_rxFifoWen <= 1'b0; + next_rxFifoData <= 8'h00; + next_timeOutCnt <= 12'h000; + next_locRespByte <= 8'h00; + NextState_rwBlkSt <= `WT_REQ; + end + `WT_REQ: + begin + next_spiCS_n <= 1'b1; + next_readWriteSDBlockRdy <= 1'b1; + next_cmdByte <= 8'h00; + next_dataByte1 <= 8'h00; + next_dataByte2 <= 8'h00; + next_dataByte3 <= 8'h00; + next_dataByte4 <= 8'h00; + next_checkSumByte <= 8'h00; + if (readWriteSDBlockReq == `READ_SD_BLOCK) + begin + NextState_rwBlkSt <= `RD_CMD_SEND_CMD; + next_spiCS_n <= 1'b0; + next_readWriteSDBlockRdy <= 1'b0; + next_readError <= `READ_NO_ERROR; + end + else if (readWriteSDBlockReq == `WRITE_SD_BLOCK) + begin + NextState_rwBlkSt <= `WR_CMD_SEND_CMD; + next_spiCS_n <= 1'b0; + next_readWriteSDBlockRdy <= 1'b0; + next_writeError <= `WRITE_NO_ERROR; + end + end + `WR_CMD_SEND_CMD: + begin + next_cmdByte <= 8'h58; + //CMD24 Block Write + next_dataByte1 <= blockAddr[31:24]; + next_dataByte2 <= blockAddr[23:16]; + next_dataByte3 <= blockAddr[15:8]; + next_dataByte4 <= blockAddr[7:0]; + next_checkSumByte <= 8'hff; + next_sendCmdReq <= 1'b1; + NextState_rwBlkSt <= `WR_CMD_DEL; + end + `WR_CMD_WT_FIN: + begin + if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 || respByte != 8'h00)) + begin + NextState_rwBlkSt <= `WT_REQ; + next_writeError <= `WRITE_CMD_ERROR; + end + else if (sendCmdRdy == 1'b1) + begin + NextState_rwBlkSt <= `WR_TOKEN_FF1_ST; + end + end + `WR_CMD_DEL: + begin + next_sendCmdReq <= 1'b0; + NextState_rwBlkSt <= `WR_CMD_WT_FIN; + end + `WR_TOKEN_FF1_FIN: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `WR_TOKEN_FF2_ST; + end + `WR_TOKEN_FF1_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_TOKEN_FF1_FIN; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_TOKEN_FF2_FIN: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `WR_TOKEN_FE_ST; + end + `WR_TOKEN_FF2_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_TOKEN_FF2_FIN; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_TOKEN_FE_FIN: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `WR_DATA_LOOP_INIT; + end + `WR_TOKEN_FE_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_TOKEN_FE_FIN; + next_txDataOut <= 8'hfe; + next_txDataWen <= 1'b1; + end + end + `WR_BUSY_CHK_FIN: + begin + if (locRespByte == 8'h00 && timeOutCnt != `TWO_FIFTY_MS) + begin + NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1; + next_timeOutCnt <= timeOutCnt + 1'b1; + end + else if (timeOutCnt == `TWO_FIFTY_MS) + begin + NextState_rwBlkSt <= `WT_REQ; + next_writeError <= `WRITE_BUSY_ERROR; + end + else + begin + NextState_rwBlkSt <= `WT_REQ; + end + end + `WR_BUSY_WT_FIN1: + begin + if (rxDataRdy == 1'b1) + begin + NextState_rwBlkSt <= `WR_BUSY_CHK_FIN; + next_locRespByte <= rxDataIn; + end + end + `WR_BUSY_DEL1: + begin + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + next_delCnt1 <= delCnt1 + 1'b1; + next_delCnt2 <= 8'h00; + if (delCnt1 == `MAX_8_BIT) + begin + NextState_rwBlkSt <= `WR_BUSY_WT_FIN1; + end + else + begin + NextState_rwBlkSt <= `WR_BUSY_DEL2; + end + end + `WR_BUSY_SEND_CMD1: + begin + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_rxDataRdyClr <= 1'b1; + next_delCnt1 <= 8'h00; + NextState_rwBlkSt <= `WR_BUSY_DEL1; + end + `WR_BUSY_DEL2: + begin + next_delCnt2 <= delCnt2 + 1'b1; + if (delCnt2 == 8'hff) + begin + NextState_rwBlkSt <= `WR_BUSY_DEL1; + end + end + `WR_BUSY_INIT_LOOP: + begin + next_timeOutCnt <= 12'h000; + NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1; + end + `RD_CMD_SEND_CMD: + begin + next_cmdByte <= 8'h51; + //CMD17 Block Read + next_dataByte1 <= blockAddr[31:24]; + next_dataByte2 <= blockAddr[23:16]; + next_dataByte3 <= blockAddr[15:8]; + next_dataByte4 <= blockAddr[7:0]; + next_checkSumByte <= 8'hff; + next_sendCmdReq <= 1'b1; + NextState_rwBlkSt <= `RD_CMD_DEL; + end + `RD_CMD_WT_FIN: + begin + if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 || respByte != 8'h00)) + begin + NextState_rwBlkSt <= `WT_REQ; + next_readError <= `READ_CMD_ERROR; + end + else if (sendCmdRdy == 1'b1) + begin + NextState_rwBlkSt <= `RD_TOKEN_INIT_LOOP; + end + end + `RD_CMD_DEL: + begin + next_sendCmdReq <= 1'b0; + NextState_rwBlkSt <= `RD_CMD_WT_FIN; + end + `RD_TOKEN_CHK_LOOP: + begin + if (locRespByte != 8'hfe && timeOutCnt != `ONE_HUNDRED_MS) + begin + NextState_rwBlkSt <= `RD_TOKEN_DEL2; + next_timeOutCnt <= timeOutCnt + 1'b1; + next_delCnt1 <= 8'h00; + end + else if (timeOutCnt == `ONE_HUNDRED_MS) + begin + NextState_rwBlkSt <= `WT_REQ; + next_readError <= `READ_TOKEN_ERROR; + end + else + begin + NextState_rwBlkSt <= `RD_DATA_CLR_RX; + next_rxDataRdyClr <= 1'b1; + end + end + `RD_TOKEN_WT_FIN: + begin + if (rxDataRdy == 1'b1) + begin + NextState_rwBlkSt <= `RD_TOKEN_CHK_LOOP; + next_locRespByte <= rxDataIn; + end + end + `RD_TOKEN_SEND_CMD: + begin + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_rxDataRdyClr <= 1'b1; + NextState_rwBlkSt <= `RD_TOKEN_DEL1; + end + `RD_TOKEN_DEL2: + begin + next_delCnt1 <= delCnt1 + 1'b1; + next_delCnt2 <= 8'h00; + if (delCnt1 == `MAX_8_BIT) + begin + NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD; + end + else + begin + NextState_rwBlkSt <= `RD_TOKEN_DEL3; + end + end + `RD_TOKEN_INIT_LOOP: + begin + next_timeOutCnt <= 12'h000; + NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD; + end + `RD_TOKEN_DEL1: + begin + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + NextState_rwBlkSt <= `RD_TOKEN_WT_FIN; + end + `RD_TOKEN_DEL3: + begin + next_delCnt2 <= delCnt2 + 1'b1; + if (delCnt2 == 8'hff) + begin + NextState_rwBlkSt <= `RD_TOKEN_DEL2; + end + end + `RD_DATA_ST_LOOP: + begin + next_txDataWen <= 1'b1; + next_txDataOut <= 8'hff; + next_loopCnt <= loopCnt + 1'b1; + NextState_rwBlkSt <= `RD_DATA_WT_DATA; + end + `RD_DATA_WT_DATA: + begin + next_txDataWen <= 1'b0; + if (rxDataRdy == 1'b1) + begin + NextState_rwBlkSt <= `RD_DATA_CHK_LOOP; + next_rxFifoWen <= 1'b1; + next_rxDataRdyClr <= 1'b1; + next_rxFifoData <= rxDataIn; + end + end + `RD_DATA_CHK_LOOP: + begin + if (loopCnt == 9'b000000000) + begin + NextState_rwBlkSt <= `RD_DATA_CS_ST1; + next_rxDataRdyClr <= 1'b0; + next_rxFifoWen <= 1'b0; + end + else + begin + NextState_rwBlkSt <= `RD_DATA_ST_LOOP; + next_rxDataRdyClr <= 1'b0; + next_rxFifoWen <= 1'b0; + end + end + `RD_DATA_CLR_RX: + begin + NextState_rwBlkSt <= `RD_DATA_ST_LOOP; + next_rxDataRdyClr <= 1'b0; + next_loopCnt <= 9'b000000000; + end + `RD_DATA_CS_FIN2: + begin + next_txDataWen <= 1'b0; + if (txDataEmpty == 1'b1) + begin + NextState_rwBlkSt <= `WT_REQ; + end + end + `RD_DATA_CS_FIN1: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `RD_DATA_CS_ST2; + end + `RD_DATA_CS_ST1: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `RD_DATA_CS_FIN1; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `RD_DATA_CS_ST2: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `RD_DATA_CS_FIN2; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_DATA_D_FIN: + begin + next_txDataWen <= 1'b0; + if (loopCnt == 9'b000000000) + begin + NextState_rwBlkSt <= `WR_DATA_CS_ST1; + end + else + begin + NextState_rwBlkSt <= `WR_DATA_RD_FIFO1; + end + end + `WR_DATA_D_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_DATA_D_FIN; + next_txDataOut <= txFifoData; + next_txDataWen <= 1'b1; + end + end + `WR_DATA_RD_FIFO1: + begin + next_txFifoRen <= 1'b1; + next_loopCnt <= loopCnt + 1'b1; + NextState_rwBlkSt <= `WR_DATA_RD_FIFO2; + end + `WR_DATA_RD_FIFO2: + begin + next_txFifoRen <= 1'b0; + NextState_rwBlkSt <= `WR_DATA_D_ST; + end + `WR_DATA_LOOP_INIT: + begin + next_loopCnt <= 9'b000000000; + NextState_rwBlkSt <= `WR_DATA_RD_FIFO1; + end + `WR_DATA_CS_ST1: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_DATA_CS_FIN1; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_DATA_CS_FIN1: + begin + next_txDataWen <= 1'b0; + NextState_rwBlkSt <= `WR_DATA_CS_ST2; + end + `WR_DATA_CS_FIN2: + begin + next_txDataWen <= 1'b0; + next_timeOutCnt <= 12'h000; + if (txDataEmpty == 1'b1) + begin + NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST; + end + end + `WR_DATA_CS_ST2: + begin + if (txDataFull == 1'b0) + begin + NextState_rwBlkSt <= `WR_DATA_CS_FIN2; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `WR_DATA_CHK_RESP: + begin + if (timeOutCnt == `WR_RESP_TOUT) + begin + NextState_rwBlkSt <= `WT_REQ; + next_writeError <= `WRITE_DATA_ERROR; + end + else if (locRespByte[4:0] == 5'h5) + begin + NextState_rwBlkSt <= `WR_BUSY_INIT_LOOP; + end + else + begin + NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST; + end + end + `WR_DATA_REQ_RESP_ST: + begin + NextState_rwBlkSt <= `WR_DATA_DEL; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_timeOutCnt <= timeOutCnt + 1'b1; + next_rxDataRdyClr <= 1'b1; + end + `WR_DATA_REQ_RESP_FIN: + begin + if (rxDataRdy == 1'b1) + begin + NextState_rwBlkSt <= `WR_DATA_CHK_RESP; + next_locRespByte <= rxDataIn; + end + end + `WR_DATA_DEL: + begin + NextState_rwBlkSt <= `WR_DATA_REQ_RESP_FIN; + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_rwBlkSt <= `ST_RW_SD; + else + CurrState_rwBlkSt <= NextState_rwBlkSt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + readWriteSDBlockRdy <= 1'b0; + spiCS_n <= 1'b1; + readError <= 1'b0; + writeError <= 1'b0; + txDataOut <= 8'h00; + txDataWen <= 1'b0; + rxDataRdyClr <= 1'b0; + cmdByte <= 8'h00; + dataByte1 <= 8'h00; + dataByte2 <= 8'h00; + dataByte3 <= 8'h00; + dataByte4 <= 8'h00; + checkSumByte <= 8'h00; + sendCmdReq <= 1'b0; + txFifoRen <= 1'b0; + rxFifoWen <= 1'b0; + rxFifoData <= 8'h00; + loopCnt <= 8'h00; + delCnt1 <= 8'h00; + delCnt2 <= 8'h00; + timeOutCnt <= 12'h000; + locRespByte <= 8'h00; + end + else + begin + readWriteSDBlockRdy <= next_readWriteSDBlockRdy; + spiCS_n <= next_spiCS_n; + readError <= next_readError; + writeError <= next_writeError; + txDataOut <= next_txDataOut; + txDataWen <= next_txDataWen; + rxDataRdyClr <= next_rxDataRdyClr; + cmdByte <= next_cmdByte; + dataByte1 <= next_dataByte1; + dataByte2 <= next_dataByte2; + dataByte3 <= next_dataByte3; + dataByte4 <= next_dataByte4; + checkSumByte <= next_checkSumByte; + sendCmdReq <= next_sendCmdReq; + txFifoRen <= next_txFifoRen; + rxFifoWen <= next_rxFifoWen; + rxFifoData <= next_rxFifoData; + loopCnt <= next_loopCnt; + delCnt1 <= next_delCnt1; + delCnt2 <= next_delCnt2; + timeOutCnt <= next_timeOutCnt; + locRespByte <= next_locRespByte; + end +end + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/sd_interface/RTL/readWriteSPIWireData.asf b/usrp2/fpga/opencores/sd_interface/RTL/readWriteSPIWireData.asf new file mode 100644 index 00000000..f6f39e49 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/readWriteSPIWireData.asf @@ -0,0 +1,121 @@ +VERSION=1.15 +HEADER +FILE="readWriteSPIWireData.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="readWriteSPIWireData" +FRAMES=ON +FREEOID=95 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// readWriteSPIWireData.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// parameterized dual clock domain fifo. \n//// fifo depth is restricted to 2^ADDR_WIDTH\n//// No protection against over runs and under runs.\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 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fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module readWriteSPIWireData (clk, clkDelay, rst, rxDataOut, rxDataRdySet, spiClkOut, spiDataIn, spiDataOut, txDataEmpty, txDataFull, txDataFullClr, txDataIn); +input clk; +input [7:0]clkDelay; +input rst; +input spiDataIn; +input txDataFull; +input [7:0]txDataIn; +output [7:0]rxDataOut; +output rxDataRdySet; +output spiClkOut; +output spiDataOut; +output txDataEmpty; +output txDataFullClr; + +wire clk; +wire [7:0]clkDelay; +wire rst; +reg [7:0]rxDataOut, next_rxDataOut; +reg rxDataRdySet, next_rxDataRdySet; +reg spiClkOut, next_spiClkOut; +wire spiDataIn; +reg spiDataOut, next_spiDataOut; +reg txDataEmpty, next_txDataEmpty; +wire txDataFull; +reg txDataFullClr, next_txDataFullClr; +wire [7:0]txDataIn; + +// diagram signals declarations +reg [3:0]bitCnt, next_bitCnt; +reg [7:0]clkDelayCnt, next_clkDelayCnt; +reg [7:0]rxDataShiftReg, next_rxDataShiftReg; +reg [7:0]txDataShiftReg, next_txDataShiftReg; + +// BINARY ENCODED state machine: rwSPISt +// State codes definitions: +`define WT_TX_DATA 2'b00 +`define CLK_HI 2'b01 +`define CLK_LO 2'b10 +`define ST_RW_WIRE 2'b11 + +reg [1:0]CurrState_rwSPISt, NextState_rwSPISt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: rwSPISt + +// NextState logic (combinatorial) +always @ (txDataFull or txDataIn or clkDelayCnt or clkDelay or txDataShiftReg or bitCnt or rxDataShiftReg or spiDataIn or rxDataRdySet or txDataEmpty or txDataFullClr or spiClkOut or spiDataOut or rxDataOut or CurrState_rwSPISt) +begin + NextState_rwSPISt <= CurrState_rwSPISt; + // Set default values for outputs and signals + next_rxDataRdySet <= rxDataRdySet; + next_txDataEmpty <= txDataEmpty; + next_txDataShiftReg <= txDataShiftReg; + next_rxDataShiftReg <= rxDataShiftReg; + next_bitCnt <= bitCnt; + next_clkDelayCnt <= clkDelayCnt; + next_txDataFullClr <= txDataFullClr; + next_spiClkOut <= spiClkOut; + next_spiDataOut <= spiDataOut; + next_rxDataOut <= rxDataOut; + case (CurrState_rwSPISt) // synopsys parallel_case full_case + `WT_TX_DATA: + begin + next_rxDataRdySet <= 1'b0; + next_txDataEmpty <= 1'b1; + if (txDataFull == 1'b1) + begin + NextState_rwSPISt <= `CLK_HI; + next_txDataShiftReg <= txDataIn; + next_rxDataShiftReg <= 8'h00; + next_bitCnt <= 4'h0; + next_clkDelayCnt <= 8'h00; + next_txDataFullClr <= 1'b1; + next_txDataEmpty <= 1'b0; + end + end + `CLK_HI: + begin + next_clkDelayCnt <= clkDelayCnt + 1'b1; + next_txDataFullClr <= 1'b0; + next_rxDataRdySet <= 1'b0; + if (clkDelayCnt == clkDelay) + begin + NextState_rwSPISt <= `CLK_LO; + next_spiClkOut <= 1'b0; + next_spiDataOut <= txDataShiftReg[7]; + next_txDataShiftReg <= {txDataShiftReg[6:0], 1'b0}; + next_clkDelayCnt <= 8'h00; + end + end + `CLK_LO: + begin + next_clkDelayCnt <= clkDelayCnt + 1'b1; + if ((bitCnt == 4'h8) && (txDataFull == 1'b1)) + begin + NextState_rwSPISt <= `CLK_HI; + next_rxDataRdySet <= 1'b1; + next_rxDataOut <= rxDataShiftReg; + next_txDataShiftReg <= txDataIn; + next_bitCnt <= 3'b000; + next_clkDelayCnt <= 8'h00; + next_txDataFullClr <= 1'b1; + end + else if (bitCnt == 4'h8) + begin + NextState_rwSPISt <= `WT_TX_DATA; + next_rxDataRdySet <= 1'b1; + next_rxDataOut <= rxDataShiftReg; + end + else if (clkDelayCnt == clkDelay) + begin + NextState_rwSPISt <= `CLK_HI; + next_spiClkOut <= 1'b1; + next_bitCnt <= bitCnt + 1'b1; + next_clkDelayCnt <= 8'h00; + next_rxDataShiftReg <= {rxDataShiftReg[6:0], spiDataIn}; + end + end + `ST_RW_WIRE: + begin + next_bitCnt <= 4'h0; + next_clkDelayCnt <= 8'h00; + next_txDataFullClr <= 1'b0; + next_rxDataRdySet <= 1'b0; + next_txDataShiftReg <= 8'h00; + next_rxDataShiftReg <= 8'h00; + next_rxDataOut <= 8'h00; + next_spiDataOut <= 1'b0; + next_spiClkOut <= 1'b0; + next_txDataEmpty <= 1'b0; + NextState_rwSPISt <= `WT_TX_DATA; + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_rwSPISt <= `ST_RW_WIRE; + else + CurrState_rwSPISt <= NextState_rwSPISt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + rxDataRdySet <= 1'b0; + txDataEmpty <= 1'b0; + txDataFullClr <= 1'b0; + spiClkOut <= 1'b0; + spiDataOut <= 1'b0; + rxDataOut <= 8'h00; + txDataShiftReg <= 8'h00; + rxDataShiftReg <= 8'h00; + bitCnt <= 4'h0; + clkDelayCnt <= 8'h00; + end + else + begin + rxDataRdySet <= next_rxDataRdySet; + txDataEmpty <= next_txDataEmpty; + txDataFullClr <= next_txDataFullClr; + spiClkOut <= next_spiClkOut; + spiDataOut <= next_spiDataOut; + rxDataOut <= next_rxDataOut; + txDataShiftReg <= next_txDataShiftReg; + rxDataShiftReg <= next_rxDataShiftReg; + bitCnt <= next_bitCnt; + clkDelayCnt <= next_clkDelayCnt; + end +end + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/sd_interface/RTL/sendCmd.asf b/usrp2/fpga/opencores/sd_interface/RTL/sendCmd.asf new file mode 100644 index 00000000..4d05954e --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/sendCmd.asf @@ -0,0 +1,231 @@ +VERSION=1.15 +HEADER +FILE="sendCmd.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="sendCmd" +FRAMES=ON +FREEOID=426 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// sendCmd.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// parameterized dual clock domain fifo. \n//// fifo depth is restricted to 2^ADDR_WIDTH\n//// No protection against over runs and under runs.\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 4 +B F "Current State" 255,255,0 0 0 1 255,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Comments" 157,157,157 0 0 1 255,255,255 0 3527 1480 0000 1 "Arial" 0 +B L "Info" 0,255,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +END +INSTHEADER 1 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 5000,5000 10000,10000 +END +INSTHEADER 168 +PAGE 25400,25400 215900,279400 +UPPERLEFT 0,0 +GRID=OFF +GRIDSIZE 0,0 10000,10000 +END +OBJECTS +S 287 169 36864 ELLIPSE "States" | 58145,42664 6500 6500 +C 286 284 0 TEXT "Conditions" | 58455,63310 1 0 0 "txDataFull == 1'b0" +A 285 284 16 TEXT "Actions" | 58389,58640 1 0 0 "txDataOut <= dataByte3;\ntxDataWen <= 1'b1;" +W 284 169 0 289 287 BEZIER "Transitions" | 55994,62919 56515,59615 56972,52449 57396,49118 +G 1 0 0 TEXT 0,0,0 0 0 0 255,255,255 0 3527 1480 0000 1 "Arial" 0 | 110650,276400 1 0 0 "Module: sendCmd" +A 5 0 1 TEXT "Actions" | 30400,270465 1 0 0 "-- diagram ACTION\nalways @(sendCmdReq1 or sendCmdReq2 ) begin\n sendCmdReq <= sendCmdReq1 | sendCmdReq2;\nend\n\nalways @(posedge clk) begin\n cmdByte <= cmdByte_1 | cmdByte_2;\n dataByte1 <= dataByte1_1 | dataByte1_2;\n dataByte2 <= dataByte2_1 | dataByte2_2;\n dataByte3 <= dataByte3_1 | dataByte3_2;\n dataByte4 <= dataByte4_1 | dataByte4_2;\n checkSumByte <= checkSumByte_1 | checkSumByte_2;\nend" +F 6 0 512 72 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,208764 +L 7 6 0 TEXT "Labels" | 33841,199139 1 0 0 "sndCmdSt" +L 298 297 0 TEXT "State Labels" | 119183,117704 1 0 0 "D_BYTE4_ST\n/12/" +S 297 169 49152 ELLIPSE "States" | 119183,117704 6500 6500 +L 296 295 0 TEXT "State Labels" | 121962,90985 1 0 0 "D_BYTE4_FIN\n/11/" +S 295 169 45056 ELLIPSE "States" | 121962,90985 6500 6500 +C 294 292 0 TEXT "Conditions" | 122272,111631 1 0 0 "txDataFull == 1'b0" +A 293 292 16 TEXT "Actions" | 122206,106961 1 0 0 "txDataOut <= dataByte4;\ntxDataWen <= 1'b1;" +W 292 169 0 297 295 BEZIER "Transitions" | 119811,111240 120332,107936 120789,100770 121213,97439 +L 290 289 0 TEXT "State Labels" | 55366,69383 1 0 0 "D_BYTE3_ST\n/10/" +S 289 169 40960 ELLIPSE "States" | 55366,69383 6500 6500 +L 288 287 0 TEXT "State Labels" | 58145,42664 1 0 0 "D_BYTE3_FIN\n/9/" +W 319 169 0 205 247 BEZIER "Transitions" | 63983,140499 60844,135517 56583,126997 53444,122015 +A 318 295 4 TEXT "Actions" | 139150,86599 1 0 0 "txDataWen <= 1'b0;" +A 317 287 4 TEXT "Actions" | 76633,44284 1 0 0 "txDataWen <= 1'b0;" +A 316 225 4 TEXT "Actions" | 71992,91513 1 0 0 "txDataWen <= 1'b0;" +A 315 311 4 TEXT "Actions" | 134912,45978 1 0 0 "txDataWen <= 1'b0;\ntimeOutCnt <= 10'h000;" +L 314 313 0 TEXT "State Labels" | 122732,70475 1 0 0 "CS_ST\n/14/" +S 313 169 57344 ELLIPSE "States" | 122732,70475 6500 6500 +L 312 311 0 TEXT "State Labels" | 125511,43756 1 0 0 "CS_FIN\n/13/" +S 311 169 53248 ELLIPSE "States" | 125511,43756 6500 6500 +C 310 308 0 TEXT "Conditions" | 125821,64402 1 0 0 "txDataFull == 1'b0" +A 309 308 16 TEXT "Actions" | 125755,59732 1 0 0 "txDataOut <= checkSumByte;\ntxDataWen <= 1'b1;" +W 308 169 0 313 311 BEZIER "Transitions" | 123360,64011 123881,60707 124338,53541 124762,50210 +W 335 169 0 332 182 BEZIER "Transitions" | 45364,251903 47642,252271 81651,254936 85013,246121 +W 334 169 0 185 332 BEZIER "Transitions" | 41073,269282 40336,265731 39290,259500 38553,255949 +S 332 169 61440 ELLIPSE "States" | 39325,249500 6500 6500 +L 331 332 0 TEXT "State Labels" | 39325,251108 1 0 0 "SEND_FF_ST\n/15/" +I 329 0 2 Builtin Signal | 178213,215725 "" "" +L 328 329 0 TEXT "Labels" | 181213,215725 1 0 0 "sendCmdReq" +L 327 326 0 TEXT "Labels" | 157273,263636 1 0 0 "sendCmdReq2" +I 326 0 2 Builtin InPort | 151273,263636 "" "" +I 325 0 2 Builtin InPort | 151961,268514 "" "" +L 324 325 0 TEXT "Labels" | 157961,268514 1 0 0 "sendCmdReq1" +W 322 169 0 295 313 BEZIER "Transitions" | 122244,84497 122585,81836 122598,79603 122939,76942 +W 321 169 0 287 297 BEZIER "Transitions" | 63804,39468 72608,38035 85574,34251 91921,34114\ + 98268,33978 106049,36299 107653,41212 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"Labels" | 189826,245330 1 0 0 "rxDataRdyClr" +I 121 0 2 Builtin OutPort | 183826,245330 "" "" +L 118 117 0 TEXT "Labels" | 156520,254066 1 0 0 "txDataOut[7:0]" +I 117 0 130 Builtin OutPort | 150520,254066 "" "" +L 116 115 0 TEXT "Labels" | 191737,253793 1 0 0 "rxDataIn[7:0]" +I 115 0 130 Builtin InPort | 185737,253793 "" "" +L 112 111 0 TEXT "Labels" | 156520,249425 1 0 0 "txDataWen" +L 392 393 0 TEXT "Labels" | 155040,236450 1 0 0 "cmdByte_1[7:0]" +I 393 0 130 Builtin InPort | 149040,236450 "" "" +L 394 395 0 TEXT "Labels" | 155040,232130 1 0 0 "cmdByte_2[7:0]" +I 395 0 130 Builtin InPort | 149040,232130 "" "" +L 396 397 0 TEXT "Labels" | 115350,214850 1 0 0 "respTout" +I 397 0 2 Builtin OutPort | 109350,214850 "" "" +L 398 399 0 TEXT "Labels" | 156083,221028 1 0 0 "cmdByte[7:0]" +I 399 0 130 Builtin Signal | 153083,221028 "" "" +A 137 100 4 TEXT "Actions" | 132312,205914 1 0 0 "sendCmdRdy <= 1'b0;\ntxDataWen <= 1'b0;\ntxDataOut <= 8'h00;\nrxDataRdyClr <= 1'b0;\nrespByte <= 8'h00;\nrespTout <= 1'b0;\ntimeOutCnt <= 10'h000;" +A 138 102 4 TEXT "Actions" | 124218,176348 1 0 0 "sendCmdRdy <= 1'b1;" +A 139 106 16 TEXT "Actions" | 108893,161005 1 0 0 "sendCmdRdy <= 1'b0;\nrespTout <= 1'b0;" +L 400 401 0 TEXT "Labels" | 156156,216020 1 0 0 "timeOutCnt[9:0]" +I 401 0 130 Builtin Signal | 153156,216020 "" "" +L 407 408 0 TEXT "Labels" | 158650,240900 1 0 0 "txDataEmpty" +I 408 0 2 Builtin InPort | 152650,240900 "" "" +A 412 410 16 TEXT "Actions" | 187604,127904 1 0 0 "" +C 411 410 0 TEXT "Conditions" | 176525,34775 1 0 0 "txDataEmpty == 1'b1" +W 410 169 0 311 234 BEZIER "Transitions" | 129680,38771 133617,37459 138963,34462 145962,34024\ + 152962,33587 173088,34463 180556,35962 188025,37462\ + 197775,42588 199431,55306 201088,68025 197962,113775\ + 186681,128962 175400,144150 133400,159150 122119,165962\ + 110838,172775 107712,185025 107774,191306 107837,197587\ + 111213,210463 112150,219431 113087,228400 113463,251400\ + 114962,258243 116462,265087 122088,269463 125056,270025\ + 128025,270588 133111,267776 136236,266714 +L 420 421 0 TEXT "State Labels" | 197224,232320 1 0 0 "DEL\n/19/" +S 421 169 77824 ELLIPSE "States" | 197224,232320 6500 6500 +W 422 169 0 234 421 BEZIER "Transitions" | 147223,260243 159499,254229 180037,242591 192313,236577 +A 423 422 16 TEXT "Actions" | 153948,265428 1 0 0 "txDataOut <= 8'hff;\ntxDataWen <= 1'b1;\ntimeOutCnt <= timeOutCnt + 1'b1;\nrxDataRdyClr <= 1'b1;" +W 424 169 0 421 237 BEZIER "Transitions" | 190754,232933 178974,233801 160757,232683 148977,233551 +A 425 424 16 TEXT "Actions" | 157420,238644 1 0 0 "txDataWen <= 1'b0;\nrxDataRdyClr <= 1'b0;" +L 167 168 0 TEXT "State Labels" | 111928,143426 1 0 0 "CMD" +S 168 6 73732 ELLIPSE 0,0,0 0 0 1 0,255,255 1 | 111928,143426 6500 6500 +H 169 168 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28668,29070 213168,277070 +S 176 169 65536 ELLIPSE "States" | 60614,226551 6500 6500 +A 177 176 4 TEXT "Actions" | 78632,227097 1 0 0 "txDataWen <= 1'b0;" +W 178 169 0 182 176 BEZIER "Transitions" | 85317,242783 68957,244509 60312,236489 60462,233017 +L 181 176 0 TEXT "State Labels" | 60614,226551 1 0 0 "CMD_BYTE_ST\n/16/" +S 182 169 8192 ELLIPSE "States" | 91419,245022 6500 6500 +L 183 182 0 TEXT "State Labels" | 91419,245558 1 0 0 "SEND_FF_FIN\n/2/" +I 184 169 0 Builtin Exit | 133914,177514 +I 185 169 0 Builtin Entry | 41073,271359 +L 193 194 0 TEXT "State Labels" | 61318,198350 1 0 0 "CMD_BYTE_FIN\n/3/" +S 194 169 12288 ELLIPSE "States" | 61318,198350 6500 6500 +W 197 169 0 176 194 BEZIER "Transitions" | 60038,220079 60241,216895 60646,208095 60689,204810 +C 200 197 0 TEXT "Conditions" | 62427,219576 1 0 0 "txDataFull == 1'b0" +A 201 197 16 TEXT "Actions" | 62131,214610 1 0 0 "txDataOut <= cmdByte;\ntxDataWen <= 1'b1;" +W 202 169 0 242 205 BEZIER "Transitions" | 65275,171028 65478,167844 67531,155583 67557,152187 +A 203 202 16 TEXT "Actions" | 55728,165182 1 0 0 "txDataOut <= dataByte1;\ntxDataWen <= 1'b1;" +C 204 202 0 TEXT "Conditions" | 67553,171135 1 0 0 "txDataFull == 1'b0" +S 205 169 16384 ELLIPSE "States" | 67858,145716 6500 6500 +L 206 205 0 TEXT "State Labels" | 67858,145716 1 0 0 "D_BYTE1_FIN\n/4/" +W 222 169 0 247 225 BEZIER "Transitions" | 52145,109346 52666,106042 53123,98876 53547,95545 +A 223 222 16 TEXT "Actions" | 54540,105067 1 0 0 "txDataOut <= dataByte2;\ntxDataWen <= 1'b1;" +C 224 222 0 TEXT "Conditions" | 54606,109737 1 0 0 "txDataFull == 1'b0" +S 225 169 0 ELLIPSE "States" | 54296,89091 6500 6500 +L 226 225 0 TEXT "State Labels" | 54296,89091 1 0 0 "D_BYTE2_FIN\n/0/" +L 233 234 0 TEXT "State Labels" | 141088,262390 1 0 0 "REQ_RESP_ST\n/5/" +S 234 169 20480 ELLIPSE "States" | 141088,262390 6500 6500 +L 236 237 0 TEXT "State Labels" | 142710,231828 1 0 0 "REQ_RESP_FIN\n/6/" +S 237 169 24576 ELLIPSE "States" | 142710,231828 6500 6500 +L 238 239 0 TEXT "State Labels" | 145411,207811 1 0 0 "CHK_RESP\n/7/" +S 239 169 28672 ELLIPSE "States" | 145411,207811 6500 6500 +C 255 253 0 TEXT "Conditions" | 150412,229033 1 0 0 "rxDataRdy == 1'b1" +W 253 169 0 237 239 BEZIER "Transitions" | 143448,225372 143908,221460 144298,218142 144670,214266 +S 247 169 4096 ELLIPSE "States" | 51517,115810 6500 6500 +L 246 247 0 TEXT "State Labels" | 51517,115810 1 0 0 "D_BYTE2_ST\n/1/" +W 245 169 0 194 242 BEZIER "Transitions" | 62217,191914 62763,188911 63074,186881 63620,183878 +A 243 205 4 TEXT "Actions" | 77303,148032 1 0 0 "txDataWen <= 1'b0;" +S 242 169 32768 ELLIPSE "States" | 64894,177508 6500 6500 +L 241 242 0 TEXT "State Labels" | 64894,177508 1 0 0 "D_BYTE1_ST\n/8/" +A 240 194 4 TEXT "Actions" | 71835,200982 1 0 0 "txDataWen <= 1'b0;" +W 264 169 3 239 234 BEZIER "Transitions" | 140148,211623 134593,217246 123512,226873 120971,232699\ + 118431,238525 119380,250586 121717,254311 124054,258037\ + 130485,259851 134685,261273 +C 263 262 0 TEXT "Conditions" | 112592,197061 1 0 0 "respByte[7] == 1'b0" +W 262 169 2 239 184 BEZIER "Transitions" | 143473,201609 142051,196460 135404,184680 133914,179562 +C 261 260 0 TEXT "Conditions" | 158534,204974 1 0 0 "timeOutCnt == 10'h200" +W 260 169 1 239 184 BEZIER "Transitions" | 151546,205667 157905,203655 172683,180675 136858,177514 +END diff --git a/usrp2/fpga/opencores/sd_interface/RTL/sendCmd.v b/usrp2/fpga/opencores/sd_interface/RTL/sendCmd.v new file mode 100644 index 00000000..25f68298 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/sendCmd.v @@ -0,0 +1,369 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// sendCmd.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" + + +module sendCmd (checkSumByte_1, checkSumByte_2, clk, cmdByte_1, cmdByte_2, dataByte1_1, dataByte1_2, dataByte2_1, dataByte2_2, dataByte3_1, dataByte3_2, dataByte4_1, dataByte4_2, respByte, respTout, rst, rxDataIn, rxDataRdy, rxDataRdyClr, sendCmdRdy, sendCmdReq1, sendCmdReq2, txDataEmpty, txDataFull, txDataOut, txDataWen); +input [7:0]checkSumByte_1; +input [7:0]checkSumByte_2; +input clk; +input [7:0]cmdByte_1; +input [7:0]cmdByte_2; +input [7:0]dataByte1_1; +input [7:0]dataByte1_2; +input [7:0]dataByte2_1; +input [7:0]dataByte2_2; +input [7:0]dataByte3_1; +input [7:0]dataByte3_2; +input [7:0]dataByte4_1; +input [7:0]dataByte4_2; +input rst; +input [7:0]rxDataIn; +input rxDataRdy; +input sendCmdReq1; +input sendCmdReq2; +input txDataEmpty; +input txDataFull; +output [7:0]respByte; +output respTout; +output rxDataRdyClr; +output sendCmdRdy; +output [7:0]txDataOut; +output txDataWen; + +wire [7:0]checkSumByte_1; +wire [7:0]checkSumByte_2; +wire clk; +wire [7:0]cmdByte_1; +wire [7:0]cmdByte_2; +wire [7:0]dataByte1_1; +wire [7:0]dataByte1_2; +wire [7:0]dataByte2_1; +wire [7:0]dataByte2_2; +wire [7:0]dataByte3_1; +wire [7:0]dataByte3_2; +wire [7:0]dataByte4_1; +wire [7:0]dataByte4_2; +reg [7:0]respByte, next_respByte; +reg respTout, next_respTout; +wire rst; +wire [7:0]rxDataIn; +wire rxDataRdy; +reg rxDataRdyClr, next_rxDataRdyClr; +reg sendCmdRdy, next_sendCmdRdy; +wire sendCmdReq1; +wire sendCmdReq2; +wire txDataEmpty; +wire txDataFull; +reg [7:0]txDataOut, next_txDataOut; +reg txDataWen, next_txDataWen; + +// diagram signals declarations +reg [7:0]checkSumByte, next_checkSumByte; +reg [7:0]cmdByte, next_cmdByte; +reg [7:0]dataByte1, next_dataByte1; +reg [7:0]dataByte2, next_dataByte2; +reg [7:0]dataByte3, next_dataByte3; +reg [7:0]dataByte4, next_dataByte4; +reg sendCmdReq, next_sendCmdReq; +reg [9:0]timeOutCnt, next_timeOutCnt; + +// BINARY ENCODED state machine: sndCmdSt +// State codes definitions: +`define CMD_D_BYTE2_FIN 5'b00000 +`define CMD_D_BYTE2_ST 5'b00001 +`define CMD_SEND_FF_FIN 5'b00010 +`define CMD_CMD_BYTE_FIN 5'b00011 +`define CMD_D_BYTE1_FIN 5'b00100 +`define CMD_REQ_RESP_ST 5'b00101 +`define CMD_REQ_RESP_FIN 5'b00110 +`define CMD_CHK_RESP 5'b00111 +`define CMD_D_BYTE1_ST 5'b01000 +`define CMD_D_BYTE3_FIN 5'b01001 +`define CMD_D_BYTE3_ST 5'b01010 +`define CMD_D_BYTE4_FIN 5'b01011 +`define CMD_D_BYTE4_ST 5'b01100 +`define CMD_CS_FIN 5'b01101 +`define CMD_CS_ST 5'b01110 +`define CMD_SEND_FF_ST 5'b01111 +`define CMD_CMD_BYTE_ST 5'b10000 +`define WT_CMD 5'b10001 +`define ST_S_CMD 5'b10010 +`define CMD_DEL 5'b10011 + +reg [4:0]CurrState_sndCmdSt, NextState_sndCmdSt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION +always @(sendCmdReq1 or sendCmdReq2 ) begin +sendCmdReq <= sendCmdReq1 | sendCmdReq2; +end +always @(posedge clk) begin +cmdByte <= cmdByte_1 | cmdByte_2; +dataByte1 <= dataByte1_1 | dataByte1_2; +dataByte2 <= dataByte2_1 | dataByte2_2; +dataByte3 <= dataByte3_1 | dataByte3_2; +dataByte4 <= dataByte4_1 | dataByte4_2; +checkSumByte <= checkSumByte_1 | checkSumByte_2; +end + + +// Machine: sndCmdSt + +// NextState logic (combinatorial) +always @ (txDataFull or dataByte2 or timeOutCnt or rxDataRdy or rxDataIn or respByte or dataByte1 or dataByte3 or dataByte4 or txDataEmpty or checkSumByte or cmdByte or sendCmdReq or txDataWen or txDataOut or rxDataRdyClr or respTout or sendCmdRdy or CurrState_sndCmdSt) +begin + NextState_sndCmdSt <= CurrState_sndCmdSt; + // Set default values for outputs and signals + next_txDataWen <= txDataWen; + next_txDataOut <= txDataOut; + next_timeOutCnt <= timeOutCnt; + next_rxDataRdyClr <= rxDataRdyClr; + next_respByte <= respByte; + next_respTout <= respTout; + next_sendCmdRdy <= sendCmdRdy; + case (CurrState_sndCmdSt) // synopsys parallel_case full_case + `WT_CMD: + begin + next_sendCmdRdy <= 1'b1; + if (sendCmdReq == 1'b1) + begin + NextState_sndCmdSt <= `CMD_SEND_FF_ST; + next_sendCmdRdy <= 1'b0; + next_respTout <= 1'b0; + end + end + `ST_S_CMD: + begin + next_sendCmdRdy <= 1'b0; + next_txDataWen <= 1'b0; + next_txDataOut <= 8'h00; + next_rxDataRdyClr <= 1'b0; + next_respByte <= 8'h00; + next_respTout <= 1'b0; + next_timeOutCnt <= 10'h000; + NextState_sndCmdSt <= `WT_CMD; + end + `CMD_D_BYTE2_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_D_BYTE3_ST; + end + `CMD_D_BYTE2_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_D_BYTE2_FIN; + next_txDataOut <= dataByte2; + next_txDataWen <= 1'b1; + end + end + `CMD_SEND_FF_FIN: + begin + NextState_sndCmdSt <= `CMD_CMD_BYTE_ST; + end + `CMD_CMD_BYTE_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_D_BYTE1_ST; + end + `CMD_D_BYTE1_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_D_BYTE2_ST; + end + `CMD_REQ_RESP_ST: + begin + NextState_sndCmdSt <= `CMD_DEL; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + next_timeOutCnt <= timeOutCnt + 1'b1; + next_rxDataRdyClr <= 1'b1; + end + `CMD_REQ_RESP_FIN: + begin + if (rxDataRdy == 1'b1) + begin + NextState_sndCmdSt <= `CMD_CHK_RESP; + next_respByte <= rxDataIn; + end + end + `CMD_CHK_RESP: + begin + if (timeOutCnt == 10'h200) + begin + NextState_sndCmdSt <= `WT_CMD; + next_respTout <= 1'b1; + end + else if (respByte[7] == 1'b0) + begin + NextState_sndCmdSt <= `WT_CMD; + end + else + begin + NextState_sndCmdSt <= `CMD_REQ_RESP_ST; + end + end + `CMD_D_BYTE1_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_D_BYTE1_FIN; + next_txDataOut <= dataByte1; + next_txDataWen <= 1'b1; + end + end + `CMD_D_BYTE3_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_D_BYTE4_ST; + end + `CMD_D_BYTE3_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_D_BYTE3_FIN; + next_txDataOut <= dataByte3; + next_txDataWen <= 1'b1; + end + end + `CMD_D_BYTE4_FIN: + begin + next_txDataWen <= 1'b0; + NextState_sndCmdSt <= `CMD_CS_ST; + end + `CMD_D_BYTE4_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_D_BYTE4_FIN; + next_txDataOut <= dataByte4; + next_txDataWen <= 1'b1; + end + end + `CMD_CS_FIN: + begin + next_txDataWen <= 1'b0; + next_timeOutCnt <= 10'h000; + if (txDataEmpty == 1'b1) + begin + NextState_sndCmdSt <= `CMD_REQ_RESP_ST; + end + end + `CMD_CS_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_CS_FIN; + next_txDataOut <= checkSumByte; + next_txDataWen <= 1'b1; + end + end + `CMD_SEND_FF_ST: + begin + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_SEND_FF_FIN; + next_txDataOut <= 8'hff; + next_txDataWen <= 1'b1; + end + end + `CMD_CMD_BYTE_ST: + begin + next_txDataWen <= 1'b0; + if (txDataFull == 1'b0) + begin + NextState_sndCmdSt <= `CMD_CMD_BYTE_FIN; + next_txDataOut <= cmdByte; + next_txDataWen <= 1'b1; + end + end + `CMD_DEL: + begin + NextState_sndCmdSt <= `CMD_REQ_RESP_FIN; + next_txDataWen <= 1'b0; + next_rxDataRdyClr <= 1'b0; + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_sndCmdSt <= `ST_S_CMD; + else + CurrState_sndCmdSt <= NextState_sndCmdSt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + txDataWen <= 1'b0; + txDataOut <= 8'h00; + rxDataRdyClr <= 1'b0; + respByte <= 8'h00; + respTout <= 1'b0; + sendCmdRdy <= 1'b0; + timeOutCnt <= 10'h000; + end + else + begin + txDataWen <= next_txDataWen; + txDataOut <= next_txDataOut; + rxDataRdyClr <= next_rxDataRdyClr; + respByte <= next_respByte; + respTout <= next_respTout; + sendCmdRdy <= next_sendCmdRdy; + timeOutCnt <= next_timeOutCnt; + end +end + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/sd_interface/RTL/spiCtrl.asf b/usrp2/fpga/opencores/sd_interface/RTL/spiCtrl.asf new file mode 100644 index 00000000..a5bdd745 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/spiCtrl.asf @@ -0,0 +1,141 @@ +VERSION=1.15 +HEADER +FILE="spiCtrl.asf" +FID=4788d213 +LANGUAGE=VERILOG +ENTITY="spiCtrl" +FRAMES=ON +FREEOID=187 +"LIBRARIES=//////////////////////////////////////////////////////////////////////\n//// ////\n//// spiCtrl.v ////\n//// ////\n//// This file is part of the spiMaster opencores effort.\n//// ////\n//// ////\n//// Module Description: ////\n//// parameterized dual clock domain fifo. \n//// fifo depth is restricted to 2^ADDR_WIDTH\n//// No protection against over runs and under runs.\n//// \n//// ////\n//// To Do: ////\n//// \n//// ////\n//// Author(s): ////\n//// - Steve Fielding, sfielding@base2designs.com ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//// ////\n//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////\n//// ////\n//// This source file may be used and distributed without ////\n//// restriction provided that this copyright statement is not ////\n//// removed from the file and that any derivative work contains ////\n//// the original copyright notice and the associated disclaimer. ////\n//// ////\n//// This source file is free software; you can redistribute it ////\n//// and/or modify it under the terms of the GNU Lesser General ////\n//// Public License as published by the Free Software Foundation; ////\n//// either version 2.1 of the License, or (at your option) any ////\n//// later version. ////\n//// ////\n//// This source is distributed in the hope that it will be ////\n//// useful, but WITHOUT ANY WARRANTY; without even the implied ////\n//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////\n//// PURPOSE. See the GNU Lesser General Public License for more ////\n//// details. ////\n//// ////\n//// You should have received a copy of the GNU Lesser General ////\n//// Public License along with this source; if not, download it ////\n//// from ////\n//// ////\n//////////////////////////////////////////////////////////////////////\n//\n`include \"timescale.v\"\n`include \"spiMaster_defines.v\"\n" +END +BUNDLES +B T "Declarations" 0,0,255 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Conditions" 0,0,0 0 0 0 255,255,255 0 3125 0 0110 1 "Arial" 0 +B F "States" 0,0,0 0 0 1 0,255,0 1 3527 1480 0000 1 "Arial" 0 +B T "Actions" 0,0,0 0 0 1 255,255,255 0 3125 0 0000 1 "Arial" 0 +B T "Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 "Arial" 0 +B L "Transitions" 0,0,0 0 0 1 0,0,0 1 3527 1480 0000 1 "Arial" 0 +B F "Ports" 0,0,0 0 0 1 0,255,255 1 3527 1480 0000 1 "Arial" 0 +B L "Errors" 255,0,0 0 3 1 255,255,255 1 3527 1480 0000 1 "Arial" 0 +B T "State Labels" 0,0,0 0 0 0 255,255,255 0 3125 0 0000 1 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102862,186278 81827,184985 67818,183250 +L 98 99 0 TEXT "State Labels" | 61244,155715 1 0 0 "J1" +S 99 6 8196 ELLIPSE 0,0,0 0 0 1 255,0,0 1 | 61335,155624 3871 3871 +W 100 6 0 96 99 BEZIER "Transitions" | 61562,175246 61630,170469 58461,163807 60148,158618 +C 101 100 0 TEXT "Conditions" | 62422,174791 1 0 0 "spiTransCtrl == `TRANS_START" +A 102 100 16 TEXT "Actions" | 58411,169566 1 0 0 "spiTransSts <= `TRANS_BUSY;" +H 103 99 0 RECT 0,0,0 0 0 1 255,255,255 0 | 28400,28400 212900,276400 +I 106 103 0 Builtin Entry | 96520,182880 +I 107 103 0 Builtin Exit | 144780,121920 +W 108 103 0 106 107 BEZIER "Transitions" | 100342,182880 105892,175161 136499,129639 142050,121920 +L 110 111 0 TEXT "State Labels" | 138174,125339 1 0 0 "DIR_ACC\n/3/" +S 111 6 16384 ELLIPSE "States" | 138174,125339 6500 6500 +W 113 6 0 99 111 BEZIER "Transitions" | 61166,151770 61234,146806 61130,137919 61640,134485\ + 62150,131051 64054,127243 73166,126223 82278,125203\ + 114404,125351 131676,125215 +C 115 113 0 TEXT "Conditions" | 67726,131051 1 0 0 "spiTransType == `DIRECT_ACCESS" +L 120 121 0 TEXT "Labels" | 46442,250017 1 0 0 "txDataWen" +I 121 0 2 Builtin OutPort | 40442,250017 "" "" +A 123 113 16 TEXT "Actions" | 94110,126699 1 0 0 "txDataWen <= 1'b1;\nspiCS_n <= 1'b0;" +A 125 111 4 TEXT "Actions" | 125118,137851 1 0 0 "txDataWen <= 1'b0;" +L 126 127 0 TEXT "State Labels" | 164014,125067 1 0 0 "WT_FIN1\n/2/" +S 127 6 12288 ELLIPSE "States" | 164014,125067 6500 6500 +W 128 6 0 111 127 BEZIER "Transitions" | 144619,124502 150739,124502 151363,124352 157533,124582 +W 136 6 0 127 96 BEZIER "Transitions" | 162717,131431 160337,140339 156330,157231 149122,163725\ + 141914,170219 117842,178379 106656,180181 95470,181983\ + 78345,181829 68009,181353 +C 137 136 0 TEXT "Conditions" | 156126,140571 1 0 0 "rxDataRdy == 1'b1" +A 138 136 16 TEXT "Actions" | 144158,151179 1 0 0 "rxDataRdyClr <= 1'b1;\nspiCS_n <= 1'b1;" +A 139 96 4 TEXT "Actions" | 42430,197963 1 0 0 "rxDataRdyClr <= 1'b0;\nspiTransSts <= `TRANS_NOT_BUSY;" +L 140 141 0 TEXT "State Labels" | 138990,98683 1 0 0 "INIT\n/4/" +S 141 6 20480 ELLIPSE "States" | 138990,98683 6500 6500 +W 142 6 0 99 141 BEZIER "Transitions" | 60786,151798 60378,142958 58886,126563 58818,120307\ + 58750,114051 59294,106707 60280,104225 61266,101743\ + 64666,99159 74118,98581 83570,98003 115288,98421\ + 132492,98557 +C 144 142 0 TEXT "Conditions" | 66910,103851 1 0 0 "spiTransType == `INIT_SD" +A 146 142 16 TEXT "Actions" | 93022,99499 1 0 0 "SDInitReq <= 1'b1;" +L 147 148 0 TEXT "State Labels" | 163742,99499 1 0 0 "WT_FIN2\n/5/" +S 148 6 24576 ELLIPSE "States" | 163742,99499 6500 6500 +W 149 6 0 141 148 BEZIER "Transitions" | 145474,99128 150302,99196 152415,99360 157243,99428 +A 150 141 4 TEXT "Actions" | 122126,110651 1 0 0 "SDInitReq <= 1'b0;" +W 151 6 0 148 96 BEZIER "Transitions" | 168589,103829 172805,107705 180470,114663 182272,121531\ + 184074,128399 182850,148119 177444,156007 172038,163895\ + 151638,175727 141812,179059 131986,182391 113082,183887\ + 103562,183887 94042,183887 77595,182762 68007,182014 +C 152 151 0 TEXT "Conditions" | 162382,115003 1 0 0 "SDInitRdy == 1'b1" +L 153 154 0 TEXT "State Labels" | 139806,74203 1 0 0 "RW\n/6/" +S 154 6 28672 ELLIPSE "States" | 139806,74203 6500 6500 +L 155 156 0 TEXT "State Labels" | 165374,73931 1 0 0 "WT_FIN3\n/7/" +S 156 6 32768 ELLIPSE "States" | 165374,73931 6500 6500 +W 161 6 0 99 154 BEZIER "Transitions" | 60982,151777 60302,133009 58070,97323 58546,87327\ + 59022,77331 62286,74883 71942,74271 81598,73659\ + 115628,74049 133308,74049 +W 162 6 0 99 154 BEZIER "Transitions" | 61169,151767 60217,127151 57526,79507 57832,66587\ + 58138,53667 62998,56357 73205,49463 83413,42570\ + 122689,61354 133487,72683 +W 163 6 0 154 156 BEZIER "Transitions" | 146246,75076 150598,74736 154569,75047 158921,74707 +C 165 161 0 TEXT "Conditions" | 65006,80459 1 0 0 "spiTransType == `RW_WRITE_SD_BLOCK" +C 166 162 0 TEXT "Conditions" | 61742,61486 1 0 0 "spiTransType == `RW_READ_SD_BLOCK" +A 167 161 16 TEXT "Actions" | 64462,75019 1 0 0 "readWriteSDBlockReq <= `WRITE_SD_BLOCK;" +A 168 162 16 TEXT "Actions" | 60862,54842 1 0 0 "readWriteSDBlockReq <= `READ_SD_BLOCK;" +A 169 154 4 TEXT "Actions" | 103358,87803 1 0 0 "readWriteSDBlockReq <= `NO_BLOCK_REQ;" +W 170 6 0 156 96 BEZIER "Transitions" | 171013,77161 178425,82737 192778,92291 196144,105313\ + 199510,118335 198150,159271 192336,170967 186522,182663\ + 164626,188511 153678,189531 142730,190551 120834,188783\ + 109886,187661 98938,186539 78902,183914 67954,182554 +C 171 170 0 TEXT "Conditions" | 168638,86715 1 0 0 "readWriteSDBlockRdy == 1'b1" +L 172 173 0 TEXT "Labels" | 46441,240515 1 0 0 "rxDataRdyClr" +I 173 0 2 Builtin OutPort | 40441,240515 "" "" +L 176 177 0 TEXT "Labels" | 133432,244833 1 0 0 "readWriteSDBlockReq[1:0]" +I 177 0 130 Builtin OutPort | 127432,244833 "" "" +L 178 179 0 TEXT "Labels" | 48477,245479 1 0 0 "rxDataRdy" +I 179 0 2 Builtin InPort | 42477,245479 "" "" +L 182 183 0 TEXT "Labels" | 135468,240330 1 0 0 "readWriteSDBlockRdy" +I 183 0 2 Builtin InPort | 129468,240330 "" "" +A 184 78 4 TEXT "Actions" | 131510,229116 1 0 0 "readWriteSDBlockReq <= `NO_BLOCK_REQ;\ntxDataWen <= 1'b0;\nSDInitReq <= 1'b0;\nrxDataRdyClr <= 1'b0;\nspiTransSts <= `TRANS_NOT_BUSY;\nspiCS_n <= 1'b1;" +L 185 186 0 TEXT "Labels" | 165711,256531 1 0 0 "spiCS_n" +I 186 0 2 Builtin OutPort | 159711,256531 "" "" +END diff --git a/usrp2/fpga/opencores/sd_interface/RTL/spiCtrl.v b/usrp2/fpga/opencores/sd_interface/RTL/spiCtrl.v new file mode 100644 index 00000000..0f84004a --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/spiCtrl.v @@ -0,0 +1,224 @@ + +////////////////////////////////////////////////////////////////////// +//// //// +//// spiCtrl.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module spiCtrl (clk, readWriteSDBlockRdy, readWriteSDBlockReq, rst, rxDataRdy, rxDataRdyClr, SDInitRdy, SDInitReq, spiCS_n, spiTransCtrl, spiTransSts, spiTransType, txDataWen); +input clk; +input readWriteSDBlockRdy; +input rst; +input rxDataRdy; +input SDInitRdy; +input spiTransCtrl; +input [1:0]spiTransType; +output [1:0]readWriteSDBlockReq; +output rxDataRdyClr; +output SDInitReq; +output spiCS_n; +output spiTransSts; +output txDataWen; + +wire clk; +wire readWriteSDBlockRdy; +reg [1:0]readWriteSDBlockReq, next_readWriteSDBlockReq; +wire rst; +wire rxDataRdy; +reg rxDataRdyClr, next_rxDataRdyClr; +wire SDInitRdy; +reg SDInitReq, next_SDInitReq; +reg spiCS_n, next_spiCS_n; +wire spiTransCtrl; +reg spiTransSts, next_spiTransSts; +wire [1:0]spiTransType; +reg txDataWen, next_txDataWen; + +// BINARY ENCODED state machine: spiCtrlSt +// State codes definitions: +`define ST_S_CTRL 3'b000 +`define WT_S_CTRL_REQ 3'b001 +`define WT_FIN1 3'b010 +`define DIR_ACC 3'b011 +`define INIT 3'b100 +`define WT_FIN2 3'b101 +`define RW 3'b110 +`define WT_FIN3 3'b111 + +reg [2:0]CurrState_spiCtrlSt, NextState_spiCtrlSt; + +// Diagram actions (continuous assignments allowed only: assign ...) +// diagram ACTION + + +// Machine: spiCtrlSt + +// NextState logic (combinatorial) +always @ (spiTransCtrl or rxDataRdy or spiTransType or SDInitRdy or readWriteSDBlockRdy or readWriteSDBlockReq or txDataWen or SDInitReq or rxDataRdyClr or spiTransSts or spiCS_n or CurrState_spiCtrlSt) +begin + NextState_spiCtrlSt <= CurrState_spiCtrlSt; + // Set default values for outputs and signals + next_readWriteSDBlockReq <= readWriteSDBlockReq; + next_txDataWen <= txDataWen; + next_SDInitReq <= SDInitReq; + next_rxDataRdyClr <= rxDataRdyClr; + next_spiTransSts <= spiTransSts; + next_spiCS_n <= spiCS_n; + case (CurrState_spiCtrlSt) // synopsys parallel_case full_case + `ST_S_CTRL: + begin + next_readWriteSDBlockReq <= `NO_BLOCK_REQ; + next_txDataWen <= 1'b0; + next_SDInitReq <= 1'b0; + next_rxDataRdyClr <= 1'b0; + next_spiTransSts <= `TRANS_NOT_BUSY; + next_spiCS_n <= 1'b1; + NextState_spiCtrlSt <= `WT_S_CTRL_REQ; + end + `WT_S_CTRL_REQ: + begin + next_rxDataRdyClr <= 1'b0; + next_spiTransSts <= `TRANS_NOT_BUSY; + if ((spiTransCtrl == `TRANS_START) && (spiTransType == `INIT_SD)) + begin + NextState_spiCtrlSt <= `INIT; + next_spiTransSts <= `TRANS_BUSY; + next_SDInitReq <= 1'b1; + end + else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_WRITE_SD_BLOCK)) + begin + NextState_spiCtrlSt <= `RW; + next_spiTransSts <= `TRANS_BUSY; + next_readWriteSDBlockReq <= `WRITE_SD_BLOCK; + end + else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_READ_SD_BLOCK)) + begin + NextState_spiCtrlSt <= `RW; + next_spiTransSts <= `TRANS_BUSY; + next_readWriteSDBlockReq <= `READ_SD_BLOCK; + end + else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `DIRECT_ACCESS)) + begin + NextState_spiCtrlSt <= `DIR_ACC; + next_spiTransSts <= `TRANS_BUSY; + next_txDataWen <= 1'b1; + next_spiCS_n <= 1'b0; + end + end + `WT_FIN1: + begin + if (rxDataRdy == 1'b1) + begin + NextState_spiCtrlSt <= `WT_S_CTRL_REQ; + next_rxDataRdyClr <= 1'b1; + next_spiCS_n <= 1'b1; + end + end + `DIR_ACC: + begin + next_txDataWen <= 1'b0; + NextState_spiCtrlSt <= `WT_FIN1; + end + `INIT: + begin + next_SDInitReq <= 1'b0; + NextState_spiCtrlSt <= `WT_FIN2; + end + `WT_FIN2: + begin + if (SDInitRdy == 1'b1) + begin + NextState_spiCtrlSt <= `WT_S_CTRL_REQ; + end + end + `RW: + begin + next_readWriteSDBlockReq <= `NO_BLOCK_REQ; + NextState_spiCtrlSt <= `WT_FIN3; + end + `WT_FIN3: + begin + if (readWriteSDBlockRdy == 1'b1) + begin + NextState_spiCtrlSt <= `WT_S_CTRL_REQ; + end + end + endcase +end + +// Current State Logic (sequential) +always @ (posedge clk) +begin + if (rst == 1'b1) + CurrState_spiCtrlSt <= `ST_S_CTRL; + else + CurrState_spiCtrlSt <= NextState_spiCtrlSt; +end + +// Registered outputs logic +always @ (posedge clk) +begin + if (rst == 1'b1) + begin + readWriteSDBlockReq <= `NO_BLOCK_REQ; + txDataWen <= 1'b0; + SDInitReq <= 1'b0; + rxDataRdyClr <= 1'b0; + spiTransSts <= `TRANS_NOT_BUSY; + spiCS_n <= 1'b1; + end + else + begin + readWriteSDBlockReq <= next_readWriteSDBlockReq; + txDataWen <= next_txDataWen; + SDInitReq <= next_SDInitReq; + rxDataRdyClr <= next_rxDataRdyClr; + spiTransSts <= next_spiTransSts; + spiCS_n <= next_spiCS_n; + end +end + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/sd_interface/RTL/spiMaster.v b/usrp2/fpga/opencores/sd_interface/RTL/spiMaster.v new file mode 100644 index 00000000..af844baa --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/spiMaster.v @@ -0,0 +1,383 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// spiMaster.v //// +//// //// +//// This file is part of the spiMaster opencores effort. +//// //// +//// //// +//// Module Description: //// +//// parameterized dual clock domain fifo. +//// fifo depth is restricted to 2^ADDR_WIDTH +//// No protection against over runs and under runs. +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + +module spiMaster( + clk_i, + rst_i, + address_i, + data_i, + data_o, + strobe_i, + we_i, + ack_o, + + // SPI logic clock + spiSysClk, + + //SPI bus + spiClkOut, + spiDataIn, + spiDataOut, + spiCS_n +); + +//Wishbone bus +input clk_i; +input rst_i; +input [7:0] address_i; +input [7:0] data_i; +output [7:0] data_o; +input strobe_i; +input we_i; +output ack_o; + +// SPI logic clock +input spiSysClk; + +//SPI bus +output spiClkOut; +input spiDataIn; +output spiDataOut; +output spiCS_n; + +// local wires and regs +wire spiSysClk; +wire [7:0] spiClkDelayFromInitSD; +wire rstSyncToSpiClk; +wire [7:0] rxDataFromRWSPIWireData; +wire rxDataRdySetFromRWSPIWireData; +wire txDataFullFromSpiTxRxData; +wire txDataFullClrFromRWSPIWireData; +wire [7:0] txDataToRWSPIWireData; +wire rxDataRdyClrFromRWSDBlock; +wire rxDataRdyClrFromSendCmd; +wire [7:0] rxDataFromSpiTxRxData; +wire rxDataRdy; +wire [7:0] txDataFromRWSDBlock; +wire txDataWenFromRWSDBlock; +wire [7:0] txDataFromSendCmd; +wire txDataWenFromSendCmd; +wire [7:0] txDataFromInitSD; +wire txDataWenFromInitSD; +wire [7:0] dataFromCtrlStsReg; +wire [7:0] dataFromTxFifo; +wire [7:0] dataFromRxFifo; +wire [1:0] spiTransType; +wire [7:0] spiDirectAccessTxData; +wire [1:0] readWriteSDBlockReq; +wire [1:0] SDWriteError; +wire [1:0] SDReadError; +wire [1:0] SDInitError; +wire [7:0] cmdByteFromInitSD; +wire [7:0] dataByte1FromInitSD; +wire [7:0] dataByte2FromInitSD; +wire [7:0] dataByte3FromInitSD; +wire [7:0] dataByte4FromInitSD; +wire [7:0] checkSumByteFromInitSD; +wire [7:0] sendCmdRespByte; +wire [7:0] cmdByteFromRWSDBlock; +wire [7:0] dataByte1FromRWSDBlock; +wire [7:0] dataByte2FromRWSDBlock; +wire [7:0] dataByte3FromRWSDBlock; +wire [7:0] dataByte4FromRWSDBlock; +wire [7:0] checkSumByteFromRWSDBlock; +wire [7:0] txFifoDataOut; +wire [7:0] rxFifoDataIn; +wire [31:0] SDAddr; +wire [7:0] spiClkDelayFromCtrlStsReg; +wire spiCS_nFromInitSD; +wire spiCS_nFromRWSDBlock; +wire spiCS_nFromSpiCtrl; + + +assign spiCS_n = spiCS_nFromInitSD & spiCS_nFromRWSDBlock & spiCS_nFromSpiCtrl; + +// ----------------------------------- +// Instance of Module: wishBoneBI +// ----------------------------------- +wishBoneBI u_wishBoneBI( + .ack_o( ack_o ), + .address( address_i ), + .clk( clk_i ), + .ctrlStsRegSel( ctrlStsRegSel ), + .dataFromCtrlStsReg( dataFromCtrlStsReg ), + .dataFromRxFifo( dataFromRxFifo ), + .dataFromTxFifo( dataFromTxFifo ), + .dataIn( data_i ), + .dataOut( data_o ), + .rst( rst_i ), + .rxFifoSel( rxFifoSel ), + .strobe_i( strobe_i ), + .txFifoSel( txFifoSel ), + .writeEn( we_i ) + ); + +// ----------------------------------- +// Instance of Module: ctrlStsRegBI +// ----------------------------------- +ctrlStsRegBI u_ctrlStsRegBI( + .busClk( clk_i ), + .spiSysClk( spiSysClk ), + .rstSyncToBusClkOut( rstSyncToBusClk ), + .rstSyncToSpiClkOut( rstSyncToSpiClk ), + .rstFromWire( rst_i ), + .address( address_i ), + .strobe_i( strobe_i ), + .dataIn( data_i ), + .dataOut( dataFromCtrlStsReg ), + .ctrlStsRegSel( ctrlStsRegSel ), + .spiTransType( spiTransType ), + .spiTransCtrl( spiTransCtrl ), + .spiTransStatus( spiTransSts ), + .spiDirectAccessTxData(spiDirectAccessTxData), + .spiDirectAccessRxData(rxDataFromSpiTxRxData), + .writeEn( we_i ), + .SDWriteError( SDWriteError ), + .SDReadError( SDReadError ), + .SDInitError( SDInitError ), + .SDAddr( SDAddr ), + .spiClkDelay( spiClkDelayFromCtrlStsReg) + ); + +// ----------------------------------- +// Instance of Module: spiCtrl +// ----------------------------------- +spiCtrl u_spiCtrl( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .SDInitReq( SDInitReq ), + .SDInitRdy( SDInitRdy ), + .readWriteSDBlockReq( readWriteSDBlockReq ), + .readWriteSDBlockRdy( readWriteSDBlockRdy ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdyClr( rxDataRdyClrFromSpiCtrl), + .spiTransType( spiTransType ), + .spiTransCtrl( spiTransCtrl ), + .spiTransSts( spiTransSts ), + .txDataWen( txDataWenFromSpiCtrl ), + .spiCS_n( spiCS_nFromSpiCtrl ) + ); + + +// ----------------------------------- +// Instance of Module: initSD +// ----------------------------------- +initSD u_initSD( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .SDInitReq( SDInitReq ), + .SDInitRdy( SDInitRdy ), + .initError( SDInitError ), + .sendCmdReq( sendCmdReqFromInitSD ), + .sendCmdRdy( sendCmdRdy ), + .cmdByte( cmdByteFromInitSD ), + .dataByte1( dataByte1FromInitSD ), + .dataByte2( dataByte2FromInitSD ), + .dataByte3( dataByte3FromInitSD ), + .dataByte4( dataByte4FromInitSD ), + .checkSumByte( checkSumByteFromInitSD), + .respByte( sendCmdRespByte ), + .respTout( sendCmdRespTout ), + .spiCS_n( spiCS_nFromInitSD ), + .spiClkDelayOut( spiClkDelayFromInitSD ), + .spiClkDelayIn( spiClkDelayFromCtrlStsReg), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataEmpty( txDataEmptyFromRWSPIWireData), + .txDataOut( txDataFromInitSD ), + .txDataWen( txDataWenFromInitSD ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdyClr( rxDataRdyClrFromInitSD) + ); + +// ----------------------------------- +// Instance of Module: readWriteSDBlock +// ----------------------------------- +readWriteSDBlock u_readWriteSDBlock( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .readWriteSDBlockReq( readWriteSDBlockReq ), + .readWriteSDBlockRdy( readWriteSDBlockRdy ), + .cmdByte( cmdByteFromRWSDBlock ), + .dataByte1( dataByte1FromRWSDBlock), + .dataByte2( dataByte2FromRWSDBlock), + .dataByte3( dataByte3FromRWSDBlock), + .dataByte4( dataByte4FromRWSDBlock), + .checkSumByte( checkSumByteFromRWSDBlock), + .readError( SDReadError ), + .respByte( sendCmdRespByte ), + .respTout( sendCmdRespTout ), + .rxDataIn( rxDataFromSpiTxRxData ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdyClr( rxDataRdyClrFromRWSDBlock), + .sendCmdRdy( sendCmdRdy ), + .sendCmdReq( sendCmdReqFromRWSDBlock), + .spiCS_n( spiCS_nFromRWSDBlock ), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataEmpty( txDataEmptyFromRWSPIWireData), + .txDataOut( txDataFromRWSDBlock ), + .txDataWen( txDataWenFromRWSDBlock), + .txFifoData( txFifoDataOut ), + .txFifoRen( txFifoRE ), + .rxFifoData( rxFifoDataIn ), + .rxFifoWen( rRxFifoWE ), + .writeError( SDWriteError ), + .blockAddr( SDAddr ) + + ); + +// ----------------------------------- +// Instance of Module: sendCmd +// ----------------------------------- +sendCmd u_sendCmd( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .sendCmdReq1( sendCmdReqFromInitSD ), + .sendCmdReq2( sendCmdReqFromRWSDBlock), + .sendCmdRdy( sendCmdRdy ), + .cmdByte_1( cmdByteFromInitSD ), + .cmdByte_2( cmdByteFromRWSDBlock ), + .dataByte1_1( dataByte1FromInitSD ), + .dataByte1_2( dataByte1FromRWSDBlock), + .dataByte2_1( dataByte2FromInitSD ), + .dataByte2_2( dataByte2FromRWSDBlock), + .dataByte3_1( dataByte3FromInitSD ), + .dataByte3_2( dataByte3FromRWSDBlock), + .dataByte4_1( dataByte4FromInitSD ), + .dataByte4_2( dataByte4FromRWSDBlock), + .checkSumByte_1( checkSumByteFromInitSD), + .checkSumByte_2( checkSumByteFromRWSDBlock), + .respByte( sendCmdRespByte ), + .respTout( sendCmdRespTout ), + .rxDataIn( rxDataFromSpiTxRxData ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdyClr( rxDataRdyClrFromSendCmd), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataEmpty( txDataEmptyFromRWSPIWireData), + .txDataOut( txDataFromSendCmd ), + .txDataWen( txDataWenFromSendCmd ) + ); + +// ----------------------------------- +// Instance of Module: spiTxRxData +// ----------------------------------- +spiTxRxData u_spiTxRxData( + .clk( spiSysClk ), + .rst( rstSyncToSpiClk ), + .rx1DataRdyClr( rxDataRdyClrFromRWSDBlock), + .rx2DataRdyClr( rxDataRdyClrFromSendCmd), + .rx3DataRdyClr( rxDataRdyClrFromInitSD), + .rx4DataRdyClr( rxDataRdyClrFromSpiCtrl), + .rxDataIn( rxDataFromRWSPIWireData), + .rxDataOut( rxDataFromSpiTxRxData ), + .rxDataRdy( rxDataRdyFromSpiTxRxData), + .rxDataRdySet( rxDataRdySetFromRWSPIWireData), + .tx1DataIn( txDataFromRWSDBlock ), + .tx1DataWEn( txDataWenFromRWSDBlock), + .tx2DataIn( txDataFromSendCmd ), + .tx2DataWEn( txDataWenFromSendCmd ), + .tx3DataIn( txDataFromInitSD ), + .tx3DataWEn( txDataWenFromInitSD ), + .tx4DataIn( spiDirectAccessTxData ), + .tx4DataWEn( txDataWenFromSpiCtrl ), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataFullClr( txDataFullClrFromRWSPIWireData), + .txDataOut( txDataToRWSPIWireData ) + ); + +// ----------------------------------- +// Instance of Module: readWriteSPIWireData +// ----------------------------------- +readWriteSPIWireData u_readWriteSPIWireData( + .clk( spiSysClk ), + .clkDelay( spiClkDelayFromInitSD ), + .rst( rstSyncToSpiClk ), + .rxDataOut( rxDataFromRWSPIWireData), + .rxDataRdySet( rxDataRdySetFromRWSPIWireData), + .spiClkOut( spiClkOut ), + .spiDataIn( spiDataIn ), + .spiDataOut( spiDataOut ), + .txDataFull( txDataFullFromSpiTxRxData), + .txDataFullClr( txDataFullClrFromRWSPIWireData), + .txDataIn( txDataToRWSPIWireData ), + .txDataEmpty( txDataEmptyFromRWSPIWireData) + ); + +TxFifo #(`TX_FIFO_DEPTH, `TX_FIFO_ADDR_WIDTH) u_txFifo ( + .spiSysClk(spiSysClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToSpiClk(rstSyncToSpiClk), + .fifoREn(txFifoRE), + .fifoEmpty(hostTxFifoEmpty), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(txFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromTxFifo), + .fifoDataOut(txFifoDataOut) ); + + +RxFifo #(`RX_FIFO_DEPTH, `RX_FIFO_ADDR_WIDTH) u_rxFifo( + .spiSysClk(spiSysClk), + .busClk(clk_i), + .rstSyncToBusClk(rstSyncToBusClk), + .rstSyncToSpiClk(rstSyncToSpiClk), + .fifoWEn(rRxFifoWE), + .fifoFull(hostRxFifoFull), + .busAddress(address_i[2:0]), + .busWriteEn(we_i), + .busStrobe_i(strobe_i), + .busFifoSelect(rxFifoSel), + .busDataIn(data_i), + .busDataOut(dataFromRxFifo), + .fifoDataIn(rxFifoDataIn) ); + +endmodule + diff --git a/usrp2/fpga/opencores/sd_interface/RTL/spiMaster_defines.v b/usrp2/fpga/opencores/sd_interface/RTL/spiMaster_defines.v new file mode 100644 index 00000000..1e219f67 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/spiMaster_defines.v @@ -0,0 +1,125 @@ +// ------------------------ spiMaster_defines.v ---------------------- +`define SPI_MASTER_VERSION_NUM 8'h00 +`define SPI_SYS_CLK_48MHZ +//`define SPI_SYS_CLK_30MHZ + +//memoryMap +`define CTRL_STS_REG_BASE 8'h00 +`define RX_FIFO_BASE 8'h10 +`define TX_FIFO_BASE 8'h20 +`define ADDRESS_DECODE_MASK 8'hf0 +`define SPI_MASTER_VERSION_REG 8'h00 +`define SPI_MASTER_CONTROL_REG 8'h01 +`define TRANS_TYPE_REG 8'h02 +`define TRANS_CTRL_REG 8'h03 +`define TRANS_STS_REG 8'h04 +`define TRANS_ERROR_REG 8'h05 +`define DIRECT_ACCESS_DATA_REG 8'h06 +`define SD_ADDR_7_0_REG 8'h07 +`define SD_ADDR_15_8_REG 8'h08 +`define SD_ADDR_23_16_REG 8'h09 +`define SD_ADDR_31_24_REG 8'h0a +`define SPI_CLK_DEL_REG 8'h0b + + +//FifoAddresses +`define FIFO_DATA_REG 3'b000 +`define FIFO_STATUS_REG 3'b001 +`define FIFO_DATA_COUNT_MSB 3'b010 +`define FIFO_DATA_COUNT_LSB 3'b011 +`define FIFO_CONTROL_REG 3'b100 + + +`ifdef SIM_COMPILE +`define SLOW_SPI_CLK 8'h2 +`define FAST_SPI_CLK 8'h00 +`define TWO_MS 10'h001 +`define TWO_FIFTY_MS 12'h001 +`define ONE_HUNDRED_MS 12'h00c +`else //not SIM_COMPILE + +`ifdef SPI_SYS_CLK_48MHZ + +// --------------- spiSysClk = 48MHz +// if you change the clock frequency you will need to change these constants + +// SLOW_SPI_CLK controls the SPI clock at start up. +// should be aiming for 400KHz +// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1 +`define SLOW_SPI_CLK 8'h3b +// controls the SPI clock after init is complete. +// should be aiming for 24MHz ? +// controls the SPI clock after init is complete. +// should be aiming for 24MHz ? +// if spiSysClk >= 48MHz +// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1 +// else FAST_SPI_CLK = 0 +`define FAST_SPI_CLK 8'h00 +// TWO_MS = ((2mS * spiSysClk) / 256) - 1 +`define TWO_MS 10'h177 +// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1 +`define TWO_FIFTY_MS 12'h0b6 +// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1 +`define ONE_HUNDRED_MS 12'h048 + +`else //not SPI_SYS_CLK_48MHZ + +`ifdef SPI_SYS_CLK_30MHZ +// --------------- spiSysClk = 30MHz +`define SLOW_SPI_CLK 8'h24 +`define FAST_SPI_CLK 8'h00 +`define TWO_MS 10'h0e9 +`define TWO_FIFTY_MS 12'h071 +`define ONE_HUNDRED_MS 12'h02c + +`endif //SPI_SYS_CLK_30MHZ +`endif //SPI_SYS_CLK_48MHZ +`endif //SIM_COMPILE + + + +`ifdef SIM_COMPILE +`define SD_INIT_START_SEQ_LEN 8'h03 +`define MAX_8_BIT 8'h08 +`else +`define SD_INIT_START_SEQ_LEN 8'ha0 +`define MAX_8_BIT 8'hff +`endif + + +`define WR_RESP_TOUT 12'hf00 + +`define NO_BLOCK_REQ 2'b00 +`define WRITE_SD_BLOCK 2'b01 +`define READ_SD_BLOCK 2'b10 + +`define READ_NO_ERROR 2'b00 +`define READ_CMD_ERROR 2'b01 +`define READ_TOKEN_ERROR 2'b10 + +`define WRITE_NO_ERROR 2'b00 +`define WRITE_CMD_ERROR 2'b01 +`define WRITE_DATA_ERROR 2'b10 +`define WRITE_BUSY_ERROR 2'b11 + + +`define TRANS_NOT_BUSY 1'b0 +`define TRANS_BUSY 1'b1 + +`define TRANS_START 1'b1 +`define TRANS_STOP 1'b0 + +`define DIRECT_ACCESS 2'b00 +`define INIT_SD 2'b01 +`define RW_READ_SD_BLOCK 2'b10 +`define RW_WRITE_SD_BLOCK 2'b11 + +`define INIT_NO_ERROR 2'b00 +`define INIT_CMD0_ERROR 2'b01 +`define INIT_CMD1_ERROR 2'b10 + +`define TX_FIFO_DEPTH 512 +`define TX_FIFO_ADDR_WIDTH 9 +`define RX_FIFO_DEPTH 512 +`define RX_FIFO_ADDR_WIDTH 9 + diff --git a/usrp2/fpga/opencores/sd_interface/RTL/spiTxRxData.v b/usrp2/fpga/opencores/sd_interface/RTL/spiTxRxData.v new file mode 100644 index 00000000..2b5870c2 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/spiTxRxData.v @@ -0,0 +1,108 @@ +`include "timescale.v" + +module spiTxRxData ( + clk, + rst, + + tx1DataIn, + tx2DataIn, + tx3DataIn, + tx4DataIn, + tx1DataWEn, + tx2DataWEn, + tx3DataWEn, + tx4DataWEn, + + txDataOut, + txDataFull, + txDataFullClr, + + rx1DataRdyClr, + rx2DataRdyClr, + rx3DataRdyClr, + rx4DataRdyClr, + + rxDataIn, + rxDataOut, + rxDataRdy, + rxDataRdySet +); + +input clk; +input rst; + +input [7:0] tx1DataIn; +input [7:0] tx2DataIn; +input [7:0] tx3DataIn; +input [7:0] tx4DataIn; +input tx1DataWEn; +input tx2DataWEn; +input tx3DataWEn; +input tx4DataWEn; + +output [7:0] txDataOut; +reg [7:0] txDataOut; +output txDataFull; +reg txDataFull; +input txDataFullClr; + +input rx1DataRdyClr; +input rx2DataRdyClr; +input rx3DataRdyClr; +input rx4DataRdyClr; + +input [7:0] rxDataIn; +output [7:0] rxDataOut; +reg [7:0] rxDataOut; +output rxDataRdy; +reg rxDataRdy; +input rxDataRdySet; + + +// --- Transmit control +always @(posedge clk) begin + if (rst == 1'b1) begin + txDataOut <= 8'h00; + txDataFull <= 1'b0; + end + else begin + if (tx1DataWEn == 1'b1) begin + txDataOut <= tx1DataIn; + txDataFull <= 1'b1; + end + else if (tx2DataWEn == 1'b1) begin + txDataOut <= tx2DataIn; + txDataFull <= 1'b1; + end + else if (tx3DataWEn == 1'b1) begin + txDataOut <= tx3DataIn; + txDataFull <= 1'b1; + end + else if (tx4DataWEn == 1'b1) begin + txDataOut <= tx4DataIn; + txDataFull <= 1'b1; + end + if (txDataFullClr == 1'b1) + txDataFull <= 1'b0; + end +end + +// --- Receive control +always @(posedge clk) begin + if (rst == 1'b1) begin + rxDataOut <= 8'h00; + rxDataRdy <= 1'b0; + end + else begin + if (rx1DataRdyClr == 1'b1 || rx2DataRdyClr == 1'b1 || rx3DataRdyClr == 1'b1 || rx4DataRdyClr == 1'b1) begin + rxDataRdy <= 1'b0; + end + if (rxDataRdySet == 1'b1) begin + rxDataRdy <= 1'b1; + rxDataOut <= rxDataIn; + end + end +end + +endmodule + diff --git a/usrp2/fpga/opencores/sd_interface/RTL/timescale.v b/usrp2/fpga/opencores/sd_interface/RTL/timescale.v new file mode 100644 index 00000000..571f4a06 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/timescale.v @@ -0,0 +1,5 @@ +////////////////////////////////////////////////////////////////////// +// timescale.v +////////////////////////////////////////////////////////////////////// +`timescale 1ns / 1ps + diff --git a/usrp2/fpga/opencores/sd_interface/RTL/wishBoneBI.v b/usrp2/fpga/opencores/sd_interface/RTL/wishBoneBI.v new file mode 100644 index 00000000..72daaa48 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/RTL/wishBoneBI.v @@ -0,0 +1,145 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wishBoneBI.v //// +//// //// +//// This file is part of the usbhostslave opencores effort. +//// //// +//// //// +//// Module Description: //// +//// +//// //// +//// To Do: //// +//// +//// //// +//// Author(s): //// +//// - Steve Fielding, sfielding@base2designs.com //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +`include "timescale.v" +`include "spiMaster_defines.v" + + +module wishBoneBI ( + clk, rst, + address, dataIn, dataOut, writeEn, + strobe_i, + ack_o, + ctrlStsRegSel, + rxFifoSel, txFifoSel, + dataFromCtrlStsReg, + dataFromRxFifo, + dataFromTxFifo + ); +input clk; +input rst; +input [7:0] address; +input [7:0] dataIn; +output [7:0] dataOut; +input strobe_i; +output ack_o; +input writeEn; +output ctrlStsRegSel; +output rxFifoSel; +output txFifoSel; +input [7:0] dataFromCtrlStsReg; +input [7:0] dataFromRxFifo; +input [7:0] dataFromTxFifo; + + +wire clk; +wire rst; +wire [7:0] address; +wire [7:0] dataIn; +reg [7:0] dataOut; +wire writeEn; +wire strobe_i; +reg ack_o; +reg ctrlStsRegSel; +reg rxFifoSel; +reg txFifoSel; +wire [7:0] dataFromCtrlStsReg; +wire [7:0] dataFromRxFifo; +wire [7:0] dataFromTxFifo; + +//internal wires and regs +reg ack_delayed; +reg ack_immediate; + +//address decode and data mux +always @(address or + dataFromCtrlStsReg or + dataFromRxFifo or + dataFromTxFifo) +begin + ctrlStsRegSel <= 1'b0; + rxFifoSel <= 1'b0; + txFifoSel <= 1'b0; + case (address & `ADDRESS_DECODE_MASK) + `CTRL_STS_REG_BASE : begin + ctrlStsRegSel <= 1'b1; + dataOut <= dataFromCtrlStsReg; + end + `RX_FIFO_BASE : begin + rxFifoSel <= 1'b1; + dataOut <= dataFromRxFifo; + end + `TX_FIFO_BASE : begin + txFifoSel <= 1'b1; + dataOut <= dataFromTxFifo; + end + default: + dataOut <= 8'h00; + endcase +end + +//delayed ack +always @(posedge clk) begin + ack_delayed <= strobe_i; +end + +//immediate ack +always @(strobe_i) begin + ack_immediate <= strobe_i; +end + +//select between immediate and delayed ack +always @(writeEn or address or ack_delayed or ack_immediate) begin + if (writeEn == 1'b0 && + (address == `RX_FIFO_BASE + `FIFO_DATA_REG || + address == `TX_FIFO_BASE + `FIFO_DATA_REG) ) + begin + ack_o <= ack_delayed; + end + else + begin + ack_o <= ack_immediate; + end +end + +endmodule diff --git a/usrp2/fpga/opencores/sd_interface/bench/testCase0.v b/usrp2/fpga/opencores/sd_interface/bench/testCase0.v new file mode 100644 index 00000000..09e4bc0f --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/bench/testCase0.v @@ -0,0 +1,126 @@ +// ---------------------------------- testcase0.v ---------------------------- +`include "timescale.v" +`include "spiMaster_defines.v" + +module testCase0(); + +reg ack; +reg [7:0] data; +reg [15:0] dataWord; +reg [7:0] dataRead; +reg [7:0] dataWrite; +integer i; +integer j; + +initial +begin + $write("\n\n"); + //testHarness.reset; + #1000; + + //write to block addr reg, and read back + //testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , 8'h5a); + $write("Testing register read/write\n"); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SPI_CLK_DEL_REG , 8'h10); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SPI_CLK_DEL_REG , 8'h10); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_7_0_REG , 8'h78); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_15_8_REG , 8'h56); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_23_16_REG , 8'h34); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`SD_ADDR_31_24_REG , 8'h12); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_7_0_REG , 8'h78); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_15_8_REG , 8'h56); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_23_16_REG , 8'h34); + testHarness.u_wb_master_model.wb_cmp(1, `CTRL_STS_REG_BASE+`SD_ADDR_31_24_REG , 8'h12); + + //write one byte to spi bus, and wait for complete + $write("Testing SPI bus direct access\n"); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `DIRECT_ACCESS}); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`DIRECT_ACCESS_DATA_REG , 8'h5f); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + while (dataRead[0] == `TRANS_BUSY) + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + + //write one byte to spi bus, and wait for complete + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`DIRECT_ACCESS_DATA_REG , 8'haa); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + while (dataRead[0] == `TRANS_BUSY) + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + + //init test + $write("Testing SD init\n"); + testHarness.u_sdModel.setRespByte(8'h01); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `INIT_SD}); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + #60000; + testHarness.u_sdModel.setRespByte(8'h00); + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + while (dataRead[0] == `TRANS_BUSY) + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_ERROR_REG , dataRead); + if (dataRead[1:0] == `INIT_NO_ERROR) + $write("SD init test passed\n"); + else + $write("---- ERROR: SD init test failed. Error code = 0x%01x\n", dataRead[1:0] ); + + //block write + $write("Testing block write\n"); + dataWrite = 8'h00; + for (i=0; i<=511; i=i+1) begin + testHarness.u_wb_master_model.wb_write(1, `TX_FIFO_BASE+`FIFO_DATA_REG , dataWrite); + dataWrite = dataWrite + 1'b1; + end + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `RW_WRITE_SD_BLOCK}); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + #100000; + testHarness.u_sdModel.setRespByte(8'h05); //write response + #8000000; + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + if (dataRead[0] == `TRANS_BUSY) begin + $write("---- ERROR: SD block write failed to complete\n"); + end + else begin + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_ERROR_REG , dataRead); + if (dataRead[5:4] == `WRITE_NO_ERROR) + $write("SD block write passed\n"); + else + $write("---- ERROR: SD block write failed. Error code = 0x%01x\n", dataRead[5:4] ); + end + + //block read + $write("Testing block read\n"); + testHarness.u_sdModel.setRespByte(8'h00); //cmd response + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_TYPE_REG , {6'b000000, `RW_READ_SD_BLOCK}); + testHarness.u_wb_master_model.wb_write(1, `CTRL_STS_REG_BASE+`TRANS_CTRL_REG , {7'b0000000, `TRANS_START}); + #100000; + testHarness.u_sdModel.setRespByte(8'hfe); //read response + #8000000; + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_STS_REG , dataRead); + if (dataRead[0] == `TRANS_BUSY) begin + $write("---- ERROR: SD block read failed to complete\n"); + end + else begin + testHarness.u_wb_master_model.wb_read(1, `CTRL_STS_REG_BASE+`TRANS_ERROR_REG , dataRead); + if (dataRead[3:2] == `READ_NO_ERROR) begin + $write("SD block read passed\n"); + for (j=0; j<=15; j=j+1) begin + $write("Data 0x%0x = ",j*32); + for (i=0; i<=31; i=i+1) begin + testHarness.u_wb_master_model.wb_read(1, `RX_FIFO_BASE+`FIFO_DATA_REG , dataRead); + $write("0x%0x ",dataRead); + end + $write("\n"); + end + end + else + $write("---- ERROR: SD block read failed. Error code = 0x%01x\n", dataRead[3:2] ); + end + + $write("Finished all tests\n"); + $stop; + +end + +endmodule + diff --git a/usrp2/fpga/opencores/sd_interface/bench/testHarness.v b/usrp2/fpga/opencores/sd_interface/bench/testHarness.v new file mode 100644 index 00000000..ce126d67 --- /dev/null +++ b/usrp2/fpga/opencores/sd_interface/bench/testHarness.v @@ -0,0 +1,105 @@ +`include "timescale.v" + +module testHarness( ); + + +// ----------------------------------- +// Local Wires +// ----------------------------------- +reg clk; +reg rst; +reg spiSysClk; +wire [7:0] adr; +wire [7:0] masterDout; +wire [7:0] masterDin; +wire stb; +wire we; +wire ack; +wire spiClk; +wire spiMasterDataIn; +wire spiMasterDataOut; +wire spiCS_n; + + +initial begin +$dumpfile("wave.vcd"); +$dumpvars(0, u_spiMaster); +end + +spiMaster u_spiMaster ( + //Wishbone bus + .clk_i(clk), + .rst_i(rst), + .address_i(adr), + .data_i(masterDout), + .data_o(masterDin), + .strobe_i(stb), + .we_i(we), + .ack_o(ack), + + // SPI logic clock + .spiSysClk(spiSysClk), + + //SPI bus + .spiClkOut(spiClk), + .spiDataIn(spiMasterDataIn), + .spiDataOut(spiMasterDataOut), + .spiCS_n(spiCS_n) +); + +wb_master_model #(.dwidth(8), .awidth(8)) u_wb_master_model ( + .clk(clk), + .rst(rst), + .adr(adr), + .din(masterDin), + .dout(masterDout), + .cyc(), + .stb(stb), + .we(we), + .sel(), + .ack(ack), + .err(1'b0), + .rty(1'b0) +); + +sdModel u_sdModel ( + .spiClk(spiClk), + .spiDataIn(spiMasterDataOut), + .spiDataOut(spiMasterDataIn), + .spiCS_n(spiCS_n) +); +//--------------- reset --------------- +initial begin + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + rst <= 1'b1; + @(posedge clk); + rst <= 1'b0; + @(posedge clk); +end + +// ****************************** Clock section ****************************** +`define CLK_50MHZ_HALF_PERIOD 10 +`define CLK_25MHZ_HALF_PERIOD 20 + +always begin + #`CLK_25MHZ_HALF_PERIOD clk <= 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z2H{vV*!oDwi$M{#BRCGdr9K1N)^Co(0$0l4(?i0rIKuRhFdWzoNe~YtNGLNBj@yD^ z0RFa=7m2{{i2Y3mfVMSXB#aQB0ZhWSU16NzZIs|B2FoGYAfsS(cO+J1!c1zy_+|;(_iv^t& zAup(Ygx``MizMvxV1S0*8V>~{#3p_$3hY=VkPnC1(%$%Sm@Rm~j{_BufET#AZNXjO z=!+z*YbY4xAoqK|C>ZFd32AsYW`cM?1%zco0qne9!uDNfc|JpKMi#O zU`N&Oc_8`GV0SYC4S10g)B`vYs(@SKp$M@A#M{!RfDRA6MK6H188@69^nsU^1O9jc z74wV02Mrk2e6ltswk#l5=s*EwTU#d=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_gray_dl1 <=0; + else + Add_rd_gray_dl1 <=Add_rd_gray; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_ungray =0; + else + begin + Add_rd_ungray[MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[MAC_RX_FF_DEPTH-1]; + for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; + end + assign Add_wr_pluse=Add_wr+1; + assign Add_wr_pluse4=Add_wr+4; + assign Add_wr_pluse3=Add_wr+3; + assign Add_wr_pluse2=Add_wr+2; + + + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Full <=0; + else if (Add_wr_pluse==Add_rd_ungray) + Full <=1; + else + Full <=0; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Almost_full <=0; + else if (Add_wr_pluse4==Add_rd_ungray|| + Add_wr_pluse3==Add_rd_ungray|| + Add_wr_pluse2==Add_rd_ungray|| + Add_wr_pluse==Add_rd_ungray + ) + Almost_full <=1; + else + Almost_full <=0; + + assign Fifo_full =Almost_full; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr <=0; + else if (Current_state==State_err_end) + Add_wr <=Add_wr_reg; + else if (Wr_en&&!Full) + Add_wr <=Add_wr +1; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump_tmp <=0; + else if (Current_state==State_err_end) + Add_wr_jump_tmp <=1; + else + Add_wr_jump_tmp <=0; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump_tmp_pl1 <=0; + else + Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_jump <=0; + else if (Current_state==State_err_end) + Add_wr_jump <=1; + else if (Add_wr_jump_tmp_pl1) + Add_wr_jump <=0; + + // + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_en_dl1 <=0; + else + Fifo_data_en_dl1 <=Fifo_data_en; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_dl1 <=0; + else + Fifo_data_dl1 <=Fifo_data; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte3 <=0; + else if (Current_state==State_byte3&&Fifo_data_en_dl1) + Fifo_data_byte3 <=Fifo_data_dl1; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte2 <=0; + else if (Current_state==State_byte2&&Fifo_data_en_dl1) + Fifo_data_byte2 <=Fifo_data_dl1; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_byte1 <=0; + else if (Current_state==State_byte1&&Fifo_data_en_dl1) + Fifo_data_byte1 <=Fifo_data_dl1; + + always @ (* ) + case (Current_state) + State_be0: + Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1}; + State_be1: + Din_tmp ={4'b1001,Fifo_data_byte3,24'h0}; + State_be2: + Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0}; + State_be3: + Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0}; + default: + Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1}; + endcase + + always @ (*) + if (Current_state==State_be0||Current_state==State_be1|| + Current_state==State_be2||Current_state==State_be3|| + (Current_state==State_byte0&&Fifo_data_en)) + Wr_en_tmp =1; + else + Wr_en_tmp =0; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Din_tmp_reg <=0; + else if(Wr_en_tmp) + Din_tmp_reg <=Din_tmp; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Wr_en_ptr <=0; + else if(Current_state==State_idle) + Wr_en_ptr <=0; + else if(Wr_en_tmp) + Wr_en_ptr <=1; + + //if not append FCS,delay one cycle write data and Wr_en signal to drop FCS + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + begin + Wr_en <=0; + Din <=0; + end + else if(RX_APPEND_CRC) + begin + Wr_en <=Wr_en_tmp; + Din <=Din_tmp; + end + else + begin + Wr_en <=Wr_en_tmp&&Wr_en_ptr; + Din <={Din_tmp[35:32],Din_tmp_reg[31:0]}; + end + + //this signal for read side to handle the packet number in fifo + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Packet_number_add_tmp <=0; + else if (Current_state==State_be0||Current_state==State_be1|| + Current_state==State_be2||Current_state==State_be3) + Packet_number_add_tmp <=1; + else + Packet_number_add_tmp <=0; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + begin + Packet_number_add_tmp_dl1 <=0; + Packet_number_add_tmp_dl2 <=0; + end + else + begin + Packet_number_add_tmp_dl1 <=Packet_number_add_tmp; + Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1; + end + + //Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram. + //expand to two cycles long almost=16 ns + //if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Packet_number_add <=0; + else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2) + Packet_number_add <=1; + else + Packet_number_add <=0; + + // ****************************************************************************** + // domain Clk_SYS,read data from dprom.b-port for read + // ****************************************************************************** + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Current_state_SYS <=SYS_idle; + else + Current_state_SYS <=Next_state_SYS; + + always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty) + case (Current_state_SYS) + SYS_idle: + if (Rx_mac_rd&&Rx_mac_ra&&!Empty) + Next_state_SYS =SYS_read; + else if(Rx_mac_rd&&Rx_mac_ra&&Empty) + Next_state_SYS =FF_emtpy_err; + else + Next_state_SYS =Current_state_SYS; + SYS_read: + if (!Rx_mac_rd) + Next_state_SYS =SYS_pause; + else if (Dout[35]) + Next_state_SYS =SYS_wait_end; + else if (Empty) + Next_state_SYS =FF_emtpy_err; + else + Next_state_SYS =Current_state_SYS; + SYS_pause: + if (Rx_mac_rd) + Next_state_SYS =SYS_read; + else + Next_state_SYS =Current_state_SYS; + FF_emtpy_err: + if (!Empty) + Next_state_SYS =SYS_read; + else + Next_state_SYS =Current_state_SYS; + SYS_wait_end: + if (!Rx_mac_rd) + Next_state_SYS =SYS_idle; + else + Next_state_SYS =Current_state_SYS; + default: + Next_state_SYS =SYS_idle; + endcase // case(Current_state_SYS) + + //gen Rx_mac_ra + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Packet_number_add_dl1 <=0; + Packet_number_add_dl2 <=0; + end + else + begin + Packet_number_add_dl1 <=Packet_number_add; + Packet_number_add_dl2 <=Packet_number_add_dl1; + end + assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2; + + always @ (Current_state_SYS or Next_state_SYS) + if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end) + Packet_number_sub =1; + else + Packet_number_sub =0; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF <=0; + else if (Packet_number_add_edge&&!Packet_number_sub) + Packet_number_inFF <=Packet_number_inFF + 1; + else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0) + Packet_number_inFF <=Packet_number_inFF - 1; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_data_count <=0; + else + Fifo_data_count <=Add_wr_ungray[MAC_RX_FF_DEPTH-1:MAC_RX_FF_DEPTH-5]-Add_rd[MAC_RX_FF_DEPTH-1:MAC_RX_FF_DEPTH-5]; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Rx_Hwmark_pl <=0; + Rx_Lwmark_pl <=0; + end + else + begin + Rx_Hwmark_pl <=Rx_Hwmark; + Rx_Lwmark_pl <=Rx_Lwmark; + end + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_ra <=0; + else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl) + Rx_mac_ra <=0; + else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl) + Rx_mac_ra <=1; + + + //control Add_rd signal; + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd <=0; + else if (Current_state_SYS==SYS_read&&!Dout[35]) + Add_rd <=Add_rd + 1; + + // + always @ (posedge Reset or posedge Clk_SYS) + if (Reset) + Add_rd_gray <=0; + else + begin + Add_rd_gray[MAC_RX_FF_DEPTH-1] <=Add_rd[MAC_RX_FF_DEPTH-1]; + for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i]; + end + // + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_gray_dl1 <=0; + else + Add_wr_gray_dl1 <=Add_wr_gray; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_jump_rd_pl1 <=0; + else + Add_wr_jump_rd_pl1 <=Add_wr_jump; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr_ungray =0; + else if (!Add_wr_jump_rd_pl1) + begin + Add_wr_ungray[MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[MAC_RX_FF_DEPTH-1]; + for (i=MAC_RX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; + end + //empty signal gen + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Empty <=1; + else if (Add_rd==Add_wr_ungray) + Empty <=1; + else + Empty <=0; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Dout_dl1 <=0; + else + Dout_dl1 <=Dout; + + assign Rx_mac_data =Dout_dl1[31:0]; + assign Rx_mac_BE =Dout_dl1[33:32]; + assign Rx_mac_eop =Dout_dl1[35]; + + //aligned to Addr_rd + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_pa_tmp <=0; + else if (Current_state_SYS==SYS_read&&!Dout[35]) + Rx_mac_pa_tmp <=1; + else + Rx_mac_pa_tmp <=0; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_pa <=0; + else + Rx_mac_pa <=Rx_mac_pa_tmp; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Rx_mac_sop_tmp <=0; + else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read) + Rx_mac_sop_tmp <=1; + else + Rx_mac_sop_tmp <=0; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Rx_mac_sop_tmp_dl1 <=0; + Rx_mac_sop <=0; + end + else + begin + Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp; + Rx_mac_sop <=Rx_mac_sop_tmp_dl1; + end + + //****************************************************************************** + + duram #(36,MAC_RX_FF_DEPTH) + U_duram(.data_a (Din ), + .wren_a (Wr_en ), + .address_a (Add_wr ), + .address_b (Add_rd ), + .clock_a (Clk_MAC ), + .clock_b (Clk_SYS ), + .q_b (Dout )); + +endmodule // MAC_rx_FF diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_add_chk.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_add_chk.v new file mode 100644 index 00000000..1019779e --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_add_chk.v @@ -0,0 +1,156 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_add_chk.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_rx_add_chk.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_add_chk ( +Reset , +Clk , +Init , +data , +MAC_add_en , +MAC_rx_add_chk_err , +//From CPU +MAC_rx_add_chk_en , +MAC_add_prom_data , +MAC_add_prom_add , +MAC_add_prom_wr + +); +input Reset ; +input Clk ; +input Init ; +input [7:0] data ; +input MAC_add_en ; +output MAC_rx_add_chk_err ; + //From CPU +input MAC_rx_add_chk_en ; +input [7:0] MAC_add_prom_data ; +input [2:0] MAC_add_prom_add ; +input MAC_add_prom_wr ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [2:0] addr_rd; +wire[2:0] addr_wr; +wire[7:0] din; +wire[7:0] dout; +wire wr_en; + +reg MAC_rx_add_chk_err; +reg MAC_add_prom_wr_dl1; +reg MAC_add_prom_wr_dl2; +reg [7:0] data_dl1 ; +reg MAC_add_en_dl1 ; +//****************************************************************************** +//write data from cpu to prom +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + data_dl1 <=0; + MAC_add_en_dl1 <=0; + end + else + begin + data_dl1 <=data; + MAC_add_en_dl1 <=MAC_add_en; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + MAC_add_prom_wr_dl1 <=0; + MAC_add_prom_wr_dl2 <=0; + end + else + begin + MAC_add_prom_wr_dl1 <=MAC_add_prom_wr; + MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1; + end + +assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2; +assign addr_wr =MAC_add_prom_add; +assign din =MAC_add_prom_data; + +//****************************************************************************** +//mac add verify +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + addr_rd <=0; + else if (Init) + addr_rd <=0; + else if (MAC_add_en) + addr_rd <=addr_rd + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_rx_add_chk_err <=0; + else if (Init) + MAC_rx_add_chk_err <=0; + else if (MAC_rx_add_chk_en&&MAC_add_en_dl1&&dout!=data_dl1) + MAC_rx_add_chk_err <=1; + + +//****************************************************************************** +//a port for read ,b port for write . +//****************************************************************************** +duram #(8,3,"M512","DUAL_PORT") U_duram( +.data_a (din ), +.wren_a (wr_en ), +.address_a (addr_wr ), +.address_b (addr_rd ), +.clock_a (Clk ), +.clock_b (Clk ), +.q_b (dout )); + +endmodule diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_ctrl.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_ctrl.v new file mode 100644 index 00000000..24701498 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_rx/MAC_rx_ctrl.v @@ -0,0 +1,536 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_rx_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_rx_ctrl.v,v $ +// Revision 1.4 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:37 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_rx_ctrl ( +Reset , +Clk , +//RMII interface +MCrs_dv , // +MRxD , // +MRxErr , // +//CRC_chk interface +CRC_en , +CRC_init , +CRC_err , +//MAC_rx_add_chk interface +MAC_add_en , +MAC_rx_add_chk_err , +//broadcast_filter +broadcast_ptr , +broadcast_drop , +//flow_control signals +pause_quanta , +pause_quanta_val , +//MAC_rx_FF interface +Fifo_data , +Fifo_data_en , +Fifo_data_err , +Fifo_data_end , +Fifo_full , +//RMON interface +Rx_pkt_type_rmon , +Rx_pkt_length_rmon , +Rx_apply_rmon , +Rx_pkt_err_type_rmon , +//CPU +RX_IFG_SET , +RX_MAX_LENGTH, +RX_MIN_LENGTH +); + +input Reset ; +input Clk ; + //RMII interface +input MCrs_dv ; +input [7:0] MRxD ; +input MRxErr ; + //CRC_chk interface +output CRC_en ; +output CRC_init; +input CRC_err ; + //MAC_rx_add_chk interface +output MAC_add_en ; +input MAC_rx_add_chk_err ; + //broadcast_filter +output broadcast_ptr ; +input broadcast_drop ; + //flow_control signals +output [15:0] pause_quanta ; +output pause_quanta_val ; + //MAC_rx_FF interface +output [7:0] Fifo_data ; +output Fifo_data_en ; +output Fifo_data_err ; +output Fifo_data_end ; +input Fifo_full; + //RMON interface +output [15:0] Rx_pkt_length_rmon ; +output Rx_apply_rmon ; +output [2:0] Rx_pkt_err_type_rmon ; +output [2:0] Rx_pkt_type_rmon ; + //CPU +input [5:0] RX_IFG_SET ; +input [15:0] RX_MAX_LENGTH ;// 1518 +input [6:0] RX_MIN_LENGTH ;// 64 + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter State_idle =4'd00; +parameter State_preamble =4'd01; +parameter State_SFD =4'd02; +parameter State_data =4'd03; +parameter State_checkCRC =4'd04; +parameter State_OkEnd =4'd07; +parameter State_drop =4'd08; +parameter State_ErrEnd =4'd09; +parameter State_CRCErrEnd =4'd10; +parameter State_FFFullDrop =4'd11; +parameter State_FFFullErrEnd =4'd12; +parameter State_IFG =4'd13; + +parameter Pause_idle =4'd0; +parameter Pause_pre_syn =4'd1; +parameter Pause_quanta_hi =4'd2; +parameter Pause_quanta_lo =4'd3; +parameter Pause_syn =4'd4; + +reg [3:0] Current_state /* synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [3:0] Pause_current /* synthesis syn_keep=1 */; +reg [3:0] Pause_next; +reg [5:0] IFG_counter; +reg Crs_dv ; +reg [7:0] RxD ; +reg [7:0] RxD_dl1 ; +reg RxErr ; +reg [15:0] Frame_length_counter; +reg Too_long; +reg Too_short; +reg Fifo_data_en; +reg Fifo_data_end; +reg Fifo_data_err; +reg CRC_en; +reg CRC_init; +reg Rx_apply_rmon; +reg Rx_apply_rmon_tmp; +reg Rx_apply_rmon_tmp_pl1; +reg [2:0] Rx_pkt_err_type_rmon; +reg MAC_add_en; +reg [2:0] Rx_pkt_type_rmon; +reg [7:0] pause_quanta_h ; +reg [15:0] pause_quanta ; +reg pause_quanta_val ; +reg pause_quanta_val_tmp; +reg pause_frame_ptr ; +reg broadcast_ptr ; +//****************************************************************************** +//delay signals +//****************************************************************************** + +always @ (posedge Reset or posedge Clk) + if (Reset) + begin + Crs_dv <=0; + RxD <=0; + RxErr <=0; + end + else + begin + Crs_dv <=MCrs_dv ; + RxD <=MRxD ; + RxErr <=MRxErr ; + end + +always @ (posedge Reset or posedge Clk) + if (Reset) + RxD_dl1 <=0; + else + RxD_dl1 <=RxD; + +//****************************************************************************** +//State_machine +//****************************************************************************** + +always @ (posedge Reset or posedge Clk) + if (Reset) + Current_state <=State_idle; + else + Current_state <=Next_state; + +always @ (*) + case (Current_state) + State_idle: + if (Crs_dv&&RxD==8'h55) + Next_state =State_preamble; + else + Next_state =Current_state; + State_preamble: + if (!Crs_dv) + Next_state =State_ErrEnd; + else if (RxErr) + Next_state =State_drop; + else if (RxD==8'hd5) + Next_state =State_SFD; + else if (RxD==8'h55) + Next_state =Current_state; + else + Next_state =State_drop; + State_SFD: + if (!Crs_dv) + Next_state =State_ErrEnd; + else if (RxErr) + Next_state =State_drop; + else + Next_state =State_data; + State_data: + if (!Crs_dv&&!Too_short&&!Too_long) + Next_state =State_checkCRC; + else if (!Crs_dv&&(Too_short||Too_long)) + Next_state =State_ErrEnd; + else if (Fifo_full) + Next_state =State_FFFullErrEnd; + else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop) + Next_state =State_drop; + else + Next_state =State_data; + State_checkCRC: + if (CRC_err) + Next_state =State_CRCErrEnd; + else + Next_state =State_OkEnd; + State_drop: + if (!Crs_dv) + Next_state =State_ErrEnd; + else + Next_state =Current_state; + State_OkEnd: + Next_state =State_IFG; + State_ErrEnd: + Next_state =State_IFG; + + State_CRCErrEnd: + Next_state =State_IFG; + State_FFFullDrop: + if (!Crs_dv) + Next_state =State_IFG; + else + Next_state =Current_state; + State_FFFullErrEnd: + Next_state =State_FFFullDrop; + State_IFG: + if (IFG_counter==RX_IFG_SET-4) //remove some additional time + Next_state =State_idle; + else + Next_state =Current_state; + + default: + Next_state =State_idle; + endcase + + +always @ (posedge Reset or posedge Clk) + if (Reset) + IFG_counter <=0; + else if (Current_state!=State_IFG) + IFG_counter <=0; + else + IFG_counter <=IFG_counter + 1; +//****************************************************************************** +//gen fifo interface signals +//****************************************************************************** + +assign Fifo_data =RxD_dl1; + +always @(Current_state) + if (Current_state==State_data) + Fifo_data_en =1; + else + Fifo_data_en =0; + +always @(Current_state) + if (Current_state==State_ErrEnd||Current_state==State_OkEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Fifo_data_end =1; + else + Fifo_data_end =0; + +always @(Current_state) + if (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Fifo_data_err =1; + else + Fifo_data_err =0; + +//****************************************************************************** +//CRC_chk interface +//****************************************************************************** + +always @(Current_state) + if (Current_state==State_data) + CRC_en =1; + else + CRC_en =0; + +always @(Current_state) + if (Current_state==State_SFD) + CRC_init =1; + else + CRC_init =0; + +//****************************************************************************** +//gen rmon signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Frame_length_counter <=0; + else if (Current_state==State_SFD) + Frame_length_counter <=1; + else if (Current_state==State_data) + Frame_length_counter <=Frame_length_counter+ 1'b1; + +always @ (Frame_length_counter or RX_MIN_LENGTH) + if (Frame_length_counterRX_MAX_LENGTH) + Too_long =1; + else + Too_long =0; + +assign Rx_pkt_length_rmon=Frame_length_counter-1'b1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon_tmp <=0; + else if (Current_state==State_OkEnd||Current_state==State_ErrEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Rx_apply_rmon_tmp <=1; + else + Rx_apply_rmon_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon_tmp_pl1 <=0; + else + Rx_apply_rmon_tmp_pl1 <=Rx_apply_rmon_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_apply_rmon <=0; + else if (Current_state==State_OkEnd||Current_state==State_ErrEnd + ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd) + Rx_apply_rmon <=1; + else if (Rx_apply_rmon_tmp_pl1) + Rx_apply_rmon <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_err_type_rmon <=0; + else if (Current_state==State_CRCErrEnd) + Rx_pkt_err_type_rmon <=3'b001 ;// + else if (Current_state==State_FFFullErrEnd) + Rx_pkt_err_type_rmon <=3'b010 ;// + else if (Current_state==State_ErrEnd) + Rx_pkt_err_type_rmon <=3'b011 ;// + else if(Current_state==State_OkEnd) + Rx_pkt_err_type_rmon <=3'b100 ; + + + +always @ (posedge Clk or posedge Reset) + if (Reset) + Rx_pkt_type_rmon <=0; + else if (Current_state==State_OkEnd&&pause_frame_ptr) + Rx_pkt_type_rmon <=3'b100 ;// + else if(Current_state==State_SFD&&Next_state==State_data) + Rx_pkt_type_rmon <={1'b0,MRxD[7:6]}; + +always @ (posedge Clk or posedge Reset) + if (Reset) + broadcast_ptr <=0; + else if(Current_state==State_IFG) + broadcast_ptr <=0; + else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11) + broadcast_ptr <=1; + + + +//****************************************************************************** +//MAC add checker signals +//****************************************************************************** +always @ (Frame_length_counter or Fifo_data_en) + if(Frame_length_counter>=1&&Frame_length_counter<=6) + MAC_add_en <=Fifo_data_en; + else + MAC_add_en <=0; + +//****************************************************************************** +//flow control signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Pause_current <=Pause_idle; + else + Pause_current <=Pause_next; + +always @ (*) + case (Pause_current) + Pause_idle : + if(Current_state==State_SFD) + Pause_next =Pause_pre_syn; + else + Pause_next =Pause_current; + Pause_pre_syn: + case (Frame_length_counter) + 16'd1: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd2: if (RxD_dl1==8'h80) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd3: if (RxD_dl1==8'hc2) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd4: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd5: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd6: if (RxD_dl1==8'h01) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd13: if (RxD_dl1==8'h88) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd14: if (RxD_dl1==8'h08) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd15: if (RxD_dl1==8'h00) + Pause_next =Pause_current; + else + Pause_next =Pause_idle; + 16'd16: if (RxD_dl1==8'h01) + Pause_next =Pause_quanta_hi; + else + Pause_next =Pause_idle; + default: Pause_next =Pause_current; + endcase + Pause_quanta_hi : + Pause_next =Pause_quanta_lo; + Pause_quanta_lo : + Pause_next =Pause_syn; + Pause_syn : + if (Current_state==State_IFG) + Pause_next =Pause_idle; + else + Pause_next =Pause_current; + default + Pause_next =Pause_idle; + endcase + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_h <=0; + else if(Pause_current==Pause_quanta_hi) + pause_quanta_h <=RxD_dl1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta <=0; + else if(Pause_current==Pause_quanta_lo) + pause_quanta <={pause_quanta_h,RxD_dl1}; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val_tmp <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn) + pause_quanta_val_tmp <=1; + else + pause_quanta_val_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_val <=0; + else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp) + pause_quanta_val <=1; + else + pause_quanta_val <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_frame_ptr <=0; + else if(Pause_current==Pause_syn) + pause_frame_ptr <=1; + else + pause_frame_ptr <=0; + +endmodule + + \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_top.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_top.v new file mode 100644 index 00000000..c1b21154 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_top.v @@ -0,0 +1,430 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_top.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_top.v,v $ +// Revision 1.3 2006/01/19 14:07:52 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:13 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module MAC_top( + //system signals +input Reset , +input Clk_125M , +input Clk_user , +input Clk_reg , +output [2:0] Speed , + //user interface +output Rx_mac_ra , +input Rx_mac_rd , +output [31:0] Rx_mac_data , +output [1:0] Rx_mac_BE , +output Rx_mac_pa , +output Rx_mac_sop , +output Rx_mac_eop , + //user interface +output Tx_mac_wa , +input Tx_mac_wr , +input [31:0] Tx_mac_data , +input [1:0] Tx_mac_BE ,//big endian +input Tx_mac_sop , +input Tx_mac_eop , + //Phy interface + //Phy interface +output Gtx_clk ,//used only in GMII mode +input Rx_clk , +input Tx_clk ,//used only in MII mode +output Tx_er , +output Tx_en , +output [7:0] Txd , +input Rx_er , +input Rx_dv , +input [7:0] Rxd , +input Crs , +input Col , + //host interface +input CSB , +input WRB , +input [15:0] CD_in , +output [15:0] CD_out , +input [7:0] CA , + //mdx +inout Mdio ,// MII Management Data In +output Mdc // MII Management Data Clock + +); +//****************************************************************************** +//internal signals +//****************************************************************************** + //RMON interface +wire [15:0] Rx_pkt_length_rmon ; +wire Rx_apply_rmon ; +wire [2:0] Rx_pkt_err_type_rmon ; +wire [2:0] Rx_pkt_type_rmon ; +wire [2:0] Tx_pkt_type_rmon ; +wire [15:0] Tx_pkt_length_rmon ; +wire Tx_apply_rmon ; +wire [2:0] Tx_pkt_err_type_rmon ; + //PHY interface +wire MCrs_dv ; +wire [7:0] MRxD ; +wire MRxErr ; + //flow_control signals +wire [15:0] pause_quanta ; +wire pause_quanta_val ; + //PHY interface +wire [7:0] MTxD ; +wire MTxEn ; +wire MCRS ; + //interface clk signals +wire MAC_tx_clk ; +wire MAC_rx_clk ; +wire MAC_tx_clk_div ; +wire MAC_rx_clk_div ; + //reg signals +wire [4:0] Tx_Hwmark ; +wire [4:0] Tx_Lwmark ; +wire pause_frame_send_en ; +wire [15:0] pause_quanta_set ; +wire MAC_tx_add_en ; +wire FullDuplex ; +wire [3:0] MaxRetry ; +wire [5:0] IFGset ; +wire [7:0] MAC_tx_add_prom_data ; +wire [2:0] MAC_tx_add_prom_add ; +wire MAC_tx_add_prom_wr ; +wire tx_pause_en ; +wire xoff_cpu ; +wire xon_cpu ; + //Rx host interface +wire MAC_rx_add_chk_en ; +wire [7:0] MAC_rx_add_prom_data ; +wire [2:0] MAC_rx_add_prom_add ; +wire MAC_rx_add_prom_wr ; +wire broadcast_filter_en ; +wire [15:0] broadcast_MAX ; +wire RX_APPEND_CRC ; +wire [4:0] Rx_Hwmark ; +wire [4:0] Rx_Lwmark ; +wire CRC_chk_en ; +wire [5:0] RX_IFG_SET ; +wire [15:0] RX_MAX_LENGTH ; +wire [6:0] RX_MIN_LENGTH ; + //RMON host interface +wire [5:0] CPU_rd_addr ; +wire CPU_rd_apply ; +wire CPU_rd_grant ; +wire [31:0] CPU_rd_dout ; + //Phy int host interface +wire Line_loop_en ; + //MII to CPU +wire [7:0] Divider ; +wire [15:0] CtrlData ; +wire [4:0] Rgad ; +wire [4:0] Fiad ; +wire NoPre ; +wire WCtrlData ; +wire RStat ; +wire ScanStat ; +wire Busy ; +wire LinkFail ; +wire Nvalid ; +wire [15:0] Prsd ; +wire WCtrlDataStart ; +wire RStatStart ; +wire UpdateMIIRX_DATAReg ; +wire [15:0] broadcast_bucket_depth ; +wire [15:0] broadcast_bucket_interval ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +MAC_rx U_MAC_rx( +.Reset (Reset ), +.Clk_user (Clk_user ), +.Clk (MAC_rx_clk_div ), + //RMII interface (//PHY interface ), +.MCrs_dv (MCrs_dv ), +.MRxD (MRxD ), +.MRxErr (MRxErr ), + //flow_control signals (//flow_control signals ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ), + //user interface (//user interface ), +.Rx_mac_ra (Rx_mac_ra ), +.Rx_mac_rd (Rx_mac_rd ), +.Rx_mac_data (Rx_mac_data ), +.Rx_mac_BE (Rx_mac_BE ), +.Rx_mac_pa (Rx_mac_pa ), +.Rx_mac_sop (Rx_mac_sop ), +.Rx_mac_eop (Rx_mac_eop ), + //CPU (//CPU ), +.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), +.MAC_add_prom_data (MAC_rx_add_prom_data ), +.MAC_add_prom_add (MAC_rx_add_prom_add ), +.MAC_add_prom_wr (MAC_rx_add_prom_wr ), +.broadcast_filter_en (broadcast_filter_en ), +.broadcast_bucket_depth (broadcast_bucket_depth ), +.broadcast_bucket_interval (broadcast_bucket_interval ), +.RX_APPEND_CRC (RX_APPEND_CRC ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.CRC_chk_en (CRC_chk_en ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ), + //RMON interface (//RMON interface ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ) +); + +MAC_tx U_MAC_tx( +.Reset (Reset ), +.Clk (MAC_tx_clk_div ), +.Clk_user (Clk_user ), + //PHY interface (//PHY interface ), +.TxD (MTxD ), +.TxEn (MTxEn ), +.CRS (MCRS ), + //RMON (//RMON ), +.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), +.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), +.Tx_apply_rmon (Tx_apply_rmon ), +.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //user interface (//user interface ), +.Tx_mac_wa (Tx_mac_wa ), +.Tx_mac_wr (Tx_mac_wr ), +.Tx_mac_data (Tx_mac_data ), +.Tx_mac_BE (Tx_mac_BE ), +.Tx_mac_sop (Tx_mac_sop ), +.Tx_mac_eop (Tx_mac_eop ), + //host interface (//host interface ), +.Tx_Hwmark (Tx_Hwmark ), +.Tx_Lwmark (Tx_Lwmark ), +.pause_frame_send_en (pause_frame_send_en ), +.pause_quanta_set (pause_quanta_set ), +.MAC_tx_add_en (MAC_tx_add_en ), +.FullDuplex (FullDuplex ), +.MaxRetry (MaxRetry ), +.IFGset (IFGset ), +.MAC_add_prom_data (MAC_tx_add_prom_data ), +.MAC_add_prom_add (MAC_tx_add_prom_add ), +.MAC_add_prom_wr (MAC_tx_add_prom_wr ), +.tx_pause_en (tx_pause_en ), +.xoff_cpu (xoff_cpu ), +.xon_cpu (xon_cpu ), + //MAC_rx_flow (//MAC_rx_flow ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ) +); + +RMON U_RMON( +.Clk (Clk_reg ), +.Reset (Reset ), + //Tx_RMON (//Tx_RMON ), +.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), +.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), +.Tx_apply_rmon (Tx_apply_rmon ), +.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //Tx_RMON (//Tx_RMON ), +.Rx_pkt_type_rmon (Rx_pkt_type_rmon ), +.Rx_pkt_length_rmon (Rx_pkt_length_rmon ), +.Rx_apply_rmon (Rx_apply_rmon ), +.Rx_pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //CPU (//CPU ), +.CPU_rd_addr (CPU_rd_addr ), +.CPU_rd_apply (CPU_rd_apply ), +.CPU_rd_grant (CPU_rd_grant ), +.CPU_rd_dout (CPU_rd_dout ) +); + +Phy_int U_Phy_int( +.Reset (Reset ), +.MAC_rx_clk (MAC_rx_clk ), +.MAC_tx_clk (MAC_tx_clk ), + //Rx interface (//Rx interface ), +.MCrs_dv (MCrs_dv ), +.MRxD (MRxD ), +.MRxErr (MRxErr ), + //Tx interface (//Tx interface ), +.MTxD (MTxD ), +.MTxEn (MTxEn ), +.MCRS (MCRS ), + //Phy interface (//Phy interface ), +.Tx_er (Tx_er ), +.Tx_en (Tx_en ), +.Txd (Txd ), +.Rx_er (Rx_er ), +.Rx_dv (Rx_dv ), +.Rxd (Rxd ), +.Crs (Crs ), +.Col (Col ), + //host interface (//host interface ), +.Line_loop_en (Line_loop_en ), +.Speed (Speed ) +); + +Clk_ctrl U_Clk_ctrl( +.Reset (Reset ), +.Clk_125M (Clk_125M ), + //host interface (//host interface ), +.Speed (Speed ), + //Phy interface (//Phy interface ), +.Gtx_clk (Gtx_clk ), +.Rx_clk (Rx_clk ), +.Tx_clk (Tx_clk ), + //interface clk (//interface clk ), +.MAC_tx_clk (MAC_tx_clk ), +.MAC_rx_clk (MAC_rx_clk ), +.MAC_tx_clk_div (MAC_tx_clk_div ), +.MAC_rx_clk_div (MAC_rx_clk_div ) +); + +eth_miim U_eth_miim( +.Clk (Clk_reg ), +.Reset (Reset ), +.Divider (Divider ), +.NoPre (NoPre ), +.CtrlData (CtrlData ), +.Rgad (Rgad ), +.Fiad (Fiad ), +.WCtrlData (WCtrlData ), +.RStat (RStat ), +.ScanStat (ScanStat ), +.Mdio (Mdio ), +.Mdc (Mdc ), +.Busy (Busy ), +.Prsd (Prsd ), +.LinkFail (LinkFail ), +.Nvalid (Nvalid ), +.WCtrlDataStart (WCtrlDataStart ), +.RStatStart (RStatStart ), +.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg )); + +reg_int U_reg_int( +.Reset (Reset ), +.Clk_reg (Clk_reg ), +.CSB (CSB ), +.WRB (WRB ), +.CD_in (CD_in ), +.CD_out (CD_out ), +.CA (CA ), + //Tx host interface (//Tx host interface ), +.Tx_Hwmark (Tx_Hwmark ), +.Tx_Lwmark (Tx_Lwmark ), +.pause_frame_send_en (pause_frame_send_en ), +.pause_quanta_set (pause_quanta_set ), +.MAC_tx_add_en (MAC_tx_add_en ), +.FullDuplex (FullDuplex ), +.MaxRetry (MaxRetry ), +.IFGset (IFGset ), +.MAC_tx_add_prom_data (MAC_tx_add_prom_data ), +.MAC_tx_add_prom_add (MAC_tx_add_prom_add ), +.MAC_tx_add_prom_wr (MAC_tx_add_prom_wr ), +.tx_pause_en (tx_pause_en ), +.xoff_cpu (xoff_cpu ), +.xon_cpu (xon_cpu ), + //Rx host interface (//Rx host interface ), +.MAC_rx_add_chk_en (MAC_rx_add_chk_en ), +.MAC_rx_add_prom_data (MAC_rx_add_prom_data ), +.MAC_rx_add_prom_add (MAC_rx_add_prom_add ), +.MAC_rx_add_prom_wr (MAC_rx_add_prom_wr ), +.broadcast_filter_en (broadcast_filter_en ), +.broadcast_bucket_depth (broadcast_bucket_depth ), +.broadcast_bucket_interval (broadcast_bucket_interval ), +.RX_APPEND_CRC (RX_APPEND_CRC ), +.Rx_Hwmark (Rx_Hwmark ), +.Rx_Lwmark (Rx_Lwmark ), +.CRC_chk_en (CRC_chk_en ), +.RX_IFG_SET (RX_IFG_SET ), +.RX_MAX_LENGTH (RX_MAX_LENGTH ), +.RX_MIN_LENGTH (RX_MIN_LENGTH ), + //RMON host interface (//RMON host interface ), +.CPU_rd_addr (CPU_rd_addr ), +.CPU_rd_apply (CPU_rd_apply ), +.CPU_rd_grant (CPU_rd_grant ), +.CPU_rd_dout (CPU_rd_dout ), + //Phy int host interface (//Phy int host interface ), +.Line_loop_en (Line_loop_en ), +.Speed (Speed ), + //MII to CPU (//MII to CPU ), +.Divider (Divider ), +.CtrlData (CtrlData ), +.Rgad (Rgad ), +.Fiad (Fiad ), +.NoPre (NoPre ), +.WCtrlData (WCtrlData ), +.RStat (RStat ), +.ScanStat (ScanStat ), +.Busy (Busy ), +.LinkFail (LinkFail ), +.Nvalid (Nvalid ), +.Prsd (Prsd ), +.WCtrlDataStart (WCtrlDataStart ), +.RStatStart (RStatStart ), +.UpdateMIIRX_DATAReg (UpdateMIIRX_DATAReg ) +); + +endmodule + + + + + + + + + + + + + + + + + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx.v new file mode 100644 index 00000000..f5e605bc --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx.v @@ -0,0 +1,266 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_tx.v,v $ +// Revision 1.4 2006/11/17 17:53:07 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:14 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// +module MAC_tx( +input Reset , +input Clk , +input Clk_user , + //PHY interface +output [7:0] TxD , +output TxEn , +input CRS , + //RMON +output [2:0] Tx_pkt_type_rmon , +output [15:0] Tx_pkt_length_rmon , +output Tx_apply_rmon , +output [2:0] Tx_pkt_err_type_rmon, + //user interface +output Tx_mac_wa , +input Tx_mac_wr , +input [31:0] Tx_mac_data , +input [1:0] Tx_mac_BE ,//big endian +input Tx_mac_sop , +input Tx_mac_eop , + //host interface +input [4:0] Tx_Hwmark , +input [4:0] Tx_Lwmark , +input pause_frame_send_en , +input [15:0] pause_quanta_set , +input MAC_tx_add_en , +input FullDuplex , +input [3:0] MaxRetry , +input [5:0] IFGset , +input [7:0] MAC_add_prom_data , +input [2:0] MAC_add_prom_add , +input MAC_add_prom_wr , +input tx_pause_en , +input xoff_cpu , +input xon_cpu , + //MAC_rx_flow , +input [15:0] pause_quanta , +input pause_quanta_val +); +//****************************************************************************** +//internal signals +//****************************************************************************** + //CRC_gen Interface +wire CRC_init ; +wire[7:0] Frame_data ; +wire Data_en ; +wire CRC_rd ; +wire CRC_end ; +wire[7:0] CRC_out ; + //Ramdon_gen interface +wire Random_init ; +wire[3:0] RetryCnt ; +wire Random_time_meet ;//levle hight indicate random time passed away + //flow control +wire pause_apply ; +wire pause_quanta_sub ; +wire xoff_gen ; +wire xoff_gen_complete ; +wire xon_gen ; +wire xon_gen_complete ; + //MAC_rx_FF +wire[7:0] Fifo_data ; +wire Fifo_rd ; +wire Fifo_eop ; +wire Fifo_da ; +wire Fifo_rd_finish ; +wire Fifo_rd_retry ; +wire Fifo_ra ; +wire Fifo_data_err_empty ; +wire Fifo_data_err_full ; + //MAC_tx_addr_add +wire MAC_tx_addr_init ; +wire MAC_tx_addr_rd ; +wire[7:0] MAC_tx_addr_data ; + +//****************************************************************************** +//instantiation +//****************************************************************************** +MAC_tx_ctrl U_MAC_tx_ctrl( +.Reset (Reset ), +.Clk (Clk ), + //CRC_gen Interface (//CRC_gen Interface ), +.CRC_init (CRC_init ), +.Frame_data (Frame_data ), +.Data_en (Data_en ), +.CRC_rd (CRC_rd ), +.CRC_end (CRC_end ), +.CRC_out (CRC_out ), + //Random_gen interfac (//Random_gen interfac ), +.Random_init (Random_init ), +.RetryCnt (RetryCnt ), +.Random_time_meet (Random_time_meet ), + //flow control (//flow control ), +.pause_apply (pause_apply ), +.pause_quanta_sub (pause_quanta_sub ), +.xoff_gen (xoff_gen ), +.xoff_gen_complete (xoff_gen_complete ), +.xon_gen (xon_gen ), +.xon_gen_complete (xon_gen_complete ), + //MAC_tx_FF (//MAC_tx_FF ), +.Fifo_data (Fifo_data ), +.Fifo_rd (Fifo_rd ), +.Fifo_eop (Fifo_eop ), +.Fifo_da (Fifo_da ), +.Fifo_rd_finish (Fifo_rd_finish ), +.Fifo_rd_retry (Fifo_rd_retry ), +.Fifo_ra (Fifo_ra ), +.Fifo_data_err_empty (Fifo_data_err_empty ), +.Fifo_data_err_full (Fifo_data_err_full ), + //RMII (//RMII ), +.TxD (TxD ), +.TxEn (TxEn ), +.CRS (CRS ), + //MAC_tx_addr_add (//MAC_tx_addr_add ), +.MAC_tx_addr_rd (MAC_tx_addr_rd ), +.MAC_tx_addr_data (MAC_tx_addr_data ), +.MAC_tx_addr_init (MAC_tx_addr_init ), + //RMON (//RMON ), +.Tx_pkt_type_rmon (Tx_pkt_type_rmon ), +.Tx_pkt_length_rmon (Tx_pkt_length_rmon ), +.Tx_apply_rmon (Tx_apply_rmon ), +.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //CPU (//CPU ), +.pause_frame_send_en (pause_frame_send_en ), +.pause_quanta_set (pause_quanta_set ), +.MAC_tx_add_en (MAC_tx_add_en ), +.FullDuplex (FullDuplex ), +.MaxRetry (MaxRetry ), +.IFGset (IFGset ) +); + +CRC_gen U_CRC_gen( +.Reset (Reset ), +.Clk (Clk ), +.Init (CRC_init ), +.Frame_data (Frame_data ), +.Data_en (Data_en ), +.CRC_rd (CRC_rd ), +.CRC_out (CRC_out ), +.CRC_end (CRC_end ) +); + +flow_ctrl U_flow_ctrl( +.Reset (Reset ), +.Clk (Clk ), + //host processor (//host processor ), +.tx_pause_en (tx_pause_en ), +.xoff_cpu (xoff_cpu ), +.xon_cpu (xon_cpu ), + //MAC_rx_flow (//MAC_rx_flow ), +.pause_quanta (pause_quanta ), +.pause_quanta_val (pause_quanta_val ), + //MAC_tx_ctrl (//MAC_tx_ctrl ), +.pause_apply (pause_apply ), +.pause_quanta_sub (pause_quanta_sub ), +.xoff_gen (xoff_gen ), +.xoff_gen_complete (xoff_gen_complete ), +.xon_gen (xon_gen ), +.xon_gen_complete (xon_gen_complete ) +); + +`ifdef MAC_SOURCE_REPLACE_EN +MAC_tx_addr_add U_MAC_tx_addr_add( +.Reset (Reset ), +.Clk (Clk ), +.MAC_tx_addr_rd (MAC_tx_addr_rd ), +.MAC_tx_addr_init (MAC_tx_addr_init ), +.MAC_tx_addr_data (MAC_tx_addr_data ), + //CPU (//CPU ), +.MAC_add_prom_data (MAC_add_prom_data ), +.MAC_add_prom_add (MAC_add_prom_add ), +.MAC_add_prom_wr (MAC_add_prom_wr ) +); +`else +assign MAC_tx_addr_data=0; +`endif +MAC_tx_FF #(.MAC_TX_FF_DEPTH(9)) + U_MAC_tx_FF(.Reset (Reset ), + .Clk_MAC (Clk ), + .Clk_SYS (Clk_user ), + //MAC_rx_ctrl interf (//MAC_rx_ctrl interf ), + .Fifo_data (Fifo_data ), + .Fifo_rd (Fifo_rd ), + .Fifo_rd_finish (Fifo_rd_finish ), + .Fifo_rd_retry (Fifo_rd_retry ), + .Fifo_eop (Fifo_eop ), + .Fifo_da (Fifo_da ), + .Fifo_ra (Fifo_ra ), + .Fifo_data_err_empty (Fifo_data_err_empty ), + .Fifo_data_err_full (Fifo_data_err_full ), + //user interface (//user interface ), + .Tx_mac_wa (Tx_mac_wa ), + .Tx_mac_wr (Tx_mac_wr ), + .Tx_mac_data (Tx_mac_data ), + .Tx_mac_BE (Tx_mac_BE ), + .Tx_mac_sop (Tx_mac_sop ), + .Tx_mac_eop (Tx_mac_eop ), + //host interface (//host interface ), + .FullDuplex (FullDuplex ), + .Tx_Hwmark (Tx_Hwmark ), + .Tx_Lwmark (Tx_Lwmark ) + ); + +random_gen U_random_gen( +.Reset (Reset ), +.Clk (Clk ), +.Init (Random_init ), +.RetryCnt (RetryCnt ), +.Random_time_meet (Random_time_meet ) +); + +endmodule diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CRC_gen.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CRC_gen.v new file mode 100644 index 00000000..c3b6b080 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CRC_gen.v @@ -0,0 +1,168 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CRC_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: CRC_gen.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module CRC_gen ( +Reset , +Clk , +Init , +Frame_data , +Data_en , +CRC_rd , +CRC_end , +CRC_out + +); +input Reset ; +input Clk ; +input Init ; +input [7:0] Frame_data ; +input Data_en ; +input CRC_rd ; +output [7:0] CRC_out ; +output CRC_end ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [7:0] CRC_out ; +reg [31:0] CRC_reg; +reg CRC_end; +reg [3:0] Counter; +//****************************************************************************** +//****************************************************************************** +//input data width is 8bit, and the first bit is bit[0] +function[31:0] NextCRC; + input[7:0] D; + input[31:0] C; + reg[31:0] NewCRC; + begin + NewCRC[0]=C[24]^C[30]^D[1]^D[7]; + NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7]; + NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]; + NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7]; + NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7]; + NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5]; + NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4]; + NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7]; + NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6]; + NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5]; + NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4]; + NewCRC[20]=C[12]^C[28]^D[3]; + NewCRC[21]=C[13]^C[29]^D[2]; + NewCRC[22]=C[14]^C[24]^D[7]; + NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7]; + NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6]; + NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5]; + NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7]; + NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6]; + NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5]; + NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4]; + NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3]; + NewCRC[31]=C[23]^C[29]^D[2]; + NextCRC=NewCRC; + end + endfunction +//****************************************************************************** + +always @ (posedge Clk or posedge Reset) + if (Reset) + CRC_reg <=32'hffffffff; + else if (Init) + CRC_reg <=32'hffffffff; + else if (Data_en) + CRC_reg <=NextCRC(Frame_data,CRC_reg); + else if (CRC_rd) + CRC_reg <={CRC_reg[23:0],8'hff}; + +always @ (CRC_rd or CRC_reg) + if (CRC_rd) + CRC_out <=~{ + CRC_reg[24], + CRC_reg[25], + CRC_reg[26], + CRC_reg[27], + CRC_reg[28], + CRC_reg[29], + CRC_reg[30], + CRC_reg[31] + }; + else + CRC_out <=0; + +//caculate CRC out length ,4 cycles +//CRC_end aligned to last CRC checksum data +always @(posedge Clk or posedge Reset) + if (Reset) + Counter <=0; + else if (!CRC_rd) + Counter <=0; + else + Counter <=Counter + 1; + +always @ (Counter) + if (Counter==3) + CRC_end=1; + else + CRC_end=0; + +endmodule + + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Entries new file mode 100644 index 00000000..58f964cb --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Entries @@ -0,0 +1,7 @@ +/CRC_gen.v/1.3/Thu Jan 19 14:07:54 2006// +/MAC_tx_addr_add.v/1.3/Thu Jan 19 14:07:54 2006// +/flow_ctrl.v/1.3/Thu Jan 19 14:07:54 2006// +/MAC_tx_FF.v/1.5/Tue May 1 07:35:17 2007// +/MAC_tx_Ctrl.v/1.4/Wed May 2 06:49:15 2007// +/Ramdon_gen.v/1.3/Wed May 2 06:49:15 2007// +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Repository new file mode 100644 index 00000000..3f5abe3c --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/rtl/verilog/MAC_tx diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v new file mode 100644 index 00000000..b13c0662 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_FF.v @@ -0,0 +1,745 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_FF.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_tx_FF.v,v $ +// Revision 1.5 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.4 2006/05/28 05:09:20 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:18 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:39 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_tx_FF + #(parameter MAC_TX_FF_DEPTH = 9) + (Reset , + Clk_MAC , + Clk_SYS , + //MAC_rx_ctrl interface + Fifo_data , + Fifo_rd , + Fifo_rd_finish , + Fifo_rd_retry , + Fifo_eop , + Fifo_da , + Fifo_ra , + Fifo_data_err_empty , + Fifo_data_err_full , + //user interface + Tx_mac_wa , + Tx_mac_wr , + Tx_mac_data , + Tx_mac_BE , + Tx_mac_sop , + Tx_mac_eop , + //host interface + FullDuplex , + Tx_Hwmark , + Tx_Lwmark); + + input Reset ; + input Clk_MAC ; + input Clk_SYS ; + //MAC_tx_ctrl + output [7:0] Fifo_data ; + input Fifo_rd ; + input Fifo_rd_finish ; + input Fifo_rd_retry ; + output Fifo_eop ; + output Fifo_da ; + output Fifo_ra ; + output Fifo_data_err_empty ; + output Fifo_data_err_full ; + //user interface + output Tx_mac_wa ; + input Tx_mac_wr ; + input [31:0] Tx_mac_data ; + input [1:0] Tx_mac_BE ;//big endian + input Tx_mac_sop ; + input Tx_mac_eop ; + //host interface + input FullDuplex ; + input [4:0] Tx_Hwmark ; + input [4:0] Tx_Lwmark ; + // ****************************************************************************** + //internal signals + // ****************************************************************************** + parameter MAC_byte3 =4'd00; + parameter MAC_byte2 =4'd01; + parameter MAC_byte1 =4'd02; + parameter MAC_byte0 =4'd03; + parameter MAC_wait_finish =4'd04; + parameter MAC_retry =4'd08; + parameter MAC_idle =4'd09; + parameter MAC_FFEmpty =4'd10; + parameter MAC_FFEmpty_drop =4'd11; + parameter MAC_pkt_sub =4'd12; + parameter MAC_FF_Err =4'd13; + + reg [3:0] Current_state_MAC /* synthesis syn_preserve =1 */ ; + reg [3:0] Current_state_MAC_reg /* synthesis syn_preserve =1 */ ; + reg [3:0] Next_state_MAC ; + + parameter SYS_idle =4'd0; + parameter SYS_WaitSop =4'd1; + parameter SYS_SOP =4'd2; + parameter SYS_MOP =4'd3; + parameter SYS_DROP =4'd4; + parameter SYS_EOP_ok =4'd5; + parameter SYS_FFEmpty =4'd6; + parameter SYS_EOP_err =4'd7; + parameter SYS_SOP_err =4'd8; + + reg [3:0] Current_state_SYS /* synthesis syn_preserve =1 */; + reg [3:0] Next_state_SYS; + + reg [MAC_TX_FF_DEPTH-1:0] Add_wr ; + reg [MAC_TX_FF_DEPTH-1:0] Add_wr_ungray ; + reg [MAC_TX_FF_DEPTH-1:0] Add_wr_gray ; + reg [MAC_TX_FF_DEPTH-1:0] Add_wr_gray_dl1 ; + wire [MAC_TX_FF_DEPTH-1:0] Add_wr_gray_tmp ; + + reg [MAC_TX_FF_DEPTH-1:0] Add_rd ; + reg [MAC_TX_FF_DEPTH-1:0] Add_rd_reg ; + reg [MAC_TX_FF_DEPTH-1:0] Add_rd_gray ; + reg [MAC_TX_FF_DEPTH-1:0] Add_rd_gray_dl1 ; + wire [MAC_TX_FF_DEPTH-1:0] Add_rd_gray_tmp ; + reg [MAC_TX_FF_DEPTH-1:0] Add_rd_ungray ; + wire [35:0] Din ; + wire [35:0] Dout ; + reg Wr_en ; + wire [MAC_TX_FF_DEPTH-1:0] Add_wr_pluse ; + wire [MAC_TX_FF_DEPTH-1:0] Add_wr_pluse_pluse; + wire [MAC_TX_FF_DEPTH-1:0] Add_rd_pluse ; + reg [MAC_TX_FF_DEPTH-1:0] Add_rd_reg_dl1 ; + reg Full /* synthesis syn_keep=1 */; + reg AlmostFull /* synthesis syn_keep=1 */; + reg Empty /* synthesis syn_keep=1 */; + + reg Tx_mac_wa ; + reg Tx_mac_wr_dl1 ; + reg [31:0] Tx_mac_data_dl1 ; + reg [1:0] Tx_mac_BE_dl1 ; + reg Tx_mac_sop_dl1 ; + reg Tx_mac_eop_dl1 ; + reg FF_FullErr ; + wire [1:0] Dout_BE ; + wire Dout_eop ; + wire Dout_err ; + wire [31:0] Dout_data ; + reg [35:0] Dout_reg /* synthesis syn_preserve=1 */; + reg Packet_number_sub_dl1 ; + reg Packet_number_sub_dl2 ; + reg Packet_number_sub_edge /* synthesis syn_preserve=1 */; + reg Packet_number_add /* synthesis syn_preserve=1 */; + reg [4:0] Fifo_data_count ; + reg Fifo_ra /* synthesis syn_keep=1 */; + reg [7:0] Fifo_data ; + reg Fifo_da ; + reg Fifo_data_err_empty /* synthesis syn_preserve=1 */; + reg Fifo_eop ; + reg Fifo_rd_dl1 ; + reg Fifo_ra_tmp ; + reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */; + reg [5:0] Packet_number_inFF_reg /* synthesis syn_preserve=1 */; + reg Pkt_sub_apply_tmp ; + reg Pkt_sub_apply ; + reg Add_rd_reg_rdy_tmp ; + reg Add_rd_reg_rdy ; + reg Add_rd_reg_rdy_dl1 ; + reg Add_rd_reg_rdy_dl2 ; + reg [4:0] Tx_Hwmark_pl ; + reg [4:0] Tx_Lwmark_pl ; + reg Add_rd_jump_tmp ; + reg Add_rd_jump_tmp_pl1 ; + reg Add_rd_jump ; + reg Add_rd_jump_wr_pl1 ; + + integer i ; + + // ****************************************************************************** + //write data to from FF . + //domain Clk_SYS + // ****************************************************************************** + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Current_state_SYS <=SYS_idle; + else + Current_state_SYS <=Next_state_SYS; + + always @ (Current_state_SYS or Tx_mac_wr or Tx_mac_sop or Full or AlmostFull + or Tx_mac_eop ) + case (Current_state_SYS) + SYS_idle: + if (Tx_mac_wr&&Tx_mac_sop&&!Full) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =Current_state_SYS ; + SYS_SOP: + Next_state_SYS =SYS_MOP; + SYS_MOP: + if (AlmostFull) + Next_state_SYS =SYS_DROP; + else if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP_err; + else if (Tx_mac_wr&&Tx_mac_eop) + Next_state_SYS =SYS_EOP_ok; + else + Next_state_SYS =Current_state_SYS ; + SYS_EOP_ok: + if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =SYS_idle; + SYS_EOP_err: + if (Tx_mac_wr&&Tx_mac_sop) + Next_state_SYS =SYS_SOP; + else + Next_state_SYS =SYS_idle; + SYS_SOP_err: + Next_state_SYS =SYS_DROP; + SYS_DROP: //FIFO overflow + if (Tx_mac_wr&&Tx_mac_eop) + Next_state_SYS =SYS_EOP_err; + else + Next_state_SYS =Current_state_SYS ; + default: + Next_state_SYS =SYS_idle; + endcase + + //delay signals + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Tx_mac_wr_dl1 <=0; + Tx_mac_data_dl1 <=0; + Tx_mac_BE_dl1 <=0; + Tx_mac_sop_dl1 <=0; + Tx_mac_eop_dl1 <=0; + end + else + begin + Tx_mac_wr_dl1 <=Tx_mac_wr ; + Tx_mac_data_dl1 <=Tx_mac_data ; + Tx_mac_BE_dl1 <=Tx_mac_BE ; + Tx_mac_sop_dl1 <=Tx_mac_sop ; + Tx_mac_eop_dl1 <=Tx_mac_eop ; + end + + always @(Current_state_SYS) + if (Current_state_SYS==SYS_EOP_err) + FF_FullErr =1; + else + FF_FullErr =0; + + reg Tx_mac_eop_gen; + + always @(Current_state_SYS) + if (Current_state_SYS==SYS_EOP_err||Current_state_SYS==SYS_EOP_ok) + Tx_mac_eop_gen =1; + else + Tx_mac_eop_gen =0; + + assign Din={Tx_mac_eop_gen,FF_FullErr,Tx_mac_BE_dl1,Tx_mac_data_dl1}; + + always @(Current_state_SYS or Tx_mac_wr_dl1) + if ((Current_state_SYS==SYS_SOP||Current_state_SYS==SYS_EOP_ok|| + Current_state_SYS==SYS_MOP||Current_state_SYS==SYS_EOP_err)&&Tx_mac_wr_dl1) + Wr_en = 1; + else + Wr_en = 0; + + + always @ (posedge Reset or posedge Clk_SYS) + if (Reset) + Add_wr_gray <=0; + else + begin + Add_wr_gray[MAC_TX_FF_DEPTH-1] <=Add_wr[MAC_TX_FF_DEPTH-1]; + for (i=MAC_TX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i]; + end + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_gray_dl1 <=0; + else + Add_rd_gray_dl1 <=Add_rd_gray; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_jump_wr_pl1 <=0; + else + Add_rd_jump_wr_pl1 <=Add_rd_jump; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_ungray =0; + else if (!Add_rd_jump_wr_pl1) + begin + Add_rd_ungray[MAC_TX_FF_DEPTH-1] =Add_rd_gray_dl1[MAC_TX_FF_DEPTH-1]; + for (i=MAC_TX_FF_DEPTH-2;i>=0;i=i-1) + Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i]; + end + assign Add_wr_pluse =Add_wr+1; + assign Add_wr_pluse_pluse =Add_wr+4; + + always @ (Add_wr_pluse or Add_rd_ungray) + if (Add_wr_pluse==Add_rd_ungray) + Full =1; + else + Full =0; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + AlmostFull <=0; + else if (Add_wr_pluse_pluse==Add_rd_ungray) + AlmostFull <=1; + else + AlmostFull <=0; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_wr <= 0; + else if (Wr_en&&!Full) + Add_wr <= Add_wr +1; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Packet_number_sub_dl1 <=0; + Packet_number_sub_dl2 <=0; + end + else + begin + Packet_number_sub_dl1 <=Pkt_sub_apply; + Packet_number_sub_dl2 <=Packet_number_sub_dl1; + end + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_sub_edge <=0; + else if (Packet_number_sub_dl1&!Packet_number_sub_dl2) + Packet_number_sub_edge <=1; + else + Packet_number_sub_edge <=0; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_add <=0; + else if (Current_state_SYS==SYS_EOP_ok||Current_state_SYS==SYS_EOP_err) + Packet_number_add <=1; + else + Packet_number_add <=0; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF <=0; + else if (Packet_number_add&&!Packet_number_sub_edge) + Packet_number_inFF <=Packet_number_inFF + 1'b1; + else if (!Packet_number_add&&Packet_number_sub_edge) + Packet_number_inFF <=Packet_number_inFF - 1'b1; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Packet_number_inFF_reg <=0; + else + Packet_number_inFF_reg <=Packet_number_inFF; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Add_rd_reg_rdy_dl1 <=0; + Add_rd_reg_rdy_dl2 <=0; + end + else + begin + Add_rd_reg_rdy_dl1 <=Add_rd_reg_rdy; + Add_rd_reg_rdy_dl2 <=Add_rd_reg_rdy_dl1; + end + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Add_rd_reg_dl1 <=0; + else if (Add_rd_reg_rdy_dl1&!Add_rd_reg_rdy_dl2) + Add_rd_reg_dl1 <=Add_rd_reg; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_data_count <=0; + else if (FullDuplex) + Fifo_data_count <=Add_wr[MAC_TX_FF_DEPTH-1:MAC_TX_FF_DEPTH-5]-Add_rd_ungray[MAC_TX_FF_DEPTH-1:MAC_TX_FF_DEPTH-5]; + else + Fifo_data_count <=Add_wr[MAC_TX_FF_DEPTH-1:MAC_TX_FF_DEPTH-5]-Add_rd_reg_dl1[MAC_TX_FF_DEPTH-1:MAC_TX_FF_DEPTH-5]; //for half duplex backoff requirement + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Fifo_ra_tmp <=0; + else if (Packet_number_inFF_reg>=1||Fifo_data_count>=Tx_Lwmark) + Fifo_ra_tmp <=1; + else + Fifo_ra_tmp <=0; + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + begin + Tx_Hwmark_pl <=0; + Tx_Lwmark_pl <=0; + end + else + begin + Tx_Hwmark_pl <=Tx_Hwmark; + Tx_Lwmark_pl <=Tx_Lwmark; + end + + always @ (posedge Clk_SYS or posedge Reset) + if (Reset) + Tx_mac_wa <=0; + else if (Fifo_data_count>=Tx_Hwmark_pl) + Tx_mac_wa <=0; + else if (Fifo_data_count=0;i=i-1) + Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i]; + end + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_gray_dl1 <=0; + else + Add_wr_gray_dl1 <=Add_wr_gray; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_wr_ungray =0; + else + begin + Add_wr_ungray[MAC_TX_FF_DEPTH-1] =Add_wr_gray_dl1[MAC_TX_FF_DEPTH-1]; + for (i=MAC_TX_FF_DEPTH-2;i>=0;i=i-1) + Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i]; + end + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Empty <=1; + else if (Add_rd==Add_wr_ungray) + Empty <=1; + else + Empty <=0; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_ra <=0; + else + Fifo_ra <=Fifo_ra_tmp; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Pkt_sub_apply_tmp <=0; + else if (Current_state_MAC==MAC_pkt_sub) + Pkt_sub_apply_tmp <=1; + else + Pkt_sub_apply_tmp <=0; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Pkt_sub_apply <=0; + else if ((Current_state_MAC==MAC_pkt_sub)||Pkt_sub_apply_tmp) + Pkt_sub_apply <=1; + else + Pkt_sub_apply <=0; + + //reg Add_rd for collison retry + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg <=0; + else if (Fifo_rd_finish) + Add_rd_reg <=Add_rd; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg_rdy_tmp <=0; + else if (Fifo_rd_finish) + Add_rd_reg_rdy_tmp <=1; + else + Add_rd_reg_rdy_tmp <=0; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_reg_rdy <=0; + else if (Fifo_rd_finish||Add_rd_reg_rdy_tmp) + Add_rd_reg_rdy <=1; + else + Add_rd_reg_rdy <=0; + + reg Add_rd_add /* synthesis syn_keep=1 */; + + always @ (Current_state_MAC or Next_state_MAC) + if ((Current_state_MAC==MAC_idle||Current_state_MAC==MAC_byte0)&&Next_state_MAC==MAC_byte3) + Add_rd_add =1; + else + Add_rd_add =0; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd <= Add_rd_reg; + else if (Add_rd_add) + Add_rd <= Add_rd + 1; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump_tmp <=1; + else + Add_rd_jump_tmp <=0; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump_tmp_pl1 <=0; + else + Add_rd_jump_tmp_pl1 <=Add_rd_jump_tmp; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Add_rd_jump <=0; + else if (Current_state_MAC==MAC_retry) + Add_rd_jump <=1; + else if (Add_rd_jump_tmp_pl1) + Add_rd_jump <=0; + + //gen Fifo_data + always @ (Dout_data or Current_state_MAC) + case (Current_state_MAC) + MAC_byte3: + Fifo_data =Dout_data[31:24]; + MAC_byte2: + Fifo_data =Dout_data[23:16]; + MAC_byte1: + Fifo_data =Dout_data[15:8]; + MAC_byte0: + Fifo_data =Dout_data[7:0]; + default: + Fifo_data =0; + endcase + + //gen Fifo_da + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_rd_dl1 <=0; + else + Fifo_rd_dl1 <=Fifo_rd; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_da <=0; + else if ((Current_state_MAC==MAC_byte0||Current_state_MAC==MAC_byte1|| + Current_state_MAC==MAC_byte2||Current_state_MAC==MAC_byte3)&&Fifo_rd&&!Fifo_eop) + Fifo_da <=1; + else + Fifo_da <=0; + + //gen Fifo_data_err_empty + assign Fifo_data_err_full=Dout_err; + //gen Fifo_data_err_empty + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Current_state_MAC_reg <=0; + else + Current_state_MAC_reg <=Current_state_MAC; + + always @ (posedge Clk_MAC or posedge Reset) + if (Reset) + Fifo_data_err_empty <=0; + else if (Current_state_MAC_reg==MAC_FFEmpty) + Fifo_data_err_empty <=1; + else + Fifo_data_err_empty <=0; + + always @ (posedge Clk_MAC) + if (Current_state_MAC_reg==MAC_FF_Err) + begin + $finish(2); + $display("mac_tx_FF meet error status at time :%t",$time); + end + + //gen Fifo_eop aligned to last valid data byte¡£ + always @ (Current_state_MAC or Dout_eop) + if (((Current_state_MAC==MAC_byte0&&Dout_BE==2'b00|| + Current_state_MAC==MAC_byte1&&Dout_BE==2'b11|| + Current_state_MAC==MAC_byte2&&Dout_BE==2'b10|| + Current_state_MAC==MAC_byte3&&Dout_BE==2'b01)&&Dout_eop)) + Fifo_eop =1; + else + Fifo_eop =0; + //****************************************************************************** + duram #(36,MAC_TX_FF_DEPTH) + U_duram(.data_a (Din ), + .wren_a (Wr_en ), + .address_a (Add_wr ), + .address_b (Add_rd ), + .clock_a (Clk_SYS ), + .clock_b (Clk_MAC ), + .q_b (Dout )); + +endmodule // MAC_tx_FF diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_addr_add.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_addr_add.v new file mode 100644 index 00000000..fa6cd4c2 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_addr_add.v @@ -0,0 +1,128 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_addr_add.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_tx_addr_add.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:18 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_tx_addr_add ( +Reset , +Clk , +MAC_tx_addr_init , +MAC_tx_addr_rd , +MAC_tx_addr_data , +//CPU , +MAC_add_prom_data , +MAC_add_prom_add , +MAC_add_prom_wr +); + +input Reset ; +input Clk ; +input MAC_tx_addr_rd ; +input MAC_tx_addr_init ; +output [7:0] MAC_tx_addr_data ; + //CPU ; +input [7:0] MAC_add_prom_data ; +input [2:0] MAC_add_prom_add ; +input MAC_add_prom_wr ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [2:0] add_rd; +wire[2:0] add_wr; +wire[7:0] din; +wire[7:0] dout; +wire wr_en; +reg MAC_add_prom_wr_dl1; +reg MAC_add_prom_wr_dl2; +//****************************************************************************** +//write data from cpu to prom +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + MAC_add_prom_wr_dl1 <=0; + MAC_add_prom_wr_dl2 <=0; + end + else + begin + MAC_add_prom_wr_dl1 <=MAC_add_prom_wr; + MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1; + end +assign # 2 wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2; +assign # 2 add_wr =MAC_add_prom_add; +assign # 2 din =MAC_add_prom_data; + +//****************************************************************************** +//read data from cpu to prom +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + add_rd <=0; + else if (MAC_tx_addr_init) + add_rd <=0; + else if (MAC_tx_addr_rd) + add_rd <=add_rd + 1; +assign MAC_tx_addr_data=dout; +//****************************************************************************** +//b port for read ,a port for write . +//****************************************************************************** +duram #(8,3,"M512","DUAL_PORT") U_duram( +.data_a (din ), +.wren_a (wr_en ), +.address_a (add_wr ), +.address_b (add_rd ), +.clock_a (Clk ), +.clock_b (Clk ), +.q_b (dout )); + + +endmodule + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_ctrl.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_ctrl.v new file mode 100644 index 00000000..5412bd13 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/MAC_tx_ctrl.v @@ -0,0 +1,646 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// MAC_tx_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: MAC_tx_Ctrl.v,v $ +// Revision 1.4 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:17 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:38 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module MAC_tx_ctrl ( +Reset , +Clk , +//CRC_gen Interface +CRC_init , +Frame_data , +Data_en , +CRC_rd , +CRC_end , +CRC_out , +//Ramdon_gen interfac +Random_init , +RetryCnt , +Random_time_meet , +//flow control +pause_apply , +pause_quanta_sub , +xoff_gen , +xoff_gen_complete , +xon_gen , +xon_gen_complete , +//MAC_tx_FF +Fifo_data , +Fifo_rd , +Fifo_eop , +Fifo_da , +Fifo_rd_finish , +Fifo_rd_retry , +Fifo_ra , +Fifo_data_err_empty , +Fifo_data_err_full , +//RMII +TxD , +TxEn , +CRS , +//MAC_tx_addr_add +MAC_tx_addr_rd , +MAC_tx_addr_data , +MAC_tx_addr_init , +//RMON +Tx_pkt_type_rmon , +Tx_pkt_length_rmon , +Tx_apply_rmon , +Tx_pkt_err_type_rmon, +//CPU +pause_frame_send_en , +pause_quanta_set , +MAC_tx_add_en , +FullDuplex , +MaxRetry , +IFGset +); + +input Reset ; +input Clk ; + //CRC_gen Interface +output CRC_init ; +output [7:0] Frame_data ; +output Data_en ; +output CRC_rd ; +input CRC_end ; +input [7:0] CRC_out ; + //Ramdon_gen interface +output Random_init ; +output [3:0] RetryCnt ; +input Random_time_meet ;//levle hight indicate random time passed away + //flow control +input pause_apply ; +output pause_quanta_sub ; +input xoff_gen ; +output xoff_gen_complete ; +input xon_gen ; +output xon_gen_complete ; + //MAC_rx_FF +input [7:0] Fifo_data ; +output Fifo_rd ; +input Fifo_eop ; +input Fifo_da ; +output Fifo_rd_finish ; +output Fifo_rd_retry ; +input Fifo_ra ; +input Fifo_data_err_empty ; +input Fifo_data_err_full ; + //RMII +output [7:0] TxD ; +output TxEn ; +input CRS ; + //MAC_tx_addr_add +output MAC_tx_addr_init ; +output MAC_tx_addr_rd ; +input [7:0] MAC_tx_addr_data ; + //RMON +output [2:0] Tx_pkt_type_rmon ; +output [15:0] Tx_pkt_length_rmon ; +output Tx_apply_rmon ; +output [2:0] Tx_pkt_err_type_rmon; + //CPU +input pause_frame_send_en ; +input [15:0] pause_quanta_set ; +input MAC_tx_add_en ; +input FullDuplex ; +input [3:0] MaxRetry ; +input [5:0] IFGset ; +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter StateIdle =4'd00; +parameter StatePreamble =4'd01; +parameter StateSFD =4'd02; +parameter StateData =4'd03; +parameter StatePause =4'd04; +parameter StatePAD =4'd05; +parameter StateFCS =4'd06; +parameter StateIFG =4'd07; +parameter StateJam =4'd08; +parameter StateBackOff =4'd09; +parameter StateJamDrop =4'd10; +parameter StateFFEmptyDrop =4'd11; +parameter StateSwitchNext =4'd12; +parameter StateDefer =4'd13; +parameter StateSendPauseFrame =4'd14; + +reg [3:0] Current_state /*synthesis syn_keep=1 */; +reg [3:0] Next_state; +reg [5:0] IFG_counter; +reg [4:0] Preamble_counter;// +reg [7:0] TxD_tmp ; +reg TxEn_tmp ; +reg [15:0] Tx_pkt_length_rmon ; +reg Tx_apply_rmon ; +reg Tx_apply_rmon_tmp ; +reg Tx_apply_rmon_tmp_pl1; +reg [2:0] Tx_pkt_err_type_rmon; +reg [3:0] RetryCnt ; +reg Random_init ; +reg Fifo_rd_finish ; +reg Fifo_rd_retry ; +reg [7:0] TxD ; +reg TxEn ; +reg CRC_init ; +reg Data_en ; +reg CRC_rd ; +reg Fifo_rd ; +reg MAC_tx_addr_rd ; +reg MAC_header_slot ; +reg MAC_header_slot_tmp ; +reg [2:0] Tx_pkt_type_rmon ; +wire Collision ; +reg MAC_tx_addr_init ; +reg Src_MAC_ptr ; +reg [7:0] IPLengthCounter ;//for pad append +reg [1:0] PADCounter ; +reg [7:0] JamCounter ; +reg PktDrpEvenPtr ; +reg [7:0] pause_counter ; +reg pause_quanta_sub ; +reg pause_frame_send_en_dl1 ; +reg [15:0] pause_quanta_set_dl1 ; +reg xoff_gen_complete ; +reg xon_gen_complete ; +//****************************************************************************** +//boundery signal processing +//****************************************************************************** +always @(posedge Clk or posedge Reset) + if (Reset) + begin + pause_frame_send_en_dl1 <=0; + pause_quanta_set_dl1 <=0; + end + else + begin + pause_frame_send_en_dl1 <=pause_frame_send_en ; + pause_quanta_set_dl1 <=pause_quanta_set ; + end +//****************************************************************************** +//state machine +//****************************************************************************** +assign Collision=TxEn&CRS; + +always @(posedge Clk or posedge Reset) + if (Reset) + pause_counter <=0; + else if (Current_state!=StatePause) + pause_counter <=0; + else + pause_counter <=pause_counter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + IPLengthCounter <=0; + else if (Current_state==StateDefer) + IPLengthCounter <=0; + else if (IPLengthCounter!=8'hff&&(Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD)) + IPLengthCounter <=IPLengthCounter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + PADCounter <=0; + else if (Current_state!=StatePAD) + PADCounter <=0; + else + PADCounter <=PADCounter+1; + +always @(posedge Clk or posedge Reset) + if (Reset) + Current_state <=StateDefer; + else + Current_state <=Next_state; + +always @ (*) + case (Current_state) + StateDefer: + if ((FullDuplex)||(!FullDuplex&&!CRS)) + Next_state=StateIFG; + else + Next_state=Current_state; + StateIFG: + if (!FullDuplex&&CRS) + Next_state=StateDefer; + else if ((FullDuplex&&IFG_counter==IFGset-4)||(!FullDuplex&&!CRS&&IFG_counter==IFGset-4))//remove some additional time + Next_state=StateIdle; + else + Next_state=Current_state; + StateIdle: + if (!FullDuplex&&CRS) + Next_state=StateDefer; + else if (pause_apply) + Next_state=StatePause; + else if ((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen))) + Next_state=StatePreamble; + else + Next_state=Current_state; + StatePause: + if (pause_counter==512/8) + Next_state=StateDefer; + else + Next_state=Current_state; + StatePreamble: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if ((FullDuplex&&Preamble_counter==6)||(!FullDuplex&&!Collision&&Preamble_counter==6)) + Next_state=StateSFD; + else + Next_state=Current_state; + StateSFD: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) + Next_state=StateSendPauseFrame; + else + Next_state=StateData; + StateSendPauseFrame: + if (IPLengthCounter==17) + Next_state=StatePAD; + else + Next_state=Current_state; + StateData: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (Fifo_data_err_empty) + Next_state=StateFFEmptyDrop; + else if (Fifo_eop&&IPLengthCounter>=59)//IP+MAC+TYPE=60 ,start from 0 + Next_state=StateFCS; + else if (Fifo_eop) + Next_state=StatePAD; + else + Next_state=StateData; + StatePAD: + if (!FullDuplex&&Collision) + Next_state=StateJam; + else if (IPLengthCounter>=59) + Next_state=StateFCS; + else + Next_state=Current_state; + StateJam: + if (RetryCnt<=MaxRetry&&JamCounter==16) + Next_state=StateBackOff; + else if (RetryCnt>MaxRetry) + Next_state=StateJamDrop; + else + Next_state=Current_state; + StateBackOff: + if (Random_time_meet) + Next_state =StateDefer; + else + Next_state =Current_state; + StateFCS: + if (!FullDuplex&&Collision) + Next_state =StateJam; + else if (CRC_end) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateFFEmptyDrop: + if (Fifo_eop) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateJamDrop: + if (Fifo_eop) + Next_state =StateSwitchNext; + else + Next_state =Current_state; + StateSwitchNext: + Next_state =StateDefer; + default: + Next_state =StateDefer; + endcase + + + +always @ (posedge Clk or posedge Reset) + if (Reset) + JamCounter <=0; + else if (Current_state!=StateJam) + JamCounter <=0; + else if (Current_state==StateJam) + JamCounter <=JamCounter+1; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + RetryCnt <=0; + else if (Current_state==StateSwitchNext) + RetryCnt <=0; + else if (Current_state==StateJam&&Next_state==StateBackOff) + RetryCnt <=RetryCnt + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + IFG_counter <=0; + else if (Current_state!=StateIFG) + IFG_counter <=0; + else + IFG_counter <=IFG_counter + 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Preamble_counter <=0; + else if (Current_state!=StatePreamble) + Preamble_counter <=0; + else + Preamble_counter <=Preamble_counter+ 1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + PktDrpEvenPtr <=0; + else if(Current_state==StateJamDrop||Current_state==StateFFEmptyDrop) + PktDrpEvenPtr <=~PktDrpEvenPtr; +//****************************************************************************** +//generate output signals +//****************************************************************************** +//CRC related +always @(Current_state) + if (Current_state==StateSFD) + CRC_init =1; + else + CRC_init =0; + +assign Frame_data=TxD_tmp; + +always @(Current_state) + if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD) + Data_en =1; + else + Data_en =0; + +always @(Current_state) + if (Current_state==StateFCS) + CRC_rd =1; + else + CRC_rd =0; + +//Ramdon_gen interface +always @(Current_state or Next_state) + if (Current_state==StateJam&&Next_state==StateBackOff) + Random_init =1; + else + Random_init =0; + +//MAC_rx_FF +//data have one cycle delay after fifo read signals +always @ (*) + if (Current_state==StateData || + Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) || + Current_state==StateJamDrop&&PktDrpEvenPtr|| + Current_state==StateFFEmptyDrop&&PktDrpEvenPtr ) + Fifo_rd =1; + else + Fifo_rd =0; + +always @ (Current_state) + if (Current_state==StateSwitchNext) + Fifo_rd_finish =1; + else + Fifo_rd_finish =0; + +always @ (Current_state) + if (Current_state==StateJam) + Fifo_rd_retry =1; + else + Fifo_rd_retry =0; +//RMII +always @(Current_state) + if (Current_state==StatePreamble||Current_state==StateSFD|| + Current_state==StateData||Current_state==StateSendPauseFrame|| + Current_state==StateFCS||Current_state==StatePAD||Current_state==StateJam) + TxEn_tmp =1; + else + TxEn_tmp =0; + +//gen txd data +always @(*) + case (Current_state) + StatePreamble: + TxD_tmp =8'h55; + StateSFD: + TxD_tmp =8'hd5; + StateData: + if (Src_MAC_ptr&&MAC_tx_add_en) + TxD_tmp =MAC_tx_addr_data; + else + TxD_tmp =Fifo_data; + StateSendPauseFrame: + if (Src_MAC_ptr&&MAC_tx_add_en) + TxD_tmp =MAC_tx_addr_data; + else + case (IPLengthCounter) + 7'd0: TxD_tmp =8'h01; + 7'd1: TxD_tmp =8'h80; + 7'd2: TxD_tmp =8'hc2; + 7'd3: TxD_tmp =8'h00; + 7'd4: TxD_tmp =8'h00; + 7'd5: TxD_tmp =8'h01; + 7'd12: TxD_tmp =8'h88;//type + 7'd13: TxD_tmp =8'h08;// + 7'd14: TxD_tmp =8'h00;//opcode + 7'd15: TxD_tmp =8'h01; + 7'd16: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[15:8]; + 7'd17: TxD_tmp =xon_gen?8'b0:pause_quanta_set_dl1[7:0]; +// 7'd60: TxD_tmp =8'h26; +// 7'd61: TxD_tmp =8'h6b; +// 7'd62: TxD_tmp =8'hae; +// 7'd63: TxD_tmp =8'h0a; + default:TxD_tmp =0; + endcase + + StatePAD: + TxD_tmp =8'h00; + StateJam: + TxD_tmp =8'h01; //jam sequence + StateFCS: + TxD_tmp =CRC_out; + default: + TxD_tmp =2'b0; + endcase +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + TxD <=0; + TxEn <=0; + end + else + begin + TxD <=TxD_tmp; + TxEn <=TxEn_tmp; + end +//RMON + + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_length_rmon <=0; + else if (Current_state==StateSFD) + Tx_pkt_length_rmon <=0; + else if (Current_state==StateData||Current_state==StateSendPauseFrame||Current_state==StatePAD||Current_state==StateFCS) + Tx_pkt_length_rmon <=Tx_pkt_length_rmon+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon_tmp <=0; + else if ((Fifo_eop&&Current_state==StateJamDrop)|| + (Fifo_eop&&Current_state==StateFFEmptyDrop)|| + CRC_end) + Tx_apply_rmon_tmp <=1; + else + Tx_apply_rmon_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon_tmp_pl1 <=0; + else + Tx_apply_rmon_tmp_pl1 <=Tx_apply_rmon_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_apply_rmon <=0; + else if ((Fifo_eop&&Current_state==StateJamDrop)|| + (Fifo_eop&&Current_state==StateFFEmptyDrop)|| + CRC_end) + Tx_apply_rmon <=1; + else if (Tx_apply_rmon_tmp_pl1) + Tx_apply_rmon <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_err_type_rmon <=0; + else if(Fifo_eop&&Current_state==StateJamDrop) + Tx_pkt_err_type_rmon <=3'b001;// + else if(Fifo_eop&&Current_state==StateFFEmptyDrop) + Tx_pkt_err_type_rmon <=3'b010;//underflow + else if(Fifo_eop&&Fifo_data_err_full) + Tx_pkt_err_type_rmon <=3'b011;//overflow + else if(CRC_end) + Tx_pkt_err_type_rmon <=3'b100;//normal + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_header_slot_tmp <=0; + else if(Current_state==StateSFD&&Next_state==StateData) + MAC_header_slot_tmp <=1; + else + MAC_header_slot_tmp <=0; + +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_header_slot <=0; + else + MAC_header_slot <=MAC_header_slot_tmp; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Tx_pkt_type_rmon <=0; + else if (Current_state==StateSendPauseFrame) + Tx_pkt_type_rmon <=3'b100; + else if(MAC_header_slot) + Tx_pkt_type_rmon <={1'b0,TxD[7:6]}; + + +always @(Tx_pkt_length_rmon) + if (Tx_pkt_length_rmon>=6&&Tx_pkt_length_rmon<=11) + Src_MAC_ptr =1; + else + Src_MAC_ptr =0; + +//MAC_tx_addr_add +always @ (posedge Clk or posedge Reset) + if (Reset) + MAC_tx_addr_rd <=0; + else if ((Tx_pkt_length_rmon>=4&&Tx_pkt_length_rmon<=9)&&(MAC_tx_add_en||Current_state==StateSendPauseFrame)) + MAC_tx_addr_rd <=1; + else + MAC_tx_addr_rd <=0; + +always @ (Tx_pkt_length_rmon or Fifo_rd) + if ((Tx_pkt_length_rmon==3)&&Fifo_rd) + MAC_tx_addr_init=1; + else + MAC_tx_addr_init=0; + +//flow control +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_sub <=0; + else if(pause_counter==512/8) + pause_quanta_sub <=1; + else + pause_quanta_sub <=0; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + xoff_gen_complete <=0; + else if(Current_state==StateDefer&&xoff_gen) + xoff_gen_complete <=1; + else + xoff_gen_complete <=0; + + +always @ (posedge Clk or posedge Reset) + if (Reset) + xon_gen_complete <=0; + else if(Current_state==StateDefer&&xon_gen) + xon_gen_complete <=1; + else + xon_gen_complete <=0; + +endmodule diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/flow_ctrl.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/flow_ctrl.v new file mode 100644 index 00000000..76534e65 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/flow_ctrl.v @@ -0,0 +1,203 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// flow_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: flow_ctrl.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module flow_ctrl +( +Reset , +Clk , +//host processor , +tx_pause_en , +xoff_cpu , +xon_cpu , +//MAC_rx_flow , +pause_quanta , +pause_quanta_val , +//MAC_tx_ctrl , +pause_apply , +pause_quanta_sub , +xoff_gen , +xoff_gen_complete , +xon_gen , +xon_gen_complete + +); + +input Reset ; +input Clk ; + //host processor ; +input tx_pause_en ; +input xoff_cpu ; +input xon_cpu ; + //MAC_rx_flow ; +input [15:0] pause_quanta ; +input pause_quanta_val ; + //MAC_tx_ctrl ; +output pause_apply ; +input pause_quanta_sub ; +output xoff_gen ; +input xoff_gen_complete ; +output xon_gen ; +input xon_gen_complete ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg xoff_cpu_dl1 ; +reg xoff_cpu_dl2 ; +reg xon_cpu_dl1 ; +reg xon_cpu_dl2 ; +reg [15:0] pause_quanta_dl1 ; +reg pause_quanta_val_dl1 ; +reg pause_quanta_val_dl2 ; +reg pause_apply ; +reg xoff_gen ; +reg xon_gen ; +reg [15:0] pause_quanta_counter ; +reg tx_pause_en_dl1 ; +reg tx_pause_en_dl2 ; +//****************************************************************************** +//boundery signal processing +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + xoff_cpu_dl1 <=0; + xoff_cpu_dl2 <=0; + end + else + begin + xoff_cpu_dl1 <=xoff_cpu; + xoff_cpu_dl2 <=xoff_cpu_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + xon_cpu_dl1 <=0; + xon_cpu_dl2 <=0; + end + else + begin + xon_cpu_dl1 <=xon_cpu; + xon_cpu_dl2 <=xon_cpu_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + pause_quanta_dl1 <=0; + end + else + begin + pause_quanta_dl1 <=pause_quanta; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + pause_quanta_val_dl1 <=0; + pause_quanta_val_dl2 <=0; + end + else + begin + pause_quanta_val_dl1 <=pause_quanta_val; + pause_quanta_val_dl2 <=pause_quanta_val_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + tx_pause_en_dl1 <=0; + tx_pause_en_dl2 <=0; + end + else + begin + tx_pause_en_dl1 <=tx_pause_en; + tx_pause_en_dl2 <=tx_pause_en_dl1; + end + +//****************************************************************************** +//gen output signals +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + xoff_gen <=0; + else if (xoff_gen_complete) + xoff_gen <=0; + else if (xoff_cpu_dl1&&!xoff_cpu_dl2) + xoff_gen <=1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + xon_gen <=0; + else if (xon_gen_complete) + xon_gen <=0; + else if (xon_cpu_dl1&&!xon_cpu_dl2) + xon_gen <=1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_quanta_counter <=0; + else if(pause_quanta_val_dl1&&!pause_quanta_val_dl2) + pause_quanta_counter <=pause_quanta_dl1; + else if(pause_quanta_sub&&pause_quanta_counter!=0) + pause_quanta_counter <=pause_quanta_counter-1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + pause_apply <=0; + else if(pause_quanta_counter==0) + pause_apply <=0; + else if (tx_pause_en_dl2) + pause_apply <=1; + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/random_gen.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/random_gen.v new file mode 100644 index 00000000..ba344693 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/MAC_tx/random_gen.v @@ -0,0 +1,123 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// random_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: Ramdon_gen.v,v $ +// Revision 1.3 2006/01/19 14:07:54 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// + +module random_gen( +Reset , +Clk , +Init , +RetryCnt , +Random_time_meet +); +input Reset ; +input Clk ; +input Init ; +input [3:0] RetryCnt ; +output Random_time_meet; + +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [9:0] Random_sequence ; +reg [9:0] Random ; +reg [9:0] Random_counter ; +reg [7:0] Slot_time_counter; //256*2=512bit=1 slot time +reg Random_time_meet; + +//****************************************************************************** +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_sequence <=0; + else + Random_sequence <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])}; + +always @ (RetryCnt or Random_sequence) + case (RetryCnt) + 4'h0 : Random={9'b0,Random_sequence[0]}; + 4'h1 : Random={8'b0,Random_sequence[1:0]}; + 4'h2 : Random={7'b0,Random_sequence[2:0]}; + 4'h3 : Random={6'b0,Random_sequence[3:0]}; + 4'h4 : Random={5'b0,Random_sequence[4:0]}; + 4'h5 : Random={4'b0,Random_sequence[5:0]}; + 4'h6 : Random={3'b0,Random_sequence[6:0]}; + 4'h7 : Random={2'b0,Random_sequence[7:0]}; + 4'h8 : Random={1'b0,Random_sequence[8:0]}; + 4'h9 : Random={ Random_sequence[9:0]}; + default : Random={ Random_sequence[9:0]}; + endcase + +always @ (posedge Clk or posedge Reset) + if (Reset) + Slot_time_counter <=0; + else if(Init) + Slot_time_counter <=0; + else if(!Random_time_meet) + Slot_time_counter <=Slot_time_counter+1; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_counter <=0; + else if (Init) + Random_counter <=Random; + else if (Random_counter!=0&&Slot_time_counter==255) + Random_counter <=Random_counter -1 ; + +always @ (posedge Clk or posedge Reset) + if (Reset) + Random_time_meet <=1; + else if (Init) + Random_time_meet <=0; + else if (Random_counter==0) + Random_time_meet <=1; + +endmodule + + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/Phy_int.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/Phy_int.v new file mode 100644 index 00000000..7e0090f5 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/Phy_int.v @@ -0,0 +1,227 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Phy_int.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: Phy_int.v,v $ +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.3 2005/12/16 06:44:14 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.2 2005/12/13 12:15:36 Administrator +// no message +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module Phy_int ( +Reset , +MAC_rx_clk , +MAC_tx_clk , +//Rx interface , +MCrs_dv , +MRxD , +MRxErr , +//Tx interface , +MTxD , +MTxEn , +MCRS , +//Phy interface , +Tx_er , +Tx_en , +Txd , +Rx_er , +Rx_dv , +Rxd , +Crs , +Col , +//host interface , +Line_loop_en , +Speed + +); +input Reset ; +input MAC_rx_clk ; +input MAC_tx_clk ; + //Rx interface +output MCrs_dv ; +output [7:0] MRxD ; +output MRxErr ; + //Tx interface +input [7:0] MTxD ; +input MTxEn ; +output MCRS ; + //Phy interface +output Tx_er ; +output Tx_en ; +output [7:0] Txd ; +input Rx_er ; +input Rx_dv ; +input [7:0] Rxd ; +input Crs ; +input Col ; + //host interface +input Line_loop_en ; +input [2:0] Speed ; +//****************************************************************************** +//internal signals +//****************************************************************************** +reg [7:0] MTxD_dl1 ; +reg MTxEn_dl1 ; +reg Tx_odd_data_ptr ; +reg Rx_odd_data_ptr ; +reg Tx_en ; +reg [7:0] Txd ; +reg MCrs_dv ; +reg [7:0] MRxD ; +reg Rx_er_dl1 ; +reg Rx_dv_dl1 ; +reg Rx_dv_dl2 ; +reg [7:0] Rxd_dl1 ; +reg [7:0] Rxd_dl2 ; +reg Crs_dl1 ; +reg Col_dl1 ; +//****************************************************************************** +//Tx control +//****************************************************************************** +//reg boundery signals +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + begin + MTxD_dl1 <=0; + MTxEn_dl1 <=0; + end + else + begin + MTxD_dl1 <=MTxD ; + MTxEn_dl1 <=MTxEn ; + end + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Tx_odd_data_ptr <=0; + else if (!MTxD_dl1) + Tx_odd_data_ptr <=0; + else + Tx_odd_data_ptr <=!Tx_odd_data_ptr; + + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Txd <=0; + else if(Speed[2]&&MTxEn_dl1) + Txd <=MTxD_dl1; + else if(MTxEn_dl1&&!Tx_odd_data_ptr) + Txd <={4'b0,MTxD_dl1[3:0]}; + else if(MTxEn_dl1&&Tx_odd_data_ptr) + Txd <={4'b0,MTxD_dl1[7:4]}; + else + Txd <=0; + +always @ (posedge MAC_tx_clk or posedge Reset) + if (Reset) + Tx_en <=0; + else if(MTxEn_dl1) + Tx_en <=1; + else + Tx_en <=0; + +assign Tx_er=0; + +//****************************************************************************** +//Rx control +//****************************************************************************** +//reg boundery signals +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + begin + Rx_er_dl1 <=0; + Rx_dv_dl1 <=0; + Rx_dv_dl2 <=0 ; + Rxd_dl1 <=0; + Rxd_dl2 <=0; + Crs_dl1 <=0; + Col_dl1 <=0; + end + else + begin + Rx_er_dl1 <=Rx_er ; + Rx_dv_dl1 <=Rx_dv ; + Rx_dv_dl2 <=Rx_dv_dl1 ; + Rxd_dl1 <=Rxd ; + Rxd_dl2 <=Rxd_dl1 ; + Crs_dl1 <=Crs ; + Col_dl1 <=Col ; + end + +assign MRxErr =Rx_er_dl1 ; +assign MCRS =Crs_dl1 ; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + MCrs_dv <=0; + else if(Line_loop_en) + MCrs_dv <=Tx_en; + else if(Rx_dv_dl2) + MCrs_dv <=1; + else + MCrs_dv <=0; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + Rx_odd_data_ptr <=0; + else if (!Rx_dv_dl1) + Rx_odd_data_ptr <=0; + else + Rx_odd_data_ptr <=!Rx_odd_data_ptr; + +always @ (posedge MAC_rx_clk or posedge Reset) + if (Reset) + MRxD <=0; + else if(Line_loop_en) + MRxD <=Txd; + else if(Speed[2]&&Rx_dv_dl2) + MRxD <=Rxd_dl2; + else if(Rx_dv_dl1&&Rx_odd_data_ptr) + MRxD <={Rxd_dl1[3:0],Rxd_dl2[3:0]}; + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON.v new file mode 100644 index 00000000..c7821a97 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON.v @@ -0,0 +1,180 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: RMON.v,v $ +// Revision 1.4 2006/06/25 04:58:56 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:53 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:16 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + +module RMON + (Clk , + Reset , + //Tx_RMON + Tx_pkt_type_rmon , + Tx_pkt_length_rmon , + Tx_apply_rmon , + Tx_pkt_err_type_rmon, + //Tx_RMON + Rx_pkt_type_rmon , + Rx_pkt_length_rmon , + Rx_apply_rmon , + Rx_pkt_err_type_rmon, + //CPU + CPU_rd_addr , + CPU_rd_apply , + CPU_rd_grant , + CPU_rd_dout + ); + + input Clk ; + input Reset ; + //Tx_RMON + input [2:0] Tx_pkt_type_rmon ; + input [15:0] Tx_pkt_length_rmon ; + input Tx_apply_rmon ; + input [2:0] Tx_pkt_err_type_rmon; + //Tx_RMON + input [2:0] Rx_pkt_type_rmon ; + input [15:0] Rx_pkt_length_rmon ; + input Rx_apply_rmon ; + input [2:0] Rx_pkt_err_type_rmon; + //CPU + input [5:0] CPU_rd_addr ; + input CPU_rd_apply ; + output CPU_rd_grant ; + output [31:0] CPU_rd_dout ; + + // ****************************************************************************** + //interface signals + // ****************************************************************************** + wire Reg_apply_0 ; + wire [4:0] Reg_addr_0 ; + wire [15:0] Reg_data_0 ; + wire Reg_next_0 ; + wire Reg_apply_1 ; + wire [4:0] Reg_addr_1 ; + wire [15:0] Reg_data_1 ; + wire Reg_next_1 ; + wire [5:0] Addra ; + wire [31:0] Dina ; + wire [31:0] Douta ; + wire Wea ; + + // ****************************************************************************** + + RMON_addr_gen + U_0_Rx_RMON_addr_gen(.Clk (Clk ), + .Reset (Reset ), + //RMON (//RMON ), + // .Pkt_type_rmon (Rx_pkt_type_rmon ), + .Pkt_length_rmon (Rx_pkt_length_rmon ), + .Apply_rmon (Rx_apply_rmon ), + .Pkt_err_type_rmon (Rx_pkt_err_type_rmon ), + //Rmon_ctrl (//Rmon_ctrl ), + .Reg_apply (Reg_apply_0 ), + .Reg_addr (Reg_addr_0 ), + .Reg_data (Reg_data_0 ), + .Reg_next (Reg_next_0 ), + //CPU (//CPU ), + .Reg_drop_apply ( )); + + RMON_addr_gen + U_0_Tx_RMON_addr_gen(.Clk (Clk ), + .Reset (Reset ), + //RMON (//RMON ), + .Pkt_type_rmon (Tx_pkt_type_rmon ), + .Pkt_length_rmon (Tx_pkt_length_rmon ), + .Apply_rmon (Tx_apply_rmon ), + .Pkt_err_type_rmon (Tx_pkt_err_type_rmon ), + //Rmon_ctrl (//Rmon_ctrl ), + .Reg_apply (Reg_apply_1 ), + .Reg_addr (Reg_addr_1 ), + .Reg_data (Reg_data_1 ), + .Reg_next (Reg_next_1 ), + //CPU (//CPU ), + .Reg_drop_apply ( )); + + RMON_ctrl + U_RMON_ctrl(.Clk (Clk ), + .Reset (Reset ), + //RMON_CTRL (//RMON_CTRL ), + .Reg_apply_0 (Reg_apply_0 ), + .Reg_addr_0 (Reg_addr_0 ), + .Reg_data_0 (Reg_data_0 ), + .Reg_next_0 (Reg_next_0 ), + .Reg_apply_1 (Reg_apply_1 ), + .Reg_addr_1 (Reg_addr_1 ), + .Reg_data_1 (Reg_data_1 ), + .Reg_next_1 (Reg_next_1 ), + //dual-port ram (//dual-port ram ), + .Addra (Addra ), + .Dina (Dina ), + .Douta (Douta ), + .Wea (Wea ), + //CPU (//CPU ), + .CPU_rd_addr (CPU_rd_addr ), + .CPU_rd_apply (CPU_rd_apply ), + .CPU_rd_grant (CPU_rd_grant ), + .CPU_rd_dout (CPU_rd_dout ) + ); + + RMON_dpram + U_Rx_RMON_dpram(.Reset (Reset ), + .Clk (Clk ), + //port-a for Rmon (//port-a for Rmon ), + .Addra (Addra ), + .Dina (Dina ), + .Douta ( ), + .Wea (Wea ), + //port-b for CPU (//port-b for CPU ), + .Addrb (Addra ), + .Doutb (Douta )); + +endmodule // RMON diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Entries new file mode 100644 index 00000000..5df4f14a --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Entries @@ -0,0 +1,4 @@ +/RMON_addr_gen.v/1.4/Sun Jun 25 04:58:57 2006// +/RMON_ctrl.v/1.4/Sun Jun 25 04:58:57 2006// +/RMON_dpram.v/1.2/Thu Jan 19 14:07:55 2006// +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Repository new file mode 100644 index 00000000..788bf5c9 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/rtl/verilog/RMON diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_addr_gen.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_addr_gen.v new file mode 100644 index 00000000..0a3b00cf --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_addr_gen.v @@ -0,0 +1,295 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON_addr_gen.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: RMON_addr_gen.v,v $ +// Revision 1.4 2006/06/25 04:58:57 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:55 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +module RMON_addr_gen( +Clk , +Reset , +//RMON +Pkt_type_rmon , +Pkt_length_rmon , +Apply_rmon ,//pluse signal looks like eop +Pkt_err_type_rmon , +// +Reg_apply , +Reg_addr , +Reg_data , +Reg_next , +//CPU +Reg_drop_apply +); +input Clk ; +input Reset ; + //RMON +input [2:0] Pkt_type_rmon ; +input [15:0] Pkt_length_rmon ; +input Apply_rmon ;//pluse signal looks like eop +input [2:0] Pkt_err_type_rmon ; + //RMON_ctrl +output Reg_apply ; +output [4:0] Reg_addr ; +output [15:0] Reg_data ; +input Reg_next ; + //CPU +output Reg_drop_apply ; + +//****************************************************************************** +//internal signals +//****************************************************************************** +parameter StateIdle =4'd0; +parameter StatePktLength =4'd1; +parameter StatePktNumber =4'd2; +parameter StatePktType =4'd3; +parameter StatePktRange =4'd4; + +reg [3:0] CurrentState /* synthesys syn_keep=1 */; +reg [3:0] NextState; + +reg [2:0] PktTypeReg ; +reg [15:0] PktLengthReg ; +reg [2:0] PktErrTypeReg ; + +reg Reg_apply ; +reg [4:0] Reg_addr ; +reg [15:0] Reg_data ; +reg Reg_drop_apply ; +//****************************************************************************** +//register boundery signals + +//****************************************************************************** +reg Apply_rmon_dl1; +reg Apply_rmon_dl2; +reg Apply_rmon_pulse; +reg [2:0] Pkt_type_rmon_dl1 ; +reg [15:0] Pkt_length_rmon_dl1 ; +reg [2:0] Pkt_err_type_rmon_dl1 ; + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + Pkt_type_rmon_dl1 <=0; + Pkt_length_rmon_dl1 <=0; + Pkt_err_type_rmon_dl1 <=0; + end + else + begin + Pkt_type_rmon_dl1 <=Pkt_type_rmon ; + Pkt_length_rmon_dl1 <=Pkt_length_rmon ; + Pkt_err_type_rmon_dl1 <=Pkt_err_type_rmon ; + end + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + Apply_rmon_dl1 <=0; + Apply_rmon_dl2 <=0; + end + else + begin + Apply_rmon_dl1 <=Apply_rmon; + Apply_rmon_dl2 <=Apply_rmon_dl1; + end + +always @(Apply_rmon_dl1 or Apply_rmon_dl2) + if (Apply_rmon_dl1&!Apply_rmon_dl2) + Apply_rmon_pulse =1; + else + Apply_rmon_pulse =0; + + + +always @(posedge Clk or posedge Reset) + if (Reset) + begin + PktTypeReg <=0; + PktLengthReg <=0; + PktErrTypeReg <=0; + end + else if (Apply_rmon_pulse&&CurrentState==StateIdle) + begin + PktTypeReg <=Pkt_type_rmon_dl1 ; + PktLengthReg <=Pkt_length_rmon_dl1 ; + PktErrTypeReg <=Pkt_err_type_rmon_dl1 ; + end + + +//****************************************************************************** +//State Machine +//****************************************************************************** +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState <=StateIdle; + else + CurrentState <=NextState; + +always @(CurrentState or Apply_rmon_pulse or Reg_next) + case (CurrentState) + StateIdle: + if (Apply_rmon_pulse) + NextState =StatePktLength; + else + NextState =StateIdle; + StatePktLength: + if (Reg_next) + NextState =StatePktNumber; + else + NextState =CurrentState; + StatePktNumber: + if (Reg_next) + NextState =StatePktType; + else + NextState =CurrentState; + StatePktType: + if (Reg_next) + NextState =StatePktRange; + else + NextState =CurrentState; + StatePktRange: + if (Reg_next) + NextState =StateIdle; + else + NextState =CurrentState; + default: + NextState =StateIdle; + endcase + +//****************************************************************************** +//gen output signals +//****************************************************************************** +//Reg_apply +always @ (CurrentState) + if (CurrentState==StatePktLength||CurrentState==StatePktNumber|| + CurrentState==StatePktType||CurrentState==StatePktRange) + Reg_apply =1; + else + Reg_apply =0; + +//Reg_addr +always @ (posedge Clk or posedge Reset) + if (Reset) + Reg_addr <=0; + else case (CurrentState) + StatePktLength: + Reg_addr <=5'd00; + StatePktNumber: + Reg_addr <=5'd01; + StatePktType: + case(PktTypeReg) + 3'b011: + Reg_addr <=5'd02; //broadcast + 3'b001: + Reg_addr <=5'd03; //multicast + 3'b100: + Reg_addr <=5'd16; //pause frame + default: + Reg_addr <=5'd04; //unicast + endcase + StatePktRange: + case(PktErrTypeReg) + 3'b001: + Reg_addr <=5'd05; + 3'b010: + Reg_addr <=5'd06; + 3'b011: + Reg_addr <=5'd07; + 3'b100: + if (PktLengthReg<64) + Reg_addr <=5'd08; + else if (PktLengthReg==64) + Reg_addr <=5'd09; + else if (PktLengthReg<128) + Reg_addr <=5'd10; + else if (PktLengthReg<256) + Reg_addr <=5'd11; + else if (PktLengthReg<512) + Reg_addr <=5'd12; + else if (PktLengthReg<1024) + Reg_addr <=5'd13; + else if (PktLengthReg<1519) + Reg_addr <=5'd14; + else + Reg_addr <=5'd15; + default: + Reg_addr <=5'd05; + endcase + default: + Reg_addr <=5'd05; + endcase + +//Reg_data +always @ (CurrentState or PktLengthReg) + case (CurrentState) + StatePktLength: + Reg_data =PktLengthReg; + StatePktNumber: + Reg_data =1; + StatePktType: + Reg_data =1; + StatePktRange: + Reg_data =1; + default: + Reg_data =0; + endcase + +//Reg_drop_apply +always @ (posedge Clk or posedge Reset) + if (Reset) + Reg_drop_apply <=0; + else if (CurrentState!=StateIdle&&Apply_rmon_pulse) + Reg_drop_apply <=1; + else + Reg_drop_apply <=0; + + +endmodule + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_ctrl.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_ctrl.v new file mode 100644 index 00000000..02ecab3f --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_ctrl.v @@ -0,0 +1,290 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// RMON_ctrl.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: RMON_ctrl.v,v $ +// Revision 1.4 2006/06/25 04:58:57 maverickist +// no message +// +// Revision 1.3 2006/01/19 14:07:55 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:19 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +module RMON_ctrl ( +Clk , +Reset , +//RMON_CTRL +Reg_apply_0 , +Reg_addr_0 , +Reg_data_0 , +Reg_next_0 , +Reg_apply_1 , +Reg_addr_1 , +Reg_data_1 , +Reg_next_1 , +//dual-port ram +Addra , +Dina , +Douta , +Wea , +//CPU +CPU_rd_addr , +CPU_rd_apply , +CPU_rd_grant , +CPU_rd_dout + +); +input Clk ; +input Reset ; + //RMON_CTRL +input Reg_apply_0 ; +input [4:0] Reg_addr_0 ; +input [15:0] Reg_data_0 ; +output Reg_next_0 ; +input Reg_apply_1 ; +input [4:0] Reg_addr_1 ; +input [15:0] Reg_data_1 ; +output Reg_next_1 ; + //dual-port ram + //port-a for Rmon +output [5:0] Addra ; +output [31:0] Dina ; +input [31:0] Douta ; +output Wea ; + //CPU +input [5:0] CPU_rd_addr ; +input CPU_rd_apply ; +output CPU_rd_grant ; +output [31:0] CPU_rd_dout ; + + + + +//****************************************************************************** +//internal signals +//****************************************************************************** + +parameter StateCPU =4'd00; +parameter StateMAC0 =4'd01; +parameter StateMAC1 =4'd02; + + +reg [3:0] CurrentState /* synthesys syn_keep=1 */; +reg [3:0] NextState; +reg [3:0] CurrentState_reg; + +reg [4:0] StepCounter; +reg [31:0] DoutaReg; +reg [5:0] Addra ; +reg [31:0] Dina; +reg Reg_next_0 ; +reg Reg_next_1 ; +reg Write; +reg Read; +reg Pipeline; +reg [31:0] CPU_rd_dout ; +reg CPU_rd_apply_reg ; +//****************************************************************************** +//State Machine +//****************************************************************************** + +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState <=StateMAC0; + else + CurrentState <=NextState; + +always @(posedge Clk or posedge Reset) + if (Reset) + CurrentState_reg <=StateMAC0; + else if(CurrentState!=StateCPU) + CurrentState_reg <=CurrentState; + +always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg + or Reg_apply_1 + or StepCounter + ) + case(CurrentState) + StateMAC0: + if(!Reg_apply_0&&CPU_rd_apply_reg) + NextState =StateCPU; + else if(!Reg_apply_0) + NextState =StateMAC1; + else + NextState =CurrentState; + StateMAC1: + if(!Reg_apply_1&&CPU_rd_apply_reg) + NextState =StateCPU; + else if(!Reg_apply_1) + NextState =StateMAC0; + else + NextState =CurrentState; + StateCPU: + if (StepCounter==3) + case (CurrentState_reg) + StateMAC0 :NextState =StateMAC0 ; + StateMAC1 :NextState =StateMAC1 ; + default :NextState =StateMAC0; + endcase + else + NextState =CurrentState; + + default: + NextState =StateMAC0; + endcase + + + +always @(posedge Clk or posedge Reset) + if (Reset) + StepCounter <=0; + else if(NextState!=CurrentState) + StepCounter <=0; + else if (StepCounter!=4'hf) + StepCounter <=StepCounter + 1; + +//****************************************************************************** +//temp signals +//****************************************************************************** +always @(StepCounter) + if( StepCounter==1||StepCounter==4|| + StepCounter==7||StepCounter==10) + Read =1; + else + Read =0; + +always @(StepCounter or CurrentState) + if( StepCounter==2||StepCounter==5|| + StepCounter==8||StepCounter==11) + Pipeline =1; + else + Pipeline =0; + +always @(StepCounter or CurrentState) + if( StepCounter==3||StepCounter==6|| + StepCounter==9||StepCounter==12) + Write =1; + else + Write =0; + +always @(posedge Clk or posedge Reset) + if (Reset) + DoutaReg <=0; + else if (Read) + DoutaReg <=Douta; + + +//****************************************************************************** +//gen output signals +//****************************************************************************** +//Addra +always @(*) + case(CurrentState) + StateMAC0 : Addra={1'd0 ,Reg_addr_0 }; + StateMAC1 : Addra={1'd1 ,Reg_addr_1 }; + StateCPU: Addra=CPU_rd_addr; + default: Addra=0; + endcase + +//Dina +always @(posedge Clk or posedge Reset) + if (Reset) + Dina <=0; + else + case(CurrentState) + StateMAC0 : Dina<=Douta+Reg_data_0 ; + StateMAC1 : Dina<=Douta+Reg_data_1 ; + StateCPU: Dina<=0; + default: Dina<=0; + endcase + +assign Wea =Write; +//Reg_next +always @(CurrentState or Pipeline) + if(CurrentState==StateMAC0) + Reg_next_0 =Pipeline; + else + Reg_next_0 =0; + +always @(CurrentState or Pipeline) + if(CurrentState==StateMAC1) + Reg_next_1 =Pipeline; + else + Reg_next_1 =0; + + +//CPU_rd_grant +reg CPU_rd_apply_dl1; +reg CPU_rd_apply_dl2; +//rising edge +always @ (posedge Clk or posedge Reset) + if (Reset) + begin + CPU_rd_apply_dl1 <=0; + CPU_rd_apply_dl2 <=0; + end + else + begin + CPU_rd_apply_dl1 <=CPU_rd_apply; + CPU_rd_apply_dl2 <=CPU_rd_apply_dl1; + end + +always @ (posedge Clk or posedge Reset) + if (Reset) + CPU_rd_apply_reg <=0; + else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2) + CPU_rd_apply_reg <=1; + else if (CurrentState==StateCPU&&Write) + CPU_rd_apply_reg <=0; + +assign CPU_rd_grant =!CPU_rd_apply_reg; + +always @ (posedge Clk or posedge Reset) + if (Reset) + CPU_rd_dout <=0; + else if (Pipeline&&CurrentState==StateCPU) + CPU_rd_dout <=Douta; + +endmodule diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_dpram.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_dpram.v new file mode 100644 index 00000000..4b58512c --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/RMON/RMON_dpram.v @@ -0,0 +1,46 @@ +module RMON_dpram + (Reset , + Clk , + //port-a for Rmon + Addra, + Dina, + Douta, + Wea, + //port-b for CPU + Addrb, + Doutb + ); + + input Reset ; + input Clk ; + //port-a for Rmon + input [5:0] Addra; + input [31:0] Dina; + output [31:0] Douta; + input Wea; + //port-b for CPU + input [5:0] Addrb; + output [31:0] Doutb; + // ****************************************************************************** + //internal signals + // ****************************************************************************** + + wire Clka; + wire Clkb; + assign Clka=Clk; + assign #2 Clkb=Clk; + // ****************************************************************************** + + duram #(32,6) + U_duram(.data_a (Dina ), + .data_b (32'b0 ), + .wren_a (Wea ), + .wren_b (1'b0 ), + .address_a (Addra ), + .address_b (Addrb ), + .clock_a (Clka ), + .clock_b (Clkb ), + .q_a (Douta ), + .q_b (Doutb )); + +endmodule // RMON_dpram diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CLK_SWITCH.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CLK_SWITCH.v new file mode 100644 index 00000000..d18d719f --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CLK_SWITCH.v @@ -0,0 +1,68 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_SWITCH.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: CLK_SWITCH.v,v $ +// Revision 1.3 2006/01/19 14:07:56 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// +module CLK_SWITCH ( +input IN_0, +input IN_1, +input SW , +output OUT + +); + +assign OUT=SW?IN_1:IN_0; + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries new file mode 100644 index 00000000..25cf148b --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries @@ -0,0 +1,5 @@ +/CLK_SWITCH.v/1.3/Thu Jan 19 14:07:56 2006// +D/altera//// +D/xilinx//// +/duram.v/1.2/Wed May 2 02:54:45 2007// +/CLK_DIV2.v/1.3/Wed May 2 06:49:15 2007// diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Repository new file mode 100644 index 00000000..3c7177d2 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/rtl/verilog/TECH diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CLK_DIV2.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CLK_DIV2.v new file mode 100644 index 00000000..ce94e2de --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CLK_DIV2.v @@ -0,0 +1,74 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_DIV2.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: CLK_DIV2.v,v $ +// Revision 1.1 2006/10/22 16:12:24 maverickist +// no message +// +// Revision 1.1 2006/06/22 09:01:41 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// + +module CLK_DIV2 ( +input Reset, +input IN, +output reg OUT +); + +always @ (posedge IN or posedge Reset) + if (Reset) + OUT <=0; + else + OUT <=!OUT; + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CLK_SWITCH.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CLK_SWITCH.v new file mode 100644 index 00000000..4e1a5d35 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CLK_SWITCH.v @@ -0,0 +1,71 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_SWITCH.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: CLK_SWITCH.v,v $ +// Revision 1.1 2006/10/22 16:12:24 maverickist +// no message +// +// Revision 1.1 2006/06/22 09:01:41 Administrator +// no message +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// +module CLK_SWITCH ( +input IN_0, +input IN_1, +input SW , +output OUT + +); + +assign OUT=SW?IN_1:IN_0; + +endmodule \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Entries new file mode 100644 index 00000000..426ef42e --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Entries @@ -0,0 +1,4 @@ +/CLK_DIV2.v/1.1/Sun Oct 22 16:12:24 2006// +/CLK_SWITCH.v/1.1/Sun Oct 22 16:12:24 2006// +/duram.v/1.1/Sun Oct 22 16:12:24 2006// +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Repository new file mode 100644 index 00000000..25356ea5 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/rtl/verilog/TECH/altera diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/duram.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/duram.v new file mode 100644 index 00000000..b653bedd --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/altera/duram.v @@ -0,0 +1,87 @@ +module duram( +data_a, +data_b, +wren_a, +wren_b, +address_a, +address_b, +clock_a, +clock_b, +q_a, +q_b); //synthesis syn_black_box + +parameter DATA_WIDTH = 32; +parameter ADDR_WIDTH = 5; +parameter BLK_RAM_TYPE = "AUTO"; +parameter DURAM_MODE = "BIDIR_DUAL_PORT"; +parameter ADDR_DEPTH = 2**ADDR_WIDTH; + + + +input [DATA_WIDTH -1:0] data_a; +input wren_a; +input [ADDR_WIDTH -1:0] address_a; +input clock_a; +output [DATA_WIDTH -1:0] q_a; +input [DATA_WIDTH -1:0] data_b; +input wren_b; +input [ADDR_WIDTH -1:0] address_b; +input clock_b; +output [DATA_WIDTH -1:0] q_b; + + + +altsyncram U_altsyncram ( +.wren_a (wren_a), +.wren_b (wren_b), +.data_a (data_a), +.data_b (data_b), +.address_a (address_a), +.address_b (address_b), +.clock0 (clock_a), +.clock1 (clock_b), +.q_a (q_a), +.q_b (q_b), +// synopsys translate_off +.aclr0 (), +.aclr1 (), +.addressstall_a (), +.addressstall_b (), +.byteena_a (), +.byteena_b (), +.clocken0 (), +.clocken1 (), +.rden_b () +// synopsys translate_on +); + defparam + U_altsyncram.intended_device_family = "Stratix", + U_altsyncram.ram_block_type = BLK_RAM_TYPE, + U_altsyncram.operation_mode = DURAM_MODE, + U_altsyncram.width_a = DATA_WIDTH, + U_altsyncram.widthad_a = ADDR_WIDTH, +// U_altsyncram.numwords_a = 256, + U_altsyncram.width_b = DATA_WIDTH, + U_altsyncram.widthad_b = ADDR_WIDTH, +// U_altsyncram.numwords_b = 256, + U_altsyncram.lpm_type = "altsyncram", + U_altsyncram.width_byteena_a = 1, + U_altsyncram.width_byteena_b = 1, + U_altsyncram.outdata_reg_a = "UNREGISTERED", + U_altsyncram.outdata_aclr_a = "NONE", + U_altsyncram.outdata_reg_b = "UNREGISTERED", + U_altsyncram.indata_aclr_a = "NONE", + U_altsyncram.wrcontrol_aclr_a = "NONE", + U_altsyncram.address_aclr_a = "NONE", + U_altsyncram.indata_reg_b = "CLOCK1", + U_altsyncram.address_reg_b = "CLOCK1", + U_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1", + U_altsyncram.indata_aclr_b = "NONE", + U_altsyncram.wrcontrol_aclr_b = "NONE", + U_altsyncram.address_aclr_b = "NONE", + U_altsyncram.outdata_aclr_b = "NONE", + U_altsyncram.power_up_uninitialized = "FALSE"; + +endmodule + + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/clkdiv2.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/clkdiv2.v new file mode 100644 index 00000000..00b2712a --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/clkdiv2.v @@ -0,0 +1,71 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// CLK_DIV2.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode///// +//// //// +//// Author(s): //// +//// - Jon Gao (gaojon@yahoo.com) //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: CLK_DIV2.v,v $ +// Revision 1.3 2006/01/19 14:07:56 maverickist +// verification is complete. +// +// Revision 1.2 2005/12/16 06:44:20 Administrator +// replaced tab with space. +// passed 9.6k length frame test. +// +// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator +// no message +// + + +////////////////////////////////////////////////////////////////////// +// This file can only used for simulation . +// You need to replace it with your own element according to technology +////////////////////////////////////////////////////////////////////// + +module clkdiv2 ( +input Reset, +input IN, +output reg OUT +); + +always @ (posedge IN or posedge Reset) + if (Reset) + OUT <=0; + else + OUT <=!OUT; + +endmodule diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/duram.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/duram.v new file mode 100644 index 00000000..f831932b --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/TECH/duram.v @@ -0,0 +1,103 @@ + + +module duram + (data_a, + data_b, + wren_a, + wren_b, + address_a, + address_b, + clock_a, + clock_b, + q_a, + q_b); + + parameter DATA_WIDTH = 32; + parameter ADDR_WIDTH = 5; + parameter ADDR_DEPTH = 1<>1) -1; // We are counting half of period + + + // Counter counts half period + always @ (posedge Clk or posedge Reset) + begin + if(Reset) + Counter[7:0] <= #Tp 8'h1; + else + begin + if(CountEq0) + begin + Counter[7:0] <= #Tp CounterPreset[7:0]; + end + else + Counter[7:0] <= #Tp Counter - 8'h1; + end + end + + + // Mdc is asserted every other half period + always @ (posedge Clk or posedge Reset) + begin + if(Reset) + Mdc <= #Tp 1'b0; + else + begin + if(CountEq0) + Mdc <= #Tp ~Mdc; + end + end + + + assign CountEq0 = Counter == 8'h0; + assign MdcEn = CountEq0 & ~Mdc; + assign MdcEn_n = CountEq0 & Mdc; + +endmodule // eth_clockgen + + + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_outputcontrol.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_outputcontrol.v new file mode 100644 index 00000000..9c45b088 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_outputcontrol.v @@ -0,0 +1,162 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_outputcontrol.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_outputcontrol.v,v $ +// Revision 1.2 2005/12/13 12:54:49 maverickist +// first simulation passed +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:46 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.4 2002/07/09 20:11:59 mohor +// Comment removed. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + +module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); + +parameter Tp = 1; + +input Clk; // Host Clock +input Reset; // General Reset +input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) +input NoPre; // No Preamble (no 32-bit preamble) +input InProgress; // Operation in progress +input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal +input [6:0] BitCounter; // Bit Counter +input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls. + +output Mdo; // MII Management Data Output +output MdoEn; // MII Management Data Output Enable + +wire SerialEn; + +reg MdoEn_2d; +reg MdoEn_d; +reg MdoEn; + +reg Mdo_2d; +reg Mdo_d; +reg Mdo; // MII Management Data Output + + + +// Generation of the Serial Enable signal (enables the serialization of the data) +assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) ) + | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre )); + + +// Generation of the MdoEn signal +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + MdoEn_2d <= #Tp 1'b0; + MdoEn_d <= #Tp 1'b0; + MdoEn <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32; + MdoEn_d <= #Tp MdoEn_2d; + MdoEn <= #Tp MdoEn_d; + end + end +end + + +// Generation of the Mdo signal. +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + Mdo_2d <= #Tp 1'b0; + Mdo_d <= #Tp 1'b0; + Mdo <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + Mdo_2d <= #Tp ~SerialEn & BitCounter<32; + Mdo_d <= #Tp ShiftedBit | Mdo_2d; + Mdo <= #Tp Mdo_d; + end + end +end + + + +endmodule diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_shiftreg.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_shiftreg.v new file mode 100644 index 00000000..a11ead1d --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/eth_shiftreg.v @@ -0,0 +1,164 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// eth_shiftreg.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: eth_shiftreg.v,v $ +// Revision 1.2 2005/12/13 12:54:49 maverickist +// first simulation passed +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.2 2005/04/27 15:58:47 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.5 2002/08/14 18:16:59 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.4 2002/03/02 21:06:01 mohor +// LinkFail signal was not latching appropriate bit. +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 08:43:51 mohor +// eth_timescale.v changed to timescale.v This is done because of the +// simulation of the few cores in a one joined project. +// +// Revision 1.1 2001/08/06 14:44:29 mohor +// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). +// Include files fixed to contain no path. +// File names and module names changed ta have a eth_ prologue in the name. +// File eth_timescale.v is used to define timescale +// All pin names on the top module are changed to contain _I, _O or _OE at the end. +// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O +// and Mdo_OE. The bidirectional signal must be created on the top level. This +// is done due to the ASIC tools. +// +// Revision 1.1 2001/07/30 21:23:42 mohor +// Directory structure changed. Files checked and joind together. +// +// Revision 1.3 2001/06/01 22:28:56 mohor +// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. +// +// + +`timescale 1ns/10ps + + +module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, + LatchByte, ShiftedBit, Prsd, LinkFail); + + +parameter Tp=1; + +input Clk; // Input clock (Host clock) +input Reset; // Reset signal +input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. +input Mdi; // MII input data +input [4:0] Fiad; // PHY address +input [4:0] Rgad; // Register address (within the selected PHY) +input [15:0]CtrlData; // Control data (data to be written to the PHY) +input WriteOp; // The current operation is a PHY register write operation +input [3:0] ByteSelect; // Byte select +input [1:0] LatchByte; // Byte select for latching (read operation) + +output ShiftedBit; // Bit shifted out of the shift register +output[15:0]Prsd; // Read Status Data (data read from the PHY) +output LinkFail; // Link Integrity Signal + +reg [7:0] ShiftReg; // Shift register for shifting the data in and out +reg [15:0]Prsd; +reg LinkFail; + + + + +// ShiftReg[7:0] :: Shift Register Data +always @ (posedge Clk or posedge Reset) +begin + if(Reset) + begin + ShiftReg[7:0] <= #Tp 8'h0; + Prsd[15:0] <= #Tp 16'h0; + LinkFail <= #Tp 1'b0; + end + else + begin + if(MdcEn_n) + begin + if(|ByteSelect) + begin + case (ByteSelect[3:0]) + 4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; + 4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10}; + 4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8]; + 4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0]; + default : ShiftReg[7:0] <= #Tp 8'h0; + endcase + end + else + begin + ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi}; + if(LatchByte[0]) + begin + Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi}; + if(Rgad == 5'h01) + LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet + end + else + begin + if(LatchByte[1]) + Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi}; + end + end + end + end +end + + +assign ShiftedBit = ShiftReg[7]; + + +endmodule diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/timescale.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/timescale.v new file mode 100644 index 00000000..4517d897 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/miim/timescale.v @@ -0,0 +1,62 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// timescale.v //// +//// //// +//// This file is part of the Ethernet IP core project //// +//// http://www.opencores.org/projects/ethmac/ //// +//// //// +//// Author(s): //// +//// - Igor Mohor (igorM@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: timescale.v,v $ +// Revision 1.2 2005/12/13 12:54:49 maverickist +// first simulation passed +// +// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator +// no message +// +// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator +// no message +// +// Revision 1.3 2002/01/23 10:28:16 mohor +// Link in the header changed. +// +// Revision 1.2 2001/10/19 11:36:31 mohor +// Log file added. +// +// +// + +`timescale 1ns / 1ns diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/reg_int.v b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/reg_int.v new file mode 100644 index 00000000..cbb67a98 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/rtl/verilog/reg_int.v @@ -0,0 +1,179 @@ +module reg_int ( +input Reset , +input Clk_reg , +input CSB , +input WRB , +input [15:0] CD_in , +output reg [15:0] CD_out , +input [7:0] CA , + //Tx host interface +output [4:0] Tx_Hwmark , +output [4:0] Tx_Lwmark , +output pause_frame_send_en , +output [15:0] pause_quanta_set , +output MAC_tx_add_en , +output FullDuplex , +output [3:0] MaxRetry , +output [5:0] IFGset , +output [7:0] MAC_tx_add_prom_data , +output [2:0] MAC_tx_add_prom_add , +output MAC_tx_add_prom_wr , +output tx_pause_en , +output xoff_cpu , +output xon_cpu , + //Rx host interface +output MAC_rx_add_chk_en , +output [7:0] MAC_rx_add_prom_data , +output [2:0] MAC_rx_add_prom_add , +output MAC_rx_add_prom_wr , +output broadcast_filter_en , +output [15:0] broadcast_bucket_depth , +output [15:0] broadcast_bucket_interval , +output RX_APPEND_CRC , +output [4:0] Rx_Hwmark , +output [4:0] Rx_Lwmark , +output CRC_chk_en , +output [5:0] RX_IFG_SET , +output [15:0] RX_MAX_LENGTH ,// 1518 +output [6:0] RX_MIN_LENGTH ,// 64 + //RMON host interface +output [5:0] CPU_rd_addr , +output CPU_rd_apply , +input CPU_rd_grant , +input [31:0] CPU_rd_dout , + //Phy int host interface +output Line_loop_en , +output [2:0] Speed , + //MII to CPU +output [7:0] Divider ,// Divider for the host clock +output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.) +output [4:0] Rgad ,// Register Address (within the PHY) +output [4:0] Fiad ,// PHY Address +output NoPre ,// No Preamble (no 32-bit preamble) +output WCtrlData ,// Write Control Data operation +output RStat ,// Read Status operation +output ScanStat ,// Scan Status operation +input Busy ,// Busy Signal +input LinkFail ,// Link Integrity Signal +input Nvalid ,// Invalid Status (qualifier for the valid scan result) +input [15:0] Prsd ,// Read Status Data (data read from the PHY) +input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register +input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register +input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data +); + + RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0008,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); +// RegCPUData U_0_032(CPU_rd_dout_h ,7'd032,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_033(Line_loop_en ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + RegCPUData U_0_034(Speed ,7'd034,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in); + +always @ (posedge Clk_reg or posedge Reset) + if (Reset) + CD_out <=0; + else if (!CSB&&WRB) + case (CA[7:1]) + 7'd00: CD_out<=Tx_Hwmark ; + 7'd01: CD_out<=Tx_Lwmark ; + 7'd02: CD_out<=pause_frame_send_en ; + 7'd03: CD_out<=pause_quanta_set ; + 7'd04: CD_out<=IFGset ; + 7'd05: CD_out<=FullDuplex ; + 7'd06: CD_out<=MaxRetry ; + 7'd07: CD_out<=MAC_tx_add_en ; + 7'd08: CD_out<=MAC_tx_add_prom_data ; + 7'd09: CD_out<=MAC_tx_add_prom_add ; + 7'd10: CD_out<=MAC_tx_add_prom_wr ; + 7'd11: CD_out<=tx_pause_en ; + 7'd12: CD_out<=xoff_cpu ; + 7'd13: CD_out<=xon_cpu ; + 7'd14: CD_out<=MAC_rx_add_chk_en ; + 7'd15: CD_out<=MAC_rx_add_prom_data ; + 7'd16: CD_out<=MAC_rx_add_prom_add ; + 7'd17: CD_out<=MAC_rx_add_prom_wr ; + 7'd18: CD_out<=broadcast_filter_en ; + 7'd19: CD_out<=broadcast_bucket_depth ; + 7'd20: CD_out<=broadcast_bucket_interval ; + 7'd21: CD_out<=RX_APPEND_CRC ; + 7'd22: CD_out<=Rx_Hwmark ; + 7'd23: CD_out<=Rx_Lwmark ; + 7'd24: CD_out<=CRC_chk_en ; + 7'd25: CD_out<=RX_IFG_SET ; + 7'd26: CD_out<=RX_MAX_LENGTH ; + 7'd27: CD_out<=RX_MIN_LENGTH ; + 7'd28: CD_out<=CPU_rd_addr ; + 7'd29: CD_out<=CPU_rd_apply ; + 7'd30: CD_out<=CPU_rd_grant ; + 7'd31: CD_out<=CPU_rd_dout[15:0] ; + 7'd32: CD_out<=CPU_rd_dout[31:16] ; + 7'd33: CD_out<=Line_loop_en ; + 7'd34: CD_out<=Speed ; + default: CD_out<=0 ; + endcase + else + CD_out<=0 ; + +endmodule + +module RegCPUData( +RegOut, +CA_reg_set, +RegInit, + +Reset, +Clk, +CWR_pulse, +CCSB, +CA_reg, +CD_in_reg +); +output[15:0] RegOut; +input[6:0] CA_reg_set; +input[15:0] RegInit; +// +input Reset; +input Clk; +input CWR_pulse; +input CCSB; +input[7:0] CA_reg; +input[15:0] CD_in_reg; +// +reg[15:0] RegOut; + +always @(posedge Reset or posedge Clk) + if(Reset) + RegOut <=RegInit; + else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0]) + RegOut <=CD_in_reg; + +endmodule diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Entries new file mode 100644 index 00000000..9487498a --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Entries @@ -0,0 +1 @@ +D/rtl_sim//// diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Repository new file mode 100644 index 00000000..cd76b955 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries new file mode 100644 index 00000000..110ed0af --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries @@ -0,0 +1 @@ +D/ncsim_sim//// diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Repository new file mode 100644 index 00000000..930bcb3d --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries new file mode 100644 index 00000000..08bef4ec --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries @@ -0,0 +1,6 @@ +D/bin//// +D/data//// +D/log//// +D/out//// +D/run//// +D/script//// diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Repository new file mode 100644 index 00000000..06f0c568 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Entries new file mode 100644 index 00000000..75c10e88 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Entries @@ -0,0 +1,12 @@ +/cds.lib/1.2/Thu Jan 19 14:07:56 2006// +/com.nc/1.2/Fri Jan 20 12:18:05 2006// +/config.ini/1.1/Tue Dec 13 12:54:51 2005// +/hdl.var/1.1/Tue Dec 13 12:54:51 2005// +/ip_32W_check.dll/1.1/Thu Jan 19 14:07:56 2006/-kb/ +/ip_32W_check_vpi.dll/1.1/Tue Dec 13 12:54:51 2005/-kb/ +/ip_32W_gen.dll/1.1/Thu Jan 19 14:07:56 2006/-kb/ +/ip_32W_gen_vpi.dll/1.1/Tue Dec 13 12:54:51 2005/-kb/ +/sim.nc/1.3/Fri Jan 20 12:18:05 2006// +/sim_only.nc/1.1/Thu Jan 19 14:07:56 2006// +/vlog.list/1.2/Thu Jan 19 14:07:56 2006// +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Repository new file mode 100644 index 00000000..f3861d09 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/cds.lib b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/cds.lib new file mode 100644 index 00000000..c8b8c7c8 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/cds.lib @@ -0,0 +1,2 @@ +DEFINE work ./worknc + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/com.nc b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/com.nc new file mode 100644 index 00000000..566452b8 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/com.nc @@ -0,0 +1,36 @@ +if test -d worknc +then +echo worknc is ready +else +mkdir worknc +echo worknc is created +fi + +ncvlog -f vlog.list -logfile ../log/ncvlog.log + +if test $? -ne 0 +then +echo compiling err occured... +exit 1 +fi + +ncelab work.tb_top -NEVERWARN -loadvpi ip_32W_gen:PLI_register -loadvpi ip_32W_check:PLI_register -snapshot work:snap -timescale 1ns/1ps -message -access +rw -logfile ../log/ncelab.log + +if test $? -ne 0 +then +echo ncelab err occured... +exit 1 +fi + +if test -f ../log/.sim_failed +then + echo "../log/.sim_failed log file has been removed!" + rm ../log/.sim_failed +fi + +if test -f ../log/sim_succeed +then + echo "../log/sim_succeed log file has been removed!" + rm ../log/sim_succeed +fi + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/config.ini b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/config.ini new file mode 100644 index 00000000..cbcc5a0d --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/config.ini @@ -0,0 +1,3 @@ +46,1500,1,0 + +#Pkt_begin_length,Pkt_end_length,Pkt_number,Random_en diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/hdl.var b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/hdl.var new file mode 100644 index 00000000..1899fcea --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/hdl.var @@ -0,0 +1 @@ +DEFINE WORK work diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll new file mode 100644 index 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diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim.nc b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim.nc new file mode 100644 index 00000000..6d38346a --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim.nc @@ -0,0 +1,37 @@ +if test -d worknc +then +echo worknc is ready +else +mkdir worknc +echo worknc is created +fi + +ncvlog -f vlog.list -logfile ../log/ncvlog.log + +if test $? -ne 0 +then +echo compiling err occured... +exit 1 +fi + +ncelab work.tb_top -NEVERWARN -loadvpi ip_32W_gen:PLI_register -loadvpi ip_32W_check:PLI_register -snapshot work:snap -timescale 1ns/1ps -message -access +rw -logfile ../log/ncelab.log + +if test $? -ne 0 +then +echo ncelab err occured... +exit 1 +fi + +if test -f ../log/.sim_failed +then + echo "../log/.sim_failed log file has been removed!" + rm ../log/.sim_failed +fi + +if test -f ../log/sim_succeed +then + echo "../log/sim_succeed log file has been removed!" + rm ../log/sim_succeed +fi + +ncsim work:snap $1 -UNBUFFERED -logfile ../log/ncsim.log -NOKEY diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim_only.nc b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim_only.nc new file mode 100644 index 00000000..feae8e7d --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim_only.nc @@ -0,0 +1,13 @@ +if test -f ../log/.sim_failed +then + echo "../log/.sim_failed log file has been removed!" + rm ../log/.sim_failed +fi + +if test -f ../log/sim_succeed +then + echo "../log/sim_succeed log file has been removed!" + rm ../log/sim_succeed +fi + +ncsim work:snap $1 -UNBUFFERED -logfile ../log/ncsim.log -NOKEY diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/vlog.list b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/vlog.list new file mode 100644 index 00000000..a937c843 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/vlog.list @@ -0,0 +1,41 @@ +../../../../rtl/verilog/header.v + +../../../../rtl/verilog/TECH/CLK_SWITCH.v +../../../../rtl/verilog/TECH/CLK_DIV2.v +../../../../rtl/verilog/TECH/duram.v + +../../../../rtl/verilog/MAC_tx/MAC_tx_FF.v +../../../../rtl/verilog/MAC_tx/Ramdon_gen.v +../../../../rtl/verilog/MAC_tx/CRC_gen.v +../../../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v +../../../../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v +../../../../rtl/verilog/MAC_tx/flow_ctrl.v + +../../../../rtl/verilog/MAC_rx/CRC_chk.v +../../../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v +../../../../rtl/verilog/MAC_rx/MAC_rx_FF.v +../../../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v +../../../../rtl/verilog/MAC_rx/Broadcast_filter.v + +../../../../rtl/verilog/miim/eth_clockgen.v +../../../../rtl/verilog/miim/eth_outputcontrol.v +../../../../rtl/verilog/miim/eth_shiftreg.v + +../../../../rtl/verilog/RMON/RMON_addr_gen.v +../../../../rtl/verilog/RMON/RMON_ctrl.v +../../../../rtl/verilog/RMON/RMON_dpram.v + +../../../../rtl/verilog/RMON.v +../../../../rtl/verilog/MAC_rx.v +../../../../rtl/verilog/MAC_tx.v +../../../../rtl/verilog/eth_miim.v +../../../../rtl/verilog/MAC_top.v +../../../../rtl/verilog/Phy_int.v +../../../../rtl/verilog/Clk_ctrl.v +../../../../rtl/verilog/Reg_int.v + +../../../../bench/verilog/altera_mf.v +../../../../bench/verilog/Phy_sim.v +../../../../bench/verilog/User_int_sim.v +../../../../bench/verilog/host_sim.v +../../../../bench/verilog/tb_top.v diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec new file mode 100644 index 00000000..36418359 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec @@ -0,0 +1 @@ +01200004 diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec new file mode 100644 index 00000000..b4f602f8 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec @@ -0,0 +1 @@ +01200002 diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec new file mode 100644 index 00000000..a3b94187 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec @@ -0,0 +1 @@ +01200001 diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/46-50.ini b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/46-50.ini new file mode 100644 index 00000000..313b49c7 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/46-50.ini @@ -0,0 +1 @@ +46,50,1,0 diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CPU.vec b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CPU.vec new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Entries new file mode 100644 index 00000000..0df4c079 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Entries @@ -0,0 +1,11 @@ +/1000Mbps_duplex.vec/1.1/Thu Jan 19 14:07:57 2006// +/100Mbps_duplex.vec/1.1/Thu Jan 19 14:07:57 2006// +/10Mbps_duplex.vec/1.1/Thu Jan 19 14:07:57 2006// +/46-50.ini/1.1/Thu Jan 19 14:07:57 2006// +/CPU.vec/1.1/Thu Jan 19 14:07:57 2006// +/batch.dat/1.1/Thu Jan 19 14:07:57 2006// +/config.ini/1.2/Sun Jun 25 04:58:57 2006// +/flow_ctrl.vec/1.1/Thu Jan 19 14:07:57 2006// +/source_mac_replace.vec/1.1/Thu Jan 19 14:07:57 2006// +/target_mac_check.vec/1.1/Thu Jan 19 14:07:57 2006// +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Repository new file mode 100644 index 00000000..cc9effe3 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/batch.dat b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/batch.dat new file mode 100644 index 00000000..a37f5040 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/batch.dat @@ -0,0 +1,3 @@ +{1000Mbps mode 46-80 length packet testcase} 46-50.ini 1000Mbps_duplex.vec +{100 Mbps mode 46-50 length packet testcase} 46-50.ini 100Mbps_duplex.vec +{10 Mbps mode 46-50 length packet testcase} 46-50.ini 10Mbps_duplex.vec diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/config.ini b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/config.ini new file mode 100644 index 00000000..cd64f169 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/config.ini @@ -0,0 +1 @@ +46,1500,1,0,0 diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec new file mode 100644 index 00000000..978689ab --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec @@ -0,0 +1,4 @@ +04020001 +0403000a +040b000a +040c0001 diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec new file mode 100644 index 00000000..f1f49894 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec @@ -0,0 +1,24 @@ +12070001 +12080030 +120a0001 +180a0000 +18080031 +18090001 +180a0001 +180a0000 +18080032 +18090002 +180a0001 +180a0000 +18080033 +18090003 +180a0001 +180a0000 +18080034 +18090004 +180a0001 +180a0000 +18080035 +18090005 +180a0001 +180a0000 diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec new file mode 100644 index 00000000..71401b15 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec @@ -0,0 +1,25 @@ +190e0001 +190f0010 +19100000 +19110001 +19110000 +190f0011 +19100001 +19110001 +19110000 +190f0012 +19100002 +19110001 +19110000 +190f0013 +19100003 +19110001 +19110000 +190f0014 +19100004 +19110001 +19110000 +190f0016 +19100005 +19110001 +19110000 \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Entries new file mode 100644 index 00000000..85b414b7 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Entries @@ -0,0 +1,2 @@ +/ncsim.log/1.3/Fri Nov 17 17:53:07 2006// +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Repository new file mode 100644 index 00000000..06099086 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/ncsim.log b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/ncsim.log new file mode 100644 index 00000000..c2ede538 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/ncsim.log @@ -0,0 +1,245 @@ +ncsim: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc. +////////////////////////////////////////////////////////////////////// +//// +//// $ip_32W_gen is used to generate stimulus with 32bit +//// width ip packet data flow. +//// The only parameter is config.ini file that is used to +//// control the generated packet data flow. +//// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +//// StartOfSim callback printing info +////////////////////////////////////////////////////////////////////// +ncsim> run + +the NO. 0001 IP Length is:0046 CRC-32check OK! +the NO. 0002 IP Length is:0047 CRC-32check OK! +the NO. 0003 IP Length is:0048 CRC-32check OK! +the NO. 0004 IP Length is:0049 CRC-32check OK! +the NO. 0005 IP Length is:0050 CRC-32check OK! +the NO. 0006 IP Length is:0051 CRC-32check OK! +the NO. 0007 IP Length is:0052 CRC-32check OK! +the NO. 0008 IP Length is:0053 CRC-32check OK! +the NO. 0009 IP Length is:0054 CRC-32check OK! +the NO. 000a IP Length is:0055 CRC-32check OK! +the NO. 000b IP Length is:0056 CRC-32check OK! +the NO. 000c IP Length is:0057 CRC-32check OK! +the NO. 000d IP Length is:0058 CRC-32check OK! +the NO. 000e IP Length is:0059 CRC-32check OK! +the NO. 000f IP Length is:0060 CRC-32check OK! +the NO. 0010 IP Length is:0061 CRC-32check OK! +the NO. 0011 IP Length is:0062 CRC-32check OK! +the NO. 0012 IP Length is:0063 CRC-32check OK! +the NO. 0013 IP Length is:0064 CRC-32check OK! +the NO. 0014 IP Length is:0065 CRC-32check OK! +the NO. 0015 IP Length is:0066 CRC-32check OK! +the NO. 0016 IP Length is:0067 CRC-32check OK! +the NO. 0017 IP Length is:0068 CRC-32check OK! +the NO. 0018 IP Length is:0069 CRC-32check OK! +the NO. 0019 IP Length is:0070 CRC-32check OK! +the NO. 001a IP Length is:0071 CRC-32check OK! +the NO. 001b IP Length is:0072 CRC-32check OK! +the NO. 001c IP Length is:0073 CRC-32check OK! +the NO. 001d IP Length is:0074 CRC-32check OK! +the NO. 001e IP Length is:0075 CRC-32check OK! +the NO. 001f IP Length is:0076 CRC-32check OK! +the NO. 0020 IP Length is:0077 CRC-32check OK! +the NO. 0021 IP Length is:0078 CRC-32check OK! +the NO. 0022 IP Length is:0079 CRC-32check OK! +the NO. 0023 IP Length is:0080 CRC-32check OK! +the NO. 0024 IP Length is:0081 CRC-32check OK! +the NO. 0025 IP Length is:0082 CRC-32check OK! +the NO. 0026 IP Length is:0083 CRC-32check OK! +the NO. 0027 IP Length is:0084 CRC-32check OK! +the NO. 0028 IP Length is:0085 CRC-32check OK! +the NO. 0029 IP Length is:0086 CRC-32check OK! +the NO. 002a IP Length is:0087 CRC-32check OK! +the NO. 002b IP Length is:0088 CRC-32check OK! +the NO. 002c IP Length is:0089 CRC-32check OK! +the NO. 002d IP Length is:0090 CRC-32check OK! +the NO. 002e IP Length is:0091 CRC-32check OK! +the NO. 002f IP Length is:0092 CRC-32check OK! +the NO. 0030 IP Length is:0093 CRC-32check OK! +the NO. 0031 IP Length is:0094 CRC-32check OK! +the NO. 0032 IP Length is:0095 CRC-32check OK! +the NO. 0033 IP Length is:0096 CRC-32check OK! +the NO. 0034 IP Length is:0097 CRC-32check OK! +the NO. 0035 IP Length is:0098 CRC-32check OK! +the NO. 0036 IP Length is:0099 CRC-32check OK! +the NO. 0037 IP Length is:0100 CRC-32check OK! +the NO. 0038 IP Length is:0101 CRC-32check OK! +the NO. 0039 IP Length is:0102 CRC-32check OK! +the NO. 003a IP Length is:0103 CRC-32check OK! +the NO. 003b IP Length is:0104 CRC-32check OK! +the NO. 003c IP Length is:0105 CRC-32check OK! +the NO. 003d IP Length is:0106 CRC-32check OK! +the NO. 003e IP Length is:0107 CRC-32check OK! +the NO. 003f IP Length is:0108 CRC-32check OK! +the NO. 0040 IP Length is:0109 CRC-32check OK! +the NO. 0041 IP Length is:0110 CRC-32check OK! +the NO. 0042 IP Length is:0111 CRC-32check OK! +the NO. 0043 IP Length is:0112 CRC-32check OK! +the NO. 0044 IP Length is:0113 CRC-32check OK! +the NO. 0045 IP Length is:0114 CRC-32check OK! +the NO. 0046 IP Length is:0115 CRC-32check OK! +the NO. 0047 IP Length is:0116 CRC-32check OK! +the NO. 0048 IP Length is:0117 CRC-32check OK! +the NO. 0049 IP Length is:0118 CRC-32check OK! +the NO. 004a IP Length is:0119 CRC-32check OK! +the NO. 004b IP Length is:0120 CRC-32check OK! +the NO. 004c IP Length is:0121 CRC-32check OK! +the NO. 004d IP Length is:0122 CRC-32check OK! +the NO. 004e IP Length is:0123 CRC-32check OK! +the NO. 004f IP Length is:0124 CRC-32check OK! +the NO. 0050 IP Length is:0125 CRC-32check OK! +the NO. 0051 IP Length is:0126 CRC-32check OK! +the NO. 0052 IP Length is:0127 CRC-32check OK! +the NO. 0053 IP Length is:0128 CRC-32check OK! +the NO. 0054 IP Length is:0129 CRC-32check OK! +the NO. 0055 IP Length is:0130 CRC-32check OK! +the NO. 0056 IP Length is:0131 CRC-32check OK! +the NO. 0057 IP Length is:0132 CRC-32check OK! +the NO. 0058 IP Length is:0133 CRC-32check OK! +the NO. 0059 IP Length is:0134 CRC-32check OK! +the NO. 005a IP Length is:0135 CRC-32check OK! +the NO. 005b IP Length is:0136 CRC-32check OK! +the NO. 005c IP Length is:0137 CRC-32check OK! +the NO. 005d IP Length is:0138 CRC-32check OK! +the NO. 005e IP Length is:0139 CRC-32check OK! +the NO. 005f IP Length is:0140 CRC-32check OK! +the NO. 0060 IP Length is:0141 CRC-32check OK! +the NO. 0061 IP Length is:0142 CRC-32check OK! +the NO. 0062 IP Length is:0143 CRC-32check OK! +the NO. 0063 IP Length is:0144 CRC-32check OK! +the NO. 0064 IP Length is:0145 CRC-32check OK! +the NO. 0065 IP Length is:0146 CRC-32check OK! +the NO. 0066 IP Length is:0147 CRC-32check OK! +the NO. 0067 IP Length is:0148 CRC-32check OK! +the NO. 0068 IP Length is:0149 CRC-32check OK! +the NO. 0069 IP Length is:0150 CRC-32check OK! +the NO. 006a IP Length is:0151 CRC-32check OK! +the NO. 006b IP Length is:0152 CRC-32check OK! +the NO. 006c IP Length is:0153 CRC-32check OK! +the NO. 006d IP Length is:0154 CRC-32check OK! +the NO. 006e IP Length is:0155 CRC-32check OK! +the NO. 006f IP Length is:0156 CRC-32check OK! +the NO. 0070 IP Length is:0157 CRC-32check OK! +the NO. 0071 IP Length is:0158 CRC-32check OK! +the NO. 0072 IP Length is:0159 CRC-32check OK! +the NO. 0073 IP Length is:0160 CRC-32check OK! +the NO. 0074 IP Length is:0161 CRC-32check OK! +the NO. 0075 IP Length is:0162 CRC-32check OK! +the NO. 0076 IP Length is:0163 CRC-32check OK! +the NO. 0077 IP Length is:0164 CRC-32check OK! +the NO. 0078 IP Length is:0165 CRC-32check OK! +the NO. 0079 IP Length is:0166 CRC-32check OK! +the NO. 007a IP Length is:0167 CRC-32check OK! +the NO. 007b IP Length is:0168 CRC-32check OK! +the NO. 007c IP Length is:0169 CRC-32check OK! +the NO. 007d IP Length is:0170 CRC-32check OK! +the NO. 007e IP Length is:0171 CRC-32check OK! +the NO. 007f IP Length is:0172 CRC-32check OK! +the NO. 0080 IP Length is:0173 CRC-32check OK! +the NO. 0081 IP Length is:0174 CRC-32check OK! +the NO. 0082 IP Length is:0175 CRC-32check OK! +the NO. 0083 IP Length is:0176 CRC-32check OK! +the NO. 0084 IP Length is:0177 CRC-32check OK! +the NO. 0085 IP Length is:0178 CRC-32check OK! +the NO. 0086 IP Length is:0179 CRC-32check OK! +the NO. 0087 IP Length is:0180 CRC-32check OK! +the NO. 0088 IP Length is:0181 CRC-32check OK! +the NO. 0089 IP Length is:0182 CRC-32check OK! +the NO. 008a IP Length is:0183 CRC-32check OK! +the NO. 008b IP Length is:0184 CRC-32check OK! +the NO. 008c IP Length is:0185 CRC-32check OK! +the NO. 008d IP Length is:0186 CRC-32check OK! +the NO. 008e IP Length is:0187 CRC-32check OK! +the NO. 008f IP Length is:0188 CRC-32check OK! +the NO. 0090 IP Length is:0189 CRC-32check OK! +the NO. 0091 IP Length is:0190 CRC-32check OK! +the NO. 0092 IP Length is:0191 CRC-32check OK! +the NO. 0093 IP Length is:0192 CRC-32check OK! +the NO. 0094 IP Length is:0193 CRC-32check OK! +the NO. 0095 IP Length is:0194 CRC-32check OK! +the NO. 0096 IP Length is:0195 CRC-32check OK! +the NO. 0097 IP Length is:0196 CRC-32check OK! +the NO. 0098 IP Length is:0197 CRC-32check OK! +the NO. 0099 IP Length is:0198 CRC-32check OK! +the NO. 009a IP Length is:0199 CRC-32check OK! +the NO. 009b IP Length is:0200 CRC-32check OK! +the NO. 009c IP Length is:0201 CRC-32check OK! +the NO. 009d IP Length is:0202 CRC-32check OK! +the NO. 009e IP Length is:0203 CRC-32check OK! +the NO. 009f IP Length is:0204 CRC-32check OK! +the NO. 00a0 IP Length is:0205 CRC-32check OK! +the NO. 00a1 IP Length is:0206 CRC-32check OK! +the NO. 00a2 IP Length is:0207 CRC-32check OK! +the NO. 00a3 IP Length is:0208 CRC-32check OK! +the NO. 00a4 IP Length is:0209 CRC-32check OK! +the NO. 00a5 IP Length is:0210 CRC-32check OK! +the NO. 00a6 IP Length is:0211 CRC-32check OK! +the NO. 00a7 IP Length is:0212 CRC-32check OK! +the NO. 00a8 IP Length is:0213 CRC-32check OK! +the NO. 00a9 IP Length is:0214 CRC-32check OK! +the NO. 00aa IP Length is:0215 CRC-32check OK! +the NO. 00ab IP Length is:0216 CRC-32check OK! +the NO. 00ac IP Length is:0217 CRC-32check OK! +the NO. 00ad IP Length is:0218 CRC-32check OK! +the NO. 00ae IP Length is:0219 CRC-32check OK! +the NO. 00af IP Length is:0220 CRC-32check OK! +the NO. 00b0 IP Length is:0221 CRC-32check OK! +the NO. 00b1 IP Length is:0222 CRC-32check OK! +the NO. 00b2 IP Length is:0223 CRC-32check OK! +the NO. 00b3 IP Length is:0224 CRC-32check OK! +the NO. 00b4 IP Length is:0225 CRC-32check OK! +the NO. 00b5 IP Length is:0226 CRC-32check OK! +the NO. 00b6 IP Length is:0227 CRC-32check OK! +the NO. 00b7 IP Length is:0228 CRC-32check OK! +the NO. 00b8 IP Length is:0229 CRC-32check OK! +the NO. 00b9 IP Length is:0230 CRC-32check OK! +the NO. 00ba IP Length is:0231 CRC-32check OK! +the NO. 00bb IP Length is:0232 CRC-32check OK! +the NO. 00bc IP Length is:0233 CRC-32check OK! +the NO. 00bd IP Length is:0234 CRC-32check OK! +the NO. 00be IP Length is:0235 CRC-32check OK! +the NO. 00bf IP Length is:0236 CRC-32check OK! +the NO. 00c0 IP Length is:0237 CRC-32check OK! +the NO. 00c1 IP Length is:0238 CRC-32check OK! +the NO. 00c2 IP Length is:0239 CRC-32check OK! +the NO. 00c3 IP Length is:0240 CRC-32check OK! +the NO. 00c4 IP Length is:0241 CRC-32check OK! +the NO. 00c5 IP Length is:0242 CRC-32check OK! +the NO. 00c6 IP Length is:0243 CRC-32check OK! +the NO. 00c7 IP Length is:0244 CRC-32check OK! +the NO. 00c8 IP Length is:0245 CRC-32check OK! +the NO. 00c9 IP Length is:0246 CRC-32check OK! +the NO. 00ca IP Length is:0247 CRC-32check OK! +the NO. 00cb IP Length is:0248 CRC-32check OK! +the NO. 00cc IP Length is:0249 CRC-32check OK! +the NO. 00cd IP Length is:0250 CRC-32check OK! +the NO. 00ce IP Length is:0251 CRC-32check OK! +the NO. 00cf IP Length is:0252 CRC-32check OK! +the NO. 00d0 IP Length is:0253 CRC-32check OK! +the NO. 00d1 IP Length is:0254 CRC-32check OK! +the NO. 00d2 IP Length is:0255 CRC-32check OK! +the NO. 00d3 IP Length is:0256 CRC-32check OK! +the NO. 00d4 IP Length is:0257 CRC-32check OK! +the NO. 00d5 IP Length is:0258 CRC-32check OK! +the NO. 00d6 IP Length is:0259 CRC-32check OK! +the NO. 00d7 IP Length is:0260 CRC-32check OK! +the NO. 00d8 IP Length is:0261 CRC-32check OK! +the NO. 00d9 IP Length is:0262 CRC-32check OK! +the NO. 00da IP Length is:0263 CRC-32check OK! +the NO. 00db IP Length is:0264 CRC-32check OK! +the NO. 00dc IP Length is:0265 CRC-32check OK! +the NO. 00dd IP Length is:0266 CRC-32check OK! +the NO. 00de IP Length is:0267 CRC-32check OK! +the NO. 00df IP Length is:0268 CRC-32check OK! +the NO. 00e0 IP Length is:0269 CRC-32check OK! +the NO. 00e1 IP Length is:0270 CRC-32check OK! +the NO. 00e2 IP Length is:0271 CRC-32check OK! +the NO. 00e3 IP Length is:0272 CRC-32check OK! +the NO. 00e4 IP Length is:0273 CRC-32check OK! +the NO. 00e5 IP Length is:0274 CRC-32check OK! +the NO. 00e6 IP Length is:0275 CRC-32check OK!Simulation interrupted at 367372 NS + 0 +ncsim> exit diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Repository new file mode 100644 index 00000000..46dd9edc --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Entries new file mode 100644 index 00000000..17848105 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Repository new file mode 100644 index 00000000..90f69920 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Entries new file mode 100644 index 00000000..4ca22003 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Entries @@ -0,0 +1,9 @@ +/batch_mode.tcl/1.2/Thu Apr 6 13:12:05 2006// +/filesel.tcl/1.1/Thu Jan 19 16:18:28 2006// +/run.tcl/1.1/Thu Jan 19 16:18:28 2006// +/run_proc.tcl/1.2/Thu Apr 6 13:12:05 2006// +/set_reg_data.tcl/1.3/Thu Apr 6 13:12:05 2006// +/set_stimulus.tcl/1.2/Thu Apr 6 13:12:05 2006// +/start_verify.tcl/1.2/Thu Apr 6 13:12:05 2006// +/user_lib.tcl/1.2/Thu Apr 6 13:12:05 2006// +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Repository new file mode 100644 index 00000000..7e86a150 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl new file mode 100644 index 00000000..9185aded --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl @@ -0,0 +1,148 @@ +proc batch_mode {} { +variable i +variable index empty +variable batch_data +set namelist \ +{- Description Stimulus RegVector} +############################################################################### + toplevel .b + wm title .b "Setting Reg Data" + focus .b + frame .b.f100 + + set lth1 20 + set lth2 15 + set lth3 15 + cd ../data + if {[catch {open batch.dat r} fileid]} { + break + } else { + set batch_data {} + gets $fileid line + while {[eof $fileid]==0} { + lappend batch_data $line + if {[string length [lindex $line 0]] > $lth1 } { + set lth1 [string length [lindex $line 0]] + } + if {[string length [lindex $line 1]] > $lth2 } { + set lth2 [string length [lindex $line 1]] + } + if {[string length [lindex $line 2]] > $lth3 } { + set lth3 [string length [lindex $line 2]] + } + gets $fileid line + } + close $fileid + } + + label .b.f100.l1 -text [lindex $namelist 0] -fg blue -width 5 + label .b.f100.l2 -text [lindex $namelist 1] -fg blue -width [expr $lth1 +5] + label .b.f100.l3 -text [lindex $namelist 2] -fg blue -width [expr $lth2 +5] + label .b.f100.l4 -text [lindex $namelist 3] -fg blue -width [expr $lth3 +5] + pack .b.f100 + pack .b.f100.l1 .b.f100.l2 .b.f100.l3 .b.f100.l4 -side left + + set i 0 + foreach line $batch_data { + frame .b.f$i + set tmp [expr $i+1] + checkbutton .b.f$i.c -variable check$i -text $tmp -width 5 + label .b.f$i.l1 -text [lindex $line 0] -width $lth1 + button .b.f$i.b1 -text "Change" -width 5 -command [list ChangeDescript .b.f$i.l1 $i 0] + label .b.f$i.l2 -text [lindex $line 1] -width $lth2 + button .b.f$i.b2 -text "Change" -width 5 -command [list ChangeLabel .b.f$i.l2 $i 1] + label .b.f$i.l3 -text [lindex $line 2] -width $lth3 + button .b.f$i.b3 -text "Change" -width 5 -command [list ChangeLabel .b.f$i.l3 $i 2] + pack .b.f$i + pack .b.f$i.c .b.f$i.l1 .b.f$i.b1 .b.f$i.l2 .b.f$i.b2 .b.f$i.l3 .b.f$i.b3 -side left + incr i + } + + + frame .b.f102 + button .b.f102.b1 -text "Start Verify" -width 10 + button .b.f102.b2 -text "Save" -width 10 -command {save_batch_data} + button .b.f102.b3 -text "Exit" -width 10 -command {destroy .b} + pack .b.f102 + pack .b.f102.b1 .b.f102.b2 .b.f102.b3 -side left + bind .b.f102.b1 {create_index $i} + bind .b.f102.b1 {start_verify 1 $index} +} + +proc create_index {i} { + global index + set index empty + set sim_times 0 + save_batch_data + for {set c 0} {$c < $i} {incr c} { + upvar 1 check$c tmp + if {$tmp==1 && $sim_times==0} { + set index $c + incr sim_times + } elseif {$tmp==1} { + lappend index $c + incr sim_times + } + } +} + +proc ChangeLabel {target_label y x} { + global batch_data + global fileselect + fileselect + tkwait window .fileSelectWindow + if {$fileselect(canceled)==1} { + return + } elseif {$fileselect(selectedfile)==""} { + warning_message "file have not been selected!" + } else { + $target_label config -text $fileselect(selectedfile) + set line [lindex $batch_data $y] + set line [lreplace $line $x $x $fileselect(selectedfile)] + set batch_data [lreplace $batch_data $y $y $line] + } +} + +proc save_batch_data {} { + global batch_data + if {[catch {open batch.dat w} fileid]} { + break + } else { + foreach line $batch_data { + puts $fileid $line + } + close $fileid + } +} + +proc ChangeDescript {target_label y x} { + global batch_data + variable value + variable target + variable newy + variable newx + toplevel .tmp + focus .tmp + set target $target_label + set newy $y + set newx $x + entry .tmp.en -width 20 -textvariable value + button .tmp.b -width 5 -text "Apply" -command {destroy .tmp} + button .tmp.b1 -width 5 -text "quit" + bind .tmp.b {ChangeDescriptApply $target $newy $newx $value} + + + pack .tmp.en .tmp.b +} + +proc ChangeDescriptApply {target_label y x value} { + global batch_data + if {$value==""} { + warning_message "Description can not be empty" + } else { + $target_label config -text $value + set line [lindex $batch_data $y] + set line [lreplace $line 0 0 $value] + set batch_data [lreplace $batch_data $y $y $line] + } +} \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/filesel.tcl b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/filesel.tcl new file mode 100644 index 00000000..c300a440 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/filesel.tcl @@ -0,0 +1,325 @@ +# +# fileselect.tcl -- +# simple file selector. +# +# Mario Jorge Silva msilva@cs.Berkeley.EDU +# University of California Berkeley Ph: +1(510)642-8248 +# Computer Science Division, 571 Evans Hall Fax: +1(510)642-5775 +# Berkeley CA 94720 +# + +# Layout: +# +# file: +----+ +# ____________________ | OK | +# +----+ +# +# +------------------+ Cancel +# | .. |S +# | file1 |c +# | file2 |r +# | |b +# | filen |a +# | |r +# +------------------+ +# currrent-directory +# +# Copyright 1993 Regents of the University of California +# Permission to use, copy, modify, and distribute this +# software and its documentation for any purpose and without +# fee is hereby granted, provided that this copyright +# notice appears in all copies. The University of California +# makes no representations about the suitability of this +# software for any purpose. It is provided "as is" without +# express or implied warranty. +# + +# Copyright 1996 + +# Slight modifications to and adoption to Tk4.0 were made to this +# fileselectionbox code by Lakshmi Sastry, Rutherford Appleton Laboratory, +# chilton, Didcot, OXON, OX11 0QX, UK. + +# You can now type in a non-existing file name as well. This file name is +# returned for the application to open a new file to write to + +# AGOCG Tcl/Tk Cookbook +# Authors + +# Lakshmi Sastry +# Computing and Information Systems Department +# Rutherford Appleton Laboratory, Chilton, Didcot. OX11 0QX +# lakshmi.sastry@rl.ac.uk + +# and + +# Venkat VSS Sastry +# Department of Applied Mathematics and Operational Research +# Cranfield University, RMCS Shrivenham, Swindon, SN6 8LA +# sastry@rmcs.cran.ac.uk + +# Permission to use, copy, modify, and distribute this +# software and its documentation for any purpose and without +# fee is hereby granted, provided that this copyright +# notice appears in all copies. + +# The authors, RAL, RMCS Shrivenham, Cranfield University and AGOCG +# make no representations about the suitability of this +# software for any purpose. It is provided "as is" without +# express or implied warranty. Likewise they accept no responsibility +# whatsoever for any public domain software modules used (which are +# hereby acknowledged) in this software + + +# names starting with "fileselect" are reserved by this module +# no other names used. + +# use the "option" command for further configuration + +option add *Listbox*font \ + "-*-helvetica-medium-r-normal-*-12-*-*-*-p-*-iso8859-1" startupFile +option add *Entry*font \ + "-*-helvetica-medium-r-normal-*-12-*-*-*-p-*-iso8859-1" startupFile +option add *Label*font \ + "-*-helvetica-medium-r-normal-*-12-*-*-*-p-*-iso8859-1" startupFile + + +# this is the default proc called when "OK" is pressed +# to indicate yours, give it as the first arg to "fileselect" + +proc fileselect.default.cmd {f} { +global fileselect +set fileselect(selectedfile) $f +set fileselect(canceled) 0 +#puts stderr "selected file $f" + +} + + +# this is the default proc called when error is detected +# indicate your own pro as an argument to fileselect + +proc fileselect.default.errorHandler {errorMessage} { + puts stdout "error: $errorMessage" + catch { cd ~ } +} + +# this is the proc that creates the file selector box + +proc fileselect { + {cmd fileselect.default.cmd} + {purpose "Open file:"} + {w .fileSelectWindow} + {errorHandler fileselect.default.errorHandler}} { + + catch {destroy $w} + + toplevel $w + grab $w + wm title $w "Select File" + + + # path independent names for the widgets + global fileselect + global selected + set fileselect(entry) $w.file.eframe.entry + set fileselect(list) $w.file.sframe.list + set fileselect(scroll) $w.file.sframe.scroll + set fileselect(ok) $w.bframe.okframe.ok + set fileselect(cancel) $w.bframe.cancel + set fileselect(dirlabel) $w.file.dirlabel + + # widgets + frame $w.file -bd 10 + frame $w.bframe -bd 10 + pack append $w \ + $w.file {left filly} \ + $w.bframe {left expand frame n} + + frame $w.file.eframe + frame $w.file.sframe + label $w.file.dirlabel -anchor e -width 24 -text [pwd] + + pack append $w.file \ + $w.file.eframe {top frame w} \ + $w.file.sframe {top fillx} \ + $w.file.dirlabel {top frame w} + + + label $w.file.eframe.label -anchor w -width 24 -text $purpose + entry $w.file.eframe.entry -relief sunken + + pack append $w.file.eframe \ + $w.file.eframe.label {top expand frame w} \ + $w.file.eframe.entry {top fillx frame w} + + + scrollbar $w.file.sframe.yscroll -relief sunken \ + -command "$w.file.sframe.list yview" + listbox $w.file.sframe.list -relief sunken -selectmode single \ + -yscroll "$w.file.sframe.yscroll set" + #$fileselect(list) configure -selectmode single + pack append $w.file.sframe \ + $w.file.sframe.yscroll {right filly} \ + $w.file.sframe.list {left expand fill} + + # buttons + frame $w.bframe.okframe -borderwidth 2 -relief sunken + + button $w.bframe.okframe.ok -text OK -relief raised -padx 10 \ + -command "fileselect.ok.cmd $w $cmd $errorHandler" + + button $w.bframe.cancel -text cancel -relief raised -padx 10 \ + -command "fileselect.cancel.cmd $w" + pack append $w.bframe.okframe $w.bframe.okframe.ok {padx 10 pady 10} + + pack append $w.bframe $w.bframe.okframe {expand padx 20 pady 20}\ + $w.bframe.cancel {top} + + # Fill the listbox with a list of the files in the directory (run + # the "/bin/ls" command to get that information). + # to not display the "." files, remove the -a option and fileselect + # will still work + + $fileselect(list) insert end ".." + foreach i [exec ls -a [pwd]] { + if {[string compare $i "."] != 0 && \ + [string compare $i ".."] != 0 } { + $fileselect(list) insert end $i + } + } + + # Set up bindings for the browser. + bind $fileselect(entry) {eval $fileselect(ok) invoke} + bind $fileselect(entry) {eval $fileselect(cancel) invoke} + + bind $fileselect(list) { + # puts stderr "button 1 release" + set x [$fileselect(list) curselection] + $fileselect(entry) delete 0 end + $fileselect(entry) insert 0 [%W get [%W nearest %y]] + } + + bind $fileselect(list) { + set x [$fileselect(list) curselection] + $fileselect(entry) delete 0 end + $fileselect(entry) insert 0 [%W get [%W nearest %y]] + } + + bind $fileselect(list) { + # puts stderr "double button 1" + set x [$fileselect(list) curselection] + $fileselect(entry) delete 0 end + $fileselect(entry) insert 0 [%W get [%W nearest %y]] + $fileselect(ok) invoke + } + + bind $fileselect(list) { + set x [$fileselect(list) curselection] + $fileselect(entry) delete 0 end + $fileselect(entry) insert 0 [%W get [%W nearest %y]] + $fileselect(ok) invoke + } + + # set kbd focus to entry widget + + focus $fileselect(entry) + +} + + +# auxiliary button procedures + +proc fileselect.cancel.cmd {w} { + # puts stderr "Cancel" + global fileselect + set fileselect(canceled) 1 + destroy $w +} + +proc fileselect.ok.cmd {w cmd errorHandler} { + global fileselect + global selected + set selected [$fileselect(entry) get] + # some nasty file names may cause "file isdirectory" to return an error + set sts [catch { + file isdirectory $selected + } errorMessage ] + + if { $sts != 0 } then { + $errorHandler $errorMessage + destroy $w + return + + } + + # clean the text entry and prepare the list + $fileselect(entry) delete 0 end + $fileselect(list) delete 0 end + $fileselect(list) insert end ".." + + # perform globbing on the selection. + # If globing returns an error (no match) check if a non-null name is + # entered. If name string is non-empty return it as a new file name + # else give an error message. + # If resulting list length > 1, put the list on the file listbox and return + # If globing expands to a list of filenames in multiple directories, + # the indicated regexp is invalid and the error handler is called instead. +set globlist 0 + + set sts [catch { + set globlist [glob [list $selected]] + } errorMessage ] + + if { $sts != 0 } then { + if { [llength $globlist] == 1 } { + destroy $w + $cmd $selected + return + } else { + + $errorHandler $errorMessage + destroy $w + return + + } + + + } + + if {[llength $globlist] > 1} { + if {[regexp "/" $globlist] != 0} { + $errorHandler [list "Invalid regular expression, " $selected, "."] + destroy $w + return + } + foreach i $globlist { + if {[string compare $i "."] != 0 && \ + [string compare $i ".."] != 0} { + $fileselect(list) insert end $i + } + } + return + } + + # selection may be a directory. Expand it. + + if {[file isdirectory $selected] != 0} { + cd $selected + set dir [pwd] + $fileselect(dirlabel) configure -text $dir + + foreach i [exec ls -a $dir] { + if {[string compare $i "."] != 0 && \ + [string compare $i ".."] != 0} { + $fileselect(list) insert end $i + } + } + return + } + + destroy $w + $cmd $selected + +} + diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run.tcl b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run.tcl new file mode 100644 index 00000000..ac8a307d --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run.tcl @@ -0,0 +1,26 @@ +source user_lib.tcl +source set_stimulus.tcl +source set_reg_data.tcl +source start_verify.tcl +source batch_mode.tcl +source filesel.tcl + + +wm title . "main" +frame .frame +button .frame.b1 -width 20 -text "set_stimulus" +button .frame.b2 -width 20 -text "set_cpu_data" +button .frame.b3 -width 20 -text "start_verify" +button .frame.b4 -width 20 -text "batch_mode" +button .frame.b40 -width 20 -text "exit" + +bind .frame.b1 {set_stimulus} +bind .frame.b2 {set_reg_data} +bind .frame.b3 {start_verify 0 empty} +bind .frame.b4 {batch_mode} +bind .frame.b40 {exit} + + +pack .frame .frame.b1 .frame.b2 .frame.b3 .frame.b4 .frame.b40 + + \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run_proc.tcl b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run_proc.tcl new file mode 100644 index 00000000..294cb2c7 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run_proc.tcl @@ -0,0 +1,27 @@ +proc run_proc {} { +source user_lib.tcl +source set_stimulus.tcl +source set_reg_data.tcl +source start_verify.tcl +source batch_mode.tcl +source filesel.tcl + +toplevel .frame +focus .frame +wm title .frame "main" +button .frame.b1 -width 20 -text "set_stimulus" +button .frame.b2 -width 20 -text "set_cpu_data" +button .frame.b3 -width 20 -text "start_verify" +button .frame.b4 -width 20 -text "batch_mode" +button .frame.b40 -width 20 -text "exit" -command {cd ../../../../ ;destroy .frame} + +bind .frame.b1 {set_stimulus} +bind .frame.b2 {set_reg_data} +bind .frame.b3 {start_verify 0 empty} +bind .frame.b4 {batch_mode} + + + +pack .frame.b1 .frame.b2 .frame.b3 .frame.b4 .frame.b40 + +} \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl new file mode 100644 index 00000000..b4bfae35 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl @@ -0,0 +1,192 @@ +proc set_reg_data {} { +variable help_strings +variable RegVector +variable datalist +set help_strings { +Set Reg Data: + The verifcation system will config DUT(Design Under Test) +with those data automatically at startup time. You must read +the tri-mode thernet spec-doc before setting the REG.Only the +correct configuration can make sitmulation continue.} + +set namelist { +RegName Address default Data} +set datalist { + +{Tx_Hwmark 0 0x001e 0x001e} +{Tx_Lwmark 1 0x0019 0x0019} +{pause_frame_send_en 2 0x0000 0x0000} +{pause_quanta_set 3 0x0000 0x0000} +{IFGset 4 0x001e 0x001e} +{FullDuplex 5 0x0001 0x0001} +{MaxRetry 6 0x0002 0x0002} +{MAC_tx_add_en 7 0x0000 0x0000} +{MAC_tx_add_prom_data 8 0x0000 0x0000} +{MAC_tx_add_prom_add 9 0x0000 0x0000} +{MAC_tx_add_prom_wr 10 0x0000 0x0000} +{tx_pause_en 11 0x0000 0x0000} +{xoff_cpu 12 0x0000 0x0000} +{xon_cpu 13 0x0000 0x0000} +{MAC_rx_add_chk_en 14 0x0000 0x0000} +{MAC_rx_add_prom_data 15 0x0000 0x0000} +{MAC_rx_add_prom_add 16 0x0000 0x0000} +{MAC_rx_add_prom_wr 17 0x0000 0x0000} +{broadcast_filter_en 18 0x0000 0x0000} +{broadcast_bucket_depth 19 0x0000 0x0000} +{broadcast_bucket_interval 20 0x0000 0x0000} +{RX_APPEND_CRC 21 0x0000 0x0000} +{Rx_Hwmark 22 0x001a 0x001a} +{Rx_Lwmark 23 0x0010 0x0010} +{CRC_chk_en 24 0x0000 0x0000} +{RX_IFG_SET 25 0x001e 0x001e} +{RX_MAX_LENGTH 26 0x2710 0x2710} +{RX_MIN_LENGTH 27 0x0040 0x0040} +{CPU_rd_addr 28 0x0000 0x0000} +{CPU_rd_apply 29 0x0000 0x0000} +{Line_loop_en 33 0x0000 0x0000} +{Speed 34 0x0004 0x0004} +} + +cd ../data + + if {[catch {open CPU.vec r} fileid]} { + set RegVector {} + } else { + set RegVector {} + gets $fileid line + while {[eof $fileid]==0} { + scan $line "%02x%02x%04x" counter addr NewValue + set y [search_add $addr] + if {$y!=-1} { + set x [lindex $datalist $y] + set x [lreplace $x 3 3 [format "0x%04x" $NewValue]] + set datalist [lreplace $datalist $y $y $x] + lappend RegVector "$y $NewValue" + } + gets $fileid line + } + close $fileid + + } + +toplevel .p +wm title .p "Setting Reg Data" +focus .p +frame .p.f1 +frame .p.f2 +pack .p.f1 .p.f2 -side top + +frame .p.f1.f1 +frame .p.f1.f2 +frame .p.f1.f3 +frame .p.f1.f4 +frame .p.f1.f5 +pack .p.f1.f1 .p.f1.f2 .p.f1.f3 .p.f1.f4 .p.f1.f5 -side left + +label .p.f1.f1.l100 -text [lindex $namelist 0] -fg blue +label .p.f1.f2.l100 -text [lindex $namelist 1] -fg blue -width 10 +label .p.f1.f3.l100 -text [lindex $namelist 2] -fg blue -width 5 +label .p.f1.f4.l100 -text [lindex $namelist 3] -fg blue -width 10 + +pack .p.f1.f1.l100 .p.f1.f2.l100 .p.f1.f3.l100 .p.f1.f4.l100 + +for {set i 0} {$i < [llength $datalist]} {incr i} { + label .p.f1.f1.l$i -text [lindex [lindex $datalist $i] 0] + label .p.f1.f2.l$i -text [lindex [lindex $datalist $i] 1] + label .p.f1.f3.l$i -text [lindex [lindex $datalist $i] 2] + entry .p.f1.f4.en$i -width 10 + .p.f1.f4.en$i insert 0 [lindex [lindex $datalist $i] 3] + if {[lindex [lindex $datalist $i] 2] !=[lindex [lindex $datalist $i] 3]} { + .p.f1.f4.en$i config -fg red + } + pack .p.f1.f1.l$i .p.f1.f2.l$i .p.f1.f3.l$i .p.f1.f4.en$i + bind .p.f1.f4.en$i [list CheckModify .p.f1.f4.en$i $i ] +} + + +button .p.f2.b1 -text "Save" -width 10 -command {WriteVect CPU.vec} +button .p.f2.b2 -text "SaveAs" -width 10 -command {WriteVect [reg_save_as]} +button .p.f2.b3 -text "Exit" -width 10 -command {destroy .p} +button .p.f2.b4 -text "Help" -width 10 -command {print_help $help_strings} +pack .p.f2.b1 .p.f2.b2 .p.f2.b3 .p.f2.b4 -side left +bind .p.f2.b1 {focus .p} + + +} + +proc CheckModify {target_en index} { + global RegVector + global datalist + set data [$target_en get] + set NewValue "$index $data" + + + if {[info exists RegVector]} { + set counter [llength $RegVector] + for {set c 0} {$c<$counter} {incr c} { + if {[lindex [lindex $RegVector $c] 0]== $index} { + if {[lindex [lindex $datalist $index] 2]==$data} { + $target_en config -fg black + set RegVector [lreplace $RegVector $c $c] + } else { + set RegVector [lreplace $RegVector $c $c $NewValue] + } + return + } + } + } + if {[lindex [lindex $datalist $index] 3]==$data} { + return + } else { + $target_en config -fg red + set RegVector [lappend RegVector $NewValue] + } +} + +proc WriteVect {filename} { + global RegVector + global datalist + if {[info exists RegVector]} { + set counter [llength $RegVector] + if {[catch {open $filename w} fileid]} { + puts {failed to open vector file "$filename"} + destrop .p + } else { + for {set i 0} {$i < $counter} {incr i} { + set addr [lindex [lindex $datalist [lindex [lindex $RegVector $i] 0]] 1] + set NewValue [lindex [lindex $RegVector $i] 1] + puts $fileid [format "%02x%02x%04x" $counter $addr $NewValue] + } + close $fileid + unset RegVector + destroy .p + } + } else { + destroy .p + } +} + +proc reg_save_as {} { + global fileselect + fileselect + tkwait window .fileSelectWindow + if {$fileselect(canceled)==1} { + return + } elseif {$fileselect(selectedfile)==""} { + warning_message "file have not been selected!" + } else { + return $fileselect(selectedfile) + } +} + +proc search_add {addr} { + global datalist + set n 0 + foreach line $datalist { + if {[lindex $line 1]==$addr} { + return $n + } + incr n + } + return -1 +} \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl new file mode 100644 index 00000000..2bc42d7b --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl @@ -0,0 +1,101 @@ +proc set_stimulus {} { + toplevel .stimulus + focus .stimulus + wm title .stimulus "Setting Stimulus Prameters" + + variable StartLength + variable EndLength + variable PacketNumber + variable Random + variable Broadcast + variable help_string + +set help_string { +Set Stimulus Help: + You can select to generate packet with sequential packet length or +random packet length. If you choise random packet length, the length of +generated packet will be a random value between the "Packet begin length" +to the "Packet end length". "Total Gen Packet number"is used to set the +number of packet will be generated as stimulus + As well, you can select "sequence" mode . The first Packet will be +generated with "Packet begin length",and the next Packet length will be +"Packet begin length" pluse one untile the packet length reach the value +of "Packet end length". Packet in each length will be generated according +to the value of "Packet number per length" } + + + if {[catch {open ../data/config.ini r} fileid]} { + set StartLength 46 + set EndLength 60 + set PacketNumber 1 + set Random 0 + set Broadcast 0 + } \ + else { + gets $fileid content + scan $content "%d,%d,%d,%d,%d" StartLength EndLength PacketNumber Random Broadcast + close $fileid + } + + frame .stimulus.f1 + label .stimulus.f1.lb -text "Packet begin length:" + entry .stimulus.f1.en -textvariable StartLength + pack .stimulus.f1 -fill x + pack .stimulus.f1.en .stimulus.f1.lb -side right + + frame .stimulus.f2 + label .stimulus.f2.lb -text "Packet end length:" + entry .stimulus.f2.en -textvariable EndLength + pack .stimulus.f2 -fill x + pack .stimulus.f2.en .stimulus.f2.lb -side right + + + frame .stimulus.f3 + label .stimulus.f3.lb -text "Packet number per length:" + entry .stimulus.f3.en -textvariable PacketNumber + pack .stimulus.f3 -fill x + pack .stimulus.f3.en .stimulus.f3.lb -side right + + frame .stimulus.f4 + radiobutton .stimulus.f4.1 -text "Sequence" -variable Random -value 0 \ + -command {.stimulus.f3.lb config -text "Packet number per length:"} + radiobutton .stimulus.f4.2 -text "Random" -variable Random -value 1 \ + -command {.stimulus.f3.lb config -text "Total Gen Packet number:"} + pack .stimulus.f4 -fill x + pack .stimulus.f4.1 .stimulus.f4.2 -side right + + frame .stimulus.f5 + checkbutton .stimulus.f5.1 -text "Broadcast" -variable Broadcast + pack .stimulus.f5 -fill x + pack .stimulus.f5.1 -side right + + frame .stimulus.f20 + button .stimulus.f20.1 -text "Save" -width 10 \ + -command { set fileid [open ../data/config.ini w 0600] + puts $fileid "$StartLength,$EndLength,$PacketNumber,$Random,$Broadcast" + close $fileid + destroy .stimulus + } + button .stimulus.f20.2 -text "Save as" -command {sti_save_as $StartLength $EndLength $PacketNumber $Random $Broadcast} -width 10 + button .stimulus.f20.3 -text "Cancel" -command {destroy .stimulus} -width 10 + button .stimulus.f20.4 -text "Help" -width 10 -command {print_help $help_string} + pack .stimulus.f20 -fill x + pack .stimulus.f20.1 .stimulus.f20.2 .stimulus.f20.3 .stimulus.f20.4 -side left +} + +proc sti_save_as {StartLength EndLength PacketNumber Random Broadcast} { + global fileselect + cd ../data + fileselect + tkwait window .fileSelectWindow + if {$fileselect(canceled)==1} { + return + } elseif {$fileselect(selectedfile)==""} { + warning_message "file have not been selected!" + } else { + set fileid [open $fileselect(selectedfile) w 0600] + puts $fileid "$StartLength,$EndLength,$PacketNumber,$Random,$Broadcast" + close $fileid + destroy .stimulus + } +} \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/start_verify.tcl b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/start_verify.tcl new file mode 100644 index 00000000..3209e630 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/start_verify.tcl @@ -0,0 +1,127 @@ +proc start_verify {batch index} { +variable compiling +variable simulate_times +variable test_case_number +variable batch_data {} +variable batchmode +variable piple +############################################################################### + set batchmode $batch + toplevel .l + focus .l + wm title .l "Simulation Log" + frame .l.f1 + frame .l.f2 + pack .l.f1 .l.f2 -side top + + text .l.f1.t1 -width 80 -height 40 -yscrollcommand {.l.f1.scroll set} + + scrollbar .l.f1.scroll -command {.l.f1.t1 yview} + button .l.f2.b1 -text "Exit" -command {destroy .l} -width 10 + button .l.f2.b2 -text "Stop" -command {Stop_sim} -width 10 + pack .l.f1.scroll -side right -fill y + pack .l.f1.t1 + pack .l.f2.b1 .l.f2.b2 -side left + + set output_win .l.f1.t1 + set simulate_times 0 + set test_case_number [lindex $index 0] + cd ../bin + set compiling 1 + if {$batch==0} { + Run "bash sim.nc " $output_win + } elseif {[catch {open ../data/batch.dat r} fileid]} { + $output_win insert end "Failed open ../data/batch.dat file\n" + } elseif {[lindex $index 0] == "empty"} { + $output_win insert end "Not any test case was selected\n" + } else { + set i 0 + gets $fileid line + while {[eof $fileid]==0} { + lappend batch_data $line + gets $fileid line + incr i + } + $output_win insert end "Verifcation Started\n" + $output_win insert end "Starting Compiling Source file and libs......\n" + Run "bash com.nc" $output_win + close $fileid + } +} + +proc Run {command output_win} { + global piple + if [catch {open "|$command |& cat "} piple] { + $output_win insert end $piple\n + } else { + fileevent $piple readable [list Log $piple $output_win] + } +} + +proc Log {piple output_win} { + global compiling + global batchmode + set saparator "###################################################################\n" + if {[eof $piple]} { + if {$batchmode==0} { + $output_win insert end $saparator + $output_win insert end "end of Simulation....\n" + $output_win insert end $saparator + } elseif {$compiling==1} { + $output_win insert end $saparator + $output_win insert end "end of Compiling....\n" + $output_win insert end $saparator + $output_win insert end "\n \n \n" + set compiling 0 + sim_next_case + } else { + $output_win insert end $saparator + $output_win insert end "end of Testcase....\n" + $output_win insert end $saparator + $output_win insert end "\n \n \n" + sim_next_case + } + close $piple + } else { + gets $piple line + $output_win insert end $line\n + $output_win see end + } +} + +proc sim_next_case {} { + global test_case_number + global simulate_times + global batch_data + global index + set saparator "###################################################################\n" + set output_win .l.f1.t1 + set test_case_number [lindex $index $simulate_times] + if {$simulate_times < [llength $index]} { + set line [lindex $batch_data $test_case_number] + set source_sti [lindex $line 1] + set source_reg [lindex $line 2] + + if {$simulate_times==0 ||[file exists "../log/.sim_succeed"]} { + exec cp "../data/$source_sti" "../data/config.ini" + exec cp "../data/$source_reg" "../data/CPU.vec" + + $output_win insert end $saparator + $output_win insert end "starting test case :[lindex $line 0]....\n" + $output_win insert end $saparator + $output_win insert end "\n \n \n" + incr simulate_times + Run "bash sim_only.nc" $output_win + } else { + $output_win insert end "test_case :[lindex $line 0] simulation failed!!\n" + } + + } else { + $output_win insert end "All test_case passed simulation Successfully!!\n" + } +} + +proc Stop_sim {} { + global piple + catch {close $piple} +} \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/user_lib.tcl b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/user_lib.tcl new file mode 100644 index 00000000..14b4302b --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/user_lib.tcl @@ -0,0 +1,17 @@ +proc print_help {help_string} { + toplevel .help + frame .help.1 + message .help.1.1 -text $help_string -width 10c + frame .help.2 + button .help.2.1 -text "exit" -command {destroy .help} -width 10 + pack .help.1 .help.2 .help.1.1 .help.2.1 +} + +proc warning_message {warning_string} { + toplevel .warning + frame .warning.1 + message .warning.1.1 -text $warning_string -width 10c + frame .warning.2 + button .warning.2.1 -text "exit" -command {destroy .warning} -width 10 + pack .warning.1 .warning.2 .warning.1.1 .warning.2.1 +} \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/start.tcl b/usrp2/fpga/opencores/ethernet_tri_mode/start.tcl new file mode 100644 index 00000000..42d11c15 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/start.tcl @@ -0,0 +1,180 @@ +variable MAC_SOURCE_REPLACE_EN +variable MAC_TARGET_CHECK_EN +variable MAC_BROADCAST_FILTER_EN +variable MAC_TX_FF_DEPTH +variable MAC_RX_FF_DEPTH +variable header_data + +source sim/rtl_sim/ncsim_sim/script/run_proc.tcl + +frame .f1 +frame .f2 +text .f1.t1 -width 60 -height 20 +button .f2.b1 -text "Quit" -width 5 -command {exit} +button .f2.b2 -text "Next" -width 5 -command {module_conf} + +pack .f1 .f2 +pack .f1.t1 +pack .f2.b1 .f2.b2 -side left + +set strings \ +{Hi guys, + Thanks for your interest about this tri-speed ethernet MAC controller. +Since this project was created at 25-Nov-2005,I put almost all my free time +on this project.I am exhausted for this two month's extra work.If you think +this project is useful,let me know that and i will feel much better. + + To increase the flexibility, some optional modules can be removed from +the design to reduce area. + + Any problem or bug report please contact me by email: + gaojon@yahoo.com + + + + + + + jon + 18-Jan-2006 +} + +.f1.t1 insert end $strings + +proc module_conf {} { + global MAC_SOURCE_REPLACE_EN + global MAC_TARGET_CHECK_EN + global MAC_BROADCAST_FILTER_EN + global MAC_TX_FF_DEPTH + global MAC_RX_FF_DEPTH + global header_data + + if {[catch {open ./rtl/verilog/header.v r} fileid]} { + puts "Failed open ./rtl/verilog/header.v file\n" + } else { + gets $fileid line + if {[lindex $line 0]=="//"} { + set line [lreplace $line 0 0] + set MAC_SOURCE_REPLACE_EN 0 + } else { + set MAC_SOURCE_REPLACE_EN 1 + } + lappend header_data $line + gets $fileid line + if {[lindex $line 0]=="//"} { + set line [lreplace $line 0 0] + set MAC_TARGET_CHECK_EN 0 + } else { + set MAC_TARGET_CHECK_EN 1 + } + lappend header_data $line + gets $fileid line + if {[lindex $line 0]=="//"} { + set line [lreplace $line 0 0] + set MAC_BROADCAST_FILTER_EN 0 + } else { + set MAC_BROADCAST_FILTER_EN 1 + } + lappend header_data $line + gets $fileid line + set MAC_TX_FF_DEPTH [lindex $line 2] + lappend header_data $line + gets $fileid line + set MAC_RX_FF_DEPTH [lindex $line 2] + lappend header_data $line + close $fileid + } + + destroy .f1 .f2 + frame .f1 + frame .f2 + frame .f1.f1 + frame .f1.f2 + frame .f1.f3 + frame .f1.f4 + frame .f1.f5 + frame .f1.f6 + + pack .f1 .f2 + pack .f1.f1 .f1.f2 .f1.f3 .f1.f4 .f1.f5 .f1.f6 + label .f1.f1.lb -text "enable source MAC replace module" -width 30 + checkbutton .f1.f1.cb -variable MAC_SOURCE_REPLACE_EN + label .f1.f2.lb -text "enable target MAC check module " -width 30 + checkbutton .f1.f2.cb -variable MAC_TARGET_CHECK_EN + label .f1.f3.lb -text "enable broadcast packet filter module" -width 30 + checkbutton .f1.f3.cb -variable MAC_BROADCAST_FILTER_EN + + label .f1.f4.lb -text "MAC_TX_FF_DEPTH" -width 30 + entry .f1.f4.en -textvariable MAC_TX_FF_DEPTH -width 5 + label .f1.f5.lb -text "MAC_RX_FF_DEPTH" -width 30 + entry .f1.f5.en -textvariable MAC_RX_FF_DEPTH -width 5 + + button .f2.b1 -width 10 -text "Save" -command {save_header} + button .f2.b2 -width 10 -text "Verify" -command {run_sim} + button .f2.b4 -width 10 -text "Exit" -command {exit} + + pack .f1.f1.cb .f1.f1.lb -side right + pack .f1.f2.cb .f1.f2.lb -side right + pack .f1.f3.cb .f1.f3.lb -side right + pack .f1.f4.en .f1.f4.lb -side right + pack .f1.f5.en .f1.f5.lb -side right + + pack .f2.b1 .f2.b2 .f2.b4 -side left + +} + +proc save_header {} { + global MAC_SOURCE_REPLACE_EN + global MAC_TARGET_CHECK_EN + global MAC_BROADCAST_FILTER_EN + global MAC_TX_FF_DEPTH + global MAC_RX_FF_DEPTH + global header_data + if {[catch {open ./rtl/verilog/header.v w} fileid]} { + puts "Failed open ./rtl/verilog/header.v file\n" + } else { + set line [lindex $header_data 0] + if {$MAC_SOURCE_REPLACE_EN==0} { + set line [linsert $line 0 "//"] + } + puts $fileid $line + + set line [lindex $header_data 1] + if {$MAC_TARGET_CHECK_EN==0} { + set line [linsert $line 0 "//"] + } + puts $fileid $line + + set line [lindex $header_data 2] + if {$MAC_BROADCAST_FILTER_EN==0} { + set line [linsert $line 0 "//"] + } + puts $fileid $line + + set line [lindex $header_data 3] + set line [lreplace $line 2 2 $MAC_TX_FF_DEPTH] + puts $fileid $line + + set line [lindex $header_data 4] + set line [lreplace $line 2 2 $MAC_RX_FF_DEPTH] + puts $fileid $line + + close $fileid + } + +} + +proc start_verify {} { + cd sim/rtl_sim/ncsim_sim/script + vish run.tcl +} + +proc start_syn {} { + cd syn + synplify_pro syn.prj +} + +proc run_sim {} { + cd sim/rtl_sim/ncsim_sim/script/ + run_proc +} \ No newline at end of file diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Entries b/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Entries new file mode 100644 index 00000000..b6b97bde --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Entries @@ -0,0 +1,4 @@ +/syn.prj/1.2/Thu Jan 19 14:07:57 2006// +/syn_altrea.prj/1.1/Sun Jun 25 05:09:02 2006// +/syn_xilinx.prj/1.1/Sun Jun 25 05:09:02 2006// +D diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Repository b/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Repository new file mode 100644 index 00000000..300767ca --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/syn diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Root b/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Template b/usrp2/fpga/opencores/ethernet_tri_mode/syn/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/syn/syn.prj b/usrp2/fpga/opencores/ethernet_tri_mode/syn/syn.prj new file mode 100644 index 00000000..568a7a4e --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/syn/syn.prj @@ -0,0 +1,86 @@ +#-- Synplicity, Inc. +#-- Version Synplify 8.1 +#-- Project file D:\root\home\ethernet_tri_mode\syn\syn.prj +#-- Written on Thu Jan 19 20:25:55 2006 + + +#add_file options +add_file -verilog "../rtl/verilog/header.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v" +add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v" +add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v" +add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v" +add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v" +add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v" +add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v" +add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v" +add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v" +add_file -verilog "../rtl/verilog/TECH/duram.v" +add_file -verilog "../rtl/verilog/RMON.v" +add_file -verilog "../rtl/verilog/MAC_rx.v" +add_file -verilog "../rtl/verilog/MAC_tx.v" +add_file -verilog "../rtl/verilog/miim/eth_clockgen.v" +add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v" +add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v" +add_file -verilog "../rtl/verilog/miim/timescale.v" +add_file -verilog "../rtl/verilog/TECH/CLK_SWITCH.v" +add_file -verilog "../rtl/verilog/TECH/CLK_DIV2.v" +add_file -verilog "../rtl/verilog/eth_miim.v" +add_file -verilog "../rtl/verilog/Clk_ctrl.v" +add_file -verilog "../rtl/verilog/Phy_int.v" +add_file -verilog "../rtl/verilog/Reg_int.v" +add_file -verilog "../rtl/verilog/MAC_top.v" + + +#implementation: "syn" +impl -add syn + +#device options +set_option -technology STRATIX +set_option -part EP1S10 +set_option -package FC780 +set_option -speed_grade -5 + +#compilation/mapping options +set_option -default_enum_encoding onehot +set_option -symbolic_fsm_compiler 0 +set_option -resource_sharing 1 +set_option -use_fsm_explorer 0 + +#map options +set_option -frequency auto +set_option -run_prop_extract 0 +set_option -fanout_limit 500 +set_option -disable_io_insertion 0 +set_option -pipe 1 +set_option -update_models_cp 0 +set_option -retiming 0 +set_option -verification_mode 0 +set_option -fixgatedclocks 0 +set_option -no_sequential_opt 0 + +#simulation options +set_option -write_verilog 1 +set_option -write_vhdl 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +#set result format/file last +project -result_file "./MAC_top.vqm" + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 + +#par_1 attributes +set_option -job par_1 -add par +set_option -job par_1 -option run_backannotation 0 +impl -active "syn" diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/syn/syn_altrea.prj b/usrp2/fpga/opencores/ethernet_tri_mode/syn/syn_altrea.prj new file mode 100644 index 00000000..e227ea67 --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/syn/syn_altrea.prj @@ -0,0 +1,91 @@ +#-- Synplicity, Inc. +#-- Version Synplify Pro 8.1 +#-- Project file D:\root\home\ethernet_tri_mode\syn\syn_altrea.prj +#-- Written on Sun Jun 25 09:40:49 2006 + + +#add_file options +add_file -verilog "../rtl/verilog/header.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v" +add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v" +add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v" +add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v" +add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v" +add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v" +add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v" +add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v" +add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v" +add_file -verilog "../rtl/verilog/RMON.v" +add_file -verilog "../rtl/verilog/MAC_rx.v" +add_file -verilog "../rtl/verilog/MAC_tx.v" +add_file -verilog "../rtl/verilog/miim/eth_clockgen.v" +add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v" +add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v" +add_file -verilog "../rtl/verilog/miim/timescale.v" +add_file -verilog "../rtl/verilog/TECH/altera/duram.v" +add_file -verilog "../rtl/verilog/TECH/altera/CLK_SWITCH.v" +add_file -verilog "../rtl/verilog/TECH/altera/CLK_DIV2.v" +add_file -verilog "../rtl/verilog/eth_miim.v" +add_file -verilog "../rtl/verilog/Clk_ctrl.v" +add_file -verilog "../rtl/verilog/Phy_int.v" +add_file -verilog "../rtl/verilog/Reg_int.v" +add_file -verilog "../rtl/verilog/MAC_top.v" + + +#implementation: "syn" +impl -add syn + +#device options +set_option -technology STRATIX +set_option -part EP1S30 +set_option -package FC780 +set_option -speed_grade -5 + +#compilation/mapping options +set_option -default_enum_encoding onehot +set_option -symbolic_fsm_compiler 0 +set_option -resource_sharing 1 +set_option -use_fsm_explorer 0 +set_option -top_module "MAC_top" + +#map options +set_option -frequency auto +set_option -run_prop_extract 0 +set_option -fanout_limit 500 +set_option -disable_io_insertion 0 +set_option -pipe 1 +set_option -update_models_cp 0 +set_option -retiming 0 +set_option -verification_mode 0 +set_option -fixgatedclocks 0 +set_option -no_sequential_opt 0 + +#simulation options +set_option -write_verilog 1 +set_option -write_vhdl 0 + +#VIF options +set_option -write_vif 1 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +#set result format/file last +project -result_file "./MAC_top.vqm" + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -dup 0 +set_option -project_relative_includes 1 + +#par_1 attributes +set_option -job par_1 -add par +set_option -job par_1 -option run_backannotation 0 +impl -active "syn" diff --git a/usrp2/fpga/opencores/ethernet_tri_mode/syn/syn_xilinx.prj b/usrp2/fpga/opencores/ethernet_tri_mode/syn/syn_xilinx.prj new file mode 100644 index 00000000..94435b4b --- /dev/null +++ b/usrp2/fpga/opencores/ethernet_tri_mode/syn/syn_xilinx.prj @@ -0,0 +1,92 @@ +#-- Synplicity, Inc. +#-- Version Synplify Pro 8.1 +#-- Project file D:\root\home\ethernet_tri_mode\syn\syn_xilinx.prj +#-- Written on Sun Jun 25 09:43:29 2006 + + +#add_file options +add_file -verilog "../rtl/verilog/header.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v" +add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v" +add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v" +add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v" +add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v" +add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v" +add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v" +add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v" +add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v" +add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v" +add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v" +add_file -verilog "../rtl/verilog/RMON.v" +add_file -verilog "../rtl/verilog/MAC_rx.v" +add_file -verilog "../rtl/verilog/MAC_tx.v" +add_file -verilog "../rtl/verilog/miim/eth_clockgen.v" +add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v" +add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v" +add_file -verilog "../rtl/verilog/miim/timescale.v" +add_file -verilog "../rtl/verilog/TECH/xilinx/duram.v" +add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_SWITCH.v" +add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_DIV2.v" +add_file -verilog "../rtl/verilog/eth_miim.v" +add_file -verilog "../rtl/verilog/Clk_ctrl.v" +add_file -verilog "../rtl/verilog/Phy_int.v" +add_file -verilog "../rtl/verilog/Reg_int.v" +add_file -verilog "../rtl/verilog/MAC_top.v" + + +#implementation: "syn" +impl -add syn + +#device options +set_option -technology VIRTEX4 +set_option -part XC4VLX40 +set_option -package FF668 +set_option -speed_grade -10 + +#compilation/mapping options +set_option -default_enum_encoding onehot +set_option -symbolic_fsm_compiler 0 +set_option -resource_sharing 1 +set_option -use_fsm_explorer 0 +set_option -top_module "MAC_top" + +#map options +set_option -frequency auto +set_option -run_prop_extract 0 +set_option -fanout_limit 10000 +set_option -disable_io_insertion 0 +set_option -pipe 1 +set_option -update_models_cp 0 +set_option -verification_mode 0 +set_option -fixgatedclocks 0 +set_option -modular 0 +set_option -retiming 0 +set_option -no_sequential_opt 0 + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#VIF options +set_option -write_vif 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +#set result format/file last +project -result_file "./MAC_top.edf" + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -dup 0 +set_option -project_relative_includes 1 + +#par_1 attributes +set_option -job par_1 -add par +set_option -job par_1 -option run_backannotation 0 +impl -active "syn" diff --git a/usrp2/fpga/opencores/i2c/CVS/Entries b/usrp2/fpga/opencores/i2c/CVS/Entries new file mode 100644 index 00000000..d6947544 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/CVS/Entries @@ -0,0 +1,8 @@ +D/bench//// +D/doc//// +D/documentation//// +D/rtl//// +D/sim//// +D/software//// +D/verilog//// +D/vhdl//// diff --git a/usrp2/fpga/opencores/i2c/CVS/Repository b/usrp2/fpga/opencores/i2c/CVS/Repository new file mode 100644 index 00000000..1a9fe896 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/CVS/Repository @@ -0,0 +1 @@ +i2c diff --git a/usrp2/fpga/opencores/i2c/CVS/Root b/usrp2/fpga/opencores/i2c/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/CVS/Template b/usrp2/fpga/opencores/i2c/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/bench/CVS/Entries b/usrp2/fpga/opencores/i2c/bench/CVS/Entries new file mode 100644 index 00000000..428c5622 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/CVS/Entries @@ -0,0 +1 @@ +D/verilog//// diff --git a/usrp2/fpga/opencores/i2c/bench/CVS/Repository b/usrp2/fpga/opencores/i2c/bench/CVS/Repository new file mode 100644 index 00000000..5597c8aa --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/CVS/Repository @@ -0,0 +1 @@ +i2c/bench diff --git a/usrp2/fpga/opencores/i2c/bench/CVS/Root b/usrp2/fpga/opencores/i2c/bench/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/bench/CVS/Template b/usrp2/fpga/opencores/i2c/bench/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Entries b/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Entries new file mode 100644 index 00000000..2dd77910 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Entries @@ -0,0 +1,5 @@ +/i2c_slave_model.v/1.7/Mon Sep 4 09:08:51 2006// +/spi_slave_model.v/1.1/Sat Feb 28 15:32:54 2004// +/tst_bench_top.v/1.8/Mon Sep 4 09:08:51 2006// +/wb_master_model.v/1.4/Sat Feb 28 15:40:42 2004// +D diff --git a/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Repository b/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Repository new file mode 100644 index 00000000..b37c379e --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Repository @@ -0,0 +1 @@ +i2c/bench/verilog diff --git a/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Root b/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Template b/usrp2/fpga/opencores/i2c/bench/verilog/CVS/Template new file mode 100644 index 00000000..e69de29b diff --git a/usrp2/fpga/opencores/i2c/bench/verilog/i2c_slave_model.v b/usrp2/fpga/opencores/i2c/bench/verilog/i2c_slave_model.v new file mode 100644 index 00000000..0c8ecae0 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/verilog/i2c_slave_model.v @@ -0,0 +1,360 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant synthesizable I2C Slave model //// +//// //// +//// //// +//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws //// +//// John Sheahan (jrsheahan@optushome.com.au) //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001,2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_slave_model.v,v 1.7 2006/09/04 09:08:51 rherveille Exp $ +// +// $Date: 2006/09/04 09:08:51 $ +// $Revision: 1.7 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: i2c_slave_model.v,v $ +// Revision 1.7 2006/09/04 09:08:51 rherveille +// fixed (n)ack generation +// +// Revision 1.6 2005/02/28 11:33:48 rherveille +// Fixed Tsu:sta timing check. +// Added Thd:sta timing check. +// +// Revision 1.5 2003/12/05 11:05:19 rherveille +// Fixed slave address MSB='1' bug +// +// Revision 1.4 2003/09/11 08:25:37 rherveille +// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. +// +// Revision 1.3 2002/10/30 18:11:06 rherveille +// Added timing tests to i2c_model. +// Updated testbench. +// +// Revision 1.2 2002/03/17 10:26:38 rherveille +// Fixed some race conditions in the i2c-slave model. +// Added debug information. +// Added headers. +// + +`include "timescale.v" + +module i2c_slave_model (scl, sda); + + // + // parameters + // + parameter I2C_ADR = 7'b001_0000; + + // + // input && outpus + // + input scl; + inout sda; + + // + // Variable declaration + // + wire debug = 1'b1; + + reg [7:0] mem [3:0]; // initiate memory + reg [7:0] mem_adr; // memory address + reg [7:0] mem_do; // memory data output + + reg sta, d_sta; + reg sto, d_sto; + + reg [7:0] sr; // 8bit shift register + reg rw; // read/write direction + + wire my_adr; // my address called ?? + wire i2c_reset; // i2c-statemachine reset + reg [2:0] bit_cnt; // 3bit downcounter + wire acc_done; // 8bits transfered + reg ld; // load downcounter + + reg sda_o; // sda-drive level + wire sda_dly; // delayed version of sda + + // statemachine declaration + parameter idle = 3'b000; + parameter slave_ack = 3'b001; + parameter get_mem_adr = 3'b010; + parameter gma_ack = 3'b011; + parameter data = 3'b100; + parameter data_ack = 3'b101; + + reg [2:0] state; // synopsys enum_state + + // + // module body + // + + initial + begin + sda_o = 1'b1; + state = idle; + end + + // generate shift register + always @(posedge scl) + sr <= #1 {sr[6:0],sda}; + + //detect my_address + assign my_adr = (sr[7:1] == I2C_ADR); + // FIXME: This should not be a generic assign, but rather + // qualified on address transfer phase and probably reset by stop + + //generate bit-counter + always @(posedge scl) + if(ld) + bit_cnt <= #1 3'b111; + else + bit_cnt <= #1 bit_cnt - 3'h1; + + //generate access done signal + assign acc_done = !(|bit_cnt); + + // generate delayed version of sda + // this model assumes a hold time for sda after the falling edge of scl. + // According to the Phillips i2c spec, there s/b a 0 ns hold time for sda + // with regards to scl. If the data changes coincident with the clock, the + // acknowledge is missed + // Fix by Michael Sosnoski + assign #1 sda_dly = sda; + + + //detect start condition + always @(negedge sda) + if(scl) + begin + sta <= #1 1'b1; + d_sta <= #1 1'b0; + sto <= #1 1'b0; + + if(debug) + $display("DEBUG i2c_slave; start condition detected at %t", $time); + end + else + sta <= #1 1'b0; + + always @(posedge scl) + d_sta <= #1 sta; + + // detect stop condition + always @(posedge sda) + if(scl) + begin + sta <= #1 1'b0; + sto <= #1 1'b1; + + if(debug) + $display("DEBUG i2c_slave; stop condition detected at %t", $time); + end + else + sto <= #1 1'b0; + + //generate i2c_reset signal + assign i2c_reset = sta || sto; + + // generate statemachine + always @(negedge scl or posedge sto) + if (sto || (sta && !d_sta) ) + begin + state <= #1 idle; // reset statemachine + + sda_o <= #1 1'b1; + ld <= #1 1'b1; + end + else + begin + // initial settings + sda_o <= #1 1'b1; + ld <= #1 1'b0; + + case(state) // synopsys full_case parallel_case + idle: // idle state + if (acc_done && my_adr) + begin + state <= #1 slave_ack; + rw <= #1 sr[0]; + sda_o <= #1 1'b0; // generate i2c_ack + + #2; + if(debug && rw) + $display("DEBUG i2c_slave; command byte received (read) at %t", $time); + if(debug && !rw) + $display("DEBUG i2c_slave; command byte received (write) at %t", $time); + + if(rw) + begin + mem_do <= #1 mem[mem_adr]; + + if(debug) + begin + #2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr); + #2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]); + end + end + end + + slave_ack: + begin + if(rw) + begin + state <= #1 data; + sda_o <= #1 mem_do[7]; + end + else + state <= #1 get_mem_adr; + + ld <= #1 1'b1; + end + + get_mem_adr: // wait for memory address + if(acc_done) + begin + state <= #1 gma_ack; + mem_adr <= #1 sr; // store memory address + sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address + + if(debug) + #1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o); + end + + gma_ack: + begin + state <= #1 data; + ld <= #1 1'b1; + end + + data: // receive or drive data + begin + if(rw) + sda_o <= #1 mem_do[7]; + + if(acc_done) + begin + state <= #1 data_ack; + mem_adr <= #2 mem_adr + 8'h1; + sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read + + if(rw) + begin + #3 mem_do <= mem[mem_adr]; + + if(debug) + #5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr); + end + + if(!rw) + begin + mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory + + if(debug) + #2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr); + end + end + end + + data_ack: + begin + ld <= #1 1'b1; + + if(rw) + if(sr[0]) // read operation && master send NACK + begin + state <= #1 idle; + sda_o <= #1 1'b1; + end + else + begin + state <= #1 data; + sda_o <= #1 mem_do[7]; + end + else + begin + state <= #1 data; + sda_o <= #1 1'b1; + end + end + + endcase + end + + // read data from memory + always @(posedge scl) + if(!acc_done && rw) + mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation + + // generate tri-states + assign sda = sda_o ? 1'bz : 1'b0; + + + // + // Timing checks + // + + wire tst_sto = sto; + wire tst_sta = sta; + + specify + specparam normal_scl_low = 4700, + normal_scl_high = 4000, + normal_tsu_sta = 4700, + normal_thd_sta = 4000, + normal_tsu_sto = 4000, + normal_tbuf = 4700, + + fast_scl_low = 1300, + fast_scl_high = 600, + fast_tsu_sta = 1300, + fast_thd_sta = 600, + fast_tsu_sto = 600, + fast_tbuf = 1300; + + $width(negedge scl, normal_scl_low); // scl low time + $width(posedge scl, normal_scl_high); // scl high time + + $setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start + $setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start + $setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop + + $setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time + endspecify + +endmodule + + diff --git a/usrp2/fpga/opencores/i2c/bench/verilog/spi_slave_model.v b/usrp2/fpga/opencores/i2c/bench/verilog/spi_slave_model.v new file mode 100644 index 00000000..7d2f436f --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/verilog/spi_slave_model.v @@ -0,0 +1,128 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// SPI Slave Model //// +//// //// +//// //// +//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws //// +//// //// +//// http://www.opencores.org/projects/simple_spi/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: spi_slave_model.v,v 1.1 2004/02/28 15:32:54 rherveille Exp $ +// +// $Date: 2004/02/28 15:32:54 $ +// $Revision: 1.1 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: spi_slave_model.v,v $ +// Revision 1.1 2004/02/28 15:32:54 rherveille +// Added testbench +// +// +// + + +// Requires: Verilog2001 + +`include "timescale.v" + +module spi_slave_model ( + input wire csn; + input wire sck + input wire di; + output wire do +); + + // + // Variable declaration + // + wire debug = 1'b1; + + wire cpol = 1'b0; + wire cpha = 1'b0; + + reg [7:0] mem [7:0]; // initiate memory + reg [2:0] mem_adr; // memory address + reg [7:0] mem_do; // memory data output + + reg [7:0] sri, sro; // 8bit shift register + + reg [2:0] bit_cnt; + reg ld; + + wire clk; + + // + // module body + // + + assign clk = cpol ^ cpha ^ sck; + + // generate shift registers + always @(posedge clk) + sri <= #1 {sri[6:0],di}; + + always @(posedge clk) + if (&bit_cnt) + sro <= #1 mem[mem_adr]; + else + sro <= #1 {sro[6:0],1'bx}; + + assign do = sro[7]; + + //generate bit-counter + always @(posedge clk, posedge csn) + if(csn) + bit_cnt <= #1 3'b111; + else + bit_cnt <= #1 bit_cnt - 3'h1; + + //generate access done signal + always @(posedge clk) + ld <= #1 ~(|bit_cnt); + + always @(negedge clk) + if (ld) begin + mem[mem_adr] <= #1 sri; + mem_adr <= #1 mem_adr + 1'b1; + end + + initial + begin + bit_cnt=3'b111; + mem_adr = 0; + sro = mem[mem_adr]; + end +endmodule + + diff --git a/usrp2/fpga/opencores/i2c/bench/verilog/tst_bench_top.v b/usrp2/fpga/opencores/i2c/bench/verilog/tst_bench_top.v new file mode 100644 index 00000000..66284e4d --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/verilog/tst_bench_top.v @@ -0,0 +1,467 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant I2C Master controller Testbench //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: tst_bench_top.v,v 1.8 2006/09/04 09:08:51 rherveille Exp $ +// +// $Date: 2006/09/04 09:08:51 $ +// $Revision: 1.8 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: tst_bench_top.v,v $ +// Revision 1.8 2006/09/04 09:08:51 rherveille +// fixed (n)ack generation +// +// Revision 1.7 2005/02/27 09:24:18 rherveille +// Fixed scl, sda delay. +// +// Revision 1.6 2004/02/28 15:40:42 rherveille +// *** empty log message *** +// +// Revision 1.4 2003/12/05 11:04:38 rherveille +// Added slave address configurability +// +// Revision 1.3 2002/10/30 18:11:06 rherveille +// Added timing tests to i2c_model. +// Updated testbench. +// +// Revision 1.2 2002/03/17 10:26:38 rherveille +// Fixed some race conditions in the i2c-slave model. +// Added debug information. +// Added headers. +// + +`include "timescale.v" + +module tst_bench_top(); + + // + // wires && regs + // + reg clk; + reg rstn; + + wire [31:0] adr; + wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i; + wire we; + wire stb; + wire cyc; + wire ack; + wire inta; + + reg [7:0] q, qq; + + wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen; + wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen; + + parameter PRER_LO = 3'b000; + parameter PRER_HI = 3'b001; + parameter CTR = 3'b010; + parameter RXR = 3'b011; + parameter TXR = 3'b011; + parameter CR = 3'b100; + parameter SR = 3'b100; + + parameter TXR_R = 3'b101; // undocumented / reserved output + parameter CR_R = 3'b110; // undocumented / reserved output + + parameter RD = 1'b1; + parameter WR = 1'b0; + parameter SADR = 7'b0010_000; + + // + // Module body + // + + // generate clock + always #5 clk = ~clk; + + // hookup wishbone master model + wb_master_model #(8, 32) u0 ( + .clk(clk), + .rst(rstn), + .adr(adr), + .din(dat_i), + .dout(dat_o), + .cyc(cyc), + .stb(stb), + .we(we), + .sel(), + .ack(ack), + .err(1'b0), + .rty(1'b0) + ); + + wire stb0 = stb & ~adr[3]; + wire stb1 = stb & adr[3]; + + assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i); + + // hookup wishbone_i2c_master core + i2c_master_top i2c_top ( + + // wishbone interface + .wb_clk_i(clk), + .wb_rst_i(1'b0), + .arst_i(rstn), + .wb_adr_i(adr[2:0]), + .wb_dat_i(dat_o), + .wb_dat_o(dat0_i), + .wb_we_i(we), + .wb_stb_i(stb0), + .wb_cyc_i(cyc), + .wb_ack_o(ack), + .wb_inta_o(inta), + + // i2c signals + .scl_pad_i(scl), + .scl_pad_o(scl0_o), + .scl_padoen_o(scl0_oen), + .sda_pad_i(sda), + .sda_pad_o(sda0_o), + .sda_padoen_o(sda0_oen) + ), + i2c_top2 ( + + // wishbone interface + .wb_clk_i(clk), + .wb_rst_i(1'b0), + .arst_i(rstn), + .wb_adr_i(adr[2:0]), + .wb_dat_i(dat_o), + .wb_dat_o(dat1_i), + .wb_we_i(we), + .wb_stb_i(stb1), + .wb_cyc_i(cyc), + .wb_ack_o(ack), + .wb_inta_o(inta), + + // i2c signals + .scl_pad_i(scl), + .scl_pad_o(scl1_o), + .scl_padoen_o(scl1_oen), + .sda_pad_i(sda), + .sda_pad_o(sda1_o), + .sda_padoen_o(sda1_oen) + ); + + + // hookup i2c slave model + i2c_slave_model #(SADR) i2c_slave ( + .scl(scl), + .sda(sda) + ); + + // create i2c lines + delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl), + m1_scl (scl1_oen ? 1'bz : scl1_o, scl), + m0_sda (sda0_oen ? 1'bz : sda0_o, sda), + m1_sda (sda1_oen ? 1'bz : sda1_o, sda); + + pullup p1(scl); // pullup scl line + pullup p2(sda); // pullup sda line + + initial + begin + `ifdef WAVES + $shm_open("waves"); + $shm_probe("AS",tst_bench_top,"AS"); + $display("INFO: Signal dump enabled ...\n\n"); + `endif + +// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information + force i2c_slave.debug = 1'b0; // disable i2c_slave debug information + + $display("\nstatus: %t Testbench started\n\n", $time); + +// $dumpfile("bench.vcd"); +// $dumpvars(1, tst_bench_top); +// $dumpvars(1, tst_bench_top.i2c_slave); + + // initially values + clk = 0; + + // reset system + rstn = 1'b1; // negate reset + #2; + rstn = 1'b0; // assert reset + repeat(1) @(posedge clk); + rstn = 1'b1; // negate reset + + $display("status: %t done reset", $time); + + @(posedge clk); + + // + // program core + // + + // program internal registers + u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte + u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte + u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte + $display("status: %t programmed registers", $time); + + u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte + u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte + $display("status: %t verified registers", $time); + + u0.wb_write(1, CTR, 8'h80); // enable core + $display("status: %t core enabled", $time); + + // + // access slave (write) + // + + // drive slave address + u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit + u0.wb_write(0, CR, 8'h90 ); // set command (start, write) + $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} ); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(0, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory address + u0.wb_write(1, TXR, 8'h01); // present slave's memory address + u0.wb_write(0, CR, 8'h10); // set command (write) + $display("status: %t write slave memory address 01", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(0, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory contents + u0.wb_write(1, TXR, 8'ha5); // present data + u0.wb_write(0, CR, 8'h10); // set command (write) + $display("status: %t write data a5", $time); + +while (scl) #1; +force scl= 1'b0; +#100000; +release scl; + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory contents for next memory address (auto_inc) + u0.wb_write(1, TXR, 8'h5a); // present data + u0.wb_write(0, CR, 8'h50); // set command (stop, write) + $display("status: %t write next data 5a, generate 'stop'", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // + // delay + // +// #100000; // wait for 100us. +// $display("status: %t wait 100us", $time); + + // + // access slave (read) + // + + // drive slave address + u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit + u0.wb_write(0, CR, 8'h90 ); // set command (start, write) + $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} ); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory address + u0.wb_write(1, TXR, 8'h01); // present slave's memory address + u0.wb_write(0, CR, 8'h10); // set command (write) + $display("status: %t write slave address 01", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // drive slave address + u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit + u0.wb_write(0, CR, 8'h90 ); // set command (start, write) + $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} ); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // read data from slave + u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) + $display("status: %t read + ack", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // check data just received + u0.wb_read(1, RXR, qq); + if(qq !== 8'ha5) + $display("\nERROR: Expected a5, received %x at time %t", qq, $time); + else + $display("status: %t received %x", $time, qq); + + // read data from slave + u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) + $display("status: %t read + ack", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // check data just received + u0.wb_read(1, RXR, qq); + if(qq !== 8'h5a) + $display("\nERROR: Expected 5a, received %x at time %t", qq, $time); + else + $display("status: %t received %x", $time, qq); + + // read data from slave + u0.wb_write(1, CR, 8'h20); // set command (read, ack_read) + $display("status: %t read + ack", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // check data just received + u0.wb_read(1, RXR, qq); + $display("status: %t received %x from 3rd read address", $time, qq); + + // read data from slave + u0.wb_write(1, CR, 8'h28); // set command (read, nack_read) + $display("status: %t read + nack", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // check data just received + u0.wb_read(1, RXR, qq); + $display("status: %t received %x from 4th read address", $time, qq); + + // + // check invalid slave memory address + // + + // drive slave address + u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit + u0.wb_write(0, CR, 8'h90 ); // set command (start, write) + $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} ); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // send memory address + u0.wb_write(1, TXR, 8'h10); // present slave's memory address + u0.wb_write(0, CR, 8'h10); // set command (write) + $display("status: %t write slave memory address 10", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + // slave should have send NACK + $display("status: %t Check for nack", $time); + if(!q[7]) + $display("\nERROR: Expected NACK, received ACK\n"); + + // read data from slave + u0.wb_write(1, CR, 8'h40); // set command (stop) + $display("status: %t generate 'stop'", $time); + + // check tip bit + u0.wb_read(1, SR, q); + while(q[1]) + u0.wb_read(1, SR, q); // poll it until it is zero + $display("status: %t tip==0", $time); + + #250000; // wait 250us + $display("\n\nstatus: %t Testbench done", $time); + $finish; + end + +endmodule + +module delay (in, out); + input in; + output out; + + assign out = in; + + specify + (in => out) = (600,600); + endspecify +endmodule + + diff --git a/usrp2/fpga/opencores/i2c/bench/verilog/wb_master_model.v b/usrp2/fpga/opencores/i2c/bench/verilog/wb_master_model.v new file mode 100644 index 00000000..14ed6cbf --- /dev/null +++ b/usrp2/fpga/opencores/i2c/bench/verilog/wb_master_model.v @@ -0,0 +1,205 @@ +/////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 Wishbone Master model //// +//// //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/mem_ctrl //// +//// //// +/////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +/////////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $ +// +// $Date: 2004/02/28 15:40:42 $ +// $Revision: 1.4 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// +`include "timescale.v" + +module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty); + +parameter dwidth = 32; +parameter awidth = 32; + +input clk, rst; +output [awidth -1:0] adr; +input [dwidth -1:0] din; +output [dwidth -1:0] dout; +output cyc, stb; +output we; +output [dwidth/8 -1:0] sel; +input ack, err, rty; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [awidth -1:0] adr; +reg [dwidth -1:0] dout; +reg cyc, stb; +reg we; +reg [dwidth/8 -1:0] sel; + +reg [dwidth -1:0] q; + +//////////////////////////////////////////////////////////////////// +// +// Memory Logic +// + +initial + begin + //adr = 32'hxxxx_xxxx; + //adr = 0; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + cyc = 1'b0; + stb = 1'bx; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + #1; + $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); + end + +//////////////////////////////////////////////////////////////////// +// +// Wishbone write cycle +// + +task wb_write; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signal + #1; + adr = a; + dout = d; + cyc = 1'b1; + stb = 1'b1; + we = 1'b1; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + + end +endtask + +//////////////////////////////////////////////////////////////////// +// +// Wishbone read cycle +// + +task wb_read; + input delay; + integer delay; + + input [awidth -1:0] a; + output [dwidth -1:0] d; + + begin + + // wait initial delay + repeat(delay) @(posedge clk); + + // assert wishbone signals + #1; + adr = a; + dout = {dwidth{1'bx}}; + cyc = 1'b1; + stb = 1'b1; + we = 1'b0; + sel = {dwidth/8{1'b1}}; + @(posedge clk); + + // wait for acknowledge from slave + while(~ack) @(posedge clk); + + // negate wishbone signals + #1; + cyc = 1'b0; + stb = 1'bx; + adr = {awidth{1'bx}}; + dout = {dwidth{1'bx}}; + we = 1'hx; + sel = {dwidth/8{1'bx}}; + d = din; + + end +endtask + +//////////////////////////////////////////////////////////////////// +// +// Wishbone compare cycle (read data from location and compare with expected data) +// + +task wb_cmp; + input delay; + integer delay; + + input [awidth -1:0] a; + input [dwidth -1:0] d_exp; + + begin + wb_read (delay, a, q); + + if (d_exp !== q) + $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time); + end +endtask + +endmodule + + diff --git a/usrp2/fpga/opencores/i2c/doc/CVS/Entries b/usrp2/fpga/opencores/i2c/doc/CVS/Entries new file mode 100644 index 00000000..ec323c90 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/doc/CVS/Entries @@ -0,0 +1,2 @@ +/i2c_specs.pdf/1.3/Thu Jul 3 15:20:47 2003/-kb/ +D/src//// diff --git a/usrp2/fpga/opencores/i2c/doc/CVS/Repository b/usrp2/fpga/opencores/i2c/doc/CVS/Repository new file mode 100644 index 00000000..2ee10951 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/doc/CVS/Repository @@ -0,0 +1 @@ +i2c/doc diff --git a/usrp2/fpga/opencores/i2c/doc/CVS/Root b/usrp2/fpga/opencores/i2c/doc/CVS/Root new file mode 100644 index 00000000..44b2aa23 --- /dev/null +++ b/usrp2/fpga/opencores/i2c/doc/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/fpga/opencores/i2c/doc/CVS/Template b/usrp2/fpga/opencores/i2c/doc/CVS/Template new file mode 100644 index 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Polarity IN +LINE Normal 144 704 144 672 +PIN 144 704 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[10:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[10:0] +PINATTR Polarity OUT + diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.ngc b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.ngc new file mode 100644 index 00000000..321f44d7 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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\ No newline at end of file diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.sym b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.sym new file mode 100644 index 00000000..ab6729a9 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.sym @@ -0,0 +1,74 @@ +VERSION 5 +BEGIN SYMBOL fifo_xlnx_2Kx36_2clk +SYMBOLTYPE BLOCK +TIMESTAMP 2008 7 14 23 44 58 +SYMPIN 0 80 Input din[35:0] +SYMPIN 0 144 Input wr_en +SYMPIN 0 176 Input wr_clk +SYMPIN 0 240 Input rd_en +SYMPIN 0 272 Input rd_clk +SYMPIN 144 704 Input rst +SYMPIN 576 80 Output dout[35:0] +SYMPIN 576 208 Output full +SYMPIN 576 368 Output wr_data_count[10:0] +SYMPIN 576 432 Output empty +SYMPIN 576 592 Output rd_data_count[10:0] +BEGIN DISPLAY 32 32 TEXT fifo_xlnx_2Kx36_2clk + FONT 40 "Arial" +END DISPLAY +RECTANGLE N 32 32 544 672 +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 144 32 144 +BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 176 32 176 +BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 240 32 240 +BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 272 32 272 +BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 144 704 144 672 +BEGIN DISPLAY 144 668 PIN rst ATTR PinName + ALIGNMENT BCENTER + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 80 544 80 +END LINE +BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 208 544 208 +BEGIN DISPLAY 540 208 PIN full ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 368 544 368 +END LINE +BEGIN DISPLAY 540 368 PIN wr_data_count[10:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 432 544 432 +BEGIN DISPLAY 540 432 PIN empty ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 592 544 592 +END LINE +BEGIN DISPLAY 540 592 PIN rd_data_count[10:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +END SYMBOL diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.v b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.v new file mode 100644 index 00000000..c45dacda --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating +// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_2Kx36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [10 : 0] rd_data_count; +output [10 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(11), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("2kx18"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(2047), + .C_PROG_FULL_THRESH_NEGATE_VAL(2046), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(11), + .C_RD_DEPTH(2048), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(11), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(0), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(11), + .C_WR_DEPTH(2048), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(11), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box" + +endmodule + diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.veo b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.veo new file mode 100644 index 00000000..bb691ff4 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_2Kx36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [10 : 0] + .wr_data_count(wr_data_count)); // Bus [10 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating +// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vhd b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vhd new file mode 100644 index 00000000..834abf27 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vhd @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating +-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY fifo_xlnx_2Kx36_2clk IS + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(10 downto 0); + wr_data_count: OUT std_logic_VECTOR(10 downto 0)); +END fifo_xlnx_2Kx36_2clk; + +ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS +-- synthesis translate_off +component wrapped_fifo_xlnx_2Kx36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(10 downto 0); + wr_data_count: OUT std_logic_VECTOR(10 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 1, + c_din_width => 36, + c_has_wr_data_count => 1, + c_full_flags_rst_val => 1, + c_implementation_type => 2, + c_family => "spartan3", + c_use_embedded_reg => 0, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 0, + c_dout_width => 36, + c_msgon_val => 1, + c_rd_depth => 2048, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 11, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 11, + c_use_fwft_data_count => 0, + c_has_almost_empty => 0, + c_rd_data_count_width => 11, + c_enable_rlocs => 0, + c_wr_pntr_width => 11, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 11, + c_preload_regs => 1, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 2046, + c_wr_depth => 2048, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 2047, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "2kx18", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_fifo_xlnx_2Kx36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- synthesis translate_on + +END fifo_xlnx_2Kx36_2clk_a; + diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vho b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vho new file mode 100644 index 00000000..3fd2e43f --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vho @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component fifo_xlnx_2Kx36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(10 downto 0); + wr_data_count: OUT std_logic_VECTOR(10 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of fifo_xlnx_2Kx36_2clk: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_xlnx_2Kx36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating +-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.xco b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.xco new file mode 100644 index 00000000..3afc64a1 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.37 +# Date: Mon Jul 14 23:45:29 2008 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_2Kx36_2clk +CSET data_count=false +CSET data_count_width=11 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=2047 +CSET full_threshold_negate_value=2046 +CSET input_data_width=36 +CSET input_depth=2048 +CSET output_data_width=36 +CSET output_depth=2048 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=11 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=false +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=11 +# END Parameters +GENERATE +# CRC: a8b698f5 + diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 00000000..f1a6f789 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 00000000..7089f8c2 --- /dev/null +++ b/usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,105 @@ + + + + + + +