From b34e89b319f8c8144b50bfb6f98221bf776fc503 Mon Sep 17 00:00:00 2001 From: eb Date: Wed, 15 Oct 2008 00:42:58 +0000 Subject: [PATCH] Added firmware support for adc_mux to handle swapping I/Q, etc. Modified dsp_core_rx.v to swap A and B mapping so that the software thinks that the TVRX is connected to A/D A. ISE 10.1 SP3 is required to compile the FPGA successfully. SP2 is insufficient. It compiles with SP2, but the firmware doesn't load. Only the F led is one in that case. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9795 221aa14e-8319-0410-a670-987f0aec2ac5 --- usrp2/firmware/lib/db_init.c | 10 +++++----- usrp2/firmware/lib/db_tvrx.c | 6 +++--- usrp2/firmware/lib/memory_map.h | 9 ++++----- usrp2/firmware/lib/u2_init.c | 2 +- usrp2/fpga/sdr_lib/dsp_core_rx.v | 19 ++++++++++++++----- 5 files changed, 27 insertions(+), 19 deletions(-) diff --git a/usrp2/firmware/lib/db_init.c b/usrp2/firmware/lib/db_init.c index 20816418..160ed294 100644 --- a/usrp2/firmware/lib/db_init.c +++ b/usrp2/firmware/lib/db_init.c @@ -180,8 +180,8 @@ set_gpio_mode(int bank, struct db_base *db) } } -static int -determine_tx_mux_value(struct db_base *db) +static int __attribute__((unused)) +determine_tx_mux_value(struct db_base *db) { if (db->i_and_q_swapped) return 0x01; @@ -240,9 +240,9 @@ db_init(void) //printf("db_init: tx dbid = 0x%x\n", tx_dboard->dbid); set_gpio_mode(GPIO_TX_BANK, tx_dboard); tx_dboard->init(tx_dboard); - m = determine_tx_mux_value(tx_dboard); - dsp_tx_regs->tx_mux = m; - printf("tx_mux = 0x%x\n", m); + //m = determine_tx_mux_value(tx_dboard); + //dsp_tx_regs->tx_mux = m; + //printf("tx_mux = 0x%x\n", m); rx_dboard = lookup_dboard(I2C_ADDR_RX_A, &db_basic_rx, "Rx"); //printf("db_init: rx dbid = 0x%x\n", rx_dboard->dbid); diff --git a/usrp2/firmware/lib/db_tvrx.c b/usrp2/firmware/lib/db_tvrx.c index 062d7189..73504951 100644 --- a/usrp2/firmware/lib/db_tvrx.c +++ b/usrp2/firmware/lib/db_tvrx.c @@ -185,7 +185,7 @@ tvrx_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc) printf("N_DIV = %d, actual_freq = %d, actual_lo_freq = %d\n", N_DIV, u2_fxpt_freq_round_to_int(actual_freq),u2_fxpt_freq_round_to_int(actual_freq)); - char buf[4]; + unsigned char buf[4]; buf[0] = (N_DIV>>8) & 0xff; buf[1] = N_DIV & 0xff; buf[2] = control_byte_1; @@ -200,7 +200,7 @@ tvrx_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc) bool tvrx_set_gain(struct db_base *dbb, u2_fxpt_gain_t gain) { - struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb; + //struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb; int rfgain; int ifgain; if(gain>U2_DOUBLE_TO_FXPT_GAIN(95.0)) @@ -235,6 +235,6 @@ tvrx_set_gain(struct db_base *dbb, u2_fxpt_gain_t gain) bool tvrx_lock_detect(struct db_base *dbb) { - struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb; + // struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb; return true; } diff --git a/usrp2/firmware/lib/memory_map.h b/usrp2/firmware/lib/memory_map.h index bbf8165b..a7d38a15 100644 --- a/usrp2/firmware/lib/memory_map.h +++ b/usrp2/firmware/lib/memory_map.h @@ -411,7 +411,7 @@ typedef struct { * The default value is 0x10 * */ - volatile uint32_t tx_mux; + //volatile uint32_t tx_mux; // FIXME this register is currently unimplemented } dsp_tx_regs_t; @@ -435,7 +435,6 @@ typedef struct { volatile uint32_t dcoffset_i; // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic volatile uint32_t dcoffset_q; // Bit 31 high sets fixed offset mode, using lower 14 bits - volatile uint32_t adc_mux; // 4 bits -- lowest 2 for adc_i, next for adc_q /*! * \brief input mux configuration. @@ -449,16 +448,16 @@ typedef struct { * 3 2 1 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-------+-------+-------+-------+-------+-------+-------+-------+ - * | |Q1 |I1 |Q0 |I0 | + * | |Q0 |I0 | * +-------+-------+-------+-------+-------+-------+-------+-------+ * * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero) * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero) * - * The default value is 0x44444444 + * The default value is 0x4 * */ - volatile uint32_t rx_mux; + volatile uint32_t rx_mux; // called adc_mux in dsp_core_rx.v } dsp_rx_regs_t; diff --git a/usrp2/firmware/lib/u2_init.c b/usrp2/firmware/lib/u2_init.c index 94805569..7482040f 100644 --- a/usrp2/firmware/lib/u2_init.c +++ b/usrp2/firmware/lib/u2_init.c @@ -87,7 +87,7 @@ u2_init(void) ad9777_write_reg(12, 0); // Initial values for tx and rx mux registers - dsp_tx_regs->tx_mux = 0x10; + // dsp_tx_regs->tx_mux = 0x10; dsp_rx_regs->rx_mux = 0x44444444; // Set up serdes diff --git a/usrp2/fpga/sdr_lib/dsp_core_rx.v b/usrp2/fpga/sdr_lib/dsp_core_rx.v index a2569a1d..0e4af37f 100644 --- a/usrp2/fpga/sdr_lib/dsp_core_rx.v +++ b/usrp2/fpga/sdr_lib/dsp_core_rx.v @@ -56,17 +56,26 @@ module dsp_core_rx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(muxctrl),.changed()); + // The TVRX connects to what is called adc_b, thus A and B are + // swapped throughout the design. + // + // In the interest of expediency and keeping the s/w sane, we just remap them here. + // The I & Q fields are mapped the same: + // 0 -> "the real A" (as determined by the TVRX) + // 1 -> "the real B" + // 2 -> const zero + always @(posedge clk) - case(muxctrl[1:0]) - 0: adc_i <= adc_a_ofs; - 1: adc_i <= adc_b_ofs; + case(muxctrl[1:0]) // The I mapping + 0: adc_i <= adc_b_ofs; // "the real A" + 1: adc_i <= adc_a_ofs; 2: adc_i <= 0; default: adc_i <= 0; endcase // case(muxctrl[1:0]) always @(posedge clk) - case(muxctrl[3:2]) - 0: adc_q <= adc_b_ofs; + case(muxctrl[3:2]) // The Q mapping + 0: adc_q <= adc_b_ofs; // "the real A" 1: adc_q <= adc_a_ofs; 2: adc_q <= 0; default: adc_q <= 0; -- 2.30.2