From e76f5fbeaa15ee0679147f7e2daccd74932faaca Mon Sep 17 00:00:00 2001 From: johanknol Date: Sat, 2 Feb 2002 14:37:02 +0000 Subject: [PATCH] xa 51, work in progress git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1890 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- sim/ucsim/xa.src/glob.cc | 24 ++++--- sim/ucsim/xa.src/glob.h | 5 ++ sim/ucsim/xa.src/inst.cc | 78 ++++++++++++++++----- sim/ucsim/xa.src/regsxa.h | 50 +++++++------- sim/ucsim/xa.src/xa.cc | 100 +++++++++++++++++---------- sim/ucsim/xa.src/xacl.h | 7 ++ src/asm.c | 8 +-- src/mcs51/gen.c | 2 +- src/xa51/gen.c | 138 +++++++++++++++++++++++++++++++++++++- src/xa51/main.c | 1 + 10 files changed, 315 insertions(+), 98 deletions(-) diff --git a/sim/ucsim/xa.src/glob.cc b/sim/ucsim/xa.src/glob.cc index a139c5d7..b25b95c7 100644 --- a/sim/ucsim/xa.src/glob.cc +++ b/sim/ucsim/xa.src/glob.cc @@ -236,7 +236,7 @@ struct xa_dis_entry disass_xa[]= { {0xe308,0xff8f,' ',4,CJNE, IREG_DATA8_REL8}, // CJNE [Rd], data8, rel8 1 1 1 0 0 0 1 1 0 d d d 1 0 0 0 {0xeb08,0xff8f,' ',5,CJNE, IREG_DATA16_REL8},// CJNE [Rd], data16, rel8 1 1 1 0 1 0 1 1 0 d d d 1 0 0 0 - {0x0800,0xfffc,' ',3,CLR, BIT_ALONE }, // CLR bit 0 0 0 0 1 0 0 0 0 0 0 0 0 0 b b + {0x0800,0xfffc,' ',3,CLR, BIT_ALONE }, // CLR bit 0 0 0 0 1 0 0 0 0 0 0 0 0 0 b b {0x4100,0xf700,' ',2,CMP, REG_REG }, // CMP Rd, Rs 0 1 0 0 S 0 0 1 d d d d s s s s {0x4200,0xf708,' ',2,CMP, REG_IREG }, // CMP Rd, [Rs] 0 1 0 0 S 0 1 0 d d d d 0 s s s {0x4208,0xf708,' ',2,CMP, IREG_REG }, // CMP [Rd], Rs 0 1 0 0 S 0 1 0 s s s s 1 d d d @@ -281,11 +281,14 @@ struct xa_dis_entry disass_xa[]= { {0x9780,0xfffc,' ',4, JB, BIT_REL8 }, // JB bit,rel8 1 0 0 1 0 1 1 1 1 0 0 0 0 0 b b {0x97c0,0xfffc,' ',4, JBC, BIT_REL8 }, // JBC bit,rel8 1 0 0 1 0 1 1 1 1 1 0 0 0 0 b b - {0xd670,0xfff8,' ',2, JMP, IREG }, // JMP [Rs] 1 1 0 1 0 1 1 0 0 1 1 1 0 s s s {0xd500,0xff00,' ',3, JMP, REL16 }, // JMP rel16 1 1 0 1 0 1 0 1 + {0xd670,0xfff8,' ',2, JMP, IREG }, // JMP [Rs] 1 1 0 1 0 1 1 0 0 1 1 1 0 s s s /* JMP(2) */ {0x97a0,0xfffc,' ',4, JNB, BIT_REL8 }, // JNB bit,rel8 1 0 0 1 0 1 1 1 1 0 1 0 0 0 b b - /* JNZ, JZ, LEA(2), LSR(3?) */ + /* JNZ, JZ */ + {0x4000,0xff88,' ',3, LEA, REG_REGOFF8 }, // LEA Rd,Rs+offset8 0 1 0 0 0 0 0 0 0 d d d 0 s s s + {0x4800,0xff88,' ',3, LEA, REG_REGOFF16 }, // LEA Rd,Rs+offset16 0 1 0 0 0 0 0 0 0 d d d 0 s s s + /* LSR(3?) */ {0x8100,0xf700,' ',2,MOV, REG_REG }, // MOV Rd, Rs 1 0 0 0 S 0 0 1 d d d d s s s s {0x8200,0xf708,' ',2,MOV, REG_IREG }, // MOV Rd, [Rs] 1 0 0 0 S 0 1 0 d d d d 0 s s s @@ -356,7 +359,7 @@ struct xa_dis_entry disass_xa[]= { {0xd690,0xffff,' ',2, RETI, NO_OPERANDS }, // RETI 1 1 0 1 0 1 1 0 1 0 0 1 0 0 0 0 /* RL, RLC, RR, RRC */ {0x0810,0xfffc,' ',3, SETB, BIT_ALONE }, // SETB bit 0 0 0 0 1 0 0 0 0 0 0 1 0 0 b b - /* SEXT */ + {0x9009,0xf70f,' ',2, SEXT, REG }, // SEXT Rd 1 0 0 1 S 0 0 0 d d d d 1 0 0 1 {0x2100,0xf700,' ',2,SUB, REG_REG }, // SUB Rd, Rs 0 0 1 0 S 0 0 1 d d d d s s s s {0x2200,0xf708,' ',2,SUB, REG_IREG }, // SUB Rd, [Rs] 0 0 1 0 S 0 1 0 d d d d 0 s s s {0x2208,0xf708,' ',2,SUB, IREG_REG }, // SUB [Rd], Rs 0 0 1 0 S 0 1 0 s s s s 1 d d d @@ -404,7 +407,8 @@ struct xa_dis_entry disass_xa[]= { {0x9d03,0xff8f,' ',6,SUBB,IREGOFF16_DATA16}, //SUBB [Rd+offset16], #data16 1 0 0 1 1 1 0 1 0 d d d 0 0 1 1 {0x9603,0xff8f,' ',4,SUBB,DIRECT_DATA8 }, //SUBB direct, #data8 1 0 0 1 0 1 1 0 0 b b b 0 0 1 1 {0x9e03,0xff8f,' ',5,SUBB,DIRECT_DATA16 }, //SUBB direct, #data16 1 0 0 1 0 1 1 0 0 b b b 0 0 1 1 - /* TRAP, XCH(3) */ + {0xd630,0xfff0,' ',2,TRAP,DATA4 }, //TRAP #data4 1 1 0 1 0 1 1 0 0 0 1 1 #data4 + /* XCH(3) */ {0x7100,0xf700,' ',2,XOR, REG_REG }, // XOR Rd, Rs 0 1 1 1 S 0 0 1 d d d d s s s s {0x7200,0xf708,' ',2,XOR, REG_IREG }, // XOR Rd, [Rs] 0 1 1 1 S 0 1 0 d d d d 0 s s s @@ -419,7 +423,7 @@ struct xa_dis_entry disass_xa[]= { {0x7600,0xf708,' ',3,XOR, REG_DIRECT }, // XOR Rd, direct 0 1 1 1 S 1 1 0 d d d d 0 x x x {0x9107,0xff0f,' ',3,XOR, REG_DATA8 }, // XOR Rd, #data8 1 0 0 1 0 0 0 1 d d d d 0 1 1 1 {0x9907,0xff0f,' ',4,XOR, REG_DATA16 }, // XOR Rd, #data16 1 0 0 1 1 0 0 1 d d d d 0 1 1 1 - {0x9207,0xff8f,' ',3,XOR, IREG_DATA8 }, // XOR [Rd], #data8 1 0 0 1 0 0 1 0 0 d d d 0 1 1 1 + {0x9207,0xff8f,' ',3,XOR, IREG_DATA8 }, // XOR [Rd], #data8 1 0 0 1 0 0 1 0 0 d d d 0 1 1 1 {0x9a07,0xff8f,' ',4,XOR, IREG_DATA16 }, // XOR [Rd], #data16 1 0 0 1 1 0 1 0 0 d d d 0 1 1 1 {0x9307,0xff8f,' ',3,XOR, IREGINC_DATA8 }, // XOR [Rd+], #data8 1 0 0 1 0 0 1 1 0 d d d 0 1 1 1 {0x9b07,0xff8f,' ',4,XOR, IREGINC_DATA16 }, // XOR [Rd+], #data16 1 0 0 1 1 0 1 1 0 d d d 0 1 1 1 @@ -433,24 +437,22 @@ struct xa_dis_entry disass_xa[]= { {0x0000,0x0000, 0,1,BAD_OPCODE, REG_REG} }; -#if 0 /* * Names of SFRs */ struct name_entry sfr_tabXA51[]= { - {CPU_XA51G3, 0x400, "PSW"}, +#include "xa_sfr.cc" }; /* - * Names SBITs + * Names of SBITs */ struct name_entry bit_tabXA51[]= { - {CPU_XA51G3, 0x33b, "ETI1"}, +#include "xa_bit.cc" }; -#endif /* End of xa.src/glob.cc */ diff --git a/sim/ucsim/xa.src/glob.h b/sim/ucsim/xa.src/glob.h index d2215369..090675cb 100644 --- a/sim/ucsim/xa.src/glob.h +++ b/sim/ucsim/xa.src/glob.h @@ -149,6 +149,7 @@ enum op_operands { NO_OPERANDS, // for NOP C_BIT, C_NOTBIT, + DATA4, REG_DATA4, IREG_DATA4, IREGINC_DATA4, @@ -165,6 +166,8 @@ enum op_operands { BIT_REL8, REG_REL8, DIRECT_REL8, + REG_REGOFF8, + REG_REGOFF16, REL8, REL16, @@ -191,6 +194,8 @@ extern struct dis_entry glob_disass_xa[]; extern struct xa_dis_entry disass_xa[]; +extern struct name_entry sfr_tabXA51[]; +extern struct name_entry bit_tabXA51[]; #endif /* End of xa.src/glob.h */ diff --git a/sim/ucsim/xa.src/inst.cc b/sim/ucsim/xa.src/inst.cc index 47920fdf..aafde7ed 100644 --- a/sim/ucsim/xa.src/inst.cc +++ b/sim/ucsim/xa.src/inst.cc @@ -44,12 +44,36 @@ int cl_xa::get_reg(int word_flag, unsigned int index) // return mem_direct[0x400+index]; //} else { /* non-banked */ if (word_flag) - return get_word_direct(0x400+index); + return get_word_direct(index); else - return mem_direct[0x400+index]; + return mem_direct[index]; //} } +bool cl_xa::get_bit(int bit) { + short offset=0; + if (bit>=0x200) { + // in sfr space + bit-=0x200; + offset=0x400; + } + return mem_direct[offset + (bit/8)] & (1 << (bit%8)); +} + +void cl_xa::set_bit(int bit, int value) { + short offset=0; + if (bit>=0x200) { + // in sfr space + bit-=0x200; + offset=0x400; + } + if (value) { + mem_direct[offset + (bit/8)] |= (1 << (bit%8)); + } else { + mem_direct[offset + (bit/8)] &= ~(1 << (bit%8)); + } +} + #define RI_F0 ((code >> 4) & 0xf) #define RI_70 ((code >> 4) & 0x7) #define RI_0F (code & 0xf) @@ -186,33 +210,35 @@ int cl_xa::inst_CALL(uint code, int operands) { int jmpaddr; unsigned int sp; + bool pageZero=get_scr()&1; switch(operands) { case REL16: { jmpaddr = (signed short)fetch2(); - sp = get_sp() - 4; + sp = get_sp() - (pageZero ? 2 : 4); set_sp(sp); - store2(sp, PC); - store2(sp+2, 0); /* segment(not sure about ordering...) */ + store2(sp, PC&0xffff); + if (!pageZero) { + store2(sp+2, (PC>>16)&0xff); + } jmpaddr *= 2; - PC = (PC + jmpaddr) & 0xfffffffe; + PC = (PC + jmpaddr) & 0xfffffe; } break; case IREG: { - sp = get_sp() - 2; + sp = get_sp() - (pageZero ? 2 : 4); set_sp(sp); - store2(sp, PC); -#if 0 // only in huge model - store2(sp+2, ... -#endif + store2(sp, PC&0xffff); + if (!pageZero) { + store2(sp+2, (PC>>16)&0xff); + } jmpaddr = reg2(RI_07); jmpaddr *= 2; - PC = (PC + jmpaddr) & 0xfffffffe; + PC = (PC + jmpaddr) & 0xfffffe; } break; - /* fixme 2 more... */ /* johan: which ones? */ } return(resGO); } @@ -569,17 +595,35 @@ int cl_xa::inst_RET(uint code, int operands) { unsigned int retaddr; unsigned short sp; + bool pageZero=get_scr()&1; + sp = get_sp(); retaddr = get2(sp); -#if 0 // only in huge model - retaddr |= get2(sp+2) << 16; -#endif - set_sp(sp+2); + if (!pageZero) { + retaddr |= get2(sp+2) << 16; + set_sp(sp+4); + } else { + set_sp(sp+2); + } PC = retaddr; return(resGO); } int cl_xa::inst_RETI(uint code, int operands) { + unsigned int retaddr; + unsigned short sp; + bool pageZero=get_scr()&1; + + sp = get_sp(); + set_psw(get2(sp)); + retaddr = get2(sp+2); + if (!pageZero) { + retaddr |= get2(sp+4) << 16; + set_sp(sp+6); + } else { + set_sp(sp+4); + } + PC = retaddr; return(resGO); } int cl_xa::inst_RL(uint code, int operands) diff --git a/sim/ucsim/xa.src/regsxa.h b/sim/ucsim/xa.src/regsxa.h index 96b9281b..1334fcb4 100644 --- a/sim/ucsim/xa.src/regsxa.h +++ b/sim/ucsim/xa.src/regsxa.h @@ -28,6 +28,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /*@1@*/ +#define REGS_OFFSET 0 +//#define REGS_OFFSET 0x400 + #ifndef REGSAVR_HEADER #define REGSAVR_HEADER @@ -43,24 +46,19 @@ struct t_regs */ /* direct is a special code space for built-in ram and SFR, 1K size */ -#ifdef WORDS_BIGENDIAN #define set_word_direct(_index, _value) { \ - mem_direct[(_index)] = (_value >> 8); \ + mem_direct[(_index)+1] = (_value >> 8); \ mem_direct[(_index)] = (_value & 0xff); } #define get_word_direct(_index) \ - ( (mem_direct[(_index)] << 8) | mem_direct[(_index)+1] ) -#else -#define set_word_direct(_index, _value) { \ - wmem_direct[(_index) >> 1] = _value; } -#define get_word_direct(_index) (wmem_direct[(_index) >> 1] ) -#endif + ( (mem_direct[(_index+1)] << 8) | mem_direct[(_index)] ) +#define set_byte_direct(_index, _value) (mem_direct[_index] = _value) #define get_byte_direct(_index) (mem_direct[_index]) /* store to ram */ -#define store2(addr, val) { ram->set((t_addr) (addr), val & 0xff); \ - ram->set((t_addr) (addr+1), (val >> 8) & 0xff); } +#define store2(addr, val) { ram->set((t_addr) (addr), (val) & 0xff); \ + ram->set((t_addr) (addr+1), ((val) >> 8) & 0xff); } #define store1(addr, val) ram->set((t_addr) (addr), val) /* get from ram */ @@ -79,23 +77,19 @@ struct t_regs #define reg2(_index) get_reg(1, (_index<<1)) /* function in inst.cc */ #define reg1(_index) (unsigned char)get_reg(0, (_index)) -#define set_byte_direct(_index, _value) { \ - mem_direct[_index] = _value; \ -} - #define set_reg1(_index, _value) { \ if ((_index) < 3) { /* banked */ \ - mem_direct[0x400+(_index)] = _value; \ + mem_direct[REGS_OFFSET+(_index)] = _value; \ } else { /* non-banked */ \ - mem_direct[0x400+(_index)] = _value; \ + mem_direct[REGS_OFFSET+(_index)] = _value; \ } \ } #define set_reg2(_index, _value) { \ if ((_index) < 3) { /* banked */ \ - set_word_direct((0x400+(_index<<1)), _value); \ + set_word_direct((REGS_OFFSET+(_index<<1)), _value); \ } else { /* non-banked */ \ - set_word_direct((0x400+(_index<<1)), _value); \ + set_word_direct((REGS_OFFSET+(_index<<1)), _value); \ } \ } @@ -106,20 +100,22 @@ struct t_regs { set_reg1((_index), _value) } \ } -// fixme: implement -#define get_bit(x) (x) -#define set_bit(x,y) - /* R7 mirrors 1 of 2 real SP's */ #define set_sp(_value) { \ - { set_word_direct(0x400+(7*2), _value); } \ + { set_word_direct(REGS_OFFSET+(7*2), _value); } \ } -#define get_sp() ((TYPE_UWORD)(get_word_direct(0x400+(7*2)))) +#define get_sp() ((TYPE_UWORD)(get_word_direct(REGS_OFFSET+(7*2)))) + +/* the program status word */ +#define PSW 0x400 +#define get_psw() ((TYPE_UWORD)(get_word_direct(PSW))) +#define set_psw(_flags) set_word_direct(PSW, _flags) -// fixme: I don't know where the psw is kept, just want to compile... -#define get_psw() ((TYPE_UWORD)(get_word_direct(0x400+(0x80*2)))) -#define set_psw(_flags) set_word_direct(0x400+(0x80*2), _flags) +/* the system configuration register */ +#define SCR 0x440 +#define get_scr() get_byte_direct(SCR) +#define set_scr(scr) set_byte_direct(SCR, scr) // PSW bits... #define BIT_C 0x80 diff --git a/sim/ucsim/xa.src/xa.cc b/sim/ucsim/xa.src/xa.cc index 75db1369..e189643f 100644 --- a/sim/ucsim/xa.src/xa.cc +++ b/sim/ucsim/xa.src/xa.cc @@ -65,8 +65,14 @@ cl_xa::init(void) wmem_direct = (TYPE_UWORD *) &mem_direct[0]; + /* set SCR to osc/4, native XA mode, flat 24 */ + set_scr(0); /* initialize SP to 100H */ set_reg2(7, 0x100); + /* set PSW from reset vector */ + set_psw(getcode2(0)); + /* set PC from reset vector */ + PC = getcode2(2); printf("The XA Simulator is in development, UNSTABLE, DEVELOPERS ONLY!\n"); @@ -117,18 +123,15 @@ cl_xa::dis_tbl(void) return(glob_disass_xa); } -/*struct name_entry * -cl_xa::sfr_tbl(void) +struct name_entry *cl_xa::sfr_tbl(void) { - return(0); -}*/ + return(sfr_tabXA51); +} -/*struct name_entry * -cl_xa::bit_tbl(void) +struct name_entry *cl_xa::bit_tbl(void) { - //FIXME - return(0); -}*/ + return(bit_tabXA51); +} int cl_xa::inst_length(t_addr addr) @@ -156,6 +159,22 @@ cl_xa::longest_inst(void) return 6; } +static char dir_name[64]; +char *cl_xa::get_dir_name(short addr) { + if (!get_name(addr, sfr_tbl(), dir_name)) { + sprintf (dir_name, "0x%03x", addr); + } + return dir_name; +} + +static char bit_name[64]; +char *cl_xa::get_bit_name(short addr) { + if (!get_name(addr, bit_tbl(), bit_name)) { + sprintf (bit_name, "0x%03x", addr); + } + return bit_name; +} + /*-------------------------------------------------------------------- get_disasm_info - Given an address, return information about the opcode which resides there. @@ -336,15 +355,17 @@ cl_xa::disass(t_addr addr, char *sep) reg_strs[((code >> 4) & 0xf)] ); break; case DIRECT_REG : - sprintf(parm_str, "0x%03x,%s", - ((code & 0x7) << 8) | get_mem(MEM_ROM, addr+immed_offset), + sprintf(parm_str, "%s,%s", + get_dir_name(((code & 0x7) << 8) | + get_mem(MEM_ROM, addr+immed_offset)), reg_strs[((code >> 4) & 0xf)] ); ++immed_offset; break; case REG_DIRECT : - sprintf(parm_str, "%s,0x%03x", - reg_strs[((code >> 4) & 0xf)], - ((code & 0x7) << 8) + get_mem(MEM_ROM, addr+immed_offset) ); + sprintf(parm_str, "%s,%s", + reg_strs[((code >> 4) & 0xf)], + get_dir_name(((code & 0x7) << 8) | + get_mem(MEM_ROM, addr+immed_offset))); ++immed_offset; break; case REG_DATA8 : @@ -422,14 +443,16 @@ cl_xa::disass(t_addr addr, char *sep) immed_offset += 4; break; case DIRECT_DATA8 : - sprintf(parm_str, "0x%03x,#0x%02x", - ((code & 0x0070) << 4) | get_mem(MEM_ROM, addr+immed_offset), + sprintf(parm_str, "%s,#0x%02x", + get_dir_name(((code & 0x0070) << 4) | + get_mem(MEM_ROM, addr+immed_offset)), get_mem(MEM_ROM, addr+immed_offset+1)); immed_offset += 3; break; case DIRECT_DATA16 : - sprintf(parm_str, "%0x03x,#0x%04x", - ((code & 0x0070) << 4) | get_mem(MEM_ROM, addr+immed_offset), + sprintf(parm_str, "%s,#0x%04x", + get_dir_name(((code & 0x0070) << 4) | + get_mem(MEM_ROM, addr+immed_offset)), get_mem(MEM_ROM, addr+immed_offset+2) + (get_mem(MEM_ROM, addr+immed_offset+1)<<8)); immed_offset += 3; @@ -458,11 +481,15 @@ cl_xa::disass(t_addr addr, char *sep) strcpy(parm_str, "IREGOFF16_DATA4"); break; case DIRECT_DATA4 : - strcpy(parm_str, "DIRECT_DATA4"); + sprintf(parm_str, "%s,#0x%x", + get_dir_name(((code & 0x70)<<4) | + get_mem(MEM_ROM, addr+2)), + code&0x0f); break; case DIRECT : - sprintf(parm_str, "0x%03x", - ((code & 0x007) << 4) + get_mem(MEM_ROM, addr+2)); + sprintf(parm_str, "%s", + get_dir_name(((code & 0x007) << 4) + + get_mem(MEM_ROM, addr+2))); break; case REG : sprintf(parm_str, "%s", @@ -473,34 +500,34 @@ cl_xa::disass(t_addr addr, char *sep) reg_strs[((code >> 4) & 0xf)] ); break; case BIT_ALONE : - sprintf(parm_str, "0x%03x", - ((code&0x0003)<<8) + get_mem(MEM_ROM, addr+2)); + sprintf(parm_str, "%s", + get_bit_name(((code&0x0003)<<8) + get_mem(MEM_ROM, addr+2))); break; case BIT_REL8 : - sprintf(parm_str, "0x%03x,0x%04x", - ((code&0x0003)<<8) + get_mem(MEM_ROM, addr+2), + sprintf(parm_str, "%s,0x%04x", + get_bit_name((code&0x0003)<<8) + get_mem(MEM_ROM, addr+2), ((signed char)get_mem(MEM_ROM, addr+3)*2+addr+len)&0xfffe); break; case ADDR24 : strcpy(parm_str, "ADDR24"); break; case REG_REL8 : - //strcpy(parm_str, "REG_REL8"); sprintf(parm_str, "%s,0x%04x", reg_strs[(code>>4) & 0xf], ((signed char)get_mem(MEM_ROM, addr+2)*2+addr+len)&0xfffe); break; case DIRECT_REL8 : - strcpy(parm_str, "DIRECT_REL8"); + sprintf(parm_str, "%s,0x%04x", + get_dir_name(((code&0x07)<<8) + + get_mem(MEM_ROM, addr+2)), + ((signed char)get_mem(MEM_ROM, addr+2)*2+addr+len)&0xfffe); break; case REL8 : - //strcpy(parm_str, "REL8"); sprintf(parm_str, "0x%04x", ((signed char)get_mem(MEM_ROM, addr+1)*2+addr+len)&0xfffe); break; case REL16 : - //strcpy(parm_str, "REL16"); sprintf(parm_str, "0x%04x", ((signed short)((get_mem(MEM_ROM, addr+1)<<8) + get_mem(MEM_ROM, addr+2))*2+addr+len)&0xfffe); break; @@ -510,36 +537,37 @@ cl_xa::disass(t_addr addr, char *sep) break; case REG_DIRECT_REL8 : - sprintf(parm_str, "%s,0x%02x,0x%02x", + sprintf(parm_str, "%s,%s,0x%02x", reg_strs[((code >> 4) & 0xf)], - ((code & 0x7) << 8) + get_mem(MEM_ROM, addr+immed_offset), - (get_mem(MEM_ROM, addr+immed_offset+1) * 2) & 0xfffe ); + get_dir_name(((code & 0x7) << 8) + + get_mem(MEM_ROM, addr+immed_offset)), + ((signed char) get_mem(MEM_ROM, addr+immed_offset+1) * 2) & 0xfffe ); break; case REG_DATA8_REL8 : sprintf(parm_str, "%s,#0x%04x,0x%02x", reg_strs[((code >> 4) & 0xf)], get_mem(MEM_ROM, addr+immed_offset), - (get_mem(MEM_ROM, addr+immed_offset+1) * 2) & 0xfffe ); + ((signed char)get_mem(MEM_ROM, addr+immed_offset+1) * 2) & 0xfffe ); break; case REG_DATA16_REL8 : sprintf(parm_str, "%s,#0x%02x,0x%02x", w_reg_strs[((code >> 4) & 0x7)*2], get_mem(MEM_ROM, addr+immed_offset+1) + (get_mem(MEM_ROM, addr+immed_offset+0)<<8), - (get_mem(MEM_ROM, addr+immed_offset+2) * 2) & 0xfffe ); + ((signed char)get_mem(MEM_ROM, addr+immed_offset+2) * 2) & 0xfffe ); break; case IREG_DATA8_REL8 : sprintf(parm_str, "[%s],#0x%04x,0x%02x", reg_strs[((code >> 4) & 0x7)], get_mem(MEM_ROM, addr+immed_offset), - (get_mem(MEM_ROM, addr+immed_offset+1) * 2) & 0xfffe ); + ((signed char)get_mem(MEM_ROM, addr+immed_offset+1) * 2) & 0xfffe ); break; case IREG_DATA16_REL8 : sprintf(parm_str, "[%s],#0x%02x,0x%02x", w_reg_strs[((code >> 4) & 0x7)*2], get_mem(MEM_ROM, addr+immed_offset+1) + (get_mem(MEM_ROM, addr+immed_offset+0)<<8), - (get_mem(MEM_ROM, addr+immed_offset+2) * 2) & 0xfffe ); + ((signed char)get_mem(MEM_ROM, addr+immed_offset+2) * 2) & 0xfffe ); break; default: diff --git a/sim/ucsim/xa.src/xacl.h b/sim/ucsim/xa.src/xacl.h index 5b330452..ad2b2a1b 100644 --- a/sim/ucsim/xa.src/xacl.h +++ b/sim/ucsim/xa.src/xacl.h @@ -61,6 +61,11 @@ public: virtual struct dis_entry *dis_tbl(void); + virtual struct name_entry *sfr_tbl(void); + virtual struct name_entry *bit_tbl(void); + virtual char *get_dir_name(short); + virtual char *get_bit_name(short); + virtual int inst_length(t_addr addr); virtual int inst_branch(t_addr addr); virtual int longest_inst(void); @@ -77,6 +82,8 @@ public: virtual int exec_inst(void); virtual int get_reg(int word_flag, unsigned int index); + virtual bool get_bit(int bit); + virtual void set_bit(int bit, int value); #include "instcl.h" diff --git a/src/asm.c b/src/asm.c index 325b28a9..e1da9063 100644 --- a/src/asm.c +++ b/src/asm.c @@ -402,10 +402,10 @@ static const ASM_MAPPING _xa_asm_mapping[] = {"dbs", ".db \"%s\""}, {"dw", ".dw"}, {"dws", ".dw %s"}, - {"constbyte", "0%02xh"}, - {"constword", "0%04xh"}, - {"immedword", "#0%04Xh"}, - {"immedbyte", "#0%02Xh"}, + {"constbyte", "0x%02x"}, + {"constword", "0x%04x"}, + {"immedword", "0x%04x"}, + {"immedbyte", "0x%02x"}, {"hashedstr", "#%s"}, {"lsbimmeds", "#<%s"}, {"msbimmeds", "#>%s"}, diff --git a/src/mcs51/gen.c b/src/mcs51/gen.c index 718a1cca..c138f123 100644 --- a/src/mcs51/gen.c +++ b/src/mcs51/gen.c @@ -8632,7 +8632,7 @@ genCast (iCode * ic) /* now depending on the sign of the source && destination */ size = AOP_SIZE (result) - AOP_SIZE (right); /* if unsigned or not an integral type */ - if (SPEC_USIGN (rtype) || !IS_SPEC (rtype) || AOP_TYPE(right)==AOP_CRY) + if (!IS_SPEC (rtype) || SPEC_USIGN (rtype) || AOP_TYPE(right)==AOP_CRY) { while (size--) aopPut (AOP (result), zero, offset++); diff --git a/src/xa51/gen.c b/src/xa51/gen.c index b466d5dd..fb739458 100755 --- a/src/xa51/gen.c +++ b/src/xa51/gen.c @@ -560,7 +560,7 @@ char * printOp (operand *op) { } else if (IS_VALOP(op)) { opRegName(op, 0, line, 1); } else if (IS_TYPOP(op)) { - sprintf (line, "["); + sprintf (line, "("); if (isPtr) { if (DCL_TYPE(optype)==FPOINTER) strcat (line, "far * "); @@ -577,7 +577,7 @@ char * printOp (operand *op) { if (SPEC_USIGN(operandType(op))) strcat (line, "unsigned "); if (SPEC_LONG(operandType(op))) strcat (line, "long "); strcat (line, nounName(operandType(op))); - strcat (line, "]"); + strcat (line, ")"); } else { bailOut("printOp: unexpected operand type"); } @@ -1564,9 +1564,143 @@ static void genJumpTab (iCode * ic) { /* genCast - gen code for casting */ /*-----------------------------------------------------------------*/ static void genCast (iCode * ic) { + int size; + operand *result=IC_RESULT(ic); + operand *right=IC_RIGHT(ic); + sym_link *ctype=operandType(IC_LEFT(ic)); + sym_link *rtype=operandType(IC_RIGHT(ic)); + sym_link *etype=getSpec(rtype); + short ptrType, signedness; + printIc ("genCast", ic, 1,1,1); + + aopOp(result, TRUE, TRUE); + aopOp(right, !aopIsPtr(result), AOP_TYPE(result)!=AOP_DIR); + size=AOP_SIZE(result); + + /* if result is a bit */ + if (AOP_TYPE(result) == AOP_BIT) { + /* if right is literal, we know what the value is */ + if (AOP_TYPE(right) == AOP_LIT) { + if (operandLitValue(right)) { + emitcode ("setb", AOP_NAME(result)[0]); + } else { + emitcode ("clr", AOP_NAME(result)[0]); + } + return; + } + /* if right is also a bit */ + if (AOP_TYPE(right) == AOP_BIT) { + emitcode ("mov", "c,%s", AOP_NAME(right)); + emitcode ("mov", "%s,c", AOP_NAME(result)); + return; + } + /* we need to or */ + emitcode ("mov", "%s,%s; toBoolean", AOP_NAME(result), toBoolean(right)); + return; + } + + /* if right is a bit */ + if (AOP_TYPE(right)==AOP_BIT) { + emitcode ("mov", "c,%s", AOP_NAME(right)); + emitcode ("mov", "%s,#0", AOP_NAME(result)[0]); + emitcode ("rlc", "%s,#1", AOP_NAME(result)[0]); + if (size>2) { + emitcode ("mov", "%s,#0", AOP_NAME(result)[1]); + } + return; + } + + /* if the result is of type pointer */ + if (IS_PTR (ctype)) { + + if (AOP_SIZE(right)>1) { + emitcode ("mov", "%s,%s", AOP_NAME(result)[0], AOP_NAME(right)[0]); + } else { + emitcode ("mov", "r1l,%s", AOP_NAME(right)[0]); + emitcode ("sext", "r1h"); + emitcode ("mov", "%s,r1", AOP_NAME(result)[0]); + } + + /* if pointer to generic pointer */ + if (IS_GENPTR (ctype)) { + + if (IS_GENPTR (rtype)) { + bailOut("genCast: gptr -> gptr"); + } + + if (IS_PTR (rtype)) { + ptrType = DCL_TYPE (rtype); + } else { + /* we have to go by the storage class */ + if (!SPEC_OCLS(etype)) { + bailOut("genCast: unknown storage class"); + } else { + ptrType = PTR_TYPE (SPEC_OCLS (etype)); + } + } + + /* the generic part depends on the type */ + switch (ptrType) + { + case POINTER: + emitcode ("mov", "%s,#0x00", AOP_NAME(result)[1]); + break; + case FPOINTER: + emitcode ("mov", "%s,#0x01", AOP_NAME(result)[1]); + break; + case CPOINTER: + emitcode ("mov", "%s,#0x02", AOP_NAME(result)[1]); + break; + default: + bailOut("genCast: got unknown storage class"); + } + } + return; + } + + /* do we have to sign extend? */ + signedness = SPEC_USIGN(rtype); + + /* now depending on the size */ + switch ((AOP_SIZE(result)<<4) + AOP_SIZE(right)) + { + case 0x44: + case 0x33: + emitcode("mov", "%s,%s", AOP_NAME(result)[1], AOP_NAME(right)[1]); + // fall through + case 0x24: + case 0x22: + case 0x11: + emitcode("mov", "%s,%s", AOP_NAME(result)[0], AOP_NAME(right)[0]); + return; + case 0x41: + case 0x21: + emitcode("mov", "r1l,%s", AOP_NAME(right)[0]); + if (signedness) { + emitcode("sext", "r1h"); + } else { + emitcode("mov", "rlh,#0"); + } + emitcode("mov", "%s,r1", AOP_NAME(result)[0]); + if (size==2) + return; + // fall through: case 0x41 + emitcode("sext", AOP_NAME(result)[1]); + return; + case 14: + case 12: + emitcode("mov", "r1,%s", AOP_NAME(right)[0]); + emitcode("mov", "%s,r1l", AOP_NAME(result)[0]); + return; + case 24: + emitcode("mov", "%s,%s", AOP_NAME(result)[0], AOP_NAME(right)[0]); + return; + } + bailOut("genCast: unknown size"); } + /*-----------------------------------------------------------------*/ /* genDjnz - generate decrement & jump if not zero instrucion */ /*-----------------------------------------------------------------*/ diff --git a/src/xa51/main.c b/src/xa51/main.c index 03c72ef3..05ba1c83 100755 --- a/src/xa51/main.c +++ b/src/xa51/main.c @@ -148,6 +148,7 @@ _xa51_genAssemblerPreamble (FILE * of) fprintf (of, "\t.dw\t__sdcc_gsinit_startup\n"); fprintf (of, "\n"); fprintf (of, "__sdcc_gsinit_startup:\n"); + fprintf (of, "\tmov.b\t_SCR,#0x01\t; page zero mode\n"); fprintf (of, "\tmov\tr7,#0x%04x\n", options.stack_loc); fprintf (of, "\tcall\t_external_startup\n"); _xa51_genXINIT(of); -- 2.30.2