From 6a3f3837414a261001288bcfc8c8bfb008fb8391 Mon Sep 17 00:00:00 2001 From: bernhardheld Date: Sun, 25 Nov 2001 01:45:20 +0000 Subject: [PATCH] * sim/ucsim/s51.src/glob.cc: DS390 SFRs and bits added. * sim/ucsim/s51.src/port.cc: Port 4 and 5 added. * sim/ucsim/s51.src/regs51.h: DS390 SFRs added. * sim/ucsim/s51.src/uc390.cc: Some details improved, CKRDY works for tinibios. * sim/ucsim/s51.src/uc390cl.h: Work in progress. * sim/ucsim/sim.src/uccl.h: 6 ports for DS390. * support/regression/fwk/lib/testfwk.c: Run with tinibios. * support/regression/ports/mcs51/spec.mk: Fine tuninig. * support/regression/ports/ds390/support.c: Use tinibios. * support/regression/ports/ds390/spec.mk: Fine tuning, use tinibios. git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1640 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- sim/ucsim/s51.src/glob.cc | 260 +++++++++++++++++++++++-------- sim/ucsim/s51.src/port.cc | 2 + sim/ucsim/s51.src/regs51.h | 16 +- sim/ucsim/s51.src/uc390.cc | 303 +++++++++++++++++++++++++----------- sim/ucsim/s51.src/uc390cl.h | 12 +- sim/ucsim/sim.src/uccl.h | 2 +- 6 files changed, 438 insertions(+), 157 deletions(-) diff --git a/sim/ucsim/s51.src/glob.cc b/sim/ucsim/s51.src/glob.cc index 2f2e88ba..381f3a07 100644 --- a/sim/ucsim/s51.src/glob.cc +++ b/sim/ucsim/s51.src/glob.cc @@ -302,72 +302,154 @@ struct dis_entry disass_51[]= { struct name_entry sfr_tab51[]= { - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xe0, "ACC"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xf0, "B"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd0, "PSW"}, + {CPU_251, 0x84, "DPXL"}, + {CPU_251|CPU_DS390|CPU_DS390F, 0x93, "DPX"}, + {CPU_251, 0xa8, "IE0"}, + {CPU_251, 0xb7, "IPH0"}, + {CPU_251, 0xb8, "IPL0"}, + {CPU_251, 0xbd, "SPH"}, + {CPU_251, 0xd1, "PSW1"}, + + {CPU_DS390|CPU_DS390F, 0x80, "P4"}, + {CPU_DS390|CPU_DS390F, 0x84, "DPL1"}, + {CPU_DS390|CPU_DS390F, 0x85, "DPH1"}, + {CPU_DS390|CPU_DS390F, 0x86, "DPS"}, + {CPU_DS390|CPU_DS390F, 0x8e, "CKCON"}, + {CPU_DS390|CPU_DS390F, 0x91, "EXIF"}, + {CPU_DS390|CPU_DS390F, 0x92, "P4CNT"}, + {CPU_DS390|CPU_DS390F, 0x95, "DPX1"}, + {CPU_DS390|CPU_DS390F, 0x96, "C0RMS0"}, + {CPU_DS390|CPU_DS390F, 0x97, "C0RMS1"}, + {CPU_DS390|CPU_DS390F, 0x98, "SCON0"}, + {CPU_DS390|CPU_DS390F, 0x99, "SBUF0"}, + {CPU_DS390|CPU_DS390F, 0x9b, "ESP"}, + {CPU_DS390|CPU_DS390F, 0x9c, "AP"}, + {CPU_DS390|CPU_DS390F, 0x9d, "ACON"}, + {CPU_DS390|CPU_DS390F, 0x9e, "C0TMA0"}, + {CPU_DS390|CPU_DS390F, 0x9f, "C0TMA1"}, + {CPU_DS390|CPU_DS390F, 0xa1, "P5"}, + {CPU_DS390|CPU_DS390F, 0xa2, "P5CNT"}, + {CPU_DS390|CPU_DS390F, 0xa3, "C0C"}, + {CPU_DS390|CPU_DS390F, 0xa4, "C0S"}, + {CPU_DS390|CPU_DS390F, 0xa5, "C0IR"}, + {CPU_DS390|CPU_DS390F, 0xa6, "C0TE"}, + {CPU_DS390|CPU_DS390F, 0xa7, "C0RE"}, + {CPU_DS390|CPU_DS390F, 0xa9, "SADDR0"}, + {CPU_DS390|CPU_DS390F, 0xaa, "SADDR1"}, + {CPU_DS390|CPU_DS390F, 0xab, "C0M1C"}, + {CPU_DS390|CPU_DS390F, 0xac, "C0M2C"}, + {CPU_DS390|CPU_DS390F, 0xad, "C0M3C"}, + {CPU_DS390|CPU_DS390F, 0xae, "C0M4C"}, + {CPU_DS390|CPU_DS390F, 0xaf, "C0M5C"}, + {CPU_DS390|CPU_DS390F, 0xb3, "C0M6C"}, + {CPU_DS390|CPU_DS390F, 0xb4, "C0M7C"}, + {CPU_DS390|CPU_DS390F, 0xb5, "C0M8C"}, + {CPU_DS390|CPU_DS390F, 0xb6, "C0M9C"}, + {CPU_DS390|CPU_DS390F, 0xb7, "C0M10C"}, + {CPU_DS390|CPU_DS390F, 0xb9, "SADEN0"}, + {CPU_DS390|CPU_DS390F, 0xba, "SADEN1"}, + {CPU_DS390|CPU_DS390F, 0xbb, "C0M11C"}, + {CPU_DS390|CPU_DS390F, 0xbc, "C0M12C"}, + {CPU_DS390|CPU_DS390F, 0xbd, "C0M13C"}, + {CPU_DS390|CPU_DS390F, 0xbe, "C0M14C"}, + {CPU_DS390|CPU_DS390F, 0xbf, "C0M15C"}, + {CPU_DS390|CPU_DS390F, 0xc0, "SCON1"}, + {CPU_DS390|CPU_DS390F, 0xc1, "SBUF1"}, + {CPU_DS390|CPU_DS390F, 0xc4, "PMR"}, + {CPU_DS390|CPU_DS390F, 0xc5, "STATUS"}, + {CPU_DS390|CPU_DS390F, 0xc6, "MCON"}, + {CPU_DS390|CPU_DS390F, 0xc7, "TA"}, + {CPU_DS390|CPU_DS390F, 0xce, "COR"}, + {CPU_DS390|CPU_DS390F, 0xd1, "MCNT0"}, + {CPU_DS390|CPU_DS390F, 0xd2, "MCNT1"}, + {CPU_DS390|CPU_DS390F, 0xd3, "MA"}, + {CPU_DS390|CPU_DS390F, 0xd4, "MB"}, + {CPU_DS390|CPU_DS390F, 0xd5, "MC"}, + {CPU_DS390|CPU_DS390F, 0xd6, "C1RMS0"}, + {CPU_DS390|CPU_DS390F, 0xd7, "C1RMS1"}, + {CPU_DS390|CPU_DS390F, 0xd8, "WDCON"}, + {CPU_DS390|CPU_DS390F, 0xde, "C1TMA0"}, + {CPU_DS390|CPU_DS390F, 0xdf, "C1TMA1"}, + {CPU_DS390|CPU_DS390F, 0xe3, "C1C"}, + {CPU_DS390|CPU_DS390F, 0xe4, "C1S"}, + {CPU_DS390|CPU_DS390F, 0xe5, "C11R"}, + {CPU_DS390|CPU_DS390F, 0xe6, "C1TE"}, + {CPU_DS390|CPU_DS390F, 0xe7, "C1RE"}, + {CPU_DS390|CPU_DS390F, 0xe8, "EIE"}, + {CPU_DS390|CPU_DS390F, 0xea, "MXAX"}, + {CPU_DS390|CPU_DS390F, 0xeb, "C1M1C"}, + {CPU_DS390|CPU_DS390F, 0xec, "C1M2C"}, + {CPU_DS390|CPU_DS390F, 0xed, "C1M3C"}, + {CPU_DS390|CPU_DS390F, 0xee, "C1M4C"}, + {CPU_DS390|CPU_DS390F, 0xef, "C1M5C"}, + {CPU_DS390|CPU_DS390F, 0xf3, "C1M6C"}, + {CPU_DS390|CPU_DS390F, 0xf4, "C1M7C"}, + {CPU_DS390|CPU_DS390F, 0xf5, "C1M8C"}, + {CPU_DS390|CPU_DS390F, 0xf6, "C1M9C"}, + {CPU_DS390|CPU_DS390F, 0xf7, "C1M10C"}, + {CPU_DS390|CPU_DS390F, 0xfb, "C1M11C"}, + {CPU_DS390|CPU_DS390F, 0xfc, "C1M12C"}, + {CPU_DS390|CPU_DS390F, 0xfd, "C1M13C"}, + {CPU_DS390|CPU_DS390F, 0xfe, "C1M14C"}, + {CPU_DS390|CPU_DS390F, 0xff, "C1M15C"}, + + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x80, "P0"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x81, "SP"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x82, "DPL"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x83, "DPH"}, - {CPU_251|CPU_DS390F, 0x93, "DPX"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x80, "P0"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x90, "P1"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa0, "P2"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xb0, "P3"}, - {CPU_ALL_51|CPU_ALL_52, 0xb8, "IP"}, - {CPU_ALL_51|CPU_ALL_52, 0xa8, "IE"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x89, "TMOD"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x87, "PCON"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x88, "TCON"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8c, "TH0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x89, "TMOD"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8a, "TL0"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8d, "TH1"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8b, "TL1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8c, "TH0"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8d, "TH1"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x90, "P1"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x98, "SCON"}, - {CPU_DS390|CPU_DS390F, 0x99, "SBUF0"}, - {CPU_DS390|CPU_DS390F, 0xC1, "SBUF1"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x99, "SBUF"}, - {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x87, "PCON"}, - {CPU_ALL_52|CPU_251, 0xc8, "T2CON"}, - {CPU_ALL_52|CPU_251, 0xcd, "TH2"}, - {CPU_ALL_52|CPU_251, 0xcc, "TL2"}, - {CPU_ALL_52|CPU_251, 0xcb, "RCAP2H"}, - {CPU_ALL_52|CPU_251, 0xca, "RCAP2L"}, - {CPU_251, 0x84, "DPXL"}, - {CPU_DS390|CPU_DS390F, 0x84, "DPL1"}, - {CPU_DS390|CPU_DS390F, 0x85, "DPH1"}, - {CPU_DS390|CPU_DS390F, 0x86, "DPS"}, - {CPU_89C51R|CPU_51R, 0x8e, "AUXR"}, - {CPU_51R|CPU_89C51R|CPU_251, 0xa6, "WDTRST"}, - {CPU_51R|CPU_89C51R|CPU_251, 0xa9, "SADDR"}, - {CPU_89C51R|CPU_51R, 0xb7, "IPH"}, - {CPU_251, 0xb7, "IPH0"}, - {CPU_251, 0xa8, "IE0"}, - {CPU_251, 0xb8, "IPL0"}, - {CPU_51R|CPU_89C51R|CPU_251, 0xb9, "SADEN"}, - {CPU_251, 0xbd, "SPH"}, - {CPU_51R|CPU_89C51R|CPU_251, 0xc9, "T2MOD"}, - {CPU_251, 0xd1, "PSW1"}, - {CPU_89C51R|CPU_251, 0xd8, "CCON"}, - {CPU_89C51R|CPU_251, 0xd9, "CMOD"}, - {CPU_89C51R|CPU_251, 0xda, "CCAPM0"}, - {CPU_89C51R|CPU_251, 0xdb, "CCAPM1"}, - {CPU_89C51R|CPU_251, 0xdc, "CCAPM2"}, - {CPU_89C51R|CPU_251, 0xdd, "CCAPM3"}, - {CPU_89C51R|CPU_251, 0xde, "CCAPM4"}, - {CPU_89C51R|CPU_251, 0xe9, "CL"}, - {CPU_89C51R|CPU_251, 0xea, "CCAP0L"}, - {CPU_89C51R|CPU_251, 0xeb, "CCAP1L"}, - {CPU_89C51R|CPU_251, 0xec, "CCAP2L"}, - {CPU_89C51R|CPU_251, 0xed, "CCAP3L"}, - {CPU_89C51R|CPU_251, 0xee, "CCAP4L"}, - {CPU_89C51R|CPU_251, 0xf9, "CH"}, - {CPU_89C51R|CPU_251, 0xfa, "CCAP0H"}, - {CPU_89C51R|CPU_251, 0xfb, "CCAP1H"}, - {CPU_89C51R|CPU_251, 0xfc, "CCAP2H"}, - {CPU_89C51R|CPU_251, 0xfd, "CCAP3H"}, - {CPU_89C51R|CPU_251, 0xfe, "CCAP4H"}, - {CPU_89C51R, 0xa2, "AUXR1"}, - {CPU_DS390F, 0x9B, "ESP"}, - {CPU_DS390F, 0x9D, "ACON"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa0, "P2"}, + {CPU_ALL_51|CPU_ALL_52, 0xa8, "IE"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xb0, "P3"}, + {CPU_ALL_51|CPU_ALL_52, 0xb8, "IP"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd0, "PSW"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xe0, "ACC"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xf0, "B"}, + + {CPU_ALL_52|CPU_251, 0xc8, "T2CON"}, + {CPU_ALL_52|CPU_251, 0xca, "RCAP2L"}, + {CPU_ALL_52|CPU_251, 0xcb, "RCAP2H"}, + {CPU_ALL_52|CPU_251, 0xcc, "TL2"}, + {CPU_ALL_52|CPU_251, 0xcd, "TH2"}, + + {CPU_51R|CPU_89C51R, 0x8e, "AUXR"}, + {CPU_51R|CPU_89C51R|CPU_251, 0xa6, "WDTRST"}, + {CPU_51R|CPU_89C51R|CPU_251, 0xa9, "SADDR"}, + {CPU_51R|CPU_89C51R, 0xb7, "IPH"}, + {CPU_51R|CPU_89C51R|CPU_251, 0xb9, "SADEN"}, + {CPU_51R|CPU_89C51R|CPU_251|\ + CPU_DS390|CPU_DS390F, 0xc9, "T2MOD"}, /* fixme: isn't that CPU_ALL_52? */ + + {CPU_89C51R, 0xa2, "AUXR1"}, + {CPU_89C51R|CPU_251, 0xd8, "CCON"}, + {CPU_89C51R|CPU_251, 0xd9, "CMOD"}, + {CPU_89C51R|CPU_251, 0xda, "CCAPM0"}, + {CPU_89C51R|CPU_251, 0xdb, "CCAPM1"}, + {CPU_89C51R|CPU_251, 0xdc, "CCAPM2"}, + {CPU_89C51R|CPU_251, 0xdd, "CCAPM3"}, + {CPU_89C51R|CPU_251, 0xde, "CCAPM4"}, + {CPU_89C51R|CPU_251, 0xe9, "CL"}, + {CPU_89C51R|CPU_251, 0xea, "CCAP0L"}, + {CPU_89C51R|CPU_251, 0xeb, "CCAP1L"}, + {CPU_89C51R|CPU_251, 0xec, "CCAP2L"}, + {CPU_89C51R|CPU_251, 0xed, "CCAP3L"}, + {CPU_89C51R|CPU_251, 0xee, "CCAP4L"}, + {CPU_89C51R|CPU_251, 0xf9, "CH"}, + {CPU_89C51R|CPU_251, 0xfa, "CCAP0H"}, + {CPU_89C51R|CPU_251, 0xfb, "CCAP1H"}, + {CPU_89C51R|CPU_251, 0xfc, "CCAP2H"}, + {CPU_89C51R|CPU_251, 0xfd, "CCAP3H"}, + {CPU_89C51R|CPU_251, 0xfe, "CCAP4H"}, + {0, 0, NULL} }; @@ -385,6 +467,7 @@ struct name_entry bit_tab51[]= {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd4, "RS1"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd3, "RS0"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd2, "OV"}, + {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd1, "F1"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd0, "P"}, /* TCON */ {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8f, "TF1"}, @@ -397,16 +480,20 @@ struct name_entry bit_tab51[]= {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x88, "IT0"}, /* IE */ {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xaf, "EA"}, - {CPU_89C51R|CPU_251, 0xae, "EC"}, - {CPU_ALL_52|CPU_251, 0xad, "ET2"}, + {CPU_DS390|CPU_DS390F, 0xae, "ES1"}, + {CPU_89C51R|CPU_251, 0xae, "EC"}, + {CPU_ALL_52|CPU_251, 0xad, "ET2"}, + {CPU_DS390|CPU_DS390F, 0xac, "ES0"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xac, "ES"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xab, "ET1"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xaa, "EX1"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa9, "ET0"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa8, "EX0"}, /* IP */ - {CPU_89C51R|CPU_251, 0xbe, "PPC"}, - {CPU_ALL_52, 0xbd, "PT2"}, + {CPU_89C51R|CPU_251, 0xbe, "PPC"}, + {CPU_DS390|CPU_DS390F, 0xbe, "PS1"}, + {CPU_ALL_52, 0xbd, "PT2"}, + {CPU_DS390|CPU_DS390F, 0xbc, "PS0"}, {CPU_ALL_51|CPU_ALL_52, 0xbc, "PS"}, {CPU_ALL_51|CPU_ALL_52, 0xbb, "PT1"}, {CPU_ALL_51|CPU_ALL_52, 0xba, "PX1"}, @@ -421,8 +508,17 @@ struct name_entry bit_tab51[]= {CPU_251, 0xb9, "IPL0.1"}, {CPU_251, 0xb8, "IPL0.0"}, /* SCON */ - {CPU_51R|CPU_89C51R|CPU_251, 0x9f, "FE/SM0"}, - {CPU_ALL_51|CPU_ALL_52, 0x9f, "SM0"}, + {CPU_DS390|CPU_DS390F, 0x9f, "SM0/FE_0"}, + {CPU_DS390|CPU_DS390F, 0x9e, "SM1_0"}, + {CPU_DS390|CPU_DS390F, 0x9d, "SM2_0"}, + {CPU_DS390|CPU_DS390F, 0x9c, "REN_0"}, + {CPU_DS390|CPU_DS390F, 0x9b, "TB8_0"}, + {CPU_DS390|CPU_DS390F, 0x9a, "RB8_0"}, + {CPU_DS390|CPU_DS390F, 0x99, "TI_0"}, + {CPU_DS390|CPU_DS390F, 0x98, "RI_0"}, + + {CPU_51R|CPU_89C51R|CPU_251, 0x9f, "FE/SM0"}, + {CPU_ALL_51|CPU_ALL_52, 0x9f, "SM0"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9e, "SM1"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9d, "SM2"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9c, "REN"}, @@ -430,6 +526,15 @@ struct name_entry bit_tab51[]= {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9a, "RB8"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x99, "TI"}, {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x98, "RI"}, + /* SCON 1 */ + {CPU_DS390|CPU_DS390F, 0xc7, "SM0/FE_1"}, + {CPU_DS390|CPU_DS390F, 0xc6, "SM1_1"}, + {CPU_DS390|CPU_DS390F, 0xc5, "SM2_1"}, + {CPU_DS390|CPU_DS390F, 0xc4, "REN_1"}, + {CPU_DS390|CPU_DS390F, 0xc3, "TB8_1"}, + {CPU_DS390|CPU_DS390F, 0xc2, "RB8_1"}, + {CPU_DS390|CPU_DS390F, 0xc1, "TI_1"}, + {CPU_DS390|CPU_DS390F, 0xc0, "RI_1"}, /* T2CON */ {CPU_ALL_52|CPU_251, 0xcf, "TF2"}, {CPU_ALL_52|CPU_251, 0xce, "EXF2"}, @@ -456,6 +561,33 @@ struct name_entry bit_tab51[]= {CPU_89C51R|CPU_251, 0x92, "EXI"}, {CPU_89C51R|CPU_251, 0x91, "T2EX"}, {CPU_89C51R|CPU_251, 0x90, "T2"}, + /* WDCON */ + {CPU_DS390|CPU_DS390F, 0xdf, "SMOD_1"}, + {CPU_DS390|CPU_DS390F, 0xde, "POR,"}, + {CPU_DS390|CPU_DS390F, 0xdd, "EPF1"}, + {CPU_DS390|CPU_DS390F, 0xdc, "PF1"}, + {CPU_DS390|CPU_DS390F, 0xdb, "WDIF"}, + {CPU_DS390|CPU_DS390F, 0xda, "WTRF"}, + {CPU_DS390|CPU_DS390F, 0xd9, "EWT"}, + {CPU_DS390|CPU_DS390F, 0xd8, "RWT"}, + /* EIE */ + {CPU_DS390|CPU_DS390F, 0xef, "CANBIE"}, + {CPU_DS390|CPU_DS390F, 0xee, "C0IE"}, + {CPU_DS390|CPU_DS390F, 0xed, "C1IE"}, + {CPU_DS390|CPU_DS390F, 0xec, "EWDI"}, + {CPU_DS390|CPU_DS390F, 0xeb, "EX5"}, + {CPU_DS390|CPU_DS390F, 0xea, "EX4"}, + {CPU_DS390|CPU_DS390F, 0xe9, "EX3"}, + {CPU_DS390|CPU_DS390F, 0xe8, "EX2"}, + /* EIP */ + {CPU_DS390|CPU_DS390F, 0xef, "CANBIP"}, + {CPU_DS390|CPU_DS390F, 0xee, "C0IP"}, + {CPU_DS390|CPU_DS390F, 0xed, "C1IP"}, + {CPU_DS390|CPU_DS390F, 0xec, "PWDI"}, + {CPU_DS390|CPU_DS390F, 0xeb, "PX5"}, + {CPU_DS390|CPU_DS390F, 0xea, "PX4"}, + {CPU_DS390|CPU_DS390F, 0xe9, "PX3"}, + {CPU_DS390|CPU_DS390F, 0xe8, "PX2"}, {0, 0, NULL} }; diff --git a/sim/ucsim/s51.src/port.cc b/sim/ucsim/s51.src/port.cc index 3367c724..e746bfa0 100644 --- a/sim/ucsim/s51.src/port.cc +++ b/sim/ucsim/s51.src/port.cc @@ -44,6 +44,8 @@ cl_port::init(void) case 1: sfr= P1; break; case 2: sfr= P2; break; case 3: sfr= P3; break; + case 4: sfr= P4; break; + case 5: sfr= P5; break; default: sfr= P0; return(1); } return(0); diff --git a/sim/ucsim/s51.src/regs51.h b/sim/ucsim/s51.src/regs51.h index b9f55a5c..ab07115c 100644 --- a/sim/ucsim/s51.src/regs51.h +++ b/sim/ucsim/s51.src/regs51.h @@ -61,14 +61,20 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define AUXR 0x8e /* Auxiliary Register */ #define AUXR1 0xa2 /* Secondary Aux Register */ +#define P4 0x80 #define DPXL 0x84 /* */ #define DPL1 0x84 /* 2nd Data Pointer Low byte */ #define DPH1 0x85 /* 2nd Data Pointer High byte */ #define DPS 0x86 /* DPS 1H=DPTR is DPL1/DPH1,... */ +#define EXIF 0x91 /* */ +#define P4CNT 0x92 /* */ #define DPX 0x93 /* Data Pointer HHigh byte */ #define DPX1 0x95 /* Data Pointer HHigh byte */ -#define ESP 0x9B /* Extended Stack Pointer */ -#define ACON 0x9D /* */ +#define ESP 0x9b /* Extended Stack Pointer */ +#define ACON 0x9d /* */ +#define P5 0xa1 +#define P5CNT 0xa2 /* */ +#define C0C 0xa3 /* */ #define WDTRST 0xa6 /* */ #define IE0 0xa8 /* */ #define SADDR 0xa9 /* */ @@ -77,7 +83,11 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define IPL0 0xb8 /* */ #define SADEN 0xb9 /* */ #define SPH 0xbd /* */ +#define PMR 0xc4 /* */ +#define MCON 0xc6 /* */ +#define TA 0xc7 /* */ #define T2MOD 0xc9 /* */ +#define COR 0xce /* */ #define PSW1 0xd1 /* */ #define MCNT0 0xd1 #define MCNT1 0xd2 @@ -85,12 +95,14 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define MB 0xd4 /* MB register from math accelerator */ #define MC 0xd5 /* MC register from math accelerator */ #define CCON 0xd8 /* */ +#define WDCON 0xd8 /* */ #define CMOD 0xd9 /* */ #define CCAPM0 0xda /* */ #define CCAPM1 0xdb /* */ #define CCAPM2 0xdc /* */ #define CCAPM3 0xdd /* */ #define CCAPM4 0xde /* */ +#define C1C 0xe3 /* */ #define CL 0xe9 /* */ #define CCAP0L 0xea /* */ #define CCAP1L 0xeb /* */ diff --git a/sim/ucsim/s51.src/uc390.cc b/sim/ucsim/s51.src/uc390.cc index e8e029fe..ec37e006 100644 --- a/sim/ucsim/s51.src/uc390.cc +++ b/sim/ucsim/s51.src/uc390.cc @@ -29,12 +29,15 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA // Bernhard's ToDo list: -// - add sfr-descriptions to s51.src/glob.cc // - implement math accelerator // - consider ACON bits -// - proc_write_sp (*aof_SP); insert this at the appropriate places +// - proc_write_sp (*aof_SP) / resSTACK_OV / event_at: insert this at the appropriate places // - buy some memory to run s51 with 2*4 Meg ROM/XRAM +// strcpy (mem(MEM_ROM) ->addr_format, "0x%06x"); +// strcpy (mem(MEM_XRAM)->addr_format, "0x%06x"); + + #include "ddconfig.h" #include @@ -319,20 +322,52 @@ t_uc390::t_uc390 (int Itype, int Itech, class cl_sim *asim): { if (Itype == CPU_DS390F) { - printf ("FLAT24 MODE SET, warning: experimental code\n"); + printf ("24-bit flat mode, warning: lots of sfr-functions not implemented!\n> "); flat24_flag = 1; } } - // strcpy (mem(MEM_ROM) ->addr_format, "0x%06x"); - // strcpy (mem(MEM_XRAM)->addr_format, "0x%06x"); +/* + * Setting up SFR area to reset value + */ + +void +t_uc390::clear_sfr(void) +{ + int i; + + for (i = 0; i < SFR_SIZE; i++) + sfr->set(i, 0); + /* SFR value */ + sfr->set(0x80, 0xff); /* P4 */ + sfr->set(0x81, 0x07); /* SP */ + sfr->set(0x86, 0x04); /* DPS */ + sfr->set(0x90, 0xff); /* P1 */ + sfr->set(0x92, 0xbf); /* P4CNT */ + sfr->set(0x9b, 0xfc); /* ESP */ + if (flat24_flag) + sfr->set(ACON, 0xfa); /* ACON; AM1 set: 24-bit flat */ + else + sfr->set(ACON, 0xf8); /* ACON */ + sfr->set(0xa0, 0xff); /* P2 */ + sfr->set(0xa1, 0xff); /* P5 */ + sfr->set(0xa3, 0x09); /* COC */ + sfr->set(0xb0, 0xff); /* P3 */ + sfr->set(0xb8, 0x80); /* IP */ + sfr->set(0xc5, 0x10); /* STATUS */ + sfr->set(0xc6, 0x10); /* MCON */ + sfr->set(0xc7, 0xff); /* TA */ + sfr->set(0xc9, 0xe4); /* T2MOD */ + sfr->set(0xd2, 0x2f); /* MCNT1 */ + sfr->set(0xe3, 0x09); /* C1C */ + + prev_p1 = port_pins[1] & sfr->get(P1); + prev_p3 = port_pins[3] & sfr->get(P3); +} t_addr t_uc390::get_mem_size (enum mem_class type) { - //if ((sfr->get (ACON) & 0x3) == 2) - if (!flat24_flag) - return t_uc52::get_mem_size (type); switch (type) { case MEM_ROM: @@ -355,24 +390,23 @@ t_uc390::get_mem_size (enum mem_class type) ulong t_uc390::read_mem(enum mem_class type, t_mem addr) { - //if ((sfr->get (ACON) & 0x3) == 2) if (type == MEM_XRAM && - flat24_flag && - addr >= 0x400000) + addr >= 0x400000 && + (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */ { addr -= 0x400000; type = MEM_IXRAM; } - return t_uc51::read_mem (type, addr); + return t_uc51::read_mem (type, addr); /* 24 bit */ } ulong t_uc390::get_mem (enum mem_class type, t_addr addr) { if (type == MEM_XRAM && - flat24_flag && - addr >= 0x400000) + addr >= 0x400000 && + (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */ { addr -= 0x400000; type = MEM_IXRAM; @@ -384,8 +418,8 @@ void t_uc390::write_mem (enum mem_class type, t_addr addr, t_mem val) { if (type == MEM_XRAM && - flat24_flag && - addr >= 0x400000) + addr >= 0x400000 && + (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */ { addr -= 0x400000; type = MEM_IXRAM; @@ -397,8 +431,8 @@ void t_uc390::set_mem (enum mem_class type, t_addr addr, t_mem val) { if (type == MEM_XRAM && - flat24_flag && - addr >= 0x400000) + addr >= 0x400000 && + (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */ { addr -= 0x400000; type = MEM_IXRAM; @@ -469,30 +503,6 @@ t_uc390::pop_byte (int *Pres) return uc; } -/* - * 0x05 2 12 INC addr - *____________________________________________________________________________ - * - */ -int -t_uc390::inst_inc_addr (uchar code) -{ - uchar *addr; - - addr = get_direct (fetch (), &event_at.wi, &event_at.ws); - - /* mask off the 2Hex bit adjacent to the 1H bit which selects - which DPTR we use. This is a feature of 80C390. - You can do INC DPS and it only effects bit 1. */ - if (code == DPS) - (*addr) ^= 1; /* just toggle */ - else - (*addr)++; - - proc_write (addr); - return resGO; -} - /* * 0xa3 1 24 INC DPTR *____________________________________________________________________________ @@ -521,22 +531,20 @@ t_uc390::inst_inc_dptr (uchar code) } dptr = sfr->get (ph) * 256 + sfr->get (pl); - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ dptr += sfr->get (px) *256*256; if (dps & 0x80) /* decr set */ dptr--; else dptr++; - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ sfr->set (px, (dptr >> 16) & 0xff); sfr->set (event_at.ws = ph, (dptr >> 8) & 0xff); sfr->set (pl, dptr & 0xff); if (dps & 0x20) /* auto-switch dptr */ - sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */ tick (1); return resGO; } @@ -569,8 +577,7 @@ t_uc390::inst_jmp_$a_dptr (uchar code) PC = (sfr->get (ph) * 256 + sfr->get (pl) + read_mem (MEM_SFR, ACC)) & (EROM_SIZE - 1); - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ PC += sfr->get (px) * 256*256; tick (1); @@ -602,14 +609,13 @@ t_uc390::inst_mov_dptr_$data (uchar code) px = DPX; } - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ sfr->set (px, fetch ()); sfr->set (event_at.ws = ph, fetch ()); sfr->set (pl, fetch ()); if (dps & 0x20) /* auto-switch dptr */ - sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */ tick (1); return resGO; @@ -641,8 +647,7 @@ t_uc390::inst_movc_a_$a_dptr (uchar code) px = DPX; } - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ sfr->set (ACC, get_mem (MEM_ROM, event_at.rc = (sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl) + @@ -653,7 +658,7 @@ t_uc390::inst_movc_a_$a_dptr (uchar code) sfr->get (ACC)) & (EROM_SIZE-1))); if (dps & 0x20) /* auto-switch dptr */ - sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */ tick (1); return resGO; @@ -723,8 +728,7 @@ t_uc390::inst_movx_a_$dptr (uchar code) px = DPX; } - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ sfr->set (event_at.ws = ACC, get_mem (MEM_XRAM, event_at.rx = sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl))); @@ -734,7 +738,7 @@ t_uc390::inst_movx_a_$dptr (uchar code) event_at.rx = sfr->get (ph) * 256 + sfr->get (pl))); if (dps & 0x20) /* auto-switch dptr */ - sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */ tick (1); return resGO; @@ -765,8 +769,7 @@ t_uc390::inst_movx_$dptr_a (uchar code) px = DPX; } - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ set_mem (MEM_XRAM, event_at.wx = sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl), sfr->get (event_at.rs = ACC)); @@ -776,7 +779,7 @@ t_uc390::inst_movx_$dptr_a (uchar code) sfr->get (event_at.rs = ACC)); if (dps & 0x20) /* auto-switch dptr */ - sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */ + sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */ tick (1); return resGO; @@ -793,8 +796,7 @@ t_uc390::inst_ajmp_addr (uchar code) { uchar x, h, l; - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ { x = (code >> 5) & 0x07; h = fetch (); @@ -822,8 +824,7 @@ t_uc390::inst_ljmp (uchar code) { uchar x, h, l; - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ { x = fetch (); h = fetch (); @@ -852,8 +853,7 @@ t_uc390::inst_acall_addr (uchar code) uchar x, h, l, *sp, *aof_SP; int res; - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ { x = (code >> 5) & 0x07; h = fetch (); @@ -909,8 +909,7 @@ t_uc390::inst_lcall (uchar code, uint addr) if (!addr) { /* this is a normal lcall */ - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ x = fetch (); h = fetch (); l = fetch (); @@ -920,8 +919,7 @@ t_uc390::inst_lcall (uchar code, uint addr) res = push_byte ( PC & 0xff); /* push low byte */ res = push_byte ((PC >> 8) & 0xff); /* push high byte */ - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ { res = push_byte ((PC >> 16) & 0xff); /* push x byte */ if (addr) @@ -951,16 +949,14 @@ t_uc390::inst_ret (uchar code) uchar x = 0, h, l; int res; - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ x = pop_byte (&res); h = pop_byte (&res); l = pop_byte (&res); tick (1); - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ { tick (1); PC = x * 256*256 + h * 256 + l; @@ -983,16 +979,13 @@ t_uc390::inst_reti (uchar code) uchar x = 0, h, l; int res; - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ x = pop_byte (&res); h = pop_byte (&res); l = pop_byte (&res); tick (1); - //if ((sfr->get (ACON) & 0x3) == 2) - if (flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ { tick (1); PC = x * 256*256 + h * 256 + l; @@ -1012,6 +1005,142 @@ t_uc390::inst_reti (uchar code) return res; } +/* + * Processing write operation to IRAM + * + * It starts serial transmition if address is in SFR and it is + * SBUF. Effect on IE is also checked. + */ + +void +t_uc390::proc_write(uchar *addr) +{ + if (addr == &((sfr->umem8)[SBUF])) + { + s_out= sfr->get(SBUF); + s_sending= DD_TRUE; + s_tr_bit = 0; + s_tr_tick= 0; + s_tr_t1 = 0; + } + else if (addr == &((sfr->umem8)[IE])) + was_reti= DD_TRUE; + else if (addr == &((sfr->umem8)[DPS])) + { + *addr &= 0xe5; + *addr |= 0x04; + } + else if (addr == &((sfr->umem8)[EXIF])) + { + } + else if (addr == &((sfr->umem8)[P4CNT])) + { + ; + } + else if (addr == &((sfr->umem8)[ACON])) + { + *addr |= 0xf8; + /* lockout: IDM1:IDM0 and SA can't be set at the same time */ + if (((sfr->umem8)[MCON] & 0xc0) == 0xc0) /* IDM1 and IDM0 set? */ + *addr &= ~0x04; /* lockout SA */ + } + else if (addr == &((sfr->umem8)[P5CNT])) + { + ; + } + else if (addr == &((sfr->umem8)[C0C])) + { + ; + } + else if (addr == &((sfr->umem8)[PMR])) + { + *addr |= 0x03; + // todo: check previous state + if ((*addr & 0xd0) == 0x90) /* CD1:CD0 set to 10, CTM set */ + { + ctm_ticks = ticks->ticks; + (sfr->umem8)[EXIF] &= ~0x08; /* clear CKRDY */ + } + else + ctm_ticks = 0; + } + else if (addr == &((sfr->umem8)[MCON])) + { + *addr |= 0x10; + /* lockout: IDM1:IDM0 and SA can't be set at the same time */ + if (((sfr->umem8)[ACON] & 0x04) == 0x04) /* SA set? */ + *addr &= ~0xc0; /* lockout IDM1:IDM0 */ + } + else if (addr == &((sfr->umem8)[TA])) + { + if (*addr == 0x55) + { + timed_access_ticks = ticks->ticks; + timed_access_state = 1; + } + else if (*addr == 0xaa && + timed_access_state == 1 && + timed_access_ticks == ticks->ticks + 1) + { + timed_access_ticks = ticks->ticks; + timed_access_state = 2; + } + else + timed_access_state = 0; + } + else if (addr == &((sfr->umem8)[T2MOD])) + *addr |= 0xe0; + else if (addr == &((sfr->umem8)[COR])) + { + ; + } + else if (addr == &((sfr->umem8)[WDCON])) + { + ; + } + else if (addr == &((sfr->umem8)[C1C])) + { + ; + } + else if (addr == &((sfr->umem8)[MCNT1])) + *addr |= 0x0f; +} + + +/* + * Reading IRAM or SFR, but if address points to a port, it reads + * port pins instead of port latches + */ + +uchar +t_uc390::read(uchar *addr) +{ + //if (addr == &(MEM(MEM_SFR)[P1])) + if (addr == &(sfr->umem8[P1])) + return get_mem (MEM_SFR, P1) & port_pins[1]; + //if (addr == &(MEM(MEM_SFR)[P2])) + else if (addr == &(sfr->umem8[P2])) + return get_mem (MEM_SFR, P2) & port_pins[2]; + //if (addr == &(MEM(MEM_SFR)[P3])) + else if (addr == &(sfr->umem8[P3])) + return get_mem (MEM_SFR, P3) & port_pins[3]; + //if (addr == &(MEM(MEM_SFR)[P4])) + else if (addr == &(sfr->umem8[P4])) + return get_mem (MEM_SFR, P4) & port_pins[4]; + //if (addr == &(MEM(MEM_SFR)[P5])) + else if (addr == &(sfr->umem8[P5])) + return get_mem (MEM_SFR, P5) & port_pins[5]; + else if (addr == &(sfr->umem8[EXIF])) + if (ctm_ticks && + ticks->ticks >= ctm_ticks + 65535) + { + *addr |= 0x08; /* set CKRDY */ + ctm_ticks = 0; + } + return *addr; +} + + /* * Disassembling an instruction */ @@ -1019,12 +1148,12 @@ t_uc390::inst_reti (uchar code) struct dis_entry * t_uc390::dis_tbl (void) { - //if ((sfr->get (ACON) & 0x3) == 2) - if (!flat24_flag) + if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */ + return disass_390f; + else return disass_51; //t_uc51::dis_tbl (); - return disass_390f; } char * @@ -1034,8 +1163,7 @@ t_uc390::disass (t_addr addr, char *sep) char *buf, *p, *b, *t; t_mem code; - //if ((sfr->get (ACON) & 0x3) == 2) - if (!flat24_flag) + if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */ return t_uc51::disass (addr, sep); code = get_mem (MEM_ROM, addr); @@ -1143,13 +1271,12 @@ t_uc390::disass (t_addr addr, char *sep) } void -t_uc390::print_regs(class cl_console *con) +t_uc390::print_regs (class cl_console *con) { t_addr start; uchar data; - //if ((sfr->get (ACON) & 0x3) == 2) - if (!flat24_flag) + if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */ { t_uc51::print_regs (con); return; diff --git a/sim/ucsim/s51.src/uc390cl.h b/sim/ucsim/s51.src/uc390cl.h index 8cd93fb7..ca8e4f4f 100644 --- a/sim/ucsim/s51.src/uc390cl.h +++ b/sim/ucsim/s51.src/uc390cl.h @@ -37,7 +37,8 @@ class t_uc390: public t_uc52 { public: t_uc390(int Itype, int Itech, class cl_sim *asim); - int flat24_flag; /* true if flat24 mode code: ((ACON:9Dh & 3) == 0x2) */ + + virtual void clear_sfr(void); // making objects virtual t_addr get_mem_size (enum mem_class type); @@ -49,7 +50,6 @@ public: virtual void set_mem (enum mem_class type, t_addr addr, t_mem val); /* mods for dual-dptr */ - virtual int inst_inc_addr(uchar code); virtual int inst_inc_dptr(uchar code); virtual int inst_jmp_$a_dptr(uchar code); virtual int inst_mov_dptr_$data(uchar code); @@ -69,14 +69,22 @@ public: virtual int inst_push (uchar code); virtual int inst_pop (uchar code); + /* miscellaneous */ + virtual void proc_write(uchar *addr); + /* mods for disassembly of flat24 */ virtual struct dis_entry *dis_tbl(void); virtual char * disass(t_addr addr, char *sep); virtual void print_regs(class cl_console *con); protected: + int flat24_flag; /* true if processor == ds390f */ + unsigned long ctm_ticks; /* mini-state-machine for "crystal multiplier" */ + unsigned long timed_access_ticks; + int timed_access_state; /* 0: idle; 1: $aa written; 2: $55 written */ virtual int push_byte (uchar uc); virtual uchar pop_byte (int *Pres); + virtual uchar read(uchar *addr); }; /* End of s51.src/uc390cl.h */ diff --git a/sim/ucsim/sim.src/uccl.h b/sim/ucsim/sim.src/uccl.h index c969e1ce..63e5365f 100644 --- a/sim/ucsim/sim.src/uccl.h +++ b/sim/ucsim/sim.src/uccl.h @@ -196,7 +196,7 @@ public: /* Following fields and virtual methods defined in uc51 I don't have energy to redesign them:-( */ public: - uchar port_pins[4]; // Port pins + uchar port_pins[6]; // Port pins; 0...5 for DS390 public: virtual void proc_write(uchar *addr) {} virtual void set_p_flag(void) {} -- 2.30.2