From: johanknol Date: Wed, 6 Feb 2002 17:05:26 +0000 (+0000) Subject: work in progress X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=f14435d5192436647b96d495324d223671e08b9a;p=fw%2Fsdcc work in progress git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1901 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- diff --git a/sim/ucsim/xa.src/glob.cc b/sim/ucsim/xa.src/glob.cc index 83497dd5..f8efeb13 100644 --- a/sim/ucsim/xa.src/glob.cc +++ b/sim/ucsim/xa.src/glob.cc @@ -202,8 +202,8 @@ struct xa_dis_entry disass_xa[]= { {0,0x9605,0xff8f,' ',4, AND,DIRECT_DATA8 }, // AND direct, #data8 1 0 0 1 0 1 1 0 0 b b b 0 1 0 1 {0,0x9e05,0xff8f,' ',5, AND,DIRECT_DATA16 }, // AND direct, #data16 1 0 0 1 0 1 1 0 1 b b b 0 1 0 1 - {0,0x0840,0xfffc,' ',2,ANL, C_BIT }, // ANL C, bit 0 0 0 0 1 0 0 0 0 1 0 0 0 0 b b - {0,0x0850,0xfffc,' ',2,ANL, C_NOTBIT }, // ANL C, /bit 0 0 0 0 1 0 0 0 0 1 0 1 0 0 b b + {0,0x0840,0xfffc,' ',2,ANL, CY_BIT }, // ANL C, bit 0 0 0 0 1 0 0 0 0 1 0 0 0 0 b b + {0,0x0850,0xfffc,' ',2,ANL, CY_NOTBIT }, // ANL C, /bit 0 0 0 0 1 0 0 0 0 1 0 1 0 0 b b {0,0xc150,0xf300,' ',2,ASL, REG_REG }, // ASL Rd, Rs 1 1 0 0 S S 0 1 d d d d s s s s {0,0xdd00,0xff00,' ',2,ASL, REG_DATA5 }, // ASL Rd, #data5 (dword) 1 1 0 1 1 1 0 1 d d d #data5 {0,0xd100,0xf700,' ',2,ASL, REG_DATA4 }, // ASL Rd, #data4 1 1 0 1 S S 0 1 d d d d #data4 @@ -316,7 +316,11 @@ struct xa_dis_entry disass_xa[]= { {0,0x9d08,0xff8f,' ',6,MOV, IREGOFF16_DATA16}, // MOV [Rd+offset16], #data16 1 0 0 1 1 1 0 1 0 d d d 1 0 0 0 {0,0x9608,0xff8f,' ',4,MOV, DIRECT_DATA8 }, // MOV direct, #data8 1 0 0 1 0 1 1 0 0 b b b 1 0 0 0 {0,0x9e08,0xff8f,' ',5,MOV, DIRECT_DATA16 }, // MOV direct, #data16 1 0 0 1 0 1 1 0 0 b b b 1 0 0 0 - /* MOV(5) */ + {0,0x9700,0xf788,' ',4,MOV, DIRECT_DIRECT }, // MOV direct, direct 1 0 0 1 S 1 1 1 0 d d d 0 d d d + {0,0x900f,0xff0f,' ',2,MOV, REG_USP }, // MOV Rd, USP 1 0 0 1 0 0 0 0 d d d d 1 1 1 1 + {0,0x980f,0xff0f,' ',2,MOV, USP_REG }, // MOV USP, RS 1 0 0 1 0 0 0 0 s s s s 1 1 1 1 + {0,0x0820,0xfffc,' ',3,MOV, CY_BIT }, // MOV C, bit 0 0 0 0 1 0 0 0 0 0 1 0 0 0 b b + {0,0x0830,0xfffc,' ',3,MOV, BIT_CY }, // MOV bit, C 0 0 0 0 1 0 0 0 0 0 1 1 0 0 b b {0,0x8000,0xf308,' ',2,MOVC, REG_IREGINC }, // MOVC Rd,[Rs+] 1 0 0 0 S 0 0 0 d d d d 0 s s s {0,0x904e,0xffff,' ',2,MOVC, A_APLUSDPTR }, // MOVC A,[A+DPTR] 1 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 {0,0x904c,0xffff,' ',2,MOVC, A_APLUSPC }, // MOVC A,[A+PC] 1 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 @@ -348,8 +352,8 @@ struct xa_dis_entry disass_xa[]= { {0,0x9d06,0xff8f,' ',6, OR, IREGOFF16_DATA16}, // OR [Rd+offset16], #data16 1 0 0 1 1 1 0 1 0 d d d 0 1 1 0 {0,0x9606,0xff8f,' ',4, OR, DIRECT_DATA8 }, // OR direct, #data8 1 0 0 1 0 1 1 0 0 b b b 0 1 1 0 {0,0x9e06,0xff8f,' ',5, OR, DIRECT_DATA16 }, // OR direct, #data16 1 0 0 1 0 1 1 0 0 b b b 0 1 1 0 - {0,0x0860,0xfffc,' ',3, ORL, C_BIT }, // ORL C, bit 0 0 0 0 1 0 0 0 0 1 1 0 0 0 b b - {0,0x0870,0xfffc,' ',3, ORL, C_NOTBIT }, // ORL C, /bit 0 0 0 0 1 0 0 0 0 1 1 1 0 0 b b + {0,0x0860,0xfffc,' ',3, ORL, CY_BIT }, // ORL C, bit 0 0 0 0 1 0 0 0 0 1 1 0 0 0 b b + {0,0x0870,0xfffc,' ',3, ORL, CY_NOTBIT }, // ORL C, /bit 0 0 0 0 1 0 0 0 0 1 1 1 0 0 b b {0,0x8710,0xf7f8,' ',3, POP, DIRECT }, // POP direct 1 0 0 0 S 1 1 1 0 0 0 1 0 d d d {1,0x2700,0xb700,' ',2, POP, RLIST }, // POP Rlist 0 H 1 0 S 1 1 1 rlist {0,0x8700,0xf7f8,' ',3, POPU, DIRECT }, // POPU direct 1 0 0 0 S 1 1 1 0 0 0 0 0 d d d diff --git a/sim/ucsim/xa.src/glob.h b/sim/ucsim/xa.src/glob.h index 9d731fe7..008bef38 100644 --- a/sim/ucsim/xa.src/glob.h +++ b/sim/ucsim/xa.src/glob.h @@ -147,8 +147,9 @@ enum op_operands { // odd-ball ones NO_OPERANDS, // for NOP - C_BIT, - C_NOTBIT, + CY_BIT, + BIT_CY, + CY_NOTBIT, DATA4, REG_DATA4, REG_DATA5, @@ -162,6 +163,7 @@ enum op_operands { IREG, BIT_ALONE, DIRECT, + DIRECT_DIRECT, RLIST, ADDR24, BIT_REL8, @@ -170,6 +172,9 @@ enum op_operands { REG_REGOFF8, REG_REGOFF16, + REG_USP, + USP_REG, + REL8, REL16, diff --git a/sim/ucsim/xa.src/inst.cc b/sim/ucsim/xa.src/inst.cc index 1549367c..451774ab 100644 --- a/sim/ucsim/xa.src/inst.cc +++ b/sim/ucsim/xa.src/inst.cc @@ -509,7 +509,7 @@ int cl_xa::inst_JBC(uint code, int operands) if (get_bit(bitAddr)) { PC = (PC+jmpAddr)&0xfffffe; } - set_bit(bitAddr); + set_bit(bitAddr,0); return(resGO); } int cl_xa::inst_JNB(uint code, int operands) diff --git a/sim/ucsim/xa.src/xa.cc b/sim/ucsim/xa.src/xa.cc index 26dceffa..41b840c7 100644 --- a/sim/ucsim/xa.src/xa.cc +++ b/sim/ucsim/xa.src/xa.cc @@ -472,8 +472,13 @@ cl_xa::disass(t_addr addr, char *sep) case NO_OPERANDS : // for NOP strcpy(parm_str, ""); break; - case C_BIT : - strcpy(parm_str, "C_BIT"); + case CY_BIT : + sprintf(parm_str, "C,%s", + get_bit_name(((code&0x0003)<<8) + get_mem(MEM_ROM, addr+2))); + break; + case BIT_CY : + sprintf(parm_str, "%s,C", + get_bit_name(((code&0x0003)<<8) + get_mem(MEM_ROM, addr+2))); break; case REG_DATA4 : strcpy(parm_str, "REG_DATA4"); @@ -535,7 +540,12 @@ cl_xa::disass(t_addr addr, char *sep) get_mem(MEM_ROM, addr+2)), ((signed char)get_mem(MEM_ROM, addr+2)*2+addr+len)&0xfffe); break; - + case REG_USP: + sprintf(parm_str, "REG_USP"); + break; + case USP_REG: + sprintf(parm_str, "USP_REG"); + break; case REL8 : sprintf(parm_str, "0x%04x", ((signed char)get_mem(MEM_ROM, addr+1)*2+addr+len)&0xfffe);