From: MaartenBrock Date: Tue, 8 May 2007 16:59:41 +0000 (+0000) Subject: * device/lib/mcs51/crtxinit.asm: added disabled version for dual dptr X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=d449808b93c0aa2097228b94160090e01fffbdd6;p=fw%2Fsdcc * device/lib/mcs51/crtxinit.asm: added disabled version for dual dptr * device/include/mcs51/uPSD33xx.h: added sfr DPS as alias for DPTC * support/regression/tests/longlit.c: modified to be tested at all and to pass the actual test git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4795 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- diff --git a/ChangeLog b/ChangeLog index f69cb0d0..7b4a6b07 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,10 @@ +2007-05-08 Maarten Brock + + * device/lib/mcs51/crtxinit.asm: added disabled version for dual dptr + * device/include/mcs51/uPSD33xx.h: added sfr DPS as alias for DPTC + * support/regression/tests/longlit.c: modified to be tested at all and + to pass the actual test + 2007-05-07 Jesus Calvino-Fraga * device/include/mcs51/uPSD33xx.h: Added. @@ -33,7 +40,7 @@ clarified sone points, added sections on how to add devices to the PIC14/PIC16 ports -2007-05-05 Maarten Brock +2007-05-06 Maarten Brock * src/z80/peeph.def: fixed bug in rule 2 diff --git a/device/include/mcs51/uPSD33xx.h b/device/include/mcs51/uPSD33xx.h index 9f835ee8..e86949fe 100644 --- a/device/include/mcs51/uPSD33xx.h +++ b/device/include/mcs51/uPSD33xx.h @@ -46,6 +46,7 @@ SFR(DPL, 0x82); // Data Pointer Low. SFR(DPH, 0x83); // Data Pointer High. SFR(DPTC, 0x85); // Data Pointer Control Register. +SFR(DPS, 0x85); // Data Pointer Control Register alias for SDCC #define AT 0x40 //0:Manually Select Data Pointer / 1:Auto Toggle between DPTR0 and DPTR1 #define DPSE0 0x01 // 0:DPTR0 Selected for use as DPTR / 1:DPTR1 Selected for use as DPTR @@ -68,7 +69,7 @@ SFR(PCON, 0x87); // Power Control. #define TCLK1 0x04 //Transmit Clock Flag (UART1) #define PD 0x02 //Power-Down Mode Enable. #define IDL 0x01 //Idle Mode Enable. - + SFR(TCON, 0x88); // Timer/Counter Control. SBIT(TF1, 0x88, 7); // Timer 1 overflow flag. SBIT(TR1, 0x88, 6); // Timer 1 run control flag. @@ -78,7 +79,7 @@ SFR(TCON, 0x88); // Timer/Counter Control. SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit. SBIT(IE0, 0x88, 1); // Interrupt 0 flag. SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit. - + SFR(TMOD, 0x89); // Timer/Counter Mode Control. #define GATE1 0x80 // External enable for timer 1. #define C_T1 0x40 // Timer or counter select for timer 1. @@ -132,7 +133,7 @@ SFR(P1, 0x90); // Port 1 SBIT(SPIRXD, 0x90, 5); SBIT(SPITXD, 0x90, 6); SBIT(SPISEL, 0x90, 7); - + SFR(P3SFS, 0x91); // Port 3 Special Function Select Register #define P3SF7 0x80 #define P3SF6 0x40 @@ -162,14 +163,14 @@ SFR(P4SFS1, 0x93); //Port 4 Special Function Select 1 Register. #define P4SF12 0x04 #define P4SF11 0x02 #define P4SF10 0x01 - + SFR(ADCPS, 0x94); // ADC pre-scaller? #define ADCCE 0x08 // ADC Conversion Reference Clock Enable. //ADC Reference Clock PreScaler. Only three Prescaler values are allowed: #define ADCPS2 0x02 // Resulting ADC clock is fOSC. #define ADCPS1 0x01 // Resulting ADC clock is fOSC/2. #define ADCPS0 0x00 // Resulting ADC clock is fOSC/4. - + SFR(ADAT0, 0x95); // A/D result register (bits 0 to 7). SFR(ADAT1, 0x96); // A/D result register (bits 8 and 9). SFR(ACON, 0x97); // A/D control register. @@ -181,7 +182,7 @@ SFR(ACON, 0x97); // A/D control register. #define ADS0 0x04 // Analog channel Select bit 1. #define ADST 0x02 // ADC Start Bit. #define ADSF 0x01 // ADC Status Bit. - + SFR(SCON, 0x98); // For compatibity with legacy code SFR(SCON0, 0x98); // Serial Port UART0 Control Register SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0. @@ -205,7 +206,7 @@ SFR(BUSCON, 0x9D); // Bus Control Register. #define RDW0 0x04 // RD Wait bit 1. #define CW1 0x02 // PSEN Wait bit 2. #define CW0 0x01 // PSEN Wait bit 1. - + SFR(PCACL0, 0xA2); // The low 8 bits of PCA 0 16-bit counter. SFR(PCACH0, 0xA3); // The high 8 bits of PCA 0 16-bit counter. SFR(PCACON0, 0xA4); // PCA 0 Control Register. @@ -222,14 +223,14 @@ SFR(IEA, 0xA7); // Interrupt Enable Addition Register. #define EI2C 0x02 // Enable I2C Interrupt. SFR(IE, 0xA8); // Interrupt Enable Register. - SBIT(EA, 0xA8, 7); // Global disable bit. + SBIT(EA, 0xA8, 7); // Global disable bit. SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt. SBIT(ES0, 0xA8, 4); // Enable UART0 Interrupt. SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt. SBIT(EX1, 0xA8, 2); // Enable External Interrupt INT1. SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt. SBIT(EX0, 0xA8, 0); // Enable External Interrupt INT0. - + SFR(TCMMODE0, 0xA9); // TCM 0 Mode. SFR(TCMMODE1, 0xAA); // TCM 1 Mode. SFR(TCMMODE2, 0xAB); // TCM 2 Mode. @@ -245,7 +246,7 @@ SFR(TCMMODE5, 0xBF); // TCM 5 Mode. #define TOGGLE 0x04 // A match on the comparator results in a toggling output on CEXn pin. #define PWM1 0x02 // PWM mode bit 2. #define PWM0 0x01 // PWM mode bit 1. - + SFR(CAPCOML0, 0xAC); // Capture/Compare register low of TCM 0. SFR(CAPCOMH0, 0xAD); // Capture/Compare register High of TCM 0. SFR(CAPCOML1, 0xAF); // Capture/Compare register low of TCM 1. @@ -330,7 +331,7 @@ SFR(CCON0, 0xF9); // Clock Control Register. #define CPUPS2 0x04 // MCUCLK Pre-Scaler bit 3. #define CPUPS1 0x02 // MCUCLK Pre-Scaler bit 2. #define CPUPS0 0x01 // MCUCLK Pre-Scaler bit 1. - + SFR(CCON2, 0xFB); // Pre-scaler value for PCA0. #define PCA0CE 0x10 // PCA0 Clock Enable. #define PCA0PS3 0x08 // PCA0 Pre-Scaler bit 4. @@ -352,14 +353,14 @@ SFR(SPICLKD, 0xD2); // SPI Prescaler (Clock Divider) Register. #define DIV16 0x10 #define DIV8 0x08 #define DIV4 0x04 - + SFR(SPISTAT, 0xD3); // SPI Interface Status Register. #define BUSY 0x10 // SPI Busy. #define TEISF 0x08 // Transmission End Interrupt Source flag. #define RORISF 0x04 // Receive Overrun Interrupt Source flag. #define TISF 0x02 // Transfer Interrupt Source flag. #define RISF 0x01 // Receive Interrupt Source flag. - + SFR(SPITDR, 0xD4); // SPI transmit data register. SFR(SPIRDR, 0xD5); // SPI receive data register. @@ -370,7 +371,7 @@ SFR(SPICON0, 0xD6); // SPI Control Register 0. #define SSEL 0x08 // Slave Selection. #define FLSB 0x04 // First LSB. #define SPO 0x02 // Sampling Polarity. - + SFR(SPICON1, 0xD7); // SPI Interface Control Register 1. #define TEIE 0x08 // Transmission End Interrupt Enable. #define RORIE 0x04 // Receive Overrun Interrupt Enable. diff --git a/device/lib/mcs51/crtxinit.asm b/device/lib/mcs51/crtxinit.asm index 84126fa7..87021c66 100644 --- a/device/lib/mcs51/crtxinit.asm +++ b/device/lib/mcs51/crtxinit.asm @@ -1,26 +1,32 @@ ; /*------------------------------------------------------------------------- -; +; ; crtxinit.asm :- C run-time: copy XINIT to XISEG -; +; ; This library is free software; you can redistribute it and/or modify it ; under the terms of the GNU Library General Public License as published by the ; Free Software Foundation; either version 2, or (at your option) any ; later version. -; +; ; This library is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU Library General Public License for more details. -; +; ; You should have received a copy of the GNU Library General Public License ; along with this program; if not, write to the Free Software ; Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -; +; ; In other words, you are welcome to use, share and improve this program. ; You are forbidden to forbid anyone else to use, share and improve -; what you give them. Help stamp out software-hoarding! +; what you give them. Help stamp out software-hoarding! ; -------------------------------------------------------------------------*/ +; Set DUAL_DPTR to 1 and reassemble if your derivative has dual data pointers +; Especially useful if movx @Ri cannot go beyond the first 256 bytes of xdata +; due to lack of P2 or _XPAGE +; If the derivative has auto-toggle or auto-increment it can be further optimized + DUAL_DPTR = 0 + .area CSEG (CODE) .area GSINIT0 (CODE) .area GSINIT1 (CODE) @@ -31,10 +37,37 @@ .area GSINIT (CODE) .area GSFINAL (CODE) - .globl __XPAGE - .area GSINIT3 (CODE) - + + .if DUAL_DPTR + + .globl _DPS ; assume DPSEL is in DPS bit0 + +__mcs51_genXINIT:: + mov r1,#l_XINIT + mov a,r1 + orl a,#(l_XINIT >> 8) + jz 00003$ + mov r2,#((l_XINIT+255) >> 8) + orl _DPS,#0x01 ; set DPSEL, select DPTR1 + mov dptr,#s_XINIT ; DPTR1 for code + dec _DPS ; clear DPSEL, select DPTR0 + mov dptr,#s_XISEG ; DPTR0 for xdata +00001$: clr a + inc _DPS ; set DPSEL, select DPTR1 + movc a,@a+dptr + inc dptr + dec _DPS ; clear DPSEL, select DPTR0 + movx @dptr,a + inc dptr + djnz r1,00001$ + djnz r2,00001$ +00003$: + + .else + + .globl __XPAGE + __mcs51_genXINIT:: mov r1,#l_XINIT mov a,r1 @@ -55,4 +88,5 @@ __mcs51_genXINIT:: djnz r2,00001$ mov __XPAGE,#0xFF 00003$: - \ No newline at end of file + + .endif diff --git a/support/regression/tests/longlit.c b/support/regression/tests/longlit.c index c8e7fcf6..ded0d15e 100644 --- a/support/regression/tests/longlit.c +++ b/support/regression/tests/longlit.c @@ -4,12 +4,14 @@ #include #define OSCILLATOR 11059200 -#define BAUD 19200 +#define BAUD 19200L #define T1_RELOAD_VALUE -(2*OSCILLATOR)/(32*12*BAUD) static unsigned char T1=T1_RELOAD_VALUE; -void test (void) { +void +testLongLit(void) +{ ASSERT(T1==0xfd); }