From: MaartenBrock <MaartenBrock@4a8a32a2-be11-0410-ad9d-d568d2c75423>
Date: Mon, 2 Jul 2007 14:38:54 +0000 (+0000)
Subject: * device/include/mcs51/C8051F360.h: fixed bug #1746410, thanks Chris Jones
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=d446cb1283ca88e68db9054d33921ef96bedbf29;p=fw%2Fsdcc

* device/include/mcs51/C8051F360.h: fixed bug #1746410, thanks Chris Jones

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@4872 4a8a32a2-be11-0410-ad9d-d568d2c75423
---

diff --git a/ChangeLog b/ChangeLog
index fbead692..d0f8bd8f 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2007-07-02 Maarten Brock <sourceforge.brock AT dse.nl>
+
+	* device/include/mcs51/C8051F360.h: fixed bug #1746410, thanks Chris Jones
+
 2007-06-29 Borut Razem <borut.razem AT siol.net>
 
 	* src/SDCCmain.c: fixed bug
diff --git a/device/include/mcs51/C8051F360.h b/device/include/mcs51/C8051F360.h
index d920e526..04efab4b 100644
--- a/device/include/mcs51/C8051F360.h
+++ b/device/include/mcs51/C8051F360.h
@@ -103,7 +103,7 @@ SFR(P2,         0xA0);      // Port 2
 SFR(SPI0CFG,    0xA1);      // SPI Configuration
 SFR(SPI0CKR,    0xA2);      // SPI Clock Rate Control
 SFR(SPI0DAT,    0xA3);      // SPI Data
-SFR(SFRNEXT,    0xA7);      // SFR Page Select
+SFR(SFRPAGE,    0xA7);      // SFR Page Select
 SFR(IE,         0xA8);      // Interrupt Enable
    SBIT(EX0,      0xA8, 0); // Enable External Interrupt 0
    SBIT(ET0,      0xA8, 1); // Enable Timer 0 Interrupt
@@ -164,7 +164,7 @@ SFR(TMR2CN,     0xC8);      // Timer/Counter 2 Control
    SBIT(TF2CEN,   0xC8, 4); // Timer 2 Low-Frequency Oscillator Capture Enable
    SBIT(TF2LEN,   0xC8, 5); // Timer 2 Low Byte Interrupt Enable
    SBIT(TF2L,     0xC8, 6); // Timer 2 Low Byte Overflow Flag
-   SBIT(TF2L,     0xC8, 7); // Timer 2 High Byte Overflow Flag
+   SBIT(TF2H,     0xC8, 7); // Timer 2 High Byte Overflow Flag
 SFR16(TMR2RL,   0xCA);      // Timer/Counter 2 Reload Word
    SFR(TMR2RLL,   0xCA);    // Timer/Counter 2 Reload Low Byte
    SFR(TMR2RLH,   0xCB);    // Timer/Counter 2 Reload High Byte
@@ -239,9 +239,9 @@ SFR16(PCA0,     0xF9);      // PCA Counter Word
 SFR16(PCA0CP0,  0xFB);      // PCA Capture 0 Word
    SFR(PCA0CPL0,  0xFB);    // PCA Capture 0 Low Byte
    SFR(PCA0CPH0,  0xFC);    // PCA Capture 0 High Byte
-SFR16(PCA0CP5,  0xFD);      // PCA Capture 5 Word
-   SFR(PCA0CPL5,  0xFD);    // PCA Capture 5 Low Byte
-   SFR(PCA0CPH5,  0xFE);    // PCA Capture 5 High Byte
+SFR16(PCA0CP4,  0xFD);      // PCA Capture 4 Word
+   SFR(PCA0CPL4,  0xFD);    // PCA Capture 4 Low Byte
+   SFR(PCA0CPH4,  0xFE);    // PCA Capture 4 High Byte
 SFR(VDM0CN,     0xFF);      // VDD Monitor Control
 
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