From: Bdale Garbee <bdale@gag.com>
Date: Sun, 11 Sep 2011 23:19:53 +0000 (-0600)
Subject: add attribute to cause DRC to skip the outline layer
X-Git-Tag: fab-v0.2~20
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=c3b77606b34e985369af183187138b96482790ff;p=hw%2Fteleterra

add attribute to cause DRC to skip the outline layer
---

diff --git a/teleterra.pcb b/teleterra.pcb
index 05d5e47..95a5410 100644
--- a/teleterra.pcb
+++ b/teleterra.pcb
@@ -2154,6 +2154,7 @@ Layer(2 "bottom")
 )
 Layer(3 "outline")
 (
+	Attribute("PCB::skip-drc" "1")
 	Line[27550 0 342550 0 1000 2000 "lock"]
 	Line[27550 175200 342550 175200 1000 2000 "lock"]
 	Line[0 28550 0 146650 1000 2000 "lock"]