From: jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>
Date: Thu, 20 Sep 2007 03:34:02 +0000 (+0000)
Subject: Merged r6475:6484 from jcorgan/radar into trunk.
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=a64acfe8cef1fa73da333d0860b3da0c97a5eb45;p=debian%2Fgnuradio

Merged r6475:6484 from jcorgan/radar into trunk.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6485 221aa14e-8319-0410-a670-987f0aec2ac5
---

diff --git a/gr-radar-mono/src/fpga/lib/Makefile.am b/gr-radar-mono/src/fpga/lib/Makefile.am
index 2a7d6d88..2c520538 100644
--- a/gr-radar-mono/src/fpga/lib/Makefile.am
+++ b/gr-radar-mono/src/fpga/lib/Makefile.am
@@ -28,7 +28,7 @@ EXTRA_DIST = 			\
 		radar_tx.v	\
 		radar_rx.v	\
 		dac_interface.v	\
-		fifo32_4k.v	\
+		fifo32_2k.v	\
 		cordic_nco.v
 
 MOSTLYCLEANFILES = *~ *.bak
diff --git a/gr-radar-mono/src/fpga/lib/fifo32_2k.v b/gr-radar-mono/src/fpga/lib/fifo32_2k.v
new file mode 100755
index 00000000..c045b70e
--- /dev/null
+++ b/gr-radar-mono/src/fpga/lib/fifo32_2k.v
@@ -0,0 +1,161 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo 
+
+// ============================================================
+// File Name: fifo32_2k.v
+// Megafunction Name(s):
+// 			scfifo
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo32_2k (
+	clock,
+	data,
+	rdreq,
+	sclr,
+	wrreq,
+	empty,
+	q);
+
+	input	  clock;
+	input	[31:0]  data;
+	input	  rdreq;
+	input	  sclr;
+	input	  wrreq;
+	output	  empty;
+	output	[31:0]  q;
+
+	wire  sub_wire0;
+	wire [31:0] sub_wire1;
+	wire  empty = sub_wire0;
+	wire [31:0] q = sub_wire1[31:0];
+
+	scfifo	scfifo_component (
+				.rdreq (rdreq),
+				.sclr (sclr),
+				.clock (clock),
+				.wrreq (wrreq),
+				.data (data),
+				.empty (sub_wire0),
+				.q (sub_wire1)
+				// synopsys translate_off
+				,
+				.aclr (),
+				.almost_empty (),
+				.almost_full (),
+				.full (),
+				.usedw ()
+				// synopsys translate_on
+				);
+	defparam
+		scfifo_component.add_ram_output_register = "OFF",
+		scfifo_component.intended_device_family = "Cyclone",
+		scfifo_component.lpm_numwords = 2048,
+		scfifo_component.lpm_showahead = "OFF",
+		scfifo_component.lpm_type = "scfifo",
+		scfifo_component.lpm_width = 32,
+		scfifo_component.lpm_widthu = 11,
+		scfifo_component.overflow_checking = "OFF",
+		scfifo_component.underflow_checking = "OFF",
+		scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "2048"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "32"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_2k_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/lib/fifo32_4k.v b/gr-radar-mono/src/fpga/lib/fifo32_4k.v
deleted file mode 100644
index f31d020f..00000000
--- a/gr-radar-mono/src/fpga/lib/fifo32_4k.v
+++ /dev/null
@@ -1,161 +0,0 @@
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: scfifo 
-
-// ============================================================
-// File Name: fifo32_4k.v
-// Megafunction Name(s):
-// 			scfifo
-//
-// Simulation Library Files(s):
-// 			altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2007 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions 
-//and other software and tools, and its AMPP partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Altera Program License 
-//Subscription Agreement, Altera MegaCore Function License 
-//Agreement, or other applicable license agreement, including, 
-//without limitation, that your use is for the sole purpose of 
-//programming logic devices manufactured by Altera and sold by 
-//Altera or its authorized distributors.  Please refer to the 
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module fifo32_4k (
-	clock,
-	data,
-	rdreq,
-	sclr,
-	wrreq,
-	empty,
-	q);
-
-	input	  clock;
-	input	[31:0]  data;
-	input	  rdreq;
-	input	  sclr;
-	input	  wrreq;
-	output	  empty;
-	output	[31:0]  q;
-
-	wire  sub_wire0;
-	wire [31:0] sub_wire1;
-	wire  empty = sub_wire0;
-	wire [31:0] q = sub_wire1[31:0];
-
-	scfifo	scfifo_component (
-				.rdreq (rdreq),
-				.sclr (sclr),
-				.clock (clock),
-				.wrreq (wrreq),
-				.data (data),
-				.empty (sub_wire0),
-				.q (sub_wire1)
-				// synopsys translate_off
-				,
-				.aclr (),
-				.almost_empty (),
-				.almost_full (),
-				.full (),
-				.usedw ()
-				// synopsys translate_on
-				);
-	defparam
-		scfifo_component.add_ram_output_register = "OFF",
-		scfifo_component.intended_device_family = "Cyclone",
-		scfifo_component.lpm_numwords = 4096,
-		scfifo_component.lpm_showahead = "OFF",
-		scfifo_component.lpm_type = "scfifo",
-		scfifo_component.lpm_width = 32,
-		scfifo_component.lpm_widthu = 12,
-		scfifo_component.overflow_checking = "OFF",
-		scfifo_component.underflow_checking = "OFF",
-		scfifo_component.use_eab = "ON";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Depth NUMERIC "4096"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
-// Retrieval info: PRIVATE: UsedW NUMERIC "0"
-// Retrieval info: PRIVATE: Width NUMERIC "32"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "32"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_bb.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_wave*.jpg TRUE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/gr-radar-mono/src/fpga/lib/radar.v b/gr-radar-mono/src/fpga/lib/radar.v
index d71d9397..1023d2f2 100644
--- a/gr-radar-mono/src/fpga/lib/radar.v
+++ b/gr-radar-mono/src/fpga/lib/radar.v
@@ -24,7 +24,7 @@
 module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
 	     tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
 	     rx_adc_i_i,rx_adc_q_i,
-	     rx_strobe_o,rx_ech_i_o,rx_ech_q_o,auto_tr_o);
+	     rx_strobe_o,rx_ech_i_o,rx_ech_q_o,io_tx_ena_o);
    
    // System interface
    input         clk_i;		// Master clock @ 64 MHz
@@ -37,7 +37,7 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
    output        tx_strobe_o;	// Generate an transmitter output sample
    output [13:0] tx_dac_i_o;	// I channel transmitter output to DAC
    output [13:0] tx_dac_q_o;    // Q channel transmitter output to DAC
-   output        auto_tr_o;     // Transmit/Receive switching
+   output        io_tx_ena_o;   // Transmit/Receive switching
       
    // Receive subsystem
    input  [15:0] rx_adc_i_i;	// I channel input from ADC
@@ -65,8 +65,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
      (.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
       .reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled),
       .tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
-      .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num));
-    assign auto_tr_o = tx_ctrl;
+      .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num),
+      .io_tx_ena_o(io_tx_ena_o));
 
    radar_tx transmitter
      ( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o),
diff --git a/gr-radar-mono/src/fpga/lib/radar_config.vh b/gr-radar-mono/src/fpga/lib/radar_config.vh
index 251b2dba..89a33673 100644
--- a/gr-radar-mono/src/fpga/lib/radar_config.vh
+++ b/gr-radar-mono/src/fpga/lib/radar_config.vh
@@ -38,3 +38,4 @@
 `define FR_RADAR_AMPL           `FR_USER_5
 `define FR_RADAR_FSTART         `FR_USER_6
 `define FR_RADAR_FINCR          `FR_USER_7
+`define FR_RADAR_ATRDEL         `FR_USER_8
diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v
index 86494110..05b78198 100644
--- a/gr-radar-mono/src/fpga/lib/radar_control.v
+++ b/gr-radar-mono/src/fpga/lib/radar_control.v
@@ -23,8 +23,8 @@
 
 module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
 		     tx_side_o,dbg_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
-		     ampl_o,fstart_o,fincr_o,pulse_num_o);
-
+		     ampl_o,fstart_o,fincr_o,pulse_num_o,io_tx_ena_o);
+   
    // System interface
    input         clk_i;		// Master clock @ 64 MHz
    input  [6:0]  saddr_i;	// Configuration bus address
@@ -42,7 +42,8 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
    output [31:0] fstart_o;
    output [31:0] fincr_o;
    output [15:0] pulse_num_o;
-
+   output        io_tx_ena_o;
+   
    // Internal configuration
    wire 	 lp_ena;
    wire 	 md_ena;
@@ -52,7 +53,8 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
    wire   [15:0] t_sw;
    wire   [15:0] t_look;
    wire   [31:0] t_idle;
-
+   wire   [31:0] atrdel;
+   
    // Configuration from host
    wire [31:0] 	 mode;
    setting_reg #(`FR_RADAR_MODE)   sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
@@ -86,6 +88,9 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
    setting_reg #(`FR_RADAR_FINCR)  sr_fincr(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
 					    .out(fincr_o));
 
+   setting_reg #(`FR_RADAR_ATRDEL)  sr_atrdel(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
+					    .out(atrdel));
+   
    // Pulse state machine
    `define ST_ON   4'b0001
    `define ST_SW   4'b0010
@@ -152,5 +157,10 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,reset_o,
    assign tx_strobe_o = count[0]; // Drive DAC inputs at 32 MHz
    assign tx_ctrl_o = (state == `ST_ON);
    assign rx_ctrl_o = (state == `ST_LOOK);
+
+   // Create delayed version of tx_ctrl_o to drive mixers and TX/RX switch
+   atr_delay atr_delay(.clk_i(clk_i),.rst_i(reset_o),.ena_i(1'b1),.tx_empty_i(!tx_ctrl_o),
+		       .tx_delay_i(atrdel[27:16]),.rx_delay_i(atrdel[11:0]),
+		       .atr_tx_o(io_tx_ena_o));
    
 endmodule // radar_control
diff --git a/gr-radar-mono/src/fpga/lib/radar_rx.v b/gr-radar-mono/src/fpga/lib/radar_rx.v
index 29bbadd4..4b0b83c4 100644
--- a/gr-radar-mono/src/fpga/lib/radar_rx.v
+++ b/gr-radar-mono/src/fpga/lib/radar_rx.v
@@ -55,12 +55,12 @@ module radar_rx(clk_i,rst_i,ena_i,dbg_i,pulse_num_i,rx_in_i_i,
 
 // Use model if simulating, otherwise Altera Megacell
 `ifdef SIMULATION
-   fifo_1clk #(32, 4096) buffer(.clock(clk_i),.sclr(rst_i),
+   fifo_1clk #(32, 2048) buffer(.clock(clk_i),.sclr(rst_i),
 				.data(fifo_inp),.wrreq(ena_i),
 				.rdreq(fifo_ack),.q(fifo_out),
 				.empty(fifo_empty));
 `else
-   fifo32_4k buffer(.clock(clk_i),.sclr(rst_i),
+   fifo32_2k buffer(.clock(clk_i),.sclr(rst_i),
 		    .data(fifo_inp),.wrreq(ena_i),
 		    .rdreq(fifo_ack),.q(fifo_out),
 		    .empty(fifo_empty));
diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.sav b/gr-radar-mono/src/fpga/tb/radar_tb.sav
index 69e48d21..66289c07 100644
--- a/gr-radar-mono/src/fpga/tb/radar_tb.sav
+++ b/gr-radar-mono/src/fpga/tb/radar_tb.sav
@@ -1,4 +1,4 @@
-*-24.712317 7100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-24.712532 40200000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 @28
 radar_tb.clk
 radar_tb.ena
@@ -18,13 +18,14 @@ radar_tb.uut.transmitter.freq[31:0]
 radar_tb.tx_strobe
 @8420
 radar_tb.uut.tx_dac_i_o[13:0]
+@8421
 radar_tb.uut.tx_dac_q_o[13:0]
 @200
 -
 @28
+radar_tb.uut.io_tx_ena_o
 radar_tb.uut.controller.tx_ctrl_o
 radar_tb.uut.controller.rx_ctrl_o
-radar_tb.uut.auto_tr_o
 @200
 -
 @28
@@ -37,13 +38,5 @@ radar_tb.fifo_q[15:0]
 -
 @22
 radar_tb.uut.pulse_num[15:0]
-radar_tb.uut.receiver.count[15:0]
-@28
-radar_tb.uut.receiver.fifo_empty
-@22
-radar_tb.uut.receiver.fifo_inp[31:0]
-radar_tb.uut.receiver.fifo_out[31:0]
-@28
-radar_tb.uut.receiver.state[2:0]
 @200
 -
diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.v b/gr-radar-mono/src/fpga/tb/radar_tb.v
index cb26abf5..3583b70e 100644
--- a/gr-radar-mono/src/fpga/tb/radar_tb.v
+++ b/gr-radar-mono/src/fpga/tb/radar_tb.v
@@ -178,6 +178,15 @@ module radar_tb;
       end
    endtask // set_fincr
 
+   // Chirp frequency increment
+   task set_atrdel;
+      input [31:0] atrdel;
+
+      begin
+	 write_cfg_register(`FR_RADAR_ATRDEL, atrdel);
+      end
+   endtask // set_fincr
+
    // Test transmitter functionality
    task test_tx;
       begin
@@ -191,7 +200,7 @@ module radar_tb;
 	 #20 set_ampl(16'd9946);
 	 #20 set_fstart(32'h80000000); // -16 to 16 MHz
 	 #20 set_fincr (32'h0199999A);
-	 
+	 #20 set_atrdel(32'h00400046); // 64 TX clks, 70 RX clks	 
 	 #20 set_reset(0);
 	 #200000;
       end
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
index d1db2e9c..9b13989c 100644
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
+++ b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
@@ -380,7 +380,7 @@ set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
 set_global_assignment -name VERILOG_FILE dacpll.v
 set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
 set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
-set_global_assignment -name VERILOG_FILE ../lib/fifo32_4k.v
+set_global_assignment -name VERILOG_FILE ../lib/fifo32_2k.v
 set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
 set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
 set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
index 13c36c78..229da496 100644
Binary files a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf and b/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf differ
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v b/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
index 0382734b..f1723fa6 100644
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
+++ b/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
@@ -86,7 +86,7 @@ module usrp_radar_mono
 
    // TX
    wire        tx_sample_strobe;
-   wire        auto_tr;
+   wire        io_tx_ena;
    
    wire        serial_strobe;
    wire [6:0]  serial_addr;
@@ -145,8 +145,24 @@ module usrp_radar_mono
    radar radar_mono ( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
 	     .tx_side_o(tx_side),.tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
 	     .rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
-	     .rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q),.auto_tr_o(auto_tr)
+	     .rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q),.io_tx_ena_o(io_tx_ena)
 	   );
+
+   // Route TX enable out to RFX transmit mixer enable
+   assign io_tx_a[5] = tx_side ? 1'bz : io_tx_ena;
+   assign io_tx_b[5] = tx_side ? io_tx_ena : 1'bz;
+
+   // Route opposite of TX enable out to RFX receive mixer
+   assign io_rx_a[5] = tx_side ? 1'bz : ~io_tx_ena;
+   assign io_rx_b[5] = tx_side ? ~io_tx_ena : 1'bz;
+   
+   // Route TX enable out to RX/TX switch
+   assign io_tx_a[6] = tx_side ? 1'bz : ~io_tx_ena;
+   assign io_tx_b[6] = tx_side ? ~io_tx_ena : 1'bz;
+
+   // Enable common RX/TX antenna
+   assign io_rx_a[6] = tx_side ? 1'bz : 1'b0;
+   assign io_rx_b[6] = tx_side ? 1'b0 : 1'bz;
    
    ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    // Control Functions
@@ -175,13 +191,18 @@ module usrp_radar_mono
        .interp_rate(),.decim_rate(),
        .tx_sample_strobe(),.strobe_interp(),
        .rx_sample_strobe(),.strobe_decim(),
-       .tx_empty(auto_tr),
+       .tx_empty(),
        .debug_0(),.debug_1(),
        .debug_2(),.debug_3(),
        .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
+
+   wire [1:0] dummy_io = 2'bz;
    
    io_pins io_pins
-     (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
+     (.io_0({io_tx_a[15:7],dummy_io,io_tx_a[4:0]}), // Don't connect pins used above
+      .io_1({io_rx_a[15:7],dummy_io,io_rx_a[4:0]}),
+      .io_2({io_tx_b[15:7],dummy_io,io_tx_b[4:0]}),
+      .io_3({io_rx_b[15:7],dummy_io,io_rx_b[4:0]}),
       .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
       .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
diff --git a/gr-radar-mono/src/python/radar_mono.py b/gr-radar-mono/src/python/radar_mono.py
index 701157cc..6e2c993e 100644
--- a/gr-radar-mono/src/python/radar_mono.py
+++ b/gr-radar-mono/src/python/radar_mono.py
@@ -45,8 +45,9 @@ FR_RADAR_TIDLE  = usrp.FR_USER_4	# 32-bit inter-pulse idle time
 FR_RADAR_AMPL   = usrp.FR_USER_5  	# 16-bit pulse amplitude (2s complement) into CORDIC
 FR_RADAR_FSTART = usrp.FR_USER_6  	# 32-bit FTW for chirp start frequency
 FR_RADAR_FINCR  = usrp.FR_USER_7  	# 32-bit FTW increment per transmit clock
+FR_RADAR_ATRDEL = usrp.FR_USER_8        # 16-bit TX delay in clocks, 16-bit RX delay in clocks
 
-# These are for phase II development
+# These are for phase II development (need to renumber)
 #FR_RADAR_FREQ1N = usrp.FR_USER_8  # 24-bit N register for chirp #1
 #FR_RADAR_FREQ1R = usrp.FR_USER_9  # 24-bit R register for chirp #1
 #FR_RADAR_FREQ1C = usrp.FR_USER_10 # 24-bit C register for chirp #1
@@ -153,6 +154,7 @@ class radar_rx(gr.top_block):
     def __init__(self, options, callback):
 	gr.top_block.__init__(self, "radar_rx")
 
+	self._u = None
         self._subdev_spec = options.rx_subdev_spec
         self._gain = options.gain
 	self._verbose = options.verbose
@@ -160,6 +162,7 @@ class radar_rx(gr.top_block):
         self._callback = callback
 	self._length_set = False
 	self._connected = False
+	self._frequency = 0.0
         self._msgq = gr.msg_queue()
         self._watcher = _queue_watcher_thread(self._msgq, self._callback)
 	        
@@ -173,9 +176,11 @@ class radar_rx(gr.top_block):
     def tune(self, frequency):
         if self._verbose:
             print "Setting receiver frequency to", n2s(frequency)
-        result = self._u.tune(0, self._subdev, frequency)
-        if result == False:
-            raise RuntimeError("Failed to set receiver frequency.")
+	self._frequency = frequency
+	if (self._u):
+            result = self._u.tune(0, self._subdev, frequency)
+	    if result == False:
+    	        raise RuntimeError("Failed to set receiver frequency.")
 
     def set_gain(self, gain):
         self._gain = gain
@@ -212,10 +217,8 @@ class radar_rx(gr.top_block):
             print "Using", self._subdev.side_and_name(), "for radar receiver."
             print "Setting receiver gain to", self._gain
         self.set_gain(self._gain)
-	self._subdev.set_auto_tr(True)
-	self._subdev.set_atr_tx_delay(26) # TX CORDIC pipeline delay
-	self._subdev.set_atr_rx_delay(26)
-		
+	self.tune(self._frequency)
+			
     def _setup_connections(self):
 	if not self._length_set:
 	    raise RuntimeError("Echo length not set.")
@@ -286,8 +289,13 @@ class radar(object):
 
     def set_freq(self, center_freq, chirp_width):
         self._trans.set_freq(center_freq, chirp_width)
-        # set receiver center frequency
-        
+	self._rcvr.tune(center_freq)
+	        
+    def set_atrdel(self, tx_delay, rx_delay):
+        if self._verbose:
+	    print "Setting TX delay of", tx_delay, "clocks, RX delay of", rx_delay
+        self._trans._u._write_fpga_reg(FR_RADAR_ATRDEL, tx_delay << 16 | rx_delay)
+
     def start(self):
 	self.set_reset(False)
 	self._trans.start()
diff --git a/gr-radar-mono/src/python/usrp_radar_mono.py b/gr-radar-mono/src/python/usrp_radar_mono.py
index 077b798c..a8ed9b8b 100755
--- a/gr-radar-mono/src/python/usrp_radar_mono.py
+++ b/gr-radar-mono/src/python/usrp_radar_mono.py
@@ -32,8 +32,8 @@ logfile = None
 
 def process_echo(echo):
     global logfile
-    #sys.stdout.write('.')
-    logfile.write(echo)
+    if logfile is not None:
+        logfile.write(echo)
         
 def main():
     global logfile
@@ -71,14 +71,10 @@ def main():
         parser.print_help()
         sys.exit(1)
 
-    if options.filename == None:
-        print "Must supply filename for logging received data."
-        sys.exit(1)
-    else:
+    if options.filename is not None:
         if options.verbose:
             print "Logging echo records to file: ", options.filename
-
-    logfile = open(options.filename, 'wb')
+	logfile = open(options.filename, 'wb')
         
     r = radar(options, process_echo)
 
@@ -88,11 +84,14 @@ def main():
     r.set_prf(options.prf)
     r.set_amplitude(options.amplitude)
     r.set_freq(options.frequency, options.chirp_width)
-
+    r.set_atrdel(64, 70) # TODO: parameterize
+    
     r.start()
     raw_input("Press ENTER to stop.")
     r.stop()
-    logfile.close()
+
+    if logfile is not None:
+        logfile.close()
             
 if __name__ == "__main__":
     main()