From: Thomas Koeller <thomas.koeller@baslerweb.com>
Date: Tue, 10 Aug 2010 12:56:42 +0000 (+0200)
Subject: DM36x: Use enable bit for PLL pre-divider
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=98d2579c61aea1cfc4c1e4bd391b9acf1b1ff5db;hp=a8c8c238f2dd1abe102f83bfa392ac40f313dd73;p=fw%2Fopenocd

DM36x: Use enable bit for PLL pre-divider

The PLL pre- and postdividers seem to have enable bits, although
these are not mentioned in the chip documentation.

Signed-off-by: Thomas Koeller <thomas.koeller@baslerweb.com>
---

diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index 6c6769fa9..b736c6ef3 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -179,7 +179,7 @@ proc pll_v03_setup {pll_addr mult config} {
 	mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff]
 	if { [dict exists $config prediv] } {
 		set div [dict get $config prediv]
-		set div [expr ($div - 1)]
+		set div [expr 0x8000 | ($div - 1)]
 		mww [expr $pll_addr + 0x0114] $div
 	}
 	if { [dict exists $config postdiv] } {