From: johanknol Date: Sun, 16 Dec 2001 14:40:49 +0000 (+0000) Subject: missing files for "added seperate segments for initialized data" X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=9790d1ca81de1512cd77ec2840bb9ac513e0d991;p=fw%2Fsdcc missing files for "added seperate segments for initialized data" git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1677 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- diff --git a/src/SDCCast.c b/src/SDCCast.c index f0e2e00d..b3cd43fb 100644 --- a/src/SDCCast.c +++ b/src/SDCCast.c @@ -1057,42 +1057,7 @@ createIval (ast * sym, sym_link * type, initList * ilist, ast * wid) /*-----------------------------------------------------------------*/ /* initAggregates - initialises aggregate variables with initv */ /*-----------------------------------------------------------------*/ - -/* this has to go */ void printIval (symbol *, sym_link *, initList *, FILE *); - ast * initAggregates (symbol * sym, initList * ival, ast * wid) { - ast *ast; - symbol *newSym; - - if (getenv("TRY_THE_NEW_INITIALIZER")) { - - if (!TARGET_IS_MCS51 || !(options.model==MODEL_LARGE)) { - fprintf (stderr, "Can't \"TRY_THE_NEW_INITIALIZER\" unless " - "with -mmcs51 and --model-large\n"); - exit(404); - } - - if (SPEC_OCLS(sym->etype)==xdata && - getSize(sym->type) > 16) { // else it isn't worth it: do it the old way - - // copy this symbol - newSym=copySymbol (sym); - SPEC_OCLS(newSym->etype)=code; - sprintf (newSym->name, "%s_init__", sym->name); - sprintf (newSym->rname,"%s_init__", sym->rname); - addSym (SymbolTab, newSym, newSym->name, 0, 0, 1); - - // emit it in the static segment - addSet(&statsg->syms, newSym); - - // now memcpy() the entire array from cseg - ast=newNode (ARRAYINIT, // ASSIGN_AGGREGATE - newAst_VALUE (symbolVal (sym)), - newAst_VALUE (symbolVal (newSym))); - return decorateType(resolveSymbols(ast)); - } - } - return createIval (newAst_VALUE (symbolVal (sym)), sym->type, ival, wid); } diff --git a/src/SDCCglue.c b/src/SDCCglue.c index 4895a3e0..fd6d3967 100644 --- a/src/SDCCglue.c +++ b/src/SDCCglue.c @@ -170,11 +170,12 @@ emitRegularMap (memmap * map, bool addPublics, bool arFlag) else tfprintf (map->oFile, "\t!area\n", map->sname); } - - /* print the area name */ + for (sym = setFirstItem (map->syms); sym; sym = setNextItem (map->syms)) { + symbol *newSym=NULL; + /* if extern then add it into the extern list */ if (IS_EXTERN (sym->etype)) @@ -228,35 +229,34 @@ emitRegularMap (memmap * map, bool addPublics, bool arFlag) fprintf (map->oFile, "%s$%d$%d", sym->name, sym->level, sym->block); } - /* if is has an absolute address then generate - an equate for this no need to allocate space */ - if (SPEC_ABSA (sym->etype)) - { - if (options.debug) { - fprintf (map->oFile, " == 0x%04x\n", SPEC_ADDR (sym->etype)); - } - fprintf (map->oFile, "%s\t=\t0x%04x\n", - sym->rname, - SPEC_ADDR (sym->etype)); - } - else - { - /* allocate space */ - if (options.debug) { - fprintf (map->oFile, "==.\n"); - } - if (IS_STATIC (sym->etype)) - tfprintf (map->oFile, "!slabeldef\n", sym->rname); - else - tfprintf (map->oFile, "!labeldef\n", sym->rname); - tfprintf (map->oFile, "\t!ds\n", - (unsigned int) getSize (sym->type) & 0xffff); - } - /* if it has an initial value then do it only if it is a global variable */ - if (sym->ival && sym->level == 0) - { + if (sym->ival && sym->level == 0) { + // can we copy xidata from xinit? + if (port->genXINIT && + SPEC_OCLS(sym->etype)==xdata && + !SPEC_ABSA(sym->etype)) { + + // create a new "XINIT (CODE)" symbol + newSym=copySymbol (sym); + SPEC_OCLS(newSym->etype)=xinit; + sprintf (newSym->name, "_xinit_%s", sym->name); + sprintf (newSym->rname,"_xinit_%s", sym->rname); + SPEC_CONST(newSym->etype)=1; + //SPEC_STAT(newSym->etype)=1; + addSym (SymbolTab, newSym, newSym->name, 0, 0, 1); + + // add it to the "XINIT (CODE)" segment + addSet(&xinit->syms, newSym); + + // move sym from "XSEG (XDATA)" to "XISEG (XDATA)" segment + //deleteSetItem(&xdata->syms, sym); + addSet(&xidata->syms, sym); + SPEC_OCLS(sym->etype)=xidata; + + //fprintf (stderr, "moved %s from xdata to xidata\n", sym->rname); + + } else { if (IS_AGGREGATE (sym->type)) { ival = initAggregates (sym, sym->ival, NULL); } else { @@ -265,28 +265,58 @@ emitRegularMap (memmap * map, bool addPublics, bool arFlag) sym->name, sym->lineDef); } ival = newNode ('=', newAst_VALUE (symbolVal (sym)), - decorateType (resolveSymbols (list2expr (sym->ival)))); + decorateType (resolveSymbols (list2expr (sym->ival)))); } codeOutFile = statsg->oFile; allocInfo = 0; - + // set ival's lineno to where the symbol was defined if (ival) ival->lineno=sym->lineDef; eBBlockFromiCode (iCodeFromAst (ival)); allocInfo = 1; + } + + /* if the ival is a symbol assigned to an aggregate, + (bug #458099 -> #462479) + we don't need it anymore, so delete it from its segment */ + if (sym->ival->type == INIT_NODE && + IS_AST_SYM_VALUE(sym->ival->init.node) && + IS_AGGREGATE (sym->type) ) { + symIval=AST_SYMBOL(sym->ival->init.node); + segment = SPEC_OCLS (symIval->etype); + deleteSetItem (&segment->syms, symIval); + } + + sym->ival = NULL; + } - /* if the ival is a symbol assigned to an aggregate, - (bug #458099 -> #462479) - we don't need it anymore, so delete it from its segment */ - if (sym->ival->type == INIT_NODE && - IS_AST_SYM_VALUE(sym->ival->init.node) && - IS_AGGREGATE (sym->type) ) { - symIval=AST_SYMBOL(sym->ival->init.node); - segment = SPEC_OCLS (symIval->etype); - deleteSetItem (&segment->syms, symIval); + /* if is has an absolute address then generate + an equate for this no need to allocate space */ + if (SPEC_ABSA (sym->etype)) + { + if (options.debug) { + fprintf (map->oFile, " == 0x%04x\n", SPEC_ADDR (sym->etype)); + } + fprintf (map->oFile, "%s\t=\t0x%04x\n", + sym->rname, + SPEC_ADDR (sym->etype)); + } + else + { + if (newSym) { + // this has been moved to another segment + } else { + /* allocate space */ + if (options.debug) { + fprintf (map->oFile, "==.\n"); + } + if (IS_STATIC (sym->etype)) + tfprintf (map->oFile, "!slabeldef\n", sym->rname); + else + tfprintf (map->oFile, "!labeldef\n", sym->rname); + tfprintf (map->oFile, "\t!ds\n", + (unsigned int) getSize (sym->type) & 0xffff); } - - sym->ival = NULL; } } } @@ -849,9 +879,19 @@ printIvalCharPtr (symbol * sym, sym_link * type, value * val, FILE * oFile) aopLiteral (val, 0), aopLiteral (val, 1)); break; case 3: - /* PENDING: 0x02 or 0x%02x, CDATA? */ - fprintf (oFile, "\t.byte %s,%s,#0x02\n", - aopLiteral (val, 0), aopLiteral (val, 1)); + werror (E_LITERAL_GENERIC); + fprintf (oFile, "\t.byte %s,%s,%s\n", + aopLiteral (val, 0), + aopLiteral (val, 1), + aopLiteral (val, 2)); + break; + case 4: + werror (E_LITERAL_GENERIC); + fprintf (oFile, "\t.byte %s,%s,%s,%s\n", + aopLiteral (val, 0), + aopLiteral (val, 1), + aopLiteral (val, 2), + aopLiteral (val, 3)); break; default: assert (0); @@ -988,9 +1028,7 @@ emitStaticSeg (memmap * map, FILE * out) { symbol *sym; - /* fprintf(map->oFile,"\t.area\t%s\n",map->sname); */ - if (!out) - out = code->oFile; + fprintf(out, "\t.area\t%s\n", map->sname); /* for all variables in this segment do */ for (sym = setFirstItem (map->syms); sym; @@ -1077,12 +1115,18 @@ emitMaps () emitRegularMap (idata, TRUE, TRUE); emitRegularMap (bit, TRUE, FALSE); emitRegularMap (xdata, TRUE, TRUE); + if (port->genXINIT) { + emitRegularMap (xidata, TRUE, TRUE); + } emitRegularMap (sfr, FALSE, FALSE); emitRegularMap (sfrbit, FALSE, FALSE); emitRegularMap (home, TRUE, FALSE); emitRegularMap (code, TRUE, FALSE); emitStaticSeg (statsg, code->oFile); + if (port->genXINIT) { + emitStaticSeg (xinit, code->oFile); + } inInitMode--; } @@ -1131,7 +1175,6 @@ createInterruptVect (FILE * vFile) if (!port->genIVT || !(port->genIVT (vFile, interrupts, maxInterrupts))) { /* "generic" interrupt table header (if port doesn't specify one). - * Look suspiciously like 8051 code to me... */ @@ -1442,6 +1485,12 @@ glue () fprintf (asmFile, "%s", iComments2); copyFile (asmFile, xdata->oFile); + /* copy xternal initialized ram data */ + fprintf (asmFile, "%s", iComments2); + fprintf (asmFile, "; external initialized ram data\n"); + fprintf (asmFile, "%s", iComments2); + copyFile (asmFile, xidata->oFile); + /* copy the interrupt vector table */ if (mainf && IFFUNC_HASBODY(mainf->type)) { @@ -1498,6 +1547,11 @@ glue () fprintf (asmFile, "\tljmp\t__sdcc_program_startup\n"); fprintf (asmFile, "__sdcc_init_data:\n"); + // if the port can copy the XINIT segment to XISEG + if (port->genXINIT) { + port->genXINIT(asmFile); + } + } copyFile (asmFile, statsg->oFile); diff --git a/src/SDCCmem.c b/src/SDCCmem.c index 4eeca0f5..29fcc840 100644 --- a/src/SDCCmem.c +++ b/src/SDCCmem.c @@ -5,14 +5,16 @@ #include "common.h" /* memory segments */ -memmap *xstack = NULL; /* xternal stack data */ -memmap *istack = NULL; /* internal stack */ -memmap *code = NULL; /* code segment */ -memmap *data = NULL; /* internal data upto 128 */ -memmap *xdata = NULL; /* external data */ -memmap *idata = NULL; /* internal data upto 256 */ -memmap *bit = NULL; /* bit addressable space */ -memmap *statsg = NULL; /* the constant data segment */ +memmap *xstack = NULL; /* xternal stack data */ +memmap *istack = NULL; /* internal stack */ +memmap *code = NULL; /* code segment */ +memmap *data = NULL; /* internal data upto 128 */ +memmap *xdata = NULL; /* external data */ +memmap *xidata = NULL; /* the initialized xdata */ +memmap *xinit = NULL; /* the initializers for xidata */ +memmap *idata = NULL; /* internal data upto 256 */ +memmap *bit = NULL; /* bit addressable space */ +memmap *statsg = NULL; /* the constant data segment */ memmap *sfr = NULL; /* register space */ memmap *reg = NULL; /* register space */ memmap *sfrbit = NULL; /* sfr bit space */ @@ -175,6 +177,8 @@ initMem () POINTER-TYPE - FPOINTER */ xdata = allocMap (0, 1, 0, 0, 0, 0, options.xdata_loc, XDATA_NAME, 'F', FPOINTER); + xidata = allocMap (0, 1, 0, 0, 0, 0, 0, XIDATA_NAME, 'F', FPOINTER); + xinit = allocMap (0, 1, 0, 0, 0, 1, 0, XINIT_NAME, 'C', CPOINTER); /* Inderectly addressed internal data segment SFRSPACE - NO diff --git a/src/SDCCmem.h b/src/SDCCmem.h index ebdc158e..37881855 100644 --- a/src/SDCCmem.h +++ b/src/SDCCmem.h @@ -37,6 +37,8 @@ extern FILE *junkFile; #define DATA_NAME port->mem.data_name #define IDATA_NAME port->mem.idata_name #define XDATA_NAME port->mem.xdata_name +#define XIDATA_NAME port->mem.xidata_name +#define XINIT_NAME port->mem.xinit_name #define BIT_NAME port->mem.bit_name #define REG_NAME port->mem.reg_name #define STATIC_NAME port->mem.static_name @@ -48,6 +50,8 @@ extern memmap *istack; /* internal stack */ extern memmap *code; /* code segment */ extern memmap *data; /* internal data upto 128 */ extern memmap *xdata; /* external data */ +extern memmap *xidata; /* the initialized xdata */ +extern memmap *xinit; /* the initializers for xidata */ extern memmap *idata; /* internal data upto 256 */ extern memmap *bit; /* bit addressable space */ extern memmap *statsg; /* static code segment */ diff --git a/src/ds390/main.c b/src/ds390/main.c index 03e68184..86cc4250 100644 --- a/src/ds390/main.c +++ b/src/ds390/main.c @@ -209,6 +209,31 @@ _ds390_genIVT (FILE * of, symbol ** interrupts, int maxInterrupts) return TRUE; } +/* Generate code to copy XINIT to XISEG */ +static void _ds390_genXINIT (FILE * of) { + fprintf (of, "; _ds390_genXINIT() start\n"); + fprintf (of, " mov a,#s_XINIT\n"); + fprintf (of, " add a,#l_XINIT\n"); + fprintf (of, " mov r1,a\n"); + fprintf (of, " mov a,#s_XINIT>>8\n"); + fprintf (of, " addc a,#l_XINIT>>8\n"); + fprintf (of, " mov r2,a\n"); + fprintf (of, " mov dptr,#s_XINIT\n"); + fprintf (of, " mov dps,#0x21\n"); + fprintf (of, " mov dptr,#s_XISEG\n"); + fprintf (of, "00001$: clr a\n"); + fprintf (of, " movc a,@a+dptr\n"); + fprintf (of, " movx @dptr,a\n"); + fprintf (of, " inc dptr\n"); + fprintf (of, " inc dptr\n"); + fprintf (of, "00002$: mov a,dpl\n"); + fprintf (of, " cjne a,ar1,00001$\n"); + fprintf (of, " mov a,dph\n"); + fprintf (of, " cjne a,ar2,00001$\n"); + fprintf (of, " mov dps,#0\n"); + fprintf (of, "; _ds390_genXINIT() end\n"); +} + /* Do CSE estimation */ static bool cseCostEstimation (iCode *ic, iCode *pdic) { @@ -295,8 +320,8 @@ PORT ds390_port = "OSEG (OVR,DATA)", "GSFINAL (CODE)", "HOME (CODE)", - NULL, // xidata - NULL, // xinit + "XISEG (XDATA)", // initialized xdata + "XINIT (CODE)", // a code copy of xiseg NULL, NULL, 1 @@ -318,7 +343,7 @@ PORT ds390_port = _ds390_keywords, _ds390_genAssemblerPreamble, _ds390_genIVT, - NULL, // _ds390_genXINIT + _ds390_genXINIT, _ds390_reset_regparm, _ds390_regparm, NULL, diff --git a/src/port.h b/src/port.h index 2e1bab4b..88f764ad 100644 --- a/src/port.h +++ b/src/port.h @@ -134,8 +134,10 @@ typedef struct const char *overlay_name; const char *post_static_name; const char *home_name; - struct memmap *default_local_map; /* default location for auto vars */ - struct memmap *default_globl_map; /* default location for globl vars */ + const char *xidata_name; // initialized xdata + const char *xinit_name; // a code copy of xidata + struct memmap *default_local_map; // default location for auto vars + struct memmap *default_globl_map; // default location for globl vars int code_ro; /* code space read-only 1=yes */ } mem; @@ -204,6 +206,7 @@ typedef struct */ int (*genIVT) (FILE * of, symbol ** intTable, int intCount); + void (*genXINIT) (FILE * of); /* parameter passing in register related functions */ void (*reset_regparms) (); /* reset the register count */