From: maartenbrock Date: Thu, 27 Jan 2005 11:48:57 +0000 (+0000) Subject: * device/include/c8051fxxx.h: removed these 6 new files X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=954f46dd363ea04737d24f05b45320a100f0cd90;p=fw%2Fsdcc * device/include/c8051fxxx.h: removed these 6 new files * device/include/mcs51/c8051fxxx.h: added these 11 new files git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@3658 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- diff --git a/ChangeLog b/ChangeLog index 3d9cb32c..56c30a19 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2004-01-27 Maarten Brock + + * device/include/c8051fxxx.h: removed these 6 new files + * device/include/mcs51/c8051fxxx.h: added these 11 new files + 2005-01-26 Raphael Neider * src/pic16/gen.c (genAssign): fixed assignment from longs diff --git a/device/include/c8051f000.h b/device/include/c8051f000.h deleted file mode 100644 index bc9de6a9..00000000 --- a/device/include/c8051f000.h +++ /dev/null @@ -1,283 +0,0 @@ -/*------------------------------------------------------------------------- - Register Declarations for the Cygnal C8051F000-C8051F017 Processor Range - - Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --------------------------------------------------------------------------*/ - -#ifndef C8051F000_H -#define C8051F000_H - - -/* BYTE Registers */ -sfr at 0x80 P0 ; /* PORT 0 */ -sfr at 0x81 SP ; /* STACK POINTER */ -sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -sfr at 0x87 PCON ; /* POWER CONTROL */ -sfr at 0x88 TCON ; /* TIMER CONTROL */ -sfr at 0x89 TMOD ; /* TIMER MODE */ -sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -sfr at 0x8E CKCON ; /* CLOCK CONTROL */ -sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ -sfr at 0x90 P1 ; /* PORT 1 */ -sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ -sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */ -sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */ -sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ -sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ -sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ -sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ -sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */ -sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */ -sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */ -sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */ -sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */ -sfr at 0xA0 P2 ; /* PORT 2 */ -sfr at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */ -sfr at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */ -sfr at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */ -sfr at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */ -sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ -sfr at 0xAD PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */ -sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ -sfr at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */ -sfr at 0xB0 P3 ; /* PORT 3 */ -sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ -sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */ -sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ -sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ -sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ -sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ -sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ -sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ -sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ -sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ -sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ -sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ -sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ -sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ -sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ -sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ -sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ -sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ -sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ -sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ -sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ -sfr at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ -sfr at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ -sfr at 0xD7 DAC1CN ; /* DAC 1 CONTROL */ -sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ -sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ -sfr at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */ -sfr at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */ -sfr at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */ -sfr at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */ -sfr at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */ -sfr at 0xE0 ACC ; /* ACCUMULATOR */ -sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */ -sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */ -sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */ -sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ -sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ -sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ -sfr at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */ -sfr at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */ -sfr at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */ -sfr at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */ -sfr at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */ -sfr at 0xEF RSTSRC ; /* RESET SOURCE */ -sfr at 0xF0 B ; /* B REGISTER */ -sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ -sfr at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */ -sfr at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ -sfr at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */ -sfr at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */ -sfr at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */ -sfr at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */ -sfr at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */ -sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ - - -/* BIT Registers */ - -/* P0 0x80 */ -sbit at 0x87 P0_7 ; -sbit at 0x86 P0_6 ; -sbit at 0x85 P0_5 ; -sbit at 0x84 P0_4 ; -sbit at 0x83 P0_3 ; -sbit at 0x82 P0_2 ; -sbit at 0x81 P0_1 ; -sbit at 0x80 P0_0 ; - -/* TCON 0x88 */ -sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ -sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ -sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ -sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ -sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ -sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ -sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ -sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ - -/* P1 0x90 */ -sbit at 0x97 P1_7 ; -sbit at 0x96 P1_6 ; -sbit at 0x95 P1_5 ; -sbit at 0x94 P1_4 ; -sbit at 0x93 P1_3 ; -sbit at 0x92 P1_2 ; -sbit at 0x91 P1_1 ; -sbit at 0x90 P1_0 ; - -/* SCON 0x98 */ -sbit at 0x9F SM0 ; /* SERIAL MODE CONTROL BIT 0 */ -sbit at 0x9E SM1 ; /* SERIAL MODE CONTROL BIT 1 */ -sbit at 0x9D SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9C REN ; /* RECEIVE ENABLE */ -sbit at 0x9B TB8 ; /* TRANSMIT BIT 8 */ -sbit at 0x9A RB8 ; /* RECEIVE BIT 8 */ -sbit at 0x99 TI ; /* TRANSMIT INTERRUPT FLAG */ -sbit at 0x98 RI ; /* RECEIVE INTERRUPT FLAG */ - -/* P2 0xA0 */ -sbit at 0xA7 P2_7 ; -sbit at 0xA6 P2_6 ; -sbit at 0xA5 P2_5 ; -sbit at 0xA4 P2_4 ; -sbit at 0xA3 P2_3 ; -sbit at 0xA2 P2_2 ; -sbit at 0xA1 P2_1 ; -sbit at 0xA0 P2_0 ; - -/* IE 0xA8 */ -sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ -sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ -sbit at 0xAC ES ; /* SERIAL PORT INTERRUPT ENABLE */ -sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ -sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ -sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ -sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ - -/* P3 0xB0 */ -sbit at 0xB7 P3_7 ; -sbit at 0xB6 P3_6 ; -sbit at 0xB5 P3_5 ; -sbit at 0xB4 P3_4 ; -sbit at 0xB3 P3_3 ; -sbit at 0xB2 P3_2 ; -sbit at 0xB1 P3_1 ; -sbit at 0xB0 P3_0 ; - -/* IP 0xB8 */ -sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ -sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ -sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ -sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ -sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ -sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ - -/* SMB0CN 0xC0 */ -sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ -sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ -sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ -sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ -sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ -sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ -sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ -sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ - -/* T2CON 0xC8 */ -sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ -sbit at 0xCE EXF2 ; /* EXTERNAL FLAG */ -sbit at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */ -sbit at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */ -sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ -sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ -sbit at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */ -sbit at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */ - -/* PSW 0xD0 */ -sbit at 0xD7 CY ; /* CARRY FLAG */ -sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ -sbit at 0xD5 F0 ; /* USER FLAG 0 */ -sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ -sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ -sbit at 0xD2 OV ; /* OVERFLOW FLAG */ -sbit at 0xD1 F1 ; /* USER FLAG 1 */ -sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ - -/* PCA0CN 0xD8H */ -sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ -sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ -sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ -sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ -sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ -sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ -sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ - -/* ADC0CN 0xE8H */ -sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ -sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ -sbit at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */ -sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ -sbit at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */ -sbit at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */ -sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */ -sbit at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ - -/* SPI0CN 0xF8H */ -sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ -sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ -sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ -sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ -sbit at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */ -sbit at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */ -sbit at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */ -sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ - - -/* Predefined SFR Bit Masks */ - -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ -#define TF3 0x80 /* TMR3CN */ -#define CPFIF 0x10 /* CPTnCN */ -#define CPRIF 0x20 /* CPTnCN */ -#define CPOUT 0x40 /* CPTnCN */ -#define ECCF 0x01 /* PCA0CPMn */ -#define PWM 0x02 /* PCA0CPMn */ -#define TOG 0x04 /* PCA0CPMn */ -#define MAT 0x08 /* PCA0CPMn */ -#define CAPN 0x10 /* PCA0CPMn */ -#define CAPP 0x20 /* PCA0CPMn */ -#define ECOM 0x40 /* PCA0CPMn */ - -#endif diff --git a/device/include/c8051f020.h b/device/include/c8051f020.h deleted file mode 100644 index d1d4ad8f..00000000 --- a/device/include/c8051f020.h +++ /dev/null @@ -1,345 +0,0 @@ -/*------------------------------------------------------------------------- - Register Declarations for the Cygnal C8051F02x Processor Range - - Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --------------------------------------------------------------------------*/ - -#ifndef C8051F020_H -#define C8051F020_H - - -/* BYTE Registers */ -sfr at 0x80 P0 ; /* PORT 0 */ -sfr at 0x81 SP ; /* STACK POINTER */ -sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -sfr at 0x84 P4 ; /* PORT 4 */ -sfr at 0x85 P5 ; /* PORT 5 */ -sfr at 0x86 P6 ; /* PORT 6 */ -sfr at 0x87 PCON ; /* POWER CONTROL */ -sfr at 0x88 TCON ; /* TIMER CONTROL */ -sfr at 0x89 TMOD ; /* TIMER MODE */ -sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -sfr at 0x8E CKCON ; /* CLOCK CONTROL */ -sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ -sfr at 0x90 P1 ; /* PORT 1 */ -sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ -sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */ -sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */ -sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ -sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ -sfr at 0x96 P7 ; /* PORT 7 */ -sfr at 0x98 SCON ; /* UART0 CONTROL */ -sfr at 0x98 SCON0 ; /* UART0 CONTROL */ -sfr at 0x99 SBUF ; /* UART0 BUFFER */ -sfr at 0x99 SBUF0 ; /* UART0 BUFFER */ -sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */ -sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */ -sfr at 0x9C ADC1 ; /* ADC 1 DATA */ -sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */ -sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */ -sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */ -sfr at 0xA0 P2 ; /* PORT 2 */ -sfr at 0xA1 EMI0TC ; /* External Memory Timing Control */ -sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ -sfr at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */ -sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ -sfr at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */ -sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ -sfr at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */ -sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ -sfr at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */ -sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ -sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ -sfr at 0xA9 SADDR0 ; /* UART0 Slave Address */ -sfr at 0xAA ADC1CN ; /* ADC 1 CONTROL */ -sfr at 0xAB ADC1CF ; /* ADC 1 CONFIGURATION */ -sfr at 0xAC AMX1SL ; /* ADC 1 MUX CHANNEL SELECTION */ -sfr at 0xAD P3IF ; /* PORT 3 EXTERNAL INTERRUPT FLAGS */ -sfr at 0xAE SADEN1 ; /* UART1 Slave Address Enable */ -sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ -sfr at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */ -sfr at 0xB0 P3 ; /* PORT 3 */ -sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -sfr at 0xB5 P74OUT ; /* PORT 4 THROUGH 7 OUTPUT MODE CONFIGURATION */ -sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ -sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */ -sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ -sfr at 0xB9 SADEN0 ; /* UART0 Slave Address Enable */ -sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ -sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ -sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ -sfr at 0xBD P1MDIN ; /* PORT 1 Input Mode */ -sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ -sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ -sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ -sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ -sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ -sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ -sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ -sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ -sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ -sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ -sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ -sfr at 0xC9 T4CON ; /* TIMER 4 CONTROL */ -sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ -sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ -sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ -sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ -sfr at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ -sfr at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ -sfr at 0xD7 DAC1CN ; /* DAC 1 CONTROL */ -sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ -sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ -sfr at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */ -sfr at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */ -sfr at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */ -sfr at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */ -sfr at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */ -sfr at 0xE0 ACC ; /* ACCUMULATOR */ -sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */ -sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */ -sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */ -sfr at 0xE4 RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xE5 RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ -sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ -sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ -sfr at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */ -sfr at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */ -sfr at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */ -sfr at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */ -sfr at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */ -sfr at 0xEF RSTSRC ; /* RESET SOURCE */ -sfr at 0xF0 B ; /* B REGISTER */ -sfr at 0xF1 SCON1 ; /* UART1 CONTROL */ -sfr at 0xF2 SBUF1 ; /* UART1 DATA */ -sfr at 0xF3 SADDR1 ; /* UART1 Slave Address */ -sfr at 0xF4 TL4 ; /* TIMER 4 DATA - LOW BYTE */ -sfr at 0xF5 TH4 ; /* TIMER 4 DATA - HIGH BYTE */ -sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ -sfr at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */ -sfr at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ -sfr at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */ -sfr at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */ -sfr at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */ -sfr at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */ -sfr at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */ -sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ - - -/* BIT Registers */ - -/* P0 0x80 */ -sbit at 0x80 P0_0 ; -sbit at 0x81 P0_1 ; -sbit at 0x82 P0_2 ; -sbit at 0x83 P0_3 ; -sbit at 0x84 P0_4 ; -sbit at 0x85 P0_5 ; -sbit at 0x86 P0_6 ; -sbit at 0x87 P0_7 ; - -/* TCON 0x88 */ -sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ -sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ -sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ -sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ -sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ -sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ -sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ -sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ - -/* P1 0x90 */ -sbit at 0x90 P1_0 ; -sbit at 0x91 P1_1 ; -sbit at 0x92 P1_2 ; -sbit at 0x93 P1_3 ; -sbit at 0x94 P1_4 ; -sbit at 0x95 P1_5 ; -sbit at 0x96 P1_6 ; -sbit at 0x97 P1_7 ; - -/* SCON 0x98 */ -sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ -sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ -sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ -sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ -sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ -sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ -sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9D SM20 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9E SM1 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */ -sbit at 0x9E SM10 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */ -sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ -sbit at 0x9F SM00 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ -sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ - -/* P2 0xA0 */ -sbit at 0xA0 P2_0 ; -sbit at 0xA1 P2_1 ; -sbit at 0xA2 P2_2 ; -sbit at 0xA3 P2_3 ; -sbit at 0xA4 P2_4 ; -sbit at 0xA5 P2_5 ; -sbit at 0xA6 P2_6 ; -sbit at 0xA7 P2_7 ; - -/* IE 0xA8 */ -sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ -sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ -sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ -sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ -sbit at 0xAC ES ; /* SERIAL PORT 0 INTERRUPT ENABLE */ -sbit at 0xAC ES0 ; /* SERIAL PORT 0 INTERRUPT ENABLE */ -sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ -sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ - -/* P3 0xB0 */ -sbit at 0xB0 P3_0 ; -sbit at 0xB1 P3_1 ; -sbit at 0xB2 P3_2 ; -sbit at 0xB3 P3_3 ; -sbit at 0xB4 P3_4 ; -sbit at 0xB5 P3_5 ; -sbit at 0xB6 P3_6 ; -sbit at 0xB7 P3_7 ; - -/* IP 0xB8 */ -sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ -sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ -sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ -sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ -sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ -sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ - -/* SMB0CN 0xC0 */ -sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ -sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ -sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ -sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ -sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ -sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ -sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ -sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ - -/* T2CON 0xC8 */ -sbit at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */ -sbit at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */ -sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ -sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ -sbit at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */ -sbit at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */ -sbit at 0xCE EXF2 ; /* EXTERNAL FLAG */ -sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ - -/* PSW 0xD0 */ -sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ -sbit at 0xD1 F1 ; /* USER FLAG 1 */ -sbit at 0xD2 OV ; /* OVERFLOW FLAG */ -sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ -sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ -sbit at 0xD5 F0 ; /* USER FLAG 0 */ -sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ -sbit at 0xD7 CY ; /* CARRY FLAG */ - -/* PCA0CN 0xD8H */ -sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ -sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ -sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ -sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ -sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ -sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ -sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ - -/* ADC0CN 0xE8H */ -sbit at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ -sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ -sbit at 0xE9 ADWINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */ -sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */ -sbit at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */ -sbit at 0xEA AD0CM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */ -sbit at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */ -sbit at 0xEB AD0CM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */ -sbit at 0xEC ADBUSY ; /* ADC 0 BUSY FLAG */ -sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ -sbit at 0xED ADCINT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */ -sbit at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */ -sbit at 0xEE ADCTM ; /* ADC 0 TRACK MODE */ -sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ -sbit at 0xEF ADCEN ; /* ADC 0 ENABLE */ -sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ - -/* SPI0CN 0xF8H */ -sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ -sbit at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */ -sbit at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */ -sbit at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */ -sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ -sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ -sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ -sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ - - -/* Predefined SFR Bit Masks */ - -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ -#define SMOD0 0x80 /* PCON */ -#define TF3 0x80 /* TMR3CN */ -#define CPFIF 0x10 /* CPTnCN */ -#define CPRIF 0x20 /* CPTnCN */ -#define CPOUT 0x40 /* CPTnCN */ -#define TR4 0x04 /* T4CON */ -#define TF4 0x80 /* T4CON */ -#define ECCF 0x01 /* PCA0CPMn */ -#define PWM 0x02 /* PCA0CPMn */ -#define TOG 0x04 /* PCA0CPMn */ -#define MAT 0x08 /* PCA0CPMn */ -#define CAPN 0x10 /* PCA0CPMn */ -#define CAPP 0x20 /* PCA0CPMn */ -#define ECOM 0x40 /* PCA0CPMn */ -#define PWM16 0x80 /* PCA0CPMn */ -#define PORSF 0x02 /* RSTSRC */ -#define SWRSF 0x10 /* RSTSRC */ -#define RI1 0x01 /* SCON1 */ -#define TI1 0x02 /* SCON1 */ -#define RB81 0x04 /* SCON1 */ -#define TB81 0x08 /* SCON1 */ -#define REN1 0x10 /* SCON1 */ -#define SM21 0x20 /* SCON1 */ -#define SM11 0x40 /* SCON1 */ -#define SM01 0x80 /* SCON1 */ - -#endif diff --git a/device/include/c8051f120.h b/device/include/c8051f120.h deleted file mode 100644 index ef9df9ad..00000000 --- a/device/include/c8051f120.h +++ /dev/null @@ -1,456 +0,0 @@ -/*------------------------------------------------------------------------- - Register Declarations for the Cygnal C8051F12x Processor Range - - Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --------------------------------------------------------------------------*/ - -#ifndef C8051F120_H -#define C8051F120_H - - -/* BYTE Registers */ - -/* All Pages */ -sfr at 0x80 P0 ; /* PORT 0 */ -sfr at 0x81 SP ; /* STACK POINTER */ -sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */ -sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */ -sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */ -sfr at 0x87 PCON ; /* POWER CONTROL */ -sfr at 0x90 P1 ; /* PORT 1 */ -sfr at 0xA0 P2 ; /* PORT 2 */ -sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ -sfr at 0xB0 P3 ; /* PORT 3 */ -sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */ -sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ -sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -sfr at 0xE0 ACC ; /* ACCUMULATOR */ -sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ -sfr at 0xF0 B ; /* B REGISTER */ -sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ -sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ - -/* Page 0x00 */ -sfr at 0x88 TCON ; /* TIMER CONTROL */ -sfr at 0x89 TMOD ; /* TIMER MODE */ -sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */ -sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */ -sfr at 0x91 SSTA0 ; /* UART 0 STATUS */ -sfr at 0x98 SCON0 ; /* UART 0 CONTROL */ -sfr at 0x98 SCON ; /* UART 0 CONTROL */ -sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */ -sfr at 0x99 SBUF ; /* UART 0 BUFFER */ -sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */ -sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */ -sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */ -sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */ -sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */ -sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */ -sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ -sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */ -sfr at 0xB7 FLSCL ; /* FLASH SCALE */ -sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */ -sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ -sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ -sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ -sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ -sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ -sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ -sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ -sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ -sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ -sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ -sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ -sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ -sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ -sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ -sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */ -sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ -sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ -sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ -sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ -sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ -sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ -sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */ -sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */ -sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */ -sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */ -sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */ -sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */ -sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ -sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xEF RSTSRC ; /* RESET SOURCE */ -sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */ -sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ -sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ -sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */ -sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */ -sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */ - -/* Page 0x01 */ -sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */ -sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */ -sfr at 0x98 SCON1 ; /* UART 1 CONTROL */ -sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */ -sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */ -sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */ -sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */ -sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */ -sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ -sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ -sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */ - -/* Page 0x02 */ -sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */ -sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */ -sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */ -sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */ -sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */ -sfr at 0xBE ADC2 ; /* ADC 2 DATA */ -sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */ -sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */ -sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */ -sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */ -sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */ -sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */ - -/* Page 0x02 */ -sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */ -sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */ -sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */ -sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */ -sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */ -sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */ -sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */ -sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */ -sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */ -sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */ -sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */ -sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */ -sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */ - -/* Page 0x0F */ -sfr at 0x88 FLSTAT ; /* FLASH STATUS */ -sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */ -sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ -sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */ -sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */ -sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */ -sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */ -sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */ -sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */ -sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */ -sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */ -sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */ -sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */ -sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */ -sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */ -sfr at 0xA3 CCH0LC ; /* CACHE LOCK */ -sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */ -sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */ -sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ -sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ -sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */ -sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */ -sfr at 0xC8 P4 ; /* PORT 4 */ -sfr at 0xD8 P5 ; /* PORT 5 */ -sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */ -sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */ -sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */ -sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */ -sfr at 0xE8 P6 ; /* PORT 6 */ -sfr at 0xF8 P7 ; /* PORT 7 */ - - -/* BIT Registers */ - -/* P0 0x80 */ -sbit at 0x80 P0_0 ; -sbit at 0x81 P0_1 ; -sbit at 0x82 P0_2 ; -sbit at 0x83 P0_3 ; -sbit at 0x84 P0_4 ; -sbit at 0x85 P0_5 ; -sbit at 0x86 P0_6 ; -sbit at 0x87 P0_7 ; - -/* TCON 0x88 */ -sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ -sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ -sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ -sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ -sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ -sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ -sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ -sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ - -/* CPT0CN 0x88 */ -sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */ -sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */ -sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */ -sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */ -sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */ -sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */ -sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */ -sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */ - -/* CPT1CN 0x88 */ -sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */ -sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */ -sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */ -sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */ -sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */ -sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */ -sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */ -sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */ - -/* FLSTAT 0x88 */ -sbit at 0x88 FLHBUSY ; /* FLASH BUSY */ - -/* SCON0 0x98 */ -sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */ -sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */ -sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */ -sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */ -sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */ -sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */ -sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */ -sbit at 0x9C REN ; /* UART 0 RX ENABLE */ -sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */ -sbit at 0x9E SM10 ; /* UART 0 MODE 1 */ -sbit at 0x9F SM00 ; /* UART 0 MODE 0 */ - -/* SCON1 0x98 */ -sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */ -sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */ -sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */ -sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */ -sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */ -sbit at 0x9D MCE1 ; /* UART 1 MCE */ -sbit at 0x9F S1MODE ; /* UART 1 MODE */ - -/* IE 0xA8 */ -sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ -sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ -sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ -sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ -sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */ -sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */ -sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ -sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ - -/* IP 0xB8 */ -sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ -sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ -sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ -sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ -sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ -sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ - -/* SMB0CN 0xC0 */ -sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ -sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ -sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ -sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ -sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ -sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ -sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ -sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ - -/* TMR2CN 0xC8 */ -sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */ -sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */ -sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ -sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ -sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */ -sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ - -/* TMR3CN 0xC8 */ -sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */ -sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */ -sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */ -sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */ -sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */ -sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */ - -/* TMR4CN 0xC8 */ -sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */ -sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */ -sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */ -sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */ -sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */ -sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */ - -/* P4 0xC8 */ -sbit at 0xC8 P4_0 ; -sbit at 0xC9 P4_1 ; -sbit at 0xCA P4_2 ; -sbit at 0xCB P4_3 ; -sbit at 0xCC P4_4 ; -sbit at 0xCD P4_5 ; -sbit at 0xCE P4_6 ; -sbit at 0xCF P4_7 ; - -/* PSW 0xD0 */ -sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ -sbit at 0xD1 F1 ; /* USER FLAG 1 */ -sbit at 0xD2 OV ; /* OVERFLOW FLAG */ -sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ -sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ -sbit at 0xD5 F0 ; /* USER FLAG 0 */ -sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ -sbit at 0xD7 CY ; /* CARRY FLAG */ - -/* PCA0CN D8H */ -sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ -sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ -sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ -sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ -sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ -sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */ -sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ -sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ - -/* P5 0xD8 */ -sbit at 0xD8 P5_0 ; -sbit at 0xD9 P5_1 ; -sbit at 0xDA P5_2 ; -sbit at 0xDB P5_3 ; -sbit at 0xDC P5_4 ; -sbit at 0xDD P5_5 ; -sbit at 0xDE P5_6 ; -sbit at 0xDF P5_7 ; - -/* ADC0CN E8H */ -sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ -sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */ -sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */ -sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */ -sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ -sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */ -sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ -sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ - -/* ADC2CN E8H */ -sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */ -sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */ -sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */ -sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */ -sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */ -sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */ -sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */ -sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */ - -/* P6 0xE8 */ -sbit at 0xE8 P6_0 ; -sbit at 0xE9 P6_1 ; -sbit at 0xEA P6_2 ; -sbit at 0xEB P6_3 ; -sbit at 0xEC P6_4 ; -sbit at 0xED P6_5 ; -sbit at 0xEE P6_6 ; -sbit at 0xEF P6_7 ; - -/* SPI0CN F8H */ -sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ -sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */ -sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */ -sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */ -sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ -sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ -sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ -sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ - -/* P7 0xF8 */ -sbit at 0xF8 P7_0 ; -sbit at 0xF9 P7_1 ; -sbit at 0xFA P7_2 ; -sbit at 0xFB P7_3 ; -sbit at 0xFC P7_4 ; -sbit at 0xFD P7_5 ; -sbit at 0xFE P7_6 ; -sbit at 0xFF P7_7 ; - - -/* Predefined SFR Bit Masks */ - -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ -#define ECCF 0x01 /* PCA0CPMn */ -#define PWM 0x02 /* PCA0CPMn */ -#define TOG 0x04 /* PCA0CPMn */ -#define MAT 0x08 /* PCA0CPMn */ -#define CAPN 0x10 /* PCA0CPMn */ -#define CAPP 0x20 /* PCA0CPMn */ -#define ECOM 0x40 /* PCA0CPMn */ -#define PWM16 0x80 /* PCA0CPMn */ -#define PORSF 0x02 /* RSTSRC */ -#define SWRSF 0x10 /* RSTSRC */ - - -/* SFR PAGE DEFINITIONS */ - -#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */ -#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */ -#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */ -#define CPT0_PAGE 0x01 /* COMPARATOR 0 */ -#define CPT1_PAGE 0x02 /* COMPARATOR 1 */ -#define UART0_PAGE 0x00 /* UART 0 */ -#define UART1_PAGE 0x01 /* UART 1 */ -#define SPI0_PAGE 0x00 /* SPI 0 */ -#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */ -#define ADC0_PAGE 0x00 /* ADC 0 */ -#define ADC2_PAGE 0x02 /* ADC 2 */ -#define SMB0_PAGE 0x00 /* SMBUS 0 */ -#define TMR2_PAGE 0x00 /* TIMER 2 */ -#define TMR3_PAGE 0x01 /* TIMER 3 */ -#define TMR4_PAGE 0x02 /* TIMER 4 */ -#define DAC0_PAGE 0x00 /* DAC 0 */ -#define DAC1_PAGE 0x01 /* DAC 1 */ -#define PCA0_PAGE 0x00 /* PCA 0 */ -#define PLL0_PAGE 0x0F /* PLL 0 */ - -#endif diff --git a/device/include/c8051f300.h b/device/include/c8051f300.h deleted file mode 100644 index 3ba1f000..00000000 --- a/device/include/c8051f300.h +++ /dev/null @@ -1,244 +0,0 @@ -/*------------------------------------------------------------------------- - Register Declarations for the Cygnal C8051F30x Processor Range - - Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --------------------------------------------------------------------------*/ - -#ifndef C8051F300_H -#define C8051F300_H - - -/* BYTE Registers */ -sfr at 0x80 P0 ; /* PORT 0 */ -sfr at 0x81 SP ; /* STACK POINTER */ -sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -sfr at 0x87 PCON ; /* POWER CONTROL */ -sfr at 0x88 TCON ; /* TIMER CONTROL */ -sfr at 0x89 TMOD ; /* TIMER MODE */ -sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -sfr at 0x8E CKCON ; /* CLOCK CONTROL */ -sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ -sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ -sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ -sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ -sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ -sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ -sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ -sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ -sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ -sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ -sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ -sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ -sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ -sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ -sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ -sfr at 0xBE ADC0 ; /* ADC 0 DATA */ -sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */ -sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ -sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */ -sfr at 0xC4 ADC0GT ; /* ADC 0 GREATER-THAN REGISTER */ -sfr at 0xC6 ADC0LT ; /* ADC 0 LESS-THAN REGISTER */ -sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ -sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ -sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -sfr at 0xD8 PCA0CN ; /* PCA CONTROL */ -sfr at 0xD9 PCA0MD ; /* PCA MODE */ -sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ -sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ -sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ -sfr at 0xE0 ACC ; /* ACCUMULATOR */ -sfr at 0xE1 PRT0MX ; /* PORT MUX CONFIGURATION REGISTER 0 */ -sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ -sfr at 0xE2 PRT1MX ; /* PORT MUX CONFIGURATION REGISTER 1 */ -sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ -sfr at 0xE3 PRT2MX ; /* PORT MUX CONFIGURATION REGISTER 2 */ -sfr at 0xE3 XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */ -sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ -sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ -sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ -sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ -sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ -sfr at 0xEF RSTSRC ; /* RESET SOURCE */ -sfr at 0xF0 B ; /* B REGISTER */ -sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ -sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ -sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -sfr at 0xF8 CPT0CN ; /* COMPARATOR 0 CONTROL */ -sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */ -sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */ -sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ -sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ - - -/* BIT Registers */ - -/* P0 0x80 */ -sbit at 0x80 P0_0 ; -sbit at 0x81 P0_1 ; -sbit at 0x82 P0_2 ; -sbit at 0x83 P0_3 ; -sbit at 0x84 P0_4 ; -sbit at 0x85 P0_5 ; -sbit at 0x86 P0_6 ; -sbit at 0x87 P0_7 ; - -/* TCON 0x88 */ -sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ -sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ -sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ -sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ -sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ -sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ -sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ -sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ - -/* SCON 0x98 */ -sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ -sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ -sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ -sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ -sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ -sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ -sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ -sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ - -/* IE 0xA8 */ -sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ -sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ -sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ -sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ -sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ -sbit at 0xAE IEGF0 ; /* IE.6 - GENERAL PURPOSE FLAG 0 */ -sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ - -/* IP 0xB8 */ -sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ -sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ -sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ -sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ -sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ -sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ -sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ - -/* SMB0CN 0xC0 */ -sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ -sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ -sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ -sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ -sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ -sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ -sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ -sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ - -/* TMR2CN 0xC8 */ -sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ -sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ -sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ -sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ -sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ -sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ -sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ - -/* PSW 0xD0 */ -sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ -sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ -sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ -sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ -sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ -sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ -sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ -sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ - -/* PCA0CN 0xD8 */ -sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ -sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ -sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ -sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ -sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ - -/* ADC0CN 0xE8 */ -sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ -sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ -sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ -sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ -sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ -sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ -sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */ -sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */ - -/* CPT0CN 0xF8 */ -sbit at 0xF8 CP0HYN0 ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/ -sbit at 0xF9 CP0HYN1 ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/ -sbit at 0xFA CP0HYP0 ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/ -sbit at 0xFB CP0HYP1 ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/ -sbit at 0xFC CP0FIF ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */ -sbit at 0xFD CP0RIF ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */ -sbit at 0xFE CP0OUT ; /* CPT0CN.6 - Comparator0 Output State Flag */ -sbit at 0xFF CP0EN ; /* CPT0CN.7 - Comparator0 Enable Bit */ - - -/* Predefined SFR Bit Masks */ - -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ -#define T1M 0x10 /* CKCON */ -#define PSWE 0x01 /* PSCTL */ -#define PSEE 0x02 /* PSCTL */ -#define ECP0F 0x10 /* EIE1 */ -#define ECP0R 0x20 /* EIE1 */ -#define PORSF 0x02 /* RSTSRC */ -#define SWRSF 0x10 /* RSTSRC */ -#define ECCF 0x01 /* PCA0CPMn */ -#define PWM 0x02 /* PCA0CPMn */ -#define TOG 0x04 /* PCA0CPMn */ -#define MAT 0x08 /* PCA0CPMn */ -#define CAPN 0x10 /* PCA0CPMn */ -#define CAPP 0x20 /* PCA0CPMn */ -#define ECOM 0x40 /* PCA0CPMn */ -#define PWM16 0x80 /* PCA0CPMn */ -#define CP0E 0x10 /* XBR1 */ -#define CP0OEN 0x10 /* XBR1 */ -#define CP0AE 0x20 /* XBR1 */ -#define CP0AOEN 0x20 /* XBR1 */ - -#endif diff --git a/device/include/c8051f310.h b/device/include/c8051f310.h deleted file mode 100644 index 4603755e..00000000 --- a/device/include/c8051f310.h +++ /dev/null @@ -1,316 +0,0 @@ -/*------------------------------------------------------------------------- - Register Declarations for the Cygnal C8051F31x Processor Range - - Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --------------------------------------------------------------------------*/ - -#ifndef C8051F310_H -#define C8051F310_H - - -/* BYTE Registers */ -sfr at 0x80 P0 ; /* PORT 0 */ -sfr at 0x81 SP ; /* STACK POINTER */ -sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -sfr at 0x87 PCON ; /* POWER CONTROL */ -sfr at 0x88 TCON ; /* TIMER CONTROL */ -sfr at 0x89 TMOD ; /* TIMER MODE */ -sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -sfr at 0x8E CKCON ; /* CLOCK CONTROL */ -sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ -sfr at 0x90 P1 ; /* PORT 1 */ -sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ -sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ -sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ -sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ -sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ -sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ -sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ -sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ -sfr at 0x9A CPT1CN ; /* COMPARATOR 1 CONTROL */ -sfr at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */ -sfr at 0x9C CPT1MD ; /* COMPARATOR 1 MODE SELECTION */ -sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ -sfr at 0x9E CPT1MX ; /* COMPARATOR 1 MUX SELECTION */ -sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ -sfr at 0xA0 P2 ; /* PORT 2 */ -sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */ -sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ -sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */ -sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ -sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ -sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ -sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ -sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ -sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */ -sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ -sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */ -sfr at 0xB0 P3 ; /* PORT 3 */ -sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ -sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ -sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ -sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ -sfr at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */ -sfr at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ -sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ -sfr at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */ -sfr at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */ -sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */ -sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ -sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */ -sfr at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */ -sfr at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */ -sfr at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */ -sfr at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */ -sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ -sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ -sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */ -sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */ -sfr at 0xD6 P2SKIP ; /* PORT 2 SKIP */ -sfr at 0xD8 PCA0CN ; /* PCA CONTROL */ -sfr at 0xD9 PCA0MD ; /* PCA MODE */ -sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ -sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ -sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ -sfr at 0xDD PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */ -sfr at 0xDE PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */ -sfr at 0xE0 ACC ; /* ACCUMULATOR */ -sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ -sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ -sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ -sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ -sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ -sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ -sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ -sfr at 0xED PCA0CPL3 ; /* PCA CAPTURE 3 LOW */ -sfr at 0xEE PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */ -sfr at 0xEF RSTSRC ; /* RESET SOURCE */ -sfr at 0xF0 B ; /* B REGISTER */ -sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ -sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ -sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ -sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ -sfr at 0xF3 P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */ -sfr at 0xF3 P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */ -sfr at 0xF4 P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */ -sfr at 0xF4 P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */ -sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */ -sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */ -sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */ -sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ -sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ -sfr at 0xFD PCA0CPL4 ; /* PCA CAPTURE 4 LOW */ -sfr at 0xFE PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */ -sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */ - - -/* BIT Registers */ - -/* P0 0x80 */ -sbit at 0x80 P0_0 ; -sbit at 0x81 P0_1 ; -sbit at 0x82 P0_2 ; -sbit at 0x83 P0_3 ; -sbit at 0x84 P0_4 ; -sbit at 0x85 P0_5 ; -sbit at 0x86 P0_6 ; -sbit at 0x87 P0_7 ; - -/* TCON 0x88 */ -sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ -sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ -sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ -sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ -sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ -sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ -sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ -sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ - -/* P1 0x90 */ -sbit at 0x90 P1_0 ; -sbit at 0x91 P1_1 ; -sbit at 0x92 P1_2 ; -sbit at 0x93 P1_3 ; -sbit at 0x94 P1_4 ; -sbit at 0x95 P1_5 ; -sbit at 0x96 P1_6 ; -sbit at 0x97 P1_7 ; - -/* SCON 0x98 */ -sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ -sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ -sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ -sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ -sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ -sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ -sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ -sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ - -/* P2 0xA0 */ -sbit at 0xA0 P2_0 ; -sbit at 0xA1 P2_1 ; -sbit at 0xA2 P2_2 ; -sbit at 0xA3 P2_3 ; -sbit at 0xA4 P2_4 ; -sbit at 0xA5 P2_5 ; -sbit at 0xA6 P2_6 ; -sbit at 0xA7 P2_7 ; - -/* IE 0xA8 */ -sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ -sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ -sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ -sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ -sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ -sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ -sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ - -/* P3 0xB0 */ -sbit at 0xB0 P3_0 ; -sbit at 0xB1 P3_1 ; -sbit at 0xB2 P3_2 ; -sbit at 0xB3 P3_3 ; -sbit at 0xB4 P3_4 ; -sbit at 0xB5 P3_5 ; -sbit at 0xB6 P3_6 ; -sbit at 0xB7 P3_7 ; - -/* IP 0xB8 */ -sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ -sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ -sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ -sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ -sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ -sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ -sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ -sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */ - -/* SMB0CN 0xC0 */ -sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ -sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ -sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ -sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ -sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ -sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ -sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ -sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ - -/* TMR2CN 0xC8 */ -sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ -sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ -sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ -sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ -sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ -sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ -sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ - -/* PSW 0xD0 */ -sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ -sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ -sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ -sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ -sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ -sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ -sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ -sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ - -/* PCA0CN 0xD8 */ -sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ -sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ -sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ -sbit at 0xDB CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */ -sbit at 0xDC CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */ -sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ -sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ - -/* ADC0CN 0xE8 */ -sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ -sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ -sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ -sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ -sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ -sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ -sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */ -sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */ - -/* SPI0CN 0xF8 */ -sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ -sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ -sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ -sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ -sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ -sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ -sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ -sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ - - -/* Predefined SFR Bit Masks */ - -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ -#define T1M 0x08 /* CKCON */ -#define PSWE 0x01 /* PSCTL */ -#define PSEE 0x02 /* PSCTL */ -#define ECP0 0x20 /* EIE1 */ -#define ECP1 0x40 /* EIE1 */ -#define PORSF 0x02 /* RSTSRC */ -#define SWRSF 0x10 /* RSTSRC */ -#define ECCF 0x01 /* PCA0CPMn */ -#define PWM 0x02 /* PCA0CPMn */ -#define TOG 0x04 /* PCA0CPMn */ -#define MAT 0x08 /* PCA0CPMn */ -#define CAPN 0x10 /* PCA0CPMn */ -#define CAPP 0x20 /* PCA0CPMn */ -#define ECOM 0x40 /* PCA0CPMn */ -#define PWM16 0x80 /* PCA0CPMn */ -#define CP0E 0x10 /* XBR0 */ -#define CP0OEN 0x10 /* XBR0 */ -#define CP0AE 0x20 /* XBR0 */ -#define CP0AOEN 0x20 /* XBR0 */ -#define CP1E 0x40 /* XBR0 */ -#define CP1AE 0x80 /* XBR0 */ - -#endif diff --git a/device/include/c8051f320.h b/device/include/c8051f320.h deleted file mode 100644 index ae8792ce..00000000 --- a/device/include/c8051f320.h +++ /dev/null @@ -1,324 +0,0 @@ -/*------------------------------------------------------------------------- - Register Declarations for the Cygnal C8051F32x Processor Range - - Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --------------------------------------------------------------------------*/ - -#ifndef C8051F320_H -#define C8051F320_H - - -/* BYTE Registers */ -sfr at 0x80 P0 ; /* PORT 0 */ -sfr at 0x81 SP ; /* STACK POINTER */ -sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ -sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ -sfr at 0x87 PCON ; /* POWER CONTROL */ -sfr at 0x88 TCON ; /* TIMER CONTROL */ -sfr at 0x89 TMOD ; /* TIMER MODE */ -sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ -sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ -sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ -sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ -sfr at 0x8E CKCON ; /* CLOCK CONTROL */ -sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ -sfr at 0x90 P1 ; /* PORT 1 */ -sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ -sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ -sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ -sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ -sfr at 0x96 USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */ -sfr at 0x97 USB0DAT ; /* USB0 DATA REGISTER */ -sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ -sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ -sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ -sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ -sfr at 0x9A CPT1CN ; /* COMPARATOR 1 CONTROL */ -sfr at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */ -sfr at 0x9C CPT1MD ; /* COMPARATOR 1 MODE SELECTION */ -sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ -sfr at 0x9E CPT1MX ; /* COMPARATOR 1 MUX SELECTION */ -sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ -sfr at 0xA0 P2 ; /* PORT 2 */ -sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */ -sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ -sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */ -sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ -sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ -sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ -sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ -sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ -sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */ -sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ -sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */ -sfr at 0xB0 P3 ; /* PORT 3 */ -sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ -sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ -sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ -sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ -sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ -sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ -sfr at 0xB9 CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */ -sfr at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */ -sfr at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ -sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ -sfr at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */ -sfr at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */ -sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */ -sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ -sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */ -sfr at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */ -sfr at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */ -sfr at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */ -sfr at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */ -sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ -sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ -sfr at 0xC9 REG0CN ; /* VOLTAGE REGULATOR CONTROL */ -sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ -sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ -sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ -sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ -sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ -sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ -sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */ -sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */ -sfr at 0xD6 P2SKIP ; /* PORT 2 SKIP */ -sfr at 0xD7 USB0XCN ; /* USB0 TRANSCEIVER CONTROL */ -sfr at 0xD8 PCA0CN ; /* PCA CONTROL */ -sfr at 0xD9 PCA0MD ; /* PCA MODE */ -sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ -sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ -sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ -sfr at 0xDD PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */ -sfr at 0xDE PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */ -sfr at 0xE0 ACC ; /* ACCUMULATOR */ -sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ -sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ -sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ -sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ -sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ -sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ -sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ -sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ -sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ -sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ -sfr at 0xED PCA0CPL3 ; /* PCA CAPTURE 3 LOW */ -sfr at 0xEE PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */ -sfr at 0xEF RSTSRC ; /* RESET SOURCE */ -sfr at 0xF0 B ; /* B REGISTER */ -sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ -sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ -sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ -sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ -sfr at 0xF3 P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */ -sfr at 0xF3 P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */ -sfr at 0xF4 P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */ -sfr at 0xF4 P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */ -sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ -sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ -sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */ -sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */ -sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */ -sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ -sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ -sfr at 0xFD PCA0CPL4 ; /* PCA CAPTURE 4 LOW */ -sfr at 0xFE PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */ -sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */ - - -/* BIT Registers */ - -/* P0 0x80 */ -sbit at 0x80 P0_0 ; -sbit at 0x81 P0_1 ; -sbit at 0x82 P0_2 ; -sbit at 0x83 P0_3 ; -sbit at 0x84 P0_4 ; -sbit at 0x85 P0_5 ; -sbit at 0x86 P0_6 ; -sbit at 0x87 P0_7 ; - -/* TCON 0x88 */ -sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ -sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ -sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ -sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ -sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ -sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ -sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ -sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ - -/* P1 0x90 */ -sbit at 0x90 P1_0 ; -sbit at 0x91 P1_1 ; -sbit at 0x92 P1_2 ; -sbit at 0x93 P1_3 ; -sbit at 0x94 P1_4 ; -sbit at 0x95 P1_5 ; -sbit at 0x96 P1_6 ; -sbit at 0x97 P1_7 ; - -/* SCON 0x98 */ -sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ -sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ -sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ -sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ -sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ -sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ -sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ -sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ -sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ -sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ -sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ - -/* P2 0xA0 */ -sbit at 0xA0 P2_0 ; -sbit at 0xA1 P2_1 ; -sbit at 0xA2 P2_2 ; -sbit at 0xA3 P2_3 ; -sbit at 0xA4 P2_4 ; -sbit at 0xA5 P2_5 ; -sbit at 0xA6 P2_6 ; -sbit at 0xA7 P2_7 ; - -/* IE 0xA8 */ -sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ -sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ -sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ -sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ -sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ -sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ -sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ -sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ - -/* P3 0xB0 */ -sbit at 0xB0 P3_0 ; -sbit at 0xB1 P3_1 ; -sbit at 0xB2 P3_2 ; -sbit at 0xB3 P3_3 ; -sbit at 0xB4 P3_4 ; -sbit at 0xB5 P3_5 ; -sbit at 0xB6 P3_6 ; -sbit at 0xB7 P3_7 ; - -/* IP 0xB8 */ -sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ -sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ -sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ -sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ -sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ -sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ -sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ -sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */ - -/* SMB0CN 0xC0 */ -sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ -sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ -sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ -sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ -sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ -sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ -sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ -sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ - -/* TMR2CN 0xC8 */ -sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ -sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ -sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ -sbit at 0xCC T2SOF ; /* TMR2CN.4 - TIMER 2 START_OF_FRAME CAPTURE ENA */ -sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ -sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ -sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ -sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ - -/* PSW 0xD0 */ -sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ -sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ -sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ -sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ -sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ -sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ -sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ -sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ - -/* PCA0CN 0xD8 */ -sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ -sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ -sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ -sbit at 0xDB CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */ -sbit at 0xDC CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */ -sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ -sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ - -/* ADC0CN 0xE8 */ -sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ -sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ -sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ -sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ -sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ -sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ -sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */ -sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */ - -/* SPI0CN 0xF8 */ -sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ -sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ -sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ -sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ -sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ -sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ -sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ -sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ - - -/* Predefined SFR Bit Masks */ - -#define IDLE 0x01 /* PCON */ -#define STOP 0x02 /* PCON */ -#define T1M 0x08 /* CKCON */ -#define PSWE 0x01 /* PSCTL */ -#define PSEE 0x02 /* PSCTL */ -#define ECP0 0x20 /* EIE1 */ -#define ECP1 0x40 /* EIE1 */ -#define PORSF 0x02 /* RSTSRC */ -#define SWRSF 0x10 /* RSTSRC */ -#define ECCF 0x01 /* PCA0CPMn */ -#define PWM 0x02 /* PCA0CPMn */ -#define TOG 0x04 /* PCA0CPMn */ -#define MAT 0x08 /* PCA0CPMn */ -#define CAPN 0x10 /* PCA0CPMn */ -#define CAPP 0x20 /* PCA0CPMn */ -#define ECOM 0x40 /* PCA0CPMn */ -#define PWM16 0x80 /* PCA0CPMn */ -#define CP0E 0x10 /* XBR0 */ -#define CP0OEN 0x10 /* XBR0 */ -#define CP0AE 0x20 /* XBR0 */ -#define CP0AOEN 0x20 /* XBR0 */ -#define CP1E 0x40 /* XBR0 */ -#define CP1AE 0x80 /* XBR0 */ - -#endif diff --git a/device/include/mcs51/c8051f000.h b/device/include/mcs51/c8051f000.h new file mode 100644 index 00000000..2e9ad76c --- /dev/null +++ b/device/include/mcs51/c8051f000.h @@ -0,0 +1,283 @@ +/*--------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F000-F017 Processor Range + + Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +---------------------------------------------------------------------------*/ + +#ifndef C8051F000_H +#define C8051F000_H + + +/* BYTE Registers */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */ +sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */ +sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ +sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ +sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */ +sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */ +sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */ +sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */ +sfr at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */ +sfr at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */ +sfr at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xAD PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */ +sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +sfr at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ +sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ +sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ +sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ +sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ +sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ +sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ +sfr at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ +sfr at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ +sfr at 0xD7 DAC1CN ; /* DAC 1 CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ +sfr at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */ +sfr at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */ +sfr at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */ +sfr at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */ +sfr at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */ +sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ +sfr at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */ +sfr at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */ +sfr at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */ +sfr at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */ +sfr at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */ +sfr at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ +sfr at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */ +sfr at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */ +sfr at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */ +sfr at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */ +sfr at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */ +sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x87 P0_7 ; +sbit at 0x86 P0_6 ; +sbit at 0x85 P0_5 ; +sbit at 0x84 P0_4 ; +sbit at 0x83 P0_3 ; +sbit at 0x82 P0_2 ; +sbit at 0x81 P0_1 ; +sbit at 0x80 P0_0 ; + +/* TCON 0x88 */ +sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ +sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ +sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ +sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ + +/* P1 0x90 */ +sbit at 0x97 P1_7 ; +sbit at 0x96 P1_6 ; +sbit at 0x95 P1_5 ; +sbit at 0x94 P1_4 ; +sbit at 0x93 P1_3 ; +sbit at 0x92 P1_2 ; +sbit at 0x91 P1_1 ; +sbit at 0x90 P1_0 ; + +/* SCON 0x98 */ +sbit at 0x9F SM0 ; /* SERIAL MODE CONTROL BIT 0 */ +sbit at 0x9E SM1 ; /* SERIAL MODE CONTROL BIT 1 */ +sbit at 0x9D SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9C REN ; /* RECEIVE ENABLE */ +sbit at 0x9B TB8 ; /* TRANSMIT BIT 8 */ +sbit at 0x9A RB8 ; /* RECEIVE BIT 8 */ +sbit at 0x99 TI ; /* TRANSMIT INTERRUPT FLAG */ +sbit at 0x98 RI ; /* RECEIVE INTERRUPT FLAG */ + +/* P2 0xA0 */ +sbit at 0xA7 P2_7 ; +sbit at 0xA6 P2_6 ; +sbit at 0xA5 P2_5 ; +sbit at 0xA4 P2_4 ; +sbit at 0xA3 P2_3 ; +sbit at 0xA2 P2_2 ; +sbit at 0xA1 P2_1 ; +sbit at 0xA0 P2_0 ; + +/* IE 0xA8 */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ +sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ + +/* P3 0xB0 */ +sbit at 0xB7 P3_7 ; +sbit at 0xB6 P3_6 ; +sbit at 0xB5 P3_5 ; +sbit at 0xB4 P3_4 ; +sbit at 0xB3 P3_3 ; +sbit at 0xB2 P3_2 ; +sbit at 0xB1 P3_1 ; +sbit at 0xB0 P3_0 ; + +/* IP 0xB8 */ +sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ +sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ +sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ +sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ +sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ +sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ +sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ +sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ +sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ +sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ +sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ + +/* T2CON 0xC8 */ +sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ +sbit at 0xCE EXF2 ; /* EXTERNAL FLAG */ +sbit at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */ +sbit at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */ +sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ +sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ +sbit at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */ +sbit at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */ + +/* PSW 0xD0 */ +sbit at 0xD7 CY ; /* CARRY FLAG */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ + +/* PCA0CN 0xD8H */ +sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ +sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ +sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ +sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ +sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ +sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ +sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ + +/* ADC0CN 0xE8H */ +sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ +sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ +sbit at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */ +sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */ +sbit at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */ +sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */ +sbit at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ + +/* SPI0CN 0xF8H */ +sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ +sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ +sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ +sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ +sbit at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */ +sbit at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */ +sbit at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */ +sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define TF3 0x80 /* TMR3CN */ +#define CPFIF 0x10 /* CPTnCN */ +#define CPRIF 0x20 /* CPTnCN */ +#define CPOUT 0x40 /* CPTnCN */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ + +#endif diff --git a/device/include/mcs51/c8051f018.h b/device/include/mcs51/c8051f018.h new file mode 100644 index 00000000..88a01d2d --- /dev/null +++ b/device/include/mcs51/c8051f018.h @@ -0,0 +1,277 @@ +/*--------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F018-F019 Processor Range + + Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +---------------------------------------------------------------------------*/ + +#ifndef C8051F018_H +#define C8051F018_H + + +/* BYTE Registers */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */ +sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */ +sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ +sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ +sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */ +sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */ +sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */ +sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */ +sfr at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */ +sfr at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */ +sfr at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xAD PRT1IF ; /* PORT 1 EXTERNAL INTERRUPT FLAGS */ +sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +sfr at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ +sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ +sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ +sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ +sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ +sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ +sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ +sfr at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */ +sfr at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */ +sfr at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */ +sfr at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */ +sfr at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */ +sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ +sfr at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */ +sfr at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */ +sfr at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */ +sfr at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */ +sfr at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */ +sfr at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ +sfr at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */ +sfr at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */ +sfr at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */ +sfr at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */ +sfr at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */ +sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x87 P0_7 ; +sbit at 0x86 P0_6 ; +sbit at 0x85 P0_5 ; +sbit at 0x84 P0_4 ; +sbit at 0x83 P0_3 ; +sbit at 0x82 P0_2 ; +sbit at 0x81 P0_1 ; +sbit at 0x80 P0_0 ; + +/* TCON 0x88 */ +sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ +sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ +sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ +sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ + +/* P1 0x90 */ +sbit at 0x97 P1_7 ; +sbit at 0x96 P1_6 ; +sbit at 0x95 P1_5 ; +sbit at 0x94 P1_4 ; +sbit at 0x93 P1_3 ; +sbit at 0x92 P1_2 ; +sbit at 0x91 P1_1 ; +sbit at 0x90 P1_0 ; + +/* SCON 0x98 */ +sbit at 0x9F SM0 ; /* SERIAL MODE CONTROL BIT 0 */ +sbit at 0x9E SM1 ; /* SERIAL MODE CONTROL BIT 1 */ +sbit at 0x9D SM2 ; /* MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9C REN ; /* RECEIVE ENABLE */ +sbit at 0x9B TB8 ; /* TRANSMIT BIT 8 */ +sbit at 0x9A RB8 ; /* RECEIVE BIT 8 */ +sbit at 0x99 TI ; /* TRANSMIT INTERRUPT FLAG */ +sbit at 0x98 RI ; /* RECEIVE INTERRUPT FLAG */ + +/* P2 0xA0 */ +sbit at 0xA7 P2_7 ; +sbit at 0xA6 P2_6 ; +sbit at 0xA5 P2_5 ; +sbit at 0xA4 P2_4 ; +sbit at 0xA3 P2_3 ; +sbit at 0xA2 P2_2 ; +sbit at 0xA1 P2_1 ; +sbit at 0xA0 P2_0 ; + +/* IE 0xA8 */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ +sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ + +/* P3 0xB0 */ +sbit at 0xB7 P3_7 ; +sbit at 0xB6 P3_6 ; +sbit at 0xB5 P3_5 ; +sbit at 0xB4 P3_4 ; +sbit at 0xB3 P3_3 ; +sbit at 0xB2 P3_2 ; +sbit at 0xB1 P3_1 ; +sbit at 0xB0 P3_0 ; + +/* IP 0xB8 */ +sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ +sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ +sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ +sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ +sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ +sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ +sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ +sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ +sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ +sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ +sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ + +/* T2CON 0xC8 */ +sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ +sbit at 0xCE EXF2 ; /* EXTERNAL FLAG */ +sbit at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */ +sbit at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */ +sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ +sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ +sbit at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */ +sbit at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */ + +/* PSW 0xD0 */ +sbit at 0xD7 CY ; /* CARRY FLAG */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ + +/* PCA0CN 0xD8H */ +sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ +sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ +sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ +sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ +sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ +sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ +sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ + +/* ADC0CN 0xE8H */ +sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ +sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ +sbit at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */ +sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */ +sbit at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */ +sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */ +sbit at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ + +/* SPI0CN 0xF8H */ +sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ +sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ +sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ +sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ +sbit at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */ +sbit at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */ +sbit at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */ +sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define TF3 0x80 /* TMR3CN */ +#define CPFIF 0x10 /* CPTnCN */ +#define CPRIF 0x20 /* CPTnCN */ +#define CPOUT 0x40 /* CPTnCN */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ + +#endif diff --git a/device/include/mcs51/c8051f020.h b/device/include/mcs51/c8051f020.h new file mode 100644 index 00000000..84edeef6 --- /dev/null +++ b/device/include/mcs51/c8051f020.h @@ -0,0 +1,345 @@ +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F02x Processor Range + + Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F020_H +#define C8051F020_H + + +/* BYTE Registers */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x84 P4 ; /* PORT 4 */ +sfr at 0x85 P5 ; /* PORT 5 */ +sfr at 0x86 P6 ; /* PORT 6 */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0x92 TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */ +sfr at 0x93 TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */ +sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0x96 P7 ; /* PORT 7 */ +sfr at 0x98 SCON ; /* UART0 CONTROL */ +sfr at 0x98 SCON0 ; /* UART0 CONTROL */ +sfr at 0x99 SBUF ; /* UART0 BUFFER */ +sfr at 0x99 SBUF0 ; /* UART0 BUFFER */ +sfr at 0x9A SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */ +sfr at 0x9B SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */ +sfr at 0x9C ADC1 ; /* ADC 1 DATA */ +sfr at 0x9D SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */ +sfr at 0x9E CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x9F CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA1 EMI0TC ; /* External Memory Timing Control */ +sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ +sfr at 0xA4 PRT0CF ; /* PORT 0 CONFIGURATION */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +sfr at 0xA5 PRT1CF ; /* PORT 1 CONFIGURATION */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +sfr at 0xA6 PRT2CF ; /* PORT 2 CONFIGURATION */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA7 PRT3CF ; /* PORT 3 CONFIGURATION */ +sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xA9 SADDR0 ; /* UART0 Slave Address */ +sfr at 0xAA ADC1CN ; /* ADC 1 CONTROL */ +sfr at 0xAB ADC1CF ; /* ADC 1 CONFIGURATION */ +sfr at 0xAC AMX1SL ; /* ADC 1 MUX CHANNEL SELECTION */ +sfr at 0xAD P3IF ; /* PORT 3 EXTERNAL INTERRUPT FLAGS */ +sfr at 0xAE SADEN1 ; /* UART1 Slave Address Enable */ +sfr at 0xAF EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +sfr at 0xAF _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0xB5 P74OUT ; /* PORT 4 THROUGH 7 OUTPUT MODE CONFIGURATION */ +sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +sfr at 0xB7 FLACL ; /* FLASH ACESS LIMIT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xB9 SADEN0 ; /* UART0 Slave Address Enable */ +sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBD P1MDIN ; /* PORT 1 Input Mode */ +sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ +sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ +sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ +sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ +sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ +sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ +sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ +sfr at 0xC9 T4CON ; /* TIMER 4 CONTROL */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ +sfr at 0xD5 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ +sfr at 0xD6 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ +sfr at 0xD7 DAC1CN ; /* DAC 1 CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ +sfr at 0xDA PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */ +sfr at 0xDB PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */ +sfr at 0xDC PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */ +sfr at 0xDD PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */ +sfr at 0xDE PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE1 XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */ +sfr at 0xE3 XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */ +sfr at 0xE4 RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xE5 RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ +sfr at 0xEA PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */ +sfr at 0xEB PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */ +sfr at 0xEC PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */ +sfr at 0xED PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */ +sfr at 0xEE PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF1 SCON1 ; /* UART1 CONTROL */ +sfr at 0xF2 SBUF1 ; /* UART1 DATA */ +sfr at 0xF3 SADDR1 ; /* UART1 Slave Address */ +sfr at 0xF4 TL4 ; /* TIMER 4 DATA - LOW BYTE */ +sfr at 0xF5 TH4 ; /* TIMER 4 DATA - HIGH BYTE */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xF8 SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */ +sfr at 0xF9 PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ +sfr at 0xFA PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */ +sfr at 0xFB PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */ +sfr at 0xFC PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */ +sfr at 0xFD PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */ +sfr at 0xFE PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */ +sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ + +/* P1 0x90 */ +sbit at 0x90 P1_0 ; +sbit at 0x91 P1_1 ; +sbit at 0x92 P1_2 ; +sbit at 0x93 P1_3 ; +sbit at 0x94 P1_4 ; +sbit at 0x95 P1_5 ; +sbit at 0x96 P1_6 ; +sbit at 0x97 P1_7 ; + +/* SCON 0x98 */ +sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9D SM20 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9E SM1 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */ +sbit at 0x9E SM10 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */ +sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +sbit at 0x9F SM00 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* P2 0xA0 */ +sbit at 0xA0 P2_0 ; +sbit at 0xA1 P2_1 ; +sbit at 0xA2 P2_2 ; +sbit at 0xA3 P2_3 ; +sbit at 0xA4 P2_4 ; +sbit at 0xA5 P2_5 ; +sbit at 0xA6 P2_6 ; +sbit at 0xA7 P2_7 ; + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* SERIAL PORT 0 INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* SERIAL PORT 0 INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ + +/* P3 0xB0 */ +sbit at 0xB0 P3_0 ; +sbit at 0xB1 P3_1 ; +sbit at 0xB2 P3_2 ; +sbit at 0xB3 P3_3 ; +sbit at 0xB4 P3_4 ; +sbit at 0xB5 P3_5 ; +sbit at 0xB6 P3_6 ; +sbit at 0xB7 P3_7 ; + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ +sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ +sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ +sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ +sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ +sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ + +/* T2CON 0xC8 */ +sbit at 0xC8 CPRL2 ; /* CAPTURE OR RELOAD SELECT */ +sbit at 0xC9 CT2 ; /* TIMER OR COUNTER SELECT */ +sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ +sbit at 0xCC TCLK ; /* TRANSMIT CLOCK FLAG */ +sbit at 0xCD RCLK ; /* RECEIVE CLOCK FLAG */ +sbit at 0xCE EXF2 ; /* EXTERNAL FLAG */ +sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ + +/* PSW 0xD0 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* CARRY FLAG */ + +/* PCA0CN 0xD8H */ +sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ +sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ +sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ +sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ +sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ +sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ +sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ + +/* ADC0CN 0xE8H */ +sbit at 0xE8 ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ +sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ +sbit at 0xE9 ADWINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */ +sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */ +sbit at 0xEA ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */ +sbit at 0xEA AD0CM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */ +sbit at 0xEB ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */ +sbit at 0xEB AD0CM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */ +sbit at 0xEC ADBUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xED ADCINT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */ +sbit at 0xED AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */ +sbit at 0xEE ADCTM ; /* ADC 0 TRACK MODE */ +sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ +sbit at 0xEF ADCEN ; /* ADC 0 ENABLE */ +sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ + +/* SPI0CN 0xF8H */ +sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ +sbit at 0xF9 MSTEN ; /* SPI 0 MASTER ENABLE */ +sbit at 0xFA SLVSEL ; /* SPI 0 SLAVE SELECT */ +sbit at 0xFB TXBSY ; /* SPI 0 TX BUSY FLAG */ +sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define SMOD0 0x80 /* PCON */ +#define TF3 0x80 /* TMR3CN */ +#define CPFIF 0x10 /* CPTnCN */ +#define CPRIF 0x20 /* CPTnCN */ +#define CPOUT 0x40 /* CPTnCN */ +#define TR4 0x04 /* T4CON */ +#define TF4 0x80 /* T4CON */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define RI1 0x01 /* SCON1 */ +#define TI1 0x02 /* SCON1 */ +#define RB81 0x04 /* SCON1 */ +#define TB81 0x08 /* SCON1 */ +#define REN1 0x10 /* SCON1 */ +#define SM21 0x20 /* SCON1 */ +#define SM11 0x40 /* SCON1 */ +#define SM01 0x80 /* SCON1 */ + +#endif diff --git a/device/include/mcs51/c8051f040.h b/device/include/mcs51/c8051f040.h new file mode 100644 index 00000000..81c00fb9 --- /dev/null +++ b/device/include/mcs51/c8051f040.h @@ -0,0 +1,500 @@ +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F04x Processor Range + + Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F040_H +#define C8051F040_H + + +/* BYTE Registers */ + +/* All Pages */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */ +sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */ +sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ + +/* Page 0x00 */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */ +sfr at 0x91 SSTA0 ; /* UART 0 STATUS */ +sfr at 0x98 SCON0 ; /* UART 0 CONTROL */ +sfr at 0x98 SCON ; /* UART 0 CONTROL */ +sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */ +sfr at 0x99 SBUF ; /* UART 0 BUFFER */ +sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */ +sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */ +sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */ +sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */ +sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */ +sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ +sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */ +sfr at 0xB7 FLSCL ; /* FLASH SCALE */ +sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */ +sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBD AMX0PRT ; /* ADC 0 PORT 3 I/O PIN SELECT */ +sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ +sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ +sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ +sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ +sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ +sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ +sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ +sfr at 0xD6 HVA0CN ; /* HIGH VOLTAGE DIFFERENTIAL AMP CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */ +sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */ +sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */ +sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */ +sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */ +sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */ +sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ +sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ +sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */ + +/* Page 0x01 */ +sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */ +sfr at 0x98 SCON1 ; /* UART 1 CONTROL */ +sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */ +sfr at 0xC0 CAN0STA ; /* CAN 0 STATUS */ +sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */ +sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */ +sfr at 0xD8 CAN0DATL ; /* CAN 0 DATA REGISTER LOW */ +sfr at 0xD9 CAN0DATH ; /* CAN 0 DATA REGISTER HIGH */ +sfr at 0xDA CAN0ADR ; /* CAN 0 ADDRESS */ +sfr at 0xDB CAN0TST ; /* CAN 0 TEST REGISTER */ +sfr at 0xF8 CAN0CN ; /* CAN 0 CONTROL */ + +/* Page 0x02 */ +sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */ +sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */ +sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */ +sfr at 0xBE ADC2 ; /* ADC 2 DATA */ +sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */ +sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */ +sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */ +sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */ +sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */ +sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */ +sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */ + +/* Page 0x03 */ +sfr at 0x88 CPT2CN ; /* COMPARATOR 2 CONTROL */ +sfr at 0x89 CPT2MD ; /* COMPARATOR 2 CONFIGURATION */ + +/* Page 0x0F */ +sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */ +sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */ +sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */ +sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */ +sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */ +sfr at 0xAE P2MDIN ; /* PORT 2 INPUT MODE */ +sfr at 0xAF P3MDIN ; /* PORT 3 INPUT MODE */ +sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */ +sfr at 0xC8 P4 ; /* PORT 4 */ +sfr at 0xD8 P5 ; /* PORT 5 */ +sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */ +sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */ +sfr at 0xE4 XBR3 ; /* CROSSBAR CONFIGURATION REGISTER 3 */ +sfr at 0xE8 P6 ; /* PORT 6 */ +sfr at 0xF8 P7 ; /* PORT 7 */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ + +/* CPT0CN 0x88 */ +sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */ +sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */ +sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */ + +/* CPT1CN 0x88 */ +sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */ +sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */ +sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */ + +/* CPT2CN 0x88 */ +sbit at 0x88 CP2HYN0 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP2HYN1 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP2HYP0 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP2HYP1 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP2FIF ; /* COMPARATOR 2 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP2RIF ; /* COMPARATOR 2 RISING EDGE INTERRUPT */ +sbit at 0x8E CP2OUT ; /* COMPARATOR 2 OUTPUT */ +sbit at 0x8F CP2EN ; /* COMPARATOR 2 ENABLE */ + +/* P1 0x90 */ +sbit at 0x90 P1_0 ; +sbit at 0x91 P1_1 ; +sbit at 0x92 P1_2 ; +sbit at 0x93 P1_3 ; +sbit at 0x94 P1_4 ; +sbit at 0x95 P1_5 ; +sbit at 0x96 P1_6 ; +sbit at 0x97 P1_7 ; + +/* SCON0 0x98 */ +sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */ +sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */ +sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */ +sbit at 0x9C REN ; /* UART 0 RX ENABLE */ +sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */ +sbit at 0x9E SM10 ; /* UART 0 MODE 1 */ +sbit at 0x9F SM00 ; /* UART 0 MODE 0 */ + +/* SCON1 0x98 */ +sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */ +sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */ +sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */ +sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */ +sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */ +sbit at 0x9D MCE1 ; /* UART 1 MCE */ +sbit at 0x9F S1MODE ; /* UART 1 MODE */ + +/* P2 0xA0 */ +sbit at 0xA0 P2_0 ; +sbit at 0xA1 P2_1 ; +sbit at 0xA2 P2_2 ; +sbit at 0xA3 P2_3 ; +sbit at 0xA4 P2_4 ; +sbit at 0xA5 P2_5 ; +sbit at 0xA6 P2_6 ; +sbit at 0xA7 P2_7 ; + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ + +/* P3 0xB0 */ +sbit at 0xB0 P3_0 ; +sbit at 0xB1 P3_1 ; +sbit at 0xB2 P3_2 ; +sbit at 0xB3 P3_3 ; +sbit at 0xB4 P3_4 ; +sbit at 0xB5 P3_5 ; +sbit at 0xB6 P3_6 ; +sbit at 0xB7 P3_7 ; + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ +sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ +sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ +sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ +sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ +sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ + +/* CAN0STA 0xC0 */ +sbit at 0xC3 CANTXOK ; /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */ +sbit at 0xC4 CANRXOK ; /* CAN RECEIVED A MESSAGE SUCCESSFULLY */ +sbit at 0xC5 CANEPASS; /* CAN ERROR PASSIVE */ +sbit at 0xC6 CANEWARN; /* CAN WARNING STATUS */ +sbit at 0xC7 CANBOFF ; /* CAN BUSOFF STATUS */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */ +sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */ +sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */ +sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ + +/* TMR3CN 0xC8 */ +sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */ +sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */ +sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */ +sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */ +sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */ + +/* TMR4CN 0xC8 */ +sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */ +sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */ +sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */ +sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */ +sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */ + +/* P4 0xC8 */ +sbit at 0xC8 P4_0 ; +sbit at 0xC9 P4_1 ; +sbit at 0xCA P4_2 ; +sbit at 0xCB P4_3 ; +sbit at 0xCC P4_4 ; +sbit at 0xCD P4_5 ; +sbit at 0xCE P4_6 ; +sbit at 0xCF P4_7 ; + +/* PSW 0xD0 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* CARRY FLAG */ + +/* PCA0CN 0xD8 */ +sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ +sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ +sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ +sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ +sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ +sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */ +sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ +sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ + +/* P5 0xD8 */ +sbit at 0xD8 P5_0 ; +sbit at 0xD9 P5_1 ; +sbit at 0xDA P5_2 ; +sbit at 0xDB P5_3 ; +sbit at 0xDC P5_4 ; +sbit at 0xDD P5_5 ; +sbit at 0xDE P5_6 ; +sbit at 0xDF P5_7 ; + +/* ADC0CN 0xE8 */ +sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ +sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */ +sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */ +sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */ +sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */ +sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ + +/* ADC2CN 0xE8 */ +sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */ +sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */ +sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */ +sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */ +sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */ +sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */ +sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */ +sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */ + +/* P6 0xE8 */ +sbit at 0xE8 P6_0 ; +sbit at 0xE9 P6_1 ; +sbit at 0xEA P6_2 ; +sbit at 0xEB P6_3 ; +sbit at 0xEC P6_4 ; +sbit at 0xED P6_5 ; +sbit at 0xEE P6_6 ; +sbit at 0xEF P6_7 ; + +/* SPI0CN 0xF8 */ +sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */ +sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */ +sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */ +sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ + +/* CAN0CN 0xF8 */ +sbit at 0xF8 CANINIT ; /* CAN INITIALIZATION */ +sbit at 0xF9 CANIE ; /* CAN MODULE INTERRUPT ENABLE */ +sbit at 0xFA CANSIE ; /* CAN STATUS CHANGE INTERRUPT ENABLE */ +sbit at 0xFB CANEIE ; /* CAN ERROR INTERRUPT ENABLE */ +sbit at 0xFC CANIF ; /* CAN INTERRUPT FLAG */ +sbit at 0xFD CANDAR ; /* CAN DISABLE AUTOMATIC RETRANSMISSION */ +sbit at 0xFE CANCCE ; /* CAN CONFIGURATION CHANGE ENABLE */ +sbit at 0xFF CANTEST ; /* CAN TEST MODE ENABLE */ + +/* P7 0xF8 */ +sbit at 0xF8 P7_0 ; +sbit at 0xF9 P7_1 ; +sbit at 0xFA P7_2 ; +sbit at 0xFB P7_3 ; +sbit at 0xFC P7_4 ; +sbit at 0xFD P7_5 ; +sbit at 0xFE P7_6 ; +sbit at 0xFF P7_7 ; + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ + + +/* SFR PAGE DEFINITIONS */ + +#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */ +#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */ +#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */ +#define CPT0_PAGE 0x01 /* COMPARATOR 0 */ +#define CPT1_PAGE 0x02 /* COMPARATOR 1 */ +#define UART0_PAGE 0x00 /* UART 0 */ +#define UART1_PAGE 0x01 /* UART 1 */ +#define SPI0_PAGE 0x00 /* SPI 0 */ +#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */ +#define ADC0_PAGE 0x00 /* ADC 0 */ +#define ADC2_PAGE 0x02 /* ADC 2 */ +#define SMB0_PAGE 0x00 /* SMBUS 0 */ +#define TMR2_PAGE 0x00 /* TIMER 2 */ +#define TMR3_PAGE 0x01 /* TIMER 3 */ +#define TMR4_PAGE 0x02 /* TIMER 4 */ +#define DAC0_PAGE 0x00 /* DAC 0 */ +#define DAC1_PAGE 0x01 /* DAC 1 */ +#define PCA0_PAGE 0x00 /* PCA 0 */ +#define CAN0_PAGE 0x01 /* CAN 0 */ + +#endif diff --git a/device/include/mcs51/c8051f060.h b/device/include/mcs51/c8051f060.h new file mode 100644 index 00000000..7ef00e47 --- /dev/null +++ b/device/include/mcs51/c8051f060.h @@ -0,0 +1,550 @@ +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F06x Processor Range + + Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F060_H +#define C8051F060_H + + +/* BYTE Registers */ + +/* All Pages */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */ +sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */ +sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ + +/* Page 0x00 */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */ +sfr at 0x91 SSTA0 ; /* UART 0 STATUS */ +sfr at 0x98 SCON0 ; /* UART 0 CONTROL */ +sfr at 0x98 SCON ; /* UART 0 CONTROL */ +sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */ +sfr at 0x99 SBUF ; /* UART 0 BUFFER */ +sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */ +sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */ +sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */ +sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */ +sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */ +sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ +sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */ +sfr at 0xB7 FLSCL ; /* FLASH SCALE */ +sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ +sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ +sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ +sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ +sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ +sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ +sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */ +sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */ +sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */ +sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */ +sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */ +sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */ +sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ +sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ +sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */ + +/* Page 0x01 */ +sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */ +sfr at 0x98 SCON1 ; /* UART 1 CONTROL */ +sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */ +sfr at 0xBC ADC1CF ; /* ADC 1 CONFIGURATION */ +sfr at 0xBE ADC1L ; /* ADC 1 DATA - LOW BYTE */ +sfr at 0xBF ADC1H ; /* ADC 1 DATA - HIGH BYTE */ +sfr at 0xC0 CAN0STA ; /* CAN 0 STATUS */ +sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */ +sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0xD1 REF1CN ; /* VOLTAGE REFERENCE 1 CONTROL */ +sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */ +sfr at 0xD8 CAN0DATL ; /* CAN 0 DATA REGISTER LOW */ +sfr at 0xD9 CAN0DATH ; /* CAN 0 DATA REGISTER HIGH */ +sfr at 0xDA CAN0ADR ; /* CAN 0 ADDRESS */ +sfr at 0xDB CAN0TST ; /* CAN 0 TEST REGISTER */ +sfr at 0xE8 ADC1CN ; /* ADC 1 CONTROL */ +sfr at 0xF8 CAN0CN ; /* CAN 0 CONTROL */ + +/* Page 0x02 */ +sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */ +sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */ +sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */ +sfr at 0xBE ADC2L ; /* ADC 2 DATA - LOW BYTE */ +sfr at 0xBF ADC2H ; /* ADC 2 DATA - HIGH BYTE */ +sfr at 0xC4 ADC2GTL ; /* ADC 2 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC2GTH ; /* ADC 2 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC2LTL ; /* ADC 2 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC2LTH ; /* ADC 2 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */ +sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */ +sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */ +sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */ +sfr at 0xD1 REF2CN ; /* VOLTAGE REFERENCE 2 CONTROL */ +sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */ + +/* Page 0x03 */ +sfr at 0x88 CPT2CN ; /* COMPARATOR 2 CONTROL */ +sfr at 0x89 CPT2MD ; /* COMPARATOR 2 CONFIGURATION */ +sfr at 0xD8 DMA0CN ; /* DMA0 CONTROL */ +sfr at 0xD9 DMA0DAL ; /* DMA0 DATA ADDRESS BEGINNING LOW BYTE */ +sfr at 0xDA DMA0DAH ; /* DMA0 DATA ADDRESS BEGINNING HIGH BYTE */ +sfr at 0xDB DMA0DSL ; /* DMA0 DATA ADDRESS POINTER LOW BYTE */ +sfr at 0xDC DMA0DSH ; /* DMA0 DATA ADDRESS POINTER HIGH BYTE */ +sfr at 0xDD DMA0IPT ; /* DMA0 INSTRUCTION WRITE ADDRESS */ +sfr at 0xDE DMA0IDT ; /* DMA0 INSTRUCTION WRITE DATA */ +sfr at 0xF8 DMA0CF ; /* DMA0 CONFIGURATION */ +sfr at 0xF9 DMA0CTL ; /* DMA0 REPEAT COUNTER LIMIT LOW BYTE */ +sfr at 0xFA DMA0CTH ; /* DMA0 REPEAT COUNTER LIMIT HIGH BYTE */ +sfr at 0xFB DMA0CSL ; /* DMA0 REPEAT COUNTER STATUS LOW BYTE */ +sfr at 0xFC DMA0CSH ; /* DMA0 REPEAT COUNTER STATUS HIGH BYTE */ +sfr at 0xFD DMA0BND ; /* DMA0 INSTRUCTION BOUNDARY */ +sfr at 0xFE DMA0ISW ; /* DMA0 INSTRUCTION STATUS */ + +/* Page 0x0F */ +sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */ +sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */ +sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */ +sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */ +sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */ +sfr at 0xAE P2MDIN ; /* PORT 2 INPUT MODE */ +sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */ +sfr at 0xBA ADC0CPT ; /* ADC0 CALIBRATION POINTER */ +sfr at 0xBB ADC0CCF ; /* ADC0 CALIBRATION COEFFICIENT */ +sfr at 0xC8 P4 ; /* PORT 4 */ +sfr at 0xD8 P5 ; /* PORT 5 */ +sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */ +sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */ +sfr at 0xE4 XBR3 ; /* CROSSBAR CONFIGURATION REGISTER 3 */ +sfr at 0xE8 P6 ; /* PORT 6 */ +sfr at 0xF8 P7 ; /* PORT 7 */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ + +/* CPT0CN 0x88 */ +sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */ +sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */ +sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */ + +/* CPT1CN 0x88 */ +sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */ +sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */ +sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */ + +/* CPT2CN 0x88 */ +sbit at 0x88 CP2HYN0 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP2HYN1 ; /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP2HYP0 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP2HYP1 ; /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP2FIF ; /* COMPARATOR 2 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP2RIF ; /* COMPARATOR 2 RISING EDGE INTERRUPT */ +sbit at 0x8E CP2OUT ; /* COMPARATOR 2 OUTPUT */ +sbit at 0x8F CP2EN ; /* COMPARATOR 2 ENABLE */ + +/* P1 0x90 */ +sbit at 0x90 P1_0 ; +sbit at 0x91 P1_1 ; +sbit at 0x92 P1_2 ; +sbit at 0x93 P1_3 ; +sbit at 0x94 P1_4 ; +sbit at 0x95 P1_5 ; +sbit at 0x96 P1_6 ; +sbit at 0x97 P1_7 ; + +/* SCON0 0x98 */ +sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */ +sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */ +sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */ +sbit at 0x9C REN ; /* UART 0 RX ENABLE */ +sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */ +sbit at 0x9E SM10 ; /* UART 0 MODE 1 */ +sbit at 0x9F SM00 ; /* UART 0 MODE 0 */ + +/* SCON1 0x98 */ +sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */ +sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */ +sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */ +sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */ +sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */ +sbit at 0x9D MCE1 ; /* UART 1 MCE */ +sbit at 0x9F S1MODE ; /* UART 1 MODE */ + +/* P2 0xA0 */ +sbit at 0xA0 P2_0 ; +sbit at 0xA1 P2_1 ; +sbit at 0xA2 P2_2 ; +sbit at 0xA3 P2_3 ; +sbit at 0xA4 P2_4 ; +sbit at 0xA5 P2_5 ; +sbit at 0xA6 P2_6 ; +sbit at 0xA7 P2_7 ; + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ + +/* P3 0xB0 */ +sbit at 0xB0 P3_0 ; +sbit at 0xB1 P3_1 ; +sbit at 0xB2 P3_2 ; +sbit at 0xB3 P3_3 ; +sbit at 0xB4 P3_4 ; +sbit at 0xB5 P3_5 ; +sbit at 0xB6 P3_6 ; +sbit at 0xB7 P3_7 ; + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ +sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ +sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ +sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ +sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ +sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ + +/* CAN0STA 0xC0 */ +sbit at 0xC3 CANTXOK ; /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */ +sbit at 0xC4 CANRXOK ; /* CAN RECEIVED A MESSAGE SUCCESSFULLY */ +sbit at 0xC5 CANEPASS; /* CAN ERROR PASSIVE */ +sbit at 0xC6 CANEWARN; /* CAN WARNING STATUS */ +sbit at 0xC7 CANBOFF ; /* CAN BUSOFF STATUS */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */ +sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */ +sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */ +sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ + +/* TMR3CN 0xC8 */ +sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */ +sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */ +sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */ +sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */ +sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */ + +/* TMR4CN 0xC8 */ +sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */ +sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */ +sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */ +sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */ +sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */ + +/* P4 0xC8 */ +sbit at 0xC8 P4_0 ; +sbit at 0xC9 P4_1 ; +sbit at 0xCA P4_2 ; +sbit at 0xCB P4_3 ; +sbit at 0xCC P4_4 ; +sbit at 0xCD P4_5 ; +sbit at 0xCE P4_6 ; +sbit at 0xCF P4_7 ; + +/* PSW 0xD0 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* CARRY FLAG */ + +/* PCA0CN 0xD8 */ +sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ +sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ +sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ +sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ +sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ +sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */ +sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ +sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ + +/* DMA0CN 0xD8 */ +sbit at 0xD8 DMA0DO0 ; /* ADC0 Data Overflow Warning Flag */ +sbit at 0xD9 DMA0DO1 ; /* ADC1 Data Overflow Warning Flag */ +sbit at 0xDA DMA0DOE ; /* Data Overflow Warning Interrupt Enable */ +sbit at 0xDB DMA0DE0 ; /* ADC0 Data Overflow Error Flag */ +sbit at 0xDC DMA0DE1 ; /* ADC1 Data Overflow Error Flag */ +sbit at 0xDD DMA0MD ; /* DMA0 Mode Select */ +sbit at 0xDE DMA0INT ; /* DMA0 Operations Complete Flag */ +sbit at 0xDF DMA0EN ; /* DMA0 Enable */ + +/* P5 0xD8 */ +sbit at 0xD8 P5_0 ; +sbit at 0xD9 P5_1 ; +sbit at 0xDA P5_2 ; +sbit at 0xDB P5_3 ; +sbit at 0xDC P5_4 ; +sbit at 0xDD P5_5 ; +sbit at 0xDE P5_6 ; +sbit at 0xDF P5_7 ; + +/* ADC0CN 0xE8 */ +sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */ +sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */ +sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */ +sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */ +sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ + +/* ADC1CN 0xE8 */ +sbit at 0xE9 AD1CM0 ; /* ADC 1 CONVERT START MODE BIT 0 */ +sbit at 0xEA AD1CM1 ; /* ADC 1 CONVERT START MODE BIT 1 */ +sbit at 0xEB AD1CM2 ; /* ADC 1 CONVERT START MODE BIT 1 */ +sbit at 0xEC AD1BUSY ; /* ADC 1 BUSY FLAG */ +sbit at 0xED AD1INT ; /* ADC 1 EOC INTERRUPT FLAG */ +sbit at 0xEE AD1TM ; /* ADC 1 TRACK MODE */ +sbit at 0xEF AD1EN ; /* ADC 1 ENABLE */ + +/* ADC2CN 0xE8 */ +sbit at 0xE8 AD2LJST ; /* ADC 2 LEFT JUSTIFY SELECT */ +sbit at 0xE9 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */ +sbit at 0xEA AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */ +sbit at 0xEB AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */ +sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */ +sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */ +sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */ +sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */ + +/* P6 0xE8 */ +sbit at 0xE8 P6_0 ; +sbit at 0xE9 P6_1 ; +sbit at 0xEA P6_2 ; +sbit at 0xEB P6_3 ; +sbit at 0xEC P6_4 ; +sbit at 0xED P6_5 ; +sbit at 0xEE P6_6 ; +sbit at 0xEF P6_7 ; + +/* SPI0CN 0xF8 */ +sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */ +sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */ +sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */ +sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ + +/* CAN0CN 0xF8 */ +sbit at 0xF8 CANINIT ; /* CAN INITIALIZATION */ +sbit at 0xF9 CANIE ; /* CAN MODULE INTERRUPT ENABLE */ +sbit at 0xFA CANSIE ; /* CAN STATUS CHANGE INTERRUPT ENABLE */ +sbit at 0xFB CANEIE ; /* CAN ERROR INTERRUPT ENABLE */ +sbit at 0xFC CANIF ; /* CAN INTERRUPT FLAG */ +sbit at 0xFD CANDAR ; /* CAN DISABLE AUTOMATIC RETRANSMISSION */ +sbit at 0xFE CANCCE ; /* CAN CONFIGURATION CHANGE ENABLE */ +sbit at 0xFF CANTEST ; /* CAN TEST MODE ENABLE */ + +/* DMA0CF 0xF8 */ +sbit at 0xF8 DMA0EO ; /* END-OF-OPERATION FLAG */ +sbit at 0xF9 DMA0EOE ; /* END-OF-OPERATION INTERRUPT ENABLE */ +sbit at 0xFA DMA0CI ; /* REPEAT COUNTER OVERFLOW FLAG */ +sbit at 0xFB DMA0CIE ; /* REPEAT COUNTER OVERFLOW INTERRUPT ENABLE */ +sbit at 0xFE DMA0XBY ; /* OFF-CHIP XRAM BUSY FLAG */ +sbit at 0xFF DMA0HLT ; /* HALT DMA0 OFF-CHIP XRAM ACCESS */ + +/* P7 0xF8 */ +sbit at 0xF8 P7_0 ; +sbit at 0xF9 P7_1 ; +sbit at 0xFA P7_2 ; +sbit at 0xFB P7_3 ; +sbit at 0xFC P7_4 ; +sbit at 0xFD P7_5 ; +sbit at 0xFE P7_6 ; +sbit at 0xFF P7_7 ; + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ + + +/* SFR PAGE DEFINITIONS */ + +#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */ +#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */ +#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */ +#define CPT0_PAGE 0x01 /* COMPARATOR 0 */ +#define CPT1_PAGE 0x02 /* COMPARATOR 1 */ +#define CPT2_PAGE 0x03 /* COMPARATOR 2 */ +#define UART0_PAGE 0x00 /* UART 0 */ +#define UART1_PAGE 0x01 /* UART 1 */ +#define SPI0_PAGE 0x00 /* SPI 0 */ +#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */ +#define ADC0_PAGE 0x00 /* ADC 0 */ +#define ADC1_PAGE 0x01 /* ADC 1 */ +#define ADC2_PAGE 0x02 /* ADC 2 */ +#define SMB0_PAGE 0x00 /* SMBUS 0 */ +#define TMR2_PAGE 0x00 /* TIMER 2 */ +#define TMR3_PAGE 0x01 /* TIMER 3 */ +#define TMR4_PAGE 0x02 /* TIMER 4 */ +#define DAC0_PAGE 0x00 /* DAC 0 */ +#define DAC1_PAGE 0x01 /* DAC 1 */ +#define PCA0_PAGE 0x00 /* PCA 0 */ +#define DMA0_PAGE 0x03 /* DMA 0 */ +#define CAN0_PAGE 0x01 /* CAN 0 */ + +#endif diff --git a/device/include/mcs51/c8051f120.h b/device/include/mcs51/c8051f120.h new file mode 100644 index 00000000..62151233 --- /dev/null +++ b/device/include/mcs51/c8051f120.h @@ -0,0 +1,456 @@ +/*--------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F12x-F13x Processor Range + + Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +---------------------------------------------------------------------------*/ + +#ifndef C8051F120_H +#define C8051F120_H + + +/* BYTE Registers */ + +/* All Pages */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */ +sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */ +sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */ + +/* Page 0x00 */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */ +sfr at 0x91 SSTA0 ; /* UART 0 STATUS */ +sfr at 0x98 SCON0 ; /* UART 0 CONTROL */ +sfr at 0x98 SCON ; /* UART 0 CONTROL */ +sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */ +sfr at 0x99 SBUF ; /* UART 0 BUFFER */ +sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */ +sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */ +sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */ +sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */ +sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */ +sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */ +sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */ +sfr at 0xB7 FLSCL ; /* FLASH SCALE */ +sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */ +sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */ +sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */ +sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */ +sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */ +sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */ +sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */ +sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */ +sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */ +sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */ +sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */ +sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */ +sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */ +sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */ +sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */ +sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */ +sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */ +sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */ + +/* Page 0x01 */ +sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */ +sfr at 0x98 SCON1 ; /* UART 1 CONTROL */ +sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */ +sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */ +sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */ +sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */ +sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */ + +/* Page 0x02 */ +sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */ +sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */ +sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */ +sfr at 0xBE ADC2 ; /* ADC 2 DATA */ +sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */ +sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */ +sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */ +sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */ +sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */ +sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */ +sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */ + +/* Page 0x03 */ +sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */ +sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */ +sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */ +sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */ +sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */ +sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */ +sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */ +sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */ +sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */ +sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */ +sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */ +sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */ +sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */ + +/* Page 0x0F */ +sfr at 0x88 FLSTAT ; /* FLASH STATUS */ +sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */ +sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */ +sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */ +sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */ +sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */ +sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */ +sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */ +sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */ +sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */ +sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */ +sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */ +sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */ +sfr at 0xA3 CCH0LC ; /* CACHE LOCK */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */ +sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */ +sfr at 0xC8 P4 ; /* PORT 4 */ +sfr at 0xD8 P5 ; /* PORT 5 */ +sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */ +sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */ +sfr at 0xE8 P6 ; /* PORT 6 */ +sfr at 0xF8 P7 ; /* PORT 7 */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */ + +/* CPT0CN 0x88 */ +sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */ +sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */ +sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */ + +/* CPT1CN 0x88 */ +sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */ +sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */ +sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */ +sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */ +sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */ +sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */ +sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */ +sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */ + +/* FLSTAT 0x88 */ +sbit at 0x88 FLHBUSY ; /* FLASH BUSY */ + +/* SCON0 0x98 */ +sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */ +sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */ +sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */ +sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */ +sbit at 0x9C REN ; /* UART 0 RX ENABLE */ +sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */ +sbit at 0x9E SM10 ; /* UART 0 MODE 1 */ +sbit at 0x9F SM00 ; /* UART 0 MODE 0 */ + +/* SCON1 0x98 */ +sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */ +sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */ +sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */ +sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */ +sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */ +sbit at 0x9D MCE1 ; /* UART 1 MCE */ +sbit at 0x9F S1MODE ; /* UART 1 MODE */ + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */ +sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */ +sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */ +sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */ +sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */ +sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */ +sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */ +sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */ +sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */ + +/* TMR3CN 0xC8 */ +sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */ +sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */ +sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */ +sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */ +sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */ + +/* TMR4CN 0xC8 */ +sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */ +sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */ +sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */ +sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */ +sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */ +sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */ + +/* P4 0xC8 */ +sbit at 0xC8 P4_0 ; +sbit at 0xC9 P4_1 ; +sbit at 0xCA P4_2 ; +sbit at 0xCB P4_3 ; +sbit at 0xCC P4_4 ; +sbit at 0xCD P4_5 ; +sbit at 0xCE P4_6 ; +sbit at 0xCF P4_7 ; + +/* PSW 0xD0 */ +sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* USER FLAG 1 */ +sbit at 0xD2 OV ; /* OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* USER FLAG 0 */ +sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* CARRY FLAG */ + +/* PCA0CN D8H */ +sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */ +sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */ +sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */ +sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */ +sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */ +sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */ +sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */ +sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */ + +/* P5 0xD8 */ +sbit at 0xD8 P5_0 ; +sbit at 0xD9 P5_1 ; +sbit at 0xDA P5_2 ; +sbit at 0xDB P5_3 ; +sbit at 0xDC P5_4 ; +sbit at 0xDD P5_5 ; +sbit at 0xDE P5_6 ; +sbit at 0xDF P5_7 ; + +/* ADC0CN E8H */ +sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */ +sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */ +sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */ +sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */ +sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */ +sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */ + +/* ADC2CN E8H */ +sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */ +sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */ +sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */ +sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */ +sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */ +sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */ +sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */ +sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */ + +/* P6 0xE8 */ +sbit at 0xE8 P6_0 ; +sbit at 0xE9 P6_1 ; +sbit at 0xEA P6_2 ; +sbit at 0xEB P6_3 ; +sbit at 0xEC P6_4 ; +sbit at 0xED P6_5 ; +sbit at 0xEE P6_6 ; +sbit at 0xEF P6_7 ; + +/* SPI0CN F8H */ +sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */ +sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */ +sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */ +sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */ + +/* P7 0xF8 */ +sbit at 0xF8 P7_0 ; +sbit at 0xF9 P7_1 ; +sbit at 0xFA P7_2 ; +sbit at 0xFB P7_3 ; +sbit at 0xFC P7_4 ; +sbit at 0xFD P7_5 ; +sbit at 0xFE P7_6 ; +sbit at 0xFF P7_7 ; + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ + + +/* SFR PAGE DEFINITIONS */ + +#define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */ +#define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */ +#define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */ +#define CPT0_PAGE 0x01 /* COMPARATOR 0 */ +#define CPT1_PAGE 0x02 /* COMPARATOR 1 */ +#define UART0_PAGE 0x00 /* UART 0 */ +#define UART1_PAGE 0x01 /* UART 1 */ +#define SPI0_PAGE 0x00 /* SPI 0 */ +#define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */ +#define ADC0_PAGE 0x00 /* ADC 0 */ +#define ADC2_PAGE 0x02 /* ADC 2 */ +#define SMB0_PAGE 0x00 /* SMBUS 0 */ +#define TMR2_PAGE 0x00 /* TIMER 2 */ +#define TMR3_PAGE 0x01 /* TIMER 3 */ +#define TMR4_PAGE 0x02 /* TIMER 4 */ +#define DAC0_PAGE 0x00 /* DAC 0 */ +#define DAC1_PAGE 0x01 /* DAC 1 */ +#define PCA0_PAGE 0x00 /* PCA 0 */ +#define PLL0_PAGE 0x0F /* PLL 0 */ + +#endif diff --git a/device/include/mcs51/c8051f300.h b/device/include/mcs51/c8051f300.h new file mode 100644 index 00000000..741832e6 --- /dev/null +++ b/device/include/mcs51/c8051f300.h @@ -0,0 +1,244 @@ +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F30x Processor Range + + Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F300_H +#define C8051F300_H + + +/* BYTE Registers */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ +sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ +sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ +sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ +sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ +sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ +sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBE ADC0 ; /* ADC 0 DATA */ +sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */ +sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ +sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */ +sfr at 0xC4 ADC0GT ; /* ADC 0 GREATER-THAN REGISTER */ +sfr at 0xC6 ADC0LT ; /* ADC 0 LESS-THAN REGISTER */ +sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ +sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ +sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE1 PRT0MX ; /* PORT MUX CONFIGURATION REGISTER 0 */ +sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ +sfr at 0xE2 PRT1MX ; /* PORT MUX CONFIGURATION REGISTER 1 */ +sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ +sfr at 0xE3 PRT2MX ; /* PORT MUX CONFIGURATION REGISTER 2 */ +sfr at 0xE3 XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */ +sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ +sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ +sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ +sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF8 CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */ +sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */ +sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ +sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* SCON 0x98 */ +sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAE IEGF0 ; /* IE.6 - GENERAL PURPOSE FLAG 0 */ +sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ +sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ +sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0CN 0xE8 */ +sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */ + +/* CPT0CN 0xF8 */ +sbit at 0xF8 CP0HYN0 ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/ +sbit at 0xF9 CP0HYN1 ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/ +sbit at 0xFA CP0HYP0 ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/ +sbit at 0xFB CP0HYP1 ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/ +sbit at 0xFC CP0FIF ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */ +sbit at 0xFD CP0RIF ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */ +sbit at 0xFE CP0OUT ; /* CPT0CN.6 - Comparator0 Output State Flag */ +sbit at 0xFF CP0EN ; /* CPT0CN.7 - Comparator0 Enable Bit */ + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define T1M 0x10 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0F 0x10 /* EIE1 */ +#define ECP0R 0x20 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR1 */ +#define CP0OEN 0x10 /* XBR1 */ +#define CP0AE 0x20 /* XBR1 */ +#define CP0AOEN 0x20 /* XBR1 */ + +#endif diff --git a/device/include/mcs51/c8051f310.h b/device/include/mcs51/c8051f310.h new file mode 100644 index 00000000..7de0ba84 --- /dev/null +++ b/device/include/mcs51/c8051f310.h @@ -0,0 +1,316 @@ +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F31x Processor Range + + Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F310_H +#define C8051F310_H + + +/* BYTE Registers */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ +sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ +sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ +sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ +sfr at 0x9A CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x9C CPT1MD ; /* COMPARATOR 1 MODE SELECTION */ +sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ +sfr at 0x9E CPT1MX ; /* COMPARATOR 1 MUX SELECTION */ +sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */ +sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ +sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */ +sfr at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */ +sfr at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */ +sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */ +sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ +sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */ +sfr at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */ +sfr at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */ +sfr at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */ +sfr at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */ +sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */ +sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */ +sfr at 0xD6 P2SKIP ; /* PORT 2 SKIP */ +sfr at 0xD8 PCA0CN ; /* PCA CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ +sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ +sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ +sfr at 0xDD PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */ +sfr at 0xDE PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ +sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ +sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ +sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ +sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ +sfr at 0xED PCA0CPL3 ; /* PCA CAPTURE 3 LOW */ +sfr at 0xEE PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ +sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ +sfr at 0xF3 P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */ +sfr at 0xF3 P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */ +sfr at 0xF4 P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */ +sfr at 0xF4 P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */ +sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */ +sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ +sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ +sfr at 0xFD PCA0CPL4 ; /* PCA CAPTURE 4 LOW */ +sfr at 0xFE PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */ +sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* P1 0x90 */ +sbit at 0x90 P1_0 ; +sbit at 0x91 P1_1 ; +sbit at 0x92 P1_2 ; +sbit at 0x93 P1_3 ; +sbit at 0x94 P1_4 ; +sbit at 0x95 P1_5 ; +sbit at 0x96 P1_6 ; +sbit at 0x97 P1_7 ; + +/* SCON 0x98 */ +sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* P2 0xA0 */ +sbit at 0xA0 P2_0 ; +sbit at 0xA1 P2_1 ; +sbit at 0xA2 P2_2 ; +sbit at 0xA3 P2_3 ; +sbit at 0xA4 P2_4 ; +sbit at 0xA5 P2_5 ; +sbit at 0xA6 P2_6 ; +sbit at 0xA7 P2_7 ; + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* P3 0xB0 */ +sbit at 0xB0 P3_0 ; +sbit at 0xB1 P3_1 ; +sbit at 0xB2 P3_2 ; +sbit at 0xB3 P3_3 ; +sbit at 0xB4 P3_4 ; +sbit at 0xB5 P3_5 ; +sbit at 0xB6 P3_6 ; +sbit at 0xB7 P3_7 ; + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ +sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ +sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ +sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +sbit at 0xDB CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */ +sbit at 0xDC CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */ +sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0CN 0xE8 */ +sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */ + +/* SPI0CN 0xF8 */ +sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define T1M 0x08 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0 0x20 /* EIE1 */ +#define ECP1 0x40 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR0 */ +#define CP0OEN 0x10 /* XBR0 */ +#define CP0AE 0x20 /* XBR0 */ +#define CP0AOEN 0x20 /* XBR0 */ +#define CP1E 0x40 /* XBR0 */ +#define CP1AE 0x80 /* XBR0 */ + +#endif diff --git a/device/include/mcs51/c8051f320.h b/device/include/mcs51/c8051f320.h new file mode 100644 index 00000000..76a4ca2b --- /dev/null +++ b/device/include/mcs51/c8051f320.h @@ -0,0 +1,324 @@ +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F32x Processor Range + + Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F320_H +#define C8051F320_H + + +/* BYTE Registers */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0x96 USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */ +sfr at 0x97 USB0DAT ; /* USB0 DATA REGISTER */ +sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ +sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ +sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ +sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ +sfr at 0x9A CPT1CN ; /* COMPARATOR 1 CONTROL */ +sfr at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x9C CPT1MD ; /* COMPARATOR 1 MODE SELECTION */ +sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ +sfr at 0x9E CPT1MX ; /* COMPARATOR 1 MUX SELECTION */ +sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */ +sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ +sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xB0 P3 ; /* PORT 3 */ +sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xB9 CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */ +sfr at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */ +sfr at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */ +sfr at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */ +sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */ +sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ +sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */ +sfr at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */ +sfr at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */ +sfr at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */ +sfr at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */ +sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xC9 REG0CN ; /* VOLTAGE REGULATOR CONTROL */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */ +sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */ +sfr at 0xD6 P2SKIP ; /* PORT 2 SKIP */ +sfr at 0xD7 USB0XCN ; /* USB0 TRANSCEIVER CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ +sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ +sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ +sfr at 0xDD PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */ +sfr at 0xDE PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ +sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ +sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ +sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ +sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ +sfr at 0xED PCA0CPL3 ; /* PCA CAPTURE 3 LOW */ +sfr at 0xEE PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ +sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ +sfr at 0xF3 P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */ +sfr at 0xF3 P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */ +sfr at 0xF4 P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */ +sfr at 0xF4 P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */ +sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */ +sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */ +sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ +sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ +sfr at 0xFD PCA0CPL4 ; /* PCA CAPTURE 4 LOW */ +sfr at 0xFE PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */ +sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* P1 0x90 */ +sbit at 0x90 P1_0 ; +sbit at 0x91 P1_1 ; +sbit at 0x92 P1_2 ; +sbit at 0x93 P1_3 ; +sbit at 0x94 P1_4 ; +sbit at 0x95 P1_5 ; +sbit at 0x96 P1_6 ; +sbit at 0x97 P1_7 ; + +/* SCON 0x98 */ +sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* P2 0xA0 */ +sbit at 0xA0 P2_0 ; +sbit at 0xA1 P2_1 ; +sbit at 0xA2 P2_2 ; +sbit at 0xA3 P2_3 ; +sbit at 0xA4 P2_4 ; +sbit at 0xA5 P2_5 ; +sbit at 0xA6 P2_6 ; +sbit at 0xA7 P2_7 ; + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* P3 0xB0 */ +sbit at 0xB0 P3_0 ; +sbit at 0xB1 P3_1 ; +sbit at 0xB2 P3_2 ; +sbit at 0xB3 P3_3 ; +sbit at 0xB4 P3_4 ; +sbit at 0xB5 P3_5 ; +sbit at 0xB6 P3_6 ; +sbit at 0xB7 P3_7 ; + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ +sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +sbit at 0xCC T2SOF ; /* TMR2CN.4 - TIMER 2 START_OF_FRAME CAPTURE ENA */ +sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ +sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ +sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +sbit at 0xDB CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */ +sbit at 0xDC CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */ +sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0CN 0xE8 */ +sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */ + +/* SPI0CN 0xF8 */ +sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define T1M 0x08 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0 0x20 /* EIE1 */ +#define ECP1 0x40 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR0 */ +#define CP0OEN 0x10 /* XBR0 */ +#define CP0AE 0x20 /* XBR0 */ +#define CP0AOEN 0x20 /* XBR0 */ +#define CP1E 0x40 /* XBR0 */ +#define CP1AE 0x80 /* XBR0 */ + +#endif diff --git a/device/include/mcs51/c8051f330.h b/device/include/mcs51/c8051f330.h new file mode 100644 index 00000000..21357274 --- /dev/null +++ b/device/include/mcs51/c8051f330.h @@ -0,0 +1,290 @@ +/*------------------------------------------------------------------------- + Register Declarations for the Cygnal/SiLabs C8051F33x Processor Range + + Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F330_H +#define C8051F330_H + + +/* BYTE Registers */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0x96 IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */ +sfr at 0x97 IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */ +sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ +sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ +sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ +sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ +sfr at 0x9B CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ +sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */ +sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ +sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xB9 IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */ +sfr at 0xBA AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */ +sfr at 0xBB AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ +sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xBD ADC0L ; /* ADC 0 DATA WORD LSB */ +sfr at 0xBE ADC0H ; /* ADC 0 DATA WORD MSB */ +sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */ +sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ +sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */ +sfr at 0xC3 ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */ +sfr at 0xC4 ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */ +sfr at 0xC5 ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */ +sfr at 0xC6 ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */ +sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */ +sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */ +sfr at 0xD8 PCA0CN ; /* PCA CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ +sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ +sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ +sfr at 0xE3 OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */ +sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ +sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ +sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ +sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ +sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */ +sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */ +sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ +sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ +sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* P1 0x90 */ +sbit at 0x90 P1_0 ; +sbit at 0x91 P1_1 ; +sbit at 0x92 P1_2 ; +sbit at 0x93 P1_3 ; +sbit at 0x94 P1_4 ; +sbit at 0x95 P1_5 ; +sbit at 0x96 P1_6 ; +sbit at 0x97 P1_7 ; + +/* SCON 0x98 */ +sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* P2 0xA0 */ +sbit at 0xA0 P2_0 ; +sbit at 0xA1 P2_1 ; +sbit at 0xA2 P2_2 ; +sbit at 0xA3 P2_3 ; +sbit at 0xA4 P2_4 ; +sbit at 0xA5 P2_5 ; +sbit at 0xA6 P2_6 ; +sbit at 0xA7 P2_7 ; + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ +sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +sbit at 0xCD TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/ +sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ +sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ +sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0CN 0xE8 */ +sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ +sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */ +sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */ + +/* SPI0CN 0xF8 */ +sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define T1M 0x08 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0 0x20 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR0 */ +#define CP0OEN 0x10 /* XBR0 */ +#define CP0AE 0x20 /* XBR0 */ +#define CP0AOEN 0x20 /* XBR0 */ + +#endif diff --git a/device/include/mcs51/c8051f350.h b/device/include/mcs51/c8051f350.h new file mode 100644 index 00000000..60cf1546 --- /dev/null +++ b/device/include/mcs51/c8051f350.h @@ -0,0 +1,304 @@ +/*------------------------------------------------------------------------- + Register Declarations for the SiLabs C8051F35x Processor Range + + Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F350_H +#define C8051F350_H + + +/* BYTE Registers */ +sfr at 0x80 P0 ; /* PORT 0 */ +sfr at 0x81 SP ; /* STACK POINTER */ +sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */ +sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */ +sfr at 0x87 PCON ; /* POWER CONTROL */ +sfr at 0x88 TCON ; /* TIMER CONTROL */ +sfr at 0x89 TMOD ; /* TIMER MODE */ +sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */ +sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */ +sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */ +sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */ +sfr at 0x8E CKCON ; /* CLOCK CONTROL */ +sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */ +sfr at 0x90 P1 ; /* PORT 1 */ +sfr at 0x91 TMR3CN ; /* TIMER 3 CONTROL */ +sfr at 0x92 TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +sfr at 0x93 TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0x94 TMR3L ; /* TIMER 3 - LOW BYTE */ +sfr at 0x95 TMR3H ; /* TIMER 3 - HIGH BYTE */ +sfr at 0x96 IDA0 ; /* CURRENT MODE DAC 0 */ +sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */ +sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */ +sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */ +sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */ +sfr at 0x9A ADC0DECL ; /* ADC DECIMATION LOW */ +sfr at 0x9B ADC0DECH ; /* ADC DECIMATION HIGH */ +sfr at 0x9C CPT0CN ; /* COMPARATOR 0 CONTROL */ +sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */ +sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */ +sfr at 0xA0 P2 ; /* PORT 2 */ +sfr at 0xA1 SPI0CFG ; /* SPI0 CONFIGURATION */ +sfr at 0xA2 SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */ +sfr at 0xA3 SPI0DAT ; /* SPI0 DATA */ +sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +sfr at 0xA8 IE ; /* INTERRUPT ENABLE */ +sfr at 0xA9 CLKSEL ; /* SYSTEM CLOCK SELECT */ +sfr at 0xAA EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +sfr at 0xAA _XPAGE ; /* XDATA/PDATA PAGE */ +sfr at 0xAB ADC0CGL ; /* ADC 0 GAIN CALIBRATION LOW */ +sfr at 0xAC ADC0CGM ; /* ADC 0 GAIN CALIBRATION MIDDLE */ +sfr at 0xAD ADC0CGH ; /* ADC 0 GAIN CALIBRATION HIGH */ +sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */ +sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */ +sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */ +sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */ +sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */ +sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */ +sfr at 0xB9 IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */ +sfr at 0xBA ADC0COL ; /* ADC 0 OFFSET CALIBRATION LOW */ +sfr at 0xBB ADC0COM ; /* ADC 0 OFFSET CALIBRATION MIDDLE */ +sfr at 0xBC ADC0COH ; /* ADC 0 OFFSET CALIBRATION HIGH */ +sfr at 0xBD ADC0BUF ; /* ADC 0 BUFFER CONTROL */ +sfr at 0xBE CLKMUL ; /* CLOCK MULTIPLIER */ +sfr at 0xBF ADC0DAC ; /* ADC 0 OFFSET DAC */ +sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */ +sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */ +sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */ +sfr at 0xC3 ADC0L ; /* ADC 0 OUTPUT LOW BYTE */ +sfr at 0xC4 ADC0M ; /* ADC 0 OUTPUT MIDDLE BYTE */ +sfr at 0xC5 ADC0H ; /* ADC 0 OUTPUT HIGH BYTE */ +sfr at 0xC6 ADC0MUX ; /* ADC 0 MULTIPLEXER */ +sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */ +sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */ +sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */ +sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */ +sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */ +sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */ +sfr at 0xD4 P0SKIP ; /* PORT 0 SKIP */ +sfr at 0xD5 P1SKIP ; /* PORT 1 SKIP */ +sfr at 0xD7 IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */ +sfr at 0xD8 PCA0CN ; /* PCA CONTROL */ +sfr at 0xD9 PCA0MD ; /* PCA MODE */ +sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */ +sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */ +sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */ +sfr at 0xDD IDA1 ; /* CURRENT MODE DAC 1 */ +sfr at 0xE0 ACC ; /* ACCUMULATOR */ +sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */ +sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */ +sfr at 0xE3 PFE0CN ; /* PREFETCH ENGINE CONTROL */ +sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */ +sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */ +sfr at 0xE8 ADC0STA ; /* ADC 0 STATUS */ +sfr at 0xE9 PCA0CPL0 ; /* PCA CAPTURE 0 LOW */ +sfr at 0xEA PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */ +sfr at 0xEB PCA0CPL1 ; /* PCA CAPTURE 1 LOW */ +sfr at 0xEC PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */ +sfr at 0xED PCA0CPL2 ; /* PCA CAPTURE 2 LOW */ +sfr at 0xEE PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */ +sfr at 0xEF RSTSRC ; /* RESET SOURCE */ +sfr at 0xF0 B ; /* B REGISTER */ +sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */ +sfr at 0xF2 P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */ +sfr at 0xF2 P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */ +sfr at 0xF3 ADC0MD ; /* ADC 0 MODE */ +sfr at 0xF4 ADC0CN ; /* ADC 0 CONTROL */ +sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +sfr at 0xF7 ADC0CLK ; /* ADC 0 CLOCK */ +sfr at 0xF8 SPI0CN ; /* SPI0 CONTROL */ +sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */ +sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */ +sfr at 0xFB ADC0CF ; /* ADC 0 CONFIGURATION */ +sfr at 0xFC ADC0FL ; /* ADC 0 FAST FILTER OUTPUT LOW */ +sfr at 0xFD ADC0FM ; /* ADC 0 FAST FILTER OUTPUT MIDDLE */ +sfr at 0xFE ADC0FH ; /* ADC 0 FAST FILTER OUTPUT HIGH */ +sfr at 0xFF VDM0CN ; /* VDD MONITOR CONTROL */ + + +/* BIT Registers */ + +/* P0 0x80 */ +sbit at 0x80 P0_0 ; +sbit at 0x81 P0_1 ; +sbit at 0x82 P0_2 ; +sbit at 0x83 P0_3 ; +sbit at 0x84 P0_4 ; +sbit at 0x85 P0_5 ; +sbit at 0x86 P0_6 ; +sbit at 0x87 P0_7 ; + +/* TCON 0x88 */ +sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* P1 0x90 */ +sbit at 0x90 P1_0 ; +sbit at 0x91 P1_1 ; +sbit at 0x92 P1_2 ; +sbit at 0x93 P1_3 ; +sbit at 0x94 P1_4 ; +sbit at 0x95 P1_5 ; +sbit at 0x96 P1_6 ; +sbit at 0x97 P1_7 ; + +/* SCON 0x98 */ +sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */ +sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */ +sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */ +sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* P2 0xA0 */ +sbit at 0xA0 P2_0 ; +sbit at 0xA1 P2_1 ; +sbit at 0xA2 P2_2 ; +sbit at 0xA3 P2_3 ; +sbit at 0xA4 P2_4 ; +sbit at 0xA5 P2_5 ; +sbit at 0xA6 P2_6 ; +sbit at 0xA7 P2_7 ; + +/* IE 0xA8 */ +sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +sbit at 0xAE ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */ +sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */ +sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */ +sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */ +sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */ +sbit at 0xBE PSPI0 ; /* IP.6 - SPI0 PRIORITY */ + +/* SMB0CN 0xC0 */ +sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +sbit at 0xCD TF2CEN ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/ +sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */ +sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */ +sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */ +sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */ +sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */ +sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */ +sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0STA 0xE8 */ +sbit at 0xE8 AD0OVR ; /* ADC0CN.0 - ADC 0 OVERRUN FLAG */ +sbit at 0xE9 AD0ERR ; /* ADC0CN.1 - ADC 0 ERROR FLAG */ +sbit at 0xEA AD0CALC ; /* ADC0CN.2 - ADC 0 CALIBRATION COMPLETE FLAG */ +sbit at 0xEB AD0FFC ; /* ADC0CN.3 - ADC 0 FAST FILTER CLIP FLAG */ +sbit at 0xEC AD0S3C ; /* ADC0CN.4 - ADC 0 SINC3 FILTER CLIP FLAG */ +sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +sbit at 0xEE AD0CBSY ; /* ADC0CN.6 - ADC 0 CALIBRATION IN PROGRESS FLAG */ +sbit at 0xEF AD0BUSY ; /* ADC0CN.7 - ADC 0 CONVERSION IN PROGRESS FLAG */ + +/* SPI0CN 0xF8 */ +sbit at 0xF8 SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */ +sbit at 0xF9 TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +sbit at 0xFA NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +sbit at 0xFB NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +sbit at 0xFC RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +sbit at 0xFD MODF ; /* SPI0CN.5 - MODE FAULT FLAG */ +sbit at 0xFE WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */ +sbit at 0xFF SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ + + +/* Predefined SFR Bit Masks */ + +#define IDLE 0x01 /* PCON */ +#define STOP 0x02 /* PCON */ +#define T1M 0x08 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0 0x20 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR0 */ +#define CP0OEN 0x10 /* XBR0 */ +#define CP0AE 0x20 /* XBR0 */ +#define CP0AOEN 0x20 /* XBR0 */ + +#endif