From: Antonio Borneo <borneo.antonio@gmail.com>
Date: Mon, 24 Jun 2019 16:28:31 +0000 (+0200)
Subject: armv7a: access monitor registers only with security extensions
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=6900c5af4ec3f6df52227169d7d897eb14a44bca;p=fw%2Fopenocd

armv7a: access monitor registers only with security extensions

Accordingly to ARM DDI 0406C at B1.5, the security extensions for
armv7a are optional extensions and can be detected by reading
ID_PFR1.
The monitor mode is part of the security extensions and the shadow
registers "sp_mon", "lr_mon" and "spsr_mon" are only present with
the security extensions.

Read the register ID_PFR1 during cortex_a examine, determine if
security extension is present and then conditionally enable the
visibility of the monitor mode shadow registers.

Change-Id: Ib4834698659046566f6dc5cd35b44de122dc02e5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5259
Tested-by: jenkins
---

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 0ef04c162..3d88c8679 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -178,6 +178,9 @@ static inline bool is_armv7a(struct armv7a_common *armv7a)
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS	0xFB8
 
+/* See ARMv7a arch spec DDI 0406C C11.10 */
+#define CPUDBG_ID_PFR1		0xD24
+
 /* Masks for Vector Catch register */
 #define DBG_VCR_FIQ_MASK	((1 << 31) | (1 << 7))
 #define DBG_VCR_IRQ_MASK	((1 << 30) | (1 << 6))
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 4f351f04a..22cbc3d06 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2678,7 +2678,7 @@ static int cortex_a_examine_first(struct target *target)
 
 	int i;
 	int retval = ERROR_OK;
-	uint32_t didr, cpuid, dbg_osreg;
+	uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1;
 
 	/* Search for the APB-AP - it is needed for access to debug registers */
 	retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
@@ -2787,7 +2787,16 @@ static int cortex_a_examine_first(struct target *target)
 		}
 	}
 
-	armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
+	retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+				 armv7a->debug_base + CPUDBG_ID_PFR1, &dbg_idpfr1);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (dbg_idpfr1 & 0x000000f0) {
+		LOG_DEBUG("target->coreid %" PRId32 " has security extensions",
+				target->coreid);
+		armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
+	}
 
 	/* Avoid recreating the registers cache */
 	if (!target_was_examined(target)) {