From: Bdale Garbee <bdale@gag.com>
Date: Sun, 6 Nov 2011 22:38:19 +0000 (-0800)
Subject: initial capture of work on a CNC board intended to be compatible with pluto-p
X-Git-Tag: fab-v0.1~36
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=5fd76e12410436843b6d35812e4374dfb0fc5b49;p=hw%2Fcncfpga

initial capture of work on a CNC board intended to be compatible with pluto-p
---

5fd76e12410436843b6d35812e4374dfb0fc5b49
diff --git a/Datasheets/altera/acex.pdf b/Datasheets/altera/acex.pdf
new file mode 100644
index 0000000..23387a9
Binary files /dev/null and b/Datasheets/altera/acex.pdf differ
diff --git a/Datasheets/altera/ep1k10.pdf b/Datasheets/altera/ep1k10.pdf
new file mode 100644
index 0000000..99c0c32
Binary files /dev/null and b/Datasheets/altera/ep1k10.pdf differ
diff --git a/Datasheets/altera/pkgds.pdf b/Datasheets/altera/pkgds.pdf
new file mode 100644
index 0000000..1a67d39
Binary files /dev/null and b/Datasheets/altera/pkgds.pdf differ
diff --git a/Datasheets/microchip/12F629.pdf b/Datasheets/microchip/12F629.pdf
new file mode 100644
index 0000000..dc66a2a
Binary files /dev/null and b/Datasheets/microchip/12F629.pdf differ
diff --git a/Datasheets/norcomp/182-YYY-213RYY1-1.pdf b/Datasheets/norcomp/182-YYY-213RYY1-1.pdf
new file mode 100644
index 0000000..97a5ca1
Binary files /dev/null and b/Datasheets/norcomp/182-YYY-213RYY1-1.pdf differ
diff --git a/Datasheets/norcomp/189-YYY-513R571.pdf b/Datasheets/norcomp/189-YYY-513R571.pdf
new file mode 100644
index 0000000..0dfc19f
Binary files /dev/null and b/Datasheets/norcomp/189-YYY-513R571.pdf differ
diff --git a/Datasheets/on/MC7800-D.PDF b/Datasheets/on/MC7800-D.PDF
new file mode 100644
index 0000000..e8967e0
Binary files /dev/null and b/Datasheets/on/MC7800-D.PDF differ
diff --git a/Datasheets/st/CD00000444.pdf b/Datasheets/st/CD00000444.pdf
new file mode 100644
index 0000000..4c73988
Binary files /dev/null and b/Datasheets/st/CD00000444.pdf differ
diff --git a/License.pdf b/License.pdf
new file mode 100644
index 0000000..01fceb2
Binary files /dev/null and b/License.pdf differ
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..886a234
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,35 @@
+# intentionally want to rebuild drc and bom on every invocation
+all:	drc partslist partslist.csv pcb
+
+drc:	cnc4pga.sch Makefile
+	-gnetlist -g drc2 cnc4pga.sch -o cnc4pga.drc
+
+partslist:	cnc4pga.sch Makefile
+	gnetlist -g bom -o cnc4pga.unsorted cnc4pga.sch
+	head -n1 cnc4pga.unsorted > partslist
+	tail -n+2 cnc4pga.unsorted | sort >> partslist
+	rm -f cnc4pga.unsorted
+
+partslist.csv:	cnc4pga.sch Makefile
+	gnetlist -g partslistgag -o cnc4pga.unsorted cnc4pga.sch
+	head -n1 cnc4pga.unsorted > partslist.csv
+	tail -n+2 cnc4pga.unsorted | sort -t \, -k 8 >> partslist.csv
+	rm -f cnc4pga.unsorted
+
+pcb:	cnc4pga.sch project Makefile
+	gsch2pcb project
+
+cnc4pga.xy:	cnc4pga.pcb
+	pcb -x bom cnc4pga.pcb
+
+cnc4pga.bottom.gbr:	cnc4pga.pcb
+	pcb -x gerber cnc4pga.pcb
+
+zip:	cnc4pga.bottom.gbr cnc4pga.bottommask.gbr cnc4pga.fab.gbr cnc4pga.top.gbr cnc4pga.topmask.gbr cnc4pga.toppaste.gbr cnc4pga.topsilk.gbr cnc4pga.group2.gbr cnc4pga.group3.gbr cnc4pga.plated-drill.cnc cnc4pga.xy  Makefile # cnc4pga.xls
+	zip cnc4pga.zip cnc4pga.*.gbr cnc4pga.*.cnc cnc4pga.xy # cnc4pga.xls
+
+clean:
+	rm -f *.bom *.drc *.log *~ cnc4pga.ps *.gbr *.cnc *bak* *- *.zip 
+	rm -f *.net *.xy *.cmd *.png partslist partslist.csv
+	rm -f *.partslist *.new.pcb *.unsorted cnc4pga.xls
+
diff --git a/attribs b/attribs
new file mode 100644
index 0000000..92a91e7
--- /dev/null
+++ b/attribs
@@ -0,0 +1,6 @@
+value
+vendor
+vendor_part_number
+footprint
+loadstatus
+device
diff --git a/cncfpga.pcb b/cncfpga.pcb
new file mode 100644
index 0000000..934f63b
--- /dev/null
+++ b/cncfpga.pcb
@@ -0,0 +1,1005 @@
+# release: pcb 1.99z
+
+# To read pcb files, the pcb version (or the git source date) must be >= the file version
+FileVersion[20070407]
+
+PCB["cncfpga" 600000 500000]
+
+Grid[100.0 0 0 0]
+Cursor[6900 33200 0.000000]
+PolyArea[200000000.000000]
+Thermal[0.500000]
+DRC[600 1000 600 500 1500 700]
+Flags("nameonpcb,snappin,liveroute")
+Groups("1,c:4,s:2:3:5")
+Styles["Signal,1000,3100,1500,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
+
+Symbol[' ' 1800]
+(
+)
+Symbol['!' 1200]
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+	SymbolLine[0 4500 0 5000 800]
+	SymbolLine[0 1000 0 3500 800]
+)
+Symbol['"' 1200]
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+	SymbolLine[0 1000 0 2000 800]
+	SymbolLine[1000 1000 1000 2000 800]
+)
+Symbol['#' 1200]
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+	SymbolLine[0 3500 2000 3500 800]
+	SymbolLine[0 2500 2000 2500 800]
+	SymbolLine[1500 2000 1500 4000 800]
+	SymbolLine[500 2000 500 4000 800]
+)
+Symbol['$' 1200]
+(
+	SymbolLine[1500 1500 2000 2000 800]
+	SymbolLine[500 1500 1500 1500 800]
+	SymbolLine[0 2000 500 1500 800]
+	SymbolLine[0 2000 0 2500 800]
+	SymbolLine[0 2500 500 3000 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[2000 3500 2000 4000 800]
+	SymbolLine[1500 4500 2000 4000 800]
+	SymbolLine[500 4500 1500 4500 800]
+	SymbolLine[0 4000 500 4500 800]
+	SymbolLine[1000 1000 1000 5000 800]
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+Symbol['%' 1200]
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+	SymbolLine[0 1500 0 2000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 1000 1000 800]
+	SymbolLine[1000 1000 1500 1500 800]
+	SymbolLine[1500 1500 1500 2000 800]
+	SymbolLine[1000 2500 1500 2000 800]
+	SymbolLine[500 2500 1000 2500 800]
+	SymbolLine[0 2000 500 2500 800]
+	SymbolLine[0 5000 4000 1000 800]
+	SymbolLine[3500 5000 4000 4500 800]
+	SymbolLine[4000 4000 4000 4500 800]
+	SymbolLine[3500 3500 4000 4000 800]
+	SymbolLine[3000 3500 3500 3500 800]
+	SymbolLine[2500 4000 3000 3500 800]
+	SymbolLine[2500 4000 2500 4500 800]
+	SymbolLine[2500 4500 3000 5000 800]
+	SymbolLine[3000 5000 3500 5000 800]
+)
+Symbol['&' 1200]
+(
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[0 1500 0 2500 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[0 3500 1500 2000 800]
+	SymbolLine[500 5000 1000 5000 800]
+	SymbolLine[1000 5000 2000 4000 800]
+	SymbolLine[0 2500 2500 5000 800]
+	SymbolLine[500 1000 1000 1000 800]
+	SymbolLine[1000 1000 1500 1500 800]
+	SymbolLine[1500 1500 1500 2000 800]
+	SymbolLine[0 3500 0 4500 800]
+)
+Symbol[''' 1200]
+(
+	SymbolLine[0 2000 1000 1000 800]
+)
+Symbol['(' 1200]
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+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[0 1500 0 4500 800]
+)
+Symbol[')' 1200]
+(
+	SymbolLine[0 1000 500 1500 800]
+	SymbolLine[500 1500 500 4500 800]
+	SymbolLine[0 5000 500 4500 800]
+)
+Symbol['*' 1200]
+(
+	SymbolLine[0 2000 2000 4000 800]
+	SymbolLine[0 4000 2000 2000 800]
+	SymbolLine[0 3000 2000 3000 800]
+	SymbolLine[1000 2000 1000 4000 800]
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+Symbol['+' 1200]
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+	SymbolLine[0 3000 2000 3000 800]
+	SymbolLine[1000 2000 1000 4000 800]
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+Symbol[',' 1200]
+(
+	SymbolLine[0 6000 1000 5000 800]
+)
+Symbol['-' 1200]
+(
+	SymbolLine[0 3000 2000 3000 800]
+)
+Symbol['.' 1200]
+(
+	SymbolLine[0 5000 500 5000 800]
+)
+Symbol['/' 1200]
+(
+	SymbolLine[0 4500 3000 1500 800]
+)
+Symbol['0' 1200]
+(
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[0 1500 0 4500 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 1500 1000 800]
+	SymbolLine[1500 1000 2000 1500 800]
+	SymbolLine[2000 1500 2000 4500 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[0 4000 2000 2000 800]
+)
+Symbol['1' 1200]
+(
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1000 1000 1000 5000 800]
+	SymbolLine[0 2000 1000 1000 800]
+)
+Symbol['2' 1200]
+(
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 2000 1000 800]
+	SymbolLine[2000 1000 2500 1500 800]
+	SymbolLine[2500 1500 2500 2500 800]
+	SymbolLine[0 5000 2500 2500 800]
+	SymbolLine[0 5000 2500 5000 800]
+)
+Symbol['3' 1200]
+(
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+	SymbolLine[500 1000 1500 1000 800]
+	SymbolLine[1500 1000 2000 1500 800]
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+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[0 4500 500 5000 800]
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+Symbol['4' 1200]
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+	SymbolLine[0 3000 2000 1000 800]
+	SymbolLine[0 3000 2500 3000 800]
+	SymbolLine[2000 1000 2000 5000 800]
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+Symbol['5' 1200]
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+	SymbolLine[0 1000 0 3000 800]
+	SymbolLine[0 3000 500 2500 800]
+	SymbolLine[500 2500 1500 2500 800]
+	SymbolLine[1500 2500 2000 3000 800]
+	SymbolLine[2000 3000 2000 4500 800]
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+	SymbolLine[500 5000 1500 5000 800]
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+Symbol['6' 1200]
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+	SymbolLine[500 1000 1500 1000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[0 1500 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[0 3000 1500 3000 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[2000 3500 2000 4500 800]
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+Symbol['7' 1200]
+(
+	SymbolLine[0 5000 2500 2500 800]
+	SymbolLine[2500 1000 2500 2500 800]
+	SymbolLine[0 1000 2500 1000 800]
+)
+Symbol['8' 1200]
+(
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+	SymbolLine[0 3500 0 4500 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[500 3000 1500 3000 800]
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+	SymbolLine[500 5000 1500 5000 800]
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+	SymbolLine[500 1000 1500 1000 800]
+	SymbolLine[1500 1000 2000 1500 800]
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+Symbol['9' 1200]
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+	SymbolLine[500 1000 1500 1000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[0 1500 0 2500 800]
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+	SymbolLine[500 3000 2000 3000 800]
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+Symbol[':' 1200]
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+	SymbolLine[0 3500 500 3500 800]
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+Symbol[';' 1200]
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+	SymbolLine[0 5000 1000 4000 800]
+	SymbolLine[1000 2500 1000 3000 800]
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+Symbol['<' 1200]
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+	SymbolLine[0 3000 1000 2000 800]
+	SymbolLine[0 3000 1000 4000 800]
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+Symbol['=' 1200]
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+	SymbolLine[0 3500 2000 3500 800]
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+Symbol['>' 1200]
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+	SymbolLine[0 4000 1000 3000 800]
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+Symbol['?' 1200]
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+	SymbolLine[1000 4500 1000 5000 800]
+	SymbolLine[0 1500 0 2000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 1500 1000 800]
+	SymbolLine[1500 1000 2000 1500 800]
+	SymbolLine[2000 1500 2000 2000 800]
+	SymbolLine[1000 3000 2000 2000 800]
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+	SymbolLine[0 4000 1000 5000 800]
+	SymbolLine[1000 5000 4000 5000 800]
+	SymbolLine[5000 3500 5000 1000 800]
+	SymbolLine[5000 1000 4000 0 800]
+	SymbolLine[4000 0 1000 0 800]
+	SymbolLine[1000 0 0 1000 800]
+	SymbolLine[1500 2000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[2000 3500 3000 3500 800]
+	SymbolLine[3000 3500 3500 3000 800]
+	SymbolLine[3500 3000 4000 3500 800]
+	SymbolLine[3500 3000 3500 1500 800]
+	SymbolLine[3500 2000 3000 1500 800]
+	SymbolLine[2000 1500 3000 1500 800]
+	SymbolLine[2000 1500 1500 2000 800]
+	SymbolLine[4000 3500 5000 3500 800]
+)
+Symbol['A' 1200]
+(
+	SymbolLine[0 1500 0 5000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 2000 1000 800]
+	SymbolLine[2000 1000 2500 1500 800]
+	SymbolLine[2500 1500 2500 5000 800]
+	SymbolLine[0 3000 2500 3000 800]
+)
+Symbol['B' 1200]
+(
+	SymbolLine[0 5000 2000 5000 800]
+	SymbolLine[2000 5000 2500 4500 800]
+	SymbolLine[2500 3500 2500 4500 800]
+	SymbolLine[2000 3000 2500 3500 800]
+	SymbolLine[500 3000 2000 3000 800]
+	SymbolLine[500 1000 500 5000 800]
+	SymbolLine[0 1000 2000 1000 800]
+	SymbolLine[2000 1000 2500 1500 800]
+	SymbolLine[2500 1500 2500 2500 800]
+	SymbolLine[2000 3000 2500 2500 800]
+)
+Symbol['C' 1200]
+(
+	SymbolLine[500 5000 2000 5000 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[0 1500 0 4500 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 2000 1000 800]
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+Symbol['D' 1200]
+(
+	SymbolLine[500 1000 500 5000 800]
+	SymbolLine[2000 1000 2500 1500 800]
+	SymbolLine[2500 1500 2500 4500 800]
+	SymbolLine[2000 5000 2500 4500 800]
+	SymbolLine[0 5000 2000 5000 800]
+	SymbolLine[0 1000 2000 1000 800]
+)
+Symbol['E' 1200]
+(
+	SymbolLine[0 3000 1500 3000 800]
+	SymbolLine[0 5000 2000 5000 800]
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 1000 2000 1000 800]
+)
+Symbol['F' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 1000 2000 1000 800]
+	SymbolLine[0 3000 1500 3000 800]
+)
+Symbol['G' 1200]
+(
+	SymbolLine[2000 1000 2500 1500 800]
+	SymbolLine[500 1000 2000 1000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[0 1500 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 2000 5000 800]
+	SymbolLine[2000 5000 2500 4500 800]
+	SymbolLine[2500 3500 2500 4500 800]
+	SymbolLine[2000 3000 2500 3500 800]
+	SymbolLine[1000 3000 2000 3000 800]
+)
+Symbol['H' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[2500 1000 2500 5000 800]
+	SymbolLine[0 3000 2500 3000 800]
+)
+Symbol['I' 1200]
+(
+	SymbolLine[0 1000 1000 1000 800]
+	SymbolLine[500 1000 500 5000 800]
+	SymbolLine[0 5000 1000 5000 800]
+)
+Symbol['J' 1200]
+(
+	SymbolLine[0 1000 1500 1000 800]
+	SymbolLine[1500 1000 1500 4500 800]
+	SymbolLine[1000 5000 1500 4500 800]
+	SymbolLine[500 5000 1000 5000 800]
+	SymbolLine[0 4500 500 5000 800]
+)
+Symbol['K' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 3000 2000 1000 800]
+	SymbolLine[0 3000 2000 5000 800]
+)
+Symbol['L' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 5000 2000 5000 800]
+)
+Symbol['M' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 1000 1500 2500 800]
+	SymbolLine[1500 2500 3000 1000 800]
+	SymbolLine[3000 1000 3000 5000 800]
+)
+Symbol['N' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 1000 0 1500 800]
+	SymbolLine[0 1500 2500 4000 800]
+	SymbolLine[2500 1000 2500 5000 800]
+)
+Symbol['O' 1200]
+(
+	SymbolLine[0 1500 0 4500 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 1500 1000 800]
+	SymbolLine[1500 1000 2000 1500 800]
+	SymbolLine[2000 1500 2000 4500 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[0 4500 500 5000 800]
+)
+Symbol['P' 1200]
+(
+	SymbolLine[500 1000 500 5000 800]
+	SymbolLine[0 1000 2000 1000 800]
+	SymbolLine[2000 1000 2500 1500 800]
+	SymbolLine[2500 1500 2500 2500 800]
+	SymbolLine[2000 3000 2500 2500 800]
+	SymbolLine[500 3000 2000 3000 800]
+)
+Symbol['Q' 1200]
+(
+	SymbolLine[0 1500 0 4500 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 1500 1000 800]
+	SymbolLine[1500 1000 2000 1500 800]
+	SymbolLine[2000 1500 2000 4500 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[1000 4000 2000 5000 800]
+)
+Symbol['R' 1200]
+(
+	SymbolLine[0 1000 2000 1000 800]
+	SymbolLine[2000 1000 2500 1500 800]
+	SymbolLine[2500 1500 2500 2500 800]
+	SymbolLine[2000 3000 2500 2500 800]
+	SymbolLine[500 3000 2000 3000 800]
+	SymbolLine[500 1000 500 5000 800]
+	SymbolLine[500 3000 2500 5000 800]
+)
+Symbol['S' 1200]
+(
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+	SymbolLine[500 1000 2000 1000 800]
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[0 1500 0 2500 800]
+	SymbolLine[0 2500 500 3000 800]
+	SymbolLine[500 3000 2000 3000 800]
+	SymbolLine[2000 3000 2500 3500 800]
+	SymbolLine[2500 3500 2500 4500 800]
+	SymbolLine[2000 5000 2500 4500 800]
+	SymbolLine[500 5000 2000 5000 800]
+	SymbolLine[0 4500 500 5000 800]
+)
+Symbol['T' 1200]
+(
+	SymbolLine[0 1000 2000 1000 800]
+	SymbolLine[1000 1000 1000 5000 800]
+)
+Symbol['U' 1200]
+(
+	SymbolLine[0 1000 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[2000 1000 2000 4500 800]
+)
+Symbol['V' 1200]
+(
+	SymbolLine[0 1000 0 4000 800]
+	SymbolLine[0 4000 1000 5000 800]
+	SymbolLine[1000 5000 2000 4000 800]
+	SymbolLine[2000 1000 2000 4000 800]
+)
+Symbol['W' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 5000 1500 3500 800]
+	SymbolLine[1500 3500 3000 5000 800]
+	SymbolLine[3000 1000 3000 5000 800]
+)
+Symbol['X' 1200]
+(
+	SymbolLine[0 1000 0 1500 800]
+	SymbolLine[0 1500 2500 4000 800]
+	SymbolLine[2500 4000 2500 5000 800]
+	SymbolLine[0 4000 0 5000 800]
+	SymbolLine[0 4000 2500 1500 800]
+	SymbolLine[2500 1000 2500 1500 800]
+)
+Symbol['Y' 1200]
+(
+	SymbolLine[0 1000 0 1500 800]
+	SymbolLine[0 1500 1000 2500 800]
+	SymbolLine[1000 2500 2000 1500 800]
+	SymbolLine[2000 1000 2000 1500 800]
+	SymbolLine[1000 2500 1000 5000 800]
+)
+Symbol['Z' 1200]
+(
+	SymbolLine[0 1000 2500 1000 800]
+	SymbolLine[2500 1000 2500 1500 800]
+	SymbolLine[0 4000 2500 1500 800]
+	SymbolLine[0 4000 0 5000 800]
+	SymbolLine[0 5000 2500 5000 800]
+)
+Symbol['[' 1200]
+(
+	SymbolLine[0 1000 500 1000 800]
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 5000 500 5000 800]
+)
+Symbol['\' 1200]
+(
+	SymbolLine[0 1500 3000 4500 800]
+)
+Symbol[']' 1200]
+(
+	SymbolLine[0 1000 500 1000 800]
+	SymbolLine[500 1000 500 5000 800]
+	SymbolLine[0 5000 500 5000 800]
+)
+Symbol['^' 1200]
+(
+	SymbolLine[0 1500 500 1000 800]
+	SymbolLine[500 1000 1000 1500 800]
+)
+Symbol['_' 1200]
+(
+	SymbolLine[0 5000 2000 5000 800]
+)
+Symbol['`' 1200]
+(
+	SymbolLine[5000 0 6500 1500 800]
+	SymbolLine[6500 5000 5000 6500 800]
+	SymbolLine[5000 6500 1500 6500 800]
+	SymbolLine[1500 6500 0 5000 800]
+	SymbolLine[0 5000 0 1500 800]
+	SymbolLine[0 1500 1500 0 800]
+	SymbolLine[1500 0 5000 0 800]
+	SymbolLine[6500 1500 6500 5000 800]
+	SymbolLine[2500 2500 4000 2500 800]
+	SymbolLine[2000 3000 2500 2500 800]
+	SymbolLine[2000 3000 2000 4000 800]
+	SymbolLine[2000 4000 2500 4500 800]
+	SymbolLine[2500 4500 4000 4500 800]
+)
+Symbol['a' 1200]
+(
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[0 3500 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[2000 3000 2000 4500 800]
+	SymbolLine[2000 4500 2500 5000 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+)
+Symbol['b' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[2000 3500 2000 4500 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[0 3500 500 3000 800]
+)
+Symbol['c' 1200]
+(
+	SymbolLine[500 3000 2000 3000 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[0 3500 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 2000 5000 800]
+)
+Symbol['d' 1200]
+(
+	SymbolLine[2000 1000 2000 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[0 3500 0 4500 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+)
+Symbol['e' 1200]
+(
+	SymbolLine[500 5000 2000 5000 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[0 3500 0 4500 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[0 4000 2000 4000 800]
+	SymbolLine[2000 4000 2000 3500 800]
+)
+Symbol['f' 1000]
+(
+	SymbolLine[500 1500 500 5000 800]
+	SymbolLine[500 1500 1000 1000 800]
+	SymbolLine[1000 1000 1500 1000 800]
+	SymbolLine[0 3000 1000 3000 800]
+)
+Symbol['g' 1200]
+(
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[0 3500 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[0 6000 500 6500 800]
+	SymbolLine[500 6500 1500 6500 800]
+	SymbolLine[1500 6500 2000 6000 800]
+	SymbolLine[2000 3000 2000 6000 800]
+)
+Symbol['h' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[2000 3500 2000 5000 800]
+)
+Symbol['i' 1000]
+(
+	SymbolLine[0 2000 0 2500 800]
+	SymbolLine[0 3500 0 5000 800]
+)
+Symbol['j' 1000]
+(
+	SymbolLine[500 2000 500 2500 800]
+	SymbolLine[500 3500 500 6000 800]
+	SymbolLine[0 6500 500 6000 800]
+)
+Symbol['k' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+	SymbolLine[0 3500 1500 5000 800]
+	SymbolLine[0 3500 1000 2500 800]
+)
+Symbol['l' 1000]
+(
+	SymbolLine[0 1000 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+)
+Symbol['m' 1200]
+(
+	SymbolLine[500 3500 500 5000 800]
+	SymbolLine[500 3500 1000 3000 800]
+	SymbolLine[1000 3000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[2000 3500 2000 5000 800]
+	SymbolLine[2000 3500 2500 3000 800]
+	SymbolLine[2500 3000 3000 3000 800]
+	SymbolLine[3000 3000 3500 3500 800]
+	SymbolLine[3500 3500 3500 5000 800]
+	SymbolLine[0 3000 500 3500 800]
+)
+Symbol['n' 1200]
+(
+	SymbolLine[500 3500 500 5000 800]
+	SymbolLine[500 3500 1000 3000 800]
+	SymbolLine[1000 3000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[2000 3500 2000 5000 800]
+	SymbolLine[0 3000 500 3500 800]
+)
+Symbol['o' 1200]
+(
+	SymbolLine[0 3500 0 4500 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[2000 3500 2000 4500 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[0 4500 500 5000 800]
+)
+Symbol['p' 1200]
+(
+	SymbolLine[500 3500 500 6500 800]
+	SymbolLine[0 3000 500 3500 800]
+	SymbolLine[500 3500 1000 3000 800]
+	SymbolLine[1000 3000 2000 3000 800]
+	SymbolLine[2000 3000 2500 3500 800]
+	SymbolLine[2500 3500 2500 4500 800]
+	SymbolLine[2000 5000 2500 4500 800]
+	SymbolLine[1000 5000 2000 5000 800]
+	SymbolLine[500 4500 1000 5000 800]
+)
+Symbol['q' 1200]
+(
+	SymbolLine[2000 3500 2000 6500 800]
+	SymbolLine[1500 3000 2000 3500 800]
+	SymbolLine[500 3000 1500 3000 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[0 3500 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+)
+Symbol['r' 1200]
+(
+	SymbolLine[500 3500 500 5000 800]
+	SymbolLine[500 3500 1000 3000 800]
+	SymbolLine[1000 3000 2000 3000 800]
+	SymbolLine[0 3000 500 3500 800]
+)
+Symbol['s' 1200]
+(
+	SymbolLine[500 5000 2000 5000 800]
+	SymbolLine[2000 5000 2500 4500 800]
+	SymbolLine[2000 4000 2500 4500 800]
+	SymbolLine[500 4000 2000 4000 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[500 3000 2000 3000 800]
+	SymbolLine[2000 3000 2500 3500 800]
+	SymbolLine[0 4500 500 5000 800]
+)
+Symbol['t' 1000]
+(
+	SymbolLine[500 1000 500 4500 800]
+	SymbolLine[500 4500 1000 5000 800]
+	SymbolLine[0 2500 1000 2500 800]
+)
+Symbol['u' 1200]
+(
+	SymbolLine[0 3000 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[2000 3000 2000 4500 800]
+)
+Symbol['v' 1200]
+(
+	SymbolLine[0 3000 0 4000 800]
+	SymbolLine[0 4000 1000 5000 800]
+	SymbolLine[1000 5000 2000 4000 800]
+	SymbolLine[2000 3000 2000 4000 800]
+)
+Symbol['w' 1200]
+(
+	SymbolLine[0 3000 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 1000 5000 800]
+	SymbolLine[1000 5000 1500 4500 800]
+	SymbolLine[1500 3000 1500 4500 800]
+	SymbolLine[1500 4500 2000 5000 800]
+	SymbolLine[2000 5000 2500 5000 800]
+	SymbolLine[2500 5000 3000 4500 800]
+	SymbolLine[3000 3000 3000 4500 800]
+)
+Symbol['x' 1200]
+(
+	SymbolLine[0 3000 2000 5000 800]
+	SymbolLine[0 5000 2000 3000 800]
+)
+Symbol['y' 1200]
+(
+	SymbolLine[0 3000 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[2000 3000 2000 6000 800]
+	SymbolLine[1500 6500 2000 6000 800]
+	SymbolLine[500 6500 1500 6500 800]
+	SymbolLine[0 6000 500 6500 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+)
+Symbol['z' 1200]
+(
+	SymbolLine[0 3000 2000 3000 800]
+	SymbolLine[0 5000 2000 3000 800]
+	SymbolLine[0 5000 2000 5000 800]
+)
+Symbol['{' 1200]
+(
+	SymbolLine[500 1500 1000 1000 800]
+	SymbolLine[500 1500 500 2500 800]
+	SymbolLine[0 3000 500 2500 800]
+	SymbolLine[0 3000 500 3500 800]
+	SymbolLine[500 3500 500 4500 800]
+	SymbolLine[500 4500 1000 5000 800]
+)
+Symbol['|' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+)
+Symbol['}' 1200]
+(
+	SymbolLine[0 1000 500 1500 800]
+	SymbolLine[500 1500 500 2500 800]
+	SymbolLine[500 2500 1000 3000 800]
+	SymbolLine[500 3500 1000 3000 800]
+	SymbolLine[500 3500 500 4500 800]
+	SymbolLine[0 5000 500 4500 800]
+)
+Symbol['~' 1200]
+(
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[500 3000 1000 3000 800]
+	SymbolLine[1000 3000 1500 3500 800]
+	SymbolLine[1500 3500 2000 3500 800]
+	SymbolLine[2000 3500 2500 3000 800]
+)
+Attribute("PCB::grid::unit" "mil")
+
+Element["hidename,lock" "hole-fox-stack" "H4" "unknown" 342520 342520 -16900 -21000 0 100 ""]
+(
+	Pin[0 0 25197 0 32000 12500 "pin1" "1" "usetherm,thermal(1S)"]
+
+	)
+
+Element["hidename,lock" "hole-fox-stack" "H3" "unknown" 31495 342520 -16900 -21000 0 100 ""]
+(
+	Pin[0 0 25197 0 32000 12500 "pin1" "1" "usetherm,thermal(1S)"]
+
+	)
+
+Element["hidename,lock" "hole-fox-stack" "H2" "unknown" 342520 31495 -16900 -21000 0 100 ""]
+(
+	Pin[0 0 25197 0 32000 12500 "pin1" "1" "usetherm,thermal(1S)"]
+
+	)
+
+Element["hidename,lock" "hole-fox-stack" "H1" "unknown" 31495 31495 -16900 -21000 0 100 ""]
+(
+	Pin[0 0 25197 0 32000 12500 "pin1" "1" "usetherm,thermal(1S)"]
+
+	)
+
+Element["lock" "BTE-020-02" "J2" "BTE-020" 340551 126772 12011 -10161 3 100 ""]
+(
+	Pin[7999 36372 4000 0 4000 4000 "mnt" "0" "hole"]
+	Pin[7999 -36371 4000 0 4000 4000 "mnt" "0" "hole"]
+	Pad[10198 -29920 14099 -29920 1799 1350 2399 "pin1" "1" "square,edge2"]
+	Pad[-14100 -29920 -10199 -29920 1799 1350 2399 "pin2" "2" "square"]
+	Pad[10198 -26771 14099 -26771 1799 1350 2399 "pin3" "3" "square,edge2"]
+	Pad[-14100 -26771 -10199 -26771 1799 1350 2399 "pin4" "4" "square"]
+	Pad[10198 -23621 14099 -23621 1799 1350 2399 "pin5" "5" "square,edge2"]
+	Pad[-14100 -23621 -10199 -23621 1799 1350 2399 "pin6" "6" "square"]
+	Pad[10198 -20471 14099 -20471 1799 1350 2399 "pin7" "7" "square,edge2"]
+	Pad[-14100 -20471 -10199 -20471 1799 1350 2399 "pin8" "8" "square"]
+	Pad[10198 -17322 14099 -17322 1799 1350 2399 "pin9" "9" "square,edge2"]
+	Pad[-14100 -17322 -10199 -17322 1799 1350 2399 "pin10" "10" "square"]
+	Pad[10198 -14172 14099 -14172 1799 1350 2399 "pin11" "11" "square,edge2"]
+	Pad[-14100 -14172 -10199 -14172 1799 1350 2399 "pin12" "12" "square"]
+	Pad[10198 -11023 14099 -11023 1799 1350 2399 "pin13" "13" "square,edge2"]
+	Pad[-14100 -11023 -10199 -11023 1799 1350 2399 "pin14" "14" "square"]
+	Pad[10198 -7873 14099 -7873 1799 1350 2399 "pin15" "15" "square,edge2"]
+	Pad[-14100 -7873 -10199 -7873 1799 1350 2399 "pin16" "16" "square"]
+	Pad[10198 -4723 14099 -4723 1799 1350 2399 "pin17" "17" "square,edge2"]
+	Pad[-14100 -4723 -10199 -4723 1799 1350 2399 "pin18" "18" "square"]
+	Pad[10198 -1574 14099 -1574 1799 1350 2399 "pin19" "19" "square,edge2"]
+	Pad[-14100 -1574 -10199 -1574 1799 1350 2399 "pin20" "20" "square"]
+	Pad[10198 1575 14099 1575 1799 1350 2399 "pin21" "21" "square,edge2"]
+	Pad[-14100 1575 -10199 1575 1799 1350 2399 "pin22" "22" "square"]
+	Pad[10198 4724 14099 4724 1799 1350 2399 "pin23" "23" "square,edge2"]
+	Pad[-14100 4724 -10199 4724 1799 1350 2399 "pin24" "24" "square"]
+	Pad[10198 7874 14099 7874 1799 1350 2399 "pin25" "25" "square,edge2"]
+	Pad[-14100 7874 -10199 7874 1799 1350 2399 "pin26" "26" "square"]
+	Pad[10198 11024 14099 11024 1799 1350 2399 "pin27" "27" "square,edge2"]
+	Pad[-14100 11024 -10199 11024 1799 1350 2399 "pin28" "28" "square"]
+	Pad[10198 14173 14099 14173 1799 1350 2399 "pin29" "29" "square,edge2"]
+	Pad[-14100 14173 -10199 14173 1799 1350 2399 "pin30" "30" "square"]
+	Pad[10198 17323 14099 17323 1799 1350 2399 "pin31" "31" "square,edge2"]
+	Pad[-14100 17323 -10199 17323 1799 1350 2399 "pin32" "32" "square"]
+	Pad[10198 20472 14099 20472 1799 1350 2399 "pin33" "33" "square,edge2"]
+	Pad[-14100 20472 -10199 20472 1799 1350 2399 "pin34" "34" "square"]
+	Pad[10198 23622 14099 23622 1799 1350 2399 "pin35" "35" "square,edge2"]
+	Pad[-14100 23622 -10199 23622 1799 1350 2399 "pin36" "36" "square"]
+	Pad[10198 26772 14099 26772 1799 1350 2399 "pin37" "37" "square,edge2"]
+	Pad[-14100 26772 -10199 26772 1799 1350 2399 "pin38" "38" "square"]
+	Pad[10198 29921 14099 29921 1799 1350 2399 "pin39" "39" "square,edge2"]
+	Pad[-14100 29921 -10199 29921 1799 1350 2399 "pin40" "40" "square"]
+	ElementLine [-11752 -39369 11751 -39369 1000]
+	ElementLine [-11752 -39369 -11752 39370 1000]
+	ElementLine [-11752 39370 11751 39370 1000]
+	ElementLine [11751 -39369 11751 39370 1000]
+	ElementArc [16424 -33070 500 500 270 360 1000]
+
+	)
+
+Element["onsolder,lock" "BSE-020-01" "J1" "BSE-020" 340551 126772 -12011 -10161 1 100 "auto"]
+(
+	Pin[-10511 39620 4000 0 4000 4000 "mnt" "0" "hole"]
+	Pin[-10511 -39619 4000 0 4000 4000 "mnt" "0" "hole"]
+	Pad[-14950 -29920 -7599 -29920 1598 1551 2198 "pin2" "2" "onsolder,square"]
+	Pad[7600 -29920 14951 -29920 1598 1551 2198 "pin1" "1" "onsolder,square,edge2"]
+	Pad[-14950 -26771 -7599 -26771 1598 1551 2198 "pin4" "4" "onsolder,square"]
+	Pad[7600 -26771 14951 -26771 1598 1551 2198 "pin3" "3" "onsolder,square,edge2"]
+	Pad[-14950 -23621 -7599 -23621 1598 1551 2198 "pin6" "6" "onsolder,square"]
+	Pad[7600 -23621 14951 -23621 1598 1551 2198 "pin5" "5" "onsolder,square,edge2"]
+	Pad[-14950 -20471 -7599 -20471 1598 1551 2198 "pin8" "8" "onsolder,square"]
+	Pad[7600 -20471 14951 -20471 1598 1551 2198 "pin7" "7" "onsolder,square,edge2"]
+	Pad[-14950 -17322 -7599 -17322 1598 1551 2198 "pin10" "10" "onsolder,square"]
+	Pad[7600 -17322 14951 -17322 1598 1551 2198 "pin9" "9" "onsolder,square,edge2"]
+	Pad[-14950 -14172 -7599 -14172 1598 1551 2198 "pin12" "12" "onsolder,square"]
+	Pad[7600 -14172 14951 -14172 1598 1551 2198 "pin11" "11" "onsolder,square,edge2"]
+	Pad[-14950 -11023 -7599 -11023 1598 1551 2198 "pin14" "14" "onsolder,square"]
+	Pad[7600 -11023 14951 -11023 1598 1551 2198 "pin13" "13" "onsolder,square,edge2"]
+	Pad[-14950 -7873 -7599 -7873 1598 1551 2198 "pin16" "16" "onsolder,square"]
+	Pad[7600 -7873 14951 -7873 1598 1551 2198 "pin15" "15" "onsolder,square,edge2"]
+	Pad[-14950 -4723 -7599 -4723 1598 1551 2198 "pin18" "18" "onsolder,square"]
+	Pad[7600 -4723 14951 -4723 1598 1551 2198 "pin17" "17" "onsolder,square,edge2"]
+	Pad[-14950 -1574 -7599 -1574 1598 1551 2198 "pin20" "20" "onsolder,square"]
+	Pad[7600 -1574 14951 -1574 1598 1551 2198 "pin19" "19" "onsolder,square,edge2"]
+	Pad[-14950 1575 -7599 1575 1598 1551 2198 "pin22" "22" "onsolder,square"]
+	Pad[7600 1575 14951 1575 1598 1551 2198 "pin21" "21" "onsolder,square,edge2"]
+	Pad[-14950 4724 -7599 4724 1598 1551 2198 "pin24" "24" "onsolder,square"]
+	Pad[7600 4724 14951 4724 1598 1551 2198 "pin23" "23" "onsolder,square,edge2"]
+	Pad[-14950 7874 -7599 7874 1598 1551 2198 "pin26" "26" "onsolder,square"]
+	Pad[7600 7874 14951 7874 1598 1551 2198 "pin25" "25" "onsolder,square,edge2"]
+	Pad[-14950 11024 -7599 11024 1598 1551 2198 "pin28" "28" "onsolder,square"]
+	Pad[7600 11024 14951 11024 1598 1551 2198 "pin27" "27" "onsolder,square,edge2"]
+	Pad[-14950 14173 -7599 14173 1598 1551 2198 "pin30" "30" "onsolder,square"]
+	Pad[7600 14173 14951 14173 1598 1551 2198 "pin29" "29" "onsolder,square,edge2"]
+	Pad[-14950 17323 -7599 17323 1598 1551 2198 "pin32" "32" "onsolder,square"]
+	Pad[7600 17323 14951 17323 1598 1551 2198 "pin31" "31" "onsolder,square,edge2"]
+	Pad[-14950 20472 -7599 20472 1598 1551 2198 "pin34" "34" "onsolder,square"]
+	Pad[7600 20472 14951 20472 1598 1551 2198 "pin33" "33" "onsolder,square,edge2"]
+	Pad[-14950 23622 -7599 23622 1598 1551 2198 "pin36" "36" "onsolder,square"]
+	Pad[7600 23622 14951 23622 1598 1551 2198 "pin35" "35" "onsolder,square,edge2"]
+	Pad[-14950 26772 -7599 26772 1598 1551 2198 "pin38" "38" "onsolder,square"]
+	Pad[7600 26772 14951 26772 1598 1551 2198 "pin37" "37" "onsolder,square,edge2"]
+	Pad[-14950 29921 -7599 29921 1598 1551 2198 "pin40" "40" "onsolder,square"]
+	Pad[7600 29921 14951 29921 1598 1551 2198 "pin39" "39" "onsolder,square,edge2"]
+	ElementLine [-14251 -41869 14252 -41869 1000]
+	ElementLine [14252 -41869 14252 41870 1000]
+	ElementLine [-14251 41870 14252 41870 1000]
+	ElementLine [-14251 -41869 -14251 41870 1000]
+	ElementArc [17987 -33070 500 500 270 360 1000]
+
+	)
+Layer(1 "top")
+(
+)
+Layer(2 "GND plane")
+(
+	Polygon("clearpoly,lock")
+	(
+		[1300 32000] [32000 1300] [342000 1300] [372700 32000] [372700 342000] 
+		[342000 372700] [32000 372700] [1300 342000] 
+	)
+)
+Layer(3 "power plane")
+(
+	Polygon("clearpoly,lock")
+	(
+		[1300 32000] [32000 1300] [342000 1300] [372700 32000] [372700 342000] 
+		[342000 372700] [32000 372700] [1300 342000] 
+	)
+)
+Layer(4 "bottom")
+(
+)
+Layer(5 "outline")
+(
+	Attribute("PCB::skip-drc" "1")
+	Line[31496 0 342520 0 1000 2000 "lock"]
+	Line[342520 0 374016 31496 1000 2000 "lock"]
+	Line[374016 31496 374016 342520 1000 2000 "lock"]
+	Line[374016 342520 342520 374016 1000 2000 "lock"]
+	Line[342520 374016 31496 374016 1000 2000 "lock"]
+	Line[31496 374016 0 342520 1000 2000 "lock"]
+	Line[0 342520 0 31496 1000 2000 "lock"]
+	Line[0 31496 31496 0 1000 2000 "lock"]
+)
+Layer(6 "silk")
+(
+)
+Layer(7 "silk")
+(
+	Line[1968 64960 31496 64960 1000 2000 ""]
+	Line[31496 64960 64960 31496 1000 2000 ""]
+	Line[64960 31496 64960 1968 1000 2000 ""]
+	Line[309052 1968 309052 31496 1000 2000 ""]
+	Line[309052 31496 342516 64960 1000 2000 ""]
+	Line[342516 64960 372044 64960 1000 2000 ""]
+	Line[1968 309052 31496 309052 1000 2000 ""]
+	Line[31496 309052 64960 342516 1000 2000 ""]
+	Line[64960 342516 64960 372044 1000 2000 ""]
+	Line[309052 372044 309052 342516 1000 2000 ""]
+	Line[309052 342516 342516 309052 1000 2000 ""]
+	Line[342516 309052 372044 309052 1000 2000 ""]
+	Text[117220 349125 0 200 "AMSAT-NA Fox-1 IHU v0.1" ""]
+	Text[78313 364079 0 100 "` 2011 Bdale Garbee KB0G   License TAPR OHL (http://www.tapr.org/OHL)" ""]
+)
+NetList()
+(
+	Net("GND" "(unknown)")
+	(
+		Connect("H1-1")
+		Connect("H2-1")
+		Connect("H3-1")
+		Connect("H4-1")
+	)
+)
diff --git a/cncfpga.sch b/cncfpga.sch
new file mode 100644
index 0000000..9a47575
--- /dev/null
+++ b/cncfpga.sch
@@ -0,0 +1,245 @@
+v 20110115 2
+C 40000 40000 0 0 0 title-D-bdale.sym
+T 67900 41800 9 30 1 0 0 0 1
+CNC FPGA Board
+T 72400 40400 9 10 1 0 0 0 1
+0.1
+T 70000 40400 9 10 1 0 0 0 1
+1
+T 70600 40400 9 10 1 0 0 0 1
+1
+T 67700 40400 9 10 1 0 0 0 1
+cncfpga.sch
+T 67700 40100 9 10 1 0 0 0 1
+http://gag.com
+C 72200 46400 1 0 0 hole_plated.sym
+{
+T 72300 48200 5 10 0 0 0 0 1
+device=HOLE_PLATED
+T 71800 46600 5 10 1 1 0 0 1
+refdes=H1
+T 72200 46400 5 10 0 0 0 0 1
+footprint=hole-fox-stack
+T 72200 46400 5 10 0 1 0 0 1
+loadstatus=noload
+T 72200 46400 5 10 0 0 0 0 1
+vendor=none
+T 72200 46400 5 10 0 1 0 0 1
+nobom=1
+}
+T 71800 47000 9 10 1 0 0 0 1
+mounting holes
+C 73300 43100 1 0 0 gnd.sym
+N 72800 45600 73400 45600 4
+N 72800 46600 73400 46600 4
+N 73400 43400 73400 46600 4
+C 72200 45400 1 0 0 hole_plated.sym
+{
+T 72300 47200 5 10 0 0 0 0 1
+device=HOLE_PLATED
+T 71800 45600 5 10 1 1 0 0 1
+refdes=H2
+T 72200 45400 5 10 0 0 0 0 1
+footprint=hole-fox-stack
+T 72200 45400 5 10 0 1 0 0 1
+loadstatus=noload
+T 72200 45400 5 10 0 1 0 0 1
+vendor=none
+T 72200 45400 5 10 0 1 0 0 1
+nobom=1
+}
+C 72200 44500 1 0 0 hole_plated.sym
+{
+T 72300 46300 5 10 0 0 0 0 1
+device=HOLE_PLATED
+T 71800 44700 5 10 1 1 0 0 1
+refdes=H3
+T 72200 44500 5 10 0 0 0 0 1
+footprint=hole-fox-stack
+T 72200 44500 5 10 0 1 0 0 1
+loadstatus=noload
+T 72200 44500 5 10 0 1 0 0 1
+vendor=none
+T 72200 44500 5 10 0 1 0 0 1
+nobom=1
+}
+C 72200 43500 1 0 0 hole_plated.sym
+{
+T 72300 45300 5 10 0 0 0 0 1
+device=HOLE_PLATED
+T 71800 43700 5 10 1 1 0 0 1
+refdes=H4
+T 72200 43500 5 10 0 0 0 0 1
+footprint=hole-fox-stack
+T 72200 43500 5 10 0 1 0 0 1
+loadstatus=noload
+T 72200 43500 5 10 0 1 0 0 1
+vendor=none
+T 72200 43500 5 10 0 1 0 0 1
+nobom=1
+}
+N 72800 44700 73400 44700 4
+N 72800 43700 73400 43700 4
+C 49600 41700 1 0 0 EP1K10.sym
+{
+T 43200 40100 5 10 0 0 0 0 1
+device=EP1K10TC100
+T 50200 60100 5 10 1 1 180 0 1
+refdes=U?
+}
+C 53200 41200 1 0 0 gnd.sym
+N 51700 41600 54900 41600 4
+N 51700 41700 51700 41600 4
+N 52100 41700 52100 41600 4
+N 52500 41700 52500 41600 4
+N 52900 41700 52900 41600 4
+N 53300 41700 53300 41600 4
+N 53300 41600 53300 41500 4
+N 53700 41700 53700 41600 4
+N 54100 41700 54100 41600 4
+N 54500 41700 54500 41600 4
+N 54900 41700 54900 41600 4
+C 41500 42700 1 0 0 conn-25.sym
+{
+T 41755 52595 5 10 1 1 0 0 1
+refdes=J?
+}
+C 63300 51000 1 0 0 conn-15.sym
+{
+T 63655 56895 5 10 1 1 0 0 1
+refdes=J?
+}
+C 65000 51000 1 0 0 conn-15.sym
+{
+T 65355 56895 5 10 1 1 0 0 1
+refdes=J?
+}
+C 66900 51000 1 0 0 conn-15.sym
+{
+T 67255 56895 5 10 1 1 0 0 1
+refdes=J?
+}
+C 68800 51000 1 0 0 conn-15.sym
+{
+T 69155 56895 5 10 1 1 0 0 1
+refdes=J?
+}
+C 67600 45200 1 0 0 conn-9.sym
+{
+T 67955 48695 5 10 1 1 0 0 1
+refdes=J?
+}
+C 59800 46100 1 0 0 PIC12F629.sym
+{
+T 60200 48100 5 10 1 1 0 0 1
+refdes=U?
+T 65200 45200 5 10 0 0 0 0 1
+device=PIC18F242
+T 65200 44900 5 10 0 0 0 0 1
+footprint=DIP28
+}
+C 43100 57100 1 0 0 TC2185.sym
+{
+T 43395 58295 5 10 1 1 0 0 1
+refdes=U?
+T 43895 58295 5 10 1 1 0 0 1
+device=TC2185-3.3
+T 43095 57095 5 10 0 1 0 0 1
+footprint=SOT23-5
+}
+C 41600 59500 1 0 1 conn-2.sym
+{
+T 41295 60145 5 10 1 1 0 6 1
+refdes=J?
+}
+N 43300 60000 41600 60000 4
+C 44100 56300 1 0 0 gnd.sym
+N 44200 57100 44200 56600 4
+N 44200 56700 41600 56700 4
+N 41600 56700 41600 59600 4
+N 43100 57600 42900 57600 4
+N 42900 57600 42900 60000 4
+C 42600 58000 1 90 0 capacitor.sym
+{
+T 41900 58200 5 10 0 0 90 0 1
+device=CAPACITOR
+T 42200 58700 5 10 1 1 180 0 1
+refdes=C?
+T 41700 58200 5 10 0 0 90 0 1
+symversion=0.1
+}
+C 45700 56700 1 90 0 capacitor.sym
+{
+T 45000 56900 5 10 0 0 90 0 1
+device=CAPACITOR
+T 45300 57400 5 10 1 1 180 0 1
+refdes=C?
+T 44800 56900 5 10 0 0 90 0 1
+symversion=0.1
+}
+C 46500 57100 1 90 0 capacitor.sym
+{
+T 45800 57300 5 10 0 0 90 0 1
+device=CAPACITOR
+T 46200 57800 5 10 1 1 180 0 1
+refdes=C?
+T 45600 57300 5 10 0 0 90 0 1
+symversion=0.1
+}
+N 44200 56700 46300 56700 4
+N 46300 56700 46300 57100 4
+N 45500 57600 45200 57600 4
+N 45200 58000 46300 58000 4
+N 42400 60000 42400 58900 4
+N 42400 58000 42400 56700 4
+C 46100 58000 1 0 0 3.3V-plus.sym
+C 52900 60500 1 0 0 3.3V-plus.sym
+N 50900 60400 55300 60400 4
+N 53100 60500 53100 60400 4
+N 50900 60400 50900 60300 4
+N 55300 60300 55300 60400 4
+N 54900 60300 54900 60400 4
+N 54500 60300 54500 60400 4
+N 54100 60300 54100 60400 4
+N 53700 60300 53700 60400 4
+N 53300 60300 53300 60400 4
+N 52900 60300 52900 60400 4
+N 52500 60300 52500 60400 4
+N 52100 60300 52100 60400 4
+N 51700 60300 51700 60400 4
+N 51300 60300 51300 60400 4
+C 43300 59400 1 0 0 volt_reg_pos.sym
+{
+T 44900 60700 5 10 0 0 0 0 1
+device=7805
+T 43800 60400 5 10 1 1 0 6 1
+refdes=U?
+T 44400 60400 5 10 1 1 0 0 1
+value=7805
+T 43300 59400 5 10 0 0 0 0 1
+vendor=digikey
+T 43300 59400 5 10 0 0 0 0 1
+vendor_part_number=497-2947-5-ND
+T 43300 59400 5 10 0 0 0 0 1
+footprint=TC220W
+}
+N 43100 58000 42900 58000 4
+C 44100 58800 1 0 0 gnd.sym
+C 45700 60000 1 0 0 5V-plus.sym
+N 45100 60000 45900 60000 4
+C 46100 59100 1 90 0 capacitor.sym
+{
+T 45400 59300 5 10 0 0 90 0 1
+device=CAPACITOR
+T 45800 59800 5 10 1 1 180 0 1
+refdes=C?
+T 45200 59300 5 10 0 0 90 0 1
+symversion=0.1
+}
+N 44200 59100 44200 59400 4
+N 45900 59100 44200 59100 4
+C 59400 47800 1 0 0 5V-plus.sym
+C 64900 47300 1 0 0 gnd.sym
+N 64800 47600 65000 47600 4
+N 59800 47600 59600 47600 4
+N 59600 47600 59600 47800 4
diff --git a/gafrc b/gafrc
new file mode 100644
index 0000000..1e29942
--- /dev/null
+++ b/gafrc
@@ -0,0 +1,3 @@
+; empty the library path and populate it with only our own symbols
+(reset-component-library)
+(component-library "./symbols")
diff --git a/packages/TO220W.fp b/packages/TO220W.fp
new file mode 100644
index 0000000..4653a53
--- /dev/null
+++ b/packages/TO220W.fp
@@ -0,0 +1,19 @@
+	Element(0x00 "Transistor" "" "TO220W" 0 10 0 100 0x00)
+(
+	Pin(100 200 90 60 "1" 0x101)
+	Pin(200 200 90 60 "2" 0x01)
+	Pin(300 200 90 60 "3" 0x01)
+	# Gehaeuse
+	ElementLine(  0  80 400  80 20)
+	ElementLine(400  80 400 260 20)
+	ElementLine(400 260   0 260 20) 
+	ElementLine(  0 260   0  80 20) 
+	# Kuehlfahne icl. Bohrung
+	ElementLine(  0  80 400  80 20)
+	ElementLine(400  80 400 140 20)
+	ElementLine(400 140   0 140 20)
+	ElementLine(  0 140   0  80 20)
+	ElementLine(130 80 130 140 10)
+	ElementLine(270 80 270 140 10)
+	Mark(100 200)
+)
diff --git a/project b/project
new file mode 100644
index 0000000..b77d709
--- /dev/null
+++ b/project
@@ -0,0 +1,4 @@
+schematics	cncfpga.sch
+output-name	cncfpga
+elements-dir	./packages
+skip-m4
diff --git a/symbols/3.3V-plus.sym b/symbols/3.3V-plus.sym
new file mode 100644
index 0000000..fbe5cc4
--- /dev/null
+++ b/symbols/3.3V-plus.sym
@@ -0,0 +1,17 @@
+v 20031231 1
+P 200 0 200 200 1 0 0
+{
+T 250 50 5 6 0 1 0 0 1
+pinnumber=1
+T 250 50 5 6 0 0 0 0 1
+pinseq=1
+T 250 50 5 6 0 1 0 0 1 
+pinlabel=1
+T 250 50 5 6 0 1 0 0 1 
+pintype=pwr
+}
+L 50 200 350 200 3 0 0 0 -1 -1
+T 75 250 9 8 1 0 0 0 1
++3.3V
+T 300 0 8 8 0 0 0 0 1
+net=+3.3V:1
diff --git a/symbols/5V-plus.sym b/symbols/5V-plus.sym
new file mode 100644
index 0000000..6804741
--- /dev/null
+++ b/symbols/5V-plus.sym
@@ -0,0 +1,17 @@
+v 20031231 1
+P 200 0 200 200 1 0 0
+{
+T 250 50 5 6 0 1 0 0 1
+pinnumber=1
+T 250 50 5 6 0 0 0 0 1
+pinseq=1
+T 250 50 5 6 0 1 0 0 1 
+pinlabel=1
+T 250 50 5 6 0 1 0 0 1 
+pintype=pwr
+}
+L 50 200 350 200 3 0 0 0 -1 -1
+T 75 250 9 8 1 0 0 0 1
++5V
+T 300 0 8 8 0 0 0 0 1
+net=+5V:1
diff --git a/symbols/EP1K10.sym b/symbols/EP1K10.sym
new file mode 100644
index 0000000..8d0a463
--- /dev/null
+++ b/symbols/EP1K10.sym
@@ -0,0 +1,1114 @@
+v 20110115 2
+P 0 5300 400 5300 1 0 0
+{
+T 305 5345 5 10 1 1 0 6 1
+pinnumber=3
+T 455 5295 3 10 1 1 0 0 1
+pinlabel=TDO
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+pinseq=18
+T 0 5300 5 10 0 1 180 6 1
+pintype=io
+}
+P 0 11700 400 11700 1 0 0
+{
+T 305 11745 5 10 1 1 0 6 1
+pinnumber=2
+T 455 11695 3 10 1 1 0 0 1
+pinlabel=nCEO
+T -400 11600 5 10 0 1 180 6 1
+pinseq=4
+T 0 11700 5 10 0 1 180 6 1
+pintype=io
+}
+P 0 12900 400 12900 1 0 0
+{
+T 305 12945 5 10 1 1 0 6 1
+pinnumber=1
+T 455 12895 3 10 1 1 0 0 1
+pinlabel=CONF_DONE
+T -400 12800 5 10 0 1 180 6 1
+pinseq=20
+T 0 12900 5 10 0 1 180 6 1
+pintype=io
+}
+P 2500 0 2500 400 1 0 0
+{
+T 2450 305 5 10 1 1 90 6 1
+pinnumber=18
+T 2500 455 3 10 1 1 90 0 1
+pinlabel=GNDINT
+T 2600 -400 5 10 0 1 270 6 1
+pinseq=3
+T 2500 0 5 10 0 1 270 6 1
+pintype=pwr
+}
+P 7000 14900 6600 14900 1 0 0
+{
+T 6695 14945 5 10 1 1 0 0 1
+pinnumber=19
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+pinlabel=IO
+T 7400 14800 5 10 0 1 180 0 1
+pinseq=21
+T 7000 14900 5 10 0 1 180 0 1
+pintype=io
+}
+B 400 400 6200 17800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T -6400 -2200 8 10 0 0 0 0 1
+description=Altera EP1K10TC100 FPGA
+T -6400 -1300 8 10 0 0 0 0 1
+numslots=1
+T -6400 -1600 8 10 0 0 0 0 1
+device=EP1K10TC100
+T 1650 15850 9 30 1 0 0 0 1
+EP1K10TC100
+T -6400 -1000 8 10 0 0 0 0 1
+slot=1
+T 600 18400 8 10 1 1 180 0 1
+refdes=U?
+P 7000 14500 6600 14500 1 0 0
+{
+T 6695 14545 5 10 1 1 0 0 1
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+pinlabel=IO
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+pinseq=25
+T 7000 14500 5 10 0 1 180 6 1
+pintype=io
+}
+P 7000 16100 6600 16100 1 0 0
+{
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+pinlabel=IO
+T 7000 16100 5 10 0 1 180 6 1
+pinseq=25
+T 7000 16100 5 10 0 1 180 6 1
+pintype=io
+}
+P 7000 15700 6600 15700 1 0 0
+{
+T 6695 15745 5 10 1 1 0 0 1
+pinnumber=15
+T 6545 15695 3 10 1 1 0 6 1
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+T 7000 15700 5 10 0 1 0 0 1
+pinseq=25
+T 7000 15700 5 10 0 1 0 0 1
+pintype=io
+}
+P 4100 18600 4100 18200 1 0 0
+{
+T 4050 18295 5 10 1 1 90 0 1
+pinnumber=17
+T 4100 18145 3 10 1 1 90 6 1
+pinlabel=VCCIO
+T 4100 18600 5 10 0 1 90 0 1
+pinseq=25
+T 4100 18600 5 10 0 1 90 0 1
+pintype=pwr
+}
+P 7000 15300 6600 15300 1 0 0
+{
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+pinnumber=16
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+pinseq=25
+T 7000 15300 5 10 0 1 0 0 1
+pintype=io
+}
+P 7000 16500 6600 16500 1 0 0
+{
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+pinnumber=13
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+pinlabel=IO
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+pinseq=25
+T 7000 16500 5 10 0 1 180 6 1
+pintype=out
+}
+P 0 12500 400 12500 1 0 0
+{
+T 305 12545 5 10 1 1 0 6 1
+pinnumber=10
+T 455 12495 3 10 1 1 0 0 1
+pinlabel=INIT_DONE
+T -400 12600 5 10 0 1 0 0 1
+pinseq=20
+T 0 12500 5 10 0 1 0 0 1
+pintype=io
+}
+P 2100 0 2100 400 1 0 0
+{
+T 2050 305 5 10 1 1 90 6 1
+pinnumber=11
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+pinlabel=GNDINT
+T 2200 -400 5 10 0 1 90 2 1
+pinseq=20
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+pintype=pwr
+}
+P 1300 18600 1300 18200 1 0 0
+{
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+pinlabel=VCCINT
+T 1400 19000 5 10 0 1 270 0 1
+pinseq=20
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+pintype=pwr
+}
+P 7000 14100 6600 14100 1 0 0
+{
+T 6695 14145 5 10 1 1 0 0 1
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+pintype=io
+}
+P 3700 18600 3700 18200 1 0 0
+{
+T 3650 18295 5 10 1 1 90 0 1
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+pinseq=18
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+pintype=pwr
+}
+P 7000 17300 6600 17300 1 0 0
+{
+T 6695 17345 5 10 1 1 0 0 1
+pinnumber=7
+T 6545 17295 3 10 1 1 0 6 1
+pinlabel=IO
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+pinseq=18
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+pintype=io
+}
+P 7000 17700 6600 17700 1 0 0
+{
+T 6695 17745 5 10 1 1 0 0 1
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+pinseq=4
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+pintype=io
+}
+P 0 9300 400 9300 1 0 0
+{
+T 305 9345 5 10 1 1 0 6 1
+pinnumber=5
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+pinlabel=CLKUSR
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+pinseq=20
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+}
+P 0 9700 400 9700 1 0 0
+{
+T 305 9745 5 10 1 1 0 6 1
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+pinlabel=RDYnBUSY
+T -400 9600 5 10 0 1 180 6 1
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+}
+P 7000 13700 6600 13700 1 0 0
+{
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+}
+P 7000 13300 6600 13300 1 0 0
+{
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+}
+P 0 4500 400 4500 1 0 0
+{
+T 305 4545 5 10 1 1 0 6 1
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+}
+P 0 14100 400 14100 1 0 0
+{
+T 100 14200 5 10 1 1 0 0 1
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+pintype=io
+}
+P 7000 16900 6600 16900 1 0 0
+{
+T 6695 16945 5 10 1 1 0 0 1
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+}
+P 7000 12100 6600 12100 1 0 0
+{
+T 6695 12145 5 10 1 1 0 0 1
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+}
+P 7000 12500 6600 12500 1 0 0
+{
+T 6695 12545 5 10 1 1 0 0 1
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+pinlabel=IO
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+}
+P 7000 12900 6600 12900 1 0 0
+{
+T 6695 12945 5 10 1 1 0 0 1
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+}
+P 7000 9700 6600 9700 1 0 0
+{
+T 6695 9745 5 10 1 1 0 0 1
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+}
+P 4500 18600 4500 18200 1 0 0
+{
+T 4450 18295 5 10 1 1 90 0 1
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+}
+P 7000 9300 6600 9300 1 0 0
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+}
+P 0 2500 400 2500 1 0 0
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+}
+P 0 3700 400 3700 1 0 0
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+}
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+}
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+}
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+}
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+}
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+}
+P 5700 18600 5700 18200 1 0 0
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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diff --git a/symbols/PIC12F629.sym b/symbols/PIC12F629.sym
new file mode 100644
index 0000000..8ef5d7f
--- /dev/null
+++ b/symbols/PIC12F629.sym
@@ -0,0 +1,104 @@
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diff --git a/symbols/TC2185.sym b/symbols/TC2185.sym
new file mode 100644
index 0000000..25816fe
--- /dev/null
+++ b/symbols/TC2185.sym
@@ -0,0 +1,63 @@
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diff --git a/symbols/capacitor.sym b/symbols/capacitor.sym
new file mode 100644
index 0000000..e814576
--- /dev/null
+++ b/symbols/capacitor.sym
@@ -0,0 +1,37 @@
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+}
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diff --git a/symbols/conn-15.sym b/symbols/conn-15.sym
new file mode 100644
index 0000000..c01b8fa
--- /dev/null
+++ b/symbols/conn-15.sym
@@ -0,0 +1,169 @@
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new file mode 100644
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