From: Fabien Le Mentec <texane@gmail.com>
Date: Sun, 23 Jun 2013 11:49:22 +0000 (-0500)
Subject: Merge branch 'master' of https://github.com/burnsfisher/stlink
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=57d068097eb57aa7ee985ddb1edea90a5d6d5d8a;p=fw%2Fstlink

Merge branch 'master' of https://github.com/burnsfisher/stlink
---

57d068097eb57aa7ee985ddb1edea90a5d6d5d8a
diff --cc src/stlink-common.c
index ed1583d,2b208bc..23bea58
--- a/src/stlink-common.c
+++ b/src/stlink-common.c
@@@ -461,10 -450,9 +461,10 @@@ int stlink_load_device_params(stlink_t 
      // read flash size from hardware, if possible...
      if (sl->chip_id == STM32_CHIPID_F2) {
          sl->flash_size = 0x100000; /* Use maximum, User must care!*/
 -    } else if (sl->chip_id == STM32_CHIPID_F4) {
 +    } else if (sl->chip_id == STM32_CHIPID_F4 ||
 +        sl->chip_id == STM32_CHIPID_F4_LP) {
  		sl->flash_size = 0x100000;			//todo: RM0090 error; size register same address as unique ID
-     } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
+     } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) {
          // if the flash size is zero, we assume it is 128k, if not we calculate the real value
          uint32_t flash_size = stlink_read_debug32(sl,params->flash_size_reg) & 0xffff;
          if ( flash_size == 0 ) {
diff --cc src/stlink-common.h
index 8b1be82,7553224..c170195
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@@ -102,10 -102,15 +102,16 @@@ extern "C" 
  #define STM32_CHIPID_F3 0x422
  #define STM32_CHIPID_F37x 0x432
  #define STM32_CHIPID_F4 0x413
 +#define STM32_CHIPID_F4_LP 0x423
  #define STM32_CHIPID_F1_HIGH 0x414
  #define STM32_CHIPID_L1_MEDIUM 0x416
- #define STM32_CHIPID_L1_MEDIUM_PLUS 0x436
+ #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
+ /*
+  * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
+  * and some that are called "High".  0x427 is assigned to the other "Medium-
+  * plus" chips.  To make it a bit simpler we just call 427 MEDIUM_PLUS and
+  * 0x436 HIGH.
+  */
  #define STM32_CHIPID_L1_HIGH 0x436
  #define STM32_CHIPID_F1_CONN 0x418
  #define STM32_CHIPID_F1_VL_MEDIUM 0x420