From: MaartenBrock Date: Mon, 10 Nov 2008 20:12:44 +0000 (+0000) Subject: * device/include/ctype.h, X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=55d8f43c15dffcca08d0cba49247f7a2f8dae48e;p=fw%2Fsdcc * device/include/ctype.h, * device/include/ds400rom.h, * device/include/ds80c390.h, * device/include/float.h, * device/include/math.h, * device/include/serial.h, * device/include/stdbool.h, * device/include/tinibios.h: replaced non-C89 '//' with '/* */', patch 2195343 * device/include/mcs51/C8051F336.h, * device/include/mcs51/C8051T600.h, * device/include/mcs51/C8051T610.h, * device/include/mcs51/C8051T630.h: new, added, patch 2183334 (svn commit by Maarten Brock ) git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@5263 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- diff --git a/ChangeLog b/ChangeLog index 07dd36b0..33856e35 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,20 @@ +2008-11-10 Steven Borley + + * device/include/ctype.h, + * device/include/ds400rom.h, + * device/include/ds80c390.h, + * device/include/float.h, + * device/include/math.h, + * device/include/serial.h, + * device/include/stdbool.h, + * device/include/tinibios.h: replaced non-C89 '//' with '/* */', + patch 2195343 + * device/include/mcs51/C8051F336.h, + * device/include/mcs51/C8051T600.h, + * device/include/mcs51/C8051T610.h, + * device/include/mcs51/C8051T630.h: new, added, patch 2183334 + (svn commit by Maarten Brock ) + 2008-11-10 Frieder Ferlemann * device/include/mcs51/P89LPC922.h: fixed #2255989, thanks kubi57 diff --git a/device/include/ctype.h b/device/include/ctype.h index f30bf8d9..67a24ef0 100644 --- a/device/include/ctype.h +++ b/device/include/ctype.h @@ -1,12 +1,12 @@ /*------------------------------------------------------------------------- ctype.h - ANSI functions forward declarations - + Written By - Sandeep Dutta . sandeep.dutta@usa.net (1998) Revisions: 1.0 - June.1.2000 1.0 - Bela Torok / bela.torok@kssg.ch order: function definitions -> macros - corretced macro: isalpha(c) + corretced macro: isalpha(c) added macros: _tolower(c), _toupper(c), tolower(c), toupper(c) toascii(c) @@ -14,19 +14,19 @@ under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - + In other words, you are welcome to use, share and improve this program. You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! + what you give them. Help stamp out software-hoarding! -------------------------------------------------------------------------*/ #ifndef __SDC51_CTYPE_H @@ -68,8 +68,8 @@ extern char isxdigit (unsigned char ) ; #define _toupper(c) ((c) + ('a' - 'A')) */ -// The _tolower & _toupper functions below can applied to any -// alpha characters regardless of the case (upper or lower) +/* The _tolower & _toupper functions below can applied to any + alpha characters regardless of the case (upper or lower) */ #define _tolower(c) ((c) | ('a' - 'A')) #define _toupper(c) ((c) & ~('a' - 'A')) @@ -78,9 +78,3 @@ extern char isxdigit (unsigned char ) ; #define toascii(c) ((c) & 0x7F) #endif - - - - - - diff --git a/device/include/ds400rom.h b/device/include/ds400rom.h index 11bacd35..c6c5f305 100644 --- a/device/include/ds400rom.h +++ b/device/include/ds400rom.h @@ -1,4 +1,4 @@ -// Interface to DS80C400 ROM functions. +/* Interface to DS80C400 ROM functions. */ #ifndef DS400ROM_H_ #define DS400ROM_H_ diff --git a/device/include/ds80c390.h b/device/include/ds80c390.h index 05dc4cf2..54f12658 100644 --- a/device/include/ds80c390.h +++ b/device/include/ds80c390.h @@ -1,40 +1,40 @@ /*------------------------------------------------------------------------- Register Declarations for the DALLAS DS80C390 Processor far from complete, e.g. no CAN - + Written By - Johan Knol, johan.knol@iduna.nl - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - + In other words, you are welcome to use, share and improve this program. You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! + what you give them. Help stamp out software-hoarding! -------------------------------------------------------------------------*/ #ifndef DS80C390_H #define DS80C390_H -__sfr __at 0x80 P4; // ce3..ce0, a19..a16 -__sfr __at 0x81 SP; // stack pointer -__sfr __at 0x82 DPL; // data pointer 0 lsb -__sfr __at 0x83 DPH; // data pointer 0 msb -__sfr __at 0x84 DPL1; // data pointer 1 lsb -__sfr __at 0x85 DPH1; // data pointer 1 msb -__sfr __at 0x86 DPS; // data pointer select -__sfr __at 0x87 PCON; // power control -__sfr __at 0x88 TCON; // timer/counter control +__sfr __at 0x80 P4; /* ce3..ce0, a19..a16 */ +__sfr __at 0x81 SP; /* stack pointer */ +__sfr __at 0x82 DPL; /* data pointer 0 lsb */ +__sfr __at 0x83 DPH; /* data pointer 0 msb */ +__sfr __at 0x84 DPL1; /* data pointer 1 lsb */ +__sfr __at 0x85 DPH1; /* data pointer 1 msb */ +__sfr __at 0x86 DPS; /* data pointer select */ +__sfr __at 0x87 PCON; /* power control */ +__sfr __at 0x88 TCON; /* timer/counter control */ __sbit __at 0x88 IT0; __sbit __at 0x89 IE0; __sbit __at 0x8a IT1; @@ -43,12 +43,12 @@ __sfr __at 0x88 TCON; // timer/counter control __sbit __at 0x8d TF0; __sbit __at 0x8e TR1; __sbit __at 0x8f TF1; -__sfr __at 0x89 TMOD; // timer mode control -__sfr __at 0x8a TL0; // timer 0 lsb -__sfr __at 0x8b TL1; // timer 1 msb -__sfr __at 0x8c TH0; // timer 0 msb -__sfr __at 0x8d TH1; // timer 1 msb -__sfr __at 0x8e CKCON; // clock control +__sfr __at 0x89 TMOD; /* timer mode control */ +__sfr __at 0x8a TL0; /* timer 0 lsb */ +__sfr __at 0x8b TL1; /* timer 1 msb */ +__sfr __at 0x8c TH0; /* timer 0 msb */ +__sfr __at 0x8d TH1; /* timer 1 msb */ +__sfr __at 0x8e CKCON; /* clock control */ __sfr __at 0x90 P1; __sbit __at 0x90 T2; __sbit __at 0x91 T2EX; @@ -58,11 +58,11 @@ __sfr __at 0x90 P1; __sbit __at 0x95 INT3; __sbit __at 0x96 INT4; __sbit __at 0x97 INT5; -__sfr __at 0x91 EXIF; // external interrupt flag +__sfr __at 0x91 EXIF; /* external interrupt flag */ __sfr __at 0x92 P4CNT; -__sfr __at 0x93 DPX; // extended datapointer 0 -__sfr __at 0x95 DPX1; // extended datapointer 1 -__sfr __at 0x98 SCON0; // serial 0 control +__sfr __at 0x93 DPX; /* extended datapointer 0 */ +__sfr __at 0x95 DPX1; /* extended datapointer 1 */ +__sfr __at 0x98 SCON0; /* serial 0 control */ __sbit __at 0x98 RI_0; __sbit __at 0x99 TI_0; __sbit __at 0x9a RB8_0; @@ -71,15 +71,15 @@ __sfr __at 0x98 SCON0; // serial 0 control __sbit __at 0x9d SM2_0; __sbit __at 0x9e SM1_0; __sbit __at 0x9f SM0_0; - __sbit __at 0x9f FE_0; // depending on SMOD0 -__sfr __at 0x99 SBUF0; // serial 0 data buffer -__sfr __at 0x9b ESP; // extended stack pointer -__sfr __at 0x9c AP; // address page -__sfr __at 0x9d ACON; // address control -__sfr __at 0xa0 P2; // never mind the sbits + __sbit __at 0x9f FE_0; /* depending on SMOD0 */ +__sfr __at 0x99 SBUF0; /* serial 0 data buffer */ +__sfr __at 0x9b ESP; /* extended stack pointer */ +__sfr __at 0x9c AP; /* address page */ +__sfr __at 0x9d ACON; /* address control */ +__sfr __at 0xa0 P2; /* never mind the sbits */ __sfr __at 0xa1 P5; __sfr __at 0xa2 P5CNT; -__sfr __at 0xa8 IE; // interrupt enable +__sfr __at 0xa8 IE; /* interrupt enable */ __sbit __at 0xa8 EX0; __sbit __at 0xa9 ET0; __sbit __at 0xaa EX1; @@ -97,15 +97,15 @@ __sfr __at 0xb0 P3; __sbit __at 0xb5 T1; __sbit __at 0xb6 WR; __sbit __at 0xb7 RD; -__sfr __at 0xb8 IP; // interupt priority - __sbit __at 0xb8 PX0; // external 0 - __sbit __at 0xb9 PT0; // timer 0 - __sbit __at 0xba PX1; // external 1 - __sbit __at 0xbb PT1; // timer 1 - __sbit __at 0xbc PS0; // serial port 0 - __sbit __at 0xbd PT2; // timer 2 - __sbit __at 0xbe PS1; // serial port 1 -__sfr __at 0xc0 SCON1; // serial 1 control +__sfr __at 0xb8 IP; /* interupt priority */ + __sbit __at 0xb8 PX0; /* external 0 */ + __sbit __at 0xb9 PT0; /* timer 0 */ + __sbit __at 0xba PX1; /* external 1 */ + __sbit __at 0xbb PT1; /* timer 1 */ + __sbit __at 0xbc PS0; /* serial port 0 */ + __sbit __at 0xbd PT2; /* timer 2 */ + __sbit __at 0xbe PS1; /* serial port 1 */ +__sfr __at 0xc0 SCON1; /* serial 1 control */ __sbit __at 0xc0 RI_1; __sbit __at 0xc1 TI_1; __sbit __at 0xc2 RB8_1; @@ -114,42 +114,42 @@ __sfr __at 0xc0 SCON1; // serial 1 control __sbit __at 0xc5 SM2_1; __sbit __at 0xc6 SM1_1; __sbit __at 0xc7 SM0_1; - __sbit __at 0xc7 FE_1; // depending on SMOD0 -__sfr __at 0xc1 SBUF1; // serial 1 data buffer -__sfr __at 0xc4 PMR; // power managment -__sfr __at 0xc6 MCON; // memory control register -__sfr __at 0xc7 TA; // timed access register -__sfr __at 0xc8 T2CON; // timer 2 control - __sbit __at 0xc8 CP_RL; // capture/reload - __sbit __at 0xc9 C_T; // count/timer - __sbit __at 0xca TR2; // stop/run + __sbit __at 0xc7 FE_1; /* depending on SMOD0 */ +__sfr __at 0xc1 SBUF1; /* serial 1 data buffer */ +__sfr __at 0xc4 PMR; /* power managment */ +__sfr __at 0xc6 MCON; /* memory control register */ +__sfr __at 0xc7 TA; /* timed access register */ +__sfr __at 0xc8 T2CON; /* timer 2 control */ + __sbit __at 0xc8 CP_RL; /* capture/reload */ + __sbit __at 0xc9 C_T; /* count/timer */ + __sbit __at 0xca TR2; /* stop/run */ __sbit __at 0xcb EXEN2; __sbit __at 0xcc TCLK; __sbit __at 0xcd RCLK; __sbit __at 0xce EXF2; - __sbit __at 0xcf TF2; // overflow flag -__sfr __at 0xc9 T2MOD; // timer 2 mode -__sfr __at 0xca RCAP2L; // timer 2 capture/reload -__sfr __at 0xca RTL2; // depends on CP_RL + __sbit __at 0xcf TF2; /* overflow flag */ +__sfr __at 0xc9 T2MOD; /* timer 2 mode */ +__sfr __at 0xca RCAP2L; /* timer 2 capture/reload */ +__sfr __at 0xca RTL2; /* depends on CP_RL */ __sfr __at 0xcb RCAP2H; __sfr __at 0xcb RTH2; -__sfr __at 0xcc TL2; // timer 2 lsb -__sfr __at 0xcd TH2; // timer 2 msb -__sfr __at 0xd0 PSW; // program status word (byte actually) - __sbit __at 0xd0 P; // parity - __sbit __at 0xd1 F1; // user flag 1 - __sbit __at 0xd2 OV; // overflow flag - __sbit __at 0xd3 RS0; // register select l - __sbit __at 0xd4 RS1; // register select h - __sbit __at 0xd5 F0; // user flag 0 - __sbit __at 0xd6 AC; // auxiliary carry flag - __sbit __at 0xd7 CY; // carry flag -__sfr __at 0xd1 MCNT0; // arithmetic accellerator +__sfr __at 0xcc TL2; /* timer 2 lsb */ +__sfr __at 0xcd TH2; /* timer 2 msb */ +__sfr __at 0xd0 PSW; /* program status word (byte actually) */ + __sbit __at 0xd0 P; /* parity */ + __sbit __at 0xd1 F1; /* user flag 1 */ + __sbit __at 0xd2 OV; /* overflow flag */ + __sbit __at 0xd3 RS0; /* register select l */ + __sbit __at 0xd4 RS1; /* register select h */ + __sbit __at 0xd5 F0; /* user flag 0 */ + __sbit __at 0xd6 AC; /* auxiliary carry flag */ + __sbit __at 0xd7 CY; /* carry flag */ +__sfr __at 0xd1 MCNT0; /* arithmetic accellerator */ __sfr __at 0xd2 MCNT1; __sfr __at 0xd3 MA; __sfr __at 0xd4 MB; __sfr __at 0xd5 MC; -__sfr __at 0xd8 WDCON; // watch dog +__sfr __at 0xd8 WDCON; /* watch dog */ __sbit __at 0xd8 RWT; __sbit __at 0xd9 EWT; __sbit __at 0xda WDRF; @@ -158,8 +158,8 @@ __sfr __at 0xd8 WDCON; // watch dog __sbit __at 0xdd EPFI; __sbit __at 0xde POR; __sbit __at 0xdf SMOD_1; -__sfr __at 0xe0 ACC; // accumulator -__sfr __at 0xe8 EIE; // extended interrupt enable +__sfr __at 0xe0 ACC; /* accumulator */ +__sfr __at 0xe8 EIE; /* extended interrupt enable */ __sbit __at 0xe8 EX2; __sbit __at 0xe9 EX3; __sbit __at 0xea EX4; @@ -168,9 +168,9 @@ __sfr __at 0xe8 EIE; // extended interrupt enable __sbit __at 0xed C1IE; __sbit __at 0xee C0IE; __sbit __at 0xef CANBIE; -__sfr __at 0xea MXAX; // extended address register -__sfr __at 0xf0 B; // aux accumulator -__sfr __at 0xf8 EIP; // extended interrupt priority +__sfr __at 0xea MXAX; /* extended address register */ +__sfr __at 0xf0 B; /* aux accumulator */ +__sfr __at 0xf8 EIP; /* extended interrupt priority */ __sbit __at 0xf8 PX2; __sbit __at 0xf9 PX3; __sbit __at 0xfa PX4; @@ -182,9 +182,9 @@ __sfr __at 0xf8 EIP; // extended interrupt priority /* WORD/DWORD Registers */ -__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */ -__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */ -__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */ -__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */ +__sfr16 __at (0x8C8A) TMR0; /* TIMER 0 COUNTER */ +__sfr16 __at (0x8D8B) TMR1; /* TIMER 1 COUNTER */ +__sfr16 __at (0xCDCC) TMR2; /* TIMER 2 COUNTER */ +__sfr16 __at (0xCBCA) RCAP2; /* TIMER 2 CAPTURE REGISTER WORD */ #endif /* DS80C390_H */ diff --git a/device/include/float.h b/device/include/float.h index b31679bc..616c34f1 100644 --- a/device/include/float.h +++ b/device/include/float.h @@ -1,25 +1,25 @@ /*------------------------------------------------------------------------- float.h - ANSI functions forward declarations - + Written By - Sandeep Dutta . sandeep.dutta@usa.net (1998) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - + In other words, you are welcome to use, share and improve this program. You are forbidden to forbid anyone else to use, share and improve - what you give them. Help stamp out software-hoarding! + what you give them. Help stamp out software-hoarding! -------------------------------------------------------------------------*/ #ifndef __SDC51_FLOAT_H @@ -76,23 +76,23 @@ char __fsgt (float, float); #define FLOAT_ASM_MCS51 -// This adds extra code for proper round-off, in -// an attempt to match the results from gcc. +/* This adds extra code for proper round-off, in + an attempt to match the results from gcc. */ #define FLOAT_FULL_ACCURACY -// This adds about 66 bytes to the code size and -// significantly speeds up shift operations more -// than 8 bits (common when subtracting numbers -// of significantly different magnitude and scaling -// to fixed point) +/* This adds about 66 bytes to the code size and + significantly speeds up shift operations more + than 8 bits (common when subtracting numbers + of significantly different magnitude and scaling + to fixed point) */ #define FLOAT_SHIFT_SPEEDUP #define sign_a psw.1 #define sign_b psw.5 #define exp_a dpl #define exp_b dph -#endif // using mcs51 assembly +#endif /* using mcs51 assembly */ -#endif // __SDC51_FLOAT_H +#endif /* __SDC51_FLOAT_H */ diff --git a/device/include/math.h b/device/include/math.h index de015c35..bca70903 100644 --- a/device/include/math.h +++ b/device/include/math.h @@ -31,9 +31,9 @@ #define iTWO_PI 0.1591549431 #define TWO_O_PI 0.6366197724 -// EPS=B**(-t/2), where B is the radix of the floating-point representation -// and there are t base-B digits in the significand. Therefore, for floats -// EPS=2**(-12). Also define EPS2=EPS*EPS. +/* EPS=B**(-t/2), where B is the radix of the floating-point representation + and there are t base-B digits in the significand. Therefore, for floats + EPS=2**(-12). Also define EPS2=EPS*EPS. */ #define EPS 244.14062E-6 #define EPS2 59.6046E-9 @@ -44,9 +44,9 @@ union float_long }; #if defined(SDCC_MATH_LIB) && defined(SDCC_mcs51) && !defined(SDCC_USE_XSTACK) && !defined(SDCC_STACK_AUTO) && !defined(_SDCC_NO_ASM_LIB_FUNCS) -// Compile the mcs51 assembly version only when all these -// conditions are met. Since not all the functions are -// reentrant, do not compile with --stack-auto is used. +/* Compile the mcs51 assembly version only when all these + conditions are met. Since not all the functions are + reentrant, do not compile with --stack-auto is used. */ #define MATH_ASM_MCS51 #endif diff --git a/device/include/mcs51/C8051F336.h b/device/include/mcs51/C8051F336.h new file mode 100644 index 00000000..d3bc8c97 --- /dev/null +++ b/device/include/mcs51/C8051F336.h @@ -0,0 +1,338 @@ +/*------------------------------------------------------------------------- + Register Declarations for the SiLabs C8051F336/7/8/9 Processor Range + + Copyright (C) 2008 - Steven Borley, steven.borley@partnerelectronics.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051F336_H +#define C8051F336_H + +#include + +/* BYTE Registers */ + +SFR( P0, 0x80 ) ; /* PORT 0 */ +SFR( SP, 0x81 ) ; /* STACK POINTER */ +SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */ +SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */ +SFR( PCON, 0x87 ) ; /* POWER CONTROL */ +SFR( TCON, 0x88 ) ; /* TIMER CONTROL */ +SFR( TMOD, 0x89 ) ; /* TIMER MODE */ +SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */ +SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */ +SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */ +SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */ +SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */ +SFR( PSCTL, 0x8F ) ; /* PROGRAM STORE R/W CONTROL */ +SFR( P1, 0x90 ) ; /* PORT 1 */ +SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */ +SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */ +SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */ +SFR( IDA0L, 0x96 ) ; /* CURRENT MODE DAC 0 - LOW BYTE */ +SFR( IDA0H, 0x97 ) ; /* CURRENT MODE DAC 0 - HIGH BYTE */ +SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */ +SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */ +SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */ +SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */ +SFR( CPT0CN, 0x9B ) ; /* COMPARATOR 0 CONTROL */ +SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */ +SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */ +SFR( P2, 0xA0 ) ; /* PORT 2 */ +SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */ +SFR( SPI0CKR, 0xA2 ) ; /* SPI0 CLOCK RATE CONTROL */ +SFR( SPI0DAT, 0xA3 ) ; /* SPI0 DATA */ +SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */ +SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */ +SFR( EMI0CN, 0xAA ) ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA PAGE */ +SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */ +SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */ +SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */ +SFR( FLSCL, 0xB6 ) ; /* FLASH MEMORY TIMING PRESCALER */ +SFR( FLKEY, 0xB7 ) ; /* FLASH ACESS LIMIT */ +SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */ +SFR( IDA0CN, 0xB9 ) ; /* CURRENT MODE DAC 0 - CONTROL */ +SFR( AMX0N, 0xBA ) ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */ +SFR( AMX0P, 0xBB ) ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ +SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */ +SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA WORD LSB */ +SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA WORD MSB */ +SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */ +SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */ +SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */ +SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN LOW BYTE */ +SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN HIGH BYTE */ +SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN LOW BYTE */ +SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN HIGH BYTE */ +SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */ +SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */ +SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */ +SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */ +SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ +SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ +SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */ +SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */ +SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */ +SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */ +SFR( P2SKIP, 0xD6 ) ; /* PORT 2 SKIP */ +SFR( SMB0ADR, 0xD7 ) ; /* SMBUS SLAVE ADDRESS */ +SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */ +SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */ +SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */ +SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */ +SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */ +SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */ +SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */ +SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */ +SFR( OSCLCN, 0xE3 ) ; /* LOW-FREQUENCY OSCILLATOR CONTROL */ +SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ +SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ +SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */ +SFR( SMB0ADM, 0xE7 ) ; /* SMBUS SLAVE ADDRESS MASK */ +SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */ +SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */ +SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */ +SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */ +SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */ +SFR( P1MAT, 0xED ) ; /* PORT 1 MATCH REGISTER */ +SFR( P1MASK, 0xEE ) ; /* PORT 1 MASK REGISTER */ +SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */ +SFR( B, 0xF0 ) ; /* B REGISTER */ +SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ +SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ +SFR( P1MODE, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */ +SFR( P1MDIN, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */ +SFR( P2MDIN, 0xF3 ) ; /* PORT 2 INPUT MODE */ +SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +SFR( PCA0PWM, 0xF7 ) ; /* PCA PWM CONFIGURATION */ +SFR( SPI0CN, 0xF8 ) ; /* SPI0 CONTROL */ +SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */ +SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */ +SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */ +SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */ +SFR( P0MAT, 0xFD ) ; /* PORT 0 MATCH REGISTER */ +SFR( P0MASK, 0xFE ) ; /* PORT 0 MASK REGISTER */ +SFR( VDM0CN, 0xFF ) ; /* VDD MONITOR CONTROL */ + + +/* WORD/DWORD Registers */ + +SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */ +SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */ +SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */ +SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ +SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ +SFR16E( TMR3, 0x9594 ) ; /* TIMER 3 COUNTER */ +SFR16E( TMR3RL, 0x9392 ) ; /* TIMER 3 CAPTURE REGISTER WORD */ +SFR16E( IDA0, 0x9796 ) ; /* CURRENT MODE DAC 0 DATA WORD */ +SFR16E( ADC0, 0xBEBD ) ; /* ADC 0 DATA WORD */ +SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */ +SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */ +SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */ +SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */ +SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */ +SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */ + + +/* BIT Registers */ + +/* P0 0x80 */ +SBIT( P0_0, 0x80, 0 ) ; +SBIT( P0_1, 0x80, 1 ) ; +SBIT( P0_2, 0x80, 2 ) ; +SBIT( P0_3, 0x80, 3 ) ; +SBIT( P0_4, 0x80, 4 ) ; +SBIT( P0_5, 0x80, 5 ) ; +SBIT( P0_6, 0x80, 6 ) ; +SBIT( P0_7, 0x80, 7 ) ; + +/* TCON 0x88 */ +SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* P1 0x90 */ +SBIT( P1_0, 0x90, 0 ) ; +SBIT( P1_1, 0x90, 1 ) ; +SBIT( P1_2, 0x90, 2 ) ; +SBIT( P1_3, 0x90, 3 ) ; +SBIT( P1_4, 0x90, 4 ) ; +SBIT( P1_5, 0x90, 5 ) ; +SBIT( P1_6, 0x90, 6 ) ; +SBIT( P1_7, 0x90, 7 ) ; + +/* SCON 0x98 */ +SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ +SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ +SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ +SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ +SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* P2 0xA0 */ +SBIT( P2_0, 0xA0, 0 ) ; +SBIT( P2_1, 0xA0, 1 ) ; +SBIT( P2_2, 0xA0, 2 ) ; +SBIT( P2_3, 0xA0, 3 ) ; +SBIT( P2_4, 0xA0, 4 ) ; +SBIT( P2_5, 0xA0, 5 ) ; +SBIT( P2_6, 0xA0, 6 ) ; +SBIT( P2_7, 0xA0, 7 ) ; + +/* IE 0xA8 */ +SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +SBIT( ESPI0, 0xA8, 6 ) ; /* IE.6 - SPI0 INTERRUPT ENABLE */ +SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */ +SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */ +SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */ +SBIT( PSPI0, 0xB8, 6 ) ; /* IP.6 - SPI0 PRIORITY */ + +/* SMB0CN 0xC0 */ +SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +SBIT( TF2CEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/ +SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */ +SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */ +SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */ +SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */ +SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */ +SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */ +SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0CN 0xE8 */ +SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ +SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */ +SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */ + +/* SPI0CN 0xF8 */ +SBIT( SPIEN, 0xF8, 0 ) ; /* SPI0CN.0 - SPI0 ENABLE */ +SBIT( TXBMT, 0xF8, 1 ) ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +SBIT( NSSMD0, 0xF8, 2 ) ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +SBIT( NSSMD1, 0xF8, 3 ) ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +SBIT( RXOVRN, 0xF8, 4 ) ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +SBIT( MODF, 0xF8, 5 ) ; /* SPI0CN.5 - MODE FAULT FLAG */ +SBIT( WCOL, 0xF8, 6 ) ; /* SPI0CN.6 - WRITE COLLISION FLAG */ +SBIT( SPIF, 0xF8, 7 ) ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ + + +/* Predefined SFR Bit Masks */ + +#define PCON_IDLE 0x01 /* PCON */ +#define PCON_STOP 0x02 /* PCON */ +#define T1M 0x08 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0 0x20 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR0 */ +#define CP0OEN 0x10 /* XBR0 */ +#define CP0AE 0x20 /* XBR0 */ +#define CP0AOEN 0x20 /* XBR0 */ + +/* Interrupts */ + +#define INT_EXT0 0 /* External Interrupt 0 */ +#define INT_TIMER0 1 /* Timer0 Overflow */ +#define INT_EXT1 2 /* External Interrupt 1 */ +#define INT_TIMER1 3 /* Timer1 Overflow */ +#define INT_UART0 4 /* Serial Port 0 */ +#define INT_TIMER2 5 /* Timer2 Overflow */ +#define INT_SPI0 6 /* Serial Peripheral Interface 0 */ +#define INT_SMBUS0 7 /* SMBus0 Interface */ +#define INT_PMAT 8 /* Port match */ +#define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */ +#define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */ +#define INT_PCA0 11 /* PCA0 Peripheral */ +#define INT_COMPARATOR0 12 /* Comparator0 */ +/* 13 Reserved */ +#define INT_TIMER3 14 /* Timer3 Overflow */ + +#endif diff --git a/device/include/mcs51/C8051T600.h b/device/include/mcs51/C8051T600.h new file mode 100644 index 00000000..2dd03c0a --- /dev/null +++ b/device/include/mcs51/C8051T600.h @@ -0,0 +1,282 @@ +/*------------------------------------------------------------------------- + Register Declarations for the SiLabs C8051T60x Processor Range + + Copyright (C) 2008 - Steven Borley, steven.borley@partnerelectronics.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051T600_H +#define C8051T600_H + +#include + + +/* BYTE Registers */ + +SFR( P0, 0x80 ) ; /* PORT 0 */ +SFR( SP, 0x81 ) ; /* STACK POINTER */ +SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */ +SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */ +SFR( PCON, 0x87 ) ; /* POWER CONTROL */ +SFR( TCON, 0x88 ) ; /* TIMER CONTROL */ +SFR( TMOD, 0x89 ) ; /* TIMER MODE */ +SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */ +SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */ +SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */ +SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */ +SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */ +SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */ +SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */ +SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */ +SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */ +SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */ +SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */ +SFR( TOFFL, 0xA2 ) ; /* TEMPERATURE SENSOR OFFSET - LOW BYTE */ +SFR( TOFFH, 0xA3 ) ; /* TEMPERATURE SENSOR OFFSET - HIGH BYTE */ +SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */ +SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */ +SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */ +SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */ +SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */ +SFR( AMX0SL, 0xBB ) ; /* ADC 0 MUX CHANNEL SELECTION */ +SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */ +SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA - LOW BYTE */ +SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA - HIGH BYTE */ +SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */ +SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */ +SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */ +SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */ +SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */ +SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */ +SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */ +SFR( REG0CN, 0xC7 ) ; /* Voltage Regulator Control */ +SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */ +SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */ +SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */ +SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */ +SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ +SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ +SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */ +SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */ +SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */ +SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */ +SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */ +SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */ +SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */ +SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */ +SFR( PRT0MX, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */ +SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */ +SFR( PRT1MX, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */ +SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */ +SFR( PRT2MX, 0xE3 ) ; /* PORT MUX CONFIGURATION REGISTER 2 */ +SFR( XBR2, 0xE3 ) ; /* PORT MUX CONFIGURATION REGISTER 2 */ +SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ +SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ +SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */ +SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */ +SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */ +SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */ +SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */ +SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */ +SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */ +SFR( B, 0xF0 ) ; /* B REGISTER */ +SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ +SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ +SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +SFR( CPT0CN, 0xF8 ) ; /* COMPARATOR 0 CONTROL */ +SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */ +SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */ +SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */ +SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */ + + +/* WORD/DWORD Registers */ + +SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */ +SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */ +SFR16E( TOFF, 0xA3A2 ) ; /* TEMPERATURE SENSOR OFFSET WORD */ +SFR16E( ADC0, 0xAEAD ) ; /* ADC0 DATA WORD */ +SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */ +SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */ +SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */ +SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ +SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ +SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */ +SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */ +SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */ +SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */ + + +/* BIT Registers */ + +/* P0 0x80 */ +SBIT( P0_0, 0x80, 0 ) ; +SBIT( P0_1, 0x80, 1 ) ; +SBIT( P0_2, 0x80, 2 ) ; +SBIT( P0_3, 0x80, 3 ) ; +SBIT( P0_4, 0x80, 4 ) ; +SBIT( P0_5, 0x80, 5 ) ; +SBIT( P0_6, 0x80, 6 ) ; +SBIT( P0_7, 0x80, 7 ) ; + +/* TCON 0x88 */ +SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* SCON 0x98 */ +SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ +SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ +SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ +SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ +SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* IE 0xA8 */ +SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +SBIT( IEGF0, 0xA8, 6 ) ; /* IE.6 - GENERAL PURPOSE FLAG 0 */ +SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */ +SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */ +SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */ + +/* SMB0CN 0xC0 */ +SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */ +SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */ +SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */ +SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */ +SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */ +SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */ +SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0CN 0xE8 */ +SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ +SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */ +SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */ + +/* CPT0CN 0xF8 */ +SBIT( CP0HYN0, 0xF8, 0 ) ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/ +SBIT( CP0HYN1, 0xF8, 1 ) ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/ +SBIT( CP0HYP0, 0xF8, 2 ) ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/ +SBIT( CP0HYP1, 0xF8, 3 ) ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/ +SBIT( CP0FIF, 0xF8, 4 ) ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */ +SBIT( CP0RIF, 0xF8, 5 ) ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */ +SBIT( CP0OUT, 0xF8, 6 ) ; /* CPT0CN.6 - Comparator0 Output State Flag */ +SBIT( CP0EN, 0xF8, 7 ) ; /* CPT0CN.7 - Comparator0 Enable Bit */ + + +/* Predefined SFR Bit Masks */ + +#define PCON_IDLE 0x01 /* PCON */ +#define PCON_STOP 0x02 /* PCON */ +#define T1M 0x10 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0F 0x10 /* EIE1 */ +#define ECP0R 0x20 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR1 */ +#define CP0OEN 0x10 /* XBR1 */ +#define CP0AE 0x20 /* XBR1 */ +#define CP0AOEN 0x20 /* XBR1 */ + +/* Interrupts */ + +#define INT_EXT0 0 /* External Interrupt 0 */ +#define INT_TIMER0 1 /* Timer0 Overflow */ +#define INT_EXT1 2 /* External Interrupt 1 */ +#define INT_TIMER1 3 /* Timer1 Overflow */ +#define INT_UART0 4 /* Serial Port 0 */ +#define INT_TIMER2 5 /* Timer2 Overflow */ +#define INT_SMBUS0 6 /* SMBus0 Interface */ +#define INT_ADC0_WINDOW 7 /* ADC0 Window Comparison */ +#define INT_ADC0_EOC 8 /* ADC0 End Of Conversion */ +#define INT_PCA0 9 /* PCA0 Peripheral */ +#define INT_CP0F 10 /* Comparator0 falling edge */ +#define INT_CP0R 11 /* Comparator1 rising edge */ + +#endif diff --git a/device/include/mcs51/C8051T610.h b/device/include/mcs51/C8051T610.h new file mode 100644 index 00000000..ecd47b59 --- /dev/null +++ b/device/include/mcs51/C8051T610.h @@ -0,0 +1,356 @@ +/*------------------------------------------------------------------------- + Register Declarations for the SiLabs C8051T61x Processor Range + + Copyright (C) 2008 - Steven Borley, steven.borley@partnerelectronics.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051T610_H +#define C8051T610_H + +#include + +/* BYTE Registers */ + +SFR( P0, 0x80 ) ; /* PORT 0 */ +SFR( SP, 0x81 ) ; /* STACK POINTER */ +SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */ +SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */ +SFR( TOFFL, 0x85 ) ; /* TEMPERATURE SENSOR OFFSET - LOW BYTE */ +SFR( TOFFH, 0x86 ) ; /* TEMPERATURE SENSOR OFFSET - HIGH BYTE */ +SFR( PCON, 0x87 ) ; /* POWER CONTROL */ +SFR( TCON, 0x88 ) ; /* TIMER CONTROL */ +SFR( TMOD, 0x89 ) ; /* TIMER MODE */ +SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */ +SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */ +SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */ +SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */ +SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */ +SFR( P1, 0x90 ) ; /* PORT 1 */ +SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */ +SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */ +SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */ +SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */ +SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */ +SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */ +SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */ +SFR( CPT1CN, 0x9A ) ; /* COMPARATOR 1 CONTROL */ +SFR( CPT0CN, 0x9B ) ; /* COMPARATOR 0 CONTROL */ +SFR( CPT1MD, 0x9C ) ; /* COMPARATOR 1 MODE SELECTION */ +SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */ +SFR( CPT1MX, 0x9E ) ; /* COMPARATOR 1 MUX SELECTION */ +SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */ +SFR( P2, 0xA0 ) ; /* PORT 2 */ +SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */ +SFR( SPI0CKR, 0xA2 ) ; /* SPI0 CLOCK RATE CONTROL */ +SFR( SPI0DAT, 0xA3 ) ; /* SPI0 DATA */ +SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +SFR( P3MDOUT, 0xA7 ) ; /* PORT 3 OUTPUT MODE CONFIGURATION */ +SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */ +SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */ +SFR( EMI0CN, 0xAA ) ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA PAGE */ +SFR( P3, 0xB0 ) ; /* PORT 3 */ +SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */ +SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */ +SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */ +SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */ +SFR( AMX0P, 0xBB ) ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ +SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */ +SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA WORD LSB */ +SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA WORD MSB */ +SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */ +SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */ +SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */ +SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN LOW BYTE */ +SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN HIGH BYTE */ +SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN LOW BYTE */ +SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN HIGH BYTE */ +SFR( REG0CN, 0xC7 ) ; /* Voltage Regulator Control */ +SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */ +SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */ +SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */ +SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */ +SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ +SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ +SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */ +SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */ +SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */ +SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */ +SFR( P2SKIP, 0xD6 ) ; /* PORT 2 SKIP */ +SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */ +SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */ +SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */ +SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */ +SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */ +SFR( PCA0CPM3, 0xDD ) ; /* PCA MODULE 3 MODE REGISTER */ +SFR( PCA0CPM4, 0xDE ) ; /* PCA MODULE 4 MODE REGISTER */ +SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */ +SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */ +SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */ +SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ +SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ +SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */ +SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */ +SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */ +SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */ +SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */ +SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */ +SFR( PCA0CPL3, 0xED ) ; /* PCA CAPTURE 3 LOW */ +SFR( PCA0CPH3, 0xEE ) ; /* PCA CAPTURE 3 HIGH */ +SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */ +SFR( B, 0xF0 ) ; /* B REGISTER */ +SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ +SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ +SFR( P1MODE, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */ +SFR( P1MDIN, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */ +SFR( P2MODE, 0xF3 ) ; /* PORT 2 INPUT MODE CONFIGURATION */ +SFR( P2MDIN, 0xF3 ) ; /* PORT 2 INPUT MODE CONFIGURATION */ +SFR( P3MODE, 0xF4 ) ; /* PORT 3 INPUT MODE CONFIGURATION */ +SFR( P3MDIN, 0xF4 ) ; /* PORT 3 INPUT MODE CONFIGURATION */ +SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +SFR( SPI0CN, 0xF8 ) ; /* SPI0 CONTROL */ +SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */ +SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */ +SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */ +SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */ +SFR( PCA0CPL4, 0xFD ) ; /* PCA CAPTURE 4 LOW */ +SFR( PCA0CPH4, 0xFE ) ; /* PCA CAPTURE 4 HIGH */ +SFR( VDM0CN, 0xFF ) ; /* VDD MONITOR CONTROL */ + + +/* WORD/DWORD Registers */ + +SFR16E( TOFF, 0x8685 ) ; /* TEMPERATURE SENSOR OFFSET WORD */ +SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */ +SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */ +SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */ +SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ +SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ +SFR16E( TMR3, 0x9594 ) ; /* TIMER 3 COUNTER */ +SFR16E( TMR3RL, 0x9392 ) ; /* TIMER 3 CAPTURE REGISTER WORD */ +SFR16E( ADC0, 0xBEBD ) ; /* ADC 0 DATA WORD */ +SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */ +SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */ +SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */ +SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */ +SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */ +SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */ +SFR16E( PCA0CP3, 0xEEED ) ; /* PCA CAPTURE 3 WORD */ +SFR16E( PCA0CP4, 0xFEFD ) ; /* PCA CAPTURE 4 WORD */ + + +/* BIT Registers */ + +/* P0 0x80 */ +SBIT( P0_0, 0x80, 0 ) ; +SBIT( P0_1, 0x80, 1 ) ; +SBIT( P0_2, 0x80, 2 ) ; +SBIT( P0_3, 0x80, 3 ) ; +SBIT( P0_4, 0x80, 4 ) ; +SBIT( P0_5, 0x80, 5 ) ; +SBIT( P0_6, 0x80, 6 ) ; +SBIT( P0_7, 0x80, 7 ) ; + +/* TCON 0x88 */ +SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* P1 0x90 */ +SBIT( P1_0, 0x90, 0 ) ; +SBIT( P1_1, 0x90, 1 ) ; +SBIT( P1_2, 0x90, 2 ) ; +SBIT( P1_3, 0x90, 3 ) ; +SBIT( P1_4, 0x90, 4 ) ; +SBIT( P1_5, 0x90, 5 ) ; +SBIT( P1_6, 0x90, 6 ) ; +SBIT( P1_7, 0x90, 7 ) ; + +/* SCON 0x98 */ +SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ +SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ +SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ +SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ +SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* P2 0xA0 */ +SBIT( P2_0, 0xA0, 0 ) ; +SBIT( P2_1, 0xA0, 1 ) ; +SBIT( P2_2, 0xA0, 2 ) ; +SBIT( P2_3, 0xA0, 3 ) ; +SBIT( P2_4, 0xA0, 4 ) ; +SBIT( P2_5, 0xA0, 5 ) ; +SBIT( P2_6, 0xA0, 6 ) ; +SBIT( P2_7, 0xA0, 7 ) ; + +/* IE 0xA8 */ +SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +SBIT( ESPI0, 0xA8, 6 ) ; /* IE.6 - SPI0 INTERRUPT ENABLE */ +SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* P3 0xB0 */ +SBIT( P3_0, 0xB0, 0 ) ; +SBIT( P3_1, 0xB0, 1 ) ; +SBIT( P3_2, 0xB0, 2 ) ; +SBIT( P3_3, 0xB0, 3 ) ; +SBIT( P3_4, 0xB0, 4 ) ; +SBIT( P3_5, 0xB0, 5 ) ; +SBIT( P3_6, 0xB0, 6 ) ; +SBIT( P3_7, 0xB0, 7 ) ; + +/* IP 0xB8 */ +SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */ +SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */ +SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */ +SBIT( PSPI0, 0xB8, 6 ) ; /* IP.6 - SPI0 PRIORITY */ + +/* SMB0CN 0xC0 */ +SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */ +SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */ +SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */ +SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */ +SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */ +SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */ +SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +SBIT( CCF3, 0xD8, 3 ) ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */ +SBIT( CCF4, 0xD8, 4 ) ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */ +SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0CN 0xE8 */ +SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ +SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */ +SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */ + +/* SPI0CN 0xF8 */ +SBIT( SPIEN, 0xF8, 0 ) ; /* SPI0CN.0 - SPI0 ENABLE */ +SBIT( TXBMT, 0xF8, 1 ) ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +SBIT( NSSMD0, 0xF8, 2 ) ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +SBIT( NSSMD1, 0xF8, 3 ) ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +SBIT( RXOVRN, 0xF8, 4 ) ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +SBIT( MODF, 0xF8, 5 ) ; /* SPI0CN.5 - MODE FAULT FLAG */ +SBIT( WCOL, 0xF8, 6 ) ; /* SPI0CN.6 - WRITE COLLISION FLAG */ +SBIT( SPIF, 0xF8, 7 ) ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ + + +/* Predefined SFR Bit Masks */ + +#define PCON_IDLE 0x01 /* PCON */ +#define PCON_STOP 0x02 /* PCON */ +#define T1M 0x08 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0 0x20 /* EIE1 */ +#define ECP1 0x40 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR0 */ +#define CP0OEN 0x10 /* XBR0 */ +#define CP0AE 0x20 /* XBR0 */ +#define CP0AOEN 0x20 /* XBR0 */ +#define CP1E 0x40 /* XBR0 */ +#define CP1AE 0x80 /* XBR0 */ + +/* Interrupts */ + +#define INT_EXT0 0 /* External Interrupt 0 */ +#define INT_TIMER0 1 /* Timer0 Overflow */ +#define INT_EXT1 2 /* External Interrupt 1 */ +#define INT_TIMER1 3 /* Timer1 Overflow */ +#define INT_UART0 4 /* Serial Port 0 */ +#define INT_TIMER2 5 /* Timer2 Overflow */ +#define INT_SPI0 6 /* Serial Peripheral Interface 0 */ +#define INT_SMBUS0 7 /* SMBus0 Interface */ +/* 8 Reserved */ +#define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */ +#define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */ +#define INT_PCA0 11 /* PCA0 Peripheral */ +#define INT_COMPARATOR0 12 /* Comparator0 */ +#define INT_COMPARATOR1 13 /* Comparator1 */ +#define INT_TIMER3 14 /* Timer3 Overflow */ + +#endif diff --git a/device/include/mcs51/C8051T630.h b/device/include/mcs51/C8051T630.h new file mode 100644 index 00000000..fc330d54 --- /dev/null +++ b/device/include/mcs51/C8051T630.h @@ -0,0 +1,337 @@ +/*------------------------------------------------------------------------- + Register Declarations for the SiLabs C8051T63x Processor Range + + Copyright (C) 2008 - Steven Borley, steven.borley@partnerelectronics.com + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +-------------------------------------------------------------------------*/ + +#ifndef C8051T630_H +#define C8051T630_H + +#include + +/* BYTE Registers */ + +SFR( P0, 0x80 ) ; /* PORT 0 */ +SFR( SP, 0x81 ) ; /* STACK POINTER */ +SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */ +SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */ +SFR( TOFFL, 0x85 ) ; /* TEMPERATURE SENSOR OFFSET - LOW BYTE */ +SFR( TOFFH, 0x86 ) ; /* TEMPERATURE SENSOR OFFSET - HIGH BYTE */ +SFR( PCON, 0x87 ) ; /* POWER CONTROL */ +SFR( TCON, 0x88 ) ; /* TIMER CONTROL */ +SFR( TMOD, 0x89 ) ; /* TIMER MODE */ +SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */ +SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */ +SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */ +SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */ +SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */ +SFR( PSCTL, 0x8F ) ; /* PROGRAM STORE R/W CONTROL */ +SFR( P1, 0x90 ) ; /* PORT 1 */ +SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */ +SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ +SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ +SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */ +SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */ +SFR( IDA0L, 0x96 ) ; /* CURRENT MODE DAC 0 - LOW BYTE */ +SFR( IDA0H, 0x97 ) ; /* CURRENT MODE DAC 0 - HIGH BYTE */ +SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */ +SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */ +SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */ +SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */ +SFR( CPT0CN, 0x9B ) ; /* COMPARATOR 0 CONTROL */ +SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */ +SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */ +SFR( P2, 0xA0 ) ; /* PORT 2 */ +SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */ +SFR( SPI0CKR, 0xA2 ) ; /* SPI0 CLOCK RATE CONTROL */ +SFR( SPI0DAT, 0xA3 ) ; /* SPI0 DATA */ +SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */ +SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */ +SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */ +SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */ +SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */ +SFR( EMI0CN, 0xAA ) ; /* EXTERNAL MEMORY INTERFACE CONTROL */ +SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA PAGE */ +SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */ +SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */ +SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */ +SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */ +SFR( IDA0CN, 0xB9 ) ; /* CURRENT MODE DAC 0 - CONTROL */ +SFR( AMX0P, 0xBB ) ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ +SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */ +SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA WORD LSB */ +SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA WORD MSB */ +SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */ +SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */ +SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */ +SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN LOW BYTE */ +SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN HIGH BYTE */ +SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN LOW BYTE */ +SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN HIGH BYTE */ +SFR( REG0CN, 0xC7 ) ; /* Voltage Regulator Control */ +SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */ +SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */ +SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ +SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ +SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */ +SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */ +SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ +SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ +SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */ +SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */ +SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */ +SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */ +SFR( SMB0ADR, 0xD7 ) ; /* SMBUS SLAVE ADDRESS */ +SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */ +SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */ +SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */ +SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */ +SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */ +SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */ +SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */ +SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */ +SFR( OSCLCN, 0xE3 ) ; /* LOW-FREQUENCY OSCILLATOR CONTROL */ +SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ +SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ +SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */ +SFR( SMB0ADM, 0xE7 ) ; /* SMBUS SLAVE ADDRESS MASK */ +SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */ +SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */ +SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */ +SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */ +SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */ +SFR( P1MAT, 0xED ) ; /* PORT 1 MATCH REGISTER */ +SFR( P1MASK, 0xEE ) ; /* PORT 1 MASK REGISTER */ +SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */ +SFR( B, 0xF0 ) ; /* B REGISTER */ +SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ +SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ +SFR( P1MODE, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */ +SFR( P1MDIN, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */ +SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ +SFR( PCA0PWM, 0xF7 ) ; /* PCA PWM CONFIGURATION */ +SFR( SPI0CN, 0xF8 ) ; /* SPI0 CONTROL */ +SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */ +SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */ +SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */ +SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */ +SFR( P0MAT, 0xFD ) ; /* PORT 0 MATCH REGISTER */ +SFR( P0MASK, 0xFE ) ; /* PORT 0 MASK REGISTER */ +SFR( VDM0CN, 0xFF ) ; /* VDD MONITOR CONTROL */ + + +/* WORD/DWORD Registers */ + +SFR16E( TOFF, 0x8685 ) ; /* TEMPERATURE SENSOR OFFSET WORD */ +SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */ +SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */ +SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */ +SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ +SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ +SFR16E( TMR3, 0x9594 ) ; /* TIMER 3 COUNTER */ +SFR16E( TMR3RL, 0x9392 ) ; /* TIMER 3 CAPTURE REGISTER WORD */ +SFR16E( IDA0, 0x9796 ) ; /* CURRENT MODE DAC 0 DATA WORD */ +SFR16E( ADC0, 0xBEBD ) ; /* ADC 0 DATA WORD */ +SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */ +SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */ +SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */ +SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */ +SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */ +SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */ + + +/* BIT Registers */ + +/* P0 0x80 */ +SBIT( P0_0, 0x80, 0 ) ; +SBIT( P0_1, 0x80, 1 ) ; +SBIT( P0_2, 0x80, 2 ) ; +SBIT( P0_3, 0x80, 3 ) ; +SBIT( P0_4, 0x80, 4 ) ; +SBIT( P0_5, 0x80, 5 ) ; +SBIT( P0_6, 0x80, 6 ) ; +SBIT( P0_7, 0x80, 7 ) ; + +/* TCON 0x88 */ +SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ +SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ +SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ +SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ +SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ +SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ +SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ +SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ + +/* P1 0x90 */ +SBIT( P1_0, 0x90, 0 ) ; +SBIT( P1_1, 0x90, 1 ) ; +SBIT( P1_2, 0x90, 2 ) ; +SBIT( P1_3, 0x90, 3 ) ; +SBIT( P1_4, 0x90, 4 ) ; +SBIT( P1_5, 0x90, 5 ) ; +SBIT( P1_6, 0x90, 6 ) ; +SBIT( P1_7, 0x90, 7 ) ; + +/* SCON 0x98 */ +SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ +SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ +SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ +SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ +SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ +SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ +SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ +SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ +SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ +SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ + +/* P2 0xA0 */ +SBIT( P2_0, 0xA0, 0 ) ; +SBIT( P2_1, 0xA0, 1 ) ; +SBIT( P2_2, 0xA0, 2 ) ; +SBIT( P2_3, 0xA0, 3 ) ; +SBIT( P2_4, 0xA0, 4 ) ; +SBIT( P2_5, 0xA0, 5 ) ; +SBIT( P2_6, 0xA0, 6 ) ; +SBIT( P2_7, 0xA0, 7 ) ; + +/* IE 0xA8 */ +SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ +SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ +SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ +SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ +SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ +SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ +SBIT( ESPI0, 0xA8, 6 ) ; /* IE.6 - SPI0 INTERRUPT ENABLE */ +SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ + +/* IP 0xB8 */ +SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ +SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */ +SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ +SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */ +SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ +SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */ +SBIT( PSPI0, 0xB8, 6 ) ; /* IP.6 - SPI0 PRIORITY */ + +/* SMB0CN 0xC0 */ +SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ +SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ +SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ +SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ +SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ +SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */ +SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ +SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ + +/* TMR2CN 0xC8 */ +SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ +SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ +SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ +SBIT( TF2CEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/ +SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ +SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ +SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ +SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ + +/* PSW 0xD0 */ +SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ +SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */ +SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */ +SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */ +SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */ +SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */ +SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */ +SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */ + +/* PCA0CN 0xD8 */ +SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ +SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ +SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ +SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ +SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ + +/* ADC0CN 0xE8 */ +SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ +SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ +SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ +SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ +SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ +SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ +SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */ +SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */ + +/* SPI0CN 0xF8 */ +SBIT( SPIEN, 0xF8, 0 ) ; /* SPI0CN.0 - SPI0 ENABLE */ +SBIT( TXBMT, 0xF8, 1 ) ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ +SBIT( NSSMD0, 0xF8, 2 ) ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ +SBIT( NSSMD1, 0xF8, 3 ) ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ +SBIT( RXOVRN, 0xF8, 4 ) ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ +SBIT( MODF, 0xF8, 5 ) ; /* SPI0CN.5 - MODE FAULT FLAG */ +SBIT( WCOL, 0xF8, 6 ) ; /* SPI0CN.6 - WRITE COLLISION FLAG */ +SBIT( SPIF, 0xF8, 7 ) ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ + + +/* Predefined SFR Bit Masks */ + +#define PCON_IDLE 0x01 /* PCON */ +#define PCON_STOP 0x02 /* PCON */ +#define T1M 0x08 /* CKCON */ +#define PSWE 0x01 /* PSCTL */ +#define PSEE 0x02 /* PSCTL */ +#define ECP0 0x20 /* EIE1 */ +#define PORSF 0x02 /* RSTSRC */ +#define SWRSF 0x10 /* RSTSRC */ +#define ECCF 0x01 /* PCA0CPMn */ +#define PWM 0x02 /* PCA0CPMn */ +#define TOG 0x04 /* PCA0CPMn */ +#define MAT 0x08 /* PCA0CPMn */ +#define CAPN 0x10 /* PCA0CPMn */ +#define CAPP 0x20 /* PCA0CPMn */ +#define ECOM 0x40 /* PCA0CPMn */ +#define PWM16 0x80 /* PCA0CPMn */ +#define CP0E 0x10 /* XBR0 */ +#define CP0OEN 0x10 /* XBR0 */ +#define CP0AE 0x20 /* XBR0 */ +#define CP0AOEN 0x20 /* XBR0 */ + +/* Interrupts */ + +#define INT_EXT0 0 /* External Interrupt 0 */ +#define INT_TIMER0 1 /* Timer0 Overflow */ +#define INT_EXT1 2 /* External Interrupt 1 */ +#define INT_TIMER1 3 /* Timer1 Overflow */ +#define INT_UART0 4 /* Serial Port 0 */ +#define INT_TIMER2 5 /* Timer2 Overflow */ +#define INT_SPI0 6 /* Serial Peripheral Interface 0 */ +#define INT_SMBUS0 7 /* SMBus0 Interface */ +#define INT_PMAT 8 /* Port match */ +#define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */ +#define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */ +#define INT_PCA0 11 /* PCA0 Peripheral */ +#define INT_COMPARATOR0 12 /* Comparator0 */ +/* 13 Reserved */ +#define INT_TIMER3 14 /* Timer3 Overflow */ + +#endif diff --git a/device/include/serial.h b/device/include/serial.h index 527c41ed..e0d06997 100644 --- a/device/include/serial.h +++ b/device/include/serial.h @@ -1,12 +1,12 @@ -//---------------------------------------------------------------------------- -//Written by Dmitry S. Obukhov, 1996 -// dso@usa.net -//---------------------------------------------------------------------------- -//This module implements serial interrupt handler and IO routinwes using -//two 256 byte cyclic buffers. Bit variables can be used as flags for -//real-time kernel tasks -//Last modified 6 Apr 97 -//---------------------------------------------------------------------------- +/*---------------------------------------------------------------------------- + Written by Dmitry S. Obukhov, 1996 + dso@usa.net + ---------------------------------------------------------------------------- + This module implements serial interrupt handler and IO routinwes using + two 256 byte cyclic buffers. Bit variables can be used as flags for + real-time kernel tasks + Last modified 6 Apr 97 + ----------------------------------------------------------------------------*/ void serial_init(void); void serial_interrupt_handler(void) __interrupt 4 __using 1; diff --git a/device/include/stdbool.h b/device/include/stdbool.h index 1144be10..216eb8b4 100644 --- a/device/include/stdbool.h +++ b/device/include/stdbool.h @@ -24,9 +24,9 @@ #define true 1 #define false 0 -// Only define bool for ports that really support it to the full extend. -// For other ports only define BOOL which can be used in most cases, -// but can result in unexpected behaviour +/* Only define bool for ports that really support it to the full extend. + For other ports only define BOOL which can be used in most cases, + but can result in unexpected behaviour */ #if defined (SDCC_hc08) || defined (SDCC_z80) || defined (SDCC_gbz80) || defined (SDCC_pic14) || defined (SDCC_pic16) #define BOOL char diff --git a/device/include/tinibios.h b/device/include/tinibios.h index 4ab9b875..61da3ac0 100644 --- a/device/include/tinibios.h +++ b/device/include/tinibios.h @@ -13,7 +13,7 @@ void Serial0Baud(unsigned long baud); void Serial0SendBreak(void); void Serial0Flush(void); -void Serial0SwitchToBuffered(void); // ds400 only. +void Serial0SwitchToBuffered(void); /* ds400 only. */ void Serial1Init (unsigned long baud, unsigned char buffered); char Serial1GetChar(void); @@ -30,11 +30,11 @@ void ClockMicroSecondsDelay(unsigned int us); #define SERIAL_0_BAUD 115200L #define SERIAL_1_BAUD 9600L -// these need to be binary numbers +/* these need to be binary numbers */ #define SERIAL_0_RECEIVE_BUFFER_SIZE 1024 #define SERIAL_1_RECEIVE_BUFFER_SIZE 64 -// I know someone is fooling with the crystals +/* I know someone is fooling with the crystals */ #if defined(SDCC_ds400) # define OSCILLATOR 14745600L #else @@ -50,15 +50,15 @@ void ClockMicroSecondsDelay(unsigned int us); #define CPU_SPEED 2 void CpuSpeed(unsigned int speed); -// The MOVX stretch cycles, see datasheet +/* The MOVX stretch cycles, see datasheet */ #define CPU_MOVX_STRETCH 0x01 -// from rtc390.c +/* from rtc390.c */ #define HAVE_RTC unsigned char RtcRead(struct tm *rtcDate); void RtcWrite(struct tm *rtcDate); -// from lcd390.c +/* from lcd390.c */ extern void LcdInit(void); extern void LcdOn(void); extern void LcdOff(void); @@ -71,7 +71,7 @@ extern void LcdLPutString(unsigned int collumnRow, char *string); extern void LcdPrintf(const char *format, ...) __reentrant; extern void LcdLPrintf(unsigned int collumnRow, const char *format, ...) __reentrant; -// from i2c390.c +/* from i2c390.c */ #define I2C_BUFSIZE 128 extern char I2CReset(void); extern char I2CStart(void); @@ -81,18 +81,18 @@ extern char I2CSendStop(char addr, char count, extern char I2CReceive(char addr, char count); extern char I2CSendReceive(char addr, char tx_count, char rx_count); -//extern char I2CByteOut(char); -//extern void I2CDumpError(char); +/*extern char I2CByteOut(char);*/ +/*extern void I2CDumpError(char);*/ /* global transfer buffers */ extern char i2cTransmitBuffer[I2C_BUFSIZE]; extern char i2cReceiveBuffer[I2C_BUFSIZE]; -// Macro for normal send transfer ending with a stop condition +/* Macro for normal send transfer ending with a stop condition */ #define I2CSend(addr, count) I2CSendStop(addr, count, 1) -// internal functions used by tinibios.c +/* internal functions used by tinibios.c */ unsigned char _sdcc_external_startup(void); void Serial0IrqHandler (void) __interrupt 4; void Serial1IrqHandler (void) __interrupt 7; @@ -103,13 +103,13 @@ void ClockIrqHandler (void) __interrupt 1 __naked; #endif #if defined(SDCC_ds400) -// functions for dealing with the ds400 ROM firmware. +/* functions for dealing with the ds400 ROM firmware. */ -// A wrapper which calls rom_init allocating all available RAM in CE0 -// to the heap, sets the serial port to SERIAL_0_BAUD, sets up the -// millisecond timer, and diddles the clock multiplier. +/* A wrapper which calls rom_init allocating all available RAM in CE0 + to the heap, sets the serial port to SERIAL_0_BAUD, sets up the + millisecond timer, and diddles the clock multiplier. */ -// Values for the romInit "speed" parameter. +/* Values for the romInit "speed" parameter. */ #define SPEED_1X 0 /* no clock multiplier, normal speed. */ #define SPEED_2X 1 /* 2x clock multiplier. */ #define SPEED_4X 2 /* 4x clock, DOESN'T WORK ON TINIm400! */ @@ -117,7 +117,7 @@ void ClockIrqHandler (void) __interrupt 1 __naked; unsigned char romInit(unsigned char noisy, char speed); -// Install an interrupt handler. +/* Install an interrupt handler. */ void installInterrupt(void (*isrPtr)(void), unsigned char offset); #endif