From: eb Date: Thu, 13 Sep 2007 23:21:41 +0000 (+0000) Subject: Merged r6329:6428 of features/inband-usb + distcheck fixes into trunk. X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=4e7d048aeb80f95b19cebed9d76b79e6cbe64a9a;p=debian%2Fgnuradio Merged r6329:6428 of features/inband-usb + distcheck fixes into trunk. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6429 221aa14e-8319-0410-a670-987f0aec2ac5 --- diff --git a/usrp/fpga/inband_lib/chan_fifo_reader.v b/usrp/fpga/inband_lib/chan_fifo_reader.v index 9392bf15..a6edf2c6 100755 --- a/usrp/fpga/inband_lib/chan_fifo_reader.v +++ b/usrp/fpga/inband_lib/chan_fifo_reader.v @@ -1,7 +1,7 @@ module chan_fifo_reader ( reset, tx_clock, tx_strobe, adc_time, samples_format, fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i, - underrun, tx_empty, debug, rssi, threshhold) ; + underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ; input wire reset ; input wire tx_clock ; @@ -18,6 +18,7 @@ module chan_fifo_reader output reg tx_empty ; //cause 0 to be the output input wire [31:0] rssi; input wire [31:0] threshhold; + input wire [31:0] rssi_wait; output wire [14:0] debug; assign debug = {reader_state, trash, skip, timestamp[4:0], adc_time[4:0]}; @@ -41,18 +42,19 @@ module chan_fifo_reader `define PAYLOAD 8:2 `define ENDOFBURST 27 `define STARTOFBURST 28 - `define RSSI_FLAG 15 + `define RSSI_FLAG 26 /* State registers */ reg [2:0] reader_state; - + /* Local registers */ reg [6:0] payload_len; reg [6:0] read_len; reg [31:0] timestamp; reg burst; reg trash; reg rssi_flag; + reg [31:0] time_wait; always @(posedge tx_clock) begin @@ -68,6 +70,7 @@ module chan_fifo_reader tx_i <= 0; trash <= 0; rssi_flag <= 0; + time_wait <= 0; end else begin @@ -81,13 +84,14 @@ module chan_fifo_reader * is already available to this fifo_reader when pkt_waiting is on */ skip <=0; + time_wait <= 0; if (pkt_waiting == 1) begin reader_state <= HEADER; rdreq <= 1; underrun <= 0; end - else if (burst == 1) + if (burst == 1 && pkt_waiting == 0) underrun <= 1; if (tx_strobe == 1) @@ -139,9 +143,18 @@ module chan_fifo_reader begin if (tx_strobe == 1) tx_empty <= 1 ; - - // Let's send it - if ((timestamp <= adc_time + `JITTER + + time_wait <= time_wait + 32'd1; + // Outdated + if ((timestamp < adc_time) || + (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag)) + begin + trash <= 1; + reader_state <= IDLE; + skip <= 1; + end + // Let's send it + else if ((timestamp <= adc_time + `JITTER && timestamp > adc_time) || timestamp == 32'hFFFFFFFF) begin @@ -153,16 +166,11 @@ module chan_fifo_reader else reader_state <= WAIT; end + else + reader_state <= WAIT; // Wait a little bit more - else if (timestamp > adc_time + `JITTER) - reader_state <= WAIT; - // Outdated - else if (timestamp < adc_time) - begin - trash <= 1; - reader_state <= IDLE; - skip <= 1; - end + //else if (timestamp > adc_time + `JITTER) + // reader_state <= WAIT; end // Wait for the transmit chain to be ready @@ -183,7 +191,7 @@ module chan_fifo_reader end end - // Send the samples to the tx_chain + // Send the samples to the tx_chain SEND: begin reader_state <= WAITSTROBE; diff --git a/usrp/fpga/inband_lib/channel_ram.v b/usrp/fpga/inband_lib/channel_ram.v index 40e0efc0..60450f02 100755 --- a/usrp/fpga/inband_lib/channel_ram.v +++ b/usrp/fpga/inband_lib/channel_ram.v @@ -101,8 +101,8 @@ module channel_ram //packet_waiting is set to zero if rd_done_int is high //because there is no guarantee that nb_packets will be pos. - assign packet_waiting = (nb_packets != 0) & (~rd_done_int); - + //assign packet_waiting = (nb_packets != 0) & (~rd_done_int); + assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int)); always @(posedge txclk) if (reset) nb_packets <= 0; diff --git a/usrp/fpga/inband_lib/packet_builder.v b/usrp/fpga/inband_lib/packet_builder.v index 20529347..fbf0a656 100755 --- a/usrp/fpga/inband_lib/packet_builder.v +++ b/usrp/fpga/inband_lib/packet_builder.v @@ -15,7 +15,8 @@ module packet_builder #(parameter NUM_CHAN = 1)( output reg [15:0]fifodata, input have_space, input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2, - input wire [31:0]rssi_3, output wire [7:0] debugbus); + input wire [31:0]rssi_3, output wire [7:0] debugbus, + input [NUM_CHAN:0] overrun, input [NUM_CHAN:0] underrun); // States @@ -45,12 +46,14 @@ module packet_builder #(parameter NUM_CHAN = 1)( reg [3:0] check_next; wire [8:0] chan_used; wire [31:0] true_rssi; + wire [4:0] true_channel; - assign debugbus = {state, chan_empty[0], chan_empty[1], check_next[0], + assign debugbus = {state, chan_empty[0], underrun[0], check_next[0], have_space, rd_select[0]}; assign chan_used = chan_usedw[8:0]; assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) : - ((rd_select[0]) ? rssi_1:rssi_0); + ((rd_select[0]) ? rssi_1:rssi_0); + assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1}); always @(posedge rxclk) begin if (reset) @@ -64,6 +67,7 @@ module packet_builder #(parameter NUM_CHAN = 1)( end else case (state) `IDLE: begin + chan_rdreq <= #1 0; if (have_space) begin if(~chan_empty[check_next]) @@ -89,13 +93,12 @@ module packet_builder #(parameter NUM_CHAN = 1)( end `HEADER2: begin - fifodata[`CHAN] <= #1 (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1}); + fifodata[`CHAN] <= #1 true_channel; fifodata[`RSSI] <= #1 true_rssi[5:0]; fifodata[`BURST] <= #1 0; fifodata[`DROPPED] <= #1 0; - fifodata[`UNDERRUN] <= #1 0; - fifodata[`OVERRUN] <= #1 0; - + fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel]; + fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel]; state <= #1 `TIMESTAMP; end @@ -117,6 +120,7 @@ module packet_builder #(parameter NUM_CHAN = 1)( begin WR <= #1 0; state <= #1 `IDLE; + chan_rdreq <= #1 0; end else if (read_length == payload_len - 4) chan_rdreq <= #1 0; diff --git a/usrp/fpga/inband_lib/register_io.v b/usrp/fpga/inband_lib/register_io.v index 63a26549..b116b3ac 100755 --- a/usrp/fpga/inband_lib/register_io.v +++ b/usrp/fpga/inband_lib/register_io.v @@ -2,12 +2,14 @@ module register_io (input clk, input reset, input wire [1:0] enable, input wire [6:0] addr, input wire [31:0] datain, output reg [31:0] dataout, output wire [15:0] debugbus, input wire [31:0] rssi_0, input wire [31:0] rssi_1, - input wire [31:0] rssi_2, input wire [31:0] rssi_3, output wire [31:0] threshhold); + input wire [31:0] rssi_2, input wire [31:0] rssi_3, + output wire [31:0] threshhold, output wire [31:0] rssi_wait); reg strobe; wire [31:0] out[7:0]; assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]}; assign threshhold = out[1]; + assign rssi_wait = out[2]; always @(*) if (reset | ~enable[1]) diff --git a/usrp/fpga/inband_lib/rx_buffer_inband.v b/usrp/fpga/inband_lib/rx_buffer_inband.v index c23ce09b..1eaecabe 100755 --- a/usrp/fpga/inband_lib/rx_buffer_inband.v +++ b/usrp/fpga/inband_lib/rx_buffer_inband.v @@ -1,175 +1,179 @@ -//`include "../../firmware/include/fpga_regs_common.v" -//`include "../../firmware/include/fpga_regs_standard.v" -module rx_buffer_inband - ( input usbclk, - input bus_reset, - input reset, // DSP side reset (used here), do not reset registers - input reset_regs, //Only reset registers - output [15:0] usbdata, - input RD, - output wire have_pkt_rdy, - output reg rx_overrun, - input wire [3:0] channels, - input wire [15:0] ch_0, - input wire [15:0] ch_1, - input wire [15:0] ch_2, - input wire [15:0] ch_3, - input wire [15:0] ch_4, - input wire [15:0] ch_5, - input wire [15:0] ch_6, - input wire [15:0] ch_7, - input rxclk, - input rxstrobe, - input clear_status, - input [6:0] serial_addr, - input [31:0] serial_data, - input serial_strobe, - output wire [15:0] debugbus, - - //Connection with tx_inband - input rx_WR, - input [15:0] rx_databus, - input rx_WR_done, - output reg rx_WR_enabled, - //signal strength - input wire [31:0] rssi_0, input wire [31:0] rssi_1, - input wire [31:0] rssi_2, input wire [31:0] rssi_3 - ); - - parameter NUM_CHAN = 1; - genvar i ; - - // FX2 Bug Fix - reg [8:0] read_count; - always @(negedge usbclk) - if(bus_reset) - read_count <= #1 9'd0; - else if(RD & ~read_count[8]) - read_count <= #1 read_count + 9'd1; - else - read_count <= #1 RD ? read_count : 9'b0; - - // Time counter - reg [31:0] adctime; - always @(posedge rxclk) - if (reset) - adctime <= 0; - else if (rxstrobe) - adctime <= adctime + 1; - - // USB side fifo - wire [11:0] rdusedw; - wire [11:0] wrusedw; - wire [15:0] fifodata; - wire WR; - wire have_space; - - fifo_4kx16_dc rx_usb_fifo ( - .aclr ( reset ), - .data ( fifodata ), - .rdclk ( ~usbclk ), - .rdreq ( RD & ~read_count[8] ), - .wrclk ( rxclk ), - .wrreq ( WR ), - .q ( usbdata ), - .rdempty ( ), - .rdusedw ( rdusedw ), - .wrfull ( ), - .wrusedw ( wrusedw ) ); - - assign have_pkt_rdy = (rdusedw >= 12'd256); - assign have_space = (wrusedw < 12'd760); - - // Rx side fifos - wire chan_rdreq; - wire [15:0] chan_fifodata; - wire [9:0] chan_usedw; - wire [NUM_CHAN:0] chan_empty; - wire [3:0] rd_select; - wire [NUM_CHAN:0] rx_full; - - packet_builder #(NUM_CHAN) rx_pkt_builer ( - .rxclk ( rxclk ), - .reset ( reset ), - .adctime ( adctime ), - .channels ( 4'd1 ), - .chan_rdreq ( chan_rdreq ), - .chan_fifodata ( chan_fifodata ), - .chan_empty ( chan_empty ), - .rd_select ( rd_select ), - .chan_usedw ( chan_usedw ), - .WR ( WR ), - .fifodata ( fifodata ), - .have_space ( have_space ), - .rssi_0(rssi_0), .rssi_1(rssi_1), - .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug)); - - // Detect overrun - always @(posedge rxclk) - if(reset) - rx_overrun <= 1'b0; - else if(rx_full[0]) - rx_overrun <= 1'b1; - else if(clear_status) - rx_overrun <= 1'b0; - - reg [6:0] test; - always @(posedge rxclk) - if (reset) - test <= 0; - else - test <= test + 7'd1; - - // TODO write this genericly - wire [15:0]ch[NUM_CHAN:0]; - assign ch[0] = ch_0; - - wire cmd_empty; - always @(posedge rxclk) - if(reset) - rx_WR_enabled <= 1; - else if(cmd_empty) - rx_WR_enabled <= 1; - else if(rx_WR_done) - rx_WR_enabled <= 0; - - wire [15:0] dataout [0:NUM_CHAN]; - wire [9:0] usedw [0:NUM_CHAN]; - - generate for (i = 0 ; i < NUM_CHAN; i = i + 1) - begin : generate_channel_fifos - wire rdreq; - - assign rdreq = (rd_select == i) & chan_rdreq; - assign chan_empty[i] = usedw[i] < 10'd126; - - fifo_2kx16 rx_chan_fifo ( - .aclr ( reset ), - .clock ( rxclk ), - .data ( ch[i] ), - .rdreq ( rdreq ), - .wrreq ( ~rx_full[i] & rxstrobe), - .empty ( ), - .full ( rx_full[i] ), - .q ( dataout[i]), - .usedw ( usedw[i] ) - ); - end - endgenerate - wire [7:0] debug; - fifo_2kx16 rx_cmd_fifo ( - .aclr ( reset ), - .clock ( rxclk ), - .data ( rx_databus ), - .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), - .wrreq ( rx_WR & rx_WR_enabled), - .empty ( cmd_empty), - .full ( rx_full[NUM_CHAN] ), - .q ( dataout[NUM_CHAN]), - .usedw ( usedw[NUM_CHAN] ) - ); - assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; - assign chan_fifodata = dataout[rd_select]; - assign chan_usedw = usedw[rd_select]; - assign debugbus = {wrusedw, have_space, RD, read_count[8], rxclk}; -endmodule +//`include "../../firmware/include/fpga_regs_common.v" +//`include "../../firmware/include/fpga_regs_standard.v" +module rx_buffer_inband + ( input usbclk, + input bus_reset, + input reset, // DSP side reset (used here), do not reset registers + input reset_regs, //Only reset registers + output [15:0] usbdata, + input RD, + output wire have_pkt_rdy, + output reg rx_overrun, + input wire [3:0] channels, + input wire [15:0] ch_0, + input wire [15:0] ch_1, + input wire [15:0] ch_2, + input wire [15:0] ch_3, + input wire [15:0] ch_4, + input wire [15:0] ch_5, + input wire [15:0] ch_6, + input wire [15:0] ch_7, + input rxclk, + input rxstrobe, + input clear_status, + input [6:0] serial_addr, + input [31:0] serial_data, + input serial_strobe, + output wire [15:0] debugbus, + + //Connection with tx_inband + input rx_WR, + input [15:0] rx_databus, + input rx_WR_done, + output reg rx_WR_enabled, + //signal strength + input wire [31:0] rssi_0, input wire [31:0] rssi_1, + input wire [31:0] rssi_2, input wire [31:0] rssi_3, + input wire [1:0] tx_overrun, input wire [1:0] tx_underrun + ); + + parameter NUM_CHAN = 1; + genvar i ; + + // FX2 Bug Fix + reg [8:0] read_count; + always @(negedge usbclk) + if(bus_reset) + read_count <= #1 9'd0; + else if(RD & ~read_count[8]) + read_count <= #1 read_count + 9'd1; + else + read_count <= #1 RD ? read_count : 9'b0; + + // Time counter + reg [31:0] adctime; + always @(posedge rxclk) + if (reset) + adctime <= 0; + else if (rxstrobe) + adctime <= adctime + 1; + + // USB side fifo + wire [11:0] rdusedw; + wire [11:0] wrusedw; + wire [15:0] fifodata; + wire WR; + wire have_space; + + fifo_4kx16_dc rx_usb_fifo ( + .aclr ( reset ), + .data ( fifodata ), + .rdclk ( ~usbclk ), + .rdreq ( RD & ~read_count[8] ), + .wrclk ( rxclk ), + .wrreq ( WR ), + .q ( usbdata ), + .rdempty ( ), + .rdusedw ( rdusedw ), + .wrfull ( ), + .wrusedw ( wrusedw ) ); + + assign have_pkt_rdy = (rdusedw >= 12'd256); + assign have_space = (wrusedw < 12'd760); + + // Rx side fifos + wire chan_rdreq; + wire [15:0] chan_fifodata; + wire [9:0] chan_usedw; + wire [NUM_CHAN:0] chan_empty; + wire [3:0] rd_select; + wire [NUM_CHAN:0] rx_full; + + packet_builder #(NUM_CHAN) rx_pkt_builer ( + .rxclk ( rxclk ), + .reset ( reset ), + .adctime ( adctime ), + .channels ( 4'd1 ), + .chan_rdreq ( chan_rdreq ), + .chan_fifodata ( chan_fifodata ), + .chan_empty ( chan_empty ), + .rd_select ( rd_select ), + .chan_usedw ( chan_usedw ), + .WR ( WR ), + .fifodata ( fifodata ), + .have_space ( have_space ), + .rssi_0(rssi_0), .rssi_1(rssi_1), + .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug), + .overrun(tx_overrun), .underrun(tx_underrun)); + + // Detect overrun + always @(posedge rxclk) + if(reset) + rx_overrun <= 1'b0; + else if(rx_full[0]) + rx_overrun <= 1'b1; + else if(clear_status) + rx_overrun <= 1'b0; + + reg [6:0] test; + always @(posedge rxclk) + if (reset) + test <= 0; + else + test <= test + 7'd1; + + // TODO write this genericly + wire [15:0]ch[NUM_CHAN:0]; + assign ch[0] = ch_0; + + wire cmd_empty; + always @(posedge rxclk) + if(reset) + rx_WR_enabled <= 1; + else if(cmd_empty) + rx_WR_enabled <= 1; + else if(rx_WR_done) + rx_WR_enabled <= 0; + + wire [15:0] dataout [0:NUM_CHAN]; + wire [9:0] usedw [0:NUM_CHAN]; + wire empty[0:NUM_CHAN]; + + generate for (i = 0 ; i < NUM_CHAN; i = i + 1) + begin : generate_channel_fifos + wire rdreq; + + assign rdreq = (rd_select == i) & chan_rdreq; + //assign chan_empty[i] = usedw[i] < 10'd126; + fifo_1kx16 rx_chan_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( ch[i] ), + .rdreq ( rdreq ), + .wrreq ( ~rx_full[i] & rxstrobe), + .empty (empty[i]), + .full (rx_full[i]), + .q ( dataout[i]), + .usedw ( usedw[i]), + .almost_empty(chan_empty[i]) + ); + end + endgenerate + wire [7:0] debug; + fifo_1kx16 rx_cmd_fifo ( + .aclr ( reset ), + .clock ( rxclk ), + .data ( rx_databus ), + .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ), + .wrreq ( rx_WR & rx_WR_enabled), + .empty ( cmd_empty), + .full ( rx_full[NUM_CHAN] ), + .q ( dataout[NUM_CHAN]), + .usedw ( usedw[NUM_CHAN] ) + ); + assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled; + assign chan_fifodata = dataout[rd_select]; + assign chan_usedw = usedw[rd_select]; + assign debugbus = {rxstrobe, chan_rdreq, debug, + rx_full[0], chan_empty[0], empty[0], have_space, RD, rxclk}; +endmodule diff --git a/usrp/fpga/inband_lib/tx_buffer_inband.v b/usrp/fpga/inband_lib/tx_buffer_inband.v index af7ed394..fec9dbe3 100755 --- a/usrp/fpga/inband_lib/tx_buffer_inband.v +++ b/usrp/fpga/inband_lib/tx_buffer_inband.v @@ -1,18 +1,13 @@ module tx_buffer_inband ( usbclk, bus_reset, reset, usbdata, WR, have_space, - tx_underrun, channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1, + channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1, tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe, clear_status, tx_empty, debugbus, rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable, reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2, - rssi_3, threshhold + rssi_3, rssi_wait, threshhold, tx_underrun ); - - //CHAN_WIDTH is the width of the channel - //NUM_CHAN is the number of data channel (index from 0 to NUM_CHAN-1) - //index NUM_CHAN is reserved for command - parameter CHAN_WIDTH = 2 ; parameter NUM_CHAN = 2 ; /* Debug paramters */ parameter STROBE_RATE_0 = 8'd1 ; @@ -37,9 +32,9 @@ module tx_buffer_inband input wire [31:0]rssi_2; input wire [31:0]rssi_3; input wire [31:0]threshhold; - + input wire [31:0]rssi_wait; + output wire have_space ; - output wire tx_underrun ; output wire tx_empty ; output wire [15:0] tx_i_0 ; output wire [15:0] tx_q_0 ; @@ -59,13 +54,14 @@ module tx_buffer_inband output wire [31:0] reg_data_in; output wire [6:0] reg_addr; output wire [1:0] reg_io_enable; + output wire [NUM_CHAN-1:0] tx_underrun; /* To generate channel readers */ genvar i ; /* These will eventually be external register */ reg [31:0] adc_time ; - wire [7:0] txstrobe_rate [CHAN_WIDTH-1:0] ; + wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ; wire [31:0] rssi [3:0]; assign rssi[0] = rssi_0; assign rssi[1] = rssi_1; @@ -82,33 +78,32 @@ module tx_buffer_inband /* Connections between tx_usb_fifo_reader and cnannel/command processing blocks */ wire [31:0] tx_data_bus ; - wire [CHAN_WIDTH:0] chan_WR ; - wire [CHAN_WIDTH:0] chan_done ; + wire [NUM_CHAN:0] chan_WR ; + wire [NUM_CHAN:0] chan_done ; /* Connections between data block and the FX2/TX chains */ - wire [CHAN_WIDTH:0] chan_underrun ; - wire [CHAN_WIDTH:0] chan_txempty ; + wire [NUM_CHAN:0] chan_underrun ; + wire [NUM_CHAN:0] chan_txempty ; /* Conections between tx_data_packet_fifo and its reader + strobe generator */ - wire [31:0] chan_fifodata [CHAN_WIDTH:0] ; - wire chan_pkt_waiting [CHAN_WIDTH:0] ; - wire chan_rdreq [CHAN_WIDTH:0] ; - wire chan_skip [CHAN_WIDTH:0] ; - wire [CHAN_WIDTH:0] chan_have_space ; - wire chan_txstrobe [CHAN_WIDTH-1:0] ; + wire [31:0] chan_fifodata [NUM_CHAN:0] ; + wire chan_pkt_waiting [NUM_CHAN:0] ; + wire chan_rdreq [NUM_CHAN:0] ; + wire chan_skip [NUM_CHAN:0] ; + wire [NUM_CHAN:0] chan_have_space ; + wire chan_txstrobe [NUM_CHAN-1:0] ; wire [14:0] debug; /* Outputs to transmit chains */ - wire [15:0] tx_i [CHAN_WIDTH-1:0] ; - wire [15:0] tx_q [CHAN_WIDTH-1:0] ; + wire [15:0] tx_i [NUM_CHAN-1:0] ; + wire [15:0] tx_q [NUM_CHAN-1:0] ; /* TODO: Figure out how to write this genericly */ assign have_space = chan_have_space[0] & chan_have_space[1]; assign tx_empty = chan_txempty[0] & chan_txempty[1] ; - assign tx_underrun = chan_underrun[0] | chan_underrun[1] ; assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ; assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ; assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ; @@ -153,6 +148,7 @@ module tx_buffer_inband generate for (i = 0 ; i < NUM_CHAN; i = i + 1) begin : generate_channel_readers + assign tx_underrun[i] = chan_underrun[i]; channel_ram tx_data_packet_fifo ( .reset (reset), .txclk (txclk), @@ -181,7 +177,8 @@ module tx_buffer_inband .pkt_waiting (chan_pkt_waiting[i]), .tx_empty (chan_txempty[i]), .rssi (rssi[i]), - .threshhold (threshhold) + .threshhold (threshhold), + .rssi_wait (rssi_wait) ); end diff --git a/usrp/fpga/megacells/fifo_1kx16.bsf b/usrp/fpga/megacells/fifo_1kx16.bsf new file mode 100755 index 00000000..329be2d4 --- /dev/null +++ b/usrp/fpga/megacells/fifo_1kx16.bsf @@ -0,0 +1,107 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 160) + (text "fifo_1kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 144 25 156)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 122 37 135)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 56) + (output) + (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) + (line (pt 160 56)(pt 144 56)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 1)) + ) + (port + (pt 160 88) + (output) + (text "almost_empty" (rect 0 0 77 14)(font "Arial" (font_size 8))) + (text "almost_empty" (rect 75 82 141 95)(font "Arial" (font_size 8))) + (line (pt 160 88)(pt 144 88)(line_width 1)) + ) + (port + (pt 160 104) + (output) + (text "usedw[9..0]" (rect 0 0 68 14)(font "Arial" (font_size 8))) + (text "usedw[9..0]" (rect 83 98 136 111)(font "Arial" (font_size 8))) + (line (pt 160 104)(pt 144 104)(line_width 3)) + ) + (drawing + (text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial" )) + (text "almost_empty < 126" (rect 58 122 144 134)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 144)(line_width 1)) + (line (pt 144 144)(pt 16 144)(line_width 1)) + (line (pt 16 144)(pt 16 16)(line_width 1)) + (line (pt 16 116)(pt 144 116)(line_width 1)) + (line (pt 16 90)(pt 22 96)(line_width 1)) + (line (pt 22 96)(pt 16 102)(line_width 1)) + ) +) diff --git a/usrp/fpga/megacells/fifo_1kx16.cmp b/usrp/fpga/megacells/fifo_1kx16.cmp new file mode 100755 index 00000000..9b2c2c0c --- /dev/null +++ b/usrp/fpga/megacells/fifo_1kx16.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo_1kx16 + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + almost_empty : OUT STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +end component; diff --git a/usrp/fpga/megacells/fifo_1kx16.inc b/usrp/fpga/megacells/fifo_1kx16.inc new file mode 100755 index 00000000..0b70afe6 --- /dev/null +++ b/usrp/fpga/megacells/fifo_1kx16.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION fifo_1kx16 +( + aclr, + clock, + data[15..0], + rdreq, + wrreq +) + +RETURNS ( + almost_empty, + empty, + full, + q[15..0], + usedw[9..0] +); diff --git a/usrp/fpga/megacells/fifo_1kx16.v b/usrp/fpga/megacells/fifo_1kx16.v new file mode 100755 index 00000000..e22b416e --- /dev/null +++ b/usrp/fpga/megacells/fifo_1kx16.v @@ -0,0 +1,175 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_1kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_1kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + almost_empty, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output almost_empty; + output empty; + output full; + output [15:0] q; + output [9:0] usedw; + + wire [9:0] sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire sub_wire4; + wire [9:0] usedw = sub_wire0[9:0]; + wire empty = sub_wire1; + wire almost_empty = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire full = sub_wire4; + + scfifo scfifo_component ( + .rdreq (rdreq), + .aclr (aclr), + .clock (clock), + .wrreq (wrreq), + .data (data), + .usedw (sub_wire0), + .empty (sub_wire1), + .almost_empty (sub_wire2), + .q (sub_wire3), + .full (sub_wire4) + // synopsys translate_off + , + .sclr (), + .almost_full () + // synopsys translate_on + ); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.almost_empty_value = 126, + scfifo_component.intended_device_family = "Cyclone", + scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", + scfifo_component.lpm_numwords = 1024, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 16, + scfifo_component.lpm_widthu = 10, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE diff --git a/usrp/fpga/megacells/fifo_1kx16_bb.v b/usrp/fpga/megacells/fifo_1kx16_bb.v new file mode 100755 index 00000000..283aada8 --- /dev/null +++ b/usrp/fpga/megacells/fifo_1kx16_bb.v @@ -0,0 +1,127 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_1kx16.v +// Megafunction Name(s): +// scfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_1kx16 ( + aclr, + clock, + data, + rdreq, + wrreq, + almost_empty, + empty, + full, + q, + usedw); + + input aclr; + input clock; + input [15:0] data; + input rdreq; + input wrreq; + output almost_empty; + output empty; + output full; + output [15:0] q; + output [9:0] usedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty +// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE diff --git a/usrp/fpga/megacells/fifo_1kx16_inst.v b/usrp/fpga/megacells/fifo_1kx16_inst.v new file mode 100755 index 00000000..73662dea --- /dev/null +++ b/usrp/fpga/megacells/fifo_1kx16_inst.v @@ -0,0 +1,12 @@ +fifo_1kx16 fifo_1kx16_inst ( + .aclr ( aclr_sig ), + .clock ( clock_sig ), + .data ( data_sig ), + .rdreq ( rdreq_sig ), + .wrreq ( wrreq_sig ), + .almost_empty ( almost_empty_sig ), + .empty ( empty_sig ), + .full ( full_sig ), + .q ( q_sig ), + .usedw ( usedw_sig ) + ); diff --git a/usrp/fpga/megacells/fifo_2k_1clk.v b/usrp/fpga/megacells/fifo_2k_1clk.v deleted file mode 100755 index 095615bb..00000000 --- a/usrp/fpga/megacells/fifo_2k_1clk.v +++ /dev/null @@ -1,167 +0,0 @@ -// megafunction wizard: %LPM_FIFO+% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_2k_1clk.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_2k_1clk ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [9:0] usedw; - - wire [9:0] sub_wire0; - wire sub_wire1; - wire [15:0] sub_wire2; - wire sub_wire3; - wire [9:0] usedw = sub_wire0[9:0]; - wire empty = sub_wire1; - wire [15:0] q = sub_wire2[15:0]; - wire full = sub_wire3; - - scfifo scfifo_component ( - .rdreq (rdreq), - .aclr (aclr), - .clock (clock), - .wrreq (wrreq), - .data (data), - .usedw (sub_wire0), - .empty (sub_wire1), - .q (sub_wire2), - .full (sub_wire3) - // synopsys translate_off - , - .almost_empty (), - .sclr (), - .almost_full () - // synopsys translate_on - ); - defparam - scfifo_component.add_ram_output_register = "OFF", - scfifo_component.intended_device_family = "Cyclone", - scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", - scfifo_component.lpm_numwords = 1024, - scfifo_component.lpm_showahead = "OFF", - scfifo_component.lpm_type = "scfifo", - scfifo_component.lpm_width = 16, - scfifo_component.lpm_widthu = 10, - scfifo_component.overflow_checking = "ON", - scfifo_component.underflow_checking = "ON", - scfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "1024" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_waveforms.html FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_wave*.jpg FALSE diff --git a/usrp/fpga/megacells/fifo_2kx16.bsf b/usrp/fpga/megacells/fifo_2kx16.bsf deleted file mode 100755 index 1067991f..00000000 --- a/usrp/fpga/megacells/fifo_2kx16.bsf +++ /dev/null @@ -1,99 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2006 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 144) - (text "fifo_2kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 128 25 140)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 114 37 127)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 16 120)(line_width 1)) - ) - (port - (pt 160 32) - (output) - (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) - (line (pt 160 32)(pt 144 32)(line_width 3)) - ) - (port - (pt 160 56) - (output) - (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) - (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) - (line (pt 160 56)(pt 144 56)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 144 72)(line_width 1)) - ) - (port - (pt 160 88) - (output) - (text "usedw[10..0]" (rect 0 0 75 14)(font "Arial" (font_size 8))) - (text "usedw[10..0]" (rect 77 82 136 95)(font "Arial" (font_size 8))) - (line (pt 160 88)(pt 144 88)(line_width 3)) - ) - (drawing - (text "16 bits x 2048 words" (rect 58 116 144 128)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 128)(line_width 1)) - (line (pt 144 128)(pt 16 128)(line_width 1)) - (line (pt 16 128)(pt 16 16)(line_width 1)) - (line (pt 16 108)(pt 144 108)(line_width 1)) - (line (pt 16 90)(pt 22 96)(line_width 1)) - (line (pt 22 96)(pt 16 102)(line_width 1)) - ) -) diff --git a/usrp/fpga/megacells/fifo_2kx16.cmp b/usrp/fpga/megacells/fifo_2kx16.cmp deleted file mode 100755 index 96c34d8d..00000000 --- a/usrp/fpga/megacells/fifo_2kx16.cmp +++ /dev/null @@ -1,29 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component fifo_2kx16 - PORT - ( - aclr : IN STD_LOGIC ; - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - rdreq : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - empty : OUT STD_LOGIC ; - full : OUT STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) - ); -end component; diff --git a/usrp/fpga/megacells/fifo_2kx16.inc b/usrp/fpga/megacells/fifo_2kx16.inc deleted file mode 100755 index 3d72c660..00000000 --- a/usrp/fpga/megacells/fifo_2kx16.inc +++ /dev/null @@ -1,30 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION fifo_2kx16 -( - aclr, - clock, - data[15..0], - rdreq, - wrreq -) - -RETURNS ( - empty, - full, - q[15..0], - usedw[10..0] -); diff --git a/usrp/fpga/megacells/fifo_2kx16.v b/usrp/fpga/megacells/fifo_2kx16.v deleted file mode 100755 index eb229769..00000000 --- a/usrp/fpga/megacells/fifo_2kx16.v +++ /dev/null @@ -1,167 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_2kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_2kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [10:0] usedw; - - wire [10:0] sub_wire0; - wire sub_wire1; - wire [15:0] sub_wire2; - wire sub_wire3; - wire [10:0] usedw = sub_wire0[10:0]; - wire empty = sub_wire1; - wire [15:0] q = sub_wire2[15:0]; - wire full = sub_wire3; - - scfifo scfifo_component ( - .rdreq (rdreq), - .aclr (aclr), - .clock (clock), - .wrreq (wrreq), - .data (data), - .usedw (sub_wire0), - .empty (sub_wire1), - .q (sub_wire2), - .full (sub_wire3) - // synopsys translate_off - , - .almost_empty (), - .sclr (), - .almost_full () - // synopsys translate_on - ); - defparam - scfifo_component.add_ram_output_register = "OFF", - scfifo_component.intended_device_family = "Cyclone", - scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", - scfifo_component.lpm_numwords = 2048, - scfifo_component.lpm_showahead = "OFF", - scfifo_component.lpm_type = "scfifo", - scfifo_component.lpm_width = 16, - scfifo_component.lpm_widthu = 11, - scfifo_component.overflow_checking = "ON", - scfifo_component.underflow_checking = "ON", - scfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "2048" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL usedw[10..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_wave*.jpg FALSE diff --git a/usrp/fpga/megacells/fifo_2kx16_bb.v b/usrp/fpga/megacells/fifo_2kx16_bb.v deleted file mode 100755 index 507bac07..00000000 --- a/usrp/fpga/megacells/fifo_2kx16_bb.v +++ /dev/null @@ -1,122 +0,0 @@ -// megafunction wizard: %FIFO%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_2kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - -module fifo_2kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [10:0] usedw; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "2048" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL usedw[10..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_wave*.jpg FALSE diff --git a/usrp/fpga/megacells/fifo_2kx16_inst.v b/usrp/fpga/megacells/fifo_2kx16_inst.v deleted file mode 100755 index 6185c6fe..00000000 --- a/usrp/fpga/megacells/fifo_2kx16_inst.v +++ /dev/null @@ -1,11 +0,0 @@ -fifo_2kx16 fifo_2kx16_inst ( - .aclr ( aclr_sig ), - .clock ( clock_sig ), - .data ( data_sig ), - .rdreq ( rdreq_sig ), - .wrreq ( wrreq_sig ), - .empty ( empty_sig ), - .full ( full_sig ), - .q ( q_sig ), - .usedw ( usedw_sig ) - ); diff --git a/usrp/fpga/megacells/fifo_4kx16.bsf b/usrp/fpga/megacells/fifo_4kx16.bsf deleted file mode 100755 index 4d988c5e..00000000 --- a/usrp/fpga/megacells/fifo_4kx16.bsf +++ /dev/null @@ -1,99 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2006 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 144) - (text "fifo_4kx16" (rect 51 1 119 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 128 25 140)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 114 37 127)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 16 120)(line_width 1)) - ) - (port - (pt 160 32) - (output) - (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) - (line (pt 160 32)(pt 144 32)(line_width 3)) - ) - (port - (pt 160 56) - (output) - (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) - (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8))) - (line (pt 160 56)(pt 144 56)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "empty" (rect 112 66 141 79)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 144 72)(line_width 1)) - ) - (port - (pt 160 88) - (output) - (text "usedw[11..0]" (rect 0 0 75 14)(font "Arial" (font_size 8))) - (text "usedw[11..0]" (rect 77 82 136 95)(font "Arial" (font_size 8))) - (line (pt 160 88)(pt 144 88)(line_width 3)) - ) - (drawing - (text "16 bits x 4096 words" (rect 58 116 144 128)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 128)(line_width 1)) - (line (pt 144 128)(pt 16 128)(line_width 1)) - (line (pt 16 128)(pt 16 16)(line_width 1)) - (line (pt 16 108)(pt 144 108)(line_width 1)) - (line (pt 16 90)(pt 22 96)(line_width 1)) - (line (pt 22 96)(pt 16 102)(line_width 1)) - ) -) diff --git a/usrp/fpga/megacells/fifo_4kx16.cmp b/usrp/fpga/megacells/fifo_4kx16.cmp deleted file mode 100755 index 7bc6941d..00000000 --- a/usrp/fpga/megacells/fifo_4kx16.cmp +++ /dev/null @@ -1,29 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component fifo_4kx16 - PORT - ( - aclr : IN STD_LOGIC ; - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - rdreq : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - empty : OUT STD_LOGIC ; - full : OUT STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - usedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) - ); -end component; diff --git a/usrp/fpga/megacells/fifo_4kx16.inc b/usrp/fpga/megacells/fifo_4kx16.inc deleted file mode 100755 index db5d4f29..00000000 --- a/usrp/fpga/megacells/fifo_4kx16.inc +++ /dev/null @@ -1,30 +0,0 @@ ---Copyright (C) 1991-2006 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION fifo_4kx16 -( - aclr, - clock, - data[15..0], - rdreq, - wrreq -) - -RETURNS ( - empty, - full, - q[15..0], - usedw[11..0] -); diff --git a/usrp/fpga/megacells/fifo_4kx16.v b/usrp/fpga/megacells/fifo_4kx16.v deleted file mode 100755 index c5ecfbae..00000000 --- a/usrp/fpga/megacells/fifo_4kx16.v +++ /dev/null @@ -1,167 +0,0 @@ -// megafunction wizard: %FIFO% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_4kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module fifo_4kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [11:0] usedw; - - wire [11:0] sub_wire0; - wire sub_wire1; - wire [15:0] sub_wire2; - wire sub_wire3; - wire [11:0] usedw = sub_wire0[11:0]; - wire empty = sub_wire1; - wire [15:0] q = sub_wire2[15:0]; - wire full = sub_wire3; - - scfifo scfifo_component ( - .rdreq (rdreq), - .aclr (aclr), - .clock (clock), - .wrreq (wrreq), - .data (data), - .usedw (sub_wire0), - .empty (sub_wire1), - .q (sub_wire2), - .full (sub_wire3) - // synopsys translate_off - , - .almost_empty (), - .sclr (), - .almost_full () - // synopsys translate_on - ); - defparam - scfifo_component.add_ram_output_register = "OFF", - scfifo_component.intended_device_family = "Cyclone", - scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", - scfifo_component.lpm_numwords = 4096, - scfifo_component.lpm_showahead = "OFF", - scfifo_component.lpm_type = "scfifo", - scfifo_component.lpm_width = 16, - scfifo_component.lpm_widthu = 12, - scfifo_component.overflow_checking = "ON", - scfifo_component.underflow_checking = "ON", - scfifo_component.use_eab = "ON"; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "4096" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 12 0 OUTPUT NODEFVAL usedw[11..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 12 0 @usedw 0 0 12 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_wave*.jpg FALSE diff --git a/usrp/fpga/megacells/fifo_4kx16_bb.v b/usrp/fpga/megacells/fifo_4kx16_bb.v deleted file mode 100755 index d41e9f09..00000000 --- a/usrp/fpga/megacells/fifo_4kx16_bb.v +++ /dev/null @@ -1,122 +0,0 @@ -// megafunction wizard: %FIFO%VBB% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: scfifo - -// ============================================================ -// File Name: fifo_4kx16.v -// Megafunction Name(s): -// scfifo -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition -// ************************************************************ - -//Copyright (C) 1991-2006 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - -module fifo_4kx16 ( - aclr, - clock, - data, - rdreq, - wrreq, - empty, - full, - q, - usedw); - - input aclr; - input clock; - input [15:0] data; - input rdreq; - input wrreq; - output empty; - output full; - output [15:0] q; - output [11:0] usedw; - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" -// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" -// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" -// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" -// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" -// Retrieval info: PRIVATE: Clock NUMERIC "0" -// Retrieval info: PRIVATE: Depth NUMERIC "4096" -// Retrieval info: PRIVATE: Empty NUMERIC "1" -// Retrieval info: PRIVATE: Full NUMERIC "1" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" -// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" -// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" -// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: Optimize NUMERIC "2" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" -// Retrieval info: PRIVATE: UsedW NUMERIC "1" -// Retrieval info: PRIVATE: Width NUMERIC "16" -// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" -// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" -// Retrieval info: PRIVATE: rsFull NUMERIC "0" -// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" -// Retrieval info: PRIVATE: sc_aclr NUMERIC "1" -// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" -// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" -// Retrieval info: PRIVATE: wsFull NUMERIC "1" -// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" -// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K" -// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" -// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" -// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" -// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" -// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" -// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" -// Retrieval info: CONSTANT: USE_EAB STRING "ON" -// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] -// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty -// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full -// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq -// Retrieval info: USED_PORT: usedw 0 0 12 0 OUTPUT NODEFVAL usedw[11..0] -// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq -// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 -// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 -// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 -// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 -// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 -// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 -// Retrieval info: CONNECT: usedw 0 0 12 0 @usedw 0 0 12 0 -// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.inc TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.cmp TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16.bsf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_inst.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_bb.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_waveforms.html TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_wave*.jpg FALSE diff --git a/usrp/fpga/megacells/fifo_4kx16_dc.bsf b/usrp/fpga/megacells/fifo_4kx16_dc.bsf new file mode 100755 index 00000000..b80add8d --- /dev/null +++ b/usrp/fpga/megacells/fifo_4kx16_dc.bsf @@ -0,0 +1,117 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2006 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 184) + (text "fifo_4kx16_dc" (rect 41 1 134 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 168 25 180)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 16 160)(line_width 1)) + ) + (port + (pt 160 40) + (output) + (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8))) + (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8))) + (line (pt 160 40)(pt 144 40)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "wrusedw[11..0]" (rect 0 0 92 14)(font "Arial" (font_size 8))) + (text "wrusedw[11..0]" (rect 63 66 132 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 3)) + ) + (port + (pt 160 96) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (port + (pt 160 120) + (output) + (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8))) + (text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8))) + (line (pt 160 120)(pt 144 120)(line_width 1)) + ) + (port + (pt 160 136) + (output) + (text "rdusedw[11..0]" (rect 0 0 87 14)(font "Arial" (font_size 8))) + (text "rdusedw[11..0]" (rect 67 130 135 143)(font "Arial" (font_size 8))) + (line (pt 160 136)(pt 144 136)(line_width 3)) + ) + (drawing + (text "(ack)" (rect 51 99 72 111)(font "Arial" )) + (text "16 bits x 4096 words" (rect 58 156 144 168)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 168)(line_width 1)) + (line (pt 144 168)(pt 16 168)(line_width 1)) + (line (pt 16 168)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 148)(pt 144 148)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/usrp/fpga/megacells/fifo_4kx16_dc.cmp b/usrp/fpga/megacells/fifo_4kx16_dc.cmp new file mode 100755 index 00000000..356de4d6 --- /dev/null +++ b/usrp/fpga/megacells/fifo_4kx16_dc.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component fifo_4kx16_dc + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); + wrfull : OUT STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) + ); +end component; diff --git a/usrp/fpga/megacells/fifo_4kx16_dc.inc b/usrp/fpga/megacells/fifo_4kx16_dc.inc new file mode 100755 index 00000000..c14c0183 --- /dev/null +++ b/usrp/fpga/megacells/fifo_4kx16_dc.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2006 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION fifo_4kx16_dc +( + aclr, + data[15..0], + rdclk, + rdreq, + wrclk, + wrreq +) + +RETURNS ( + q[15..0], + rdempty, + rdusedw[11..0], + wrfull, + wrusedw[11..0] +); diff --git a/usrp/fpga/megacells/fifo_4kx16_dc.v b/usrp/fpga/megacells/fifo_4kx16_dc.v new file mode 100755 index 00000000..1f09000e --- /dev/null +++ b/usrp/fpga/megacells/fifo_4kx16_dc.v @@ -0,0 +1,178 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4kx16_dc.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_4kx16_dc ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdusedw, + wrfull, + wrusedw); + + input aclr; + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + + wire sub_wire0; + wire [11:0] sub_wire1; + wire sub_wire2; + wire [15:0] sub_wire3; + wire [11:0] sub_wire4; + wire rdempty = sub_wire0; + wire [11:0] wrusedw = sub_wire1[11:0]; + wire wrfull = sub_wire2; + wire [15:0] q = sub_wire3[15:0]; + wire [11:0] rdusedw = sub_wire4[11:0]; + + dcfifo dcfifo_component ( + .wrclk (wrclk), + .rdreq (rdreq), + .aclr (aclr), + .rdclk (rdclk), + .wrreq (wrreq), + .data (data), + .rdempty (sub_wire0), + .wrusedw (sub_wire1), + .wrfull (sub_wire2), + .q (sub_wire3), + .rdusedw (sub_wire4) + // synopsys translate_off + , + .wrempty (), + .rdfull () + // synopsys translate_on + ); + defparam + dcfifo_component.add_ram_output_register = "OFF", + dcfifo_component.clocks_are_synchronized = "FALSE", + dcfifo_component.intended_device_family = "Cyclone", + dcfifo_component.lpm_numwords = 4096, + dcfifo_component.lpm_showahead = "ON", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 16, + dcfifo_component.lpm_widthu = 12, + dcfifo_component.overflow_checking = "OFF", + dcfifo_component.underflow_checking = "OFF", + dcfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE diff --git a/usrp/fpga/megacells/fifo_4kx16_dc_bb.v b/usrp/fpga/megacells/fifo_4kx16_dc_bb.v new file mode 100755 index 00000000..91c3c322 --- /dev/null +++ b/usrp/fpga/megacells/fifo_4kx16_dc_bb.v @@ -0,0 +1,130 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_4kx16_dc.v +// Megafunction Name(s): +// dcfifo +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2006 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_4kx16_dc ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdempty, + rdusedw, + wrfull, + wrusedw); + + input aclr; + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output rdempty; + output [11:0] rdusedw; + output wrfull; + output [11:0] wrusedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "4096" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0] +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0] +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0 +// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 +// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0 +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE diff --git a/usrp/fpga/megacells/fifo_4kx16_dc_inst.v b/usrp/fpga/megacells/fifo_4kx16_dc_inst.v new file mode 100755 index 00000000..566f27a1 --- /dev/null +++ b/usrp/fpga/megacells/fifo_4kx16_dc_inst.v @@ -0,0 +1,13 @@ +fifo_4kx16_dc fifo_4kx16_dc_inst ( + .aclr ( aclr_sig ), + .data ( data_sig ), + .rdclk ( rdclk_sig ), + .rdreq ( rdreq_sig ), + .wrclk ( wrclk_sig ), + .wrreq ( wrreq_sig ), + .q ( q_sig ), + .rdempty ( rdempty_sig ), + .rdusedw ( rdusedw_sig ), + .wrfull ( wrfull_sig ), + .wrusedw ( wrusedw_sig ) + ); diff --git a/usrp/fpga/megacells/fifo_4kx16_inst.v b/usrp/fpga/megacells/fifo_4kx16_inst.v deleted file mode 100755 index eb260aca..00000000 --- a/usrp/fpga/megacells/fifo_4kx16_inst.v +++ /dev/null @@ -1,11 +0,0 @@ -fifo_4kx16 fifo_4kx16_inst ( - .aclr ( aclr_sig ), - .clock ( clock_sig ), - .data ( data_sig ), - .rdreq ( rdreq_sig ), - .wrreq ( wrreq_sig ), - .empty ( empty_sig ), - .full ( full_sig ), - .q ( q_sig ), - .usedw ( usedw_sig ) - ); diff --git a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf b/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf index 6b476407..c9eebc1a 100644 --- a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf +++ b/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf @@ -372,14 +372,14 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps" +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4kx16_dc.v +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16.v set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_packer.v set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k_1clk.v set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1k.v set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v diff --git a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v b/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v index 3bfdda56..cc625b0e 100644 --- a/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v +++ b/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v @@ -74,10 +74,10 @@ module usrp_inband_usb assign usbrdy[0] = have_space; assign usbrdy[1] = have_pkt_rdy; - wire tx_underrun, rx_overrun; + wire rx_overrun; wire clear_status = FX2_1; assign FX2_2 = rx_overrun; - assign FX2_3 = tx_underrun; + assign FX2_3 = (tx_underrun == 0); wire [15:0] usbdata_out; @@ -135,16 +135,20 @@ wire [31:0] reg_data_out; wire [31:0] reg_data_in; wire [1:0] reg_io_enable; wire [31:0] rssi_threshhold; +wire [31:0] rssi_wait; + register_io register_control (.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in), .dataout(reg_data_out),.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), - .rssi_3(rssi_3), .threshhold(rssi_threshhold)); + .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait)); +wire [1:0] tx_overrun; +wire [1:0] tx_underrun; `ifdef TX_IN_BAND tx_buffer_inband tx_buffer ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), - .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), - .channels({tx_numchan,1'b0}), + .usbdata(usbdata),.WR(WR),.have_space(have_space), + .tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}), .tx_i_0(ch0tx),.tx_q_0(ch1tx), .tx_i_1(ch2tx),.tx_q_1(ch3tx), .tx_i_2(),.tx_q_2(), @@ -160,9 +164,9 @@ register_io register_control .reg_data_out(reg_data_out), .reg_data_in(reg_data_in), .reg_io_enable(reg_io_enable), - .debugbus(tx_debugbus), + .debugbus(), .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), - .rssi_3(rssi_3), .threshhold(rssi_threshhold)); + .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait)); `else tx_buffer tx_buffer ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), @@ -277,8 +281,9 @@ register_io register_control .rx_databus(rx_databus), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled), - .debugbus(rx_debugbus), - .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3)); + .debugbus(tx_debugbus), + .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3), + .tx_overrun(tx_overrun), .tx_underrun(tx_underrun)); `else rx_buffer rx_buffer ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), @@ -291,8 +296,7 @@ register_io register_control .ch_6(ch6rx),.ch_7(ch7rx), .rxclk(clk64),.rxstrobe(hb_strobe), .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)/*, - .debugbus(rx_debugbus)*/); + .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); `endif `ifdef RX_EN_0 @@ -371,7 +375,7 @@ register_io register_control .tx_empty(tx_empty), //.debug_0(rx_a_a),.debug_1(ddc0_in_i), .debug_0(tx_debugbus),.debug_1(tx_debugbus), - .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), + .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,(tx_underrun == 0),rx_overrun,decim_rate}), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); io_pins io_pins diff --git a/usrp/host/apps-inband/Makefile.am b/usrp/host/apps-inband/Makefile.am index 0faeb7f4..c05f04af 100644 --- a/usrp/host/apps-inband/Makefile.am +++ b/usrp/host/apps-inband/Makefile.am @@ -35,12 +35,29 @@ noinst_PROGRAMS = \ test_usrp_inband_rx \ test_usrp_inband_tx \ test_usrp_inband_timestamps \ + test_usrp_inband_overrun \ test_usrp_inband_underrun \ + test_gmac_tx \ read_packets noinst_HEADERS = \ ui_nco.h \ - ui_sincos.h + ui_sincos.h \ + gmac.h \ + gmac_symbols.h + + +EXTRA_DIST = \ + gmac.mbh + +#------------------------------------------------------------------ +# Build gmac sources + +BUILT_SOURCES = \ + gmac_mbh.cc + +gmac_mbh.cc : gmac.mbh + $(COMPILE_MBH) $(srcdir)/gmac.mbh gmac_mbh.cc test_usrp_inband_cs_SOURCES = test_usrp_inband_cs.cc ui_sincos.c @@ -58,11 +75,17 @@ test_usrp_inband_timestamps_LDADD = $(USRP_LA) $(USRP_INBAND_LA) test_usrp_inband_registers_SOURCES = test_usrp_inband_registers.cc ui_sincos.c test_usrp_inband_registers_LDADD = $(USRP_LA) $(USRP_INBAND_LA) +test_usrp_inband_overrun_SOURCES = test_usrp_inband_overrun.cc +test_usrp_inband_overrun_LDADD = $(USRP_LA) $(USRP_INBAND_LA) + test_usrp_inband_underrun_SOURCES = test_usrp_inband_underrun.cc test_usrp_inband_underrun_LDADD = $(USRP_LA) $(USRP_INBAND_LA) test_usrp_inband_rx_SOURCES = test_usrp_inband_rx.cc ui_sincos.c test_usrp_inband_rx_LDADD = $(USRP_LA) $(USRP_INBAND_LA) +test_gmac_tx_SOURCES = test_gmac_tx.cc gmac.cc gmac_mbh.cc ui_sincos.c +test_gmac_tx_LDADD = $(USRP_LA) $(USRP_INBAND_LA) + read_packets_SOURCES = read_packets.cc read_packets_LDADD = $(USRP_LA) $(USRP_INBAND_LA) diff --git a/usrp/host/apps-inband/gmac.cc b/usrp/host/apps-inband/gmac.cc new file mode 100644 index 00000000..15397916 --- /dev/null +++ b/usrp/host/apps-inband/gmac.cc @@ -0,0 +1,691 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +static bool verbose = true; + +gmac::gmac(mb_runtime *rt, const std::string &instance_name, pmt_t user_arg) + : mb_mblock(rt, instance_name, user_arg), + d_us_rx_chan(PMT_NIL), d_us_tx_chan(PMT_NIL) +{ + + // When the MAC layer is initialized, we must connect to the USRP and setup + // channels. We begin by defining ports to connect to the 'usrp_server' block + // and then initialize the USRP by opening it through the 'usrp_server.' + + // Initialize the ports + define_ports(); + + // Initialize the connection to the USRP + initialize_usrp(); + +} + +gmac::~gmac() +{ +} + +// The full functionality of GMAC is based on messages passed back and forth +// between the application and a physical layer and/or usrp_server. Each +// message triggers additional events, states, and messages to be sent. +void gmac::handle_message(mb_message_sptr msg) +{ + + // The MAC functionality is dispatched based on the event, which is the + // driving force of the MAC. The event can be anything from incoming samples + // to a message to change the carrier sense threshold. + pmt_t event = msg->signal(); + pmt_t data = msg->data(); + pmt_t port_id = msg->port_id(); + + pmt_t handle = PMT_F; + pmt_t status = PMT_F; + pmt_t dict = PMT_NIL; + std::string error_msg; + + switch(d_state) { + + //---------------------------- INIT ------------------------------------// + // In the INIT state, there should be no messages across the ports. + case INIT: + error_msg = "no messages should be passed during the INIT state:"; + goto unhandled; + + //-------------------------- OPENING USRP -------------------------------// + // In this state we expect a response from usrp_server over the CS channel + // as to whether or not the opening of the USRP was successful. If so, we + // switch states to allocating the channels for use. + case OPENING_USRP: + + if(pmt_eq(event, s_response_open) + && pmt_eq(d_us_cs->port_symbol(), port_id)) { + + status = pmt_nth(1, data); // PMT_T or PMT_F + + if(pmt_eq(status, PMT_T)) { // on success, allocate channels! + allocate_channels(); + return; + } + else { + error_msg = "failed to open usrp:"; + goto bail; + } + + } + + goto unhandled; // all other messages not handled in this state + + //------------------------ ALLOCATING CHANNELS --------------------------// + // When allocating channels, we need to wait for 2 responses from USRP + // server: one for TX and one for RX. Both are initialized to NIL so we + // know to continue to the next state once both are set. + case ALLOCATING_CHANNELS: + + // ************* TX ALLOCATION RESPONSE ***************** // + if(pmt_eq(event, s_response_allocate_channel) + && pmt_eq(d_us_tx->port_symbol(), port_id)) + { + status = pmt_nth(1, data); + + if(pmt_eq(status, PMT_T)) { // extract channel on success + d_us_tx_chan = pmt_nth(2, data); + + if(verbose) + std::cout << "[GMAC] Received TX allocation" + << " on channel " << d_us_tx_chan << std::endl; + + // If the RX has also been allocated already, we can continue + if(!pmt_eqv(d_us_rx_chan, PMT_NIL)) { + //enter_receiving(); + initialize_gmac(); + } + + return; + } + else { // TX allocation failed + error_msg = "failed to allocate TX channel:"; + goto bail; + } + } + + // ************* RX ALLOCATION RESPONSE ****************// + if(pmt_eq(event, s_response_allocate_channel) + && pmt_eq(d_us_rx->port_symbol(), port_id)) + { + status = pmt_nth(1, data); + + if(pmt_eq(status, PMT_T)) { + + d_us_rx_chan = pmt_nth(2, data); + + if(verbose) + std::cout << "[GMAC] Received RX allocation" + << " on channel " << d_us_rx_chan << std::endl; + + // If the TX has also been allocated already, we can continue + if(!pmt_eqv(d_us_tx_chan, PMT_NIL)) { + //enter_receiving(); + initialize_gmac(); + } + + return; + } + else { // RX allocation failed + error_msg = "failed to allocate RX channel:"; + goto bail; + } + } + + goto unhandled; + + //----------------------------- INIT GMAC --------------------------------// + // In the INIT_GMAC state, now that the USRP is initialized we can do things + // like right the carrier sense threshold to the FPGA register. + case INIT_GMAC: + goto unhandled; + + + //----------------------------- IDLE ------------------------------------// + // In the idle state the MAC is not quite 'idle', it is just not doing + // anything specific. It is still being passive with data between the + // application and the lower layer. + case IDLE: + + //-------- TX PORT ----------------------------------------------------// + if(pmt_eq(d_tx->port_symbol(), port_id)) { + + //-------- INCOMING PACKET ------------------------------------------// + if(pmt_eq(event, s_cmd_tx_pkt)) { + handle_cmd_tx_pkt(data); + return; + } + + } + + //--------- USRP TX PORT ----------------------------------------------// + if(pmt_eq(d_us_tx->port_symbol(), port_id)) { + + //-------- INCOMING PACKET RESPONSE ---------------------------------// + if(pmt_eq(event, s_response_xmit_raw_frame)) { + handle_response_xmit_raw_frame(data); + return; + } + + } + + //--------- CS PORT ---------------------------------------------------// + if(pmt_eq(d_cs->port_symbol(), port_id)) { + + //------- ENABLE CARRIER SENSE --------------------------------------// + if(pmt_eq(event, s_cmd_carrier_sense_enable)) { + handle_cmd_carrier_sense_enable(data); + return; + } + + //------- CARRIER SENSE THRESHOLD -----------------------------------// + if(pmt_eq(event, s_cmd_carrier_sense_threshold)) { + handle_cmd_carrier_sense_threshold(data); + return; + } + + //------- CARRIER SENSE DEADLINE ------------------------------------// + if(pmt_eq(event, s_cmd_carrier_sense_deadline)) { + handle_cmd_carrier_sense_deadline(data); + return; + } + + //------- DISABLE CARRIER SENSE -------------------------------------// + if(pmt_eq(event, s_cmd_carrier_sense_disable)) { + handle_cmd_carrier_sense_disable(data); + return; + } + + } + + goto unhandled; + + //------------------------ CLOSING CHANNELS -----------------------------// + case CLOSING_CHANNELS: + + if (pmt_eq(event, s_response_deallocate_channel) + && pmt_eq(d_us_tx->port_symbol(), port_id)) + { + status = pmt_nth(1, data); + + if(pmt_eq(status, PMT_T)) { + d_us_tx_chan = PMT_NIL; + + if(verbose) + std::cout << "[GMAC] Received TX deallocation\n"; + + // If the RX is also deallocated, we can close the USRP + if(pmt_eq(d_us_rx_chan, PMT_NIL)) + close_usrp(); + + return; + + } else { + + error_msg = "failed to deallocate TX channel:"; + goto bail; + + } + } + + if (pmt_eq(event, s_response_deallocate_channel) + && pmt_eq(d_us_rx->port_symbol(), port_id)) + { + status = pmt_nth(1, data); + + // If successful, set the port to NIL + if(pmt_eq(status, PMT_T)) { + d_us_rx_chan = PMT_NIL; + + if(verbose) + std::cout << "[GMAC] Received RX deallocation\n"; + + // If the TX is also deallocated, we can close the USRP + if(pmt_eq(d_us_tx_chan, PMT_NIL)) + close_usrp(); + + return; + + } else { + + error_msg = "failed to deallocate RX channel:"; + goto bail; + + } + } + + goto unhandled; + + //-------------------------- CLOSING USRP -------------------------------// + case CLOSING_USRP: + goto unhandled; + + } + + // An error occured, print it, and shutdown all m-blocks + bail: + std::cerr << error_msg << data + << "status = " << status << std::endl; + shutdown_all(PMT_F); + return; + + // Received an unhandled message for a specific state + unhandled: + if(0 && verbose && !pmt_eq(event, pmt_intern("%shutdown"))) + std::cout << "[GMAC] unhandled msg: " << msg + << "in state "<< d_state << std::endl; +} + +// The MAC layer connects to 'usrp_server' which has a control/status channel, +// a TX, and an RX port. The MAC layer can then relay TX/RX data back and +// forth to the application, or a physical layer once available. +void gmac::define_ports() +{ + // Ports we use to connect to usrp_server + d_us_tx = define_port("us-tx0", "usrp-tx", false, mb_port::INTERNAL); + d_us_rx = define_port("us-rx0", "usrp-rx", false, mb_port::INTERNAL); + d_us_cs = define_port("us-cs", "usrp-server-cs", false, mb_port::INTERNAL); + + // Ports applications used to connect to us + d_tx = define_port("tx0", "gmac-tx", true, mb_port::EXTERNAL); + d_rx = define_port("rx0", "gmac-rx", true, mb_port::EXTERNAL); + d_cs = define_port("cs", "gmac-cs", true, mb_port::EXTERNAL); +} + +// To initialize the USRP we must pass several parameters to 'usrp_server' such +// as the RBF to use, and the interpolation/decimation rate. The MAC layer will +// then pass these parameters to the block with a message to establish the +// connection to the USRP. +void gmac::initialize_usrp() +{ + + if(verbose) + std::cout << "[GMAC] Initializing USRP\n"; + + // The initialization parameters are passed to usrp_server via a PMT + // dictionary. + pmt_t usrp_dict = pmt_make_dict(); + + // Specify the RBF to use + pmt_dict_set(usrp_dict, + pmt_intern("rbf"), + pmt_intern("test2.rbf")); + + pmt_dict_set(usrp_dict, + pmt_intern("interp-tx"), + pmt_from_long(128)); + + pmt_dict_set(usrp_dict, + pmt_intern("decim-rx"), + pmt_from_long(16)); + + // Center frequency + pmt_dict_set(usrp_dict, + pmt_intern("rf-freq"), + pmt_from_long((long)10e6)); + + // Default is to use USRP considered '0' (incase of multiple) + d_which_usrp = pmt_from_long(0); + + define_component("USRP-SERVER", "usrp_server", usrp_dict); + + connect("self", "us-tx0", "USRP-SERVER", "tx0"); + connect("self", "us-rx0", "USRP-SERVER", "rx0"); + connect("self", "us-cs", "USRP-SERVER", "cs"); + + // Finally, enter the OPENING_USRP state by sending a request to open the + // USRP. + open_usrp(); + +} + +// In the initialization state of the MAC layer we set default values for +// several functionalities. +void gmac::initialize_gmac() +{ + + // The initial state is the INIT state. + d_state = INIT_GMAC; + + // Set carrier sense to enabled by default with the specified threshold and + // the deadline to 0 -- which is wait forever. + set_carrier_sense(true, 25, 0, PMT_NIL); + + // Can now notify the application that we are initialized + d_cs->send(s_response_gmac_initialized, + pmt_list2(PMT_NIL, PMT_T)); + + // The MAC enters an IDLE state where it waits for messages and dispatches + // based on them + enter_idle(); +} + +// Method for setting the carrier sense and an associated threshold which is +// written to a register on the FPGA, which it will read if the CS flag is set +// and perform carrier sense based on. +// +// We currently do not wait for the successful response for the write to +// register command, we assume it will succeed else the MAC must +void gmac::set_carrier_sense(bool toggle, long threshold, long deadline, pmt_t invocation) +{ + d_carrier_sense = toggle; + + // Only waste the bandwidth and processing of a C/S packet if needed + if(threshold != d_cs_thresh) { + d_us_tx->send(s_cmd_to_control_channel, // C/S packet + pmt_list2(invocation, // invoc handle + pmt_list1( + pmt_list2(s_op_write_reg, + pmt_list2( + pmt_from_long(REG_CS_THRESH), + pmt_from_long(threshold)))))); + d_cs_thresh = threshold; + + if(verbose) + std::cout << "[GMAC] Changing CS threshold: " << d_cs_thresh << std::endl; + } + + if(deadline != d_cs_deadline) { + d_us_tx->send(s_cmd_to_control_channel, // C/S packet + pmt_list2(invocation, // invoc handle + pmt_list1( + pmt_list2(s_op_write_reg, + pmt_list2( + pmt_from_long(REG_CS_DEADLINE), + pmt_from_long(deadline)))))); + d_cs_deadline = deadline; + + if(verbose) + std::cout << "[GMAC] Changing CS deadline: " << d_cs_deadline << std::endl; + } + + if(verbose) + std::cout << "[GMAC] Setting carrier sense to " << toggle << std::endl; +} + +// The following sends a command to open the USRP, which will upload the +// specified RBF when creating the instance of the USRP server and set all other +// relevant parameters. +void gmac::open_usrp() +{ + d_state = OPENING_USRP; + + d_us_cs->send(s_cmd_open, pmt_list2(PMT_NIL, d_which_usrp)); + + if(verbose) + std::cout << "[GMAC] Opening USRP " + << d_which_usrp << std::endl; +} + +// Before sending the close to the USRP we wait a couple seconds to let any data +// through the USB exit, else a bug in the driver will kick an error and cause +// an abnormal termination. +void gmac::close_usrp() +{ + d_state = CLOSING_USRP; + + sleep(2); + + d_us_cs->send(s_cmd_close, pmt_list1(PMT_NIL)); +} + +// RX and TX channels must be allocated so that the USRP server can +// properly share bandwidth across multiple USRPs. No commands will be +// successful to the USRP through the USRP server on the TX or RX channels until +// a bandwidth allocation has been received. +void gmac::allocate_channels() +{ + d_state = ALLOCATING_CHANNELS; + + if(verbose) + std::cout << "[GMAC] Sending channel allocation requests\n"; + + long capacity = (long) 16e6; + d_us_tx->send(s_cmd_allocate_channel, pmt_list2(PMT_T, pmt_from_long(capacity))); + d_us_rx->send(s_cmd_allocate_channel, pmt_list2(PMT_T, pmt_from_long(capacity))); + +} + +// Before closing the USRP connection, we deallocate our channels so that the +// capacity can be reused. +void gmac::close_channels() +{ + d_state = CLOSING_CHANNELS; + + d_us_tx->send(s_cmd_deallocate_channel, pmt_list2(PMT_NIL, d_us_tx_chan)); + d_us_rx->send(s_cmd_deallocate_channel, pmt_list2(PMT_NIL, d_us_rx_chan)); + + if(verbose) + std::cout << "[GMAC] Closing channels...\n"; +} + +// Used to enter the receiving state +void gmac::enter_receiving() +{ + d_us_rx->send(s_cmd_start_recv_raw_samples, + pmt_list2(PMT_F, + d_us_rx_chan)); + + if(verbose) + std::cout << "[GMAC] Started RX sample stream\n"; +} + +// A simple idle state, nothing more to it. +void gmac::enter_idle() +{ + d_state = IDLE; +} + +// Handles the transmission of a pkt from the application. The invocation +// handle is passed on but a response is not given back to the application until +// the response is passed from usrp_server. This ensures that the MAC passes +// back the success or failure. Furthermore, the MAC could decide to retransmit +// on a failure based on the result of the packet transmission. +// +// This should eventually be connected to a physically layer rather than +// directly to usrp_server. (d_us_tx should be replaced with a different +// connection) +void gmac::handle_cmd_tx_pkt(pmt_t data) +{ + pmt_t invocation_handle = pmt_nth(0, data); + pmt_t dst = pmt_nth(1, data); + pmt_t samples = pmt_nth(2, data); + pmt_t pkt_properties = pmt_nth(3, data); + + pmt_t us_tx_properties = pmt_make_dict(); + + // Set the packet to be carrier sensed? + if(carrier_sense_pkt(pkt_properties)) + pmt_dict_set(us_tx_properties, + pmt_intern("carrier-sense"), + PMT_T); + + pmt_t timestamp = pmt_from_long(0xffffffff); // NOW + + // Construct the proper message for USRP server + d_us_tx->send(s_cmd_xmit_raw_frame, + pmt_list5(invocation_handle, + d_us_tx_chan, + samples, + timestamp, + us_tx_properties)); + + if(verbose && 0) + std::cout << "[GMAC] Transmitted packet\n"; +} + +// Handles a response from the USRP server about the transmission of a frame, +// whether it was successful or failed. This should eventually be replaced with +// a response from the PHY layer. This is where a retransmit could be +// implemented. +void gmac::handle_response_xmit_raw_frame(pmt_t data) +{ + pmt_t invocation_handle = pmt_nth(0, data); + pmt_t status = pmt_nth(1, data); + + d_tx->send(s_response_tx_pkt, + pmt_list2(invocation_handle, + status)); +} + +// This method determines whether carrier sense should be enabled based on two +// properties. The first is the MAC setting, which the user can set to carrier +// sense packets by default or not. The second is a per packet setting, which +// can be used to override the MAC setting for the given packet only. +bool gmac::carrier_sense_pkt(pmt_t pkt_properties) +{ + // First we extract the per packet properties to check the per packet setting + // if it exists + if(pmt_is_dict(pkt_properties)) { + + if(pmt_t pkt_cs = pmt_dict_ref(pkt_properties, + pmt_intern("carrier-sense"), + PMT_NIL)) { + // If the per packet property says true, enable carrier sense regardless + // of the MAC setting + if(pmt_eqv(pkt_cs, PMT_T)) + return true; + // If the per packet setting says false, disable carrier sense regardless + // of the MAC setting + else if(pmt_eqv(pkt_cs, PMT_F)) + return false; + } + } + + // If we've hit this point, the packet properties did not state whether + // carrier sense should be used or not, so we use the MAC setting + if(d_carrier_sense) + return true; + else + return false; + +} + +// This method is envoked by an incoming cmd-enable-carrier-sense signal on the +// C/S port. It can be used to re-adjust the threshold or simply enabled +// carrier sense. When a threshold is not provided, the MAC will use an +// averaging algorithm to determine the threshold (in the future). +void gmac::handle_cmd_carrier_sense_enable(pmt_t data) +{ + pmt_t invocation_handle = pmt_nth(0, data); + pmt_t threshold = pmt_nth(1, data); + pmt_t deadline = pmt_nth(2, data); + long l_threshold, l_deadline; + + // FIXME: for now, if threshold is NIL, we do not change the threshold. + // This should be replaced with an averaging algorithm + if(pmt_eqv(threshold, PMT_NIL)) + l_threshold = d_cs_thresh; + else + l_threshold = pmt_to_long(threshold); + + // If the deadline is NIL, we do not change the value + if(pmt_eqv(threshold, PMT_NIL)) + l_deadline = d_cs_deadline; + else + l_deadline = pmt_to_long(deadline); + + set_carrier_sense(true, l_threshold, l_deadline, invocation_handle); +} + +// This method is called when an incoming disable carrier sense command is sent +// over the control status channel. It so far does not ellicit a response, this +// needs to be added correctly. It needs to wait for the response for the C/S +// packet from usrp_server. +void gmac::handle_cmd_carrier_sense_disable(pmt_t data) +{ + pmt_t invocation_handle = pmt_nth(0, data); + + // We don't change the threshold, we leave it as is because the application + // did not request that it changes, only to disable carrier sense. + set_carrier_sense(false, d_cs_thresh, d_cs_deadline, invocation_handle); +} + +// When the app requests that the threshold changes, the state of the carrier +// sense should not change. If it was enabled, it should remain enabled. +// Likewise if it was disabled. The deadline value should also remain +// unchanged. +void gmac::handle_cmd_carrier_sense_threshold(pmt_t data) +{ + pmt_t invocation_handle = pmt_nth(0, data); + pmt_t threshold = pmt_nth(1, data); + long l_threshold; + + // FIXME: for now, if threshold is NIL, we do not change the threshold. + // This should be replaced with an averaging algorithm + if(pmt_eqv(threshold, PMT_NIL)) + l_threshold = d_cs_thresh; + else + l_threshold = pmt_to_long(threshold); + + set_carrier_sense(d_carrier_sense, l_threshold, d_cs_deadline, invocation_handle); +} + +// Ability to change the deadline using a C/S packet. The state of all other +// carrier sense parameters should not change. +void gmac::handle_cmd_carrier_sense_deadline(pmt_t data) +{ + pmt_t invocation_handle = pmt_nth(0, data); + pmt_t deadline = pmt_nth(1, data); + long l_deadline; + + // If the deadline passed is NIL, do *not* change the value. + if(pmt_eqv(deadline, PMT_NIL)) + l_deadline = d_cs_deadline; + else + l_deadline = pmt_to_long(deadline); + + set_carrier_sense(d_carrier_sense, d_cs_thresh, l_deadline, invocation_handle); +} + +REGISTER_MBLOCK_CLASS(gmac); diff --git a/usrp/host/apps-inband/gmac.h b/usrp/host/apps-inband/gmac.h new file mode 100644 index 00000000..a6d0bcb1 --- /dev/null +++ b/usrp/host/apps-inband/gmac.h @@ -0,0 +1,91 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef INCLUDED_GMAC_H +#define INCLUDED_GMAC_H + +#include + +class gmac; + +class gmac : public mb_mblock +{ + + // The state is used to determine how to handle incoming messages and of + // course, the state of the MAC protocol. + enum state_t { + INIT, + OPENING_USRP, + ALLOCATING_CHANNELS, + INIT_GMAC, + IDLE, + CLOSING_CHANNELS, + CLOSING_USRP, + }; + state_t d_state; + + // Ports used for applications to connect to this block + mb_port_sptr d_tx, d_rx, d_cs; + + // Ports to connect to usrp_server (us) + mb_port_sptr d_us_tx, d_us_rx, d_us_cs; + + // The channel numbers assigned for use + pmt_t d_us_rx_chan, d_us_tx_chan; + + pmt_t d_which_usrp; + + bool d_carrier_sense; + long d_cs_thresh; + long d_cs_deadline; + + enum FPGA_REGISTERS { + REG_CS_THRESH = 1, + REG_CS_DEADLINE = 2 + }; + + public: + gmac(mb_runtime *rt, const std::string &instance_name, pmt_t user_arg); + ~gmac(); + void handle_message(mb_message_sptr msg); + + private: + void define_ports(); + void initialize_usrp(); + void initialize_gmac(); + void set_carrier_sense(bool toggle, long threshold, long deadline, pmt_t invocation); + void allocate_channels(); + void enter_receiving(); + void enter_idle(); + void close_channels(); + void open_usrp(); + void close_usrp(); + void handle_cmd_tx_pkt(pmt_t data); + void handle_response_xmit_raw_frame(pmt_t data); + bool carrier_sense_pkt(pmt_t pkt_properties); + void handle_cmd_carrier_sense_enable(pmt_t data); + void handle_cmd_carrier_sense_threshold(pmt_t data); + void handle_cmd_carrier_sense_disable(pmt_t data); + void handle_cmd_carrier_sense_deadline(pmt_t data); + +}; + +#endif // INCLUDED_GMAC_H diff --git a/usrp/host/apps-inband/gmac.mbh b/usrp/host/apps-inband/gmac.mbh new file mode 100644 index 00000000..4fa9a062 --- /dev/null +++ b/usrp/host/apps-inband/gmac.mbh @@ -0,0 +1,146 @@ +;; -*- scheme -*- ; not really, but tells emacs how to format this +;; +;; Copyright 2007 Free Software Foundation, Inc. +;; +;; This file is part of GNU Radio +;; +;; GNU Radio is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU Radio is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License along +;; with this program; if not, write to the Free Software Foundation, Inc., +;; 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +;; + +;; ---------------------------------------------------------------- +;; This is an mblock header file +;; +;; The format is very much a work-in-progress. +;; It'll be compiled to C++. +;; ---------------------------------------------------------------- + +;; In the outgoing messages described below, invocation-handle is an +;; identifier provided by the client to tag the method invocation. +;; The identifier will be returned with the response, to provide the +;; client with a mechanism to match asynchronous responses with the +;; commands that generate them. The value of the invocation-handle is +;; opaque the the server, and is not required by the server to be +;; unique. +;; +;; In the incoming messages described below, invocation-handle is the +;; identifier provided by the client in the prompting invocation. The +;; identifier is returned with the response, so that the client has a +;; mechanism to match asynchronous responses with the commands that +;; generated them. +;; +;; status is either #t, indicating success, or a symbol indicating an error. +;; All symbol's names shall begin with %error- + + +;; ---------------------------------------------------------------- +;; gmac-tx +;; +;; The protocol class is defined from the client's point-of-view. +;; (The client port is unconjugated, the server port is conjugated.) + +(define-protocol-class gmac-tx + + (:outgoing + + ;; Transmitting packets can carry an invocation handle so the application + ;; can get TX results on specific packets, such as whether a packet tagged + ;; as #1 was successfully transmitted or not. This would allow the + ;; application to implement something sliding window like. + ;; + ;; 'dst' is the destination MAC address (given a MAC addressing scheme) + ;; + ;; 'data' will be treated transparently and passed on as samples. + ;; + ;; 'properties' can be used in the future to set per-packet options such as + ;; carrier sense overriding functionality. + (cmd-tx-pkt invocation-handle dst data properties) + + ) + + (:incoming + + ;; The response will carry the same invocation-handle passed with cmd-tx-pkt + (response-tx-pkt invocation-handle status) + + ) + ) + +;; ---------------------------------------------------------------- +;; gmac-rx +;; +;; The protocol class is defined from the client's point-of-view. +;; (The client port is unconjugated, the server port is conjugated.) + +(define-protocol-class gmac-rx + + (:outgoing + + ;; There are currently no outgoing commands, I believe that the RX + ;; should always be enabled, there is no point in having an enable/disable + ;; that I can see. + + ) + + (:incoming + + ;; Contains packets decoded by the MAC destined for this machine, sent by + ;; the specified address. + (response-rx-pkt invocation-handle src data) + + ) + ) + + +;; ---------------------------------------------------------------- +;; gmac-cs +;; +;; The protocol class is defined from the client's point-of-view. +;; (The client port is unconjugated, the server port is conjugated.) +;; +;; This defines a control/status interface to the MAC layer, for control over +;; functionality such as carrier sense and future functionality such as channel +;; hopping. + + +(define-protocol-class gmac-cs + + (:outgoing + + ;; Threshold represents the carrier sense threshold based on the digital + ;; reading out of the DAC. If the threshold is set to PMT_NIL then the + ;; MAC will use averaging to determine an appropriate threshold. + (cmd-carrier-sense-enable invocation-handle threshold deadline) + (cmd-carrier-sense-threshold invocation-handle threshold) + (cmd-carrier-sense-disable invocation-handle) + + ;; Setting the number of fast transmission retries on a failure before + ;; reporting a loss back to the application. + (cmd-set-tx-retries invocation-handle retries) + + ) + + (:incoming + + (response-gmac-initialized invocation-handle status) + + (response-carrier-sense-enable invocation-handle status) + (response-carrier-sense-threshold invocation-handle status) + (response-carrier-sense-deadline invocation-handle status) + (response-carrier-sense-disable invocation-handle status) + + (response-set-tx-retries invocation-handle status) + + ) + ) diff --git a/usrp/host/apps-inband/gmac_symbols.h b/usrp/host/apps-inband/gmac_symbols.h new file mode 100644 index 00000000..0d7804be --- /dev/null +++ b/usrp/host/apps-inband/gmac_symbols.h @@ -0,0 +1,47 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef INCLUDED_GMAC_SYMBOLS_H +#define INCLUDED_GMAC_SYMBOLS_H + +#include + +// TX +static pmt_t s_cmd_tx_pkt = pmt_intern("cmd-tx-pkt"); +static pmt_t s_response_tx_pkt = pmt_intern("response-tx-pkt"); + +// RX +static pmt_t s_response_rx_pkt = pmt_intern("response-rx-pkt"); + +// CS +static pmt_t s_cmd_carrier_sense_enable = pmt_intern("cmd-carrier-sense-enable"); +static pmt_t s_cmd_carrier_sense_threshold = pmt_intern("cmd-carrier-sense-threshold"); +static pmt_t s_cmd_carrier_sense_deadline = pmt_intern("cmd-carrier-sense-deadline"); +static pmt_t s_cmd_carrier_sense_disable = pmt_intern("cmd-carrier-sense-disable"); +static pmt_t s_cmd_set_tx_retries = pmt_intern("cmd-set-tx-retries"); +static pmt_t s_response_gmac_initialized = pmt_intern("response-gmac-initialized"); +static pmt_t s_response_carrier_sense_enable = pmt_intern("response-carrier-sense-enable"); +static pmt_t s_response_carrier_sense_treshold = pmt_intern("response-carrier-sense-threshold"); +static pmt_t s_response_carrier_sense_deadline = pmt_intern("response-carrier-sense-deadline"); +static pmt_t s_response_carrier_sense_disable = pmt_intern("response-carrier-sense-disable"); +static pmt_t s_response_set_tx_retries = pmt_intern("response-set-tx-retries"); + +#endif // INCLUDED_GMAC_SYMBOLS_H diff --git a/usrp/host/apps-inband/test_gmac_tx.cc b/usrp/host/apps-inband/test_gmac_tx.cc new file mode 100644 index 00000000..dd16c3fa --- /dev/null +++ b/usrp/host/apps-inband/test_gmac_tx.cc @@ -0,0 +1,332 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include // QA only +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static bool verbose = true; + +class test_gmac_tx : public mb_mblock +{ + mb_port_sptr d_tx; + mb_port_sptr d_cs; + pmt_t d_tx_chan; // returned tx channel handle + + enum state_t { + INIT, + TRANSMITTING, + }; + + state_t d_state; + long d_nsamples_to_send; + long d_nsamples_xmitted; + long d_nframes_xmitted; + long d_samples_per_frame; + bool d_done_sending; + + // for generating sine wave output + ui_nco d_nco; + double d_amplitude; + + public: + test_gmac_tx(mb_runtime *runtime, const std::string &instance_name, pmt_t user_arg); + ~test_gmac_tx(); + void handle_message(mb_message_sptr msg); + + protected: + void open_usrp(); + void close_usrp(); + void allocate_channel(); + void send_packets(); + void enter_transmitting(); + void build_and_send_next_frame(); + void handle_xmit_response(pmt_t invocation_handle); + void enter_closing_channel(); +}; + +test_gmac_tx::test_gmac_tx(mb_runtime *runtime, const std::string &instance_name, pmt_t user_arg) + : mb_mblock(runtime, instance_name, user_arg), + d_state(INIT), d_nsamples_to_send((long) 40e6), + d_nsamples_xmitted(0), + d_nframes_xmitted(0), + d_samples_per_frame((long)(126 * 4)), // full packet + d_done_sending(false), + d_amplitude(16384) +{ + + define_component("GMAC", "gmac", PMT_NIL); + d_tx = define_port("tx0", "gmac-tx", false, mb_port::INTERNAL); + d_cs = define_port("cs", "gmac-cs", false, mb_port::INTERNAL); + + connect("self", "tx0", "GMAC", "tx0"); + connect("self", "cs", "GMAC", "cs"); + + // initialize NCO + double freq = 100e3; + int interp = 32; // 32 -> 4MS/s + double sample_rate = 128e6 / interp; + d_nco.set_freq(2*M_PI * freq/sample_rate); + +} + +test_gmac_tx::~test_gmac_tx() +{ +} + +void +test_gmac_tx::handle_message(mb_message_sptr msg) +{ + pmt_t event = msg->signal(); + pmt_t data = msg->data(); + pmt_t port_id = msg->port_id(); + + pmt_t handle = PMT_F; + pmt_t status = PMT_F; + pmt_t dict = PMT_NIL; + std::string error_msg; + + // Dispatch based on state + switch(d_state) { + + //------------------------------ INIT ---------------------------------// + // When GMAC is done initializing, it will send a response + case INIT: + + if(pmt_eq(event, s_response_gmac_initialized)) { + handle = pmt_nth(0, data); + status = pmt_nth(1, data); + + if(pmt_eq(status, PMT_T)) { + enter_transmitting(); + return; + } + else { + error_msg = "error initializing gmac:"; + goto bail; + } + } + goto unhandled; + + //-------------------------- TRANSMITTING ----------------------------// + // In the transmit state we count the number of underruns received and + // ballpark the number with an expected count (something >1 for starters) + case TRANSMITTING: + + // Check that the transmits are OK + if (pmt_eq(event, s_response_tx_pkt)){ + handle = pmt_nth(0, data); + status = pmt_nth(1, data); + + if (pmt_eq(status, PMT_T)){ + handle_xmit_response(handle); + return; + } + else { + error_msg = "bad response-tx-pkt:"; + goto bail; + } + } + + goto unhandled; + + } + + // An error occured, print it, and shutdown all m-blocks + bail: + std::cerr << error_msg << data + << "status = " << status << std::endl; + shutdown_all(PMT_F); + return; + + // Received an unhandled message for a specific state + unhandled: + if(verbose && !pmt_eq(event, pmt_intern("%shutdown"))) + std::cout << "[TEST_GMAC_TX] unhandled msg: " << msg + << "in state "<< d_state << std::endl; +} + +void +test_gmac_tx::enter_transmitting() +{ + d_state = TRANSMITTING; + d_nsamples_xmitted = 0; + + d_cs->send(s_cmd_carrier_sense_deadline, + pmt_list2(PMT_NIL, + pmt_from_long(50000000))); + + build_and_send_next_frame(); // fire off 4 to start pipeline + build_and_send_next_frame(); + build_and_send_next_frame(); + build_and_send_next_frame(); +} + +void +test_gmac_tx::build_and_send_next_frame() +{ + // allocate the uniform vector for the samples + // FIXME perhaps hold on to this between calls + +#if 0 + long nsamples_this_frame = + std::min(d_nsamples_to_send - d_nsamples_xmitted, + d_samples_per_frame); +#else + long nsamples_this_frame = d_samples_per_frame; +#endif + + if (nsamples_this_frame == 0){ + d_done_sending = true; + return; + } + + + size_t nshorts = 2 * nsamples_this_frame; // 16-bit I & Q + pmt_t uvec = pmt_make_s16vector(nshorts, 0); + size_t ignore; + int16_t *samples = pmt_s16vector_writeable_elements(uvec, ignore); + + // fill in the complex sinusoid + for (int i = 0; i < nsamples_this_frame; i++){ + + if (1){ + gr_complex s; + d_nco.sincos(&s, 1, d_amplitude); + // write 16-bit i & q + samples[2*i] = (int16_t) s.real(); + samples[2*i+1] = (int16_t) s.imag(); + } + else { + gr_complex s(d_amplitude, d_amplitude); + + // write 16-bit i & q + samples[2*i] = (int16_t) s.real(); + samples[2*i+1] = (int16_t) s.imag(); + } + } + + // Per packet properties + pmt_t tx_properties = pmt_make_dict(); + + if(d_nframes_xmitted > 25000) { + pmt_dict_set(tx_properties, + pmt_intern("carrier-sense"), + PMT_F); + } + + if(d_nframes_xmitted > 35000) { + pmt_dict_set(tx_properties, + pmt_intern("carrier-sense"), + PMT_NIL); + } + + if(d_nframes_xmitted == 45000) { + d_cs->send(s_cmd_carrier_sense_threshold, + pmt_list2(PMT_NIL, + pmt_from_long(100))); + } + + if(d_nframes_xmitted == 60000) { + d_cs->send(s_cmd_carrier_sense_threshold, + pmt_list2(PMT_NIL, + pmt_from_long(25))); + } + + if(d_nframes_xmitted == 75000) { + d_cs->send(s_cmd_carrier_sense_disable, + pmt_list1(PMT_NIL)); + } + + if(d_nframes_xmitted > 90000 && d_nframes_xmitted < 110000) { + pmt_dict_set(tx_properties, + pmt_intern("carrier-sense"), + PMT_T); + } + + if(d_nframes_xmitted > 110000) { + + if(d_nframes_xmitted % 100 == 0) + pmt_dict_set(tx_properties, + pmt_intern("carrier-sense"), + PMT_T); +} + + pmt_t timestamp = pmt_from_long(0xffffffff); // NOW + d_tx->send(s_cmd_tx_pkt, + pmt_list4(PMT_NIL, // invocation-handle + PMT_NIL, // destination + uvec, // the samples + tx_properties)); // per pkt properties + + d_nsamples_xmitted += nsamples_this_frame; + d_nframes_xmitted++; + + if(verbose && 0) + std::cout << "[TEST_GMAC_TX] Transmitted frame\n"; +} + + +void +test_gmac_tx::handle_xmit_response(pmt_t handle) +{ + if (d_done_sending && + pmt_to_long(handle) == (d_nframes_xmitted - 1)){ + // We're done sending and have received all responses + } + + build_and_send_next_frame(); +} + +REGISTER_MBLOCK_CLASS(test_gmac_tx); + + +// ---------------------------------------------------------------- + +int +main (int argc, char **argv) +{ + // handle any command line args here + + mb_runtime_sptr rt = mb_make_runtime(); + pmt_t result = PMT_NIL; + + rt->run("test_gmac_tx", "test_gmac_tx", PMT_F, &result); +} diff --git a/usrp/host/apps-inband/test_usrp_inband_cs.cc b/usrp/host/apps-inband/test_usrp_inband_cs.cc index 1d70341f..560b81ae 100644 --- a/usrp/host/apps-inband/test_usrp_inband_cs.cc +++ b/usrp/host/apps-inband/test_usrp_inband_cs.cc @@ -34,12 +34,12 @@ #include #include #include -#include #include #include #include #include +#include #include #include #include @@ -138,7 +138,7 @@ test_usrp_cs::test_usrp_cs(mb_runtime *runtime, const std::string &instance_name pmt_from_long(128)); pmt_dict_set(usrp_dict, - pmt_intern("interp-rx"), + pmt_intern("decim-rx"), pmt_from_long(16)); // Specify the RBF to use diff --git a/usrp/host/apps-inband/test_usrp_inband_overrun.cc b/usrp/host/apps-inband/test_usrp_inband_overrun.cc new file mode 100644 index 00000000..343720c2 --- /dev/null +++ b/usrp/host/apps-inband/test_usrp_inband_overrun.cc @@ -0,0 +1,376 @@ +/* -*- c++ -*- */ +/* + * Copyright 2007 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include // QA only +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// Include the symbols needed for communication with USRP server +#include +#include +#include +#include + +static bool verbose = true; + +class test_usrp_rx : public mb_mblock +{ + mb_port_sptr d_rx; + mb_port_sptr d_cs; + pmt_t d_rx_chan; // returned tx channel handle + + enum state_t { + INIT, + OPENING_USRP, + ALLOCATING_CHANNEL, + RECEIVING, + CLOSING_CHANNEL, + CLOSING_USRP, + }; + + state_t d_state; + + std::ofstream d_ofile; + + long d_n_overruns; + + long d_samples_recvd; + long d_samples_to_recv; + + public: + test_usrp_rx(mb_runtime *runtime, const std::string &instance_name, pmt_t user_arg); + ~test_usrp_rx(); + void initial_transition(); + void handle_message(mb_message_sptr msg); + + protected: + void open_usrp(); + void close_usrp(); + void allocate_channel(); + void send_packets(); + void enter_receiving(); + void build_and_send_next_frame(); + void handle_response_recv_raw_samples(pmt_t invocation_handle); + void enter_closing_channel(); +}; + +test_usrp_rx::test_usrp_rx(mb_runtime *runtime, const std::string &instance_name, pmt_t user_arg) + : mb_mblock(runtime, instance_name, user_arg), + d_n_overruns(0), + d_samples_recvd(0), + d_samples_to_recv(10e6) +{ + + d_rx = define_port("rx0", "usrp-rx", false, mb_port::INTERNAL); + d_cs = define_port("cs", "usrp-server-cs", false, mb_port::INTERNAL); + + // Pass a dictionary to usrp_server which specifies which interface to use, the stub or USRP + pmt_t usrp_dict = pmt_make_dict(); + + // Specify the RBF to use + pmt_dict_set(usrp_dict, + pmt_intern("rbf"), + pmt_intern("nanocell9.rbf")); + + pmt_dict_set(usrp_dict, + pmt_intern("decim-rx"), + pmt_from_long(128)); + + define_component("server", "usrp_server", usrp_dict); + + connect("self", "rx0", "server", "rx0"); + connect("self", "cs", "server", "cs"); + +} + +test_usrp_rx::~test_usrp_rx() +{ +} + +void +test_usrp_rx::initial_transition() +{ + open_usrp(); +} + +void +test_usrp_rx::handle_message(mb_message_sptr msg) +{ + pmt_t event = msg->signal(); + pmt_t data = msg->data(); + + pmt_t handle = PMT_F; + pmt_t status = PMT_F; + std::string error_msg; + + switch(d_state){ + + //----------------------------- OPENING_USRP ----------------------------// + // We only expect a response from opening the USRP which should be succesful + // or failed. + case OPENING_USRP: + if (pmt_eq(event, s_response_open)){ + status = pmt_nth(1, data); + if (pmt_eq(status, PMT_T)){ + allocate_channel(); + return; + } + else { + error_msg = "failed to open usrp:"; + goto bail; + } + } + goto unhandled; + + //----------------------- ALLOCATING CHANNELS --------------------// + // Allocate an RX channel to perform the overrun test. + case ALLOCATING_CHANNEL: + if (pmt_eq(event, s_response_allocate_channel)){ + status = pmt_nth(1, data); + d_rx_chan = pmt_nth(2, data); + + if (pmt_eq(status, PMT_T)){ + enter_receiving(); + return; + } + else { + error_msg = "failed to allocate channel:"; + goto bail; + } + } + goto unhandled; + + //--------------------------- RECEIVING ------------------------------// + // In the receiving state, we receive samples until the specified amount + // while counting the number of overruns. + case RECEIVING: + if (pmt_eq(event, s_response_recv_raw_samples)){ + status = pmt_nth(1, data); + + if (pmt_eq(status, PMT_T)){ + handle_response_recv_raw_samples(data); + return; + } + else { + error_msg = "bad response-xmit-raw-frame:"; + goto bail; + } + } + goto unhandled; + + //------------------------- CLOSING CHANNEL ----------------------------// + // Check deallocation response for the RX channel + case CLOSING_CHANNEL: + if (pmt_eq(event, s_response_deallocate_channel)){ + status = pmt_nth(1, data); + + if (pmt_eq(status, PMT_T)){ + close_usrp(); + return; + } + else { + error_msg = "failed to deallocate channel:"; + goto bail; + } + } + + // Alternately, we ignore all response recv samples while waiting for the + // channel to actually close + if (pmt_eq(event, s_response_recv_raw_samples)) + return; + + goto unhandled; + + //--------------------------- CLOSING USRP ------------------------------// + // Once we have received a successful USRP close response, we shutdown all + // mblocks and exit. + case CLOSING_USRP: + if (pmt_eq(event, s_response_close)){ + status = pmt_nth(1, data); + + if (pmt_eq(status, PMT_T)){ + std::cout << "\nOverruns: " << d_n_overruns << std::endl; + fflush(stdout); + shutdown_all(PMT_T); + return; + } + else { + error_msg = "failed to close USRP:"; + goto bail; + } + } + goto unhandled; + + default: + goto unhandled; + } + return; + + // An error occured, print it, and shutdown all m-blocks + bail: + std::cerr << error_msg << data + << "status = " << status << std::endl; + shutdown_all(PMT_F); + return; + + // Received an unhandled message for a specific state + unhandled: + if(verbose && !pmt_eq(event, pmt_intern("%shutdown"))) + std::cout << "test_usrp_inband_tx: unhandled msg: " << msg + << "in state "<< d_state << std::endl; +} + + +void +test_usrp_rx::open_usrp() +{ + pmt_t which_usrp = pmt_from_long(0); + + d_cs->send(s_cmd_open, pmt_list2(PMT_NIL, which_usrp)); + d_state = OPENING_USRP; + + if(verbose) + std::cout << "[TEST_USRP_INBAND_OVERRUN] Opening the USRP\n"; +} + +void +test_usrp_rx::close_usrp() +{ + d_cs->send(s_cmd_close, pmt_list1(PMT_NIL)); + d_state = CLOSING_USRP; + + if(verbose) + std::cout << "[TEST_USRP_INBAND_OVERRUN] Closing the USRP\n"; +} + +void +test_usrp_rx::allocate_channel() +{ + long capacity = (long) 16e6; + d_rx->send(s_cmd_allocate_channel, pmt_list2(PMT_T, pmt_from_long(capacity))); + d_state = ALLOCATING_CHANNEL; + + if(verbose) + std::cout << "[TEST_USRP_INBAND_OVERRUN] Requesting RX channel allocation\n"; +} + +void +test_usrp_rx::enter_receiving() +{ + d_state = RECEIVING; + + d_rx->send(s_cmd_start_recv_raw_samples, + pmt_list2(PMT_F, + d_rx_chan)); + + if(verbose) + std::cout << "[TEST_USRP_INBAND_OVERRUN] Receiving...\n"; +} + +void +test_usrp_rx::handle_response_recv_raw_samples(pmt_t data) +{ + pmt_t invocation_handle = pmt_nth(0, data); + pmt_t status = pmt_nth(1, data); + pmt_t v_samples = pmt_nth(2, data); + pmt_t timestamp = pmt_nth(3, data); + pmt_t properties = pmt_nth(4, data); + + d_samples_recvd += pmt_length(v_samples) / 4; + + // Check for overrun + if(!pmt_is_dict(properties)) { + std::cout << "[TEST_USRP_INBAND_OVERRUN] Recv samples dictionary is improper\n"; + return; + } + + if(pmt_t overrun = pmt_dict_ref(properties, + pmt_intern("overrun"), + PMT_NIL)) { + if(pmt_eqv(overrun, PMT_T)) { + d_n_overruns++; + + if(verbose && 0) + std::cout << "[TEST_USRP_INBAND_OVERRUN] Underrun\n"; + } + else { + if(verbose && 0) + std::cout << "[TEST_USRP_INBAND_OVERRUN] No overrun\n" << overrun <= d_samples_to_recv) { + d_rx->send(s_cmd_stop_recv_raw_samples, pmt_list2(PMT_NIL, d_rx_chan)); + enter_closing_channel(); + return; + } + +} + +void +test_usrp_rx::enter_closing_channel() +{ + d_state = CLOSING_CHANNEL; + + sleep(2); + + d_rx->send(s_cmd_deallocate_channel, pmt_list2(PMT_NIL, d_rx_chan)); + + if(verbose) + std::cout << "[TEST_USRP_INBAND_OVERRUN] Deallocating RX channel\n"; +} + +REGISTER_MBLOCK_CLASS(test_usrp_rx); + + +// ---------------------------------------------------------------- + +int +main (int argc, char **argv) +{ + // handle any command line args here + + mb_runtime_sptr rt = mb_make_runtime(); + pmt_t result = PMT_NIL; + + rt->run("top", "test_usrp_rx", PMT_F, &result); +} diff --git a/usrp/host/apps-inband/test_usrp_inband_ping.cc b/usrp/host/apps-inband/test_usrp_inband_ping.cc index a68f4927..5a82f0c3 100644 --- a/usrp/host/apps-inband/test_usrp_inband_ping.cc +++ b/usrp/host/apps-inband/test_usrp_inband_ping.cc @@ -126,7 +126,7 @@ test_usrp_inband_ping::test_usrp_inband_ping(mb_runtime *runtime, const std::str pmt_from_long(128)); pmt_dict_set(usrp_dict, - pmt_intern("interp-rx"), + pmt_intern("decim-rx"), pmt_from_long(16)); d_tx = define_port("tx0", "usrp-tx", false, mb_port::INTERNAL); diff --git a/usrp/host/apps-inband/test_usrp_inband_registers.cc b/usrp/host/apps-inband/test_usrp_inband_registers.cc index 922b6215..2ff42a05 100644 --- a/usrp/host/apps-inband/test_usrp_inband_registers.cc +++ b/usrp/host/apps-inband/test_usrp_inband_registers.cc @@ -127,7 +127,7 @@ test_usrp_inband_registers::test_usrp_inband_registers(mb_runtime *runtime, cons pmt_from_long(128)); pmt_dict_set(usrp_dict, - pmt_intern("interp-rx"), + pmt_intern("decim-rx"), pmt_from_long(16)); d_tx = define_port("tx0", "usrp-tx", false, mb_port::INTERNAL); diff --git a/usrp/host/apps-inband/test_usrp_inband_rx.cc b/usrp/host/apps-inband/test_usrp_inband_rx.cc index 4820c2d4..c37c19c0 100644 --- a/usrp/host/apps-inband/test_usrp_inband_rx.cc +++ b/usrp/host/apps-inband/test_usrp_inband_rx.cc @@ -39,32 +39,13 @@ #include #include -// Signal set for the USRP server -static pmt_t s_cmd_allocate_channel = pmt_intern("cmd-allocate-channel"); -static pmt_t s_cmd_close = pmt_intern("cmd-close"); -static pmt_t s_cmd_deallocate_channel = pmt_intern("cmd-deallocate-channel"); -static pmt_t s_cmd_open = pmt_intern("cmd-open"); -static pmt_t s_cmd_start_recv_raw_samples = pmt_intern("cmd-start-recv-raw-samples"); -static pmt_t s_cmd_stop_recv_raw_samples = pmt_intern("cmd-stop-recv-raw-samples"); -static pmt_t s_cmd_to_control_channel = pmt_intern("cmd-to-control-channel"); -static pmt_t s_cmd_xmit_raw_frame = pmt_intern("cmd-xmit-raw-frame"); -static pmt_t s_cmd_max_capacity = pmt_intern("cmd-max-capacity"); -static pmt_t s_cmd_ntx_chan = pmt_intern("cmd-ntx-chan"); -static pmt_t s_cmd_nrx_chan = pmt_intern("cmd-nrx-chan"); -static pmt_t s_cmd_current_capacity_allocation = pmt_intern("cmd-current-capacity-allocation"); -static pmt_t s_response_allocate_channel = pmt_intern("response-allocate-channel"); -static pmt_t s_response_close = pmt_intern("response-close"); -static pmt_t s_response_deallocate_channel = pmt_intern("response-deallocate-channel"); -static pmt_t s_response_from_control_channel = pmt_intern("response-from-control-channel"); -static pmt_t s_response_open = pmt_intern("response-open"); -static pmt_t s_response_recv_raw_samples = pmt_intern("response-recv-raw-samples"); -static pmt_t s_response_xmit_raw_frame = pmt_intern("response-xmit-raw-frame"); -static pmt_t s_response_max_capacity = pmt_intern("response-max-capacity"); -static pmt_t s_response_ntx_chan = pmt_intern("response-ntx-chan"); -static pmt_t s_response_nrx_chan = pmt_intern("response-nrx-chan"); -static pmt_t s_response_current_capacity_allocation = pmt_intern("response-current-capacity-allocation"); - -static bool verbose = false; +// Include the symbols needed for communication with USRP server +#include +#include +#include +#include + +static bool verbose = true; class test_usrp_rx : public mb_mblock { @@ -72,8 +53,6 @@ class test_usrp_rx : public mb_mblock mb_port_sptr d_cs; pmt_t d_rx_chan; // returned tx channel handle - bool d_disk_write; - enum state_t { INIT, OPENING_USRP, @@ -87,6 +66,9 @@ class test_usrp_rx : public mb_mblock std::ofstream d_ofile; + long d_samples_recvd; + long d_samples_to_recv; + public: test_usrp_rx(mb_runtime *runtime, const std::string &instance_name, pmt_t user_arg); ~test_usrp_rx(); @@ -106,54 +88,34 @@ class test_usrp_rx : public mb_mblock test_usrp_rx::test_usrp_rx(mb_runtime *runtime, const std::string &instance_name, pmt_t user_arg) : mb_mblock(runtime, instance_name, user_arg), - d_disk_write(false) + d_samples_recvd(0), + d_samples_to_recv(5e6) { d_rx = define_port("rx0", "usrp-rx", false, mb_port::INTERNAL); d_cs = define_port("cs", "usrp-server-cs", false, mb_port::INTERNAL); - //bool fake_usrp_p = true; - bool fake_usrp_p = false; - - d_disk_write = true; - - // Test the TX side - // Pass a dictionary to usrp_server which specifies which interface to use, the stub or USRP pmt_t usrp_dict = pmt_make_dict(); - if(fake_usrp_p) - pmt_dict_set(usrp_dict, - pmt_intern("fake-usrp"), - PMT_T); - // Specify the RBF to use pmt_dict_set(usrp_dict, pmt_intern("rbf"), - pmt_intern("tmac6.rbf")); + pmt_intern("nanocell9.rbf")); - // Set TX and RX interpolations pmt_dict_set(usrp_dict, - pmt_intern("interp-tx"), + pmt_intern("decim-rx"), pmt_from_long(128)); - pmt_dict_set(usrp_dict, - pmt_intern("interp-rx"), - pmt_from_long(16)); - define_component("server", "usrp_server", usrp_dict); connect("self", "rx0", "server", "rx0"); connect("self", "cs", "server", "cs"); - if(d_disk_write) - d_ofile.open("pdump_rx.dat",std::ios::binary|std::ios::out); } test_usrp_rx::~test_usrp_rx() { - if(d_disk_write) - d_ofile.close(); } void @@ -173,95 +135,119 @@ test_usrp_rx::handle_message(mb_message_sptr msg) std::string error_msg; switch(d_state){ - case OPENING_USRP: - if (pmt_eq(event, s_response_open)){ - status = pmt_nth(1, data); - if (pmt_eq(status, PMT_T)){ - allocate_channel(); - return; - } - else { - error_msg = "failed to open usrp:"; - goto bail; - } - } - goto unhandled; - case ALLOCATING_CHANNEL: - if (pmt_eq(event, s_response_allocate_channel)){ - status = pmt_nth(1, data); - d_rx_chan = pmt_nth(2, data); - - if (pmt_eq(status, PMT_T)){ - enter_receiving(); - return; + //----------------------------- OPENING_USRP ----------------------------// + // We only expect a response from opening the USRP which should be succesful + // or failed. + case OPENING_USRP: + if (pmt_eq(event, s_response_open)){ + status = pmt_nth(1, data); + if (pmt_eq(status, PMT_T)){ + allocate_channel(); + return; + } + else { + error_msg = "failed to open usrp:"; + goto bail; + } } - else { - error_msg = "failed to allocate channel:"; - goto bail; + goto unhandled; + + //----------------------- ALLOCATING CHANNELS --------------------// + // Allocate an RX channel to perform the overrun test. + case ALLOCATING_CHANNEL: + if (pmt_eq(event, s_response_allocate_channel)){ + status = pmt_nth(1, data); + d_rx_chan = pmt_nth(2, data); + + if (pmt_eq(status, PMT_T)){ + enter_receiving(); + return; + } + else { + error_msg = "failed to allocate channel:"; + goto bail; + } } - } - goto unhandled; - - case RECEIVING: - if (pmt_eq(event, s_response_recv_raw_samples)){ - status = pmt_nth(1, data); - - if (pmt_eq(status, PMT_T)){ - handle_response_recv_raw_samples(data); - return; + goto unhandled; + + //--------------------------- RECEIVING ------------------------------// + // In the receiving state, we receive samples until the specified amount + // while counting the number of overruns. + case RECEIVING: + if (pmt_eq(event, s_response_recv_raw_samples)){ + status = pmt_nth(1, data); + + if (pmt_eq(status, PMT_T)){ + handle_response_recv_raw_samples(data); + return; + } + else { + error_msg = "bad response-xmit-raw-frame:"; + goto bail; + } } - else { - error_msg = "bad response-xmit-raw-frame:"; - goto bail; + goto unhandled; + + //------------------------- CLOSING CHANNEL ----------------------------// + // Check deallocation response for the RX channel + case CLOSING_CHANNEL: + if (pmt_eq(event, s_response_deallocate_channel)){ + status = pmt_nth(1, data); + + if (pmt_eq(status, PMT_T)){ + close_usrp(); + return; + } + else { + error_msg = "failed to deallocate channel:"; + goto bail; + } } - } - goto unhandled; - case CLOSING_CHANNEL: - if (pmt_eq(event, s_response_deallocate_channel)){ - status = pmt_nth(1, data); - - if (pmt_eq(status, PMT_T)){ - close_usrp(); + // Alternately, we ignore all response recv samples while waiting for the + // channel to actually close + if (pmt_eq(event, s_response_recv_raw_samples)) return; - } - else { - error_msg = "failed to deallocate channel:"; - goto bail; - } - } - goto unhandled; - - case CLOSING_USRP: - if (pmt_eq(event, s_response_close)){ - status = pmt_nth(1, data); - if (pmt_eq(status, PMT_T)){ - shutdown_all(PMT_T); - return; + goto unhandled; + + //--------------------------- CLOSING USRP ------------------------------// + // Once we have received a successful USRP close response, we shutdown all + // mblocks and exit. + case CLOSING_USRP: + if (pmt_eq(event, s_response_close)){ + status = pmt_nth(1, data); + + if (pmt_eq(status, PMT_T)){ + fflush(stdout); + shutdown_all(PMT_T); + return; + } + else { + error_msg = "failed to close USRP:"; + goto bail; + } } - else { - error_msg = "failed to close USRP:"; - goto bail; - } - } - goto unhandled; + goto unhandled; - default: - goto unhandled; + default: + goto unhandled; } return; + // An error occured, print it, and shutdown all m-blocks bail: std::cerr << error_msg << data << "status = " << status << std::endl; shutdown_all(PMT_F); return; + // Received an unhandled message for a specific state unhandled: - std::cout << "test_usrp_inband_rx: unhandled msg: " << msg - << "in state "<< d_state << std::endl; + if(verbose && !pmt_eq(event, pmt_intern("%shutdown"))) + std::cout << "test_usrp_inband_tx: unhandled msg: " << msg + << "in state "<< d_state << std::endl; } @@ -272,6 +258,9 @@ test_usrp_rx::open_usrp() d_cs->send(s_cmd_open, pmt_list2(PMT_NIL, which_usrp)); d_state = OPENING_USRP; + + if(verbose) + std::cout << "[TEST_USRP_INBAND_RX] Opening the USRP\n"; } void @@ -279,6 +268,9 @@ test_usrp_rx::close_usrp() { d_cs->send(s_cmd_close, pmt_list1(PMT_NIL)); d_state = CLOSING_USRP; + + if(verbose) + std::cout << "[TEST_USRP_INBAND_RX] Closing the USRP\n"; } void @@ -287,6 +279,9 @@ test_usrp_rx::allocate_channel() long capacity = (long) 16e6; d_rx->send(s_cmd_allocate_channel, pmt_list2(PMT_T, pmt_from_long(capacity))); d_state = ALLOCATING_CHANNEL; + + if(verbose) + std::cout << "[TEST_USRP_INBAND_RX] Requesting RX channel allocation\n"; } void @@ -297,6 +292,9 @@ test_usrp_rx::enter_receiving() d_rx->send(s_cmd_start_recv_raw_samples, pmt_list2(PMT_F, d_rx_chan)); + + if(verbose) + std::cout << "[TEST_USRP_INBAND_RX] Receiving...\n"; } void @@ -308,26 +306,20 @@ test_usrp_rx::handle_response_recv_raw_samples(pmt_t data) pmt_t timestamp = pmt_nth(3, data); pmt_t properties = pmt_nth(4, data); - size_t n_bytes; - - const char *samples = (const char *) pmt_uniform_vector_elements(v_samples, n_bytes); + d_samples_recvd += pmt_length(v_samples) / 4; - if(d_disk_write) - d_ofile.write(samples, n_bytes); + // Check for overrun + if(!pmt_is_dict(properties)) { + std::cout << "[TEST_USRP_INBAND_RX] Recv samples dictionary is improper\n"; + return; + } - if(verbose) - std::cout << "."; - - if (pmt_is_dict(properties)) { - // Read the RSSI - if(pmt_t rssi = pmt_dict_ref(properties, - pmt_intern("rssi"), - PMT_NIL)) { - if(!pmt_eqv(rssi, PMT_NIL)) - std::cout << "RSSI: " << rssi << std::endl; - } + // Check if the number samples we have received meets the test + if(d_samples_recvd >= d_samples_to_recv) { + d_rx->send(s_cmd_stop_recv_raw_samples, pmt_list2(PMT_NIL, d_rx_chan)); + enter_closing_channel(); + return; } - } @@ -336,7 +328,12 @@ test_usrp_rx::enter_closing_channel() { d_state = CLOSING_CHANNEL; + sleep(2); + d_rx->send(s_cmd_deallocate_channel, pmt_list2(PMT_NIL, d_rx_chan)); + + if(verbose) + std::cout << "[TEST_USRP_INBAND_RX] Deallocating RX channel\n"; } REGISTER_MBLOCK_CLASS(test_usrp_rx); diff --git a/usrp/host/apps-inband/test_usrp_inband_timestamps.cc b/usrp/host/apps-inband/test_usrp_inband_timestamps.cc index d48c2a78..d24f5efc 100644 --- a/usrp/host/apps-inband/test_usrp_inband_timestamps.cc +++ b/usrp/host/apps-inband/test_usrp_inband_timestamps.cc @@ -34,12 +34,12 @@ #include #include #include -#include #include #include #include #include +#include #include #include #include @@ -143,7 +143,7 @@ test_usrp_inband_timestamps::test_usrp_inband_timestamps(mb_runtime *runtime, co pmt_from_long(128)); pmt_dict_set(usrp_dict, - pmt_intern("interp-rx"), + pmt_intern("decim-rx"), pmt_from_long(16)); // Specify the RBF to use diff --git a/usrp/host/apps-inband/test_usrp_inband_tx.cc b/usrp/host/apps-inband/test_usrp_inband_tx.cc index 18d36213..6d269a4d 100644 --- a/usrp/host/apps-inband/test_usrp_inband_tx.cc +++ b/usrp/host/apps-inband/test_usrp_inband_tx.cc @@ -34,11 +34,11 @@ #include #include #include -#include #include #include #include +#include #include #include #include @@ -121,7 +121,7 @@ test_usrp_tx::test_usrp_tx(mb_runtime *runtime, const std::string &instance_name // Specify the RBF to use pmt_dict_set(usrp_dict, pmt_intern("rbf"), - pmt_intern("boe3.rbf")); + pmt_intern("cs1.rbf")); // Set TX and RX interpolations pmt_dict_set(usrp_dict, @@ -129,7 +129,7 @@ test_usrp_tx::test_usrp_tx(mb_runtime *runtime, const std::string &instance_name pmt_from_long(128)); pmt_dict_set(usrp_dict, - pmt_intern("interp-rx"), + pmt_intern("decim-rx"), pmt_from_long(16)); pmt_dict_set(usrp_dict, @@ -298,13 +298,13 @@ test_usrp_tx::enter_transmitting() d_nsamples_xmitted = 0; // FIXME: carrier sense hack -// d_tx->send(s_cmd_to_control_channel, // C/S packet -// pmt_list2(PMT_NIL, // invoc handle -// pmt_list1( -// pmt_list2(s_op_write_reg, -// pmt_list2( -// pmt_from_long(1), -// pmt_from_long(0)))))); + d_tx->send(s_cmd_to_control_channel, // C/S packet + pmt_list2(PMT_NIL, // invoc handle + pmt_list1( + pmt_list2(s_op_write_reg, + pmt_list2( + pmt_from_long(1), + pmt_from_long(21)))))); build_and_send_next_frame(); // fire off 4 to start pipeline build_and_send_next_frame(); @@ -357,12 +357,18 @@ test_usrp_tx::build_and_send_next_frame() } } + pmt_t tx_properties = pmt_make_dict(); + pmt_dict_set(tx_properties, + pmt_intern("carrier-sense"), + PMT_T); + pmt_t timestamp = pmt_from_long(0xffffffff); // NOW d_tx->send(s_cmd_xmit_raw_frame, - pmt_list4(pmt_from_long(d_nframes_xmitted), // invocation-handle + pmt_list5(pmt_from_long(d_nframes_xmitted), // invocation-handle d_tx_chan, // channel uvec, // the samples - timestamp)); + timestamp, + tx_properties)); d_nsamples_xmitted += nsamples_this_frame; d_nframes_xmitted++; diff --git a/usrp/host/apps-inband/test_usrp_inband_underrun.cc b/usrp/host/apps-inband/test_usrp_inband_underrun.cc index 61ea9623..411e8877 100644 --- a/usrp/host/apps-inband/test_usrp_inband_underrun.cc +++ b/usrp/host/apps-inband/test_usrp_inband_underrun.cc @@ -129,7 +129,7 @@ test_usrp_inband_underrun::test_usrp_inband_underrun(mb_runtime *runtime, const d_rx_chan(PMT_NIL), d_which_usrp(pmt_from_long(0)), d_state(INIT), - d_nsamples_to_send((long) 50e6), + d_nsamples_to_send((long) 20e6), d_nsamples_xmitted(0), d_nframes_xmitted(0), d_samples_per_frame(d_nsamples_to_send), // full packet @@ -145,16 +145,16 @@ test_usrp_inband_underrun::test_usrp_inband_underrun(mb_runtime *runtime, const // Specify the RBF to use pmt_dict_set(usrp_dict, pmt_intern("rbf"), - pmt_intern("merge4.rbf")); + pmt_intern("nanocell9.rbf")); // Set TX and RX interpolations pmt_dict_set(usrp_dict, pmt_intern("interp-tx"), - pmt_from_long(16)); + pmt_from_long(8)); pmt_dict_set(usrp_dict, - pmt_intern("interp-rx"), - pmt_from_long(16)); + pmt_intern("decim-rx"), + pmt_from_long(128)); d_tx = define_port("tx0", "usrp-tx", false, mb_port::INTERNAL); d_rx = define_port("rx0", "usrp-rx", false, mb_port::INTERNAL); @@ -265,7 +265,7 @@ test_usrp_inband_underrun::handle_message(mb_message_sptr msg) // If the RX has also been allocated already, we can continue if(!pmt_eqv(d_rx_chan, PMT_NIL)) { enter_receiving(); - //enter_transmitting(); + enter_transmitting(); } return; @@ -294,7 +294,7 @@ test_usrp_inband_underrun::handle_message(mb_message_sptr msg) // If the TX has also been allocated already, we can continue if(!pmt_eqv(d_tx_chan, PMT_NIL)) { enter_receiving(); - //enter_transmitting(); + enter_transmitting(); } return; @@ -409,6 +409,7 @@ test_usrp_inband_underrun::handle_message(mb_message_sptr msg) std::cout << "[TEST_USRP_INBAND_UNDERRUN] Successfully closed USRP\n"; std::cout << "\nUnderruns: " << d_n_underruns << std::endl; + fflush(stdout); shutdown_all(PMT_T); return; @@ -616,9 +617,9 @@ void test_usrp_inband_underrun::handle_xmit_response(pmt_t handle) { if (d_done_sending && - pmt_to_long(handle) == (d_nframes_xmitted - 1)){ + pmt_to_long(handle) == (d_nframes_xmitted - 1)){ // We're done sending and have received all responses - //closing_channels(); + closing_channels(); return; } @@ -637,14 +638,19 @@ test_usrp_inband_underrun::handle_recv_response(pmt_t dict) if(pmt_t underrun = pmt_dict_ref(dict, pmt_intern("underrun"), PMT_NIL)) { - if(pmt_eqv(underrun, PMT_T)) + if(pmt_eqv(underrun, PMT_T)) { d_n_underruns++; - if(verbose) - std::cout << "[TEST_USRP_INBAND_UNDERRUN] Underrun\n"; + if(verbose && 0) + std::cout << "[TEST_USRP_INBAND_UNDERRUN] Underrun\n"; + } + else { + if(verbose && 0) + std::cout << "[TEST_USRP_INBAND_UNDERRUN] No underrun\n" << underrun <send(s_cmd_close, pmt_list1(PMT_NIL)); } diff --git a/usrp/host/apps-inband/time_stuff.c b/usrp/host/apps-inband/time_stuff.c deleted file mode 100644 index 89a4a381..00000000 --- a/usrp/host/apps-inband/time_stuff.c +++ /dev/null @@ -1,68 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include "time_stuff.h" - -#include -#ifdef HAVE_SYS_RESOURCE_H -#include -#endif -#include - -static double -timeval_to_secs (struct timeval *tv) -{ - return (double) tv->tv_sec + (double) tv->tv_usec * 1e-6; -} - -double -get_cpu_usage (void) -{ -#ifdef HAVE_GETRUSAGE - struct rusage ru; - - if (getrusage (RUSAGE_SELF, &ru) != 0) - return 0; - - return timeval_to_secs (&ru.ru_utime) + timeval_to_secs (&ru.ru_stime); -#else - return 0; /* FIXME */ -#endif -} - -/* - * return elapsed time (wall time) in seconds - */ -double -get_elapsed_time (void) -{ - struct timeval tv; - if (gettimeofday (&tv, 0) != 0) - return 0; - - return timeval_to_secs (&tv); -} - diff --git a/usrp/host/apps-inband/time_stuff.h b/usrp/host/apps-inband/time_stuff.h deleted file mode 100644 index 74b79f38..00000000 --- a/usrp/host/apps-inband/time_stuff.h +++ /dev/null @@ -1,48 +0,0 @@ -/* -*- c++ -*- */ -/* - * Copyright 2003 Free Software Foundation, Inc. - * - * This file is part of GNU Radio - * - * GNU Radio is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3, or (at your option) - * any later version. - * - * GNU Radio is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with GNU Radio; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifndef _TIME_STUFF_H_ -#define _TIME_STUFF_H_ - - - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * return USER + SYS cpu time in seconds - */ -double get_cpu_usage (void); - -/* - * return elapsed time in seconds - */ -double get_elapsed_time (void); - - -#ifdef __cplusplus -} -#endif - - -#endif /* _TIME_STUFF_H_ */ diff --git a/usrp/host/apps-inband/ui_sincos.c b/usrp/host/apps-inband/ui_sincos.c index 36ca89c7..27841f01 100644 --- a/usrp/host/apps-inband/ui_sincos.c +++ b/usrp/host/apps-inband/ui_sincos.c @@ -26,7 +26,7 @@ #define _GNU_SOURCE // ask for GNU extensions if available -#include +#include "ui_sincos.h" #include // ---------------------------------------------------------------- diff --git a/usrp/host/lib/inband/usrp_inband_usb_packet.h b/usrp/host/lib/inband/usrp_inband_usb_packet.h index 9290f55a..8c19b1ae 100644 --- a/usrp/host/lib/inband/usrp_inband_usb_packet.h +++ b/usrp/host/lib/inband/usrp_inband_usb_packet.h @@ -64,8 +64,9 @@ public: FL_DROPPED = 0x20000000, FL_START_OF_BURST = 0x10000000, FL_END_OF_BURST = 0x08000000, + FL_CARRIER_SENSE = 0x04000000, - FL_ALL_FLAGS = 0xf8000000 + FL_ALL_FLAGS = 0xfc000000 }; static const int FL_OVERRUN_SHIFT = 31; diff --git a/usrp/host/lib/inband/usrp_rx.cc b/usrp/host/lib/inband/usrp_rx.cc index 7344a6e8..caa2d717 100644 --- a/usrp/host/lib/inband/usrp_rx.cc +++ b/usrp/host/lib/inband/usrp_rx.cc @@ -119,7 +119,7 @@ usrp_rx::read_and_respond(pmt_t data) return; } - if(underrun) + if(underrun && verbose && 0) std::cout << "[usrp_rx] Underrun\n"; d_cs->send(s_response_usrp_rx_read, diff --git a/usrp/host/lib/inband/usrp_rx_stub.cc b/usrp/host/lib/inband/usrp_rx_stub.cc index bf78ddf2..5ea8135a 100644 --- a/usrp/host/lib/inband/usrp_rx_stub.cc +++ b/usrp/host/lib/inband/usrp_rx_stub.cc @@ -33,7 +33,7 @@ #include #include "usrp_standard.h" #include -#include "ui_nco.h" +#include #include #include diff --git a/usrp/host/lib/inband/usrp_rx_stub.h b/usrp/host/lib/inband/usrp_rx_stub.h index 483af5b4..5a75bf00 100644 --- a/usrp/host/lib/inband/usrp_rx_stub.h +++ b/usrp/host/lib/inband/usrp_rx_stub.h @@ -24,7 +24,7 @@ #include #include #include "usrp_standard.h" -#include "ui_nco.h" +#include #include #include #include diff --git a/usrp/host/lib/inband/usrp_server.cc b/usrp/host/lib/inband/usrp_server.cc index 760397dc..d73c7d52 100644 --- a/usrp/host/lib/inband/usrp_server.cc +++ b/usrp/host/lib/inband/usrp_server.cc @@ -53,6 +53,8 @@ usrp_server::usrp_server(mb_runtime *rt, const std::string &instance_name, pmt_t : mb_mblock(rt, instance_name, user_arg), d_fake_rx(false) { + if(verbose) + std::cout << "[USRP_SERVER] Initializing...\n"; // Dictionary for arguments to all of the components pmt_t usrp_dict = user_arg; @@ -596,11 +598,26 @@ void usrp_server::handle_cmd_xmit_raw_frame(mb_port_sptr port, std::vector