From: kbongers <kbongers@4a8a32a2-be11-0410-ad9d-d568d2c75423>
Date: Mon, 18 Feb 2002 04:57:50 +0000 (+0000)
Subject: minor work
X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=43bf8451d1a94f47b5f035e0058a1d4d7b2bd35d;p=fw%2Fsdcc

minor work


git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1934 4a8a32a2-be11-0410-ad9d-d568d2c75423
---

diff --git a/sim/ucsim/xa.src/glob.cc b/sim/ucsim/xa.src/glob.cc
index 7381bf32..e17c6b54 100644
--- a/sim/ucsim/xa.src/glob.cc
+++ b/sim/ucsim/xa.src/glob.cc
@@ -285,7 +285,9 @@ struct xa_dis_entry disass_xa[]= {
  {0,0x97c0,0xfffc,' ',4, JBC,   BIT_REL8     }, //  JBC bit,rel8               1 0 0 1 0 1 1 1  1 1 0 0 0 0 b b
  {1,0xd500,0xff00,' ',3, JMP,   REL16        }, //  JMP rel16                  1 1 0 1 0 1 0 1  rel16
  {0,0xd670,0xfff8,' ',2, JMP,   IREG         }, //  JMP [Rs]                   1 1 0 1 0 1 1 0  0 1 1 1 0 s s s
- /* JMP(2) */
+ {0,0xd646,0xffff,' ',2, JMP,   A_PLUSDPTR   }, //  JMP [A+dptr]               1 1 0 1 0 1 1 0  0 1 0 0 0 1 1 0
+ {0,0xd660,0xfff8,' ',2, JMP,   IIREG        }, //  JMP [[Rs+]]                1 1 0 1 0 1 1 0  0 1 1 0 0 s s s
+
  {0,0x97a0,0xfffc,' ',4, JNB,   BIT_REL8     }, //  JNB bit,rel8               1 0 0 1 0 1 1 1  1 0 1 0 0 0 b b
  {1,0xee00,0xff00,' ',2, JNZ,   REL8         }, //  JNZ rel8                   1 1 1 0 1 1 1 0  rel8
  {1,0xec00,0xff00,' ',2, JZ,    REL8         }, //  JZ rel8                    1 1 1 0 1 1 0 0  rel8
diff --git a/sim/ucsim/xa.src/glob.h b/sim/ucsim/xa.src/glob.h
index 008bef38..be31e94c 100644
--- a/sim/ucsim/xa.src/glob.h
+++ b/sim/ucsim/xa.src/glob.h
@@ -185,7 +185,9 @@ enum op_operands {
   IREG_DATA16_REL8,
 
   A_APLUSDPTR,
-  A_APLUSPC
+  A_APLUSPC,
+  A_PLUSDPTR,
+  IIREG
 };
 
 // table of dissassembled instructions
diff --git a/sim/ucsim/xa.src/inst.cc b/sim/ucsim/xa.src/inst.cc
index f96a9002..1ed332e1 100644
--- a/sim/ucsim/xa.src/inst.cc
+++ b/sim/ucsim/xa.src/inst.cc
@@ -224,6 +224,10 @@ int cl_xa::inst_ASL(uint code, int operands)
           if ((dst & 0xffff) == 0)
             flags |= BIT_Z;
         break;
+        case 2: // ?
+          // not really sure about the encoding here..
+          NOTDONE_ASSERT;
+        break;
         case 3:  // dword
           //dst = reg4(RI_F0);
           dst = reg2(RI_F0) | (reg2(RI_F0 + 2) << 16);
@@ -262,6 +266,10 @@ int cl_xa::inst_ASL(uint code, int operands)
           if ((dst & 0xffff) == 0)
             flags |= BIT_Z;
         break;
+        case 2: // ?
+          // not really sure about the encoding here..
+          NOTDONE_ASSERT;
+        break;
         case 3:  // dword
           dst = reg1(RI_F0 & 0xe);
           cnt = operands & 0x1f;
@@ -282,9 +290,105 @@ int cl_xa::inst_ASL(uint code, int operands)
   return(resGO);
 }
 
+/* arithmetic shift right */
 int cl_xa::inst_ASR(uint code, int operands)
 {
-  NOTDONE_ASSERT;
+  unsigned int dst, cnt;
+  unsigned char flags;
+
+  /* ASR, dest, count
+    while (count != 0)
+      C = dest.0; dest >>= 1;
+      this is a confusing one...
+  */
+
+  flags = get_psw();
+  flags &= ~BIT_ALL; /* clear these bits */
+
+  switch(operands) {
+    case REG_REG :
+      cnt = reg1(RI_0F) & 0x1f;
+      switch (code & 0xc00) {
+        case 0: // byte
+          dst = reg1(RI_F0);
+          if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
+            flags |= BIT_C;
+          if (dst & 0x01)
+            flags |= BIT_C;
+          dst >>= cnt;
+          set_reg1(RI_F0,dst);
+          if ((dst & 0xff) == 0)
+            flags |= BIT_Z;
+        break;
+        case 1: // word
+          dst = reg2(RI_F0);
+          if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
+            flags |= BIT_C;
+          dst >>= cnt;
+          set_reg2(RI_F0,dst);
+          if ((dst & 0xffff) == 0)
+            flags |= BIT_Z;
+        break;
+        case 2: // ?
+          // not really sure about the encoding here..
+          NOTDONE_ASSERT;
+        break;
+        case 3:  // dword
+          dst = reg2(RI_F0) | (reg2(RI_F0 + 2) << 16);
+          if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
+            flags |= BIT_C;
+          dst >>= cnt;
+          set_reg2(RI_F0,dst & 0xffff);
+          set_reg2(RI_F0+2, (dst>>16) & 0xffff);
+          if (dst == 0)
+            flags |= BIT_Z;
+        break;
+      }
+    break;
+
+    case REG_DATA4 :
+    case REG_DATA5 :
+      switch (code & 0xc00) {
+        case 0: // byte
+          dst = reg1(RI_F0);
+          cnt = operands & 0x0f;
+          if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
+            flags |= BIT_C;
+          dst >>= cnt;
+          set_reg1(RI_F0,dst);
+          if ((dst & 0xff) == 0)
+            flags |= BIT_Z;
+        break;
+        case 1: // word
+          dst = reg2(RI_F0);
+          cnt = operands & 0x0f;
+          if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
+            flags |= BIT_C;
+          dst >>= cnt;
+          set_reg2(RI_F0,dst);
+          if ((dst & 0xffff) == 0)
+            flags |= BIT_Z;
+        break;
+        case 2: // ?
+          // not really sure about the encoding here..
+          NOTDONE_ASSERT;
+        break;
+        case 3:  // dword
+          dst = reg1(RI_F0 & 0xe);
+          cnt = operands & 0x1f;
+          if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
+            flags |= BIT_C;
+          dst >>= cnt;
+          set_reg2(RI_F0,dst & 0xffff);
+          set_reg2(RI_F0+2, (dst>>16) & 0xffff);
+          if (dst == 0)
+            flags |= BIT_Z;
+        break;
+      }
+    break;
+  }
+  set_psw(flags);
+
   return(resGO);
 }
 
diff --git a/sim/ucsim/xa.src/xa.cc b/sim/ucsim/xa.src/xa.cc
index cd6084f1..da7ed0fc 100644
--- a/sim/ucsim/xa.src/xa.cc
+++ b/sim/ucsim/xa.src/xa.cc
@@ -668,6 +668,15 @@ cl_xa::disass(t_addr addr, char *sep)
 	        (get_mem(MEM_ROM, addr+immed_offset+0)<<8));
       break;
 
+    case A_PLUSDPTR :
+      strcpy(parm_str, "[A+DPTR]");
+      break;
+
+    case IIREG :
+      sprintf(parm_str, "[[%s]]",
+              w_reg_strs[(code & 0x7)]);
+      break;
+
     default:
       strcpy(parm_str, "???");
     break;