From: Keith Packard Date: Tue, 2 Nov 2010 00:30:49 +0000 (-0700) Subject: altos: Split out SPI driver. Add Numonyx M25P driver for TT. X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=3d70461d5860ce8b86ecf900925e2b48f19ce040;p=fw%2Faltos altos: Split out SPI driver. Add Numonyx M25P driver for TT. For TT (and TM with the companion connector), the SPI bus will be shared among multiple devices. Split out the existing SPI code into a common driver, with the SPI bus protected by a mutex. Add the Numonyx M25Pxx driver to support the flash chips on TT and newer TM versions. This is not yet integrated into the TM code. Signed-off-by: Keith Packard --- diff --git a/src/Makefile.proto b/src/Makefile.proto index 1a590969..fe916a9d 100644 --- a/src/Makefile.proto +++ b/src/Makefile.proto @@ -71,6 +71,12 @@ TELE_DRIVER_SRC = \ ao_convert.c \ ao_serial.c +# +# Spi bus driver +# +SPI_DRIVER_SRC = \ + ao_spi.c + # # Debug dongle driver (only on TI) # @@ -152,6 +158,9 @@ TT_TASK_SRC = \ ao_audio.c \ ao_terraui.c +TT_DRIVER_SRC = \ + ao_m25.c + # # All sources for TeleTerra # @@ -162,6 +171,7 @@ TT_SRC = \ $(TELE_DRIVER_SRC) \ $(TELE_COMMON_SRC) \ $(TT_MAIN_SRC) \ + $(TT_DRIVER_SRC) \ $(TT_TASK_SRC) # diff --git a/src/ao.h b/src/ao.h index a3519150..7750504f 100644 --- a/src/ao.h +++ b/src/ao.h @@ -478,6 +478,24 @@ ao_ee_read_config(uint8_t *buf, uint16_t len) __reentrant; void ao_ee_init(void); +/* + * ao_m25.c + * + * Numonyx M25P family flash driver + */ + +void +ao_flash_erase_sector(uint8_t sector) __reentrant; + +void +ao_flash_write_page(uint16_t page, __xdata uint8_t d[256]) __reentrant; + +void +ao_flash_read_page(uint16_t page, __xdata uint8_t d[256]) __reentrant; + +void +ao_flash_init(void); + /* * ao_log.c */ @@ -747,6 +765,19 @@ void ao_serial_init(void); #endif +/* + * ao_spi.c + */ + +void +ao_spi_send(void __xdata *block, uint16_t len) __reentrant; + +void +ao_spi_recv(void __xdata *block, uint16_t len) __reentrant; + +void +ao_spi_init(void); + /* * ao_gps.c */ diff --git a/src/ao_audio.c b/src/ao_audio.c index 6b16089d..32a29a27 100644 --- a/src/ao_audio.c +++ b/src/ao_audio.c @@ -277,298 +277,6 @@ __code uint8_t ao_audio_sound[] = { 125, 125, 125, 125, 125, 125, 125, 125, 125, 125, 123, 123, 122, 123, 122, 122, 120, 122, 120, 120, 122, 122, 120, 122, 122, 122, 122, 122, 122, 122, 122, 123, 123, 123, 123, 125, 125, 125, 125, 126, 126, 126, 126, 126, 128, 128, 128, 130, - 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123, 137, 151, 164, 176, 183, 176, 167, 156, 142, 128, 120, 122, 123, 125, 130, - 131, 130, 133, 139, 142, 145, 151, 153, 147, 140, 134, 131, 128, 122, 116, 112, - 112, 109, 108, 111, 117, 123, 131, 139, 147, 150, 151, 148, 145, 144, 140, 139, - 147, 158, 150, 142, 139, 136, 130, 128, 133, 144, 153, 158, 164, 159, 150, 144, - 134, 126, 123, 122, 116, 105, 95, 89, 89, 87, 91, 103, 116, 120, 120, 119, - 116, 112, 108, 109, 112, 112, 108, 103, 97, 92, 91, 91, 94, 95, 97, 101, - 106, 114, 123, 137, 151, 165, 181, 190, 186, 173, 161, 140, 126, 116, 116, 123, - 130, 136, 134, 134, 134, 134, 134, 137, 145, 151, 151, 148, 144, 136, 123, 116, - 111, 111, 116, 116, 117, 116, 116, 119, 122, 130, 137, 147, 153, 155, 159, 161, - 153, 142, 137, 130, 122, 122, 123, 128, 134, 139, 144, 145, 145, 148, 147, 144, - 144, 144, 137, 128, 120, 114, 105, 97, 92, 94, 97, 98, 103, 105, 109, 111, - 111, 114, 116, 116, 116, 114, 109, 106, 100, 95, 95, 97, 97, 95, 95, 97, - 97, 98, 101, 105, 112, 123, 134, 147, 161, 173, 176, 172, 165, 158, 144, 131, - 128, 126, 128, 133, 137, 139, 137, 136, 134, 133, 133, 139, 142, 140, 142, 140, - 139, 133, 125, 119, 116, 114, 116, 117, 122, 126, 130, 133, 136, 137, 142, 145, - 148, 155, 164, 164, 156, 150, 140, 130, 123, 122, 128, 137, 144, 151, 155, 153, - 153, 148, 140, 139, 139, 137, 133, 130, 123, 117, 106, 98, 95, 94, 97, 101, - 106, 109, 109, 111, 112, 112, 111, 111, 109, 108, 108, 108, 103, 97, 94, 89, - 84, 83, 86, 92, 98, 106, 116, 125, 136, 147, 159, 169, 175, 173, 169, 159, - 147, 133, 125, 120, 119, 126, 130, 134, 137, 136, 131, 126, 126, 128, 130, 131, - 136, 137, 136, 131, 125, 119, 112, 109, 108, 111, 117, 123, 128, 133, 137, 140, - 139, 139, 144, 151, 158, 159, 161, 158, 147, 136, 131, 128, 128, 134, 142, 151, - 156, 161, 156, 148, 142, 134, 128, 123, 120, 120, 120, 116, 111, 105, 98, 95, - 94, 94, 97, 101, 109, 112, 114, 116, 109, 106, 101, 100, 98, 97, 97, 98, - 98, 95, 94, 95, 98, 105, 112, 123, 134, 147, 158, 167, 169, 169, 167, 162, - 155, 148, 142, 136, 136, 137, 137, 139, 139, 139, 136, 131, 128, 128, 130, 128, - 131, 133, 133, 131, 128, 125, 120, 119, 117, 116, 119, 123, 126, 131, 136, 139, - 144, 148, 155, 156, 159, 158, 158, 155, 145, 144, 139, 139, 140, 144, 147, 150, - 150, 147, 145, 142, 137, 130, 123, 119, 117, 112, 108, 105, 101, 97, 92, 89, - 89, 91, 91, 94, 97, 98, 100, 98, 100, 101, 100, 98, 95, 92, 89, 89, - 87, 87, 91, 97, 103, 111, 119, 128, 139, 151, 159, 164, 165, 162, 158, 150, - 144, 136, 134, 134, 137, 140, 142, 144, 142, 139, 134, 133, 128, 126, 126, 130, - 131, 131, 131, 130, 128, 125, 122, 119, 119, 120, 123, 130, 139, 151, 158, 162, - 164, 161, 156, 148, 144, 142, 142, 145, 151, 156, 159, 159, 155, 151, 147, 145, - 140, 139, 139, 140, 139, 134, 130, 122, 114, 105, 97, 91, 87, 86, 87, 92, - 95, 95, 94, 95, 94, 92, 92, 94, 98, 101, 105, 105, 105, 105, 100, 101, - 103, 106, 112, 120, 130, 139, 150, 158, 162, 164, 162, 158, 151, 147, 142, 139, - 137, 139, 140, 142, 142, 140, 137, 133, 131, 128, 125, 123, 123, 123, 125, 126, - 126, 126, 123, 122, 120, 119, 119, 120, 128, 137, 145, 153, 159, 162, 162, 158, - 151, 145, 140, 137, 139, 140, 145, 150, 153, 155, 153, 148, 142, 134, 130, 126, - 122, 120, 117, 114, 112, 108, 103, 97, 91, 86, 80, 78, 77, 78, 80, 81, - 83, 84, 86, 87, 89, 91, 91, 91, 94, 95, 100, 103, 108, 116, 122, 126, - 133, 137, 145, 151, 158, 161, 164, 164, 161, 156, 151, 145, 140, 139, 137, 137, - 137, 139, 139, 140, 140, 140, 137, 133, 131, 130, 128, 126, 128, 130, 133, 134, - 136, 139, 140, 145, 148, 150, 153, 155, 156, 158, 158, 159, 161, 161, 161, 159, - 158, 155, 151, 151, 150, 147, 144, 142, 139, 136, 131, 128, 123, 119, 114, 109, - 105, 100, 98, 95, 92, 89, 87, 86, 84, 84, 83, 81, 81, 83, 84, 86, - 87, 91, 94, 98, 100, 103, 108, 112, 117, 125, 134, 142, 148, 150, 148, 147, - 144, 139, 134, 131, 131, 136, 142, 145, 151, 153, 151, 148, 142, 134, 128, 123, - 120, 122, 126, 131, 136, 140, 144, 145, 144, 140, 136, 134, 133, 134, 137, 142, - 145, 150, 151, 153, 151, 151, 148, 145, 144, 142, 142, 140, 142, 140, 140, 139, - 136, 133, 130, 123, 119, 114, 111, 108, 105, 103, 100, 97, 95, 92, 91, 87, - 86, 89, 89, 91, 92, 95, 97, 98, 101, 100, 103, 103, 106, 109, 111, 114, - 119, 122, 125, 128, 130, 133, 133, 134, 136, 137, 137, 139, 140, 140, 140, 140, - 140, 140, 140, 140, 142, 140, 142, 142, 142, 142, 144, 145, 147, 147, 147, 148, - 148, 150, 151, 151, 153, 155, 156, 158, 158, 156, 155, 151, 150, 148, 147, 145, - 144, 144, 144, 142, 140, 137, 136, 134, 131, 128, 125, 122, 120, 116, 114, 111, - 109, 108, 105, 105, 103, 101, 100, 98, 97, 97, 97, 98, 100, 100, 101, 103, - 105, 105, 105, 105, 105, 105, 105, 106, 109, 111, 111, 112, 114, 117, 119, 120, - 119, 120, 120, 122, 122, 125, 126, 130, 133, 134, 137, 136, 136, 137, 137, 137, - 137, 139, 139, 139, 139, 139, 137, 140, 140, 140, 139, 139, 139, 137, 140, 137, - 139, 140, 140, 142, 140, 140, 139, 140, 139, 139, 137, 137, 137, 137, 137, 137, - 137, 137, 137, 137, 136, 134, 133, 130, 128, 125, 123, 123, 123, 122, 120, 117, - 116, 112, 112, 111, 109, 109, 108, 108, 108, 106, 106, 106, 108, 108, 106, 106, - 106, 108, 109, 112, 114, 119, 122, 123, 125, 128, 130, 131, 133, 133, 134, 136, - 140, 142, 145, 147, 147, 147, 145, 144, 142, 139, 137, 137, 139, 140, 139, 139, - 139, 137, 136, 131, 128, 125, 123, 123, 123, 125, 126, 128, 130, 130, 130, 128, - 126, 126, 130, 130, 131, 133, 133, 133, 133, 131, 130, 130, 128, 126, 126, 126, - 126, 126, 125, 123, 120, 119, 116, 112, 111, 109, 109, 109, 111, 111, 111, 111, - 111, 111, 112, 111, 111, 111, 111, 114, 114, 116, 119, 120, 122, 123, 123, 125, - 126, 128, 130, 131, 133, 134, 134, 136, 136, 136, 134, 136, 136, 137, 139, 137, - 139, 137, 139, 137, 137, 137, 136, 136, 136, 136, 134, 134, 136, 134, 136, 137, - 137, 139, 137, 137, 136, 134, 133, 133, 131, 131, 131, 133, 133, 133, 134, 133, - 134, 133, 133, 128, 128, 125, 123, 126, 125, 126, 126, 126, 125, 123, 123, 122, - 120, 120, 120, 120, 120, 120, 122, 122, 122, 123, 122, 122, 122, 122, 122, 123, - 125, 126, 126, 126, 126, 126, 126, 128, 128, 128, 128, 130, 131, 131, 131, 131, - 131, 131, 131, 133, 134, 134, 134, 134, 134, 133, 131, 131, 131, 133, 133, 133, - 133, 134, 136, 134, 134, 131, 133, 131, 130, 130, 128, 130, 128, 128, 126, 125, - 123, 122, 122, 120, 120, 122, 122, 122, 122, 120, 122, 120, 120, 119, 117, 117, - 117, 117, 117, 117, 117, 119, 120, 119, 119, 117, 119, 120, 120, 120, 120, 120, - 120, 122, 122, 122, 122, 122, 122, 122, 123, 125, 125, 126, 126, 125, 126, 126, - 126, 126, 128, 128, 131, 131, 133, 133, 133, 133, 134, 137, 134, 137, 137, 137, - 139, 137, 137, 137, 137, 137, 137, 139, 137, 137, 136, 136, 137, 136, 134, 134, - 131, 130, 130, 131, 131, 131, 131, 131, 128, 128, 126, 125, 123, 125, 125, 125, - 125, 126, 126, 126, 126, 126, 125, 125, 123, 122, 122, 122, 122, 122, 122, 122, - 123, 123, 123, 122, 122, 122, 123, 123, 122, 122, 122, 123, 125, 126, 125, 128, - 126, 126, 125, 123, 122, 122, 123, 125, 126, 128, 130, 131, 133, 133, 133, 131, - 131, 131, 131, 131, 131, 131, 133, 131, 133, 133, 133, 131, 130, 128, 128, 130, - 130, 131, 130, 130, 128, 128, 128, 126, 126, 126, 128, 128, 126, 126, 123, 123, - 123, 123, 123, 123, 125, 125, 125, 125, 125, 123, 123, 123, 123, 123, 125, 125, - 123, 123, 122, 122, 122, 122, 122, 122, 122, 122, 122, 122, 123, 123, 123, 122, - 123, 125, 125, 126, 126, 126, 126, 126, 128, 128, 130, 130, 130, 131, 131, 133, - 134, 134, 134, 134, 134, 134, 136, 136, 137, 137, 137, 137, 136, 136, 136, 134, - 134, 133, 131, 133, 133, 134, 134, 133, 133, 133, 133, 133, 133, 131, 128, 128, - 128, 130, 128, 130, 131, 130, 130, 128, 126, 125, 125, 125, 123, 123, 123, 125, - 125, 125, 125, 123, 123, 123, 125, 125, 125, 125, 125, 123, 123, 122, 122, 123, - 123, 125, 123, 123, 122, 122, 120, 120, 120, 120, 122, 123, 125, 125, 126, 126, - 125, 123, 123, 122, 123, 123, 123, 125, 126, 126, 128, 128, 128, 128, 128, 130, - 130, 130, 126, 130, 128, 130, 130, 128, 131, 128, 128, 126, 126, 126, 130, 130, - 130, 130, 128, 130, 130, 128, 128, 126, 126, 126, 126, 128, 126, 126, 125, 125, - 125, 126, 125, 125, 125, 125, 125, 123, 123, 123, 125, 126, 126, 126, 126, 128, - 128, 126, 125, 125, 125, 123, 125, 125, 125, 126, 126, 126, 128, 126, 126, 126, - 126, 126, 126, 128, 128, 131, 131, 131, 131, 131, 133, 131, 131, 131, 131, 133, - 133, 134, 133, 134, 134, 134, 134, 133, 134, 136, 136, 136, 136, 134, 134, 134, - 133, 133, 131, 133, 133, 131, 133, 130, 130, 130, 130, 131, 130, 128, 126, 126, - 126, 126, 126, 126, 128, 126, 125, 125, 123, 123, 123, 123, 125, 125, 123, 123, - 122, 120, 122, 123, 122, 123, 123, 125, 125, 125, 123, 123, 123, 123, 123, 123, - 123, 123, 123, 123, 125, 123, 125, 123, 125, 125, 123, 123, 123, 125, 125, 125, - 125, 254, }; #define nop() _asm nop _endasm; diff --git a/src/ao_ee.c b/src/ao_ee.c index 26cfb7fd..a67ca12d 100644 --- a/src/ao_ee.c +++ b/src/ao_ee.c @@ -25,15 +25,8 @@ #define EE_CS P1_2 #define EE_CS_INDEX 2 -__xdata uint8_t ao_ee_dma_in_done; -__xdata uint8_t ao_ee_dma_out_done; __xdata uint8_t ao_ee_mutex; -uint8_t ao_ee_dma_out_id; -uint8_t ao_ee_dma_in_id; - -static __xdata uint8_t ao_ee_const = 0xff; - #define ao_ee_delay() do { \ _asm nop _endasm; \ _asm nop _endasm; \ @@ -54,82 +47,6 @@ void ao_ee_cs_high(void) ao_ee_delay(); } -/* Send bytes over SPI. - * - * This sets up two DMA engines, one writing the data and another reading - * bytes coming back. We use the bytes coming back to tell when the transfer - * is complete, as the transmit register is double buffered and hence signals - * completion one byte before the transfer is actually complete - */ -static void -ao_ee_send(void __xdata *block, uint16_t len) -{ - ao_dma_set_transfer(ao_ee_dma_in_id, - &U0DBUFXADDR, - &ao_ee_const, - len, - DMA_CFG0_WORDSIZE_8 | - DMA_CFG0_TMODE_SINGLE | - DMA_CFG0_TRIGGER_URX0, - DMA_CFG1_SRCINC_0 | - DMA_CFG1_DESTINC_0 | - DMA_CFG1_PRIORITY_NORMAL); - - ao_dma_set_transfer(ao_ee_dma_out_id, - block, - &U0DBUFXADDR, - len, - DMA_CFG0_WORDSIZE_8 | - DMA_CFG0_TMODE_SINGLE | - DMA_CFG0_TRIGGER_UTX0, - DMA_CFG1_SRCINC_1 | - DMA_CFG1_DESTINC_0 | - DMA_CFG1_PRIORITY_NORMAL); - - ao_dma_start(ao_ee_dma_in_id); - ao_dma_start(ao_ee_dma_out_id); - ao_dma_trigger(ao_ee_dma_out_id); - __critical while (!ao_ee_dma_in_done) - ao_sleep(&ao_ee_dma_in_done); -} - -/* Receive bytes over SPI. - * - * This sets up tow DMA engines, one reading the data and another - * writing constant values to the SPI transmitter as that is what - * clocks the data coming in. - */ -static void -ao_ee_recv(void __xdata *block, uint16_t len) -{ - ao_dma_set_transfer(ao_ee_dma_in_id, - &U0DBUFXADDR, - block, - len, - DMA_CFG0_WORDSIZE_8 | - DMA_CFG0_TMODE_SINGLE | - DMA_CFG0_TRIGGER_URX0, - DMA_CFG1_SRCINC_0 | - DMA_CFG1_DESTINC_1 | - DMA_CFG1_PRIORITY_NORMAL); - - ao_dma_set_transfer(ao_ee_dma_out_id, - &ao_ee_const, - &U0DBUFXADDR, - len, - DMA_CFG0_WORDSIZE_8 | - DMA_CFG0_TMODE_SINGLE | - DMA_CFG0_TRIGGER_UTX0, - DMA_CFG1_SRCINC_0 | - DMA_CFG1_DESTINC_0 | - DMA_CFG1_PRIORITY_NORMAL); - - ao_dma_start(ao_ee_dma_in_id); - ao_dma_start(ao_ee_dma_out_id); - ao_dma_trigger(ao_ee_dma_out_id); - __critical while (!ao_ee_dma_in_done) - ao_sleep(&ao_ee_dma_in_done); -} #define EE_BLOCK 256 @@ -143,7 +60,7 @@ ao_ee_write_enable(void) { ao_ee_cs_low(); ao_ee_instruction.instruction = EE_WREN; - ao_ee_send(&ao_ee_instruction, 1); + ao_spi_send(&ao_ee_instruction, 1); ao_ee_cs_high(); } @@ -152,8 +69,8 @@ ao_ee_rdsr(void) { ao_ee_cs_low(); ao_ee_instruction.instruction = EE_RDSR; - ao_ee_send(&ao_ee_instruction, 1); - ao_ee_recv(&ao_ee_instruction, 1); + ao_spi_send(&ao_ee_instruction, 1); + ao_spi_recv(&ao_ee_instruction, 1); ao_ee_cs_high(); return ao_ee_instruction.instruction; } @@ -164,7 +81,7 @@ ao_ee_wrsr(uint8_t status) ao_ee_cs_low(); ao_ee_instruction.instruction = EE_WRSR; ao_ee_instruction.address[0] = status; - ao_ee_send(&ao_ee_instruction, 2); + ao_spi_send(&ao_ee_instruction, 2); ao_ee_cs_high(); } @@ -191,8 +108,8 @@ ao_ee_write_block(void) ao_ee_instruction.address[0] = ao_ee_block >> 8; ao_ee_instruction.address[1] = ao_ee_block; ao_ee_instruction.address[2] = 0; - ao_ee_send(&ao_ee_instruction, 4); - ao_ee_send(ao_ee_data, EE_BLOCK); + ao_spi_send(&ao_ee_instruction, 4); + ao_spi_send(ao_ee_data, EE_BLOCK); ao_ee_cs_high(); for (;;) { uint8_t status = ao_ee_rdsr(); @@ -210,8 +127,8 @@ ao_ee_read_block(void) ao_ee_instruction.address[0] = ao_ee_block >> 8; ao_ee_instruction.address[1] = ao_ee_block; ao_ee_instruction.address[2] = 0; - ao_ee_send(&ao_ee_instruction, 4); - ao_ee_recv(ao_ee_data, EE_BLOCK); + ao_spi_send(&ao_ee_instruction, 4); + ao_spi_recv(ao_ee_data, EE_BLOCK); ao_ee_cs_high(); } @@ -423,39 +340,6 @@ ao_ee_init(void) P1DIR |= (1 << EE_CS_INDEX); P1SEL &= ~(1 << EE_CS_INDEX); - /* Set up the USART pin assignment */ - PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2; - - /* Ensure that USART0 takes precidence over USART1 for pins that - * they share - */ - P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0; - - /* Make the SPI pins be controlled by the USART peripheral */ - P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3)); - - /* Set up OUT DMA */ - ao_ee_dma_out_id = ao_dma_alloc(&ao_ee_dma_out_done); - - /* Set up IN DMA */ - ao_ee_dma_in_id = ao_dma_alloc(&ao_ee_dma_in_done); - - /* Set up the USART. - * - * SPI master mode - */ - U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_MASTER); - - /* Set the baud rate and signal parameters - * - * The cc1111 is limited to a 24/8 MHz SPI clock, - * while the 25LC1024 is limited to 20MHz. So, - * use the 3MHz clock (BAUD_E 17, BAUD_M 0) - */ - U0BAUD = 0; - U0GCR = (UxGCR_CPOL_NEGATIVE | - UxGCR_CPHA_FIRST_EDGE | - UxGCR_ORDER_MSB | - (17 << UxGCR_BAUD_E_SHIFT)); + ao_spi_init(); ao_cmd_register(&ao_ee_cmds[0]); } diff --git a/src/ao_flash.c b/src/ao_flash.c index 638e51e0..c3f45ee3 100644 --- a/src/ao_flash.c +++ b/src/ao_flash.c @@ -18,22 +18,11 @@ #include "ao.h" #include "at45db161d.h" -/* - * Using SPI on USART 0, with P1_1 as the chip select - */ - #define FLASH_CS P1_1 #define FLASH_CS_INDEX 1 -__xdata uint8_t ao_flash_dma_in_done; -__xdata uint8_t ao_flash_dma_out_done; __xdata uint8_t ao_flash_mutex; -uint8_t ao_flash_dma_out_id; -uint8_t ao_flash_dma_in_id; - -static __xdata uint8_t ao_flash_const = 0xff; - #define ao_flash_delay() do { \ _asm nop _endasm; \ _asm nop _endasm; \ @@ -54,83 +43,6 @@ void ao_flash_cs_high(void) ao_flash_delay(); } -/* Send bytes over SPI. - * - * This sets up two DMA engines, one writing the data and another reading - * bytes coming back. We use the bytes coming back to tell when the transfer - * is complete, as the transmit register is double buffered and hence signals - * completion one byte before the transfer is actually complete - */ -static void -ao_flash_send(void __xdata *block, uint16_t len) -{ - ao_dma_set_transfer(ao_flash_dma_in_id, - &U0DBUFXADDR, - &ao_flash_const, - len, - DMA_CFG0_WORDSIZE_8 | - DMA_CFG0_TMODE_SINGLE | - DMA_CFG0_TRIGGER_URX0, - DMA_CFG1_SRCINC_0 | - DMA_CFG1_DESTINC_0 | - DMA_CFG1_PRIORITY_NORMAL); - - ao_dma_set_transfer(ao_flash_dma_out_id, - block, - &U0DBUFXADDR, - len, - DMA_CFG0_WORDSIZE_8 | - DMA_CFG0_TMODE_SINGLE | - DMA_CFG0_TRIGGER_UTX0, - DMA_CFG1_SRCINC_1 | - DMA_CFG1_DESTINC_0 | - DMA_CFG1_PRIORITY_NORMAL); - - ao_dma_start(ao_flash_dma_in_id); - ao_dma_start(ao_flash_dma_out_id); - ao_dma_trigger(ao_flash_dma_out_id); - __critical while (!ao_flash_dma_in_done) - ao_sleep(&ao_flash_dma_in_done); -} - -/* Receive bytes over SPI. - * - * This sets up tow DMA engines, one reading the data and another - * writing constant values to the SPI transmitter as that is what - * clocks the data coming in. - */ -static void -ao_flash_recv(void __xdata *block, uint16_t len) -{ - ao_dma_set_transfer(ao_flash_dma_in_id, - &U0DBUFXADDR, - block, - len, - DMA_CFG0_WORDSIZE_8 | - DMA_CFG0_TMODE_SINGLE | - DMA_CFG0_TRIGGER_URX0, - DMA_CFG1_SRCINC_0 | - DMA_CFG1_DESTINC_1 | - DMA_CFG1_PRIORITY_NORMAL); - - ao_dma_set_transfer(ao_flash_dma_out_id, - &ao_flash_const, - &U0DBUFXADDR, - len, - DMA_CFG0_WORDSIZE_8 | - DMA_CFG0_TMODE_SINGLE | - DMA_CFG0_TRIGGER_UTX0, - DMA_CFG1_SRCINC_0 | - DMA_CFG1_DESTINC_0 | - DMA_CFG1_PRIORITY_NORMAL); - - ao_dma_start(ao_flash_dma_in_id); - ao_dma_start(ao_flash_dma_out_id); - ao_dma_trigger(ao_flash_dma_out_id); - __critical while (!ao_flash_dma_in_done) - ao_sleep(&ao_flash_dma_in_done); -} - struct ao_flash_instruction { uint8_t instruction; uint8_t address[3]; @@ -144,7 +56,7 @@ ao_flash_set_pagesize_512(void) ao_flash_instruction.address[0] = FLASH_SET_512_BYTE_0; ao_flash_instruction.address[1] = FLASH_SET_512_BYTE_1; ao_flash_instruction.address[2] = FLASH_SET_512_BYTE_2; - ao_flash_send(&ao_flash_instruction, 4); + ao_spi_send(&ao_flash_instruction, 4); ao_flash_cs_high(); } @@ -154,8 +66,8 @@ ao_flash_read_status(void) { ao_flash_cs_low(); ao_flash_instruction.instruction = FLASH_READ_STATUS; - ao_flash_send(&ao_flash_instruction, 1); - ao_flash_recv(&ao_flash_instruction, 1); + ao_spi_send(&ao_flash_instruction, 1); + ao_spi_recv(&ao_flash_instruction, 1); ao_flash_cs_high(); return ao_flash_instruction.instruction; } @@ -268,8 +180,8 @@ ao_flash_write_block(void) ao_flash_instruction.address[0] = ao_flash_block >> (16 - ao_flash_block_shift); ao_flash_instruction.address[1] = ao_flash_block << (ao_flash_block_shift - 8); ao_flash_instruction.address[2] = 0; - ao_flash_send(&ao_flash_instruction, 4); - ao_flash_send(ao_flash_data, FLASH_BLOCK_SIZE); + ao_spi_send(&ao_flash_instruction, 4); + ao_spi_send(ao_flash_data, FLASH_BLOCK_SIZE); ao_flash_cs_high(); ao_flash_write_pending = 1; } @@ -286,8 +198,8 @@ ao_flash_read_block(void) ao_flash_instruction.address[0] = ao_flash_block >> (16 - ao_flash_block_shift); ao_flash_instruction.address[1] = ao_flash_block << (ao_flash_block_shift - 8); ao_flash_instruction.address[2] = 0; - ao_flash_send(&ao_flash_instruction, 4); - ao_flash_recv(ao_flash_data, FLASH_BLOCK_SIZE); + ao_spi_send(&ao_flash_instruction, 4); + ao_spi_recv(ao_flash_data, FLASH_BLOCK_SIZE); ao_flash_cs_high(); } @@ -544,39 +456,6 @@ ao_ee_init(void) P1DIR |= (1 << FLASH_CS_INDEX); P1SEL &= ~(1 << FLASH_CS_INDEX); - /* Set up the USART pin assignment */ - PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2; - - /* Ensure that USART0 takes precidence over USART1 for pins that - * they share - */ - P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0; - - /* Make the SPI pins be controlled by the USART peripheral */ - P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3)); - - /* Set up OUT DMA */ - ao_flash_dma_out_id = ao_dma_alloc(&ao_flash_dma_out_done); - - /* Set up IN DMA */ - ao_flash_dma_in_id = ao_dma_alloc(&ao_flash_dma_in_done); - - /* Set up the USART. - * - * SPI master mode - */ - U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_MASTER); - - /* Set the baud rate and signal parameters - * - * The cc1111 is limited to a 24/8 MHz SPI clock, - * while the at45db161d.h is limited to 20MHz. So, - * use the 3MHz clock (BAUD_E 17, BAUD_M 0) - */ - U0BAUD = 0; - U0GCR = (UxGCR_CPOL_NEGATIVE | - UxGCR_CPHA_FIRST_EDGE | - UxGCR_ORDER_MSB | - (17 << UxGCR_BAUD_E_SHIFT)); + ao_spi_init(); ao_cmd_register(&ao_flash_cmds[0]); } diff --git a/src/ao_m25.c b/src/ao_m25.c new file mode 100644 index 00000000..f0208a37 --- /dev/null +++ b/src/ao_m25.c @@ -0,0 +1,360 @@ +/* + * Copyright © 2010 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include "ao.h" + +/* + * Each flash chip is arranged in 64kB sectors; the + * chip cannot erase in units smaller than that. + * + * Writing happens in units of 256 byte pages and + * can only change bits from 1 to 0. So, you can rewrite + * the same contents, or append to an existing page easily enough + */ + +#define M25_WREN 0x06 /* Write Enable */ +#define M25_WRDI 0x04 /* Write Disable */ +#define M25_RDID 0x9f /* Read Identification */ +#define M25_RDSR 0x05 /* Read Status Register */ +#define M25_WRSR 0x01 /* Write Status Register */ +#define M25_READ 0x03 /* Read Data Bytes */ +#define M25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define M25_PP 0x02 /* Page Program */ +#define M25_SE 0xd8 /* Sector Erase */ +#define M25_BE 0xc7 /* Bulk Erase */ +#define M25_DP 0xb9 /* Deep Power-down */ + +/* RDID response */ +#define M25_MANUF_OFFSET 0 +#define M25_MEMORY_TYPE_OFFSET 1 +#define M25_CAPACITY_OFFSET 2 +#define M25_UID_OFFSET 3 +#define M25_CFI_OFFSET 4 +#define M25_RDID_LEN 4 /* that's all we need */ + +#define M25_CAPACITY_128KB 0x11 +#define M25_CAPACITY_256KB 0x12 +#define M25_CAPACITY_512KB 0x13 +#define M25_CAPACITY_1MB 0x14 +#define M25_CAPACITY_2MB 0x15 + +/* + * Status register bits + */ + +#define M25_STATUS_SRWD (1 << 7) /* Status register write disable */ +#define M25_STATUS_BP_MASK (7 << 2) /* Block protect bits */ +#define M25_STATUS_BP_SHIFT (2) +#define M25_STATUS_WEL (1 << 1) /* Write enable latch */ +#define M25_STATUS_WIP (1 << 0) /* Write in progress */ + +/* + * On teleterra, the m25 chip select pins are + * wired on P0_0 through P0_3. + */ + +#define AO_M25_MAX_CHIPS 4 + +static uint8_t ao_m25_size[AO_M25_MAX_CHIPS]; /* number of sectors in each chip */ +static uint8_t ao_m25_pin[AO_M25_MAX_CHIPS]; /* chip select pin for each chip */ +static uint8_t ao_m25_numchips; /* number of chips detected */ +static uint8_t ao_m25_total; /* total sectors available */ +static uint8_t ao_m25_wip; /* write in progress */ + +static __xdata uint8_t ao_m25_mutex; + +/* + * This little array is abused to send and receive data. A particular + * caution -- the read and write addresses are written into the last + * three bytes of the array by ao_m25_set_page_address and then the + * first byte is used by ao_m25_wait_wip and ao_m25_write_enable, neither + * of which touch those last three bytes. + */ + +static __xdata uint8_t ao_m25_instruction[4]; + +#define AO_M25_SELECT(cs) (SPI_CS_PORT &= ~(cs)) +#define AO_M25_DESELECT(cs) (SPI_CS_PORT |= (cs)) +#define AO_M25_PAGE_TO_SECTOR(page) ((page) >> 8) +#define AO_M25_SECTOR_TO_PAGE(sector) (((uint16_t) (sector)) << 8) + +/* + * Block until the specified chip is done writing + */ +static void +ao_m25_wait_wip(uint8_t cs) +{ + if (ao_m25_wip & cs) { + AO_M25_SELECT(cs); + ao_m25_instruction[0] = M25_RDSR; + ao_spi_send(ao_m25_instruction, 1); + do { + ao_spi_recv(ao_m25_instruction, 1); + } while (ao_m25_instruction[0] & M25_STATUS_WIP); + AO_M25_DESELECT(cs); + ao_m25_wip &= ~cs; + } +} + +/* + * Set the write enable latch so that page program and sector + * erase commands will work. Also mark the chip as busy writing + * so that future operations will block until the WIP bit goes off + */ +static void +ao_m25_write_enable(uint8_t cs) +{ + AO_M25_SELECT(cs); + ao_m25_instruction[0] = M25_WREN; + ao_spi_send(&ao_m25_instruction, 1); + AO_M25_DESELECT(cs); + ao_m25_wip |= cs; +} + + +/* + * Returns the number of 64kB sectors + */ +static uint8_t +ao_m25_read_capacity(uint8_t cs) +{ + uint8_t capacity; + AO_M25_SELECT(cs); + ao_m25_instruction[0] = M25_RDID; + ao_spi_send(ao_m25_instruction, 1); + ao_spi_recv(ao_m25_instruction, M25_RDID_LEN); + AO_M25_DESELECT(cs); + + /* Check to see if the chip is present */ + if (ao_m25_instruction[0] == 0xff) + return 0; + capacity = ao_m25_instruction[M25_CAPACITY_OFFSET]; + + /* Sanity check capacity number */ + if (capacity < 0x11 || 0x1f < capacity) + return 0; + return 1 << (capacity - 0x10); +} + +static uint8_t +ao_m25_set_page_address(uint16_t page) +{ + uint8_t chip, size; + + for (chip = 0; chip < ao_m25_numchips; chip++) { + size = ao_m25_size[chip]; + if (AO_M25_PAGE_TO_SECTOR(page) < size) + break; + page -= AO_M25_SECTOR_TO_PAGE(size); + } + if (chip == ao_m25_numchips) + ao_panic(AO_PANIC_EE); + + chip = ao_m25_pin[chip]; + ao_m25_wait_wip(chip); + + ao_m25_instruction[1] = page >> 8; + ao_m25_instruction[2] = page; + ao_m25_instruction[3] = 0; + return chip; +} + +/* + * Erase the specified sector + */ +void +ao_flash_erase_sector(uint8_t sector) __reentrant +{ + uint8_t cs; + uint16_t page = AO_M25_SECTOR_TO_PAGE(sector); + + ao_mutex_get(&ao_m25_mutex); + + cs = ao_m25_set_page_address(page); + ao_m25_wait_wip(cs); + ao_m25_write_enable(cs); + + ao_m25_instruction[0] = M25_SE; + AO_M25_SELECT(cs); + ao_spi_send(ao_m25_instruction, 4); + AO_M25_DESELECT(cs); + ao_m25_wip |= cs; + + ao_mutex_put(&ao_m25_mutex); +} + +/* + * Write one page + */ +void +ao_flash_write_page(uint16_t page, uint8_t __xdata *d) __reentrant +{ + uint8_t cs; + + ao_mutex_get(&ao_m25_mutex); + + cs = ao_m25_set_page_address(page); + ao_m25_write_enable(cs); + + ao_m25_instruction[0] = M25_PP; + AO_M25_SELECT(cs); + ao_spi_send(ao_m25_instruction, 4); + ao_spi_send(d, 256); + AO_M25_DESELECT(cs); + + ao_mutex_put(&ao_m25_mutex); +} + +/* + * Read one page + */ +void +ao_flash_read_page(uint16_t page, __xdata uint8_t *d) __reentrant +{ + uint8_t cs; + + ao_mutex_get(&ao_m25_mutex); + + cs = ao_m25_set_page_address(page); + + /* No need to use the FAST_READ as we're running at only 8MHz */ + ao_m25_instruction[0] = M25_READ; + AO_M25_SELECT(cs); + ao_spi_send(ao_m25_instruction, 4); + ao_spi_recv(d, 256); + AO_M25_DESELECT(cs); + + ao_mutex_put(&ao_m25_mutex); +} + +static __xdata uint8_t ao_flash_block[256]; + +static void +ao_flash_dump(void) __reentrant +{ + uint8_t i; + + ao_cmd_hex(); + if (ao_cmd_status != ao_cmd_success) + return; + ao_flash_read_page(ao_cmd_lex_i, ao_flash_block); + i = 0; + do { + if ((i & 7) == 0) { + if (i) + putchar('\n'); + ao_cmd_put16((uint16_t) i); + } + putchar(' '); + ao_cmd_put8(ao_flash_block[i]); + ++i; + } while (i != 0); + putchar('\n'); +} + +static void +ao_flash_store(void) __reentrant +{ + uint16_t block; + uint8_t i; + uint16_t len; + uint8_t b; + + ao_cmd_hex(); + block = ao_cmd_lex_i; + ao_cmd_hex(); + i = ao_cmd_lex_i; + ao_cmd_hex(); + len = ao_cmd_lex_i; + if (ao_cmd_status != ao_cmd_success) + return; + ao_flash_read_page(block, ao_flash_block); + while (len--) { + ao_cmd_hex(); + if (ao_cmd_status != ao_cmd_success) + return; + b = ao_cmd_lex_i; + ao_flash_block[i] = ao_cmd_lex_i; + i++; + } + ao_flash_write_page(block, ao_flash_block); +} + +static void +ao_flash_info(void) __reentrant +{ + uint8_t chip, cs; + + printf ("Detected chips %d size %d\n", ao_m25_numchips, ao_m25_total); + for (chip = 0; chip < ao_m25_numchips; chip++) + printf ("Flash chip %d select %02x size %d manf %02x type %02x cap %02x uid %02x\n", + chip, ao_m25_pin[chip], ao_m25_size[chip]); + + printf ("Available chips:\n"); + for (cs = 1; cs != 0; cs <<= 1) { + if ((M25_CS_MASK & cs) == 0) + continue; + + ao_mutex_get(&ao_m25_mutex); + AO_M25_SELECT(cs); + ao_m25_instruction[0] = M25_RDID; + ao_spi_send(ao_m25_instruction, 1); + ao_spi_recv(ao_m25_instruction, M25_RDID_LEN); + AO_M25_DESELECT(cs); + + printf ("Select %02x manf %02x type %02x cap %02x uid %02x\n", + cs, + ao_m25_instruction[M25_MANUF_OFFSET], + ao_m25_instruction[M25_MEMORY_TYPE_OFFSET], + ao_m25_instruction[M25_CAPACITY_OFFSET], + ao_m25_instruction[M25_UID_OFFSET]); + ao_mutex_put(&ao_m25_mutex); + } +} + +__code struct ao_cmds ao_flash_cmds[] = { + { 'e', ao_flash_dump, "e Dump a block of EEPROM data" }, + { 'w', ao_flash_store, "w ... Write data to EEPROM" }, + { 'F', ao_flash_info, "F Display flash info" }, + { 0, ao_flash_store, NULL }, +}; + +void +ao_flash_init(void) +{ + uint8_t pin, size; + + /* Set up chip select wires */ + SPI_CS_PORT |= M25_CS_MASK; /* raise all CS pins */ + SPI_CS_DIR |= M25_CS_MASK; /* set CS pins as outputs */ + SPI_CS_SEL &= ~M25_CS_MASK; /* set CS pins as GPIO */ + ao_spi_init(); + + ao_m25_numchips = 0; + for (pin = 1; pin != 0; pin <<= 1) { + if (M25_CS_MASK & pin) { + size = ao_m25_read_capacity(pin); + if (size != 0) { + ao_m25_size[ao_m25_numchips] = size; + ao_m25_pin[ao_m25_numchips] = pin; + ao_m25_total += size; + ao_m25_numchips++; + } + } + } + ao_cmd_register(&ao_flash_cmds[0]); +} diff --git a/src/ao_pins.h b/src/ao_pins.h index 9849dfe4..8befd1fc 100644 --- a/src/ao_pins.h +++ b/src/ao_pins.h @@ -32,6 +32,9 @@ #define LEDS_AVAILABLE (AO_LED_RED) #define HAS_EXTERNAL_TEMP 0 #define AUDIO_STANDBY_ON_P2_4 0 + #define SPI_CS_ON_P1 1 + #define SPI_CS_ON_P0 0 + #define M25_CS_MASK 0x02 #endif #if defined(TELEDONGLE_V_0_2) @@ -47,6 +50,8 @@ #define AO_LED_GREEN 2 #define LEDS_AVAILABLE (AO_LED_RED|AO_LED_GREEN) #define AUDIO_STANDBY_ON_P2_4 0 + #define SPI_CS_ON_P1 1 + #define SPI_CS_ON_P0 0 #endif #if defined(TELEMETRUM_V_0_1) @@ -63,6 +68,8 @@ #define LEDS_AVAILABLE (AO_LED_RED|AO_LED_GREEN) #define HAS_EXTERNAL_TEMP 1 #define AUDIO_STANDBY_ON_P2_4 0 + #define SPI_CS_ON_P1 1 + #define SPI_CS_ON_P0 0 #endif #if defined(TELEDONGLE_V_0_1) @@ -78,6 +85,8 @@ #define AO_LED_GREEN 1 #define LEDS_AVAILABLE (AO_LED_RED|AO_LED_GREEN) #define AUDIO_STANDBY_ON_P2_4 0 + #define SPI_CS_ON_P1 1 + #define SPI_CS_ON_P0 0 #endif #if defined(TELETERRA_V_0_1) @@ -93,6 +102,9 @@ #define AO_LED_GREEN 2 #define LEDS_AVAILABLE (AO_LED_RED|AO_LED_GREEN) #define AUDIO_STANDBY_ON_P2_4 1 + #define SPI_CS_ON_P1 0 + #define SPI_CS_ON_P0 1 + #define M25_CS_MASK 0x0f #endif #if defined(TIDONGLE) @@ -107,6 +119,8 @@ #define AO_LED_RED 2 #define LEDS_AVAILABLE (AO_LED_RED) #define AUDIO_STANDBY_ON_P2_4 0 + #define SPI_CS_ON_P1 1 + #define SPI_CS_ON_P0 0 #endif #if DBG_ON_P1 @@ -145,6 +159,18 @@ #endif /* DBG_ON_P0 */ +#if SPI_CS_ON_P1 + #define SPI_CS_PORT P1 + #define SPI_CS_SEL P1SEL + #define SPI_CS_DIR P1DIR +#endif + +#if SPI_CS_ON_P0 + #define SPI_CS_PORT P0 + #define SPI_CS_SEL P0SEL + #define SPI_CS_DIR P0DIR +#endif + #ifndef HAS_SERIAL_1 #error Please define HAS_SERIAL_1 #endif diff --git a/src/ao_spi.c b/src/ao_spi.c new file mode 100644 index 00000000..bd52a0d4 --- /dev/null +++ b/src/ao_spi.c @@ -0,0 +1,157 @@ +/* + * Copyright © 2010 Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include "ao.h" + +__xdata uint8_t ao_spi_mutex; +__xdata uint8_t ao_spi_dma_in_done; +__xdata uint8_t ao_spi_dma_out_done; + +uint8_t ao_spi_dma_out_id; +uint8_t ao_spi_dma_in_id; + +static __xdata uint8_t ao_spi_const = 0xff; + +/* Send bytes over SPI. + * + * This sets up two DMA engines, one writing the data and another reading + * bytes coming back. We use the bytes coming back to tell when the transfer + * is complete, as the transmit register is double buffered and hence signals + * completion one byte before the transfer is actually complete + */ +void +ao_spi_send(void __xdata *block, uint16_t len) __reentrant +{ + ao_mutex_get(&ao_spi_mutex); + ao_dma_set_transfer(ao_spi_dma_in_id, + &U0DBUFXADDR, + &ao_spi_const, + len, + DMA_CFG0_WORDSIZE_8 | + DMA_CFG0_TMODE_SINGLE | + DMA_CFG0_TRIGGER_URX0, + DMA_CFG1_SRCINC_0 | + DMA_CFG1_DESTINC_0 | + DMA_CFG1_PRIORITY_NORMAL); + + ao_dma_set_transfer(ao_spi_dma_out_id, + block, + &U0DBUFXADDR, + len, + DMA_CFG0_WORDSIZE_8 | + DMA_CFG0_TMODE_SINGLE | + DMA_CFG0_TRIGGER_UTX0, + DMA_CFG1_SRCINC_1 | + DMA_CFG1_DESTINC_0 | + DMA_CFG1_PRIORITY_NORMAL); + + ao_dma_start(ao_spi_dma_in_id); + ao_dma_start(ao_spi_dma_out_id); + ao_dma_trigger(ao_spi_dma_out_id); + __critical while (!ao_spi_dma_in_done) + ao_sleep(&ao_spi_dma_in_done); + ao_mutex_put(&ao_spi_mutex); +} + +/* Receive bytes over SPI. + * + * This sets up tow DMA engines, one reading the data and another + * writing constant values to the SPI transmitter as that is what + * clocks the data coming in. + */ +void +ao_spi_recv(void __xdata *block, uint16_t len) __reentrant +{ + ao_mutex_get(&ao_spi_mutex); + ao_dma_set_transfer(ao_spi_dma_in_id, + &U0DBUFXADDR, + block, + len, + DMA_CFG0_WORDSIZE_8 | + DMA_CFG0_TMODE_SINGLE | + DMA_CFG0_TRIGGER_URX0, + DMA_CFG1_SRCINC_0 | + DMA_CFG1_DESTINC_1 | + DMA_CFG1_PRIORITY_NORMAL); + + ao_dma_set_transfer(ao_spi_dma_out_id, + &ao_spi_const, + &U0DBUFXADDR, + len, + DMA_CFG0_WORDSIZE_8 | + DMA_CFG0_TMODE_SINGLE | + DMA_CFG0_TRIGGER_UTX0, + DMA_CFG1_SRCINC_0 | + DMA_CFG1_DESTINC_0 | + DMA_CFG1_PRIORITY_NORMAL); + + ao_dma_start(ao_spi_dma_in_id); + ao_dma_start(ao_spi_dma_out_id); + ao_dma_trigger(ao_spi_dma_out_id); + __critical while (!ao_spi_dma_in_done) + ao_sleep(&ao_spi_dma_in_done); + ao_mutex_put(&ao_spi_mutex); +} + +/* + * Initialize USART0 for SPI using config alt 2 + * + * MO P1_5 + * MI P1_4 + * CLK P1_3 + * + * Chip select is the responsibility of the caller + */ + +void +ao_spi_init(void) +{ + /* Set up the USART pin assignment */ + PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2; + + /* Ensure that USART0 takes precidence over USART1 for pins that + * they share + */ + P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0; + + /* Make the SPI pins be controlled by the USART peripheral */ + P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3)); + + /* Set up OUT DMA */ + ao_spi_dma_out_id = ao_dma_alloc(&ao_spi_dma_out_done); + + /* Set up IN DMA */ + ao_spi_dma_in_id = ao_dma_alloc(&ao_spi_dma_in_done); + + /* Set up the USART. + * + * SPI master mode + */ + U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_MASTER); + + /* Set the baud rate and signal parameters + * + * The cc1111 is limited to a 24/8 MHz SPI clock. + * Every peripheral I've ever seen goes faster than that, + * so set the clock to 3MHz (BAUD_E 17, BAUD_M 0) + */ + U0BAUD = 0; + U0GCR = (UxGCR_CPOL_NEGATIVE | + UxGCR_CPHA_FIRST_EDGE | + UxGCR_ORDER_MSB | + (17 << UxGCR_BAUD_E_SHIFT)); +} diff --git a/src/ao_teleterra.c b/src/ao_teleterra.c index c697b5df..a1c8bef6 100644 --- a/src/ao_teleterra.c +++ b/src/ao_teleterra.c @@ -27,6 +27,8 @@ main(void) ao_led_init(AO_LED_RED|AO_LED_GREEN); ao_led_on(AO_LED_RED); ao_timer_init(); + ao_spi_init(); + ao_flash_init(); ao_audio_init(); ao_cmd_init(); ao_usb_init(); diff --git a/src/telemetrum-v0.1-sirf/Makefile.defs b/src/telemetrum-v0.1-sirf/Makefile.defs index a7310fbc..ac8dcdb9 100644 --- a/src/telemetrum-v0.1-sirf/Makefile.defs +++ b/src/telemetrum-v0.1-sirf/Makefile.defs @@ -2,6 +2,7 @@ PROG = telemetrum-v0.1-sirf-$(VERSION).ihx SRC = \ $(TM_BASE_SRC) \ + $(SPI_DRIVER_SRC) \ $(EE_DRIVER_SRC) \ $(SIRF_DRIVER_SRC) \ $(DBG_SRC) diff --git a/src/telemetrum-v0.1-sky/Makefile.defs b/src/telemetrum-v0.1-sky/Makefile.defs index 000287ba..e032d1eb 100644 --- a/src/telemetrum-v0.1-sky/Makefile.defs +++ b/src/telemetrum-v0.1-sky/Makefile.defs @@ -2,6 +2,7 @@ PROG = telemetrum-v0.1-sky-$(VERSION).ihx SRC = \ $(TM_BASE_SRC) \ + $(SPI_DRIVER_SRC) \ $(EE_DRIVER_SRC) \ $(SKY_DRIVER_SRC) \ $(DBG_SRC) diff --git a/src/telemetrum-v1.0/Makefile.defs b/src/telemetrum-v1.0/Makefile.defs index 010578df..a60a501a 100644 --- a/src/telemetrum-v1.0/Makefile.defs +++ b/src/telemetrum-v1.0/Makefile.defs @@ -2,6 +2,7 @@ PROG = telemetrum-v1.0-$(VERSION).ihx SRC = \ $(TM_BASE_SRC) \ + $(SPI_DRIVER_SRC) \ $(FLASH_DRIVER_SRC) \ $(SKY_DRIVER_SRC) \ $(DBG_SRC) diff --git a/src/teleterra-v0.1/Makefile.defs b/src/teleterra-v0.1/Makefile.defs index f347743e..4601c0b0 100644 --- a/src/teleterra-v0.1/Makefile.defs +++ b/src/teleterra-v0.1/Makefile.defs @@ -2,6 +2,7 @@ PROG = teleterra-v0.1-$(VERSION).ihx SRC = \ $(TT_SRC) \ + $(SPI_DRIVER_SRC) \ $(SKY_DRIVER_SRC) \ $(DBG_SRC)