From: drdani Date: Mon, 7 Feb 2000 07:47:30 +0000 (+0000) Subject: ucsim-0.2.37-pre3 into cvs X-Git-Url: https://git.gag.com/?a=commitdiff_plain;h=1e5d63db2c3471fc6c0f30ee9a0a90da0f89f7a2;p=fw%2Fsdcc ucsim-0.2.37-pre3 into cvs git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@76 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- diff --git a/sim/ucsim/avr.src/(c).1 b/sim/ucsim/avr.src/(c).1 new file mode 100644 index 00000000..d673f9fd --- /dev/null +++ b/sim/ucsim/avr.src/(c).1 @@ -0,0 +1,25 @@ +/* + * Simulator of microcontrollers (@@F@@) + * + * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ diff --git a/sim/ucsim/avr.src/Makefile.in b/sim/ucsim/avr.src/Makefile.in new file mode 100644 index 00000000..775edcaa --- /dev/null +++ b/sim/ucsim/avr.src/Makefile.in @@ -0,0 +1,125 @@ +# +# uCsim avr.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = @CXX@ +CPP = @CPP@ +CXXCPP = @CXXCPP@ +RANLIB = @RANLIB@ +INSTALL = @INSTALL@ + +PRJDIR = .. + +DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +CPPFLAGS = @CPPFLAGS@ -I. -I$(PRJDIR) \ + -I$(PRJDIR)/cmd.src -I$(PRJDIR)/sim.src +CFLAGS = @CFLAGS@ -Wall +CXXFLAGS = @CXXFLAGS@ -Wall +M_OR_MM = @M_OR_MM@ + +LIBS = @LIBS@ -L$(PRJDIR) -lsim -lcmd -lutil + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +includedir = @includedir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +srcdir = @srcdir@ + +OBJECTS = savr.o glob.o \ + simavr.o avr.o port.o \ + inst.o bit_inst.o jump_inst.o move_inst.o logic_inst.o \ + arith_inst.o + +AVRASM = tavrasm +TEST_OBJ = test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \ + test_arith.hex + + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs avr.src tests + +tests: $(TEST_OBJ) + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) -s savr $(bindir) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(bindir)/savr + + +# Performing self-test +# -------------------- +check: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(bindir) || $(INSTALL) -d $(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: *.cc *.h + $(CXXCPP) $(CPPFLAGS) $(M_OR_MM) *.cc >Makefile.dep + +include Makefile.dep +include clean.mk + +#parser.cc: parser.y + +#plex.cc: plex.l + +# My rules +# -------- +.SUFFIXES: .asm .hex + +avr.src: savr + +savr: $(OBJECTS) $(PRJDIR)/*.a + $(CXX) $(CXXFLAGS) -o savr $(OBJECTS) $(LIBS) + +otherlibs: + cd $(PRJDIR)/cmd.src && $(MAKE) all + cd $(PRJDIR)/sim.src && $(MAKE) all + +.cc.o: + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@ + +.asm.hex: + $(AVRASM) -l $< -o $@ -e $<.lst + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(PRJDIR)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" PRJDIR="$(PRJDIR)" freshconf;\ + fi + +# End of avr.src/Makefile.in diff --git a/sim/ucsim/avr.src/arith_cl.h b/sim/ucsim/avr.src/arith_cl.h new file mode 100644 index 00000000..24bc86ee --- /dev/null +++ b/sim/ucsim/avr.src/arith_cl.h @@ -0,0 +1,27 @@ +/* avr.src/arith_cl.h */ + + virtual int cpi_Rd_K(t_mem code); + virtual int sbci_Rd_K(t_mem code); + virtual int subi_Rd_K(t_mem code); + virtual int muls_Rd_Rr(t_mem code); + virtual int mulsu_Rd_Rr(t_mem code); + virtual int fmul_Rd_Rr(t_mem code); + virtual int fmuls_Rd_Rr(t_mem code); + virtual int fmulsu_Rd_Rr(t_mem code); + virtual int cpc_Rd_Rr(t_mem code); + virtual int sbc_Rd_Rr(t_mem code); + virtual int add_Rd_Rr(t_mem code); + virtual int cp_Rd_Rr(t_mem code); + virtual int sub_Rd_Rr(t_mem code); + virtual int adc_Rd_Rr(t_mem code); + virtual int com_Rd(t_mem code); + virtual int neg_Rd(t_mem code); + virtual int inc_Rd(t_mem code); + virtual int asr_Rd(t_mem code); + virtual int lsr_Rd(t_mem code); + virtual int ror_Rd(t_mem code); + virtual int dec_Rd(t_mem code); + virtual int mul_Rd_Rr(t_mem code); + virtual int adiw_Rdl_K(t_mem code); + +/* End of avr.src/arith_cl.h */ diff --git a/sim/ucsim/avr.src/arith_inst.cc b/sim/ucsim/avr.src/arith_inst.cc new file mode 100644 index 00000000..11f7e168 --- /dev/null +++ b/sim/ucsim/avr.src/arith_inst.cc @@ -0,0 +1,364 @@ +/* + * Simulator of microcontrollers (arith_inst.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "avrcl.h" +#include "regsavr.h" + + +int +cl_avr::cpi_Rd_K(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::sbci_Rd_K(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::subi_Rd_K(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::muls_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::mulsu_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::fmul_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::fmuls_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::fmulsu_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::cpc_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::sbc_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +/* + * Add without Carry + * ADD Rd,Rr 0<=d<=31, 0<=r<=31 + * 0000 11rd dddd rrrr + *____________________________________________________________________________ + */ + +int +cl_avr::add_Rd_Rr(t_mem code) +{ + t_addr r, d; + t_mem R, D, result, res; + + d= (code&0x1f0)>>4; + r= ((code&0x200)>>5)|(code&0xf); + R= ram->read(r); + D= ram->read(d); + result= D+R; + res= result & 0xff; + ram->write(d, &res); + + t_mem sreg= ram->get(SREG); + if (!res) + sreg|= BIT_Z; + else + sreg&= ~BIT_Z; + if (((D&R&~res)&0x80) || + ((~D&~R&res)&0x80)) + sreg|= (BIT_V|BIT_S); + else + sreg&= ~(BIT_V|BIT_S); + if (res & 0x80) + { + sreg|= BIT_N; + sreg^= BIT_S; + } + else + sreg&= ~BIT_N; + if (result & ~0xff) + sreg|= BIT_C; + else + sreg&= ~BIT_C; + if ((R&0xf) + (D&0xf) > 15) + sreg|= BIT_H; + else + sreg&= ~BIT_H; + ram->set(SREG, sreg); + + return(resGO); +} + + +int +cl_avr::cp_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::sub_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +/* + * Add with Carry + * ADC Rd,Rr 0<=d<=31, 0<=r<=31 + * 0001 11rd dddd rrrr + *____________________________________________________________________________ + */ + +int +cl_avr::adc_Rd_Rr(t_mem code) +{ + t_addr r, d; + t_mem R, D, result, res; + + d= (code&0x1f0)>>4; + r= ((code&0x200)>>5)|(code&0xf); + R= ram->read(r); + D= ram->read(d); + t_mem sreg= ram->get(SREG); + result= D+R+((sreg&BIT_C)?1:0); + res= result & 0xff; + ram->write(d, &res); + + if (!res) + sreg|= BIT_Z; + else + sreg&= ~BIT_Z; + if (((D&R&~res)&0x80) || + ((~D&~R&res)&0x80)) + sreg|= (BIT_V|BIT_S); + else + sreg&= ~(BIT_V|BIT_S); + if (res & 0x80) + { + sreg|= BIT_N; + sreg^= BIT_S; + } + else + sreg&= ~BIT_N; + if (result & ~0xff) + sreg|= BIT_C; + else + sreg&= ~BIT_C; + if ((R&0xf) + (D&0xf) > 15) + sreg|= BIT_H; + else + sreg&= ~BIT_H; + ram->set(SREG, sreg); + + return(resGO); +} + + +int +cl_avr::com_Rd(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::neg_Rd(t_mem code) +{ + return(resGO); +} + + +/* + * Increment + * INC Rd 0<=d<=31 + * 1001 010d dddd 0011 + *____________________________________________________________________________ + */ + +int +cl_avr::inc_Rd(t_mem code) +{ + t_addr d; + + d= (code&0x1f0)>>4; + t_mem data= ram->read(d)+1; + ram->write(d, &data); + + t_mem sreg= ram->get(SREG); + data= data&0xff; + if (data & 0x80) + { + sreg|= (BIT_N); + if (data == 0x80) + { + sreg|= BIT_V; + sreg&= ~BIT_S; + } + else + { + sreg&= ~BIT_V; + sreg|= BIT_S; + } + sreg&= ~BIT_Z; + } + else + { + sreg&= ~(BIT_N|BIT_V|BIT_S); + if (!data) + sreg|= BIT_Z; + else + sreg&= ~BIT_Z; + } + ram->set(SREG, sreg); + return(resGO); +} + + +int +cl_avr::asr_Rd(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::lsr_Rd(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::ror_Rd(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::dec_Rd(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::mul_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +/* + * Add Immediate to Word + * ADIW Rdl,K dl={24,26,28,30}, 0<=K<=63 + * 1001 0110 KK dd KKKK + *____________________________________________________________________________ + */ + +int +cl_avr::adiw_Rdl_K(t_mem code) +{ + t_addr dl; + t_mem D, K, result, res; + + dl= 24+(2*((code&0x30)>>4)); + K= ((code&0xc0)>>2)|(code&0xf); + D= ram->read(dl+1)*256 + ram->read(dl); + result= D+K; + res= result & 0xffff; + t_mem resl= result&0xff, resh= (result>>8)&0xff; + ram->write(dl+1, &resh); + ram->write(dl, &resl); + + t_mem sreg= ram->get(SREG); + if (!res) + sreg|= BIT_Z; + else + sreg&= ~BIT_Z; + if (D&res&0x8000) + sreg|= (BIT_V|BIT_S); + else + sreg&= ~(BIT_V|BIT_S); + if (res & 0x8000) + { + sreg|= BIT_N; + sreg^= BIT_S; + } + else + sreg&= ~BIT_N; + if ((~res)&D&0x8000) + sreg|= BIT_C; + else + sreg&= ~BIT_C; + ram->set(SREG, sreg); + tick(1); + + return(resGO); +} + + +/* End of avr.src/arith_inst.cc */ diff --git a/sim/ucsim/avr.src/avr.cc b/sim/ucsim/avr.src/avr.cc new file mode 100644 index 00000000..950bd824 --- /dev/null +++ b/sim/ucsim/avr.src/avr.cc @@ -0,0 +1,595 @@ +/* + * Simulator of microcontrollers (avr.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include +#include +#include "i_string.h" + +// prj +#include "pobjcl.h" + +// sim +#include "simcl.h" + +// local +#include "portcl.h" +#include "avrcl.h" +#include "glob.h" +#include "regsavr.h" + + +/* + * Base type of AVR microcontrollers + */ + +cl_avr::cl_avr(class cl_sim *asim): + cl_uc(asim) +{ + type= CPU_AVR; +} + +int +cl_avr::init(void) +{ + cl_uc::init(); /* Memories now exist */ + ram= mem(MEM_IRAM); + rom= mem(MEM_ROM); + return(0); +} + +char * +cl_avr::id_string(void) +{ + return("unspecified AVR"); +} + + +/* + * Making elements of the controller + */ + +t_addr +cl_avr::get_mem_size(enum mem_class type) +{ + switch(type) + { + case MEM_ROM: return(8*1024); + case MEM_IRAM: return(0x10000); + default: return(0); + } + return(cl_uc::get_mem_size(type)); +} + +int +cl_avr::get_mem_width(enum mem_class type) +{ + if (type == MEM_ROM) + return(16); + return(cl_uc::get_mem_width(type)); +} + +void +cl_avr::mk_hw_elements(void) +{ + class cl_base *o; + /* t_uc::mk_hw() does nothing */ + hws->add(o= new cl_port(this)); + o->init(); +} + + +/* + * Help command interpreter + */ + +struct dis_entry * +cl_avr::dis_tbl(void) +{ + return(disass_avr); +} + +struct name_entry * +cl_avr::sfr_tbl(void) +{ + return(sfr_tabl); +} + +struct name_entry * +cl_avr::bit_tbl(void) +{ + //FIXME + return(0); +} + +char * +cl_avr::disass(uint addr, char *sep) +{ + char work[256], temp[20]; + char *buf, *p, *b, *t; + uint code, data= 0; + int i; + + p= work; + + code= get_mem(MEM_ROM, addr); + i= 0; + while ((code & dis_tbl()[i].mask) != dis_tbl()[i].code && + dis_tbl()[i].mnemonic) + i++; + if (dis_tbl()[i].mnemonic == NULL) + { + buf= (char*)malloc(30); + strcpy(buf, "UNKNOWN/INVALID"); + return(buf); + } + b= dis_tbl()[i].mnemonic; + + while (*b) + { + if (*b == '%') + { + b++; + switch (*(b++)) + { + case 'd': // Rd .... ...d dddd .... 0<=d<=31 + if (!get_name(data= (code&0x01f0)>>4, sfr_tbl(), temp)) + sprintf(temp, "r%d", data); + break; + case 'D': // Rd .... .... dddd .... 16<=d<=31 + if (!get_name(data= 16+((code&0xf0)>>4), sfr_tbl(), temp)) + sprintf(temp, "r%d", data); + break; + case 'K': // K .... KKKK .... KKKK 0<=K<=255 + sprintf(temp, "%d", ((code&0xf00)>>4)|(code&0xf)); + break; + case 'r': // Rr .... ..r. .... rrrr 0<=r<=31 + if (!get_name(data= ((code&0x0200)>>5)|(code&0x000f), + sfr_tbl(), temp)) + sprintf(temp, "r%d", data); + break; + case '2': // Rdl .... .... ..dd .... dl= {24,26,28,30} + if (!get_name(data= 24+(2*((code&0x0030)>>4)), + sfr_tbl(), temp)) + sprintf(temp, "r%d", data); + break; + case '6': // K .... .... KK.. KKKK 0<=K<=63 + sprintf(temp, "%d", ((code&0xc0)>>2)|(code&0xf)); + break; + case 's': // s .... .... .sss .... 0<=s<=7 + sprintf(temp, "%d", (code&0x70)>>4); + break; + case 'b': // b .... .... .... .bbb 0<=b<=7 + sprintf(temp, "%d", code&0x7); + break; + case 'k': // k .... ..kk kkkk k... -64<=k<=+63 + { + int k= (code&0x3f8)>>3; + if (code&0x200) + k|= -128; + sprintf(temp, "0x%06x", k+1+(signed int)addr); + break; + } + case 'A': // k .... ...k kkkk ...k 0<=k<=64K + // kkkk kkkk kkkk kkkk 0<=k<=4M + sprintf(temp, "0x%06x", + (((code&0x1f0)>>3)|(code&1))*0x10000+ + (uint)get_mem(MEM_ROM, addr+1)); + break; + case 'P': // P .... .... pppp p... 0<=P<=31 + data= (code&0xf8)>>3; + if (!get_name(data+0x20, sfr_tbl(), temp)) + sprintf(temp, "%d", data); + break; + case 'p': // P .... .PP. .... PPPP 0<=P<=63 + data= ((code&0x600)>>5)|(code&0xf); + if (!get_name(data+0x20, sfr_tbl(), temp)) + sprintf(temp, "%d", data); + break; + case 'q': // q ..q. qq.. .... .qqq 0<=q<=63 + sprintf(temp, "%d", + ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&7)); + break; + case 'R': // k SRAM address on second word 0<=k<=65535 + sprintf(temp, "0x%06x", (uint)get_mem(MEM_ROM, addr+1)); + break; + case 'a': // k .... kkkk kkkk kkkk -2k<=k<=2k + { + int k= code&0xfff; + if (code&0x800) + k|= -4096; + sprintf(temp, "0x%06lx", + (k+1+(signed int)addr) % rom->size); + break; + } + default: + strcpy(temp, "?"); + break; + } + t= temp; + while (*t) + *(p++)= *(t++); + } + else + *(p++)= *(b++); + } + *p= '\0'; + + p= strchr(work, ' '); + if (!p) + { + buf= strdup(work); + return(buf); + } + if (sep == NULL) + buf= (char *)malloc(6+strlen(p)+1); + else + buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1); + for (p= work, b= buf; *p != ' '; p++, b++) + *b= *p; + p++; + *b= '\0'; + if (sep == NULL) + { + while (strlen(buf) < 6) + strcat(buf, " "); + } + else + strcat(buf, sep); + strcat(buf, p); + return(buf); +} + +void +cl_avr::print_disass(uint addr, class cl_console *con) +{ + char *dis; + class cl_brk *b; + int i; + + b = fbrk_at(addr); + dis= disass(addr, NULL); + if (b) + con->printf("%c", (b->perm == brkFIX)?'F':'D'); + else + con->printf(" "); + con->printf("%c %06x %04x", + inst_at(addr)?' ':'*', + addr, get_mem(MEM_ROM, addr)); + for (i= 1; i < inst_length(get_mem(MEM_ROM, addr)); i++) + con->printf(" %04x", get_mem(MEM_ROM, addr+i)); + while (i < 2) + { + con->printf(" "); + i++; + } + con->printf(" %s\n", dis); + free(dis); +} + +void +cl_avr::print_regs(class cl_console *con) +{ + uchar data, sreg= ram->get(SREG); + uint x, y, z; + + ram->dump(0, 31, 16, con); + + con->printf("ITHSVNZC SREG= 0x%02x %3d %c\n", + sreg, sreg, isprint(sreg)?sreg:'.'); + con->printf("%c%c%c%c%c%c%c%c ", + (sreg&BIT_I)?'1':'0', + (sreg&BIT_T)?'1':'0', + (sreg&BIT_H)?'1':'0', + (sreg&BIT_S)?'1':'0', + (sreg&BIT_V)?'1':'0', + (sreg&BIT_N)?'1':'0', + (sreg&BIT_Z)?'1':'0', + (sreg&BIT_C)?'1':'0'); + con->printf("SP = 0x%06x\n", + ram->get(SPH)*256+ram->get(SPL)); + + x= ram->get(XH)*256 + ram->get(XL); + data= ram->get(x); + con->printf("X= 0x%04x [X]= 0x%02x %3d %c ", x, + data, data, isprint(data)?data:'.'); + y= ram->get(YH)*256 + ram->get(YL); + data= ram->get(y); + con->printf("Y= 0x%04x [Y]= 0x%02x %3d %c ", y, + data, data, isprint(data)?data:'.'); + z= ram->get(ZH)*256 + ram->get(ZL); + data= ram->get(z); + con->printf("Z= 0x%04x [Z]= 0x%02x %3d %c\n", z, + data, data, isprint(data)?data:'.'); + + print_disass(PC, con); +} + + +/* + * Execution + */ + +int +cl_avr::exec_inst(void) +{ + t_mem code; + + if (fetch(&code)) + return(resBREAKPOINT); + tick(1); + switch (code) + { + case 0x9419: + return(eijmp(code)); + case 0x9519: + return(eicall(code)); + case 0x9508: case 0x9528: case 0x9548: case 0x9568: + return(ret(code)); + case 0x9518: case 0x9538: case 0x9558: case 0x9578: + return(reti(code)); + case 0x95c8: + return(lpm(code)); + case 0x95d8: + return(elpm(code)); // in some devices equal to lpm + case 0x95e8: + return(spm(code)); + case 0x95f8: + return(espm(code)); + case 0x9408: + return(sec(code)); + case 0x9488: + return(clc(code)); + case 0x9428: + return(sen(code)); + case 0x94a8: + return(cln(code)); + case 0x9418: + return(sez(code)); + case 0x9498: + return(clz(code)); + case 0x9478: + return(sei(code)); + case 0x94f8: + return(cli(code)); + case 0x9448: + return(ses(code)); + case 0x94c8: + return(cls(code)); + case 0x9438: + return(sev(code)); + case 0x94b8: + return(clv(code)); + case 0x9468: + return(set(code)); + case 0x94e8: + return(clt(code)); + case 0x9458: + return(seh(code)); + case 0x94d8: + return(clh(code)); + case 0x0000: + return(nop(code)); + case 0x9588: case 0x9598: + return(sleep(code)); + case 0x95a8: case 0x95b8: + return(wdr(code)); + } + switch (code & 0xf000) + { + case 0x3000: return(cpi_Rd_K(code)); + case 0x4000: return(sbci_Rd_K(code)); + case 0x5000: return(subi_Rd_K(code)); + case 0x6000: return(ori_Rd_K(code)); + case 0x7000: return(andi_Rd_K(code)); + case 0xc000: return(rjmp_k(code)); + case 0xd000: return(rcall_k(code)); + case 0xe000: return(ldi_Rd_K(code)); + } + switch (code & 0xf000) + { + case 0x0000: + // 0x0... + switch (code & 0xfc00) + { + case 0x0000: + switch (code & 0xff00) + { + case 0x0100: return(movw_Rd_Rr(code)); + case 0x0200: return(muls_Rd_Rr(code)); + case 0x0300: + switch (code & 0xff88) + { + case 0x0300: return(mulsu_Rd_Rr(code)); + case 0x0308: return(fmul_Rd_Rr(code)); + case 0x0380: return(fmuls_Rd_Rr(code)); + case 0x0388: return(fmulsu_Rd_Rr(code)); + } + } + case 0x0400: return(cpc_Rd_Rr(code)); + case 0x0800: return(sbc_Rd_Rr(code)); + case 0x0c00: return(add_Rd_Rr(code)); + } + case 0x1000: + // 0x1... + switch (code & 0xfc00) + { + case 0x1000: return(cpse_Rd_Rr(code)); + case 0x1400: return(cp_Rd_Rr(code)); + case 0x1800: return(sub_Rd_Rr(code)); + case 0x1c00: return(adc_Rd_Rr(code)); + } + case 0x2000: + // 0x2... + switch (code & 0xfc00) + { + case 0x2000: return(and_Rd_Rr(code)); + case 0x2400: return(eor_Rd_Rr(code)); + case 0x2800: return(or_Rd_Rr(code)); + case 0x2c00: return(mov_Rd_Rr(code)); + } + case 0x8000: + // 0x8... + switch (code &0xf208) + { + case 0x8000: return(ldd_Rd_Z_q(code)); + case 0x8008: return(ldd_Rd_Y_q(code)); + case 0x8200: return(std_Z_q_Rr(code)); + case 0x8208: return(std_Y_q_Rr(code)); + } + case 0x9000: + // 0x9... + if ((code & 0xff0f) == 0x9509) + return(icall(code)); + if ((code & 0xff0f) == 0x9409) + return(ijmp(code)); + if ((code & 0xff00) == 0x9600) + return(adiw_Rdl_K(code)); + switch (code & 0xfc00) + { + case 0x9000: + switch (code & 0xfe0f) + { + case 0x9000: return(lds_Rd_k(code)); + case 0x9001: return(ld_Rd_Z$(code)); + case 0x9002: return(ld_Rd_$Z(code)); + case 0x9004: return(lpm_Rd_Z(code)); + case 0x9005: return(lpm_Rd_Z$(code)); + case 0x9006: return(elpm_Rd_Z(code)); + case 0x9007: return(elpm_Rd_Z$(code)); + case 0x9009: return(ld_Rd_Y$(code)); + case 0x900a: return(ld_Rd_$Y(code)); + case 0x900c: return(ld_Rd_X(code)); + case 0x900d: return(ld_Rd_X$(code)); + case 0x900e: return(ld_Rd_$X(code)); + case 0x900f: return(pop_Rd(code)); + case 0x9200: return(sts_k_Rr(code)); + case 0x9201: return(st_Z$_Rr(code)); + case 0x9202: return(st_$Z_Rr(code)); + case 0x9209: return(st_Y$_Rr(code)); + case 0x920a: return(st_$Y_Rr(code)); + case 0x920c: return(st_X_Rr(code)); + case 0x920d: return(st_X$_Rr(code)); + case 0x920e: return(st_$X_Rr(code)); + case 0x920f: return(push_Rr(code)); + } + case 0x9400: + switch (code & 0xfe0f) + { + case 0x9400: return(com_Rd(code)); + case 0x9401: return(neg_Rd(code)); + case 0x9402: return(swap_Rd(code)); + case 0x9403: return(inc_Rd(code)); + case 0x9405: return(asr_Rd(code)); + case 0x9406: return(lsr_Rd(code)); + case 0x9407: return(ror_Rd(code)); + case 0x940a: return(dec_Rd(code)); + case 0x940c: case 0x940d: return(jmp_k(code)); + case 0x940e: case 0x940f: return(call_k(code)); + } + case 0x9800: + switch (code & 0xff00) + { + case 0x9800: return(cbi_A_b(code)); + case 0x9900: return(sbic_P_b(code)); + case 0x9a00: return(sbi_A_b(code)); + case 0x9b00: return(sbis_P_b(code)); + } + case 0x9c00: return(mul_Rd_Rr(code)); + } + case 0xa000: + // 0xa... + switch (code &0xf208) + { + case 0xa000: return(ldd_Rd_Z_q(code)); + case 0xa008: return(ldd_Rd_Y_q(code)); + case 0xa200: return(std_Z_q_Rr(code)); + case 0xa208: return(std_Y_q_Rr(code)); + } + case 0xb000: + // 0xb... + switch (code & 0xf800) + { + case 0xb000: return(in_Rd_A(code)); + case 0xb800: return(out_A_Rr(code)); + } + case 0xe000: + // 0xe... + switch (code & 0xff0f) + { + case 0xef0f: return(ser_Rd(code)); + } + case 0xf000: + // 0xf... + switch (code & 0xfc00) + { + case 0xf000: return(brbs_s_k(code)); + case 0xf400: return(brbc_s_k(code)); + case 0xf800: case 0xfc00: + switch (code & 0xfe08) + { + case 0xf800: return(bld_Rd_b(code)); + case 0xfa00: return(bst_Rd_b(code)); + case 0xfc00: case 0xfc08: return(sbrc_Rr_b(code)); + case 0xfe00: case 0xfe08: return(sbrs_Rr_b(code)); + } + } + } + if (PC) + PC--; + else + PC= get_mem_size(MEM_ROM)-1; + //tick(-clock_per_cycle()); + sim->stop(resINV_INST); + return(resINV_INST); +} + + +/* + * Set Z, N, V, S bits of SREG after logic instructions and some others + */ + +void +cl_avr::set_zn0s(t_mem data) +{ + t_mem sreg= ram->get(SREG) & ~BIT_V; + data= data&0xff; + if (!data) + sreg|= BIT_Z; + else + sreg&= ~BIT_Z; + if (data & 0x80) + sreg|= (BIT_N|BIT_S); + else + sreg&= ~(BIT_N|BIT_S); + ram->set(SREG, sreg); +} + + +/* End of avr.src/avr.cc */ diff --git a/sim/ucsim/avr.src/avrcl.h b/sim/ucsim/avr.src/avrcl.h new file mode 100644 index 00000000..34fdc3ed --- /dev/null +++ b/sim/ucsim/avr.src/avrcl.h @@ -0,0 +1,73 @@ +/* + * Simulator of microcontrollers (avrcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef AVRCL_HEADER +#define AVRCL_HEADER + +#include "uccl.h" + + +/* + * Base type of AVR microcontrollers + */ + +class cl_avr: public cl_uc +{ +public: + cl_mem *ram; + cl_mem *rom; +public: + cl_avr(class cl_sim *asim); + virtual int init(void); + virtual char *id_string(void); + + virtual t_addr get_mem_size(enum mem_class type); + virtual int get_mem_width(enum mem_class type); + virtual void mk_hw_elements(void); + + virtual struct dis_entry *dis_tbl(void); + virtual struct name_entry *sfr_tbl(void); + virtual struct name_entry *bit_tbl(void); + virtual char *disass(uint addr, char *sep); + virtual void print_disass(uint addr, class cl_console *con); + virtual void print_regs(class cl_console *con); + + virtual int exec_inst(void); + + void set_zn0s(t_mem data); +#include "arith_cl.h" +#include "logic_cl.h" +#include "move_cl.h" +#include "bit_cl.h" +#include "jump_cl.h" +#include "instcl.h" +}; + + +#endif + +/* End of avr.src/avrcl.h */ diff --git a/sim/ucsim/avr.src/bit_cl.h b/sim/ucsim/avr.src/bit_cl.h new file mode 100644 index 00000000..65ab343a --- /dev/null +++ b/sim/ucsim/avr.src/bit_cl.h @@ -0,0 +1,24 @@ +/* avr.src/bit_cl.h */ + + virtual int sec(t_mem code); + virtual int clc(t_mem code); + virtual int sen(t_mem code); + virtual int cln(t_mem code); + virtual int sez(t_mem code); + virtual int clz(t_mem code); + virtual int sei(t_mem code); + virtual int cli(t_mem code); + virtual int ses(t_mem code); + virtual int cls(t_mem code); + virtual int sev(t_mem code); + virtual int clv(t_mem code); + virtual int set(t_mem code); + virtual int clt(t_mem code); + virtual int seh(t_mem code); + virtual int clh(t_mem code); + virtual int cbi_A_b(t_mem code); + virtual int sbi_A_b(t_mem code); + virtual int bld_Rd_b(t_mem code); + virtual int bst_Rd_b(t_mem code); + +/* End of avr.src/bit_cl.h */ diff --git a/sim/ucsim/avr.src/bit_inst.cc b/sim/ucsim/avr.src/bit_inst.cc new file mode 100644 index 00000000..1753e9d0 --- /dev/null +++ b/sim/ucsim/avr.src/bit_inst.cc @@ -0,0 +1,383 @@ +/* + * Simulator of microcontrollers (bit_inst.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +// local +#include "avrcl.h" +#include "regsavr.h" + + +/* + * Set Carry Flag + * SEC + * 1001 0100 0000 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::sec(t_mem code) +{ + t_mem d= BIT_C | ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Set Negative Flag + * SEN + * 1001 0100 0010 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::sen(t_mem code) +{ + t_mem d= BIT_N | ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Set Zero Flag + * SEZ + * 1001 0100 0001 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::sez(t_mem code) +{ + t_mem d= BIT_Z | ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Set Global Interrupt Flag + * SEI + * 1001 0100 0111 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::sei(t_mem code) +{ + t_mem d= BIT_I | ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Set Signed Flag + * SES + * 1001 0100 0100 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::ses(t_mem code) +{ + t_mem d= BIT_S | ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Set Overflow Flag + * SEV + * 1001 0100 0011 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::sev(t_mem code) +{ + t_mem d= BIT_V | ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Set T Flag + * SET + * 1001 0100 0110 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::set(t_mem code) +{ + t_mem d= BIT_T | ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Set Half Carry Flag + * SEH + * 1001 0100 0101 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::seh(t_mem code) +{ + t_mem d= BIT_H | ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Clear Carry Flag + * CLC + * 1001 0100 1000 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::clc(t_mem code) +{ + t_mem d= ~BIT_C & ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Clear Negative Flag + * CLN + * 1001 0100 1010 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::cln(t_mem code) +{ + t_mem d= ~BIT_N & ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Clear Zero Flag + * CLZ + * 1001 0100 1001 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::clz(t_mem code) +{ + t_mem d= ~BIT_Z & ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Global Interrupt Flag + * CLI + * 1001 0100 1111 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::cli(t_mem code) +{ + t_mem d= ~BIT_I & ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Clear Signed Flag + * CLS + * 1001 0100 1100 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::cls(t_mem code) +{ + t_mem d= ~BIT_S & ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Clear Overflow Flag + * CLV + * 1001 0100 1011 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::clv(t_mem code) +{ + t_mem d= ~BIT_V & ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Clear T Flag + * CLT + * 1001 0100 1110 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::clt(t_mem code) +{ + t_mem d= ~BIT_T & ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Clear Half Carry Flag + * CLH + * 1001 0100 1101 1000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::clh(t_mem code) +{ + t_mem d= ~BIT_H & ram->read(SREG); + ram->write(SREG, &d); + return(resGO); +} + + +/* + * Clear Bit in I/O Register + * CBI P,b 0<=P<=31 0<=b<=7 + * 1001 1000 pppp pbbb + *____________________________________________________________________________ + */ + +int +cl_avr::cbi_A_b(t_mem code) +{ + uint addr, mask; + t_mem d; + + addr= ((code&0xf8)>>3)+0x20; + mask= 1 << (code&7); + d= ~mask & ram->read(addr); + ram->write(addr, &d); + tick(1); + return(resGO); +} + + +/* + * Set Bit in I/O Register + * SBI P,b 0<=P<=31 0<=b<=7 + * 1001 1010 pppp pbbb + *____________________________________________________________________________ + */ + +int +cl_avr::sbi_A_b(t_mem code) +{ + uint addr, mask; + + addr= ((code&0xf8)>>3)+0x20; + mask= 1 << (code&7); + t_mem d= mask | ram->read(addr); + ram->write(addr, &d); + tick(1); + return(resGO); +} + + +/* + * Bit Load from the T Flag in SREG to a Bit in Register + * BLD Rd,b 0<=d<=31, 0<=b<=7 + * 1111 100d dddd 0bbb + *____________________________________________________________________________ + */ + +int +cl_avr::bld_Rd_b(t_mem code) +{ + t_addr d; + int b, mask; + t_mem data; + + d= (code&0x1f0)>>4; + b= code&7; + mask= 1<read(SREG) & BIT_T) + data= ram->read(d) | mask; + else + data= ram->read(d) & ~mask; + ram->write(d, &data); + return(resGO); +} + + +/* + * Bit Store from Bit in Register to T Flag in SREG + * BST Rd,b 0<=d<=31, 0<=b<=7 + * 1111 101d dddd Xbbb + *____________________________________________________________________________ + */ + +int +cl_avr::bst_Rd_b(t_mem code) +{ + t_addr d; + int b, mask; + + d= (code&0x1f0)>>4; + b= code&7; + mask= 1<read(d); + if (data & mask) + ram->set_bit1(SREG, BIT_T); + else + ram->set_bit0(SREG, BIT_T); + return(resGO); +} + + +/* End of avr.src/bit_inst.cc */ diff --git a/sim/ucsim/avr.src/clean.mk b/sim/ucsim/avr.src/clean.mk new file mode 100644 index 00000000..268e437b --- /dev/null +++ b/sim/ucsim/avr.src/clean.mk @@ -0,0 +1,28 @@ +# avr.src/clean.mk + +# Deleting all files created by building the program +# -------------------------------------------------- +clean: + rm -f *core *[%~] *.[oa] + rm -f .[a-z]*~ + rm -f savr + + +# Deleting all files created by configuring or building the program +# ----------------------------------------------------------------- +distclean: clean + rm -f config.cache config.log config.status + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean + +# End of avr.src/clean.mk diff --git a/sim/ucsim/avr.src/conf.mk b/sim/ucsim/avr.src/conf.mk new file mode 100644 index 00000000..7097e848 --- /dev/null +++ b/sim/ucsim/avr.src/conf.mk @@ -0,0 +1,11 @@ +# avr.src/conf.mk +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(PRJDIR)/configure.in + cd $(PRJDIR) && $(SHELL) ./config.status + +# End of avr.src/conf.mk diff --git a/sim/ucsim/avr.src/glob.cc b/sim/ucsim/avr.src/glob.cc new file mode 100644 index 00000000..84bb4c60 --- /dev/null +++ b/sim/ucsim/avr.src/glob.cc @@ -0,0 +1,221 @@ +/* + * Simulator of microcontrollers (glob.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include + +#include "stypes.h" + + +struct dis_entry disass_avr[]= { + { 0x0000, 0xffff, ' ', 1, "nop" }, + { 0x9488, 0xffff, ' ', 1, "clc" }, + { 0x94d8, 0xffff, ' ', 1, "clh" }, + { 0x94f8, 0xffff, ' ', 1, "cli" }, + { 0x94a8, 0xffff, ' ', 1, "cln" }, + { 0x94c8, 0xffff, ' ', 1, "cls" }, + { 0x94e8, 0xffff, ' ', 1, "clt" }, + { 0x94b8, 0xffff, ' ', 1, "clv" }, + { 0x9498, 0xffff, ' ', 1, "clz" }, + { 0x9408, 0xffff, ' ', 1, "sec" }, + { 0x9458, 0xffff, ' ', 1, "seh" }, + { 0x9478, 0xffff, ' ', 1, "sei" }, + { 0x9428, 0xffff, ' ', 1, "sen" }, + { 0x9448, 0xffff, ' ', 1, "ses" }, + { 0x9468, 0xffff, ' ', 1, "set" }, + { 0x9438, 0xffff, ' ', 1, "sev" }, + { 0x9418, 0xffff, ' ', 1, "sez" }, + { 0x1c00, 0xfc00, ' ', 1, "adc %d,%r" }, + { 0x0c00, 0xfc00, ' ', 1, "add %d,%r" }, + { 0x9600, 0xff00, ' ', 1, "adiw %2,%6" }, + { 0x2000, 0xfc00, ' ', 1, "and %d,%r" }, + { 0x7000, 0xf000, ' ', 1, "andi %D,%K" }, + { 0x9405, 0xfe0f, ' ', 1, "asr %d" }, + { 0x9488, 0xff8f, ' ', 1, "bclr %s" }, + { 0xf800, 0xfe08, ' ', 1, "bld %d,%b" }, + { 0xf400, 0xfc07, ' ', 1, "brcc %k" }, + { 0xf000, 0xfc07, ' ', 1, "brcs %k" }, + { 0xf001, 0xfc07, ' ', 1, "breq %k" }, + { 0xf404, 0xfc07, ' ', 1, "brge %k" }, + { 0xf405, 0xfc07, ' ', 1, "brhc %k" }, + { 0xf005, 0xfc07, ' ', 1, "brhs %k" }, + { 0xf407, 0xfc07, ' ', 1, "brid %k" }, + { 0xf007, 0xfc07, ' ', 1, "brie %k" }, + { 0xf000, 0xfc07, ' ', 1, "brlo %k" }, + { 0xf004, 0xfc07, ' ', 1, "brlt %k" }, + { 0xf002, 0xfc07, ' ', 1, "brmi %k" }, + { 0xf401, 0xfc07, ' ', 1, "brne %k" }, + { 0xf402, 0xfc07, ' ', 1, "brpl %k" }, + { 0xf400, 0xfc07, ' ', 1, "brsh %k" }, + { 0xf406, 0xfc07, ' ', 1, "brtc %k" }, + { 0xf006, 0xfc07, ' ', 1, "brts %k" }, + { 0xf403, 0xfc07, ' ', 1, "brvc %k" }, + { 0xf003, 0xfc07, ' ', 1, "brvs %k" }, + { 0xf400, 0xfc00, ' ', 1, "brbc %b,%k" }, + { 0xf000, 0xfc00, ' ', 1, "brbs %b,%k" }, + { 0x9408, 0xff8f, ' ', 1, "bset %s" }, + { 0xfa00, 0xfe00, ' ', 1, "bst %d,%b" }, + { 0x940e, 0xfe0e, ' ', 2, "call %A" }, + { 0x9800, 0xff00, ' ', 1, "cbi %P,%b" }, + { 0x9400, 0xfe0f, ' ', 1, "com %d" }, + { 0x1400, 0xfc00, ' ', 1, "cp %d,%r" }, + { 0x0400, 0xfc00, ' ', 1, "cpc %d,%r" }, + { 0x3000, 0xf000, ' ', 1, "cpi %D,%K" }, + { 0x1000, 0xfc00, ' ', 1, "cpse %d,%r" }, + { 0x940a, 0xfe0f, ' ', 1, "dec %d" }, + { 0x2400, 0xfc00, ' ', 1, "eor %d,%r" }, + { 0x9509, 0xff0f, ' ', 1, "icall" }, + { 0x9409, 0xff0f, ' ', 1, "ijmp" }, + { 0xb000, 0xf800, ' ', 1, "in %d,%p" }, + { 0x9403, 0xfe0f, ' ', 1, "inc %d" }, + { 0x940c, 0xfe0e, ' ', 2, "jmp %A" }, + { 0x900c, 0xfe0f, ' ', 1, "ld %d,X" }, + { 0x900d, 0xfe0f, ' ', 1, "ld %d,X+" }, + { 0x900e, 0xfe0f, ' ', 1, "ld %d,-X" }, + { 0x8008, 0xfe0f, ' ', 1, "ld %d,Y" }, + { 0x9009, 0xfe0f, ' ', 1, "ld %d,Y+" }, + { 0x900a, 0xfe0f, ' ', 1, "ld %d,-Y" }, + { 0x8008, 0xd208, ' ', 1, "ldd %d,Y+%q" }, + { 0x8000, 0xfe0f, ' ', 1, "ld %d,Z" }, + { 0x9001, 0xfe0f, ' ', 1, "ld %d,Z+" }, + { 0x9002, 0xfe0f, ' ', 1, "ld %d,-Z" }, + { 0x8000, 0xd208, ' ', 1, "ldd %d,Z+%q" }, + { 0xe000, 0xf000, ' ', 1, "ldi %D,%K" }, + { 0x9000, 0xfe0f, ' ', 2, "lds %d,%R" }, + { 0x95c8, 0xffff, ' ', 1, "lpm" }, + { 0x95d8, 0xffff, ' ', 1, "elpm" }, // in some devices equal to lpm + { 0x9406, 0xfe0f, ' ', 1, "lsr %d" }, + { 0x2c00, 0xfc00, ' ', 1, "mov %d,%r" }, + { 0x9c00, 0xfc00, ' ', 1, "mul %d,%r" }, + { 0x9401, 0xfe0f, ' ', 1, "neg %d" }, + { 0x2800, 0xfc00, ' ', 1, "or %d,%r" }, + { 0x6000, 0xf000, ' ', 1, "ori %d,%K" }, + { 0xb800, 0xf800, ' ', 1, "out %p,%d" }, + { 0x900f, 0xfe0f, ' ', 1, "pop %d" }, + { 0x920f, 0xfe0f, ' ', 1, "push %d" }, + { 0xd000, 0xf000, ' ', 1, "rcall %a" }, + { 0x9508, 0xff9f, ' ', 1, "ret" }, + { 0x9518, 0xff9f, ' ', 1, "reti" }, + { 0xc000, 0xf000, ' ', 1, "rjmp %a" }, + { 0x9407, 0xfe0f, ' ', 1, "ror %d" }, + { 0x0800, 0xfc00, ' ', 1, "sbc %d,%r" }, + { 0x4000, 0xf000, ' ', 1, "sbci %D,%K" }, + { 0x9a00, 0xff00, ' ', 1, "sbi %P,%b" }, + { 0x9900, 0xff00, ' ', 1, "sbic %P,%b" }, + { 0x9b00, 0xff00, ' ', 1, "sbis %P,%b" }, + { 0x9700, 0xff00, ' ', 1, "sbiw %2,%6" }, + { 0x6000, 0xf000, ' ', 1, "sbr %D,%K" }, + { 0xfc00, 0xfe00, ' ', 1, "sbrc %d,%b" }, + { 0xfe00, 0xfe00, ' ', 1, "sbrs %d,%b" }, + { 0xef0f, 0xff0f, ' ', 1, "ser %D" }, + { 0x9588, 0xffef, ' ', 1, "sleep" }, + { 0x920c, 0xfe0f, ' ', 1, "st X,%d" }, + { 0x920d, 0xfe0f, ' ', 1, "st X+,%d" }, + { 0x920e, 0xfe0f, ' ', 1, "st -X,%d" }, + { 0x8208, 0xfe0f, ' ', 1, "st Y,%d" }, + { 0x9209, 0xfe0f, ' ', 1, "st Y+,%d" }, + { 0x920a, 0xfe0f, ' ', 1, "st -Y,%d" }, + { 0x8208, 0xd208, ' ', 1, "std Y+%q,%d" }, + { 0x8200, 0xfe0f, ' ', 1, "st Z,%d" }, + { 0x9201, 0xfe0f, ' ', 1, "st Z+,%d" }, + { 0x9202, 0xfe0f, ' ', 1, "st -Z,%d" }, + { 0x8200, 0xd208, ' ', 1, "std Z+%q,%d" }, + { 0x9200, 0xfe0f, ' ', 2, "sts %R,%d" }, + { 0x1800, 0xfc00, ' ', 1, "sub %d,%r" }, + { 0x5000, 0xf000, ' ', 1, "subi %D,%K" }, + { 0x9402, 0xfe0f, ' ', 1, "swap %d" }, + { 0x95a8, 0xffef, ' ', 1, "wdr" }, + { 0, 0, 0, 0, NULL } +}; + +// Addresses are IRAM addresses! +struct name_entry sfr_tabl[]= { + { CPU_ALL_AVR, 0x001a, "XL"}, + { CPU_ALL_AVR, 0x001a, "XL" }, + { CPU_ALL_AVR, 0x001b, "XH" }, + { CPU_ALL_AVR, 0x001c, "YL" }, + { CPU_ALL_AVR, 0x001d, "YH" }, + { CPU_ALL_AVR, 0x001e, "ZL" }, + { CPU_ALL_AVR, 0x001f, "ZH" }, + { CPU_ALL_AVR, 0x0024, "ADCL" }, + { CPU_ALL_AVR, 0x0025, "ADCH" }, + { CPU_ALL_AVR, 0x0026, "ADCSR" }, + { CPU_ALL_AVR, 0x0027, "ADMUX" }, + { CPU_ALL_AVR, 0x0028, "ACSR" }, + { CPU_ALL_AVR, 0x0029, "UBRR" }, + { CPU_ALL_AVR, 0x002A, "UCR" }, + { CPU_ALL_AVR, 0x002B, "USR" }, + { CPU_ALL_AVR, 0x002C, "UDR" }, + { CPU_ALL_AVR, 0x002D, "SPCR" }, + { CPU_ALL_AVR, 0x002E, "SPSR" }, + { CPU_ALL_AVR, 0x002F, "SPDR" }, + { CPU_ALL_AVR, 0x0030, "PIND" }, + { CPU_ALL_AVR, 0x0031, "DDRD" }, + { CPU_ALL_AVR, 0x0032, "PORTD" }, + { CPU_ALL_AVR, 0x0033, "PINC" }, + { CPU_ALL_AVR, 0x0034, "DDRC" }, + { CPU_ALL_AVR, 0x0035, "PORTC" }, + { CPU_ALL_AVR, 0x0036, "PINB" }, + { CPU_ALL_AVR, 0x0037, "DDRB" }, + { CPU_ALL_AVR, 0x0038, "PORTB" }, + { CPU_ALL_AVR, 0x0039, "PINA" }, + { CPU_ALL_AVR, 0x003A, "DDRA" }, + { CPU_ALL_AVR, 0x003B, "PORTA" }, + { CPU_ALL_AVR, 0x003C, "EECR" }, + { CPU_ALL_AVR, 0x003D, "EEDR" }, + { CPU_ALL_AVR, 0x003E, "EEARL" }, + { CPU_ALL_AVR, 0x003E, "EEARH" }, + { CPU_ALL_AVR, 0x0041, "WDTCR" }, + { CPU_ALL_AVR, 0x0042, "ASSR" }, + { CPU_ALL_AVR, 0x0043, "OCR2" }, + { CPU_ALL_AVR, 0x0044, "TCNT2" }, + { CPU_ALL_AVR, 0x0045, "TCCR2" }, + { CPU_ALL_AVR, 0x0046, "ICR1L" }, + { CPU_ALL_AVR, 0x0047, "ICR1H" }, + { CPU_ALL_AVR, 0x0048, "OCR1BL" }, + { CPU_ALL_AVR, 0x0049, "OCR1BH" }, + { CPU_ALL_AVR, 0x004A, "OCR1AL" }, + { CPU_ALL_AVR, 0x004B, "OCR1AH" }, + { CPU_ALL_AVR, 0x004C, "TCNT1L" }, + { CPU_ALL_AVR, 0x004D, "TCNT1H" }, + { CPU_ALL_AVR, 0x004E, "TCCR1B" }, + { CPU_ALL_AVR, 0x004F, "TCCR1A" }, + { CPU_ALL_AVR, 0x0052, "TCNT0" }, + { CPU_ALL_AVR, 0x0053, "TCCR0" }, + { CPU_ALL_AVR, 0x0054, "MCUSR" }, + { CPU_ALL_AVR, 0x0055, "MCUCR" }, + { CPU_ALL_AVR, 0x0058, "TIFR" }, + { CPU_ALL_AVR, 0x0059, "TIMSK" }, + { CPU_ALL_AVR, 0x005A, "GIFR" }, + { CPU_ALL_AVR, 0x005B, "GIMSK" }, + { CPU_ALL_AVR, 0x005D, "SPL" }, + { CPU_ALL_AVR, 0x005E, "SPH" }, + { CPU_ALL_AVR, 0x005F, "SREG" }, + {0, 0} +}; + + +/* End of avr.src/glob.cc */ diff --git a/sim/ucsim/avr.src/glob.h b/sim/ucsim/avr.src/glob.h new file mode 100644 index 00000000..32bc79ca --- /dev/null +++ b/sim/ucsim/avr.src/glob.h @@ -0,0 +1,40 @@ +/* + * Simulator of microcontrollers (glob.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef GLOB_HEADER +#define GLOB_HEADER + +#include "stypes.h" + + +extern struct dis_entry disass_avr[]; +extern struct name_entry sfr_tabl[]; + + +#endif + +/* End of avr.src/glob.h */ diff --git a/sim/ucsim/avr.src/info_1001.txt b/sim/ucsim/avr.src/info_1001.txt new file mode 100644 index 00000000..c9650c1a --- /dev/null +++ b/sim/ucsim/avr.src/info_1001.txt @@ -0,0 +1,47 @@ +LDS Rd,k 1001 000d dddd 0000 +LD Rd,Z+ 1001 000d dddd 0001 +LD Rd,-Z 1001 000d dddd 0010 +LPM Rd,Z 1001 000d dddd 0100 +LPM Rd,Z+ 1001 000d dddd 0101 +ELMP Rd,Z 1001 000d dddd 0110 +ELMP Rd,Z+ 1001 000d dddd 0111 +LD Rd,Y+ 1001 000d dddd 1001 +LD Rd,-Y 1001 000d dddd 1010 +LD Rd,X 1001 000d dddd 1100 +LD Rd,X+ 1001 000d dddd 1101 +LD Rd,-X 1001 000d dddd 1110 +POP Rd 1001 000d dddd 1111 + +STS k,Rr 1001 001d dddd 0000 +ST Z+,Rr 1001 001r rrrr 0001 +ST -Z,Rr 1001 001r rrrr 0010 +ST Y+,Rr 1001 001r rrrr 1001 +ST -Y,Rr 1001 001r rrrr 1010 +ST X,Rr 1001 001r rrrr 1100 +ST X+,Rr 1001 001r rrrr 1101 +ST -X,Rr 1001 001r rrrr 1110 +PUSH Rr 1001 001d dddd 1111 + +COM Rd 1001 010d dddd 0000 +NEG Rd 1001 010d dddd 0001 +SWAP Rd 1001 010d dddd 0010 +INC Rd 1001 010d dddd 0011 +ASR Rd 1001 010d dddd 0101 +LSR Rd 1001 010d dddd 0110 +ROR Rd 1001 010d dddd 0111 +DEC Rd 1001 010d dddd 1010 +JMP k 1001 010k kkkk 110k +CALL k 1001 010k kkkk 111k + +BSET s 1001 0100 0sss 1000 +BCLR s 1001 0100 1sss 1000 + +ADIW Rd,K 1001 0110 KKdd KKKK +SBIW Rd,K 1001 0111 KKdd KKKK + +CBI A,b 1001 1000 AAAA Abbb +SBIC A,b 1001 1001 AAAA Abbb +SBI A,b 1001 1010 AAAA Abbb +SBIS A,b 1001 1011 AAAA Abbb + +MUL Rd,Rr 1001 11rd dddd rrrr diff --git a/sim/ucsim/avr.src/info_1111.txt b/sim/ucsim/avr.src/info_1111.txt new file mode 100644 index 00000000..0faf0a15 --- /dev/null +++ b/sim/ucsim/avr.src/info_1111.txt @@ -0,0 +1,27 @@ +BRCS k 1111 00kk kkkk k000 =BRBS 0,k =BRLO k +BRLO k 1111 00kk kkkk k000 =BRBS 0,k =BRCS k +BREQ k 1111 00kk kkkk k001 =BRBS 1,k +BRMI k 1111 00kk kkkk k010 =BRBS 2,k +BRVS k 1111 00kk kkkk k011 =BRBS 3,k +BRLT k 1111 00kk kkkk k100 =BRBS 4,k +BRHS k 1111 00kk kkkk k101 =BRBS 5,k +BRTS k 1111 00kk kkkk k110 =BRBS 6,k +BRIE k 1111 00kk kkkk k111 =BRBS 7,k +BRBS s,k 1111 00kk kkkk ksss + +BRCC k 1111 01kk kkkk k000 =BRBC 0,k +BRHS k 1111 01kk kkkk k000 =BRBC 0,k +BRNE k 1111 01kk kkkk k001 =BRBC 1,k +BRPL k 1111 01kk kkkk k010 =BRBC 2,k +BRVC k 1111 01kk kkkk k011 =BRBC 3,k +BRGE k 1111 01kk kkkk k100 =BRBC 4,k +BRHC k 1111 01kk kkkk k101 =BRBC 5,k +BRTC k 1111 01kk kkkk k110 =BRBC 6,k +BRID k 1111 01kk kkkk k111 =BRBC 7,k +BRBC s,k 1111 01kk kkkk ksss + +BLD Rd,b 1111 100d dddd 0bbb +BST Rd,b 1111 101d dddd 0bbb + +SBRC Rr,b 1111 110r rrrr 0bbb +SBRS Rr,b 1111 111r rrrr 0bbb diff --git a/sim/ucsim/avr.src/info_types.txt b/sim/ucsim/avr.src/info_types.txt new file mode 100644 index 00000000..21f4115d --- /dev/null +++ b/sim/ucsim/avr.src/info_types.txt @@ -0,0 +1,23 @@ + inst Flash EE SRAM I/O Vcc Speed +AT90S1200 89 1K 64 0 15 2.7-6.0 0-12 +AT90S2313 118 2K 128 128 15 2.7-6.0 0-10 +AT90S2323 118 2K 128 128 3 4.0-6.0 0-10 +AT90LS2323 118 2K 128 128 3 2.7-6.0 0-4 +AT90S2343 118 2K 128 128 5 4.0-6.0 0-10 +AT90LS2343 118 2K 128 128 5 2.7-6.0 0-4 +AT90S2333 118 2K 128 128 20 4.0-6.0 0-8 +AT90LS2333 118 2K 128 128 20 2.7-6.0 0-4 +AT90S4433 118 4K 256 128 20 4.0-6.0 0-8 +AT90LS4433 118 4K 256 128 20 2.7-6.0 0-4 +AT90S4414 118 4K 256 256 32 2.7-6.0 0-8 +AT90S4434 118 4K 256 256 32 4.0-6.0 0-8 +AT90LS4434 118 4K 256 256 32 2.7-6.0 0-4 +AT90S8535 118 8K 512 512 32 4.0-6.0 0-8 +AT90LS8535 118 8K 512 512 32 2.7-6.0 0-4 +AT90S8515 118 8K 512 512 32 2.7-6.0 0-8 +ATmega603 121 64K 2K 4K 32 4.0-5.5 0-6 +ATmega603L 121 64K 2K 4K 32 2.7-3.6 0-4 +ATmega103 121 128K 4K 4K 32 4.0-5.5 0-6 +ATmega103L 121 128K 4K 4K 32 2.7-3.6 0-4 + +1200 2313 2323 2343 2333 4333 4414/34 8535/15 603 103 \ No newline at end of file diff --git a/sim/ucsim/avr.src/inst.cc b/sim/ucsim/avr.src/inst.cc new file mode 100644 index 00000000..32809dec --- /dev/null +++ b/sim/ucsim/avr.src/inst.cc @@ -0,0 +1,80 @@ +/* + * Simulator of microcontrollers (inst.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "avrcl.h" +#include "regsavr.h" + + +/* + * No Instruction + * NOP + * 0000 0000 0000 0000 + *---------------------------------------------------------------------------- + */ + +int +cl_avr::nop(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::sleep(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::wdr(t_mem code) +{ + return(resGO); +} + + +/* + * Set all bits in Register + * SER Rd 16<=d<=31 + * 1110 1111 dddd 1111 + *____________________________________________________________________________ + */ + +int +cl_avr::ser_Rd(t_mem code) +{ + t_addr d= (code&0xf0)>>4; + t_mem data= 0xff; + ram->write(d, &data); + return(resGO); +} + + +/* End of avr.src/inst.cc */ diff --git a/sim/ucsim/avr.src/instcl.h b/sim/ucsim/avr.src/instcl.h new file mode 100644 index 00000000..62b23983 --- /dev/null +++ b/sim/ucsim/avr.src/instcl.h @@ -0,0 +1,8 @@ +/* avr.src/instcl.h */ + + virtual int nop(t_mem code); + virtual int sleep(t_mem code); + virtual int wdr(t_mem code); + virtual int ser_Rd(t_mem code); + +/* End of avr.src/instcl.h */ diff --git a/sim/ucsim/avr.src/jump_cl.h b/sim/ucsim/avr.src/jump_cl.h new file mode 100644 index 00000000..92dedc7d --- /dev/null +++ b/sim/ucsim/avr.src/jump_cl.h @@ -0,0 +1,21 @@ +/* avr.src/jump_cl.h */ + + virtual int ijmp(t_mem code); + virtual int eijmp(t_mem code); + virtual int icall(t_mem code); + virtual int eicall(t_mem code); + virtual int ret(t_mem code); + virtual int reti(t_mem code); + virtual int rjmp_k(t_mem code); + virtual int rcall_k(t_mem code); + virtual int cpse_Rd_Rr(t_mem code); + virtual int jmp_k(t_mem code); + virtual int call_k(t_mem code); + virtual int brbs_s_k(t_mem code); + virtual int brbc_s_k(t_mem code); + virtual int sbrc_Rr_b(t_mem code); + virtual int sbrs_Rr_b(t_mem code); + virtual int sbic_P_b(t_mem code); + virtual int sbis_P_b(t_mem code); + +/* End of avr.src/jump_cl.h */ diff --git a/sim/ucsim/avr.src/jump_inst.cc b/sim/ucsim/avr.src/jump_inst.cc new file mode 100644 index 00000000..4b300b3a --- /dev/null +++ b/sim/ucsim/avr.src/jump_inst.cc @@ -0,0 +1,370 @@ +/* + * Simulator of microcontrollers (jmp_inst.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "avrcl.h" +#include "regsavr.h" + + +/* + * Indirect Jump + * IJMP + * 1001 0100 XXXX 1001 + *____________________________________________________________________________ + */ + +int +cl_avr::ijmp(t_mem code) +{ + t_addr z; + + z= ram->get(ZH)*256 + ram->get(ZL); + PC= ((PC & ~0xffff) | z) % rom->size; + return(resGO); +} + + +int +cl_avr::eijmp(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::icall(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::eicall(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::ret(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::reti(t_mem code) +{ + return(resGO); +} + + +/* + * Relative Jump + * RJMP k -2K<=k<=2K + * 1100 kkkk kkkk kkkk + *____________________________________________________________________________ + */ + +int +cl_avr::rjmp_k(t_mem code) +{ + long k= code & 0xfff, pc; + + if (k & 0x800) + k|= -4096; + pc= PC+k; + if (pc < 0) + pc= rom->size + pc; + PC= pc % rom->size; + tick(1); + return(resGO); +} + + +int +cl_avr::rcall_k(t_mem code) +{ + return(resGO); +} + + +/* + * Compare Skip if Equal + * CPSE Rd,Rr 0<=d<=31, 0<=r<=31 + * 0001 00rd dddd rrrr + *____________________________________________________________________________ + */ + +int +cl_avr::cpse_Rd_Rr(t_mem code) +{ + t_addr d, r; + + d= (code&0x1f0)>>4; + r= ((code&0x200)>>5)|(code&0xf); + if (ram->read(r) == ram->read(d)) + { + t_mem next_code= rom->get(PC); + int i= 0; + struct dis_entry *dt= dis_tbl(); + while ((next_code & dt[i].mask) != dt[i].code && + dt[i].mnemonic) + i++; + if (dt[i].mnemonic != NULL) + { + PC= (PC + dt[i].length) % get_mem_size(MEM_ROM); + tick(1); + } + else + return(resINV_INST); + } + return(resGO); +} + + +/* + * Jump + * JMP k 0<=k<=4M + * 1001 010k kkkk 110k + * kkkk kkkk kkkk kkkk + *____________________________________________________________________________ + */ + +int +cl_avr::jmp_k(t_mem code) +{ + t_addr k; + + k= ((code&0x1f0)>>3)|(code&1); + k= (k<<16)|fetch(); + PC= k; + //FIXME: analyze + tick(2); + return(resGO); +} + + +/* + * Long Call to a Subroutine + * CALL k 0<=k<=64k/4M + * 1001 010k kkkk 111k + * kkkk kkkk kkkk kkkk + *____________________________________________________________________________ + */ + +int +cl_avr::call_k(t_mem code) +{ + t_addr k; + + k= (((code&0x1f0)>>3)|(code&1))*0x10000; + k= k + fetch(); + + tick(3); + return(resGO); +} + + +/* + * Branch if Bit in SREG is Set + * BRBS s,k 0<=s<=7, -64<=k<=+63 + * 1111 00kk kkkk ksss + *____________________________________________________________________________ + */ + +int +cl_avr::brbs_s_k(t_mem code) +{ + int s, k; + + k= (code&0x3f8)>>3; + s= code&7; + t_mem sreg= ram->get(SREG); + t_mem mask= 1<>3; + s= code&7; + t_mem sreg= ram->get(SREG); + t_mem mask= 1<>4; + int b= code&7; + t_mem mask= 1<read(r) & mask)) + { + t_mem next_code= rom->get(PC); + int i= 0; + struct dis_entry *dt= dis_tbl(); + while ((next_code & dt[i].mask) != dt[i].code && + dt[i].mnemonic) + i++; + if (dt[i].mnemonic != NULL) + { + PC= (PC + dt[i].length) % get_mem_size(MEM_ROM); + tick(1); + } + else + return(resINV_INST); + } + return(resGO); +} + + +/* + * Skip if Bit in Register is Set + * SBRS Rr,b 0<=r<=31, 0<=b<=7 + * 1111 111r rrrr Xbbb + *____________________________________________________________________________ + */ + +int +cl_avr::sbrs_Rr_b(t_mem code) +{ + t_addr r= (code&0x1f0)>>4; + int b= code&7; + t_mem mask= 1<read(r) & mask) + { + t_mem next_code= rom->get(PC); + int i= 0; + struct dis_entry *dt= dis_tbl(); + while ((next_code & dt[i].mask) != dt[i].code && + dt[i].mnemonic) + i++; + if (dt[i].mnemonic != NULL) + { + PC= (PC + dt[i].length) % get_mem_size(MEM_ROM); + tick(1); + } + else + return(resINV_INST); + } + return(resGO); +} + + +/* + * Skip if Bit in I/O Register is Clear + * SBIC P,b 0<=P<=31 0<=b<=7 + * 1001 1001 pppp pbbb + *____________________________________________________________________________ + */ + +int +cl_avr::sbic_P_b(t_mem code) +{ + uint addr, mask; + + addr= ((code&0xf8)>>3)+0x20; + mask= 1 << (code&7); + if (0 == (mask & ram->read(addr))) + { + code= fetch(); + int size= inst_length(code); + while (size > 1) + { + fetch(); + size--; + } + tick(1); + } + return(resGO); +} + + +/* + * Skip if Bit in I/O Register is Set + * SBIS P,b 0<=P<=31 0<=b<=7 + * 1001 1011 pppp pbbb + *____________________________________________________________________________ + */ + +int +cl_avr::sbis_P_b(t_mem code) +{ + uint addr, mask; + + addr= ((code&0xf8)>>3)+0x20; + mask= 1 << (code&7); + if (mask & ram->read(addr)) + { + code= fetch(); + int size= inst_length(code); + while (size > 1) + { + fetch(); + size--; + } + tick(1); + } + return(resGO); +} + + +/* End of avr.src/jump_inst.cc */ diff --git a/sim/ucsim/avr.src/logic_cl.h b/sim/ucsim/avr.src/logic_cl.h new file mode 100644 index 00000000..636eba4f --- /dev/null +++ b/sim/ucsim/avr.src/logic_cl.h @@ -0,0 +1,9 @@ +/* avr.src/logic_cl.h */ + + virtual int ori_Rd_K(t_mem code); + virtual int andi_Rd_K(t_mem code); + virtual int and_Rd_Rr(t_mem code); + virtual int eor_Rd_Rr(t_mem code); + virtual int or_Rd_Rr(t_mem code); + +/* End of avr.src/logic_cl.h */ diff --git a/sim/ucsim/avr.src/logic_inst.cc b/sim/ucsim/avr.src/logic_inst.cc new file mode 100644 index 00000000..fadc9808 --- /dev/null +++ b/sim/ucsim/avr.src/logic_inst.cc @@ -0,0 +1,142 @@ +/* + * Simulator of microcontrollers (logic_inst.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "avrcl.h" +#include "regsavr.h" + + +/* + * Logical OR with Immediate + * ORI Rd,K 16<=d<=31 0<=K<=255 + * 0110 KKKK dddd KKKK + *____________________________________________________________________________ + */ + +int +cl_avr::ori_Rd_K(t_mem code) +{ + t_addr d; + t_mem K, data; + + d= (code&0xf0)>>4; + K= ((code&0xf00)>>4)|(code&0xf); + data= K | ram->read(d); + ram->write(d+16, &data); + set_zn0s(data); + return(resGO); +} + + +/* + * Logical AND with Immediate + * ANDI Rd,K 16<=d<=31 0<=K<=255 + * 0111 KKKK dddd KKKK + *____________________________________________________________________________ + */ + +int +cl_avr::andi_Rd_K(t_mem code) +{ + t_addr d; + t_mem K, data; + + d= (code&0xf0)>>4; + K= ((code&0xf00)>>4)|(code&0xf); + data= K & ram->read(d); + ram->write(d+16, &data); + set_zn0s(data); + return(resGO); +} + + +/* + * Logical AND + * AND Rd,Rr 0<=d<=31 0<=r<=31 + * 0010 00rd dddd rrrr + *____________________________________________________________________________ + */ + +int +cl_avr::and_Rd_Rr(t_mem code) +{ + t_addr d, r; + t_mem data; + + d= (code&0x1f0)>>4; + r= ((code&0x200)>>5)|(code&0xf); + data= ram->read(d) & ram->read(r); + ram->write(d, &data); + set_zn0s(data); + return(resGO); +} + + +/* + * Exclusive OR + * EOR Rd,Rr 0<=d<=31 0<=r<=31 + * 0010 01rd dddd rrrr + *____________________________________________________________________________ + */ + +int +cl_avr::eor_Rd_Rr(t_mem code) +{ + t_addr d, r; + t_mem data; + + d= (code&0x1f0)>>4; + r= ((code&0x200)>>5)|(code&0xf); + data= ram->read(d) ^ ram->read(r); + ram->write(d, &data); + set_zn0s(data); + return(resGO); +} + + +/* + * Logical OR + * OR Rd,Rr 0<=d<=31 0<=r<=31 + * 0010 10rd dddd rrrr + *____________________________________________________________________________ + */ + +int +cl_avr::or_Rd_Rr(t_mem code) +{ + t_addr d, r; + t_mem data; + + d= (code&0x1f0)>>4; + r= ((code&0x200)>>5)|(code&0xf); + data= ram->read(d) | ram->read(r); + ram->write(d, &data); + set_zn0s(data); + return(resGO); +} + + +/* End of avr.src/logic_inst.cc */ diff --git a/sim/ucsim/avr.src/move_cl.h b/sim/ucsim/avr.src/move_cl.h new file mode 100644 index 00000000..ffe7b4b7 --- /dev/null +++ b/sim/ucsim/avr.src/move_cl.h @@ -0,0 +1,40 @@ +/* avr.src/move_cl.h */ + + virtual int lpm(t_mem code); + virtual int elpm(t_mem code); + virtual int spm(t_mem code); + virtual int espm(t_mem code); + virtual int ldi_Rd_K(t_mem code); + virtual int movw_Rd_Rr(t_mem code); + virtual int lds_Rd_k(t_mem code); + virtual int ld_Rd_Z$(t_mem code); + virtual int ld_Rd_$Z(t_mem code); + virtual int lpm_Rd_Z(t_mem code); + virtual int lpm_Rd_Z$(t_mem code); + virtual int elpm_Rd_Z(t_mem code); + virtual int elpm_Rd_Z$(t_mem code); + virtual int ld_Rd_Y$(t_mem code); + virtual int ld_Rd_$Y(t_mem code); + virtual int ld_Rd_X(t_mem code); + virtual int ld_Rd_X$(t_mem code); + virtual int ld_Rd_$X(t_mem code); + virtual int pop_Rd(t_mem code); + virtual int sts_k_Rr(t_mem code); + virtual int st_Z$_Rr(t_mem code); + virtual int st_$Z_Rr(t_mem code); + virtual int st_Y$_Rr(t_mem code); + virtual int st_$Y_Rr(t_mem code); + virtual int st_X_Rr(t_mem code); + virtual int st_X$_Rr(t_mem code); + virtual int st_$X_Rr(t_mem code); + virtual int push_Rr(t_mem code); + virtual int swap_Rd(t_mem code); + virtual int ldd_Rd_Z_q(t_mem code); + virtual int ldd_Rd_Y_q(t_mem code); + virtual int std_Z_q_Rr(t_mem code); + virtual int std_Y_q_Rr(t_mem code); + virtual int in_Rd_A(t_mem code); + virtual int out_A_Rr(t_mem code); + virtual int mov_Rd_Rr(t_mem code); + +/* End of avr.src/move_cl.h */ diff --git a/sim/ucsim/avr.src/move_inst.cc b/sim/ucsim/avr.src/move_inst.cc new file mode 100644 index 00000000..b8271f5a --- /dev/null +++ b/sim/ucsim/avr.src/move_inst.cc @@ -0,0 +1,703 @@ +/* + * Simulator of microcontrollers (move_inst.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "avrcl.h" +#include "regsavr.h" + + +/* + * Load Program Memory + * LPM + * 1001 0101 110X 1000 + *____________________________________________________________________________ + */ + +int +cl_avr::lpm(t_mem code) +{ + t_addr addr; + t_mem data; + + addr= ram->get(ZH)*256 + ram->get(ZL); + data= rom->read(addr); + if (addr & 1) + ram->/*write*/set(0, (data>>8)&0xff); + else + ram->/*write*/set(0, data&0xff); + tick(2); + return(resGO); +} + + +int +cl_avr::elpm(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::spm(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::espm(t_mem code) +{ + return(resGO); +} + + +/* + * Load Immediate + * LDI Rd,K 16<=d<=31 0<=K<=255 + * 1110 KKKK dddd KKKK + *____________________________________________________________________________ + */ + +int +cl_avr::ldi_Rd_K(t_mem code) +{ + t_addr d; + t_mem K; + + d= (code&0xf0)>>4; + K= ((code&0xf00)>>4)|(code&0xf); + ram->write(d+16, &K); + return(resGO); +} + + +int +cl_avr::movw_Rd_Rr(t_mem code) +{ + return(resGO); +} + + +/* + * Load Indirect From SRAM to Register using Index Z + * LDD Rd,Z+q 0<=d<=31, 0<=q<=63 + * 10q0 qq0d dddd 0qqq + *____________________________________________________________________________ + */ + +int +cl_avr::ldd_Rd_Z_q(t_mem code) +{ + int d, q; + t_addr z; + + d= (code&0x1f0)>>4; + q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7); + z= ram->get(ZH)*256 + ram->get(ZL); + t_mem data= ram->read(z+q); + ram->write(d, &data); + tick(1); + return(resGO); +} + + +/* + * Load Indirect From SRAM to Register using Index Y + * LDD Rd,Y+q 0<=d<=31, 0<=q<=63 + * 10q0 qq0d dddd 1qqq + *____________________________________________________________________________ + */ + +int +cl_avr::ldd_Rd_Y_q(t_mem code) +{ + int d, q; + t_addr y; + + d= (code&0x1f0)>>4; + q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7); + y= ram->get(YH)*256 + ram->get(YL); + t_mem data= ram->read(y+q); + ram->write(d, &data); + tick(1); + return(resGO); +} + + +/* + * Store Indirect From Register to SRAM using Index Z + * ST Z+q,Rr 0<=r<=31, 0<=q<=63 + * 10q0 qq1r rrrr 0qqq + *____________________________________________________________________________ + */ + +int +cl_avr::std_Z_q_Rr(t_mem code) +{ + int r, q; + t_addr z; + + r= (code&0x1f0)>>4; + q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7); + z= ram->get(ZH)*256 + ram->get(ZL); + t_mem data= ram->read(r); + ram->write(z+q, &data); + tick(1); + return(resGO); +} + + +/* + * Store Indirect From Register to SRAM using Index Y + * ST Y+q,Rr 0<=r<=31, 0<=q<=63 + * 10q0 qq1r rrrr 1qqq + *____________________________________________________________________________ + */ + +int +cl_avr::std_Y_q_Rr(t_mem code) +{ + int r, q; + t_addr y; + + r= (code&0x1f0)>>4; + q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7); + y= ram->get(YH)*256 + ram->get(YL); + t_mem data= ram->read(r); + ram->write(y+q, &data); + tick(1); + return(resGO); +} + + +/* + * Load Direct from SRAM + * LDS Rd,k 0<=d<=31, 0<=k<=65535 + * 1001 000d dddd 0000 + * kkkk kkkk kkkk kkkk + *____________________________________________________________________________ + */ + +int +cl_avr::lds_Rd_k(t_mem code) +{ + t_addr d, k; + + d= (code&0x1f0)>>4; + k= fetch(); + t_mem data= ram->read(k); + ram->write(d, &data); + tick(2); + return(resGO); +} + + +/* + * Load Indirect From SRAM to register using Index Z + * LD Rd,Z+ 0<=d<=31 + * 1001 000d dddd 0001 + *____________________________________________________________________________ + */ + +int +cl_avr::ld_Rd_Z$(t_mem code) +{ + t_addr z, d; + + d= (code&0x1f0)>>4; + z= ram->get(ZH)*256 + ram->get(ZL); + t_mem data= ram->read(z); + ram->write(d, &data); + ram->set(ZL, data= (ram->get(ZL)+1)&0xff); + if (!data) + ram->set(ZH, (ram->get(ZH)+1)&0xff); + tick(1); + return(resGO); +} + + +/* + * Load Indirect From SRAM to register using Index Z + * LD Rd,-Z 0<=d<=31 + * 1001 000d dddd 0010 + *____________________________________________________________________________ + */ + +int +cl_avr::ld_Rd_$Z(t_mem code) +{ + t_addr z, d; + t_mem data; + + d= (code&0x1f0)>>4; + ram->set(ZL, z= (ram->get(ZL)-1)&0xff); + if (z == 0xff) + ram->set(ZH, (ram->get(ZH)-1)&0xff); + z= ram->get(ZH)*256 + z; + data= ram->read(z); + ram->write(d, &data); + tick(1); + return(resGO); +} + + +int +cl_avr::lpm_Rd_Z(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::lpm_Rd_Z$(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::elpm_Rd_Z(t_mem code) +{ + return(resGO); +} + + +int +cl_avr::elpm_Rd_Z$(t_mem code) +{ + return(resGO); +} + + +/* + * Load Indirect From SRAM to register using Index Y + * LD Rd,Y+ 0<=d<=31 + * 1001 000d dddd 1001 + *____________________________________________________________________________ + */ + +int +cl_avr::ld_Rd_Y$(t_mem code) +{ + t_addr y, d; + + d= (code&0x1f0)>>4; + y= ram->get(YH)*256 + ram->get(YL); + t_mem data= ram->read(y); + ram->write(d, &data); + ram->set(YL, data= (ram->get(YL)+1)&0xff); + if (!data) + ram->set(YH, (ram->get(YH)+1)&0xff); + tick(1); + return(resGO); +} + + +/* + * Load Indirect From SRAM to register using Index Y + * LD Rd,-Y 0<=d<=31 + * 1001 000d dddd 1010 + *____________________________________________________________________________ + */ + +int +cl_avr::ld_Rd_$Y(t_mem code) +{ + t_addr y, d; + t_mem data; + + d= (code&0x1f0)>>4; + ram->set(YL, y= (ram->get(YL)-1)&0xff); + if (y == 0xff) + ram->set(YH, (ram->get(YH)-1)&0xff); + y= ram->get(YH)*256 + y; + data= ram->read(y); + ram->write(d, &data); + tick(1); + return(resGO); +} + + +/* + * Load Indirect From SRAM to register using Index X + * LD Rd,X 0<=d<=31 + * 1001 000d dddd 1100 + *____________________________________________________________________________ + */ + +int +cl_avr::ld_Rd_X(t_mem code) +{ + t_addr x, d; + + d= (code&0x1f0)>>4; + x= ram->get(XH)*256 + ram->get(XL); + t_mem data= ram->read(x); + ram->write(d, &data); + tick(1); + return(resGO); +} + + +/* + * Load Indirect From SRAM to register using Index X + * LD Rd,X+ 0<=d<=31 + * 1001 000d dddd 1101 + *____________________________________________________________________________ + */ + +int +cl_avr::ld_Rd_X$(t_mem code) +{ + t_addr x, d; + + d= (code&0x1f0)>>4; + x= ram->get(XH)*256 + ram->get(XL); + t_mem data= ram->read(x); + ram->write(d, &data); + ram->set(XL, data= (ram->get(XL)+1)&0xff); + if (!data) + ram->set(XH, (ram->get(XH)+1)&0xff); + tick(1); + return(resGO); +} + + +/* + * Load Indirect From SRAM to register using Index X + * LD Rd,-X 0<=d<=31 + * 1001 000d dddd 1110 + *____________________________________________________________________________ + */ + +int +cl_avr::ld_Rd_$X(t_mem code) +{ + t_addr x, d; + t_mem data; + + d= (code&0x1f0)>>4; + ram->set(XL, x= (ram->get(XL)-1)&0xff); + if (x == 0xff) + ram->set(XH, (ram->get(XH)-1)&0xff); + x= ram->get(XH)*256 + x; + data= ram->read(x); + ram->write(d, &data); + tick(1); + return(resGO); +} + + +int +cl_avr::pop_Rd(t_mem code) +{ + return(resGO); +} + + +/* + * Store Direct to SRAM + * STS k,Rr 0<=r<=31, 0<=k<=65535 + * 1001 001r rrrr 0000 + * kkkk kkkk kkkk kkkk + *____________________________________________________________________________ + */ + +int +cl_avr::sts_k_Rr(t_mem code) +{ + t_addr r, k; + + r= (code&0x1f0)>>4; + k= fetch(); + t_mem data= ram->read(r); + ram->write(k, &data); + tick(2); + return(resGO); +} + + +/* + * Store Indirect From Register to SRAM using Index Z + * ST Z+,Rr 0<=r<=63 + * 1001 001r rrrr 0001 + *____________________________________________________________________________ + */ + +int +cl_avr::st_Z$_Rr(t_mem code) +{ + t_addr z, r; + + r= (code&0x1f0)>>4; + z= ram->get(ZH)*256 + ram->get(ZL); + t_mem data= ram->read(r); + ram->write(z, &data); + ram->set(ZL, data= (ram->get(ZL)+1)&0xff); + if (!data) + ram->set(ZH, (ram->get(ZH)+1)&0xff); + tick(1); + return(resGO); +} + + +/* + * Store Indirect From Register to SRAM using Index Z + * ST -Z,Rr 0<=r<=63 + * 1001 001r rrrr 0010 + *____________________________________________________________________________ + */ + +int +cl_avr::st_$Z_Rr(t_mem code) +{ + t_addr z, r; + t_mem data; + + r= (code&0x1f0)>>4; + ram->set(ZL, z= (ram->get(ZL)-1)&0xff); + if (z == 0xff) + ram->set(ZH, (ram->get(ZH)-1)&0xff); + z= ram->get(ZH)*256 + z; + data= ram->read(r); + ram->write(z, &data); + tick(1); + return(resGO); +} + + +/* + * Store Indirect From Register to SRAM using Index Y + * ST Y+,Rr 0<=r<=63 + * 1001 001r rrrr 1001 + *____________________________________________________________________________ + */ + +int +cl_avr::st_Y$_Rr(t_mem code) +{ + t_addr y, r; + + r= (code&0x1f0)>>4; + y= ram->get(YH)*256 + ram->get(YL); + t_mem data= ram->read(r); + ram->write(y, &data); + ram->set(YL, data= (ram->get(YL)+1)&0xff); + if (!data) + ram->set(YH, (ram->get(YH)+1)&0xff); + tick(1); + return(resGO); +} + + +/* + * Store Indirect From Register to SRAM using Index Y + * ST -Y,Rr 0<=r<=63 + * 1001 001r rrrr 1010 + *____________________________________________________________________________ + */ + +int +cl_avr::st_$Y_Rr(t_mem code) +{ + t_addr y, r; + t_mem data; + + r= (code&0x1f0)>>4; + ram->set(YL, y= (ram->get(YL)-1)&0xff); + if (y == 0xff) + ram->set(YH, (ram->get(YH)-1)&0xff); + y= ram->get(YH)*256 + y; + data= ram->read(r); + ram->write(y, &data); + tick(1); + return(resGO); +} + + +/* + * Store Indirect From Register to SRAM using Index X + * ST X,Rr 0<=r<=31 + * 1001 001r rrrr 1100 + *____________________________________________________________________________ + */ + +int +cl_avr::st_X_Rr(t_mem code) +{ + int r; + t_addr x; + + r= (code&0x1f0)>>4; + x= ram->get(XH)*256 + ram->get(XL); + t_mem data= ram->read(r); + ram->write(x, &data); + tick(1); + return(resGO); +} + + +/* + * Store Indirect From Register to SRAM using Index X + * ST X+,Rr 0<=r<=63 + * 1001 001r rrrr 1101 + *____________________________________________________________________________ + */ + +int +cl_avr::st_X$_Rr(t_mem code) +{ + t_addr x, r; + + r= (code&0x1f0)>>4; + x= ram->get(XH)*256 + ram->get(XL); + t_mem data= ram->read(r); + ram->write(x, &data); + ram->set(XL, data= (ram->get(XL)+1)&0xff); + if (!data) + ram->set(XH, (ram->get(XH)+1)&0xff); + tick(1); + return(resGO); +} + + +/* + * Store Indirect From Register to SRAM using Index X + * ST -X,Rr 0<=r<=63 + * 1001 001r rrrr 1110 + *____________________________________________________________________________ + */ + +int +cl_avr::st_$X_Rr(t_mem code) +{ + t_addr x, r; + t_mem data; + + r= (code&0x1f0)>>4; + ram->set(XL, x= (ram->get(XL)-1)&0xff); + if (x == 0xff) + ram->set(XH, (ram->get(XH)-1)&0xff); + x= ram->get(XH)*256 + x; + data= ram->read(r); + ram->write(x, &data); + tick(1); + return(resGO); +} + + +int +cl_avr::push_Rr(t_mem code) +{ + return(resGO); +} + + +/* + * Swap Nibbles + * SWAP Rd 0<=d<=31 + * 1001 010d dddd 0010 + *____________________________________________________________________________ + */ + +int +cl_avr::swap_Rd(t_mem code) +{ + t_addr d; + t_mem data, temp; + + d= (code&0x1f0)>>4; + data= ram->read(d); + temp= (data>>4)&0xf; + data= (data<<4)|temp; + ram->write(d, &data); + return(resGO); +} + + +/* + * Load an I/O Port to Register + * IN Rd,P 0<=d<=31 0<=P<=63 + * 1011 0PPd dddd PPPP + *____________________________________________________________________________ + */ + +int +cl_avr::in_Rd_A(t_mem code) +{ + t_mem P, data; + t_addr d; + + P= ((code&0x600)>>5)|(code&0xf); + d= (code&0x1f0)>>4; + data= ram->read(P+0x20); + ram->write(d, &data); + return(resGO); +} + + +/* + * Store Register to I/O Port + * OUT P,Rr 0<=r<=31 0<=P<=63 + * 1011 1PPr rrrr PPPP + *____________________________________________________________________________ + */ + +int +cl_avr::out_A_Rr(t_mem code) +{ + t_mem P, data; + t_addr r; + + P= ((code&0x600)>>5)|(code&0xf); + r= (code&0x1f0)>>4; + data= ram->read(r); + ram->write(P+0x20, &data); + return(resGO); +} + + +/* + * Copy Register + * MOV Rd,Rr 0<=d<=31 0<=r<=31 + * 0010 11rd dddd rrrr + *____________________________________________________________________________ + */ + +int +cl_avr::mov_Rd_Rr(t_mem code) +{ + t_addr d, r; + + d= (code&0x1f0)>>4; + r= ((code&0x200)>>5)|(code&0xf); + t_mem data= ram->read(r); + ram->write(d, &data); + return(resGO); +} + + +/* End of avr.src/move_inst.cc */ diff --git a/sim/ucsim/avr.src/port.cc b/sim/ucsim/avr.src/port.cc new file mode 100644 index 00000000..ca7be64b --- /dev/null +++ b/sim/ucsim/avr.src/port.cc @@ -0,0 +1,55 @@ +/* + * Simulator of microcontrollers (port.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + + +#include + +#include "portcl.h" + + +cl_port::cl_port(class cl_uc *auc): + cl_hw(auc, HW_PORT, 0, "port") +{ + uc->register_hw_read(MEM_SFR, 2, this); + uc->register_hw_read(MEM_SFR, 4, this); +} + +ulong +cl_port::read(class cl_mem *mem, long addr) +{ + switch (addr) + { + case 2: + return(22); + case 4: + return(44); + } + return(cl_hw::read(mem, addr)); +} + + +/* End of avr.src/port.cc */ diff --git a/sim/ucsim/avr.src/portcl.h b/sim/ucsim/avr.src/portcl.h new file mode 100644 index 00000000..fc189c74 --- /dev/null +++ b/sim/ucsim/avr.src/portcl.h @@ -0,0 +1,45 @@ +/* + * Simulator of microcontrollers (portcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef PORTCL_HEADER +#define PORTCL_HEADER + +#include "hwcl.h" + + +class cl_port: public cl_hw +{ +public: + cl_port(class cl_uc *auc); + + virtual ulong read(class cl_mem *mem, long addr); +}; + + +#endif + +/* End of avr.src/portcl.h */ diff --git a/sim/ucsim/avr.src/regsavr.h b/sim/ucsim/avr.src/regsavr.h new file mode 100644 index 00000000..a0d72b17 --- /dev/null +++ b/sim/ucsim/avr.src/regsavr.h @@ -0,0 +1,113 @@ +/* + * Simulator of microcontrollers (regsavr.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef REGSAVR_HEADER +#define REGSAVR_HEADER + +/* + * Registers, absolute data space addresses + */ + +#define X 0x001a +#define XL 0x001a +#define XH 0x001b +#define Y 0x001c +#define YL 0x001c +#define YH 0x001d +#define Z 0x001e +#define ZL 0x001e +#define ZH 0x001f + +#define ADCL 0x0024 +#define ADCH 0x0025 +#define ADCSR 0x0026 +#define ADMUX 0x0027 +#define ACSR 0x0028 +#define UBRR 0x0029 +#define UCR 0x002A +#define USR 0x002B +#define UDR 0x002C +#define SPCR 0x002D +#define SPSR 0x002E +#define SPDR 0x002F +#define PIND 0x0030 +#define DDRD 0x0031 +#define PORTD 0x0032 +#define PINC 0x0033 +#define DDRC 0x0034 +#define PORTC 0x0035 +#define PINB 0x0036 +#define DDRB 0x0037 +#define PORTB 0x0038 +#define PINA 0x0039 +#define DDRA 0x003A +#define PORTA 0x003B +#define EECR 0x003C +#define EEDR 0x003D +#define EEARL 0x003E +#define EEARH 0x003E +#define WDTCR 0x0041 +#define ASSR 0x0042 +#define OCR2 0x0043 +#define TCNT2 0x0044 +#define TCCR2 0x0045 +#define ICR1L 0x0046 +#define ICR1H 0x0047 +#define OCR1BL 0x0048 +#define OCR1BH 0x0049 +#define OCR1AL 0x004A +#define OCR1AH 0x004B +#define TCNT1L 0x004C +#define TCNT1H 0x004D +#define TCCR1B 0x004E +#define TCCR1A 0x004F +#define TCNT0 0x0052 +#define TCCR0 0x0053 +#define MCUSR 0x0054 +#define MCUCR 0x0055 +#define TIFR 0x0058 +#define TIMSK 0x0059 +#define GIFR 0x005A +#define GIMSK 0x005B +#define SPL 0x005D +#define SPH 0x005E +#define SREG 0x005F + +/* Bits of SREG */ +#define BIT_I 0x80 +#define BIT_T 0x40 +#define BIT_H 0x20 +#define BIT_S 0x10 +#define BIT_V 0x08 +#define BIT_N 0x04 +#define BIT_Z 0x02 +#define BIT_C 0x01 + + +#endif + +/* End of avr.src/regsavr.h */ diff --git a/sim/ucsim/avr.src/savr.cc b/sim/ucsim/avr.src/savr.cc new file mode 100644 index 00000000..f092b65d --- /dev/null +++ b/sim/ucsim/avr.src/savr.cc @@ -0,0 +1,46 @@ +/* + * Simulator of microcontrollers (savr.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include + +#include "globals.h" + +#include "simavrcl.h" + + +int +main(int argc, char *argv[]) +{ + simulator= new cl_simavr(0, argc, argv); + simulator->init(); + simulator->main(); + delete simulator; + return(0); +} + + +/* End of avr.src/savr.cc */ diff --git a/sim/ucsim/avr.src/simavr.cc b/sim/ucsim/avr.src/simavr.cc new file mode 100644 index 00000000..b125f7d6 --- /dev/null +++ b/sim/ucsim/avr.src/simavr.cc @@ -0,0 +1,44 @@ +/* + * Simulator of microcontrollers (simavr.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + + +#include "simavrcl.h" +#include "avrcl.h" + + +cl_simavr::cl_simavr(char *more_args, int iargc, char *iargv[]): + cl_sim(more_args, iargc, iargv) +{} + +class cl_uc * +cl_simavr::mk_controller(void) +{ + return(new cl_avr(this)); +} + + +/* End of avr.src/simavr.cc */ diff --git a/sim/ucsim/avr.src/simavrcl.h b/sim/ucsim/avr.src/simavrcl.h new file mode 100644 index 00000000..b7e2af78 --- /dev/null +++ b/sim/ucsim/avr.src/simavrcl.h @@ -0,0 +1,45 @@ +/* + * Simulator of microcontrollers (simavrcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SIMAVRCL_HEADER +#define SIMAVRCL_HEADER + +#include "simcl.h" + + +class cl_simavr: public cl_sim +{ +public: + cl_simavr(char *more_args, int iargc, char *iargv[]); + + virtual class cl_uc *mk_controller(void); +}; + + +#endif + +/* End of avr.src/simavrcl.h */ diff --git a/sim/ucsim/avr.src/test_arith.asm b/sim/ucsim/avr.src/test_arith.asm new file mode 100644 index 00000000..cb097af5 --- /dev/null +++ b/sim/ucsim/avr.src/test_arith.asm @@ -0,0 +1,81 @@ + nop + clr r0 + out $3f,r0 + +; jmp t2 + + ldi r16,$12 + mov r2,r16 + inc r16 + inc r2 + ldi r17,$ff + inc r17 + ldi r18,$7f + inc r18 + nop +t1: + ldi r16,10 ; 10+20 + ldi r17,20 + add r16,r17 + in r0,$3f + mov r18,r16 + ldi r16,127 ; 127+10 + ldi r17,10 + add r16,r17 + in r1,$3f + mov r19,r16 + ldi r16,255 ; 255+2 + ldi r17,2 + add r16,r17 + in r2,$3f + mov r20,r16 + ldi r16,255 ; 255+1 + ldi r17,1 + add r16,r17 + in r3,$3f + mov r21,r16 + ldi r16,10 ; 10+6 + ldi r17,6 + add r16,r17 + in r4,$3f + mov r22,r16 + nop + ldi r16,-10 ; -10-20 + ldi r17,-20 + add r16,r17 + in r5,$3f + mov r23,r16 + ldi r16,-120 ; -120-30 + ldi r17,-30 + add r16,r17 + in r6,$3f + mov r24,r16 + nop + ldi r16,254 ; 254+1 +0 + ldi r17,1 + clc + adc r16,r17 + in r7,$3f + mov r25,r16 + ldi r16,254 ; 254+1 +1 + sec + adc r16,r17 + in r8,$3f + mov r26,r16 + nop +t2: + ldi r24,0 + ldi r25,0 + adiw r24,20 + ldi r26,low($0fff) + ldi r27,high($0fff) + adiw r26,2 + ldi r28,low($fff0) + ldi r29,high($fff0) + adiw r28,$f + adiw r28,1 +done: + jmp done + +copyright: + .db "(c) 2000 Talker Bt." diff --git a/sim/ucsim/avr.src/test_arith.asm.lst b/sim/ucsim/avr.src/test_arith.asm.lst new file mode 100644 index 00000000..963db2bd --- /dev/null +++ b/sim/ucsim/avr.src/test_arith.asm.lst @@ -0,0 +1,106 @@ +Toms AVR macro assembler version 1.11 (Dec 13 1999) +Copyright (C) 1999 - Tom Mortensen +E-mail: tomo@image.dk WWW: http://www.image.dk/~tomo + ++------------------+-----------------------------------------------------------+ +| Value | Text | +|------------------|-----------------------------------------------------------| +| 000000 0000 | nop | +| 000001 2400 | clr r0 | +| 000002 BE0F | out $3f,r0 | +| | | +| | ; jmp t2 | +| | | +| 000003 E102 | ldi r16,$12 | +| 000004 2E20 | mov r2,r16 | +| 000005 9503 | inc r16 | +| 000006 9423 | inc r2 | +| 000007 EF1F | ldi r17,$ff | +| 000008 9513 | inc r17 | +| 000009 E72F | ldi r18,$7f | +| 00000A 9523 | inc r18 | +| 00000B 0000 | nop | +| | t1: | +| 00000C E00A | ldi r16,10 ; 10+20 | +| 00000D E114 | ldi r17,20 | +| 00000E 0F01 | add r16,r17 | +| 00000F B60F | in r0,$3f | +| 000010 2F20 | mov r18,r16 | +| 000011 E70F | ldi r16,127 ; 127+10 | +| 000012 E01A | ldi r17,10 | +| 000013 0F01 | add r16,r17 | +| 000014 B61F | in r1,$3f | +| 000015 2F30 | mov r19,r16 | +| 000016 EF0F | ldi r16,255 ; 255+2 | +| 000017 E012 | ldi r17,2 | +| 000018 0F01 | add r16,r17 | +| 000019 B62F | in r2,$3f | +| 00001A 2F40 | mov r20,r16 | +| 00001B EF0F | ldi r16,255 ; 255+1 | +| 00001C E011 | ldi r17,1 | +| 00001D 0F01 | add r16,r17 | +| 00001E B63F | in r3,$3f | +| 00001F 2F50 | mov r21,r16 | +| 000020 E00A | ldi r16,10 ; 10+6 | +| 000021 E016 | ldi r17,6 | +| 000022 0F01 | add r16,r17 | +| 000023 B64F | in r4,$3f | +| 000024 2F60 | mov r22,r16 | +| 000025 0000 | nop | +test_arith.asm:43: Warning : Constant 0xFFFFFFF6 out of range (0x00-0xFF) +| 000026 EF06 | ldi r16,-10 ; -10-20 | +test_arith.asm:44: Warning : Constant 0xFFFFFFEC out of range (0x00-0xFF) +| 000027 EE1C | ldi r17,-20 | +| 000028 0F01 | add r16,r17 | +| 000029 B65F | in r5,$3f | +| 00002A 2F70 | mov r23,r16 | +test_arith.asm:48: Warning : Constant 0xFFFFFF88 out of range (0x00-0xFF) +| 00002B E808 | ldi r16,-120 ; -120-30 | +test_arith.asm:49: Warning : Constant 0xFFFFFFE2 out of range (0x00-0xFF) +| 00002C EE12 | ldi r17,-30 | +| 00002D 0F01 | add r16,r17 | +| 00002E B66F | in r6,$3f | +| 00002F 2F80 | mov r24,r16 | +| 000030 0000 | nop | +| 000031 EF0E | ldi r16,254 ; 254+1 +0 | +| 000032 E011 | ldi r17,1 | +| 000033 9488 | clc | +| 000034 1F01 | adc r16,r17 | +| 000035 B67F | in r7,$3f | +| 000036 2F90 | mov r25,r16 | +| 000037 EF0E | ldi r16,254 ; 254+1 +1 | +| 000038 9408 | sec | +| 000039 1F01 | adc r16,r17 | +| 00003A B68F | in r8,$3f | +| 00003B 2FA0 | mov r26,r16 | +| 00003C 0000 | nop | +| | t2: | +| 00003D E080 | ldi r24,0 | +| 00003E E090 | ldi r25,0 | +| 00003F 9644 | adiw r24,20 | +| 000040 EFAF | ldi r26,low($0fff) | +| 000041 E0BF | ldi r27,high($0fff) | +| 000042 9612 | adiw r26,2 | +| 000043 EFC0 | ldi r28,low($fff0) | +| 000044 EFDF | ldi r29,high($fff0) | +| 000045 962F | adiw r28,$f | +| 000046 9621 | adiw r28,1 | +| | done: | +| 000047 940C 0047 | jmp done | +| | | +| | copyright: | +| 000049 2863 2920 | .db "(c) 2000 Talker Bt." | +| 00004B 3230 3030 | | +| 00004D 2054 616C | | +| 00004F 6B65 7220 | | +| 000051 4274 2E00 | | +| | | ++------------------+-----------------------------------------------------------+ + +Errors : 0 +Warnings : 4 +Code : 83 +Rom : 0 +Data : 0 +Unused Code : 0 +Unused Rom : 0 diff --git a/sim/ucsim/avr.src/test_arith.hex b/sim/ucsim/avr.src/test_arith.hex new file mode 100644 index 00000000..3767427c --- /dev/null +++ b/sim/ucsim/avr.src/test_arith.hex @@ -0,0 +1,13 @@ +:020000020000FC +:10000000000000240FBE02E1202E039523941FEF71 +:1000100013952FE7239500000AE014E1010F0FB6B6 +:10002000202F0FE71AE0010F1FB6302F0FEF12E05D +:10003000010F2FB6402F0FEF11E0010F3FB6502FE9 +:100040000AE016E0010F4FB6602F000006EF1CEE2D +:10005000010F5FB6702F08E812EE010F6FB6802F08 +:1000600000000EEF11E08894011F7FB6902F0EEF75 +:100070000894011F8FB6A02F000080E090E0449606 +:10008000AFEFBFE01296C0EFDFEF2F9621960C94F2 +:10009000470028632920323030302054616C6B6572 +:0600A000722042742E00E4 +:00000001FF diff --git a/sim/ucsim/avr.src/test_bit.asm b/sim/ucsim/avr.src/test_bit.asm new file mode 100644 index 00000000..687e5393 --- /dev/null +++ b/sim/ucsim/avr.src/test_bit.asm @@ -0,0 +1,87 @@ + jmp t11 + + ldi r17,0 + sbi 0,0 + sbis 0,0 + ldi r17,1 + cbi 0,0 + sbis 0,0 + ldi r17,2 + nop + + ldi r17,0 + cbi 0,0 + sbic 0,0 + ldi r17,1 + sbi 0,0 + sbic 0,0 + ldi r17,2 + nop + + clr r0 + out $3f,r0 + + sec + sen + sez + sei + ses + sev + set + seh + + ;ld sreg,$ff + + clc + cln + clz + cli + cls + clv + clt + clh + + nop + + sbi 0,0 + sbi 0,1 + sbi 0,2 + sbi 0,3 + sbi 0,4 + sbi 0,5 + sbi 0,6 + sbi 0,7 + nop + sbi $10,4 + sbi $1f,7 + nop + cbi 0,0 + cbi 0,1 + cbi 0,2 + cbi 0,3 + cbi 0,4 + cbi 0,5 + cbi 0,6 + cbi 0,7 +t1: + ldi r16,$55 + bst r16,0 + bst r16,1 + bst r16,2 + bst r16,3 + bst r16,4 + bst r16,5 + bst r16,6 + bst r16,7 +t11: + ldi r16,0 + set + bld r16,0 + ldi r16,1 + clt + bld r16,0 + + nop + +copyright: + .db "(c) 1999,2000 Talker Bt." diff --git a/sim/ucsim/avr.src/test_bit.asm.lst b/sim/ucsim/avr.src/test_bit.asm.lst new file mode 100644 index 00000000..6c089da1 --- /dev/null +++ b/sim/ucsim/avr.src/test_bit.asm.lst @@ -0,0 +1,109 @@ +Toms AVR macro assembler version 1.11 (Dec 13 1999) +Copyright (C) 1999 - Tom Mortensen +E-mail: tomo@image.dk WWW: http://www.image.dk/~tomo + ++------------------+-----------------------------------------------------------+ +| Value | Text | +|------------------|-----------------------------------------------------------| +| 000000 940C 0042 | jmp t11 | +| | | +| 000002 E010 | ldi r17,0 | +| 000003 9A00 | sbi 0,0 | +| 000004 9B00 | sbis 0,0 | +| 000005 E011 | ldi r17,1 | +| 000006 9800 | cbi 0,0 | +| 000007 9B00 | sbis 0,0 | +| 000008 E012 | ldi r17,2 | +| 000009 0000 | nop | +| | | +| 00000A E010 | ldi r17,0 | +| 00000B 9800 | cbi 0,0 | +| 00000C 9900 | sbic 0,0 | +| 00000D E011 | ldi r17,1 | +| 00000E 9A00 | sbi 0,0 | +| 00000F 9900 | sbic 0,0 | +| 000010 E012 | ldi r17,2 | +| 000011 0000 | nop | +| | | +| 000012 2400 | clr r0 | +| 000013 BE0F | out $3f,r0 | +| | | +| 000014 9408 | sec | +| 000015 9428 | sen | +| 000016 9418 | sez | +| 000017 9478 | sei | +| 000018 9448 | ses | +| 000019 9438 | sev | +| 00001A 9468 | set | +| 00001B 9458 | seh | +| | | +| | ;ld sreg,$ff | +| | | +| 00001C 9488 | clc | +| 00001D 94A8 | cln | +| 00001E 9498 | clz | +| 00001F 94F8 | cli | +| 000020 94C8 | cls | +| 000021 94B8 | clv | +| 000022 94E8 | clt | +| 000023 94D8 | clh | +| | | +| 000024 0000 | nop | +| | | +| 000025 9A00 | sbi 0,0 | +| 000026 9A01 | sbi 0,1 | +| 000027 9A02 | sbi 0,2 | +| 000028 9A03 | sbi 0,3 | +| 000029 9A04 | sbi 0,4 | +| 00002A 9A05 | sbi 0,5 | +| 00002B 9A06 | sbi 0,6 | +| 00002C 9A07 | sbi 0,7 | +| 00002D 0000 | nop | +| 00002E 9A84 | sbi $10,4 | +| 00002F 9AFF | sbi $1f,7 | +| 000030 0000 | nop | +| 000031 9800 | cbi 0,0 | +| 000032 9801 | cbi 0,1 | +| 000033 9802 | cbi 0,2 | +| 000034 9803 | cbi 0,3 | +| 000035 9804 | cbi 0,4 | +| 000036 9805 | cbi 0,5 | +| 000037 9806 | cbi 0,6 | +| 000038 9807 | cbi 0,7 | +| | t1: | +| 000039 E505 | ldi r16,$55 | +| 00003A FB00 | bst r16,0 | +| 00003B FB01 | bst r16,1 | +| 00003C FB02 | bst r16,2 | +| 00003D FB03 | bst r16,3 | +| 00003E FB04 | bst r16,4 | +| 00003F FB05 | bst r16,5 | +| 000040 FB06 | bst r16,6 | +| 000041 FB07 | bst r16,7 | +| | t11: | +| 000042 E000 | ldi r16,0 | +| 000043 9468 | set | +| 000044 F900 | bld r16,0 | +| 000045 E001 | ldi r16,1 | +| 000046 94E8 | clt | +| 000047 F900 | bld r16,0 | +| | | +| 000048 0000 | nop | +| | | +| | copyright: | +| 000049 2863 2920 | .db "(c) 1999,2000 Talker Bt." | +| 00004B 3139 3939 | | +| 00004D 2C32 3030 | | +| 00004F 3020 5461 | | +| 000051 6C6B 6572 | | +| 000053 2042 742E | | +| | | ++------------------+-----------------------------------------------------------+ + +Errors : 0 +Warnings : 0 +Code : 85 +Rom : 0 +Data : 0 +Unused Code : 0 +Unused Rom : 0 diff --git a/sim/ucsim/avr.src/test_bit.hex b/sim/ucsim/avr.src/test_bit.hex new file mode 100644 index 00000000..8a553ed0 --- /dev/null +++ b/sim/ucsim/avr.src/test_bit.hex @@ -0,0 +1,13 @@ +:020000020000FC +:100000000C94420010E0009A009B11E00098009BC5 +:1000100012E0000010E00098009911E0009A0099A9 +:1000200012E0000000240FBE0894289418947894DD +:1000300048943894689458948894A8949894F89420 +:10004000C894B894E894D8940000009A019A029A4F +:10005000039A049A059A069A079A0000849AFF9ACE +:100060000000009801980298039804980598069853 +:10007000079805E500FB01FB02FB03FB04FB05FB06 +:1000800006FB07FB00E0689400F901E0E89400F942 +:10009000000028632920313939392C3230303020A2 +:0A00A00054616C6B65722042742EEF +:00000001FF diff --git a/sim/ucsim/avr.src/test_bit.lst b/sim/ucsim/avr.src/test_bit.lst new file mode 100644 index 00000000..1e51b313 --- /dev/null +++ b/sim/ucsim/avr.src/test_bit.lst @@ -0,0 +1,82 @@ +Toms AVR macro assembler version 1.08 (Dec 11 1999) +Copyright (C) 1999 - Tom Mortensen +E-mail: tomo@image.dk WWW: http://www.image.dk/~tomo + ++------------------+-----------------------------------------------------------+ +| Value | Text | +|------------------|-----------------------------------------------------------| +| 000000 E010 | ldi r17,0 +| 000001 9A00 | sbi 0,0 +| 000002 9B00 | sbis 0,0 +| 000003 E011 | ldi r17,1 +| 000004 9800 | cbi 0,0 +| 000005 9B00 | sbis 0,0 +| 000006 E012 | ldi r17,2 +| 000007 0000 | nop +| | +| 000008 E010 | ldi r17,0 +| 000009 9800 | cbi 0,0 +| 00000A 9900 | sbic 0,0 +| 00000B E011 | ldi r17,1 +| 00000C 9A00 | sbi 0,0 +| 00000D 9900 | sbic 0,0 +| 00000E E012 | ldi r17,2 +| 00000F 0000 | nop +| | +| 000010 2400 | clr r0 +| 000011 BE0F | out $3f,r0 +| | +| 000012 9408 | sec +| 000013 9428 | sen +| 000014 9418 | sez +| 000015 9478 | sei +| 000016 9448 | ses +| 000017 9438 | sev +| 000018 9468 | set +| 000019 9458 | seh +| | +| | ;ld sreg,$ff +| | +| 00001A 9488 | clc +| 00001B 94A8 | cln +| 00001C 9498 | clz +| 00001D 94F8 | cli +| 00001E 94C8 | cls +| 00001F 94B8 | clv +| 000020 94E8 | clt +| 000021 94D8 | clh +| | +| 000022 0000 | nop +| | +| 000023 9A00 | sbi 0,0 +| 000024 9A01 | sbi 0,1 +| 000025 9A02 | sbi 0,2 +| 000026 9A03 | sbi 0,3 +| 000027 9A04 | sbi 0,4 +| 000028 9A05 | sbi 0,5 +| 000029 9A06 | sbi 0,6 +| 00002A 9A07 | sbi 0,7 +| 00002B 0000 | nop +| 00002C 9A84 | sbi $10,4 +| 00002D 9AFF | sbi $1f,7 +| 00002E 0000 | nop +| 00002F 9800 | cbi 0,0 +| 000030 9801 | cbi 0,1 +| 000031 9802 | cbi 0,2 +| 000032 9803 | cbi 0,3 +| 000033 9804 | cbi 0,4 +| 000034 9805 | cbi 0,5 +| 000035 9806 | cbi 0,6 +| 000036 9807 | cbi 0,7 +| | +| 000037 0000 | nop +| | ++------------------+-----------------------------------------------------------+ + +Errors : 0 +Warnings : 0 +Code : 56 +Rom : 0 +Data : 0 +Unused Code : 0 +Unused Rom : 0 diff --git a/sim/ucsim/avr.src/test_dis.asm b/sim/ucsim/avr.src/test_dis.asm new file mode 100644 index 00000000..71fd6213 --- /dev/null +++ b/sim/ucsim/avr.src/test_dis.asm @@ -0,0 +1,167 @@ + nop + + adc r1,r31 + add r2,r30 + adiw r24,54 + and r4,r29 + andi r16,253 + asr r5 + bclr 7 + bld r6,6 +lab1: nop + brbc 0,lab1 + brbc 1,lab1 + brbc 2,lab1 + brbc 3,lab1 + brbc 4,lab1 + brbc 5,lab1 + brbc 6,lab1 + brbc 7,lab1 +lab2: brbs 0,lab3 + brbs 1,lab3 + brbs 2,lab3 + brbs 3,lab3 + brbs 4,lab3 + brbs 5,lab3 + brbs 6,lab3 + brbs 7,lab3 +lab3: brcc lab4 + brcc lab3 +lab4: brcs lab5 + brcs lab4 +lab5: breq lab6 + breq lab5 +lab6: brge lab7 + brge lab6 +lab7: brhc lab8 + brhc lab7 +lab8: brhs lab9 + brhs lab8 +lab9: brid lab10 + brid lab9 +lab10: brie lab11 + brie lab10 +lab11: brlo lab12 + brlo lab11 +lab12: brlt lab13 + brlt lab12 +lab13: brmi lab14 + brmi lab13 +lab14: brne lab15 + brne lab14 +lab15: brpl lab16 + brpl lab15 +lab16: brsh lab17 + brsh lab16 +lab17: brtc lab18 + brtc lab17 +lab18: brts lab19 + brts lab18 +lab19: brvc lab20 + brvc lab19 +lab20: brvs lab21 + brvs lab20 +lab21: bset 6 + bst r7,5 + call 0 + call lab1 + call lab22 + nop +lab22: cbi $8,4 + + clc + clh + cli + cln + cls + clt + clv + clz + + com r9 + cp r10,r11 + cpc r12,r13 + cpi r16,95 + cpse r14,r15 + dec r17 + eor r18,r19 + icall + ijmp + in r20,9 + inc r21 + jmp lab1 + jmp lab23 + ld r22,x + ld r23,x+ + ld r24,-x + ld r25,y + ld r26,y+ + ld r27,-y + ldd r28,y+63 + ld r29,z + ld r30,z+ + ld r31,-z + ldd r0,z+1 + ldi r17,170 + lds r1,12345 + lpm + ;elpm + lsr r2 + mov r3,r4 + mul r5,r6 + neg r7 + or r8,r9 + ori r18,85 + out 9,r10 + pop r11 + push r12 + rcall lab1 + rcall lab23 + nop +lab23: ret + reti + rjmp lab23 + rjmp lab24 + nop +lab24: ror r13 + sbc r14,r15 + sbci r19,83 + sbi 10,2 + sbic 11,3 + sbis 12,4 + sbiw r26,60 + sbr r19,254 + sbrc r20,5 + sbrs r21,6 + sec + seh + sei + sen + ses + set + sev + sez + + ser r22 + sleep + st x,r23 + st x+,r24 + st -x,r25 + st y,r26 + st y+,r27 + st -y,r28 + std y+34,r29 + st z,r30 + st z+,r31 + st -z,r0 + st z+35,r1 + sts $ff00,r2 + sub r3,r4 + subi r31,123 + swap r4 + wdr + + nop +a: jmp a + + .db "(c) 1999 Talker Bt." diff --git a/sim/ucsim/avr.src/test_dis.asm.lst b/sim/ucsim/avr.src/test_dis.asm.lst new file mode 100644 index 00000000..d5cea575 --- /dev/null +++ b/sim/ucsim/avr.src/test_dis.asm.lst @@ -0,0 +1,188 @@ +Toms AVR macro assembler version 1.11 (Dec 13 1999) +Copyright (C) 1999 - Tom Mortensen +E-mail: tomo@image.dk WWW: http://www.image.dk/~tomo + ++------------------+-----------------------------------------------------------+ +| Value | Text | +|------------------|-----------------------------------------------------------| +| 000000 0000 | nop | +| | | +| 000001 1E1F | adc r1,r31 | +| 000002 0E2E | add r2,r30 | +| 000003 96C6 | adiw r24,54 | +| 000004 224D | and r4,r29 | +| 000005 7F0D | andi r16,253 | +| 000006 9455 | asr r5 | +| 000007 94F8 | bclr 7 | +| 000008 F866 | bld r6,6 | +| 000009 0000 | lab1: nop | +| 00000A F7F0 | brbc 0,lab1 | +| 00000B F7E9 | brbc 1,lab1 | +| 00000C F7E2 | brbc 2,lab1 | +| 00000D F7DB | brbc 3,lab1 | +| 00000E F7D4 | brbc 4,lab1 | +| 00000F F7CD | brbc 5,lab1 | +| 000010 F7C6 | brbc 6,lab1 | +| 000011 F7BF | brbc 7,lab1 | +| 000012 F038 | lab2: brbs 0,lab3 | +| 000013 F031 | brbs 1,lab3 | +| 000014 F02A | brbs 2,lab3 | +| 000015 F023 | brbs 3,lab3 | +| 000016 F01C | brbs 4,lab3 | +| 000017 F015 | brbs 5,lab3 | +| 000018 F00E | brbs 6,lab3 | +| 000019 F007 | brbs 7,lab3 | +| 00001A F408 | lab3: brcc lab4 | +| 00001B F7F0 | brcc lab3 | +| 00001C F008 | lab4: brcs lab5 | +| 00001D F3F0 | brcs lab4 | +| 00001E F009 | lab5: breq lab6 | +| 00001F F3F1 | breq lab5 | +| 000020 F40C | lab6: brge lab7 | +| 000021 F7F4 | brge lab6 | +| 000022 F40D | lab7: brhc lab8 | +| 000023 F7F5 | brhc lab7 | +| 000024 F00D | lab8: brhs lab9 | +| 000025 F3F5 | brhs lab8 | +| 000026 F40F | lab9: brid lab10 | +| 000027 F7F7 | brid lab9 | +| 000028 F00F | lab10: brie lab11 | +| 000029 F3F7 | brie lab10 | +| 00002A F008 | lab11: brlo lab12 | +| 00002B F3F0 | brlo lab11 | +| 00002C F00C | lab12: brlt lab13 | +| 00002D F3F4 | brlt lab12 | +| 00002E F00A | lab13: brmi lab14 | +| 00002F F3F2 | brmi lab13 | +| 000030 F409 | lab14: brne lab15 | +| 000031 F7F1 | brne lab14 | +| 000032 F40A | lab15: brpl lab16 | +| 000033 F7F2 | brpl lab15 | +| 000034 F408 | lab16: brsh lab17 | +| 000035 F7F0 | brsh lab16 | +| 000036 F40E | lab17: brtc lab18 | +| 000037 F7F6 | brtc lab17 | +| 000038 F00E | lab18: brts lab19 | +| 000039 F3F6 | brts lab18 | +| 00003A F40B | lab19: brvc lab20 | +| 00003B F7F3 | brvc lab19 | +| 00003C F00B | lab20: brvs lab21 | +| 00003D F3F3 | brvs lab20 | +| 00003E 9468 | lab21: bset 6 | +| 00003F FA75 | bst r7,5 | +| 000040 940E 0000 | call 0 | +| 000042 940E 0009 | call lab1 | +| 000044 940E 0047 | call lab22 | +| 000046 0000 | nop | +| 000047 9844 | lab22: cbi $8,4 | +| | | +| 000048 9488 | clc | +| 000049 94D8 | clh | +| 00004A 94F8 | cli | +| 00004B 94A8 | cln | +| 00004C 94C8 | cls | +| 00004D 94E8 | clt | +| 00004E 94B8 | clv | +| 00004F 9498 | clz | +| | | +| 000050 9490 | com r9 | +| 000051 14AB | cp r10,r11 | +| 000052 04CD | cpc r12,r13 | +| 000053 350F | cpi r16,95 | +| 000054 10EF | cpse r14,r15 | +| 000055 951A | dec r17 | +| 000056 2723 | eor r18,r19 | +| 000057 9509 | icall | +| 000058 9409 | ijmp | +| 000059 B149 | in r20,9 | +| 00005A 9553 | inc r21 | +| 00005B 940C 0009 | jmp lab1 | +| 00005D 940C 007A | jmp lab23 | +| 00005F 916C | ld r22,x | +| 000060 917D | ld r23,x+ | +| 000061 918E | ld r24,-x | +| 000062 8198 | ld r25,y | +| 000063 91A9 | ld r26,y+ | +| 000064 91BA | ld r27,-y | +| 000065 ADCF | ldd r28,y+63 | +| 000066 81D0 | ld r29,z | +| 000067 91E1 | ld r30,z+ | +| 000068 91F2 | ld r31,-z | +| 000069 8001 | ldd r0,z+1 | +| 00006A EA1A | ldi r17,170 | +| 00006B 9010 3039 | lds r1,12345 | +| 00006D 95C8 | lpm | +| | ;elpm | +| 00006E 9426 | lsr r2 | +| 00006F 2C34 | mov r3,r4 | +| 000070 9C56 | mul r5,r6 | +| 000071 9471 | neg r7 | +| 000072 2889 | or r8,r9 | +| 000073 6525 | ori r18,85 | +| 000074 B8A9 | out 9,r10 | +| 000075 90BF | pop r11 | +| 000076 92CF | push r12 | +| 000077 DF91 | rcall lab1 | +| 000078 D001 | rcall lab23 | +| 000079 0000 | nop | +| 00007A 9508 | lab23: ret | +| 00007B 9518 | reti | +| 00007C CFFD | rjmp lab23 | +| 00007D C001 | rjmp lab24 | +| 00007E 0000 | nop | +| 00007F 94D7 | lab24: ror r13 | +| 000080 08EF | sbc r14,r15 | +| 000081 4533 | sbci r19,83 | +| 000082 9A52 | sbi 10,2 | +| 000083 995B | sbic 11,3 | +| 000084 9B64 | sbis 12,4 | +| 000085 97DC | sbiw r26,60 | +| 000086 6F3E | sbr r19,254 | +| 000087 FD45 | sbrc r20,5 | +| 000088 FF56 | sbrs r21,6 | +| 000089 9408 | sec | +| 00008A 9458 | seh | +| 00008B 9478 | sei | +| 00008C 9428 | sen | +| 00008D 9448 | ses | +| 00008E 9468 | set | +| 00008F 9438 | sev | +| 000090 9418 | sez | +| | | +| 000091 EF6F | ser r22 | +| 000092 9588 | sleep | +| 000093 937C | st x,r23 | +| 000094 938D | st x+,r24 | +| 000095 939E | st -x,r25 | +| 000096 83A8 | st y,r26 | +| 000097 93B9 | st y+,r27 | +| 000098 93CA | st -y,r28 | +| 000099 A3DA | std y+34,r29 | +| 00009A 83E0 | st z,r30 | +| 00009B 93F1 | st z+,r31 | +| 00009C 9202 | st -z,r0 | +| 00009D A213 | st z+35,r1 | +| 00009E 9220 FF00 | sts $ff00,r2 | +| 0000A0 1834 | sub r3,r4 | +| 0000A1 57FB | subi r31,123 | +| 0000A2 9442 | swap r4 | +| 0000A3 95A8 | wdr | +| | | +| 0000A4 0000 | nop | +| 0000A5 940C 00A5 | a: jmp a | +| | | +| 0000A7 2863 2920 | .db "(c) 1999 Talker Bt." | +| 0000A9 3139 3939 | | +| 0000AB 2054 616C | | +| 0000AD 6B65 7220 | | +| 0000AF 4274 2E00 | | +| | | ++------------------+-----------------------------------------------------------+ + +Errors : 0 +Warnings : 0 +Code : 177 +Rom : 0 +Data : 0 +Unused Code : 0 +Unused Rom : 0 diff --git a/sim/ucsim/avr.src/test_dis.hex b/sim/ucsim/avr.src/test_dis.hex new file mode 100644 index 00000000..f14a2ed0 --- /dev/null +++ b/sim/ucsim/avr.src/test_dis.hex @@ -0,0 +1,25 @@ +:020000020000FC +:1000000000001F1E2E0EC6964D220D7F5594F894AB +:1000100066F80000F0F7E9F7E2F7DBF7D4F7CDF781 +:10002000C6F7BFF738F031F02AF023F01CF015F0D6 +:100030000EF007F008F4F0F708F0F0F309F0F1F330 +:100040000CF4F4F70DF4F5F70DF0F5F30FF4F7F702 +:100050000FF0F7F308F0F0F30CF0F4F30AF0F2F31A +:1000600009F4F1F70AF4F2F708F4F0F70EF4F6F7F2 +:100070000EF0F6F30BF4F3F70BF0F3F3689475FA64 +:100080000E9400000E9409000E944700000044985E +:100090008894D894F894A894C894E894B8949894C0 +:1000A0009094AB14CD040F35EF101A9523270995C2 +:1000B000099449B153950C9409000C947A006C9101 +:1000C0007D918E919881A991BA91CFADD081E19126 +:1000D000F29101801AEA10903930C8952694342C98 +:1000E000569C719489282565A9B8BF90CF9291DF5D +:1000F00001D0000008951895FDCF01C00000D794ED +:10010000EF083345529A5B99649BDC973E6F45FD3F +:1001100056FF089458947894289448946894389496 +:1001200018946FEF88957C938D939E93A883B993D1 +:10013000CA93DAA3E083F193029213A2209200FF04 +:100140003418FB574294A89500000C94A50028632E +:100150002920313939392054616C6B657220427421 +:020160002E006F +:00000001FF diff --git a/sim/ucsim/avr.src/test_dis.obj b/sim/ucsim/avr.src/test_dis.obj new file mode 100644 index 00000000..95d3cee4 Binary files /dev/null and b/sim/ucsim/avr.src/test_dis.obj differ diff --git a/sim/ucsim/avr.src/test_jmp.asm b/sim/ucsim/avr.src/test_jmp.asm new file mode 100644 index 00000000..3b6a1d4c --- /dev/null +++ b/sim/ucsim/avr.src/test_jmp.asm @@ -0,0 +1,62 @@ + nop + jmp skip + nop +skip: + ldi r16,12 + ldi r17,13 + cpse r16,r17 + inc r16 + cpse r16,r17 + inc r16 + inc r16 + nop + nop + ldi r16,0 + sbrc r16,0 + nop + sbrc r16,1 + jmp 0 + sbrs r16,2 + ldi r16,$ff + sbrs r16,7 + nop + sbrs r16,6 + jmp 0 + nop +t0: +; rjmp -$100 + bclr 0 + brbs 0,b0_1 + brbc 0,b0_1 + nop +b2_0: + nop +b1_0: + bclr 1 + brbs 1,b1_1 + brbc 1,b1_1 + nop +b0_1: + bset 0 + brbc 0,b1_0 + brbs 0,b1_0 + nop +b1_1: + bset 1 + brbc 1,b2_0 + brbs 1,b2_0 + nop +t1: + ldi r30,low(t11) + ldi r31,high(t11) + ijmp + nop +t11: + rjmp t2 + nop +t2: + rjmp t0 + nop + +copyright: + .db "(c) 2000 talker Bt." diff --git a/sim/ucsim/avr.src/test_jmp.asm.lst b/sim/ucsim/avr.src/test_jmp.asm.lst new file mode 100644 index 00000000..39dd18c0 --- /dev/null +++ b/sim/ucsim/avr.src/test_jmp.asm.lst @@ -0,0 +1,83 @@ +Toms AVR macro assembler version 1.11 (Dec 13 1999) +Copyright (C) 1999 - Tom Mortensen +E-mail: tomo@image.dk WWW: http://www.image.dk/~tomo + ++------------------+-----------------------------------------------------------+ +| Value | Text | +|------------------|-----------------------------------------------------------| +| 000000 0000 | nop | +| 000001 940C 0004 | jmp skip | +| 000003 0000 | nop | +| | skip: | +| 000004 E00C | ldi r16,12 | +| 000005 E01D | ldi r17,13 | +| 000006 1301 | cpse r16,r17 | +| 000007 9503 | inc r16 | +| 000008 1301 | cpse r16,r17 | +| 000009 9503 | inc r16 | +| 00000A 9503 | inc r16 | +| 00000B 0000 | nop | +| 00000C 0000 | nop | +| 00000D E000 | ldi r16,0 | +| 00000E FD00 | sbrc r16,0 | +| 00000F 0000 | nop | +| 000010 FD01 | sbrc r16,1 | +| 000011 940C 0000 | jmp 0 | +| 000013 FF02 | sbrs r16,2 | +| 000014 EF0F | ldi r16,$ff | +| 000015 FF07 | sbrs r16,7 | +| 000016 0000 | nop | +| 000017 FF06 | sbrs r16,6 | +| 000018 940C 0000 | jmp 0 | +| 00001A 0000 | nop | +| | t0: | +| | ; rjmp -$100 | +| 00001B 9488 | bclr 0 | +| 00001C F038 | brbs 0,b0_1 | +| 00001D F430 | brbc 0,b0_1 | +| 00001E 0000 | nop | +| | b2_0: | +| 00001F 0000 | nop | +| | b1_0: | +| 000020 9498 | bclr 1 | +| 000021 F031 | brbs 1,b1_1 | +| 000022 F429 | brbc 1,b1_1 | +| 000023 0000 | nop | +| | b0_1: | +| 000024 9408 | bset 0 | +| 000025 F7D0 | brbc 0,b1_0 | +| 000026 F3C8 | brbs 0,b1_0 | +| 000027 0000 | nop | +| | b1_1: | +| 000028 9418 | bset 1 | +| 000029 F7A9 | brbc 1,b2_0 | +| 00002A F3A1 | brbs 1,b2_0 | +| 00002B 0000 | nop | +| | t1: | +| 00002C E3E0 | ldi r30,low(t11) | +| 00002D E0F0 | ldi r31,high(t11) | +| 00002E 9409 | ijmp | +| 00002F 0000 | nop | +| | t11: | +| 000030 C001 | rjmp t2 | +| 000031 0000 | nop | +| | t2: | +| 000032 CFE8 | rjmp t0 | +| 000033 0000 | nop | +| | | +| | copyright: | +| 000034 2863 2920 | .db "(c) 2000 talker Bt." | +| 000036 3230 3030 | | +| 000038 2074 616C | | +| 00003A 6B65 7220 | | +| 00003C 4274 2E00 | | +| | | ++------------------+-----------------------------------------------------------+ + +Errors : 0 +Warnings : 0 +Code : 62 +Rom : 0 +Data : 0 +Unused Code : 0 +Unused Rom : 0 diff --git a/sim/ucsim/avr.src/test_jmp.hex b/sim/ucsim/avr.src/test_jmp.hex new file mode 100644 index 00000000..b7662a19 --- /dev/null +++ b/sim/ucsim/avr.src/test_jmp.hex @@ -0,0 +1,10 @@ +:020000020000FC +:1000000000000C94040000000CE01DE001130395B7 +:100010000113039503950000000000E000FD0000BF +:1000200001FD0C94000002FF0FEF07FF000006FF28 +:100030000C9400000000889438F030F400000000B8 +:10004000989431F029F400000894D0F7C8F3000028 +:100050001894A9F7A1F30000E0E3F0E00994000090 +:1000600001C00000E8CF0000286329203230303082 +:0C0070002074616C6B65722042742E00DD +:00000001FF diff --git a/sim/ucsim/avr.src/test_jmp.list b/sim/ucsim/avr.src/test_jmp.list new file mode 100644 index 00000000..744afce1 --- /dev/null +++ b/sim/ucsim/avr.src/test_jmp.list @@ -0,0 +1,20 @@ + +avra ver. 0.2 test_jmp.asm Sun Jan 16 19:07:06 2000 + + +000000 0000 nop +000001 cefe rjmp -$100 +000002 940c 0005 jmp t1 +000004 0000 nop + t1: +000005 c003 rjmp t2 +000006 0000 nop +000007 0000 nop +000008 0000 nop + t2: +000009 cffb rjmp t1 + + copyright: + .db "(c) 2000 talker Bt." + +Assembly complete with no errors. diff --git a/sim/ucsim/avr.src/test_jmp.obj b/sim/ucsim/avr.src/test_jmp.obj new file mode 100644 index 00000000..cc084a3c Binary files /dev/null and b/sim/ucsim/avr.src/test_jmp.obj differ diff --git a/sim/ucsim/avr.src/test_mov.asm b/sim/ucsim/avr.src/test_mov.asm new file mode 100644 index 00000000..315681c2 --- /dev/null +++ b/sim/ucsim/avr.src/test_mov.asm @@ -0,0 +1,93 @@ +;X = 0x001a +;XL = 0x001a +;XH = 0x001b +;Y = 0x001c +;YL = 0x001c +;YH = 0x001d +;Z = 0x001e +;ZL = 0x001e +.equ ZH =$1f + + jmp t42 + + ldi r16,0 + ldi r16,16 + ldi r17,0 + ldi r17,17 + ldi r30,0 + ldi r30,30 + ldi r30,255 +t1: + ldi r30,low(copyright) + ldi r31,high(copyright) + lpm + ldi r30,low(copyright+1) + ldi r31,high(copyright+1) + lpm +t2: + ldi r31,0 + ldi r30,100 + ldi r16,$65 + std z+1,r16 + std z+63,r16 + ldd r1,z+1 + ldd r2,z+63 +t21: + ldi r31,0 + ldi r30,255 + ldi r18,88 + std z,r18 + ld r6,z+ + ld r7,-z +t3: + ldi r29,0 + ldi r28,100 + ldi r17,$45 + std y+2,r17 + std y+62,r17 + ldd r3,y+2 + ldd r4,y+62 +t31: + ldi r29,0 + ldi r28,255 + ldi r19,$55 + std y,r19 + ld r8,y+ + ld r9,-y +t32: + ldi r27,0 + ldi r26,255 + ldi r19,$70 + st x,r19 + ld r20,x + ld r10,x+ + ld r11,-x +t4: + ldi r31,0 + ldi r30,255 + ldi r16,66 + ldi r17,77 + st z+,r16 + st -z,r17 +t41: + ldi r29,0 + ldi r28,255 + ldi r18,88 + ldi r19,99 + st y+,r18 + st -y,r19 +t42: + ldi r27,0 + ldi r26,255 + ldi r20,22 + ldi r21,11 + st x+,r20 + st -x,r21 + + lds r5,162 + sts 161,r5 + + nop + +copyright: + .db "(c) 2000 Talker Bt." diff --git a/sim/ucsim/avr.src/test_mov.asm.lst b/sim/ucsim/avr.src/test_mov.asm.lst new file mode 100644 index 00000000..a2a3d135 --- /dev/null +++ b/sim/ucsim/avr.src/test_mov.asm.lst @@ -0,0 +1,114 @@ +Toms AVR macro assembler version 1.11 (Dec 13 1999) +Copyright (C) 1999 - Tom Mortensen +E-mail: tomo@image.dk WWW: http://www.image.dk/~tomo + ++------------------+-----------------------------------------------------------+ +| Value | Text | +|------------------|-----------------------------------------------------------| +| | ;X = 0x001a | +| | ;XL = 0x001a | +| | ;XH = 0x001b | +| | ;Y = 0x001c | +| | ;YL = 0x001c | +| | ;YH = 0x001d | +| | ;Z = 0x001e | +| | ;ZL = 0x001e | +| | .equ ZH =$1f | +| | | +| 000000 940C 003C | jmp t42 | +| | | +| 000002 E000 | ldi r16,0 | +| 000003 E100 | ldi r16,16 | +| 000004 E010 | ldi r17,0 | +| 000005 E111 | ldi r17,17 | +| 000006 E0E0 | ldi r30,0 | +| 000007 E1EE | ldi r30,30 | +| 000008 EFEF | ldi r30,255 | +| | t1: | +| 000009 E4E7 | ldi r30,low(copyright) | +| 00000A E0F0 | ldi r31,high(copyright) | +| 00000B 95C8 | lpm | +| 00000C E4E8 | ldi r30,low(copyright+1) | +| 00000D E0F0 | ldi r31,high(copyright+1) | +| 00000E 95C8 | lpm | +| | t2: | +| 00000F E0F0 | ldi r31,0 | +| 000010 E6E4 | ldi r30,100 | +| 000011 E605 | ldi r16,$65 | +| 000012 8301 | std z+1,r16 | +| 000013 AF07 | std z+63,r16 | +| 000014 8011 | ldd r1,z+1 | +| 000015 AC27 | ldd r2,z+63 | +| | t21: | +| 000016 E0F0 | ldi r31,0 | +| 000017 EFEF | ldi r30,255 | +| 000018 E528 | ldi r18,88 | +| 000019 8320 | std z,r18 | +| 00001A 9061 | ld r6,z+ | +| 00001B 9072 | ld r7,-z | +| | t3: | +| 00001C E0D0 | ldi r29,0 | +| 00001D E6C4 | ldi r28,100 | +| 00001E E415 | ldi r17,$45 | +| 00001F 831A | std y+2,r17 | +| 000020 AF1E | std y+62,r17 | +| 000021 803A | ldd r3,y+2 | +| 000022 AC4E | ldd r4,y+62 | +| | t31: | +| 000023 E0D0 | ldi r29,0 | +| 000024 EFCF | ldi r28,255 | +| 000025 E535 | ldi r19,$55 | +| 000026 8338 | std y,r19 | +| 000027 9089 | ld r8,y+ | +| 000028 909A | ld r9,-y | +| | t32: | +| 000029 E0B0 | ldi r27,0 | +| 00002A EFAF | ldi r26,255 | +| 00002B E730 | ldi r19,$70 | +| 00002C 933C | st x,r19 | +| 00002D 914C | ld r20,x | +| 00002E 90AD | ld r10,x+ | +| 00002F 90BE | ld r11,-x | +| | t4: | +| 000030 E0F0 | ldi r31,0 | +| 000031 EFEF | ldi r30,255 | +| 000032 E402 | ldi r16,66 | +| 000033 E41D | ldi r17,77 | +| 000034 9301 | st z+,r16 | +| 000035 9312 | st -z,r17 | +| | t41: | +| 000036 E0D0 | ldi r29,0 | +| 000037 EFCF | ldi r28,255 | +| 000038 E528 | ldi r18,88 | +| 000039 E633 | ldi r19,99 | +| 00003A 9329 | st y+,r18 | +| 00003B 933A | st -y,r19 | +| | t42: | +| 00003C E0B0 | ldi r27,0 | +| 00003D EFAF | ldi r26,255 | +| 00003E E146 | ldi r20,22 | +| 00003F E05B | ldi r21,11 | +| 000040 934D | st x+,r20 | +| 000041 935E | st -x,r21 | +| | | +| 000042 9050 00A2 | lds r5,162 | +| 000044 9250 00A1 | sts 161,r5 | +| | | +| 000046 0000 | nop | +| | | +| | copyright: | +| 000047 2863 2920 | .db "(c) 2000 Talker Bt." | +| 000049 3230 3030 | | +| 00004B 2054 616C | | +| 00004D 6B65 7220 | | +| 00004F 4274 2E00 | | +| | | ++------------------+-----------------------------------------------------------+ + +Errors : 0 +Warnings : 0 +Code : 81 +Rom : 0 +Data : 0 +Unused Code : 0 +Unused Rom : 0 diff --git a/sim/ucsim/avr.src/test_mov.hex b/sim/ucsim/avr.src/test_mov.hex new file mode 100644 index 00000000..637c3f85 --- /dev/null +++ b/sim/ucsim/avr.src/test_mov.hex @@ -0,0 +1,13 @@ +:020000020000FC +:100000000C943C0000E000E110E011E1E0E0EEE1E2 +:10001000EFEFE7E4F0E0C895E8E4F0E0C895F0E041 +:10002000E4E605E6018307AF118027ACF0E0EFEFCF +:1000300028E5208361907290D0E0C4E615E41A832D +:100040001EAF3A804EACD0E0CFEF35E538838990D3 +:100050009A90B0E0AFEF30E73C934C91AD90BE90FA +:10006000F0E0EFEF02E41DE401931293D0E0CFEF54 +:1000700028E533E629933A93B0E0AFEF46E15BE041 +:100080004D935E935090A2005092A100000028630F +:100090002920323030302054616C6B6572204274FC +:0200A0002E0030 +:00000001FF diff --git a/sim/ucsim/ddconfig_in.h b/sim/ucsim/ddconfig_in.h new file mode 100644 index 00000000..1b9094bb --- /dev/null +++ b/sim/ucsim/ddconfig_in.h @@ -0,0 +1,99 @@ +/* + * Simulator of microcontrollers (ddconfig.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef DDCONFIG_HEADER +#define DDCONFIG_HEADER + +#define TRUE 1 +#define FALSE 0 +#define bool int + +#undef STDC_HEADERS +#undef HAVE_GETOPT_H +#undef HAVE_UNISTD_H +#undef HAVE_DIRENT_H +#undef HAVE_SYS_NDIR_H +#undef HAVE_SYS_DIR_H +#undef HAVE_SYS_SOCKET_H +#undef HAVE_NDIR_H + +#undef SOCKET_AVAIL + +#undef FD_NEED_TIME_H +#undef FD_NEED_TYPES_H +#undef FD_NEED_SELECT_H +#undef HEADER_FD +#undef FD_HEADER_OK + +#undef SCANF_A +#undef GNU_GETCWD + +#undef HAVE_STRLEN +#undef HAVE_STRCPY +#undef HAVE_STRCAT +#undef HAVE_STRSTR +#undef HAVE_STRCMP +#undef HAVE_STRERROR +#undef HAVE_STRTOK +#undef HAVE_STRDUP +#undef HAVE_STRCHR + +#undef HAVE_MEMCPY + +#undef HAVE_VPRINTF +#undef HAVE_DOPRNT +#undef HAVE_VSNPRINTF +#undef HAVE_VASPRINTF + +#undef HAVE_GETLINE +#undef HAVE_GETDELIM +#undef HAVE_FGETS + +#undef HAVE_YYLEX + +#undef RETSIGTYPE +#undef SIZEOF_CHAR +#undef SIZEOF_SHORT +#undef SIZEOF_INT +#undef SIZEOF_LONG +#undef SIZEOF_LONG_LONG +#undef TYPE_BYTE +#undef TYPE_WORD +#undef TYPE_DWORD +#define TYPE_UBYTE unsigned TYPE_BYTE +#define TYPE_UWORD unsigned TYPE_WORD +#define TYPE_UDWORD unsigned TYPE_DWORD +#undef WORDS_BIGENDIAN + +#undef VERSIONSTR +#undef VERSIONHI +#undef VERSIONLO +#undef VERSIONP + +#endif + +/* End of ddconfig.h */ diff --git a/sim/ucsim/globals.cc b/sim/ucsim/globals.cc new file mode 100644 index 00000000..eb10f8fb --- /dev/null +++ b/sim/ucsim/globals.cc @@ -0,0 +1,58 @@ +/* + * Simulator of microcontrollers (globals.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include + +#include "stypes.h" + + +// No other global variable should exists! +class cl_sim *simulator; + + +/* Delimiters to split up command line */ +char delimiters[]= " ,;\t\r\n"; + +struct id_element mem_ids[]= { + { MEM_ROM , "ROM " }, + { MEM_XRAM, "XRAM" }, + { MEM_IRAM, "IRAM" }, + { MEM_SFR , "SFR " }, + { 0, 0 } +}; + +struct id_element cpu_states[]= { + { stGO, "OK" }, + { stIDLE, "Idle" }, + { stPD, "PowerDown" }, + { 0, 0 } +}; + + +/* End of globals.cc */ diff --git a/sim/ucsim/globals.h b/sim/ucsim/globals.h new file mode 100644 index 00000000..f5e106d1 --- /dev/null +++ b/sim/ucsim/globals.h @@ -0,0 +1,46 @@ +/* + * Simulator of microcontrollers (globals.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef GLOBALS_HEADER +#define GLOBALS_HEADER + +#include "ddconfig.h" + +#include "stypes.h" + + +extern class cl_sim *simulator; + +extern char delimiters[]; + +extern struct id_element mem_ids[]; +extern struct id_element cpu_states[]; + + +#endif + +/* End of globals.h */ diff --git a/sim/ucsim/i_string.h b/sim/ucsim/i_string.h new file mode 100644 index 00000000..d0f96648 --- /dev/null +++ b/sim/ucsim/i_string.h @@ -0,0 +1,49 @@ +/* + * Simulator of microcontrollers (i_string.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef I_STRING_HEADER +#define I_STRING_HEADER + +#include "ddconfig.h" + +#if STDC_HEADERS +# include +#else +# ifndef HAVE_STRCHR +# define strchr index +# define strrchr rindex +# endif +char *strchr (), *strrchr (); +# ifndef HAVE_MEMCPY +# define memcpy(d, s, n) bcopy ((s), (d), (n)) +# define memmove(d, s, n) bcopy ((s), (d), (n)) +# endif +#endif + +#endif + +/* End of i_string.h */ diff --git a/sim/ucsim/pobj.cc b/sim/ucsim/pobj.cc new file mode 100644 index 00000000..ae9e850b --- /dev/null +++ b/sim/ucsim/pobj.cc @@ -0,0 +1,602 @@ +/* + * Simulator of microcontrollers (pobj.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include +#include + +#include "pstr.h" +/*#include "pobjt.h"*/ +#include "pobjcl.h" + + +/* * + ==========================================================================* + cl_base * + ==========================================================================* + * +*/ + +/* + * Initializing the object + */ + +cl_base::cl_base(void) {} + + +/* + * Destructing the object: calling hte virtual Done method + */ + +cl_base::~cl_base(void) {} + + +int cl_base::init(void) {return(0);} + + +/* * + ==========================================================================* + cl_list * + ==========================================================================* + * +*/ + +/* + * Initializing a collection + */ + +cl_list::cl_list(t_index alimit, t_index adelta): + cl_base() +{ + count= 0; + Items= 0; + Limit= 0; + Delta= adelta; + set_limit(alimit); +} + + +/* + * Disposing object's variables + */ + +cl_list::~cl_list(void) +{ + delete Items; +} + + +/* + * Get indexed item from the collection + */ + +void * +cl_list::at(t_index index) +{ + if (index < 0 || + index >= count) + error(1, index); + return(Items[index]); +} + +/*void * +cl_list::operator[](t_index index) +{ + if (index < 0 || + index >= count) + error(1, 0); + return(Items[index]); +}*/ + + +/* + * Deleting the indexed item from the collection + */ + +void +cl_list::disconn_at(t_index index) +{ + if (index < 0 || + index >= count) + error(1, 0); + count--; + memmove(&Items[index], &Items[index+1], (count-index)*sizeof(void *)); +} + + +/* + * Deleting an item from the collection but not disposing it + */ + +void +cl_list::disconn(void *item) +{ + disconn_at(index_of(item)); +} + + +/* + * Deleting all the items from the collection but not disposing them + */ + +void +cl_list::disconn_all(void) +{ + count= 0; +} + + +/* + * Deleting the indexed item from the collection and disposing it + */ + +void +cl_list::free_at(t_index index) +{ + void *Item= at(index); + + disconn_at(index); + free_item(Item); +} + + +/* + * Inserting a new item to the exact position + */ + +void +cl_list::add_at(t_index index, void *item) +{ + if (index < 0 ) + error(1, 0); + if (count == Limit) + set_limit(count + Delta); + + memmove(&Items[index+1], &Items[index], (count-index)*sizeof(void *)); + count++; + + Items[index]= item; +} + + +/* + * Put a new item to the collection. This function replaces an existing + * item with a new one but it does not delete or dispose the old item! + */ + +void +cl_list::put_at(t_index index, void *item) +{ + if (index >= count) + error(1, 0); + Items[index]= item; +} + + +/* + * Action taken when an error occure + */ + +void +cl_list::error(t_index code, t_index info) +{ + fprintf(stderr, + "Collection index error. Code= %d, Info= %d.\n", + code, info); + exit(code); +} + + +/* + * Iterator method. This function calls 'Test' using every items as Test's + * argument until Test returns TRUE. + */ + +void * +cl_list::first_that(match_func test, void *arg) +{ + for (t_index i= 0; i < count; i++) + { + if (test(Items[i], arg)) return(Items[i]); + } + return(0); +} + + +/* + * Iterator method. This function calls 'Action' using every items as + * Action's argument. + */ + +void +cl_list::for_each(iterator_func action, void *arg) +{ + for(t_index i= 0; i < count; i++) + action(Items[i], arg); +} + + +/* + * Disposing an item. + */ + +void +cl_list::free_item(void *item) +{ + delete item; +} + + +/* + * Get the number of collected items. + */ + +int +cl_list::get_count(void) +{ + return(count); +} + +void * +cl_list::pop(void) +{ + void *i; + + if (!count) + return(0); + i= Items[0]; + disconn_at(0); + return(i); +} + +void * +cl_list::top(void) +{ + if (!count) + return(0); + return(Items[0]); +} + + +/* + * Returning the index of an item. + */ + +t_index +cl_list::index_of(void *item) +{ + for (t_index i= 0; i < count; i++) + if (item == Items[i]) + return(i); + error(1, 0); + return(0); /* Needed by Sun! */ +} + + +/* + * Inserting a new item to the collection. + */ + +t_index +cl_list::add(void *item) +{ + t_index loc= count; + + add_at(count, item); + return(loc); +} + + +void +cl_list::push(void *item) +{ + if (count) + add_at(0, item); + else + add(item); +} + + +/* + * Iterator method. This function calls 'Test' using every items + * (in reversed order) as Test's argument until Test returns TRUE. + */ + +void * +cl_list::last_that(match_func test, void *arg) +{ + for(t_index i= count; i > 0; i--) + if (test(Items[i-1], arg)) + return(Items[i-1]); + return(0); +} + + +/* + * ??? + */ + +/*void +cl_list::pack(void) +{ + void **CurDst= Items; + void **CurSrc= Items; + void **Last = Items + count; + + while (CurSrc < Last) + { + if (*CurSrc != 0) + *CurDst++= *CurSrc; + *CurSrc++; + } +}*/ + + +/* + * Setting up the maximum number of items. This function may expand + * the size of the collection. + */ + +void +cl_list::set_limit(t_index alimit) +{ + void **AItems; + + if (alimit < count) + alimit= count; + if (alimit > (int)max_list_size) + alimit= max_list_size; + if (alimit != Limit) + { + if (alimit == 0) + AItems= 0; + else + { + AItems = new void *[alimit]; + //i= ALimit*(sizeof(void *)); + //AItems= (void **)malloc(i); + if (count) + memcpy(AItems, Items, count*sizeof(void *)); + } + delete Items; + Items= AItems; + Limit= alimit; + } +} + + +/* * + ==========================================================================* + cl_sorted_list * + ==========================================================================* + * +*/ + +/* + * Initilizing the sorted collection + */ + +cl_sorted_list::cl_sorted_list(t_index alimit, t_index adelta): + cl_list(alimit, adelta) +{ + Duplicates= FALSE; +} + + +cl_sorted_list::~cl_sorted_list(void) {} + + +/* + * Get the address of the key field in an item. + */ + +void * +cl_sorted_list::key_of(void *item) +{ + return(item); +} + + +/* + * Get index of an item. + */ + +t_index +cl_sorted_list::index_of(void *item) +{ + t_index i; + + if (search(key_of(item), i) == 0) + return(ccNotFound); + else + { + if (Duplicates) + while (i < count && + item != Items[i]) + i++; + if (i < count) + return(i); + else + return(ccNotFound); + } +} + + +/* + * Inserting a new item to the collection + */ + +t_index +cl_sorted_list::add(void *item) +{ + t_index i; + + if (search(key_of(item), i) == 0 || + Duplicates) // order dependency! + add_at(i, item); // must do Search + // before calling + // AtInsert + return(i); +} + + +/* + * Searching an item using binary search. + */ + +bool +cl_sorted_list::search(void *key, t_index &index) +{ + t_index l = 0; + t_index h = count - 1; + bool res= FALSE; + + while (l <= h) + { + t_index i= (l + h) >> 1; + t_index c= compare(key_of(Items[i]), key); + if (c < 0) l= i + 1; + else + { + h= i - 1; + if (c == 0) + { + res= TRUE; + if (!Duplicates) + l= i; + } + } + } + index= l; + return(res); +} + + +/* * + ==========================================================================* + cl_strings * + ==========================================================================* + * +*/ + +/* + * Initilizing the string collection + */ + +cl_strings::cl_strings(t_index alimit, t_index adelta): + cl_sorted_list(alimit, adelta) +{ + Duplicates= TRUE; +} + + +cl_strings::~cl_strings(void) {} + + +/* + * Comapare two string from the collection + */ + +int +cl_strings::compare(void *key1, void *key2) +{ + return(strcmp((char *)key1, (char *)key2)); +} + + +/* + * Deallocate string item of the collection + */ + +void +cl_strings::free_item(void* item) +{ + delete item; +} + + +/* * + ==========================================================================* + cl_ustrings * + ==========================================================================* + * +*/ + +/* + * Initilizing the unsorted string collection + */ + +cl_ustrings::cl_ustrings(t_index alimit, t_index adelta): + cl_strings(alimit, adelta) +{} + + +cl_ustrings::~cl_ustrings(void) {} + + +/* + * Comapare two string from the collection + */ + +int +cl_ustrings::compare(void *key1, void *key2) +{ + return(-1); +} + + +/* + * Searching an item using linear search. + */ + +bool +cl_ustrings::search(void *key, t_index& index) +{ + t_index i = 0; + bool found= FALSE; + void *Actual; + + if ((count) && key) + { + while (!found && (i < count)) + { + Actual= key_of(at(i)); + found = (Actual != 0) && + (compare(key, Actual) == 0); + i++; + } + } + if (found) + index= i-1; + else + index= count; + + return(found); +} + +/* End of pobj.cc */ diff --git a/sim/ucsim/pobjcl.h b/sim/ucsim/pobjcl.h new file mode 100644 index 00000000..501c53d5 --- /dev/null +++ b/sim/ucsim/pobjcl.h @@ -0,0 +1,166 @@ +/* + * Simulator of microcontrollers (pobjcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef POBJ_HEADER +#define POBJ_HEADER + +#include "ddconfig.h" + +#include "pobjt.h" + + +/* # + ==========================================================================# + cl_base # + ==========================================================================# + # +*/ + +class cl_base +{ +public: + cl_base(void); + virtual ~cl_base(void); + + virtual int init(void); +}; + + +/* # + ==========================================================================# + cl_list # + ==========================================================================# + # +*/ + +class cl_list: public cl_base +{ +public: + t_index count; +protected: + void **Items; + t_index Limit; + t_index Delta; + +public: + cl_list(t_index alimit, t_index adelta); + virtual ~cl_list(void); + + void *at(t_index index); + virtual t_index index_of(void *item); + int get_count(void); + virtual void *pop(void); + virtual void *top(void); + + //void pack(void); + virtual void set_limit(t_index alimit); + + void free_at(t_index index); + void disconn_at(t_index index); + void disconn(void *item); + void disconn_all(void); + + void add_at(t_index index, void *item); + void put_at(t_index index, void *item); + virtual t_index add(void *item); + virtual void push(void *item); + + void *first_that(match_func test, void *arg); + void *last_that(match_func test, void *arg); + void for_each(iterator_func action, void *arg); + + void error(t_index code, t_index info); +private: + virtual void free_item(void *item); +}; + + +/* # + ==========================================================================# + cl_sorted_list # + ==========================================================================# + # +*/ + +class cl_sorted_list: public cl_list +{ +public: + bool Duplicates; + + cl_sorted_list(t_index alimit, t_index adelta); + virtual ~cl_sorted_list(void); + + virtual bool search(void *key, t_index& index); + virtual t_index index_of(void *item); + virtual t_index add(void *item); + virtual void *key_of(void *item); +private: + virtual int compare(void *key1, void *key2)= 0; +}; + + +/* # + ==========================================================================# + cl_strings # + ==========================================================================# + # +*/ + +class cl_strings: public cl_sorted_list +{ +public: + cl_strings(t_index alimit, t_index adelta); + virtual ~cl_strings(void); + +private: + virtual int compare(void *key1, void *key2); + virtual void free_item(void *item); +}; + + +/* # + ==========================================================================# + cl_ustrings # + ==========================================================================# + # +*/ + +class cl_ustrings: public cl_strings +{ +public: + cl_ustrings(t_index alimit, t_index adelta); + virtual ~cl_ustrings(void); + +private: + virtual int compare(void *key1, void *key2); + virtual bool search(void *key, t_index &index); +}; + + +#endif + +/* End of pobj.h */ diff --git a/sim/ucsim/pobjt.h b/sim/ucsim/pobjt.h new file mode 100644 index 00000000..1bdc7c0e --- /dev/null +++ b/sim/ucsim/pobjt.h @@ -0,0 +1,48 @@ +/* + * Simulator of microcontrollers (pobjt.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef POBJT_HEADER +#define POBJT_HEADER + +#include "ddconfig.h" + +#ifndef MyTypesHeader +#define TRUE 1 +#define FALSE 0 +#define bool int +#endif + +typedef int t_index; +typedef int (*match_func)(void *, void *); +typedef void (*iterator_func)(void *, void *); + +#define max_list_size (0x10000/sizeof(void *)) +#define ccNotFound -1 + +#endif + +/* End of pobjt.h */ diff --git a/sim/ucsim/pstr.h b/sim/ucsim/pstr.h new file mode 100644 index 00000000..caee6e27 --- /dev/null +++ b/sim/ucsim/pstr.h @@ -0,0 +1,44 @@ +/* + * Simulator of microcontrollers (pstr.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef PSTR_HEADER +#define PSTR_HEADER + +#include "ddconfig.h" + +#ifdef STDC_HEADERS +# include +#else +# include "predefs.h" +# ifdef PUtilsNeeded +# include "putils.h" +# endif +#endif + +#endif + +/* End of pstr.h */ diff --git a/sim/ucsim/stypes.h b/sim/ucsim/stypes.h new file mode 100644 index 00000000..86243c5d --- /dev/null +++ b/sim/ucsim/stypes.h @@ -0,0 +1,207 @@ +/* + * Simulator of microcontrollers (stypes.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef STYPES_HEADER +#define STYPES_HEADER + +#include "ddconfig.h" + + +typedef unsigned char uchar; +typedef unsigned int uint; +typedef unsigned long ulong; +typedef unsigned long t_addr; +typedef unsigned long t_mem; + +struct id_element +{ + int id; + char *id_string; +}; + +// table of dissassembled instructions +struct dis_entry +{ + uint code, mask; + char branch; + uchar length; + char *mnemonic; +}; + +// table entry of SFR and BIT names +struct name_entry +{ + int cpu_type; + uint addr; + char *name; +}; + + +struct cpu_entry +{ + char *type_str; + int type; + int technology; +}; + +#define CPU_51 0x0001 +#define CPU_31 0x0002 +#define CPU_52 0x0004 +#define CPU_32 0x0008 +#define CPU_51R 0x0010 +#define CPU_89C51R 0x0020 +#define CPU_251 0x0040 +#define CPU_ALL_51 (CPU_51|CPU_31) +#define CPU_ALL_52 (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251) + +#define CPU_AVR 0x0001 +#define CPU_ALL_AVR (CPU_AVR) + +#define CPU_Z80 0x0001 +#define CPU_ALL_Z80 (CPU_Z80) + +#define CPU_CMOS 0x0001 +#define CPU_HMOS 0x0002 + +/* Classes of memories, this is index on the list */ +enum mem_class +{ + MEM_ROM= 0, + MEM_XRAM, + MEM_IRAM, + MEM_SFR, + MEM_TYPES +}; + +// Flags of consoles +#define CONS_NONE 0 +#define CONS_DEBUG 0x01 // Print debug messages on this console +#define CONS_FROZEN 0x02 // Console is frozen (g command issued) +#define CONS_PROMPT 0x04 // Prompt is out, waiting for input + +// States of simulator +#define SIM_NONE 0 +#define SIM_GO 0x01 // Processor is running +#define SIM_QUIT 0x02 // Program must exit + +/* States of CPU */ +#define stGO 0 /* Normal state */ +#define stIDLE 1 /* Idle mode is active */ +#define stPD 2 /* Power Down mode is active */ + +/* Result of instruction simulation */ +#define resGO 0 /* OK, go on */ +#define resWDTRESET 1 /* Reseted by WDT */ +#define resINTERRUPT 2 /* Interrupt accepted */ +#define resSTOP 100 /* Stop if result greather then this */ +#define resHALT 101 /* Serious error, halt CPU */ +#define resINV_ADDR 102 /* Invalid indirect address */ +#define resSTACK_OV 103 /* Stack overflow */ +#define resBREAKPOINT 104 /* Breakpoint */ +#define resUSER 105 /* Stopped by user */ +#define resINV_INST 106 /* Invalid instruction */ + + +#define BIT_MASK(bitaddr) (1 << (bitaddr & 0x07)) +#define SET_BIT(newbit, reg, bitmask) \ +if (newbit) \ + (mem(MEM_SFR))->set_bit1((reg), (bitmask)); \ +else \ + (mem(MEM_SFR))->set_bit0((reg), (bitmask)); +#define GET_C (get_mem(MEM_SFR, PSW) & bmCY) +#define SET_C(newC) SET_BIT((newC), PSW, bmCY) + +#define IRAM_SIZE 256 /* Size of Internal RAM */ +#define SFR_SIZE 256 /* Size of SFR area */ +#define SFR_START 128 /* Start address of SFR area */ +#define ERAM_SIZE 256 /* Size of ERAM in 51R */ +#define XRAM_SIZE 0x10000 /* Size of External RAM */ +//#define IROM_SIZE 0x1000 /* Size of Internal ROM */ +#define EROM_SIZE 0x10000 /* Size of External ROM */ + + +/* Type of breakpoints */ +enum brk_perm +{ + brkFIX, /* f */ + brkDYNAMIC /* d */ +}; + +enum brk_type +{ + brkFETCH, /* f */ + brkEVENT /* e */ +}; + +enum brk_event +{ + brkNONE, + brkWXRAM, /* wx */ + brkRXRAM, /* rx */ + brkRCODE, /* rc */ + brkWIRAM, /* wi */ + brkRIRAM, /* ri */ + brkWSFR, /* ws */ + brkRSFR /* rs */ +}; + +struct event_rec +{ + t_addr wx; /* write to XRAM at this address, else -1 */ + t_addr rx; /* read from XRAM at this address, else -1 */ + t_addr wi; /* write to IRAM at this address, else -1 */ + t_addr ri; /* read from IRAM at this address, else -1 */ + t_addr ws; /* write to SFR at this address, else -1 */ + t_addr rs; /* read from SFR at this address, else -1 */ + t_addr rc; /* read from ROM at this address, else -1 */ +}; + +/* Interrupt levels */ +//#define IT_NO -1 /* not in interroupt service */ +#define IT_LOW 1 /* low level interrupt service */ +#define IT_HIGH 2 /* service of high priority interrupt */ + +/* cathegories of hw elements (peripherials) */ +enum hw_cath { + HW_TIMER, + HW_UART, + HW_PORT, + HW_PCA, + HW_INTERRUPT, + HW_WDT +}; + +// flags of hw units +#define HWF_NONE 0 +#define HWF_INSIDE 0x0001 +#define HWF_OUTSIDE 0x0002 +#define HWF_MISC 0x0004 + + +#endif + +/* End of stypes.h */ diff --git a/sim/ucsim/utils.cc b/sim/ucsim/utils.cc new file mode 100644 index 00000000..6bbdbc17 --- /dev/null +++ b/sim/ucsim/utils.cc @@ -0,0 +1,73 @@ +/* + * Simulator of microcontrollers (utils.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "i_string.h" + +#include "stypes.h" + + +int +get_sub_opt(char **option, const char * const *tokens, char **valuep) +{ + char *end, *equ; + int i; + + if (!(end= strchr(*option, ','))) + end= *option + strlen(*option); + else + *end++= '\0'; + if ((equ= strchr(*option, '='))) + { + *valuep= equ+1; + *equ= '\0'; + } + else + *valuep= 0; + i= 0; + while (tokens[i] && + strcmp(*option, tokens[i])) + i++; + if (!tokens[i]) + *valuep= *option; + *option= end; + return tokens[i]?i:-1; +} + + +char * +get_id_string(struct id_element *ids, int id) +{ + int i= 0; + + while (ids[i].id_string && + id != ids[i].id) + i++; + return(ids[i].id_string); +} + + +/* End of utils.cc */ diff --git a/sim/ucsim/utils.h b/sim/ucsim/utils.h new file mode 100644 index 00000000..271d1b41 --- /dev/null +++ b/sim/ucsim/utils.h @@ -0,0 +1,40 @@ +/* + * Simulator of microcontrollers (utils.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef UTILS_HEADER +#define UTILS_HEADER + + +extern int get_sub_opt(char **option, + const char * const *tokens, + char **valuep); +extern char *get_id_string(struct id_element *ids, int id); + + +#endif + +/* End of utils.h */